mirror of https://github.com/RT-Thread/rt-thread
bsp: Separate nuvoton drivers (#10435)
* bsp: Separate nuvoton drivers * bsp: update nuvoton series project.uvprojx
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@ -9,7 +9,7 @@ Current supported BSP shown in below table:
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| NK-980IOT | ARM926EJS | [nk-980iot](nk-980iot) |
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| NuMaker-M2354 | CORTEX-M23 | [numaker-m2354](numaker-m2354) |
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| NK-RTU980 | ARM926EJS | [nk-rtu980](nk-rtu980) |
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| NK-N9H30 | CORTEX-M4 | [nk-n9h30](nk-n9h30) |
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| NK-N9H30 | ARM926EJS | [nk-n9h30](nk-n9h30) |
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| NuMaker-M032KI | CORTEX-M0 | [numaker-m032ki](numaker-m032ki) |
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| NuMaker-M467HJ | CORTEX-M4 | [numaker-m467hj](numaker-m467hj) |
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| NuMaker-IoT-M467 | CORTEX-M4 | [numaker-iot-m467](numaker-iot-m467) |
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@ -1,136 +0,0 @@
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/* ----------------------------------------------------------------------
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* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
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*
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* $Date: 19. October 2015
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* $Revision: V.1.4.5 a
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*
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* Project: CMSIS DSP Library
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* Title: arm_common_tables.h
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*
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* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
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*
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* Target Processor: Cortex-M4/Cortex-M3
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* - Neither the name of ARM LIMITED nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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* -------------------------------------------------------------------- */
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#ifndef _ARM_COMMON_TABLES_H
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#define _ARM_COMMON_TABLES_H
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#include "arm_math.h"
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extern const uint16_t armBitRevTable[1024];
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extern const q15_t armRecipTableQ15[64];
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extern const q31_t armRecipTableQ31[64];
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/* extern const q31_t realCoefAQ31[1024]; */
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/* extern const q31_t realCoefBQ31[1024]; */
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extern const float32_t twiddleCoef_16[32];
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extern const float32_t twiddleCoef_32[64];
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extern const float32_t twiddleCoef_64[128];
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extern const float32_t twiddleCoef_128[256];
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extern const float32_t twiddleCoef_256[512];
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extern const float32_t twiddleCoef_512[1024];
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extern const float32_t twiddleCoef_1024[2048];
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extern const float32_t twiddleCoef_2048[4096];
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extern const float32_t twiddleCoef_4096[8192];
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#define twiddleCoef twiddleCoef_4096
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extern const q31_t twiddleCoef_16_q31[24];
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extern const q31_t twiddleCoef_32_q31[48];
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extern const q31_t twiddleCoef_64_q31[96];
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extern const q31_t twiddleCoef_128_q31[192];
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extern const q31_t twiddleCoef_256_q31[384];
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extern const q31_t twiddleCoef_512_q31[768];
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extern const q31_t twiddleCoef_1024_q31[1536];
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extern const q31_t twiddleCoef_2048_q31[3072];
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extern const q31_t twiddleCoef_4096_q31[6144];
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extern const q15_t twiddleCoef_16_q15[24];
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extern const q15_t twiddleCoef_32_q15[48];
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extern const q15_t twiddleCoef_64_q15[96];
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extern const q15_t twiddleCoef_128_q15[192];
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extern const q15_t twiddleCoef_256_q15[384];
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extern const q15_t twiddleCoef_512_q15[768];
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extern const q15_t twiddleCoef_1024_q15[1536];
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extern const q15_t twiddleCoef_2048_q15[3072];
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extern const q15_t twiddleCoef_4096_q15[6144];
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extern const float32_t twiddleCoef_rfft_32[32];
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extern const float32_t twiddleCoef_rfft_64[64];
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extern const float32_t twiddleCoef_rfft_128[128];
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extern const float32_t twiddleCoef_rfft_256[256];
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extern const float32_t twiddleCoef_rfft_512[512];
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extern const float32_t twiddleCoef_rfft_1024[1024];
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extern const float32_t twiddleCoef_rfft_2048[2048];
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extern const float32_t twiddleCoef_rfft_4096[4096];
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/* floating-point bit reversal tables */
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#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
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#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
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#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
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#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
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#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
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#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
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#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
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#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
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#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
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extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
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/* fixed-point bit reversal tables */
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#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
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#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
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#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
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#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
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#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
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#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
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#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
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#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
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#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
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extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
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/* Tables for Fast Math Sine and Cosine */
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extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
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extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
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extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
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#endif /* ARM_COMMON_TABLES_H */
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@ -1,79 +0,0 @@
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/* ----------------------------------------------------------------------
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* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
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*
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* $Date: 19. March 2015
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* $Revision: V.1.4.5
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*
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* Project: CMSIS DSP Library
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* Title: arm_const_structs.h
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*
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* Description: This file has constant structs that are initialized for
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* user convenience. For example, some can be given as
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* arguments to the arm_cfft_f32() function.
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*
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* Target Processor: Cortex-M4/Cortex-M3
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
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||||
* distribution.
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* - Neither the name of ARM LIMITED nor the names of its contributors
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* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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* -------------------------------------------------------------------- */
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#ifndef _ARM_CONST_STRUCTS_H
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#define _ARM_CONST_STRUCTS_H
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#include "arm_math.h"
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#include "arm_common_tables.h"
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
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#endif
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File diff suppressed because it is too large
Load Diff
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@ -1,734 +0,0 @@
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/**************************************************************************//**
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* @file cmsis_armcc.h
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* @brief CMSIS Cortex-M Core Function/Instruction Header File
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* @version V4.30
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* @date 20. October 2015
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******************************************************************************/
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/* Copyright (c) 2009 - 2015 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#ifndef __CMSIS_ARMCC_H
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#define __CMSIS_ARMCC_H
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#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
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#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
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#endif
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/* ########################### Core Function Access ########################### */
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/** \ingroup CMSIS_Core_FunctionInterface
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\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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@{
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*/
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/* intrinsic void __enable_irq(); */
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/* intrinsic void __disable_irq(); */
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/**
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\brief Get Control Register
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\details Returns the content of the Control Register.
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\return Control Register value
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*/
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__STATIC_INLINE uint32_t __get_CONTROL(void)
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{
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register uint32_t __regControl __ASM("control");
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return(__regControl);
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}
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/**
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\brief Set Control Register
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\details Writes the given value to the Control Register.
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\param [in] control Control Register value to set
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*/
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__STATIC_INLINE void __set_CONTROL(uint32_t control)
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{
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register uint32_t __regControl __ASM("control");
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__regControl = control;
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}
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/**
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\brief Get IPSR Register
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\details Returns the content of the IPSR Register.
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||||
\return IPSR Register value
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*/
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__STATIC_INLINE uint32_t __get_IPSR(void)
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{
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register uint32_t __regIPSR __ASM("ipsr");
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return(__regIPSR);
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}
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/**
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\brief Get APSR Register
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||||
\details Returns the content of the APSR Register.
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||||
\return APSR Register value
|
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*/
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__STATIC_INLINE uint32_t __get_APSR(void)
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{
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register uint32_t __regAPSR __ASM("apsr");
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return(__regAPSR);
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}
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/**
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\brief Get xPSR Register
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\details Returns the content of the xPSR Register.
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||||
\return xPSR Register value
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*/
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__STATIC_INLINE uint32_t __get_xPSR(void)
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{
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register uint32_t __regXPSR __ASM("xpsr");
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return(__regXPSR);
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}
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/**
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\brief Get Process Stack Pointer
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||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
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||||
__STATIC_INLINE uint32_t __get_PSP(void)
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||||
{
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register uint32_t __regProcessStackPointer __ASM("psp");
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return(__regProcessStackPointer);
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||||
}
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||||
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|
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/**
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\brief Set Process Stack Pointer
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\details Assigns the given value to the Process Stack Pointer (PSP).
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||||
\param [in] topOfProcStack Process Stack Pointer value to set
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*/
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__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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||||
{
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||||
register uint32_t __regProcessStackPointer __ASM("psp");
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__regProcessStackPointer = topOfProcStack;
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}
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/**
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||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
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register uint32_t __regMainStackPointer __ASM("msp");
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return(__regMainStackPointer);
|
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}
|
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|
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||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
|
||||
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in integer value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in two unsigned short values.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Reverse byte order in signed short value
|
||||
\details Reverses the byte order in a signed short value with sign extension to integer.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return(result);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x04) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,798 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
#define __CORE_CM0_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M0
|
||||
@{
|
||||
*/
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __packed
|
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
||||
#include "core_cmFunc.h" /* Core Function Access */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M0 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Cortex-M0 Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt
|
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt
|
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of an external interrupt.
|
||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of an external interrupt.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of an interrupt.
|
||||
\note The priority cannot be set for every core interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of an interrupt.
|
||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
||||
or negative to specify an internal (core) interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
|
|
@ -1,914 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm0plus.h
|
||||
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0PLUS_H_GENERIC
|
||||
#define __CORE_CM0PLUS_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex-M0+
|
||||
@{
|
||||
*/
|
||||
|
||||
/* CMSIS CM0+ definitions */
|
||||
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __packed
|
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
||||
#include "core_cmFunc.h" /* Core Function Access */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0PLUS_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0PLUS_H_DEPENDANT
|
||||
#define __CORE_CM0PLUS_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0PLUS_REV
|
||||
#define __CM0PLUS_REV 0x0000U
|
||||
#warning "__CM0PLUS_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __VTOR_PRESENT
|
||||
#define __VTOR_PRESENT 0U
|
||||
#warning "__VTOR_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex-M0+ */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
- Core MPU Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
|
||||
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
#if (__VTOR_PRESENT == 1U)
|
||||
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
||||
#else
|
||||
uint32_t RESERVED0;
|
||||
#endif
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
#if (__VTOR_PRESENT == 1U)
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
|
||||
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||
#endif
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||
\brief Type definitions for the Memory Protection Unit (MPU)
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Memory Protection Unit (MPU).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
||||
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||
} MPU_Type;
|
||||
|
||||
/* MPU Type Register Definitions */
|
||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||
|
||||
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
|
||||
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
||||
|
||||
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
|
||||
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
|
||||
|
||||
/* MPU Control Register Definitions */
|
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
|
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
||||
|
||||
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
|
||||
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
||||
|
||||
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
|
||||
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
|
||||
|
||||
/* MPU Region Number Register Definitions */
|
||||
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
|
||||
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
|
||||
|
||||
/* MPU Region Base Address Register Definitions */
|
||||
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
|
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
||||
|
||||
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
|
||||
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
||||
|
||||
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
|
||||
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
|
||||
|
||||
/* MPU Region Attribute and Size Register Definitions */
|
||||
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
|
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
||||
|
||||
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
|
||||
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
||||
|
||||
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
|
||||
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
||||
|
||||
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
|
||||
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
||||
|
||||
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
|
||||
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
||||
|
||||
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
|
||||
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
||||
|
||||
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
|
||||
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
||||
|
||||
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
|
||||
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
||||
|
||||
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
|
||||
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
||||
|
||||
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
|
||||
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
||||
|
||||
/*@} end of group CMSIS_MPU */
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0+ header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Cortex-M0+ Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt
|
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt
|
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of an external interrupt.
|
||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of an external interrupt.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of an interrupt.
|
||||
\note The priority cannot be set for every core interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of an interrupt.
|
||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
||||
or negative to specify an internal (core) interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,87 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
|
|
@ -1,87 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
|
|
@ -1,96 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmSimd.h
|
||||
* @brief CMSIS Cortex-M SIMD Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMSIMD_H
|
||||
#define __CORE_CMSIMD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CMSIMD_H */
|
||||
|
|
@ -1,926 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_sc000.h
|
||||
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_SC000_H_GENERIC
|
||||
#define __CORE_SC000_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup SC000
|
||||
@{
|
||||
*/
|
||||
|
||||
/* CMSIS SC000 definitions */
|
||||
#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_SC (000U) /*!< Cortex secure core */
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __packed
|
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
||||
#include "core_cmFunc.h" /* Core Function Access */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_SC000_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_SC000_H_DEPENDANT
|
||||
#define __CORE_SC000_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __SC000_REV
|
||||
#define __SC000_REV 0x0000U
|
||||
#warning "__SC000_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group SC000 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
- Core MPU Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED0[1U];
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
uint32_t RESERVED1[154U];
|
||||
__IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
|
||||
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED0[2U];
|
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||
} SCnSCB_Type;
|
||||
|
||||
/* Auxiliary Control Register Definitions */
|
||||
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
|
||||
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||
\brief Type definitions for the Memory Protection Unit (MPU)
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Memory Protection Unit (MPU).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
||||
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||
} MPU_Type;
|
||||
|
||||
/* MPU Type Register Definitions */
|
||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||
|
||||
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
|
||||
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
||||
|
||||
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
|
||||
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
|
||||
|
||||
/* MPU Control Register Definitions */
|
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
|
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
||||
|
||||
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
|
||||
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
||||
|
||||
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
|
||||
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
|
||||
|
||||
/* MPU Region Number Register Definitions */
|
||||
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
|
||||
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
|
||||
|
||||
/* MPU Region Base Address Register Definitions */
|
||||
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
|
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
||||
|
||||
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
|
||||
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
||||
|
||||
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
|
||||
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
|
||||
|
||||
/* MPU Region Attribute and Size Register Definitions */
|
||||
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
|
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
||||
|
||||
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
|
||||
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
||||
|
||||
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
|
||||
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
||||
|
||||
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
|
||||
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
||||
|
||||
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
|
||||
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
||||
|
||||
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
|
||||
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
||||
|
||||
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
|
||||
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
||||
|
||||
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
|
||||
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
||||
|
||||
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
|
||||
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
||||
|
||||
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
|
||||
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
||||
|
||||
/*@} end of group CMSIS_MPU */
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the SC000 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of SC000 Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt
|
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt
|
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of an external interrupt.
|
||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of an external interrupt.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of an interrupt.
|
||||
\note The priority cannot be set for every core interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of an interrupt.
|
||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
||||
or negative to specify an internal (core) interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_SC000_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,16 +0,0 @@
|
|||
import rtconfig
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
src = Split("""
|
||||
""")
|
||||
|
||||
path = [cwd + '/Include',]
|
||||
|
||||
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -1,590 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file m031series.h
|
||||
* @version V3.0
|
||||
* $Revision: 12 $
|
||||
* $Date: 18/08/16 4:06p $
|
||||
* @brief M031 Series Peripheral Access Layer Header File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
|
||||
/**
|
||||
\mainpage NuMicro M031 Driver Reference Guide
|
||||
*
|
||||
* <b>Introduction</b>
|
||||
*
|
||||
* This user manual describes the usage of M031 Series MCU device driver
|
||||
*
|
||||
* <b>Disclaimer</b>
|
||||
*
|
||||
* The Software is furnished "AS IS", without warranty as to performance or results, and
|
||||
* the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
|
||||
* warranties, express, implied or otherwise, with regard to the Software, its use, or
|
||||
* operation, including without limitation any and all warranties of merchantability, fitness
|
||||
* for a particular purpose, and non-infringement of intellectual property rights.
|
||||
*
|
||||
* <b>Important Notice</b>
|
||||
*
|
||||
* Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
|
||||
* any malfunction or failure of which may cause loss of human life, bodily injury or severe
|
||||
* property damage. Such applications are deemed, "Insecure Usage".
|
||||
*
|
||||
* Insecure usage includes, but is not limited to: equipment for surgical implementation,
|
||||
* atomic energy control instruments, airplane or spaceship instruments, the control or
|
||||
* operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
|
||||
* instruments, all types of safety devices, and other applications intended to support or
|
||||
* sustain life.
|
||||
*
|
||||
* All Insecure Usage shall be made at customer's risk, and in the event that third parties
|
||||
* lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
|
||||
* the damages and liabilities thus incurred by Nuvoton.
|
||||
*
|
||||
* Please note that all data and specifications are subject to change without notice. All the
|
||||
* trademarks of products and companies mentioned in this datasheet belong to their respective
|
||||
* owners.
|
||||
*
|
||||
* <b>Copyright Notice</b>
|
||||
*
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __M031SERIES_H__
|
||||
#define __M031SERIES_H__
|
||||
|
||||
/******************************************************************************/
|
||||
/* Processor and Core Peripherals */
|
||||
/******************************************************************************/
|
||||
/** @addtogroup CMSIS_Device CMSIS Definitions
|
||||
Configuration of the Cortex-M0 Processor and Core Peripherals
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* ==========================================================================
|
||||
* ---------- Interrupt Number Definition -----------------------------------
|
||||
* ==========================================================================
|
||||
*/
|
||||
|
||||
/**
|
||||
* @details Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.
|
||||
*/
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
|
||||
|
||||
/****** ARMIKMCU Swift specific Interrupt Numbers ************************************************/
|
||||
BOD_IRQn = 0, /*!< Brown-Out Low Voltage Detected Interrupt */
|
||||
WDT_IRQn = 1, /*!< Watch Dog Timer Interrupt */
|
||||
EINT024_IRQn = 2, /*!< EINT0, EINT2 and EINT4 Interrupt */
|
||||
EINT135_IRQn = 3, /*!< EINT1, EINT3 and EINT5 Interrupt */
|
||||
GPIO_PAPB_IRQn = 4, /*!< GPIO_PAPBPGPH Interrupt */
|
||||
GPIO_PAPBPGPH_IRQn = 4, /*!< GPIO_PAPBPGPH Interrupt */
|
||||
GPIO_PCPDPEPF_IRQn = 5, /*!< GPIO_PCPDPEPF Interrupt */
|
||||
PWM0_IRQn = 6, /*!< PWM0 Interrupt */
|
||||
PWM1_IRQn = 7, /*!< PWM1 Interrupt */
|
||||
TMR0_IRQn = 8, /*!< TIMER0 Interrupt */
|
||||
TMR1_IRQn = 9, /*!< TIMER1 Interrupt */
|
||||
TMR2_IRQn = 10, /*!< TIMER2 Interrupt */
|
||||
TMR3_IRQn = 11, /*!< TIMER3 Interrupt */
|
||||
UART02_IRQn = 12, /*!< UART0 and UART2 Interrupt */
|
||||
UART1_IRQn = 13, /*!< UART1 and UART3 Interrupt */
|
||||
UART13_IRQn = 13, /*!< UART1 and UART3 Interrupt */
|
||||
SPI0_IRQn = 14, /*!< SPI0 Interrupt */
|
||||
QSPI0_IRQn = 15, /*!< QSPI0 Interrupt */
|
||||
ISP_IRQn = 16, /*!< ISP Interrupt */
|
||||
UART57_IRQn = 17, /*!< UART5 and UART7 Interrupt */
|
||||
I2C0_IRQn = 18, /*!< I2C0 Interrupt */
|
||||
I2C1_IRQn = 19, /*!< I2C1 Interrupt */
|
||||
BPWM0_IRQn = 20, /*!< BPWM0 Interrupt */
|
||||
BPWM1_IRQn = 21, /*!< BPWM1 Interrupt */
|
||||
USCI_IRQn = 22, /*!< USCI0 and USCI1 interrupt */
|
||||
USCI01_IRQn = 22, /*!< USCI0 and USCI1 interrupt */
|
||||
USBD_IRQn = 23, /*!< USB Device Interrupt */
|
||||
ACMP01_IRQn = 25, /*!< ACMP0/1 Interrupt */
|
||||
PDMA_IRQn = 26, /*!< PDMA Interrupt */
|
||||
UART46_IRQn = 27, /*!< UART4 and UART6 Interrupt */
|
||||
PWRWU_IRQn = 28, /*!< Power Down Wake Up Interrupt */
|
||||
ADC_IRQn = 29, /*!< ADC Interrupt */
|
||||
CKFAIL_IRQn = 30, /*!< Clock fail detect Interrupt */
|
||||
RTC_IRQn = 31, /*!< RTC Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/*
|
||||
* ==========================================================================
|
||||
* ----------- Processor and Core Peripheral Section ------------------------
|
||||
* ==========================================================================
|
||||
*/
|
||||
|
||||
/* Configuration of the Cortex-M0 Processor and Core Peripherals */
|
||||
#define __MPU_PRESENT 0 /*!< armikcmu does not provide a MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< armikcmu Supports 2 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Device */
|
||||
|
||||
#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
|
||||
#include "system_M031Series.h" /*!< M031 System */
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system clock
|
||||
*
|
||||
* @param None
|
||||
* @return None
|
||||
*
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the PLL and update the SystemFrequency variable
|
||||
*/
|
||||
extern void SystemInit(void);
|
||||
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Device Specific Peripheral registers structures */
|
||||
/******************************************************************************/
|
||||
|
||||
#include "acmp_reg.h"
|
||||
#include "adc_reg.h"
|
||||
#include "clk_reg.h"
|
||||
#include "crc_reg.h"
|
||||
#include "ebi_reg.h"
|
||||
#include "fmc_reg.h"
|
||||
#include "gpio_reg.h"
|
||||
#include "hdiv_reg.h"
|
||||
#include "i2c_reg.h"
|
||||
#include "pdma_reg.h"
|
||||
#include "pwm_reg.h"
|
||||
#include "bpwm_reg.h"
|
||||
#include "qspi_reg.h"
|
||||
#include "spi_reg.h"
|
||||
#include "sys_reg.h"
|
||||
#include "rtc_reg.h"
|
||||
#include "timer_reg.h"
|
||||
#include "uart_reg.h"
|
||||
#include "ui2c_reg.h"
|
||||
#include "usbd_reg.h"
|
||||
#include "uspi_reg.h"
|
||||
#include "uuart_reg.h"
|
||||
#include "wdt_reg.h"
|
||||
#include "wwdt_reg.h"
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral memory map */
|
||||
/******************************************************************************/
|
||||
/** @addtogroup PERIPHERAL_BASE Peripheral Memory Base
|
||||
Memory Mapped Structure for Series Peripheral
|
||||
@{
|
||||
*/
|
||||
/* Peripheral and SRAM base address */
|
||||
#define FLASH_BASE (( uint32_t)0x00000000)
|
||||
#define SRAM_BASE (( uint32_t)0x20000000)
|
||||
#define AHB_BASE (( uint32_t)0x40000000)
|
||||
#define APB1_BASE (( uint32_t)0x40000000)
|
||||
#define APB2_BASE (( uint32_t)0x40000000)
|
||||
|
||||
/* Peripheral memory map */
|
||||
|
||||
#define SYS_BASE (AHB_BASE + 0x00000) /*!< System Global Controller Base Address */
|
||||
#define CLK_BASE (AHB_BASE + 0x00200) /*!< System Clock Controller Base Address */
|
||||
#define INT_BASE (AHB_BASE + 0x00300) /*!< Interrupt Source Controller Base Address */
|
||||
#define NMI_BASE (AHB_BASE + 0x00300) /*!< Interrupt Source Controller Base Address */
|
||||
|
||||
#define GPIO_BASE (AHB_BASE + 0x4000) /*!< GPIO Base Address */
|
||||
#define PA_BASE (GPIO_BASE ) /*!< GPIO PA Base Address */
|
||||
#define PB_BASE (GPIO_BASE + 0x0040) /*!< GPIO PB Base Address */
|
||||
#define PC_BASE (GPIO_BASE + 0x0080) /*!< GPIO PC Base Address */
|
||||
#define PD_BASE (GPIO_BASE + 0x00C0) /*!< GPIO PD Base Address */
|
||||
#define PE_BASE (GPIO_BASE + 0x0100) /*!< GPIO PE Base Address */
|
||||
#define PF_BASE (GPIO_BASE + 0x0140) /*!< GPIO PF Base Address */
|
||||
#define PG_BASE (GPIO_BASE + 0x0180) /*!< GPIO PG Base Address */
|
||||
#define PH_BASE (GPIO_BASE + 0x01C0) /*!< GPIO PH Base Address */
|
||||
#define GPIO_DBCTL_BASE (GPIO_BASE + 0x0440) /*!< GPIO De-bounce Cycle Control Base Address */
|
||||
#define GPIO_PIN_DATA_BASE (GPIO_BASE + 0x0800) /*!< GPIO Pin Data Input/Output Control Base Address */
|
||||
|
||||
#define PDMA_BASE (AHB_BASE + 0x08000) /*!< PDMA Base Address */
|
||||
#define FMC_BASE (AHB_BASE + 0x0C000) /*!< Flash Memory Controller Base Address */
|
||||
#define EBI_BASE (AHB_BASE + 0x10000) /*!< EBI Base Address */
|
||||
#define HDIV_BASE (AHB_BASE + 0x14000) /*!< HDIV Base Address */
|
||||
#define CRC_BASE (AHB_BASE + 0x31000) /*!< CRC Base Address */
|
||||
|
||||
#define WDT_BASE (APB1_BASE + 0x40000) /*!< Watch Dog Timer Base Address */
|
||||
#define WWDT_BASE (APB1_BASE + 0x40100) /*!< Window Watch Dog Timer Base Address */
|
||||
#define RTC_BASE (APB1_BASE + 0x41000) /*!< RTC Base Address */
|
||||
#define ADC_BASE (APB1_BASE + 0x43000) /*!< ADC Base Address */
|
||||
#define ACMP01_BASE (APB1_BASE + 0x45000) /*!< ACMP01 Base Address */
|
||||
|
||||
#define TIMER0_BASE (APB1_BASE + 0x50000) /*!< Timer0 Base Address */
|
||||
#define TIMER1_BASE (APB1_BASE + 0x50020) /*!< Timer1 Base Address */
|
||||
#define TIMER2_BASE (APB2_BASE + 0x51000) /*!< Timer2 Base Address */
|
||||
#define TIMER3_BASE (APB2_BASE + 0x51020) /*!< Timer3 Base Address */
|
||||
|
||||
#define PWM0_BASE (APB1_BASE + 0x58000) /*!< PWM0 Base Address */
|
||||
#define PWM1_BASE (APB2_BASE + 0x59000) /*!< PWM1 Base Address */
|
||||
|
||||
#define BPWM0_BASE (APB1_BASE + 0x5A000) /*!< BPWM0 Base Address */
|
||||
#define BPWM1_BASE (APB2_BASE + 0x5B000) /*!< BPWM1 Base Address */
|
||||
|
||||
#define QSPI0_BASE (APB1_BASE + 0x60000) /*!< QSPI0 Base Address */
|
||||
#define SPI0_BASE (APB1_BASE + 0x61000) /*!< SPI0 Base Address */
|
||||
|
||||
#define UART0_BASE (APB1_BASE + 0x70000) /*!< UART0 Base Address */
|
||||
#define UART1_BASE (APB2_BASE + 0x71000) /*!< UART1 Base Address */
|
||||
#define UART2_BASE (APB2_BASE + 0x72000) /*!< UART2 Base Address */
|
||||
#define UART3_BASE (APB2_BASE + 0x73000) /*!< UART3 Base Address */
|
||||
#define UART4_BASE (APB2_BASE + 0x74000) /*!< UART4 Base Address */
|
||||
#define UART5_BASE (APB2_BASE + 0x75000) /*!< UART5 Base Address */
|
||||
#define UART6_BASE (APB2_BASE + 0x76000) /*!< UART6 Base Address */
|
||||
#define UART7_BASE (APB2_BASE + 0x77000) /*!< UART7 Base Address */
|
||||
|
||||
#define I2C0_BASE (APB1_BASE + 0x80000) /*!< I2C0 Base Address */
|
||||
#define I2C1_BASE (APB2_BASE + 0x81000) /*!< I2C1 Base Address */
|
||||
|
||||
#define USBD_BASE (AHB_BASE + 0xC0000) /*!< USBD1.1 Base Address */
|
||||
#define USCI0_BASE (APB1_BASE + 0xD0000) /*!< USCI0 Base Address */
|
||||
#define USCI1_BASE (APB2_BASE + 0xD1000) /*!< USCI1 Base Address */
|
||||
|
||||
|
||||
/**@}*/ /* PERIPHERAL */
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral declaration */
|
||||
/******************************************************************************/
|
||||
|
||||
/** @addtogroup PMODULE Peripheral Pointer
|
||||
The Declaration of Peripheral Pointer
|
||||
@{
|
||||
*/
|
||||
#define PA ((GPIO_T *) PA_BASE) /*!< GPIO PORTA Configuration Struct */
|
||||
#define PB ((GPIO_T *) PB_BASE) /*!< GPIO PORTB Configuration Struct */
|
||||
#define PC ((GPIO_T *) PC_BASE) /*!< GPIO PORTC Configuration Struct */
|
||||
#define PD ((GPIO_T *) PD_BASE) /*!< GPIO PORTD Configuration Struct */
|
||||
#define PE ((GPIO_T *) PE_BASE) /*!< GPIO PORTE Configuration Struct */
|
||||
#define PF ((GPIO_T *) PF_BASE) /*!< GPIO PORTF Configuration Struct */
|
||||
#define PG ((GPIO_T *) PG_BASE) /*!< GPIO PORTG Configuration Struct */
|
||||
#define PH ((GPIO_T *) PH_BASE) /*!< GPIO PORTH Configuration Struct */
|
||||
#define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE) /*!< Interrupt De-bounce Cycle Control Configuration Struct */
|
||||
|
||||
#define UART0 ((UART_T *) UART0_BASE) /*!< UART0 Configuration Struct */
|
||||
#define UART1 ((UART_T *) UART1_BASE) /*!< UART1 Configuration Struct */
|
||||
#define UART2 ((UART_T *) UART2_BASE) /*!< UART2 Configuration Struct */
|
||||
#define UART3 ((UART_T *) UART3_BASE) /*!< UART3 Configuration Struct */
|
||||
#define UART4 ((UART_T *) UART4_BASE) /*!< UART4 Configuration Struct */
|
||||
#define UART5 ((UART_T *) UART5_BASE) /*!< UART5 Configuration Struct */
|
||||
#define UART6 ((UART_T *) UART6_BASE) /*!< UART6 Configuration Struct */
|
||||
#define UART7 ((UART_T *) UART7_BASE) /*!< UART7 Configuration Struct */
|
||||
|
||||
#define TIMER0 ((TIMER_T *) TIMER0_BASE) /*!< TIMER0 Configuration Struct */
|
||||
#define TIMER1 ((TIMER_T *) TIMER1_BASE) /*!< TIMER1 Configuration Struct */
|
||||
#define TIMER2 ((TIMER_T *) TIMER2_BASE) /*!< TIMER2 Configuration Struct */
|
||||
#define TIMER3 ((TIMER_T *) TIMER3_BASE) /*!< TIMER3 Configuration Struct */
|
||||
|
||||
#define WDT ((WDT_T *) WDT_BASE) /*!< Watch Dog Timer Configuration Struct */
|
||||
|
||||
#define WWDT ((WWDT_T *) WWDT_BASE) /*!< Window Watch Dog Timer Configuration Struct */
|
||||
|
||||
#define SPI0 ((SPI_T *) SPI0_BASE) /*!< SPI0 Configuration Struct */
|
||||
#define QSPI0 ((QSPI_T *) QSPI0_BASE) /*!< QSPI0 Configuration Struct */
|
||||
|
||||
#define I2C0 ((I2C_T *) I2C0_BASE) /*!< I2C0 Configuration Struct */
|
||||
#define I2C1 ((I2C_T *) I2C1_BASE) /*!< I2C1 Configuration Struct */
|
||||
|
||||
#define ADC ((ADC_T *) ADC_BASE) /*!< ADC Configuration Struct */
|
||||
|
||||
#define ACMP01 ((ACMP_T *) ACMP01_BASE) /*!< ACMP01 Configuration Struct */
|
||||
|
||||
#define CLK ((CLK_T *) CLK_BASE) /*!< System Clock Controller Configuration Struct */
|
||||
|
||||
#define SYS ((SYS_T *) SYS_BASE) /*!< System Global Controller Configuration Struct */
|
||||
|
||||
#define SYSINT ((NMI_T *) INT_BASE) /*!< Interrupt Source Controller Configuration Struct */
|
||||
#define NMI ((NMI_T *) NMI_BASE) /*!< Interrupt Source Controller Configuration Struct */
|
||||
|
||||
#define FMC ((FMC_T *) FMC_BASE) /*!< Flash Memory Controller */
|
||||
|
||||
#define PWM0 ((PWM_T *) PWM0_BASE) /*!< PWM0 Configuration Struct */
|
||||
#define PWM1 ((PWM_T *) PWM1_BASE) /*!< PWM1 Configuration Struct */
|
||||
#define BPWM0 ((BPWM_T *) BPWM0_BASE) /*!< BPWM0 Configuration Struct */
|
||||
#define BPWM1 ((BPWM_T *) BPWM1_BASE) /*!< BPWM1 Configuration Struct */
|
||||
|
||||
#define EBI ((EBI_T *) EBI_BASE) /*!< EBI Configuration Struct */
|
||||
|
||||
#define HDIV ((HDIV_T *) HDIV_BASE) /*!< HDIV Configuration Struct */
|
||||
|
||||
#define CRC ((CRC_T *) CRC_BASE) /*!< CRC Configuration Struct */
|
||||
|
||||
#define USBD ((USBD_T *) USBD_BASE) /*!< CRC Configuration Struct */
|
||||
|
||||
#define PDMA ((PDMA_T *) PDMA_BASE) /*!< PDMA Configuration Struct */
|
||||
|
||||
#define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Configuration Struct */
|
||||
#define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Configuration Struct */
|
||||
|
||||
#define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Configuration Struct */
|
||||
#define USPI1 ((USPI_T *) USCI1_BASE) /*!< USPI1 Configuration Struct */
|
||||
|
||||
#define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Configuration Struct */
|
||||
#define UUART1 ((UUART_T *) USCI1_BASE) /*!< UUART1 Configuration Struct */
|
||||
|
||||
#define RTC ((RTC_T *) RTC_BASE) /*!< RTC Configuration Struct */
|
||||
|
||||
/**@}*/ /* end of group PMODULE */
|
||||
|
||||
|
||||
//=============================================================================
|
||||
|
||||
/** @addtogroup IO_ROUTINE I/O Routines
|
||||
The Declaration of I/O Routines
|
||||
@{
|
||||
*/
|
||||
|
||||
typedef volatile unsigned char vu8;
|
||||
typedef volatile unsigned long vu32;
|
||||
typedef volatile unsigned short vu16;
|
||||
|
||||
/**
|
||||
* @brief Get a 8-bit unsigned value from specified address
|
||||
* @param[in] addr Address to get 8-bit data from
|
||||
* @return 8-bit unsigned value stored in specified address
|
||||
*/
|
||||
#define M8(addr) (*((vu8 *) (addr)))
|
||||
|
||||
/**
|
||||
* @brief Get a 16-bit unsigned value from specified address
|
||||
* @param[in] addr Address to get 16-bit data from
|
||||
* @return 16-bit unsigned value stored in specified address
|
||||
* @note The input address must be 16-bit aligned
|
||||
*/
|
||||
#define M16(addr) (*((vu16 *) (addr)))
|
||||
|
||||
/**
|
||||
* @brief Get a 32-bit unsigned value from specified address
|
||||
* @param[in] addr Address to get 32-bit data from
|
||||
* @return 32-bit unsigned value stored in specified address
|
||||
* @note The input address must be 32-bit aligned
|
||||
*/
|
||||
#define M32(addr) (*((vu32 *) (addr)))
|
||||
|
||||
/**
|
||||
* @brief Set a 32-bit unsigned value to specified I/O port
|
||||
* @param[in] port Port address to set 32-bit data
|
||||
* @param[in] value Value to write to I/O port
|
||||
* @return None
|
||||
* @note The output port must be 32-bit aligned
|
||||
*/
|
||||
#define outpw(port,value) (*((volatile unsigned int *)(port))=(value))
|
||||
|
||||
/**
|
||||
* @brief Get a 32-bit unsigned value from specified I/O port
|
||||
* @param[in] port Port address to get 32-bit data from
|
||||
* @return 32-bit unsigned value stored in specified I/O port
|
||||
* @note The input port must be 32-bit aligned
|
||||
*/
|
||||
#define inpw(port) ((*((volatile unsigned int *)(port))))
|
||||
|
||||
/**
|
||||
* @brief Set a 16-bit unsigned value to specified I/O port
|
||||
* @param[in] port Port address to set 16-bit data
|
||||
* @param[in] value Value to write to I/O port
|
||||
* @return None
|
||||
* @note The output port must be 16-bit aligned
|
||||
*/
|
||||
#define outps(port,value) (*((volatile unsigned short *)(port))=(value))
|
||||
|
||||
/**
|
||||
* @brief Get a 16-bit unsigned value from specified I/O port
|
||||
* @param[in] port Port address to get 16-bit data from
|
||||
* @return 16-bit unsigned value stored in specified I/O port
|
||||
* @note The input port must be 16-bit aligned
|
||||
*/
|
||||
#define inps(port) ((*((volatile unsigned short *)(port))))
|
||||
|
||||
/**
|
||||
* @brief Set a 8-bit unsigned value to specified I/O port
|
||||
* @param[in] port Port address to set 8-bit data
|
||||
* @param[in] value Value to write to I/O port
|
||||
* @return None
|
||||
*/
|
||||
#define outpb(port,value) (*((volatile unsigned char *)(port))=(value))
|
||||
|
||||
/**
|
||||
* @brief Get a 8-bit unsigned value from specified I/O port
|
||||
* @param[in] port Port address to get 8-bit data from
|
||||
* @return 8-bit unsigned value stored in specified I/O port
|
||||
*/
|
||||
#define inpb(port) ((*((volatile unsigned char *)(port))))
|
||||
|
||||
/**
|
||||
* @brief Set a 32-bit unsigned value to specified I/O port
|
||||
* @param[in] port Port address to set 32-bit data
|
||||
* @param[in] value Value to write to I/O port
|
||||
* @return None
|
||||
* @note The output port must be 32-bit aligned
|
||||
*/
|
||||
#define outp32(port,value) (*((volatile unsigned int *)(port))=(value))
|
||||
|
||||
/**
|
||||
* @brief Get a 32-bit unsigned value from specified I/O port
|
||||
* @param[in] port Port address to get 32-bit data from
|
||||
* @return 32-bit unsigned value stored in specified I/O port
|
||||
* @note The input port must be 32-bit aligned
|
||||
*/
|
||||
#define inp32(port) ((*((volatile unsigned int *)(port))))
|
||||
|
||||
/**
|
||||
* @brief Set a 16-bit unsigned value to specified I/O port
|
||||
* @param[in] port Port address to set 16-bit data
|
||||
* @param[in] value Value to write to I/O port
|
||||
* @return None
|
||||
* @note The output port must be 16-bit aligned
|
||||
*/
|
||||
#define outp16(port,value) (*((volatile unsigned short *)(port))=(value))
|
||||
|
||||
/**
|
||||
* @brief Get a 16-bit unsigned value from specified I/O port
|
||||
* @param[in] port Port address to get 16-bit data from
|
||||
* @return 16-bit unsigned value stored in specified I/O port
|
||||
* @note The input port must be 16-bit aligned
|
||||
*/
|
||||
#define inp16(port) ((*((volatile unsigned short *)(port))))
|
||||
|
||||
/**
|
||||
* @brief Set a 8-bit unsigned value to specified I/O port
|
||||
* @param[in] port Port address to set 8-bit data
|
||||
* @param[in] value Value to write to I/O port
|
||||
* @return None
|
||||
*/
|
||||
#define outp8(port,value) (*((volatile unsigned char *)(port))=(value))
|
||||
|
||||
/**
|
||||
* @brief Get a 8-bit unsigned value from specified I/O port
|
||||
* @param[in] port Port address to get 8-bit data from
|
||||
* @return 8-bit unsigned value stored in specified I/O port
|
||||
*/
|
||||
#define inp8(port) ((*((volatile unsigned char *)(port))))
|
||||
|
||||
/*@}*/ /* end of group IO_ROUTINE */
|
||||
|
||||
/******************************************************************************/
|
||||
/* Legacy Constants */
|
||||
/******************************************************************************/
|
||||
|
||||
/** @addtogroup Legacy_Constants Legacy Constants
|
||||
Legacy Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
#define E_SUCCESS (0)
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL (0) ///< NULL pointer
|
||||
#endif
|
||||
|
||||
#define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value
|
||||
#define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value
|
||||
|
||||
#define ENABLE (1UL) ///< Enable, define to use in API parameters
|
||||
#define DISABLE (0UL) ///< Disable, define to use in API parameters
|
||||
|
||||
/* Define one bit mask */
|
||||
#define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer
|
||||
#define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer
|
||||
#define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer
|
||||
#define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer
|
||||
#define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer
|
||||
#define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer
|
||||
#define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer
|
||||
#define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer
|
||||
#define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer
|
||||
#define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer
|
||||
#define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer
|
||||
#define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer
|
||||
#define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer
|
||||
#define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer
|
||||
#define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer
|
||||
#define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer
|
||||
#define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer
|
||||
#define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer
|
||||
#define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer
|
||||
#define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer
|
||||
#define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer
|
||||
#define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer
|
||||
#define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer
|
||||
#define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer
|
||||
#define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer
|
||||
#define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer
|
||||
#define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer
|
||||
#define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer
|
||||
#define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer
|
||||
#define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer
|
||||
#define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer
|
||||
#define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer
|
||||
|
||||
|
||||
/* Byte Mask Definitions */
|
||||
#define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer
|
||||
#define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer
|
||||
#define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer
|
||||
#define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer
|
||||
|
||||
#define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
|
||||
#define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
|
||||
#define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
|
||||
#define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
|
||||
|
||||
/* Chip Series number definitions */
|
||||
#define GET_CHIP_SERIES_NUM ((SYS->PDID & 0xF00) >> 8) /*!< Extract chip series number from PDID */
|
||||
#define CHIP_SERIES_NUM_B (0xBUL) /*!< Chip series number for M031_B */
|
||||
#define CHIP_SERIES_NUM_C (0xCUL) /*!< Chip series number for M031_C */
|
||||
#define CHIP_SERIES_NUM_D (0xDUL) /*!< Chip series number for M031_D */
|
||||
#define CHIP_SERIES_NUM_E (0xEUL) /*!< Chip series number for M031_E */
|
||||
#define CHIP_SERIES_NUM_G (0x6UL) /*!< Chip series number for M031_G */
|
||||
#define CHIP_SERIES_NUM_I (0x1UL) /*!< Chip series number for M031_I */
|
||||
|
||||
/*@}*/ /* end of group Legacy_Constants */
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral header files */
|
||||
/******************************************************************************/
|
||||
#include "nu_sys.h"
|
||||
#include "nu_clk.h"
|
||||
#include "nu_acmp.h"
|
||||
#include "nu_adc.h"
|
||||
#include "nu_crc.h"
|
||||
#include "nu_ebi.h"
|
||||
#include "nu_fmc.h"
|
||||
#include "nu_gpio.h"
|
||||
#include "nu_i2c.h"
|
||||
#include "nu_pdma.h"
|
||||
#include "nu_pwm.h"
|
||||
#include "nu_bpwm.h"
|
||||
#include "nu_qspi.h"
|
||||
#include "nu_spi.h"
|
||||
#include "nu_rtc.h"
|
||||
#include "nu_hdiv.h"
|
||||
#include "nu_timer.h"
|
||||
#include "nu_uart.h"
|
||||
#include "nu_usbd.h"
|
||||
#include "nu_usci_i2c.h"
|
||||
#include "nu_usci_spi.h"
|
||||
#include "nu_usci_uart.h"
|
||||
#include "nu_wdt.h"
|
||||
#include "nu_wwdt.h"
|
||||
|
||||
#endif // __M031SERIES_H__
|
||||
|
||||
/* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. */
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file NuMicro.h
|
||||
* @version V1.00
|
||||
* @brief NuMicro peripheral access layer header file.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NUMICRO_H__
|
||||
#define __NUMICRO_H__
|
||||
|
||||
#include "nutool_clkcfg.h"
|
||||
#include "M031Series.h"
|
||||
|
||||
#endif /* __NUMICRO_H__ */
|
||||
|
||||
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,255 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file acmp_reg.h
|
||||
* @version V1.00
|
||||
* @brief ACMP register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __ACMP_REG_H__
|
||||
#define __ACMP_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup ACMP Analog Comparator Controller (ACMP)
|
||||
Memory Mapped Structure for ACMP Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var ACMP_T::CTL
|
||||
* Offset: 0x00/0x04 Analog Comparator 0/1 Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ACMPEN |Comparator Enable Bit
|
||||
* | | |0 = Comparator 0 Disabled.
|
||||
* | | |1 = Comparator 0 Enabled.
|
||||
* |[1] |ACMPIE |Comparator Interrupt Enable Bit
|
||||
* | | |0 = Comparator 0 interrupt Disabled.
|
||||
* | | |1 = Comparator 0 interrupt Enabled. If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
|
||||
* |[3] |ACMPOINV |Comparator Output Inverse
|
||||
* | | |0 = Comparator 0 output inverse Disabled.
|
||||
* | | |1 = Comparator 0 output inverse Enabled.
|
||||
* |[5:4] |NEGSEL |Comparator Negative Input Selection
|
||||
* | | |00 = ACMP0_N pin.
|
||||
* | | |01 = Internal comparator reference voltage (CRV).
|
||||
* | | |10 = Band-gap voltage.
|
||||
* | | |11 = Reserved.
|
||||
* |[7:6] |POSSEL |Comparator Positive Input Selection
|
||||
* | | |00 = Input from ACMP0_P0.
|
||||
* | | |01 = Input from ACMP0_P1.
|
||||
* | | |10 = Input from ACMP0_P2.
|
||||
* | | |11 = Input from ACMP0_P3.
|
||||
* |[9:8] |INTPOL |Interrupt Condition Polarity Selection
|
||||
* | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected.
|
||||
* | | |00 = Rising edge or falling edge.
|
||||
* | | |01 = Rising edge.
|
||||
* | | |10 = Falling edge.
|
||||
* | | |11 = Reserved.
|
||||
* |[12] |OUTSEL |Comparator Output Select
|
||||
* | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output.
|
||||
* | | |1 = Comparator 0 output to ACMP0_O pin is from filter output.
|
||||
* |[15:13] |FILTSEL |Comparator Output Filter Count Selection
|
||||
* | | |000 = Filter function is Disabled.
|
||||
* | | |001 = ACMP0 output is sampled 1 consecutive PCLK.
|
||||
* | | |010 = ACMP0 output is sampled 2 consecutive PCLKs.
|
||||
* | | |011 = ACMP0 output is sampled 4 consecutive PCLKs.
|
||||
* | | |100 = ACMP0 output is sampled 8 consecutive PCLKs.
|
||||
* | | |101 = ACMP0 output is sampled 16 consecutive PCLKs.
|
||||
* | | |110 = ACMP0 output is sampled 32 consecutive PCLKs.
|
||||
* | | |111 = ACMP0 output is sampled 64 consecutive PCLKs.
|
||||
* |[16] |WKEN |Power-down Wake-up Enable Bit
|
||||
* | | |0 = Wake-up function Disabled.
|
||||
* | | |1 = Wake-up function Enabled.
|
||||
* |[17] |WLATEN |Window Latch Mode Enable Bit
|
||||
* | | |0 = Window Latch Mode Disabled.
|
||||
* | | |1 = Window Latch Mode Enabled.
|
||||
* |[18] |WCMPSEL |Window Compare Mode Selection
|
||||
* | | |0 = Window Compare Mode Disabled.
|
||||
* | | |1 = Window Compare Mode is Selected.
|
||||
* @var ACMP_T::STATUS
|
||||
* Offset: 0x08 Analog Comparator Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
|
||||
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
|
||||
* | | |Note: Write 1 to clear this bit to 0.
|
||||
* |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
|
||||
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output.
|
||||
* | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
|
||||
* | | |Note: Write 1 to clear this bit to 0.
|
||||
* |[4] |ACMPO0 |Comparator 0 Output
|
||||
* | | |Synchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
|
||||
* |[5] |ACMPO1 |Comparator 1 Output
|
||||
* | | |Synchronized to the PCLK to allow reading by software
|
||||
* | | |Cleared when the comparator 1 is disabled, i.e
|
||||
* | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
|
||||
* |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag
|
||||
* | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
|
||||
* | | |0 = No power-down wake-up occurred.
|
||||
* | | |1 = Power-down wake-up occurred.
|
||||
* | | |Note: Write 1 to clear this bit to 0.
|
||||
* |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag
|
||||
* | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
|
||||
* | | |0 = No power-down wake-up occurred.
|
||||
* | | |1 = Power-down wake-up occurred.
|
||||
* | | |Note: Write 1 to clear this bit to 0.
|
||||
* |[12] |ACMPS0 |Comparator 0 Status
|
||||
* | | |Synchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
|
||||
* |[13] |ACMPS1 |Comparator 1 Status
|
||||
* | | |Synchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
|
||||
* |[16] |ACMPWO |Comparator Window Output
|
||||
* | | |This bit shows the output status of window compare mode.
|
||||
* | | |0 = The positive input voltage is outside the window.
|
||||
* | | |1 = The positive input voltage is in the window.
|
||||
* @var ACMP_T::VREF
|
||||
* Offset: 0x0C Analog Comparator Reference Voltage Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |CRVCTL |Comparator Reference Voltage Setting
|
||||
* | | |CRV = CRV source voltage * (1/6+CRVCTL/24).
|
||||
* |[6] |CRVSSEL |CRV Source Voltage Selection
|
||||
* | | |0 = AVDD is selected as CRV source voltage.
|
||||
* | | |1 = VREF is selected as as CRV source voltage.
|
||||
*/
|
||||
__IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0/1 Control Register */
|
||||
__IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */
|
||||
__IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */
|
||||
__IO uint32_t CALCTL; /*!< [0x0010] Analog Comparator Calibration Control Register */
|
||||
__I uint32_t CALSR; /*!< [0x0014] Analog Comparator Calibration Status Register */
|
||||
|
||||
} ACMP_T;
|
||||
|
||||
/**
|
||||
@addtogroup ACMP_CONST ACMP Bit Field Definition
|
||||
Constant Definitions for ACMP Controller
|
||||
@{ */
|
||||
|
||||
#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */
|
||||
#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */
|
||||
|
||||
#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */
|
||||
#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */
|
||||
|
||||
#define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL: HYSEN Position */
|
||||
#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL: HYSEN Mask */
|
||||
|
||||
#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */
|
||||
#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */
|
||||
|
||||
#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */
|
||||
#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */
|
||||
|
||||
#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */
|
||||
#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */
|
||||
|
||||
#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */
|
||||
#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */
|
||||
|
||||
#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */
|
||||
#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */
|
||||
|
||||
#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */
|
||||
#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */
|
||||
|
||||
#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */
|
||||
#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */
|
||||
|
||||
#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */
|
||||
#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */
|
||||
|
||||
#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */
|
||||
#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
|
||||
#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
|
||||
#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
|
||||
#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
|
||||
#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
|
||||
|
||||
#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
|
||||
#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
|
||||
|
||||
#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
|
||||
#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */
|
||||
#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */
|
||||
#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */
|
||||
|
||||
#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */
|
||||
#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */
|
||||
|
||||
#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */
|
||||
#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */
|
||||
|
||||
#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */
|
||||
#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */
|
||||
|
||||
#define ACMP_CALCTL_CALTRG0_Pos (0) /*!< ACMP_T::CALCTL: CALTRG0 Position */
|
||||
#define ACMP_CALCTL_CALTRG0_Msk (0x1ul << ACMP_CALCTL_CALTRG0_Pos) /*!< ACMP_T::CALCTL: CALTRG0 Mask */
|
||||
|
||||
#define ACMP_CALCTL_CALTRG1_Pos (1) /*!< ACMP_T::CALCTL: CALTRG1 Position */
|
||||
#define ACMP_CALCTL_CALTRG1_Msk (0x1ul << ACMP_CALCTL_CALTRG1_Pos) /*!< ACMP_T::CALCTL: CALTRG1 Mask */
|
||||
|
||||
#define ACMP_CALCTL_CALCLK0_Pos (4) /*!< ACMP_T::CALCTL: CALCLK0 Position */
|
||||
#define ACMP_CALCTL_CALCLK0_Msk (0x3ul << ACMP_CALCTL_CALCLK0_Pos) /*!< ACMP_T::CALCTL: CALCLK0 Mask */
|
||||
|
||||
#define ACMP_CALCTL_CALCLK1_Pos (6) /*!< ACMP_T::CALCTL: CALCLK1 Position */
|
||||
#define ACMP_CALCTL_CALCLK1_Msk (0x3ul << ACMP_CALCTL_CALCLK1_Pos) /*!< ACMP_T::CALCTL: CALCLK1 Mask */
|
||||
|
||||
#define ACMP_CALCTL_CALRVS0_Pos (16) /*!< ACMP_T::CALCTL: CALRVS0 Position */
|
||||
#define ACMP_CALCTL_CALRVS0_Msk (0x1ul << ACMP_CALCTL_CALRVS0_Pos) /*!< ACMP_T::CALCTL: CALRVS0 Mask */
|
||||
|
||||
#define ACMP_CALCTL_CALRVS1_Pos (17) /*!< ACMP_T::CALCTL: CALRVS1 Position */
|
||||
#define ACMP_CALCTL_CALRVS1_Msk (0x1ul << ACMP_CALCTL_CALRVS1_Pos) /*!< ACMP_T::CALCTL: CALRVS1 Mask */
|
||||
|
||||
#define ACMP_CALSR_DONE0_Pos (0) /*!< ACMP_T::CALSR: DONE0 Position */
|
||||
#define ACMP_CALSR_DONE0_Msk (0x1ul << ACMP_CALSR_DONE0_Pos) /*!< ACMP_T::CALSR: DONE0 Mask */
|
||||
|
||||
#define ACMP_CALSR_CALNS0_Pos (1) /*!< ACMP_T::CALSR: CALNS0 Position */
|
||||
#define ACMP_CALSR_CALNS0_Msk (0x1ul << ACMP_CALSR_CALNS0_Pos) /*!< ACMP_T::CALSR: CALNS0 Mask */
|
||||
|
||||
#define ACMP_CALSR_CALPS0_Pos (2) /*!< ACMP_T::CALSR: CALPS0 Position */
|
||||
#define ACMP_CALSR_CALPS0_Msk (0x1ul << ACMP_CALSR_CALPS0_Pos) /*!< ACMP_T::CALSR: CALPS0 Mask */
|
||||
|
||||
#define ACMP_CALSR_DONE1_Pos (4) /*!< ACMP_T::CALSR: DONE1 Position */
|
||||
#define ACMP_CALSR_DONE1_Msk (0x1ul << ACMP_CALSR_DONE1_Pos) /*!< ACMP_T::CALSR: DONE1 Mask */
|
||||
|
||||
#define ACMP_CALSR_CALNS1_Pos (5) /*!< ACMP_T::CALSR: CALNS1 Position */
|
||||
#define ACMP_CALSR_CALNS1_Msk (0x1ul << ACMP_CALSR_CALNS1_Pos) /*!< ACMP_T::CALSR: CALNS1 Mask */
|
||||
|
||||
#define ACMP_CALSR_CALPS1_Pos (6) /*!< ACMP_T::CALSR: CALPS1 Position */
|
||||
#define ACMP_CALSR_CALPS1_Msk (0x1ul << ACMP_CALSR_CALPS1_Pos) /*!< ACMP_T::CALSR: CALPS1 Mask */
|
||||
|
||||
/**@}*/ /* ACMP_CONST */
|
||||
/**@}*/ /* end of ACMP register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __ACMP_REG_H__ */
|
||||
|
|
@ -1,400 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file adc_reg.h
|
||||
* @version V1.00
|
||||
* @brief ADC register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __ADC_REG_H__
|
||||
#define __ADC_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup ADC Analog to Digital Converter (ADC)
|
||||
Memory Mapped Structure for ADC Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var ADC_T::ADDR
|
||||
* Offset: 0x00-0x74 ADC Data Register 0-29
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |RSLT |A/D Conversion Result (Read Only)
|
||||
* | | |This field contains conversion result of ADC.
|
||||
* |[16] |OVERRUN |Overrun Flag (Read Only)
|
||||
* | | |If converted data in RSLT bits has not been read before new conversion result is loaded to this register, OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read.
|
||||
* | | |0 = Data in RSLT bits is not overwrote.
|
||||
* | | |1 = Data in RSLT bits is overwrote.
|
||||
* |[17] |VALID |Valid Flag (Read Only)
|
||||
* | | |This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read.
|
||||
* | | |0 = Data in RSLT bits is not valid.
|
||||
* | | |1 = Data in RSLT bits is valid.
|
||||
* @var ADC_T::ADCR
|
||||
* Offset: 0x80 ADC Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ADEN |A/D Converter Enable Bit
|
||||
* | | |0 = A/D converter Disabled.
|
||||
* | | |1 = A/D converter Enabled.
|
||||
* | | |Note: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
|
||||
* |[1] |ADIE |A/D Interrupt Enable Bit
|
||||
* | | |A/D conversion end interrupt request is generated if ADIE bit is set to 1.
|
||||
* | | |0 = A/D interrupt function Disabled.
|
||||
* | | |1 = A/D interrupt function Enabled.
|
||||
* |[3:2] |ADMD |A/D Converter Operation Mode Control
|
||||
* | | |00 = Single conversion.
|
||||
* | | |01 = Burst conversion.
|
||||
* | | |10 = Single-cycle Scan.
|
||||
* | | |11 = Continuous Scan.
|
||||
* | | |Note1: When changing the operation mode, software should clear ADST bit first.
|
||||
* | | |Note2: In Burst mode, the A/D result data is always at ADC Data Register 0.
|
||||
* |[5:4] |TRGS |Hardware Trigger Source
|
||||
* | | |00 = A/D conversion is started by external STADC pin.
|
||||
* | | |01 = Timer0 ~ Timer3 overflow pulse trigger.
|
||||
* | | |10 = Reserved.
|
||||
* | | |11 = A/D conversion is started by PWM trigger.
|
||||
* | | |Note: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits.
|
||||
* |[7:6] |TRGCOND |External Trigger Condition
|
||||
* | | |These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger.
|
||||
* | | |00 = Low level.
|
||||
* | | |01 = High level.
|
||||
* | | |10 = Falling edge.
|
||||
* | | |11 = Rising edge.
|
||||
* |[8] |TRGEN |External Trigger Enable Bit
|
||||
* | | |Enable or disable triggering of A/D conversion by external STADC pin, PWM trigger and Timer trigger. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source.
|
||||
* | | |0 = External trigger Disabled.
|
||||
* | | |1 = External trigger Enabled.
|
||||
* | | |Note: The ADC external trigger function is only supported in Single-cycle Scan mode.
|
||||
* |[9] |PTEN |PDMA Transfer Enable Bit
|
||||
* | | |When A/D conversion is completed, the converted data is loaded into ADDR0~15, ADDR29. Software can enable this bit to generate a PDMA data transfer request.
|
||||
* | | |0 = PDMA data transfer Disabled.
|
||||
* | | |1 = PDMA data transfer in ADDR0~15, ADDR29 Enabled.
|
||||
* | | |Note: When PTEN=1, software must set ADIE=0 to disable interrupt.
|
||||
* |[10] |DIFFEN |Differential Input Mode Control
|
||||
* | | |Differential input voltage (Vdiff) = Vplus - Vminus.
|
||||
* | | |The relation between Vplus and Vminus is Vplus + Vminus = Vref.
|
||||
* | | |The Vplus of differential input paired channel x is from ADC0_CHy pin; Vminus is from ADC0_CHz pin, x=0,1..7, y=2*x, z=y+1.
|
||||
* | | |0 = Single-end analog input mode.
|
||||
* | | |1 = Differential analog input mode.
|
||||
* | | |Note: In Differential Input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER register. The conversion result will be placed to the corresponding data register of the enabled channel.
|
||||
* |[11] |ADST |A/D Conversion Start or Calibration Start
|
||||
* | | |ADST bit can be set to 1 from four sources: software, external pin STADC, PWM trigger and Timer trigger. ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode, Single-cycle Scan mode and Calibration mode. In Continuous Scan mode and Burst mode, A/D conversion is continuously performed until software writes 0 to this bit or chip is reset.
|
||||
* | | |0 = Conversion stops and A/D converter enters idle state.
|
||||
* | | |1 = Conversion starts or Calibration Start.
|
||||
* | | |Note1: When ADST become from 1 to 0, ADC macro will reset to initial state. After macro reset to initial state, user should wait at most 2 ADC clock and set this bit to start next conversion.
|
||||
* | | |Note2: Calibration Start only if CALEN (ADC_ADCALR[0]) = 1.
|
||||
* |[12] |RESET |ADC RESET (Write Protect)
|
||||
* | | |If user writes this bit, the ADC analog macro will reset
|
||||
* | | |Calibration data in macro will be deleted, but registers in ADC controller will keep.
|
||||
* | | |Note: This bit is cleared by hardware.
|
||||
* |[31] |DMOF |Differential Input Mode Output Format
|
||||
* | | |If user enables differential input mode, the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format).
|
||||
* | | |0 = A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format (straight binary format).
|
||||
* | | |1 = A/D Conversion result will be filled in RSLT at ADDRx registers with 2's complement format.
|
||||
* @var ADC_T::ADCHER
|
||||
* Offset: 0x84 ADC Channel Enable Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |CHEN |Analog Input Channel Enable Control
|
||||
* | | |Set ADCHER[15:0] bits to enable the corresponding analog input channel 15 ~ 0
|
||||
* | | |If DIFFEN bit is set to 1, only the even number channel needs to be enabled.
|
||||
* | | |Besides, set ADCHER[29] bit will enable internal channel for band-gap voltage respectively
|
||||
* | | |Other bits are reserved.
|
||||
* | | |0 = Channel Disabled.
|
||||
* | | |1 = Channel Enabled.
|
||||
* | | |Note1: If the internal channel for band-gap voltage (CHEN[29]) is active, the maximum sampling rate will be 1M SPS.
|
||||
* @var ADC_T::ADCMPR
|
||||
* Offset: 0x88/0x8C ADC Compare Register 0/1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CMPEN |Compare Enable Bit
|
||||
* | | |Set this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register.
|
||||
* | | |0 = Compare function Disabled.
|
||||
* | | |1 = Compare function Enabled.
|
||||
* |[1] |CMPIE |Compare Interrupt Enable Bit
|
||||
* | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE bit is set to 1, a compare interrupt request is generated.
|
||||
* | | |0 = Compare function interrupt Disabled.
|
||||
* | | |1 = Compare function interrupt Enabled.
|
||||
* |[2] |CMPCOND |Compare Condition
|
||||
* | | |0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD bits, the internal match counter will increase one.
|
||||
* | | |1 = Set the compare condition as that when a 12-bit A/D conversion result is greater than or equal to the 12-bit CMPD bits, the internal match counter will increase one.
|
||||
* | | |Note: When the internal counter reaches to (CMPMATCNT +1), the CMPFx bit will be set.
|
||||
* |[7:3] |CMPCH |Compare Channel Selection
|
||||
* | | |00000 = Channel 0 conversion result is selected to be compared.
|
||||
* | | |00001 = Channel 1 conversion result is selected to be compared.
|
||||
* | | |00010 = Channel 2 conversion result is selected to be compared.
|
||||
* | | |00011 = Channel 3 conversion result is selected to be compared.
|
||||
* | | |00100 = Channel 4 conversion result is selected to be compared.
|
||||
* | | |00101 = Channel 5 conversion result is selected to be compared.
|
||||
* | | |00110 = Channel 6 conversion result is selected to be compared.
|
||||
* | | |00111 = Channel 7 conversion result is selected to be compared.
|
||||
* | | |01000 = Channel 8 conversion result is selected to be compared.
|
||||
* | | |01001 = Channel 9 conversion result is selected to be compared.
|
||||
* | | |01010 = Channel 10 conversion result is selected to be compared.
|
||||
* | | |01011 = Channel 11 conversion result is selected to be compared.
|
||||
* | | |01100 = Channel 12 conversion result is selected to be compared.
|
||||
* | | |01101 = Channel 13 conversion result is selected to be compared.
|
||||
* | | |01110 = Channel 14 conversion result is selected to be compared.
|
||||
* | | |01111 = Channel 15 conversion result is selected to be compared.
|
||||
* | | |11101 = Band-gap voltage conversion result is selected to be compared.
|
||||
* | | |Others = Reserved.
|
||||
* |[11:8] |CMPMATCNT |Compare Match Count
|
||||
* | | |When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit, the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
|
||||
* |[15] |CMPWEN |Compare Window Mode Enable Bit
|
||||
* | | |0 = Compare Window Mode Disabled.
|
||||
* | | |1 = Compare Window Mode Enabled.
|
||||
* | | |Note: This bit is only presented in ADCMPR0 register.
|
||||
* |[27:16] |CMPD |Comparison Data
|
||||
* | | |The 12-bit data is used to compare with conversion result of specified channel.
|
||||
* | | |Note: CMPD bits should be filled in unsigned format (straight binary format).
|
||||
* @var ADC_T::ADSR0
|
||||
* Offset: 0x90 ADC Status Register0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ADF |A/D Conversion End Flag
|
||||
* | | |A status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.
|
||||
* | | |ADF bit is set to 1 at the following three conditions:
|
||||
* | | |1. When A/D conversion ends in Single mode.
|
||||
* | | |2. When A/D conversion ends on all specified channels in Single-cycle Scan mode and Continuous Scan mode.
|
||||
* | | |3. When more than or equal to 8 samples in FIFO in Burst mode.
|
||||
* |[1] |CMPF0 |Compare Flag 0
|
||||
* | | |When the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1. This bit is cleared by writing 1 to it.
|
||||
* | | |0 = Conversion result in ADDR does not meet ADCMPR0 setting.
|
||||
* | | |1 = Conversion result in ADDR meets ADCMPR0 setting.
|
||||
* |[2] |CMPF1 |Compare Flag 1
|
||||
* | | |When the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register then this bit is set to 1; it is cleared by writing 1 to it.
|
||||
* | | |0 = Conversion result in ADDR does not meet ADCMPR1 setting.
|
||||
* | | |1 = Conversion result in ADDR meets ADCMPR1 setting.
|
||||
* |[7] |BUSY |BUSY/IDLE (Read Only)
|
||||
* | | |This bit is a mirror of ADST bit in ADCR register.
|
||||
* | | |0 = A/D converter is in idle state.
|
||||
* | | |1 = A/D converter is busy at conversion.
|
||||
* |[8] |VALIDF |Data Valid Flag (Read Only)
|
||||
* | | |If any one of VALID (ADDRx[17]) is set, this flag will be set to 1.
|
||||
* | | |Note: When ADC is in burst mode and any conversion result is valid, this flag will be set to 1.
|
||||
* |[16] |OVERRUNF |Overrun Flag (Read Only)
|
||||
* | | |If any one of OVERRUN (ADDRx[16]) is set, this flag will be set to 1.
|
||||
* | | |Note: When ADC is in burst mode and the FIFO is overrun, this flag will be set to 1.
|
||||
* |[31:27] |CHANNEL |Current Conversion Channel (Read Only)
|
||||
* | | |When BUSY=1, this filed reflects current conversion channel. When BUSY=0, it shows the number of the next converted channel.
|
||||
* @var ADC_T::ADSR1
|
||||
* Offset: 0x94 ADC Status Register1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |VALID |Data Valid Flag (Read Only)
|
||||
* | | |VALID[29, 15:0] are the mirror of the VALID bits in ADDR29[17], ADDR15[17]~ ADDR0[17]. The other bits are reserved.
|
||||
* | | |Note: When ADC is in burst mode and any conversion result is valid, VALID[29, 15:0] will be set to 1.
|
||||
* @var ADC_T::ADSR2
|
||||
* Offset: 0x98 ADC Status Register2
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |OVERRUN |Overrun Flag (Read Only)
|
||||
* | | |OVERRUN[29, 15:0] are the mirror of the OVERRUN bit in ADDR29[16], ADDR15[16] ~ ADDR0[16]. The other bits are reserved.
|
||||
* | | |Note: When ADC is in burst mode and the FIFO is overrun, OVERRUN[29, 15:0] will be set to 1.
|
||||
* @var ADC_T::ESMPCTL
|
||||
* Offset: 0xA0 ADC Extend Sample Time Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:0] |EXTSMPT |ADC Sampling Time Extend
|
||||
* | | |When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time.
|
||||
* | | |The range of start delay time is from 0~255 ADC clock.
|
||||
* @var ADC_T::ADPDMA
|
||||
* Offset: 0x100 ADC PDMA Current Transfer Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register (Read Only)
|
||||
* | | |When PDMA transferring, read this register can monitor current PDMA transfer data.
|
||||
* | | |Current PDMA transfer data could be the content of ADDR0 ~ ADDR15 and ADDR29 registers.
|
||||
* @var ADC_T::ADCALR
|
||||
* Offset: 0x180 ADC Calibration Mode Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CALEN |Calibration Function Enable Bit
|
||||
* | | |0 = Calibration function Disable.
|
||||
* | | |1 = Calibration function Enable.
|
||||
* | | |Note: If chip power off, calibration function should be executed again.
|
||||
* |[1] |CALIE |Calibration Interrupt Enable
|
||||
* | | |If calibration function is enabled and the calibration finish, CALIF bit will be asserted, in the meanwhile, if CALIE bit is set to 1, a calibration interrupt request is generated.
|
||||
* | | |0 = Calibration function Interrupt Disable.
|
||||
* | | |1 = Calibration function Interrupt Enable.
|
||||
* @var ADC_T::ADCALSTSR
|
||||
* Offset: 0x184 ADC Calibration Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CALIF |Calibration Finish Interrupt Flag
|
||||
* | | |If calibration finish, this flag will be set to 1. It is cleared by writing 1 to it.
|
||||
*/
|
||||
__I uint32_t ADDR[30]; /*!< [0x0000-0x0074] ADC Data Register 0 ~ 29 */
|
||||
__I uint32_t RESERVE1[2];
|
||||
__IO uint32_t ADCR; /*!< [0x0080] ADC Control Register */
|
||||
__IO uint32_t ADCHER; /*!< [0x0084] ADC Channel Enable Register */
|
||||
__IO uint32_t ADCMPR[2]; /*!< [0x0088-0x008c] ADC Compare Register 0/1 */
|
||||
__IO uint32_t ADSR0; /*!< [0x0090] ADC Status Register0 */
|
||||
__I uint32_t ADSR1; /*!< [0x0094] ADC Status Register1 */
|
||||
__I uint32_t ADSR2; /*!< [0x0098] ADC Status Register2 */
|
||||
__I uint32_t RESERVE2[1];
|
||||
__IO uint32_t ESMPCTL; /*!< [0x00a0] ADC Extend Sample Time Control Register */
|
||||
__IO uint32_t CFDCTL; /*!< [0x00a4] ADC Channel Floating Detect Control Register */
|
||||
__I uint32_t RESERVE3[22];
|
||||
__I uint32_t ADPDMA; /*!< [0x0100] ADC PDMA Current Transfer Data Register */
|
||||
__I uint32_t RESERVE4[31];
|
||||
__IO uint32_t ADCALR; /*!< [0x0180] ADC Calibration Mode Register */
|
||||
__IO uint32_t ADCALSTSR; /*!< [0x0184] ADC Calibration Status Register */
|
||||
__IO uint32_t ADCALDBR; /*!< [0x0188] ADC Calibration Debug Mode Register */
|
||||
} ADC_T;
|
||||
|
||||
/**
|
||||
@addtogroup ADC_CONST ADC Bit Field Definition
|
||||
Constant Definitions for ADC Controller
|
||||
@{ */
|
||||
|
||||
#define ADC_ADDR_RSLT_Pos (0) /*!< ADC_T::ADDR: RSLT Position */
|
||||
#define ADC_ADDR_RSLT_Msk (0xfffful << ADC_ADDR_RSLT_Pos) /*!< ADC_T::ADDR: RSLT Mask */
|
||||
|
||||
#define ADC_ADDR_OVERRUN_Pos (16) /*!< ADC_T::ADDR: OVERRUN Position */
|
||||
#define ADC_ADDR_OVERRUN_Msk (0x1ul << ADC_ADDR_OVERRUN_Pos) /*!< ADC_T::ADDR: OVERRUN Mask */
|
||||
|
||||
#define ADC_ADDR_VALID_Pos (17) /*!< ADC_T::ADDR: VALID Position */
|
||||
#define ADC_ADDR_VALID_Msk (0x1ul << ADC_ADDR_VALID_Pos) /*!< ADC_T::ADDR: VALID Mask */
|
||||
|
||||
#define ADC_ADCR_ADEN_Pos (0) /*!< ADC_T::ADCR: ADEN Position */
|
||||
#define ADC_ADCR_ADEN_Msk (0x1ul << ADC_ADCR_ADEN_Pos) /*!< ADC_T::ADCR: ADEN Mask */
|
||||
|
||||
#define ADC_ADCR_ADIE_Pos (1) /*!< ADC_T::ADCR: ADIE Position */
|
||||
#define ADC_ADCR_ADIE_Msk (0x1ul << ADC_ADCR_ADIE_Pos) /*!< ADC_T::ADCR: ADIE Mask */
|
||||
|
||||
#define ADC_ADCR_ADMD_Pos (2) /*!< ADC_T::ADCR: ADMD Position */
|
||||
#define ADC_ADCR_ADMD_Msk (0x3ul << ADC_ADCR_ADMD_Pos) /*!< ADC_T::ADCR: ADMD Mask */
|
||||
|
||||
#define ADC_ADCR_TRGS_Pos (4) /*!< ADC_T::ADCR: TRGS Position */
|
||||
#define ADC_ADCR_TRGS_Msk (0x3ul << ADC_ADCR_TRGS_Pos) /*!< ADC_T::ADCR: TRGS Mask */
|
||||
|
||||
#define ADC_ADCR_TRGCOND_Pos (6) /*!< ADC_T::ADCR: TRGCOND Position */
|
||||
#define ADC_ADCR_TRGCOND_Msk (0x3ul << ADC_ADCR_TRGCOND_Pos) /*!< ADC_T::ADCR: TRGCOND Mask */
|
||||
|
||||
#define ADC_ADCR_TRGEN_Pos (8) /*!< ADC_T::ADCR: TRGEN Position */
|
||||
#define ADC_ADCR_TRGEN_Msk (0x1ul << ADC_ADCR_TRGEN_Pos) /*!< ADC_T::ADCR: TRGEN Mask */
|
||||
|
||||
#define ADC_ADCR_PTEN_Pos (9) /*!< ADC_T::ADCR: PTEN Position */
|
||||
#define ADC_ADCR_PTEN_Msk (0x1ul << ADC_ADCR_PTEN_Pos) /*!< ADC_T::ADCR: PTEN Mask */
|
||||
|
||||
#define ADC_ADCR_DIFFEN_Pos (10) /*!< ADC_T::ADCR: DIFFEN Position */
|
||||
#define ADC_ADCR_DIFFEN_Msk (0x1ul << ADC_ADCR_DIFFEN_Pos) /*!< ADC_T::ADCR: DIFFEN Mask */
|
||||
|
||||
#define ADC_ADCR_ADST_Pos (11) /*!< ADC_T::ADCR: ADST Position */
|
||||
#define ADC_ADCR_ADST_Msk (0x1ul << ADC_ADCR_ADST_Pos) /*!< ADC_T::ADCR: ADST Mask */
|
||||
|
||||
#define ADC_ADCR_RESET_Pos (12) /*!< ADC_T::ADCR: RESET Position */
|
||||
#define ADC_ADCR_RESET_Msk (0x1ul << ADC_ADCR_RESET_Pos) /*!< ADC_T::ADCR: RESET Mask */
|
||||
|
||||
#define ADC_ADCR_DMOF_Pos (31) /*!< ADC_T::ADCR: DMOF Position */
|
||||
#define ADC_ADCR_DMOF_Msk (0x1ul << ADC_ADCR_DMOF_Pos) /*!< ADC_T::ADCR: DMOF Mask */
|
||||
|
||||
#define ADC_ADCHER_CHEN_Pos (0) /*!< ADC_T::ADCHER: CHEN Position */
|
||||
#define ADC_ADCHER_CHEN_Msk (0xfffffffful << ADC_ADCHER_CHEN_Pos) /*!< ADC_T::ADCHER: CHEN Mask */
|
||||
|
||||
#define ADC_ADCMPR_CMPEN_Pos (0) /*!< ADC_T::ADCMPR: CMPEN Position */
|
||||
#define ADC_ADCMPR_CMPEN_Msk (0x1ul << ADC_ADCMPR_CMPEN_Pos) /*!< ADC_T::ADCMPR: CMPEN Mask */
|
||||
|
||||
#define ADC_ADCMPR_CMPIE_Pos (1) /*!< ADC_T::ADCMPR: CMPIE Position */
|
||||
#define ADC_ADCMPR_CMPIE_Msk (0x1ul << ADC_ADCMPR_CMPIE_Pos) /*!< ADC_T::ADCMPR: CMPIE Mask */
|
||||
|
||||
#define ADC_ADCMPR_CMPCOND_Pos (2) /*!< ADC_T::ADCMPR: CMPCOND Position */
|
||||
#define ADC_ADCMPR_CMPCOND_Msk (0x1ul << ADC_ADCMPR_CMPCOND_Pos) /*!< ADC_T::ADCMPR: CMPCOND Mask */
|
||||
|
||||
#define ADC_ADCMPR_CMPCH_Pos (3) /*!< ADC_T::ADCMPR: CMPCH Position */
|
||||
#define ADC_ADCMPR_CMPCH_Msk (0x1ful << ADC_ADCMPR_CMPCH_Pos) /*!< ADC_T::ADCMPR: CMPCH Mask */
|
||||
|
||||
#define ADC_ADCMPR_CMPMATCNT_Pos (8) /*!< ADC_T::ADCMPR: CMPMATCNT Position */
|
||||
#define ADC_ADCMPR_CMPMATCNT_Msk (0xful << ADC_ADCMPR_CMPMATCNT_Pos) /*!< ADC_T::ADCMPR: CMPMATCNT Mask */
|
||||
|
||||
#define ADC_ADCMPR_CMPWEN_Pos (15) /*!< ADC_T::ADCMPR: CMPWEN Position */
|
||||
#define ADC_ADCMPR_CMPWEN_Msk (0x1ul << ADC_ADCMPR_CMPWEN_Pos) /*!< ADC_T::ADCMPR: CMPWEN Mask */
|
||||
|
||||
#define ADC_ADCMPR_CMPD_Pos (16) /*!< ADC_T::ADCMPR: CMPD Position */
|
||||
#define ADC_ADCMPR_CMPD_Msk (0xffful << ADC_ADCMPR_CMPD_Pos) /*!< ADC_T::ADCMPR: CMPD Mask */
|
||||
|
||||
#define ADC_ADSR0_ADF_Pos (0) /*!< ADC_T::ADSR0: ADF Position */
|
||||
#define ADC_ADSR0_ADF_Msk (0x1ul << ADC_ADSR0_ADF_Pos) /*!< ADC_T::ADSR0: ADF Mask */
|
||||
|
||||
#define ADC_ADSR0_CMPF0_Pos (1) /*!< ADC_T::ADSR0: CMPF0 Position */
|
||||
#define ADC_ADSR0_CMPF0_Msk (0x1ul << ADC_ADSR0_CMPF0_Pos) /*!< ADC_T::ADSR0: CMPF0 Mask */
|
||||
|
||||
#define ADC_ADSR0_CMPF1_Pos (2) /*!< ADC_T::ADSR0: CMPF1 Position */
|
||||
#define ADC_ADSR0_CMPF1_Msk (0x1ul << ADC_ADSR0_CMPF1_Pos) /*!< ADC_T::ADSR0: CMPF1 Mask */
|
||||
|
||||
#define ADC_ADSR0_BUSY_Pos (7) /*!< ADC_T::ADSR0: BUSY Position */
|
||||
#define ADC_ADSR0_BUSY_Msk (0x1ul << ADC_ADSR0_BUSY_Pos) /*!< ADC_T::ADSR0: BUSY Mask */
|
||||
|
||||
#define ADC_ADSR0_VALIDF_Pos (8) /*!< ADC_T::ADSR0: VALIDF Position */
|
||||
#define ADC_ADSR0_VALIDF_Msk (0x1ul << ADC_ADSR0_VALIDF_Pos) /*!< ADC_T::ADSR0: VALIDF Mask */
|
||||
|
||||
#define ADC_ADSR0_OVERRUNF_Pos (16) /*!< ADC_T::ADSR0: OVERRUNF Position */
|
||||
#define ADC_ADSR0_OVERRUNF_Msk (0x1ul << ADC_ADSR0_OVERRUNF_Pos) /*!< ADC_T::ADSR0: OVERRUNF Mask */
|
||||
|
||||
#define ADC_ADSR0_CHANNEL_Pos (27) /*!< ADC_T::ADSR0: CHANNEL Position */
|
||||
#define ADC_ADSR0_CHANNEL_Msk (0x1ful << ADC_ADSR0_CHANNEL_Pos) /*!< ADC_T::ADSR0: CHANNEL Mask */
|
||||
|
||||
#define ADC_ADSR1_VALID_Pos (0) /*!< ADC_T::ADSR1: VALID Position */
|
||||
#define ADC_ADSR1_VALID_Msk (0xfffffffful << ADC_ADSR1_VALID_Pos) /*!< ADC_T::ADSR1: VALID Mask */
|
||||
|
||||
#define ADC_ADSR2_OVERRUN_Pos (0) /*!< ADC_T::ADSR2: OVERRUN Position */
|
||||
#define ADC_ADSR2_OVERRUN_Msk (0xfffffffful << ADC_ADSR2_OVERRUN_Pos) /*!< ADC_T::ADSR2: OVERRUN Mask */
|
||||
|
||||
#define ADC_ESMPCTL_EXTSMPT_Pos (0) /*!< ADC_T::ESMPCTL: EXTSMPT Position */
|
||||
#define ADC_ESMPCTL_EXTSMPT_Msk (0xfful << ADC_ESMPCTL_EXTSMPT_Pos) /*!< ADC_T::ESMPCTL: EXTSMPT Mask */
|
||||
|
||||
#define ADC_CFDCTL_PRECHEN_Pos (0) /*!< ADC_T::CFDCTL: PRECHEN Position */
|
||||
#define ADC_CFDCTL_PRECHEN_Msk (0x1ul << ADC_CFDCTL_PRECHEN_Pos) /*!< ADC_T::CFDCTL: PRECHEN Mask */
|
||||
|
||||
#define ADC_CFDCTL_DISCHEN_Pos (1) /*!< ADC_T::CFDCTL: DISCHEN Position */
|
||||
#define ADC_CFDCTL_DISCHEN_Msk (0x1ul << ADC_CFDCTL_DISCHEN_Pos) /*!< ADC_T::CFDCTL: DISCHEN Mask */
|
||||
|
||||
#define ADC_CFDCTL_FDETCHEN_Pos (8) /*!< ADC_T::CFDCTL: FDETCHEN Position */
|
||||
#define ADC_CFDCTL_FDETCHEN_Msk (0x1ul << ADC_CFDCTL_FDETCHEN_Pos) /*!< ADC_T::CFDCTL: FDETCHEN Mask */
|
||||
|
||||
#define ADC_ADPDMA_CURDAT_Pos (0) /*!< ADC_T::ADPDMA: CURDAT Position */
|
||||
#define ADC_ADPDMA_CURDAT_Msk (0x3fffful << ADC_ADPDMA_CURDAT_Pos) /*!< ADC_T::ADPDMA: CURDAT Mask */
|
||||
|
||||
#define ADC_ADCALR_CALEN_Pos (0) /*!< ADC_T::ADCALR: CALEN Position */
|
||||
#define ADC_ADCALR_CALEN_Msk (0x1ul << ADC_ADCALR_CALEN_Pos) /*!< ADC_T::ADCALR: CALEN Mask */
|
||||
|
||||
#define ADC_ADCALR_CALIE_Pos (1) /*!< ADC_T::ADCALR: CALIE Position */
|
||||
#define ADC_ADCALR_CALIE_Msk (0x1ul << ADC_ADCALR_CALIE_Pos) /*!< ADC_T::ADCALR: CALIE Mask */
|
||||
|
||||
#define ADC_ADCALSTSR_CALIF_Pos (0) /*!< ADC_T::ADCALSTSR: CALIF Position */
|
||||
#define ADC_ADCALSTSR_CALIF_Msk (0x1ul << ADC_ADCALSTSR_CALIF_Pos) /*!< ADC_T::ADCALSTSR: CALIF Mask */
|
||||
|
||||
/**@}*/ /* ADC_CONST */
|
||||
/**@}*/ /* end of ADC register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __ADC_REG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,918 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file clk_reg.h
|
||||
* @version V1.00
|
||||
* @brief CLK register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __CLK_REG_H__
|
||||
#define __CLK_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup CLK System Clock Controller (CLK)
|
||||
Memory Mapped Structure for CLK Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var CLK_T::PWRCTL
|
||||
* Offset: 0x00 System Power-down Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |HXTEN |HXT Enable Bit (Write Protect)
|
||||
* | | |0 = External high speed crystal (HXT) Disabled.
|
||||
* | | |1 = External high speed crystal (HXT) Enabled.
|
||||
* | | |Note1: Reset by power on reset.
|
||||
* | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[1] |LXTEN |LXT Enable Bit (Write Protect)
|
||||
* | | |0 = External low speed crystal (LXT) Disabled.
|
||||
* | | |1 = External low speed crystal (LXT) Enabled.
|
||||
* | | |Note1: Reset by RTC power on reset.
|
||||
* | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[2] |HIRCEN |HIRC Enable Bit (Write Protect)
|
||||
* | | |0 = Internal high speed RC oscillator (HIRC) Disabled.
|
||||
* | | |1 = Internal high speed RC oscillator (HIRC) Enabled.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[3] |LIRCEN |LIRC Enable Bit (Write Protect)
|
||||
* | | |0 = Internal low speed RC oscillator (LIRC) Disabled.
|
||||
* | | |1 = Internal low speed RC oscillator (LIRC) Enabled.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[4] |PDWKDLY |Enable the Wake-up Delay Counter (Write Protect)
|
||||
* | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
|
||||
* | | |The delayed clock cycle is 4096 clock cycles when chip works at external high speed crystal oscillator (HXT), and 512 clock cycles when chip works at internal high speed RC oscillator (HIRC).
|
||||
* | | |0 = Clock cycles delay Disabled.
|
||||
* | | |1 = Clock cycles delay Enabled.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
|
||||
* | | |0 = Power-down mode wake-up interrupt Disabled.
|
||||
* | | |1 = Power-down mode wake-up interrupt Enabled.
|
||||
* | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
|
||||
* | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status
|
||||
* | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode.
|
||||
* | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.
|
||||
* | | |Note1: Write 1 to clear the bit to 0.
|
||||
* | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
|
||||
* |[7] |PDEN |System Power-down Enable (Write Protect)
|
||||
* | | |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
|
||||
* | | |When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.
|
||||
* | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.
|
||||
* | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
|
||||
* | | |0 = Chip operating normally or chip in idle mode because of WFI command.
|
||||
* | | |1 = Chip enters Power-down mode instant or wait CPU sleep command WFI.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect)
|
||||
* | | |0 = HXT Crystal TURBO mode disabled.
|
||||
* | | |1 = HXT Crystal TURBO mode enabled.
|
||||
* | | |Note1: Reset by power on reset.
|
||||
* | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[22:20] |HXTGAIN |HXT Gain Control Bit (Write Protect)
|
||||
* | | |This is a protected register. Please refer to open lock sequence to program it.
|
||||
* | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off.
|
||||
* | | |000 = HXT frequency is lower than from 4 MHz.
|
||||
* | | |001 = HXT frequency is from 4 MHz to 8 MHz.
|
||||
* | | |010 = HXT frequency is from 8 MHz to 12 MHz.
|
||||
* | | |011 = HXT frequency is from 12 MHz to 16 MHz.
|
||||
* | | |100 = HXT frequency is from 16 MHz to 24 MHz.
|
||||
* | | |111 = HXT frequency is from 24 MHz to 32 MHz.
|
||||
* | | |Others: Reserved
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[24] |LXTSELXT |LXT Mode Selection
|
||||
* | | |0 = LXT work as crystal mode. PF.4 and PF.5 are configured as external low speed crystal (LXT) pins.
|
||||
* | | |1 = LXT work as external clock mode. PF.5 is configured as external clock input pin.
|
||||
* | | |Note1: When LXTSELXT = 1, PF.5 MFP should be setting as GPIO mode. The DC characteristic of X32_IN is the same as GPIO.
|
||||
* | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[26:25] |LXTGAIN |LXT Gain Control Bit (Write Protect)
|
||||
* | | |00 = LXT Crystal ESR = 35K, CL=12.5pFReserved.
|
||||
* | | |10 = LXT Crystal ESR = 70K, CL=12.5pFReserved.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* @var CLK_T::AHBCLK
|
||||
* Offset: 0x04 AHB Devices Clock Enable Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1] |PDMACKEN |PDMA Controller Clock Enable Bit
|
||||
* | | |0 = PDMA peripheral clock Disabled.
|
||||
* | | |1 = PDMA peripheral clock Enabled.
|
||||
* |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit
|
||||
* | | |0 = Flash ISP peripheral clock Disabled.
|
||||
* | | |1 = Flash ISP peripheral clock Enabled.
|
||||
* |[3] |EBICKEN |EBI Controller Clock Enable Bit
|
||||
* | | |0 = EBI peripheral clock Disabled.
|
||||
* | | |1 = EBI peripheral clock Enabled.Reserved.
|
||||
* |[4] |HDIVCKEN |HDIV Controller Clock Enable Bit
|
||||
* | | |0 = HDIV peripheral clock Disabled.
|
||||
* | | |1 = HDIV peripheral clock Enabled.Reserved.
|
||||
* |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit
|
||||
* | | |0 = CRC peripheral clock Disabled.
|
||||
* | | |1 = CRC peripheral clock Enabled.
|
||||
* @var CLK_T::APBCLK0
|
||||
* Offset: 0x08 APB Devices Clock Enable Control Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect)
|
||||
* | | |0 = Watchdog timer clock Disabled.
|
||||
* | | |1 = Watchdog timer clock Enabled.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. Reserved.
|
||||
* | | |Note: Reset by power on reset or watch dog reset or software chip reset.
|
||||
* |[2] |TMR0CKEN |Timer0 Clock Enable Bit
|
||||
* | | |0 = Timer0 clock Disabled.
|
||||
* | | |1 = Timer0 clock Enabled.
|
||||
* |[3] |TMR1CKEN |Timer1 Clock Enable Bit
|
||||
* | | |0 = Timer1 clock Disabled.
|
||||
* | | |1 = Timer1 clock Enabled.
|
||||
* |[4] |TMR2CKEN |Timer2 Clock Enable Bit
|
||||
* | | |0 = Timer2 clock Disabled.
|
||||
* | | |1 = Timer2 clock Enabled.
|
||||
* |[5] |TMR3CKEN |Timer3 Clock Enable Bit
|
||||
* | | |0 = Timer3 clock Disabled.
|
||||
* | | |1 = Timer3 clock Enabled.
|
||||
* |[6] |CLKOCKEN |CLKO Clock Enable Bit
|
||||
* | | |0 = CLKO clock Disabled.
|
||||
* | | |1 = CLKO clock Enabled.
|
||||
* |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit
|
||||
* | | |0 = Analog comparator 0/1 clock Disabled.
|
||||
* | | |1 = Analog comparator 0/1 clock Enabled.
|
||||
* |[8] |I2C0CKEN |I2C0 Clock Enable Bit
|
||||
* | | |0 = I2C0 clock Disabled.
|
||||
* | | |1 = I2C0 clock Enabled.
|
||||
* |[9] |I2C1CKEN |I2C1 Clock Enable Bit
|
||||
* | | |0 = I2C1 clock Disabled.
|
||||
* | | |1 = I2C1 clock Enabled.
|
||||
* |[13] |SPI0CKEN |SPI0 Clock Enable Bit
|
||||
* | | |0 = SPI0 clock Disabled.
|
||||
* | | |1 = SPI0 clock Enabled.
|
||||
* |[16] |UART0CKEN |UART0 Clock Enable Bit
|
||||
* | | |0 = UART0 clock Disabled.
|
||||
* | | |1 = UART0 clock Enabled.
|
||||
* |[17] |UART1CKEN |UART1 Clock Enable Bit
|
||||
* | | |0 = UART1 clock Disabled.
|
||||
* | | |1 = UART1 clock Enabled.
|
||||
* |[18] |UART2CKEN |UART2 Clock Enable Bit
|
||||
* | | |0 = UART2 clock Disabled.
|
||||
* | | |1 = UART2 clock Enabled.
|
||||
* |[27] |USBDCKEN |USB Device Clock Enable Bit
|
||||
* | | |0 = USB Device clock Disabled.
|
||||
* | | |1 = USB Device clock Enabled.Reserved.
|
||||
* |[28] |ADCCKEN |Analog-digital-converter (ADC) Clock Enable Bit
|
||||
* | | |0 = ADC clock Disabled.
|
||||
* | | |1 = ADC clock Enabled.Reserved.
|
||||
* @var CLK_T::APBCLK1
|
||||
* Offset: 0x0C APB Devices Clock Enable Control Register 1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8] |USCI0CKEN |USCI0 Clock Enable Bit
|
||||
* | | |0 = USCI0 clock Disabled.
|
||||
* | | |1 = USCI0 clock Enabled.
|
||||
* |[16] |PWM0CKEN |PWM0 Clock Enable Bit
|
||||
* | | |0 = PWM0 clock Disabled.
|
||||
* | | |1 = PWM0 clock Enabled.
|
||||
* |[17] |PWM1CKEN |PWM1 Clock Enable Bit
|
||||
* | | |0 = PWM1 clock Disabled.
|
||||
* | | |1 = PWM1 clock Enabled.
|
||||
* @var CLK_T::CLKSEL0
|
||||
* Offset: 0x10 Clock Source Select Control Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect)
|
||||
* | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
|
||||
* | | |000 = Clock source from HXT.
|
||||
* | | |001 = Clock source from LXT.
|
||||
* | | |010 = Clock source from PLL. (M031_E/M032_E/M031_D only)
|
||||
* | | | = Clock source from HIRC. (M031_C/B only)
|
||||
* | | |011 = Clock source from LIRC.
|
||||
* | | |111= Clock source from HIRC.
|
||||
* | | |Other = Reserved.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* | | |Note: Reset by power on reset.
|
||||
* |[5:3] |STCLKSEL |Cortex-M0 SysTick Clock Source Selection (Write Protect)
|
||||
* | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below.
|
||||
* | | |000 = Clock source from HXT.
|
||||
* | | |001 = Clock source from LXT.
|
||||
* | | |010 = Clock source from HXT/2.
|
||||
* | | |011 = Clock source from HCLK/2.
|
||||
* | | |111 = Clock source from HIRC/2.
|
||||
* | | |Other = Reserved.
|
||||
* | | |Note: if SysTick clock source is not from HCLK (i.e. SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[8] |USBDSEL |USB Device Clock Source Selection (Write Protect)
|
||||
* | | |These bits are protected bit. It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
|
||||
* | | |0 = Clock source from HIRC.
|
||||
* | | |1 = Clock source from PLL divided. (M031_E/M032_E only)
|
||||
* | | | = Clock source from HIRC. (M031_D/C/B only)
|
||||
* @var CLK_T::CLKSEL1
|
||||
* Offset: 0x14 Clock Source Select Control Register 1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect)
|
||||
* | | |00 = Reserved.
|
||||
* | | |01 = Clock source from external low speed crystal oscillator (LXT).
|
||||
* | | |10 = Clock source from HCLK/2048.
|
||||
* | | |11 = Clock source from internal low speed RC oscillator (LIRC).
|
||||
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* | | |Note2: Will be forced to 11 when CONFIG0[31], CONFIG0[4], CONFIG0[3] are all ones.
|
||||
* |[3:2] |WWDTSEL |Window Watchdog Timer Clock Source Selection (Write Protect)
|
||||
* | | |10 = Clock source from HCLK/2048.
|
||||
* | | |11 = Clock source from internal low speed RC oscillator (LIRC).
|
||||
* | | |Others = Reserved.
|
||||
* |[6:4] |CLKOSEL |Clock Divider Clock Source Selection
|
||||
* | | |000 = Clock source from external high speed crystal oscillator (HXT).
|
||||
* | | |001 = Clock source from external low speed crystal oscillator (LXT).
|
||||
* | | |010 = Clock source from HCLK.
|
||||
* | | |011 = Clock source from internal high speed RC oscillator (HIRC).
|
||||
* | | |100 = Clock source from internal low speed RC oscillator (LIRC).
|
||||
* | | |101 = Clock source from internal high speed RC oscillator (HIRC).
|
||||
* | | |110 = Clock source from PLL. (M031_E/D only).
|
||||
* | | | = Clock source from internal high speed RC oscillator (HIRC). (M031_C/B only).
|
||||
* |[10:8] |TMR0SEL |TIMER0 Clock Source Selection
|
||||
* | | |000 = Clock source from external high speed crystal oscillator (HXT).
|
||||
* | | |001 = Clock source from external low speed crystal oscillator (LXT).
|
||||
* | | |010 = Clock source from PCLK0.
|
||||
* | | |011 = Clock source from external clock T0 pin.
|
||||
* | | |101 = Clock source from internal low speed RC oscillator (LIRC).
|
||||
* | | |111 = Clock source from internal high speed RC oscillator (HIRC).
|
||||
* | | |Others = Reserved.
|
||||
* |[14:12] |TMR1SEL |TIMER1 Clock Source Selection
|
||||
* | | |000 = Clock source from external high speed crystal oscillator (HXT).
|
||||
* | | |001 = Clock source from external low speed crystal oscillator (LXT).
|
||||
* | | |010 = Clock source from PCLK0.
|
||||
* | | |011 = Clock source from external clock T1 pin.
|
||||
* | | |101 = Clock source from internal low speed RC oscillator (LIRC).
|
||||
* | | |111 = Clock source from internal high speed RC oscillator (HIRC).
|
||||
* | | |Others = Reserved.
|
||||
* |[18:16] |TMR2SEL |TIMER2 Clock Source Selection
|
||||
* | | |000 = Clock source from external high speed crystal oscillator (HXT).
|
||||
* | | |001 = Clock source from external low speed crystal oscillator (LXT).
|
||||
* | | |010 = Clock source from PCLK1.
|
||||
* | | |011 = Clock source from external clock T2 pin.
|
||||
* | | |101 = Clock source from internal low speed RC oscillator (LIRC).
|
||||
* | | |111 = Clock source from internal high speed RC oscillator (HIRC).
|
||||
* | | |Others = Reserved.
|
||||
* |[22:20] |TMR3SEL |TIMER3 Clock Source Selection
|
||||
* | | |000 = Clock source from external high speed crystal oscillator (HXT).
|
||||
* | | |001 = Clock source from external low speed crystal oscillator (LXT).
|
||||
* | | |010 = Clock source from PCLK1.
|
||||
* | | |011 = Clock source from external clock T3 pin.
|
||||
* | | |101 = Clock source from internal low speed RC oscillator (LIRC).
|
||||
* | | |111 = Clock source from internal high speed RC oscillator (HIRC).
|
||||
* | | |Others = Reserved.
|
||||
* |[26:24] |UART0SEL |UART0 Clock Source Selection
|
||||
* | | |000 = Clock source from external high speed crystal oscillator (HXT).
|
||||
* | | |001 = Clock source from PLL. (M031_E/D only)
|
||||
* | | | = Clock source from PCLK0. (M031_C/B only).
|
||||
* | | |010 = Clock source from external low speed crystal oscillator (LXT).
|
||||
* | | |011 = Clock source from internal high speed RC oscillator (HIRC).
|
||||
* | | |100 = Clock source from PCLK0.
|
||||
* | | |Other = Reserved.
|
||||
* |[30:28] |UART1SEL |UART1 Clock Source Selection
|
||||
* | | |000 = Clock source from external high speed crystal oscillator (HXT).
|
||||
* | | |001 = Clock source from PLL. (M031_E/D only)
|
||||
* | | | = Clock source from PCLK1. (M031_C/B only).
|
||||
* | | |010 = Clock source from external low speed crystal oscillator (LXT).
|
||||
* | | |011 = Clock source from internal high speed RC oscillator (HIRC).
|
||||
* | | |100 = Clock source from PCLK1.
|
||||
* | | |Other = Reserved.
|
||||
* @var CLK_T::CLKSEL2
|
||||
* Offset: 0x18 Clock Source Select Control Register 2
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |PWM0SEL |PWM0 Clock Source Selection
|
||||
* | | |The peripheral clock source of PWM0 is defined by PWM0SEL.
|
||||
* | | |0 = Clock source from PLL. (M031_E/D only)
|
||||
* | | | = Clock source from PCLK0. (M031_C/B only).
|
||||
* | | |1 = Clock source from PCLK0.
|
||||
* |[1] |PWM1SEL |PWM1 Clock Source Selection
|
||||
* | | |The peripheral clock source of PWM1 is defined by PWM1SEL.
|
||||
* | | |0 = Clock source from PLL. (M031_E/D only)
|
||||
* | | | = Clock source from PCLK1. (M031_C/B only).
|
||||
* | | |1 = Clock source from PCLK1.
|
||||
* |[5:4] |SPI0SEL |SPI0 Clock Source Selection
|
||||
* | | |00 = Clock source from external high speed crystal oscillator (HXT).
|
||||
* | | |01 = Clock source from PLL. (M031_E/D only)
|
||||
* | | | = Clock source from PCLK1. (M031_C/B only).
|
||||
* | | |10 = Clock source from PCLK1.
|
||||
* | | |11 = Clock source from internal high speed RC oscillator (HIRC).
|
||||
* |[21:20] |ADCSEL |ADC Clock Source Selection
|
||||
* | | |00 = Clock source from external high speed crystal oscillator (HXT) clock.
|
||||
* | | |01 = Clock source from PLL. (M031_E/D only)
|
||||
* | | | = Clock source from PCLK1. (M031_C/B only).
|
||||
* | | |10 = Clock source from PCLK1.
|
||||
* | | |11 = Clock source from internal high speed RC oscillator (HIRC) clock.
|
||||
* @var CLK_T::CLKSEL3
|
||||
* Offset: 0x1C Clock Source Select Control Register 3
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[26:24] |UART2SEL |UART2 Clock Source Selection
|
||||
* | | |000 = Clock source from external high speed crystal oscillator (HXT).
|
||||
* | | |001 = Clock source from PLL. (M031_E/D only)
|
||||
* | | | = Clock source from PCLK0. (M031_C/B only).
|
||||
* | | |010 = Clock source from external low speed crystal oscillator (LXT).
|
||||
* | | |011 = Clock source from internal high speed RC oscillator (HIRC).
|
||||
* | | |100 = Clock source from PCLK0.
|
||||
* | | |Other = Reserved.
|
||||
* @var CLK_T::CLKDIV0
|
||||
* Offset: 0x20 Clock Divider Number Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source
|
||||
* | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
|
||||
* |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock
|
||||
* | | |USB clock frequency = (PLL frequency) / (USBDIV + 1).
|
||||
* |[11:8] |UART0DIV |UART0 Clock Divide Number From UART0 Clock Source
|
||||
* | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1).
|
||||
* |[15:12] |UART1DIV |UART1 Clock Divide Number From UART1 Clock Source
|
||||
* | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1).
|
||||
* |[23:16] |ADCDIV |ADC Clock Divide Number From ADC Clock Source
|
||||
* | | |ADC clock frequency = (ADC clock source frequency) / (ADCDIV + 1).
|
||||
* @var CLK_T::CLKDIV4
|
||||
* Offset: 0x30 Clock Divider Number Register 4
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |UART2DIV |UART2 Clock Divide Number From UART2 Clock Source
|
||||
* | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1).
|
||||
* @var CLK_T::PCLKDIV
|
||||
* Offset: 0x34 APB Clock Divider Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[2:0] |APB0DIV |APB0 Clock DIvider
|
||||
* | | |APB0 clock can be divided from HCLK.
|
||||
* | | |000 = PCLK0 = HCLK.
|
||||
* | | |001 = PCLK0 = 1/2 HCLK.
|
||||
* | | |010 = PCLK0 = 1/4 HCLK.
|
||||
* | | |011 = PCLK0 = 1/8 HCLK.
|
||||
* | | |100 = PCLK0 = 1/16 HCLK.
|
||||
* | | |Others = Reserved.
|
||||
* |[6:4] |APB1DIV |APB1 Clock DIvider
|
||||
* | | |APB1 clock can be divided from HCLK.
|
||||
* | | |000 = PCLK1 = HCLK.
|
||||
* | | |001 = PCLK1 = 1/2 HCLK.
|
||||
* | | |010 = PCLK1 = 1/4 HCLK.
|
||||
* | | |011 = PCLK1 = 1/8 HCLK.
|
||||
* | | |100 = PCLK1 = 1/16 HCLK.
|
||||
* | | |Others = Reserved.
|
||||
* @var CLK_T::PLLCTL
|
||||
* Offset: 0x40 PLL Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect)
|
||||
* | | |Refer to the formulas below the table.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[13:9] |INDIV |PLL Input Divider Control (Write Protect)
|
||||
* | | |Refer to the formulas below the table.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect)
|
||||
* | | |Refer to the formulas below the table.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[16] |PD |Power-down Mode (Write Protect)
|
||||
* | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
|
||||
* | | |0 = PLL is in normal mode.
|
||||
* | | |1 = PLL is in Power-down mode (default).
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[17] |BP |PLL Bypass Control (Write Protect)
|
||||
* | | |0 = PLL is in normal mode (default).
|
||||
* | | |1 = PLL clock output is same as PLL input clock FIN.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect)
|
||||
* | | |0 = PLL FOUT Enabled.
|
||||
* | | |1 = PLL FOUT is fixed low.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[19] |PLLSRC |PLL Source Clock Selection (Write Protect)
|
||||
* | | |0 = PLL source clock from external high-speed crystal oscillator (HXT).
|
||||
* | | |1 = PLL source clock from 48 MHz internal high-speed oscillator (HIRC/4).
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[23] |STBSEL |PLL Stable Counter Selection (Write Protect)
|
||||
* | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz).
|
||||
* | | |1 = PLL stable time is 16128 PLL source clock (suitable for source clock is larger than 12 MHz).
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* @var CLK_T::STATUS
|
||||
* Offset: 0x50 Clock Status Monitor Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only)
|
||||
* | | |0 = External high speed crystal oscillator (HXT) clock is not stable or disabled.
|
||||
* | | |1 = External high speed crystal oscillator (HXT) clock is stable and enabled.
|
||||
* |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only)
|
||||
* | | |0 = External low speed crystal oscillator (LXT) clock is not stable or disabled.
|
||||
* | | |1 = External low speed crystal oscillator (LXT) clock is stabled and enabled.
|
||||
* |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only)
|
||||
* | | |0 = Internal PLL clock is not stable or disabled.
|
||||
* | | |1 = Internal PLL clock is stable and enabled.
|
||||
* | | |Reserved. (M031_C/B only)
|
||||
* |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only)
|
||||
* | | |0 = Internal low speed RC oscillator (LIRC) clock is not stable or disabled.
|
||||
* | | |1 = Internal low speed RC oscillator (LIRC) clock is stable and enabled.
|
||||
* |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only)
|
||||
* | | |0 = Internal high speed RC oscillator (HIRC) clock is not stable or disabled.
|
||||
* | | |1 = Internal high speed RC oscillator (HIRC) clock is stable and enabled.
|
||||
* |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only)
|
||||
* | | |This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.
|
||||
* | | |0 = Clock switching success.
|
||||
* | | |1 = Clock switching failure.
|
||||
* | | |Note: Write 1 to clear the bit to 0.
|
||||
* @var CLK_T::CLKOCTL
|
||||
* Offset: 0x60 Clock Output Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |FREQSEL |Clock Output Frequency Selection
|
||||
* | | |The formula of output frequency is
|
||||
* | | |Fout = Fin/(2^(N+1)).
|
||||
* | | |Fin is the input clock frequency.
|
||||
* | | |Fout is the frequency of divider output clock.
|
||||
* | | |N is the 4-bit value of FREQSEL[3:0].
|
||||
* |[4] |CLKOEN |Clock Output Enable Bit
|
||||
* | | |0 = Clock Output function Disabled.
|
||||
* | | |1 = Clock Output function Enabled.
|
||||
* |[5] |DIV1EN |Clock Output Divide One Enable Bit
|
||||
* | | |0 = Clock Output will output clock with source frequency divided by FREQSEL.
|
||||
* | | |1 = Clock Output will output clock with source frequency.
|
||||
* @var CLK_T::CLKDCTL
|
||||
* Offset: 0x70 Clock Fail Detector Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit
|
||||
* | | |0 = External high speed crystal oscillator (HXT) clock fail detector Disabled.
|
||||
* | | |1 = External high speed crystal oscillator (HXT) clock fail detector Enabled.
|
||||
* |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit
|
||||
* | | |0 = External high speed crystal oscillator (HXT) clock fail interrupt Disabled.
|
||||
* | | |1 = External high speed crystal oscillator (HXT) clock fail interrupt Enabled.
|
||||
* |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit
|
||||
* | | |0 = External low speed crystal oscillator (LXT) clock fail detector Disabled.
|
||||
* | | |1 = External low speed crystal oscillator (LXT) clock fail detector Enabled.
|
||||
* |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit
|
||||
* | | |0 = External low speed crystal oscillator (LXT) clock fail interrupt Disabled.
|
||||
* | | |1 = External low speed crystal oscillator (LXT) clock fail interrupt Enabled.
|
||||
* |[16] |HXTFQDEN |HXT Clock Frequency Range Detector Enable Bit
|
||||
* | | |0 = External high speed crystal oscillator (HXT) clock frequency range detector Disabled.
|
||||
* | | |1 = External high speed crystal oscillator (HXT) clock frequency range detector Enabled.
|
||||
* |[17] |HXTFQIEN |HXT Clock Frequency Range Detector Interrupt Enable Bit
|
||||
* | | |0 = External high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled.
|
||||
* | | |1 = External high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled.
|
||||
* @var CLK_T::CLKDSTS
|
||||
* Offset: 0x74 Clock Fail Detector Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |HXTFIF |HXT Clock Fail Interrupt Flag (Write Protect)
|
||||
* | | |0 = External high speed crystal oscillator (HXT) clock is normal.
|
||||
* | | |1 = External high speed crystal oscillator (HXT) clock stops.
|
||||
* | | |Note: Write 1 to clear the bit to 0.
|
||||
* |[1] |LXTFIF |LXT Clock Fail Interrupt Flag (Write Protect)
|
||||
* | | |0 = External low speed crystal oscillator (LXT) clock is normal.
|
||||
* | | |1 = External low speed crystal oscillator (LXT) stops.
|
||||
* | | |Note: Write 1 to clear the bit to 0.
|
||||
* |[8] |HXTFQIF |HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)
|
||||
* | | |0 = External high speed crystal oscillator (HXT) clock frequency is normal.
|
||||
* | | |1 = External high speed crystal oscillator (HXT) clock frequency is abnormal.
|
||||
* | | |Note: Write 1 to clear the bit to 0.
|
||||
* @var CLK_T::CDUPB
|
||||
* Offset: 0x78 Clock Frequency Range Detector Upper Boundary Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[9:0] |UPERBD |HXT Clock Frequency Range Detector Upper Boundary Value
|
||||
* | | |The bits define the maximum value of frequency range detector window.
|
||||
* | | |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
|
||||
* @var CLK_T::CDLOWB
|
||||
* Offset: 0x7C Clock Frequency Range Detector Lower Boundary Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[9:0] |LOWERBD |HXT Clock Frequency Range Detector Lower Boundary Value
|
||||
* | | |The bits define the minimum value of frequency range detector window.
|
||||
* | | |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
|
||||
* @var CLK_T::HXTFSEL
|
||||
* Offset: 0xB4 HXT Filter Select Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |HXTFSEL |HXT Filter Select
|
||||
* | | |0 = HXT frequency is > 12MHz.
|
||||
* | | |1 = HXT frequency is <= 12MHz.
|
||||
* | | |Note: This bit should not be changed during HXT is running.
|
||||
*/
|
||||
__IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */
|
||||
__IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */
|
||||
__IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */
|
||||
__IO uint32_t APBCLK1; /*!< [0x000c] APB Devices Clock Enable Control Register 1 */
|
||||
__IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */
|
||||
__IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */
|
||||
__IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */
|
||||
__IO uint32_t CLKSEL3; /*!< [0x001c] Clock Source Select Control Register 3 */
|
||||
__IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */
|
||||
__I uint32_t RESERVE0[3];
|
||||
__IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */
|
||||
__IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */
|
||||
__I uint32_t RESERVE1[2];
|
||||
__IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */
|
||||
__I uint32_t RESERVE2[3];
|
||||
__I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */
|
||||
__I uint32_t RESERVE3[3];
|
||||
__IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */
|
||||
__I uint32_t RESERVE4[3];
|
||||
__IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */
|
||||
__IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */
|
||||
__IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register */
|
||||
__IO uint32_t CDLOWB; /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register */
|
||||
__IO uint32_t LDOCTL; /*!< [0x0080] LDO Control Register */
|
||||
__I uint32_t RESERVE5[12];
|
||||
__IO uint32_t HXTFSEL; /*!< [0x00b4] HXT Filter Select Control Register */
|
||||
__I uint32_t RESERVE9[14];
|
||||
__IO uint32_t TESTCLK; /*!< [0x00f0] Test Clock Control Register */
|
||||
|
||||
} CLK_T;
|
||||
|
||||
/**
|
||||
@addtogroup CLK_CONST CLK Bit Field Definition
|
||||
Constant Definitions for CLK Controller
|
||||
@{ */
|
||||
|
||||
#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */
|
||||
#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */
|
||||
|
||||
#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */
|
||||
#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */
|
||||
|
||||
#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */
|
||||
#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */
|
||||
|
||||
#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */
|
||||
#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */
|
||||
|
||||
#define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */
|
||||
#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */
|
||||
|
||||
#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */
|
||||
#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */
|
||||
|
||||
#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */
|
||||
#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */
|
||||
|
||||
#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */
|
||||
#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */
|
||||
|
||||
#define CLK_PWRCTL_DBPDEN_Pos (9) /*!< CLK_T::PWRCTL: DBPDEN Position */
|
||||
#define CLK_PWRCTL_DBPDEN_Msk (0x1ul << CLK_PWRCTL_DBPDEN_Pos) /*!< CLK_T::PWRCTL: DBPDEN Mask */
|
||||
|
||||
#define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */
|
||||
#define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */
|
||||
|
||||
#define CLK_PWRCTL_HIRCSTBS_Pos (16) /*!< CLK_T::PWRCTL: HIRCSTBS Position */
|
||||
#define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos) /*!< CLK_T::PWRCTL: HIRCSTBS Mask */
|
||||
|
||||
#define CLK_PWRCTL_HXTGAIN_Pos (20) /*!< CLK_T::PWRCTL: HXTGAIN Position */
|
||||
#define CLK_PWRCTL_HXTGAIN_Msk (0x7ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */
|
||||
|
||||
#define CLK_PWRCTL_LXTSELXT_Pos (24) /*!< CLK_T::PWRCTL: LXTSELXT Position */
|
||||
#define CLK_PWRCTL_LXTSELXT_Msk (0x1ul << CLK_PWRCTL_LXTSELXT_Pos) /*!< CLK_T::PWRCTL: LXTSELXT Mask */
|
||||
|
||||
#define CLK_PWRCTL_LXTGAIN_Pos (25) /*!< CLK_T::PWRCTL: LXTGAIN Position */
|
||||
#define CLK_PWRCTL_LXTGAIN_Msk (0x3ul << CLK_PWRCTL_LXTGAIN_Pos) /*!< CLK_T::PWRCTL: LXTGAIN Mask */
|
||||
|
||||
#define CLK_PWRCTL_LXTSTBS_Pos (30) /*!< CLK_T::PWRCTL: LXTSTBS Position */
|
||||
#define CLK_PWRCTL_LXTSTBS_Msk (0x1ul << CLK_PWRCTL_LXTSTBS_Pos) /*!< CLK_T::PWRCTL: LXTSTBS Mask */
|
||||
|
||||
#define CLK_PWRCTL_LXTTBEN_Pos (31) /*!< CLK_T::PWRCTL: LXTTBEN Position */
|
||||
#define CLK_PWRCTL_LXTTBEN_Msk (0x1ul << CLK_PWRCTL_LXTTBEN_Pos) /*!< CLK_T::PWRCTL: LXTTBEN Mask */
|
||||
|
||||
#define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */
|
||||
#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */
|
||||
|
||||
#define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */
|
||||
#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */
|
||||
|
||||
#define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */
|
||||
#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */
|
||||
|
||||
#define CLK_AHBCLK_HDIVCKEN_Pos (4) /*!< CLK_T::AHBCLK: HDIVCKEN Position */
|
||||
#define CLK_AHBCLK_HDIVCKEN_Msk (0x1ul << CLK_AHBCLK_HDIVCKEN_Pos) /*!< CLK_T::AHBCLK: HDIVCKEN Mask */
|
||||
|
||||
#define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */
|
||||
#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */
|
||||
|
||||
#define CLK_AHBCLK_SRAM0IDLE_Pos (20) /*!< CLK_T::AHBCLK: SRAM0IDLE Position */
|
||||
#define CLK_AHBCLK_SRAM0IDLE_Msk (0x1ul << CLK_AHBCLK_SRAM0IDLE_Pos) /*!< CLK_T::AHBCLK: SRAM0IDLE Mask */
|
||||
|
||||
#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */
|
||||
#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */
|
||||
#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */
|
||||
#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */
|
||||
#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */
|
||||
#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */
|
||||
#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */
|
||||
#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */
|
||||
#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */
|
||||
#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */
|
||||
#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */
|
||||
#define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */
|
||||
#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */
|
||||
#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */
|
||||
#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */
|
||||
#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */
|
||||
#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */
|
||||
#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */
|
||||
#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_UART6CKEN_Pos (22) /*!< CLK_T::APBCLK0: UART6CKEN Position */
|
||||
#define CLK_APBCLK0_UART6CKEN_Msk (0x1ul << CLK_APBCLK0_UART6CKEN_Pos) /*!< CLK_T::APBCLK0: UART6CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_UART7CKEN_Pos (23) /*!< CLK_T::APBCLK0: UART7CKEN Position */
|
||||
#define CLK_APBCLK0_UART7CKEN_Msk (0x1ul << CLK_APBCLK0_UART7CKEN_Pos) /*!< CLK_T::APBCLK0: UART7CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */
|
||||
#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */
|
||||
|
||||
#define CLK_APBCLK0_ADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: ADCCKEN Position */
|
||||
#define CLK_APBCLK0_ADCCKEN_Msk (0x1ul << CLK_APBCLK0_ADCCKEN_Pos) /*!< CLK_T::APBCLK0: ADCCKEN Mask */
|
||||
|
||||
#define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */
|
||||
#define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */
|
||||
#define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK1_PWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: PWM0CKEN Position */
|
||||
#define CLK_APBCLK1_PWM0CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CKEN_Pos) /*!< CLK_T::APBCLK1: PWM0CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK1_PWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: PWM1CKEN Position */
|
||||
#define CLK_APBCLK1_PWM1CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CKEN_Pos) /*!< CLK_T::APBCLK1: PWM1CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */
|
||||
#define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */
|
||||
|
||||
#define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */
|
||||
#define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */
|
||||
|
||||
#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */
|
||||
#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */
|
||||
|
||||
#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */
|
||||
#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */
|
||||
|
||||
#define CLK_CLKSEL0_USBDSEL_Pos (8) /*!< CLK_T::CLKSEL0: USBDSEL Position */
|
||||
#define CLK_CLKSEL0_USBDSEL_Msk (0x1ul << CLK_CLKSEL0_USBDSEL_Pos) /*!< CLK_T::CLKSEL0: USBDSEL Mask */
|
||||
|
||||
#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */
|
||||
#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */
|
||||
|
||||
#define CLK_CLKSEL1_WWDTSEL_Pos (2) /*!< CLK_T::CLKSEL1: WWDTSEL Position */
|
||||
#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */
|
||||
|
||||
#define CLK_CLKSEL1_CLKOSEL_Pos (4) /*!< CLK_T::CLKSEL1: CLKOSEL Position */
|
||||
#define CLK_CLKSEL1_CLKOSEL_Msk (0x7ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */
|
||||
|
||||
#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */
|
||||
#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */
|
||||
#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */
|
||||
#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */
|
||||
#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */
|
||||
#define CLK_CLKSEL1_UART0SEL_Msk (0x7ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL1_UART1SEL_Pos (28) /*!< CLK_T::CLKSEL1: UART1SEL Position */
|
||||
#define CLK_CLKSEL1_UART1SEL_Msk (0x7ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL2_PWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: PWM0SEL Position */
|
||||
#define CLK_CLKSEL2_PWM0SEL_Msk (0x1ul << CLK_CLKSEL2_PWM0SEL_Pos) /*!< CLK_T::CLKSEL2: PWM0SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL2_PWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: PWM1SEL Position */
|
||||
#define CLK_CLKSEL2_PWM1SEL_Msk (0x1ul << CLK_CLKSEL2_PWM1SEL_Pos) /*!< CLK_T::CLKSEL2: PWM1SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */
|
||||
#define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */
|
||||
#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */
|
||||
#define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */
|
||||
#define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL2_ADCSEL_Pos (20) /*!< CLK_T::CLKSEL2: ADCSEL Position */
|
||||
#define CLK_CLKSEL2_ADCSEL_Msk (0x3ul << CLK_CLKSEL2_ADCSEL_Pos) /*!< CLK_T::CLKSEL2: ADCSEL Mask */
|
||||
|
||||
#define CLK_CLKSEL3_UART6SEL_Pos (8) /*!< CLK_T::CLKSEL63: UART6SEL Position */
|
||||
#define CLK_CLKSEL3_UART6SEL_Msk (0x7ul << CLK_CLKSEL3_UART6SEL_Pos) /*!< CLK_T::CLKSEL3: UART6SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL3_UART7SEL_Pos (12) /*!< CLK_T::CLKSEL3: UART7SEL Position */
|
||||
#define CLK_CLKSEL3_UART7SEL_Msk (0x7ul << CLK_CLKSEL3_UART7SEL_Pos) /*!< CLK_T::CLKSEL3: UART7SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL3_UART4SEL_Pos (16) /*!< CLK_T::CLKSEL3: UART4SEL Position */
|
||||
#define CLK_CLKSEL3_UART4SEL_Msk (0x7ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL3_UART5SEL_Pos (20) /*!< CLK_T::CLKSEL3: UART5SEL Position */
|
||||
#define CLK_CLKSEL3_UART5SEL_Msk (0x7ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */
|
||||
#define CLK_CLKSEL3_UART2SEL_Msk (0x7ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */
|
||||
|
||||
#define CLK_CLKSEL3_UART3SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART3SEL Position */
|
||||
#define CLK_CLKSEL3_UART3SEL_Msk (0x7ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */
|
||||
|
||||
#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */
|
||||
#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */
|
||||
|
||||
#define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */
|
||||
#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */
|
||||
|
||||
#define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */
|
||||
#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */
|
||||
|
||||
#define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */
|
||||
#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */
|
||||
|
||||
#define CLK_CLKDIV0_ADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: ADCDIV Position */
|
||||
#define CLK_CLKDIV0_ADCDIV_Msk (0xfful << CLK_CLKDIV0_ADCDIV_Pos) /*!< CLK_T::CLKDIV0: ADCDIV Mask */
|
||||
|
||||
#define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */
|
||||
#define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */
|
||||
|
||||
#define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */
|
||||
#define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */
|
||||
|
||||
#define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */
|
||||
#define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */
|
||||
|
||||
#define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */
|
||||
#define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */
|
||||
|
||||
#define CLK_CLKDIV4_UART6DIV_Pos (16) /*!< CLK_T::CLKDIV4: UART6DIV Position */
|
||||
#define CLK_CLKDIV4_UART6DIV_Msk (0xful << CLK_CLKDIV4_UART6DIV_Pos) /*!< CLK_T::CLKDIV4: UART6DIV Mask */
|
||||
|
||||
#define CLK_CLKDIV4_UART7DIV_Pos (20) /*!< CLK_T::CLKDIV4: UART7DIV Position */
|
||||
#define CLK_CLKDIV4_UART7DIV_Msk (0xful << CLK_CLKDIV4_UART7DIV_Pos) /*!< CLK_T::CLKDIV4: UART7DIV Mask */
|
||||
|
||||
#define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */
|
||||
#define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */
|
||||
|
||||
#define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */
|
||||
#define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */
|
||||
|
||||
#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */
|
||||
#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */
|
||||
|
||||
#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */
|
||||
#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */
|
||||
|
||||
#define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */
|
||||
#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */
|
||||
|
||||
#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */
|
||||
#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */
|
||||
|
||||
#define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */
|
||||
#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */
|
||||
|
||||
#define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */
|
||||
#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */
|
||||
|
||||
#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */
|
||||
#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */
|
||||
|
||||
#define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */
|
||||
#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */
|
||||
|
||||
#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */
|
||||
#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */
|
||||
|
||||
#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */
|
||||
#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */
|
||||
|
||||
#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */
|
||||
#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */
|
||||
|
||||
#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */
|
||||
#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */
|
||||
|
||||
#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */
|
||||
#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */
|
||||
|
||||
#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */
|
||||
#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */
|
||||
|
||||
#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */
|
||||
#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */
|
||||
|
||||
#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */
|
||||
#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */
|
||||
|
||||
#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */
|
||||
#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */
|
||||
|
||||
#define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */
|
||||
#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */
|
||||
|
||||
#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */
|
||||
#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */
|
||||
|
||||
#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */
|
||||
#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */
|
||||
|
||||
#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */
|
||||
#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */
|
||||
|
||||
#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */
|
||||
#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */
|
||||
|
||||
#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */
|
||||
#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */
|
||||
|
||||
#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */
|
||||
#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */
|
||||
|
||||
#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */
|
||||
#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */
|
||||
|
||||
#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */
|
||||
#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */
|
||||
|
||||
#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */
|
||||
#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */
|
||||
|
||||
#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */
|
||||
#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */
|
||||
|
||||
#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */
|
||||
#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */
|
||||
|
||||
#define CLK_HXTFSEL_HXTFSEL_Pos (0) /*!< CLK_T::HXTFSEL: HXTFSEL Position */
|
||||
#define CLK_HXTFSEL_HXTFSEL_Msk (0x1ul << CLK_HXTFSEL_HXTFSEL_Pos) /*!< CLK_T::HXTFSEL: HXTFSEL Mask */
|
||||
|
||||
/**@}*/ /* CLK_CONST */
|
||||
/**@}*/ /* end of CLK register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __CLK_REG_H__ */
|
||||
|
|
@ -1,151 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file crc_reg.h
|
||||
* @version V1.00
|
||||
* @brief CRC register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __CRC_REG_H__
|
||||
#define __CRC_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup CRC Cyclic Redundancy Check Controller(CRC)
|
||||
Memory Mapped Structure for CRC Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var CRC_T::CTL
|
||||
* Offset: 0x00 CRC Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CRCEN |CRC Channel Enable Bit
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = CRC operation Enabled.
|
||||
* |[1] |CHKSINIT |Checksum Initialization
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value.
|
||||
* | | |Note: This bit will be cleared automatically.
|
||||
* |[24] |DATREV |Write Data Bit Order Reverse
|
||||
* | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
|
||||
* | | |0 = Bit order reversed for CRC write data in Disabled.
|
||||
* | | |1 = Bit order reversed for CRC write data in Enabled (per byte).
|
||||
* | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
|
||||
* |[25] |CHKSREV |Checksum Bit Order Reverse
|
||||
* | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
|
||||
* | | |0 = Bit order reverse for CRC checksum Disabled.
|
||||
* | | |1 = Bit order reverse for CRC checksum Enabled.
|
||||
* | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
|
||||
* |[26] |DATFMT |Write Data 1's Complement
|
||||
* | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
|
||||
* | | |0 = 1's complement for CRC writes data in Disabled.
|
||||
* | | |1 = 1's complement for CRC writes data in Enabled.
|
||||
* |[27] |CHKSFMT |Checksum 1's Complement
|
||||
* | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
|
||||
* | | |0 = 1's complement for CRC checksum Disabled.
|
||||
* | | |1 = 1's complement for CRC checksum Enabled.
|
||||
* |[29:28] |DATLEN |CPU Write Data Length
|
||||
* | | |This field indicates the write data length.
|
||||
* | | |00 = Data length is 8-bit mode.
|
||||
* | | |01 = Data length is 16-bit mode.
|
||||
* | | |1x = Data length is 32-bit mode.
|
||||
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
|
||||
* |[31:30] |CRCMODE |CRC Polynomial Mode
|
||||
* | | |This field indicates the CRC operation polynomial mode.
|
||||
* | | |00 = CRC-CCITT Polynomial mode.
|
||||
* | | |01 = CRC-8 Polynomial mode.
|
||||
* | | |10 = CRC-16 Polynomial mode.
|
||||
* | | |11 = CRC-32 Polynomial mode.
|
||||
* @var CRC_T::DAT
|
||||
* Offset: 0x04 CRC Write Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |DATA |CRC Write Data Bits
|
||||
* | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
|
||||
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
|
||||
* @var CRC_T::SEED
|
||||
* Offset: 0x08 CRC Seed Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |SEED |CRC Seed Value
|
||||
* | | |This field indicates the CRC seed value.
|
||||
* | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
|
||||
* @var CRC_T::CHECKSUM
|
||||
* Offset: 0x0C CRC Checksum Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |CHECKSUM |CRC Checksum Results
|
||||
* | | |This field indicates the CRC checksum result.
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] CRC Control Register */
|
||||
__IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */
|
||||
__IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */
|
||||
__I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */
|
||||
|
||||
} CRC_T;
|
||||
|
||||
/**
|
||||
@addtogroup CRC_CONST CRC Bit Field Definition
|
||||
Constant Definitions for CRC Controller
|
||||
@{ */
|
||||
|
||||
|
||||
#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
|
||||
#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
|
||||
|
||||
#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */
|
||||
#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */
|
||||
|
||||
#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
|
||||
#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
|
||||
|
||||
#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
|
||||
#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
|
||||
|
||||
#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
|
||||
#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
|
||||
|
||||
#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
|
||||
#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
|
||||
|
||||
#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
|
||||
#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
|
||||
|
||||
#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
|
||||
#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
|
||||
|
||||
#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
|
||||
#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
|
||||
|
||||
#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
|
||||
#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
|
||||
|
||||
#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
|
||||
#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
|
||||
|
||||
/**@}*/ /* CRC_CONST */
|
||||
/**@}*/ /* end of CRC register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __CRC_REG_H__ */
|
||||
|
|
@ -1,224 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file ebi_reg.h
|
||||
* @version V1.00
|
||||
* @brief EBI register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __EBI_REG_H__
|
||||
#define __EBI_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup EBI External Bus Interface Controller(EBI)
|
||||
Memory Mapped Structure for EBI Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var EBI_T::CTL0
|
||||
* Offset: 0x00 External Bus Interface Bank0 Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |EN |EBI Enable Bit
|
||||
* | | |This bit is the functional enable bit for EBI.
|
||||
* | | |0 = EBI function Disabled.
|
||||
* | | |1 = EBI function Enabled.
|
||||
* |[1] |DW16 |EBI Data Width 16-bit Select
|
||||
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
|
||||
* | | |0 = EBI data width is 8-bit.
|
||||
* | | |1 = EBI data width is 16-bit.
|
||||
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
|
||||
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
|
||||
* | | |0 = Chip select pin (EBI_nCS) is active low.
|
||||
* | | |1 = Chip select pin (EBI_nCS) is active high.
|
||||
* |[4] |CACCESS |Continuous Data Access Mode
|
||||
* | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
|
||||
* | | |0 = Continuous data access mode Disabled.
|
||||
* | | |1 = Continuous data access mode Enabled.
|
||||
* |[10:8] |MCLKDIV |External Output Clock Divider
|
||||
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
|
||||
* | | |000 = HCLK/1.
|
||||
* | | |001 = HCLK/2.
|
||||
* | | |010 = HCLK/4.
|
||||
* | | |011 = HCLK/8.
|
||||
* | | |100 = HCLK/16.
|
||||
* | | |101 = HCLK/32.
|
||||
* | | |110 = HCLK/64.
|
||||
* | | |111 = HCLK/128.
|
||||
* |[18:16] |TALE |Extend Time Of of ALE
|
||||
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
|
||||
* | | |tALE = (TALE + 1)*EBI_MCLK.
|
||||
* | | |Note: This field only available in EBI_CTL0 register.
|
||||
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
|
||||
* | | |0 = EBI write buffer Disabled.
|
||||
* | | |1 = EBI write buffer Enabled.
|
||||
* | | |Note: This bit only available in EBI_CTL0 register.
|
||||
* @var EBI_T::TCTL0
|
||||
* Offset: 0x04 External Bus Interface Bank0 Timing Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:3] |TACC |EBI Data Access Time
|
||||
* | | |TACC define data access time (tACC).
|
||||
* | | |tACC = (TACC + 1) * EBI_MCLK.
|
||||
* |[10:8] |TAHD |EBI Data Access Hold Time
|
||||
* | | |TAHD define data access hold time (tAHD).
|
||||
* | | |tAHD = (TAHD + 1) * EBI_MCLK.
|
||||
* |[15:12] |W2X |Idle Cycle After Write
|
||||
* | | |This field defines the number of W2X idle cycle.
|
||||
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* | | |W2X idle cycle = (W2X * EBI_MCLK).
|
||||
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
|
||||
* | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
|
||||
* | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
|
||||
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
|
||||
* | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
|
||||
* | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
|
||||
* |[27:24] |R2R |Idle Cycle Between Read-to-read
|
||||
* | | |This field defines the number of R2R idle cycle.
|
||||
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* | | |R2R idle cycle = (R2R * EBI_MCLK).
|
||||
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* @var EBI_T::CTL1
|
||||
* Offset: 0x10 External Bus Interface Bank1 Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |EN |EBI Enable Bit
|
||||
* | | |This bit is the functional enable bit for EBI.
|
||||
* | | |0 = EBI function Disabled.
|
||||
* | | |1 = EBI function Enabled.
|
||||
* |[1] |DW16 |EBI Data Width 16-bit Select
|
||||
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
|
||||
* | | |0 = EBI data width is 8-bit.
|
||||
* | | |1 = EBI data width is 16-bit.
|
||||
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
|
||||
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
|
||||
* | | |0 = Chip select pin (EBI_nCS) is active low.
|
||||
* | | |1 = Chip select pin (EBI_nCS) is active high.
|
||||
* |[4] |CACCESS |Continuous Data Access Mode
|
||||
* | | |When con ttinuousenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
|
||||
* | | |0 = Continuous data access mode Disabled.
|
||||
* | | |1 = Continuous data access mode Enabled.
|
||||
* |[10:8] |MCLKDIV |External Output Clock Divider
|
||||
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
|
||||
* | | |000 = HCLK/1.
|
||||
* | | |001 = HCLK/2.
|
||||
* | | |010 = HCLK/4.
|
||||
* | | |011 = HCLK/8.
|
||||
* | | |100 = HCLK/16.
|
||||
* | | |101 = HCLK/32.
|
||||
* | | |110 = HCLK/64.
|
||||
* | | |111 = HCLK/128.
|
||||
* |[18:16] |TALE |Extend Time Of of ALE
|
||||
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
|
||||
* | | |tALE = (TALE + 1)*EBI_MCLK.
|
||||
* | | |Note: This field only available in EBI_CTL0 register.
|
||||
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
|
||||
* | | |0 = EBI write buffer Disabled.
|
||||
* | | |1 = EBI write buffer Enabled.
|
||||
* | | |Note: This bit only available in EBI_CTL0 register.
|
||||
* @var EBI_T::TCTL1
|
||||
* Offset: 0x14 External Bus Interface Bank1 Timing Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:3] |TACC |EBI Data Access Time
|
||||
* | | |TACC define data access time (tACC).
|
||||
* | | |tACC = (TACC + 1) * EBI_MCLK.
|
||||
* |[10:8] |TAHD |EBI Data Access Hold Time
|
||||
* | | |TAHD define data access hold time (tAHD).
|
||||
* | | |tAHD = (TAHD + 1) * EBI_MCLK.
|
||||
* |[15:12] |W2X |Idle Cycle After Write
|
||||
* | | |This field defines the number of W2X idle cycle.
|
||||
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* | | |W2X idle cycle = (W2X * EBI_MCLK).
|
||||
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
|
||||
* | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
|
||||
* | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
|
||||
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
|
||||
* | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
|
||||
* | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
|
||||
* |[27:24] |R2R |Idle Cycle Between Read-to-read
|
||||
* | | |This field defines the number of R2R idle cycle.
|
||||
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
|
||||
* | | |R2R idle cycle = (R2R * EBI_MCLK).
|
||||
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
|
||||
*/
|
||||
__IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
|
||||
__IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
|
||||
__I uint32_t RESERVE0[2];
|
||||
__IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
|
||||
__IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
|
||||
|
||||
} EBI_T;
|
||||
|
||||
/**
|
||||
@addtogroup EBI_CONST EBI Bit Field Definition
|
||||
Constant Definitions for EBI Controller
|
||||
@{ */
|
||||
|
||||
#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
|
||||
#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
|
||||
|
||||
#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
|
||||
#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
|
||||
|
||||
#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
|
||||
#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
|
||||
|
||||
#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */
|
||||
#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */
|
||||
|
||||
#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
|
||||
#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
|
||||
|
||||
#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
|
||||
#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
|
||||
|
||||
#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */
|
||||
#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */
|
||||
|
||||
#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
|
||||
#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
|
||||
|
||||
#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
|
||||
#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
|
||||
|
||||
#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
|
||||
#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
|
||||
|
||||
#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
|
||||
#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
|
||||
|
||||
#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
|
||||
#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
|
||||
|
||||
#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
|
||||
#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
|
||||
|
||||
/**@}*/ /* EBI_CONST */
|
||||
/**@}*/ /* end of EBI register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __EBI_REG_H__ */
|
||||
|
|
@ -1,317 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file fmc_reg.h
|
||||
* @version V1.00
|
||||
* @brief FMC register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __FMC_REG_H__
|
||||
#define __FMC_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup FMC Flash Memory Controller(FMC)
|
||||
Memory Mapped Structure for FMC Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var FMC_T::ISPCTL
|
||||
* Offset: 0x00 ISP Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ISPEN |ISP Enable Bit (Write Protection)
|
||||
* | | |ISP function enable bit. Set this bit to enable ISP function.
|
||||
* | | |0 = ISP function Disabled.
|
||||
* | | |1 = ISP function Enabled.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* |[1] |BS |Boot Select (Write Protection)
|
||||
* | | |Set/clear this bit to select next booting from LDROM/APROM, respectively.
|
||||
* | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from.
|
||||
* | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
|
||||
* | | |0 = Booting from APROM.
|
||||
* | | |1 = Booting from LDROM.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* |[2] |SPUEN |SPROM Update Enable Bit (Write Protection)
|
||||
* | | |0 = SPROM cannot be updated.
|
||||
* | | |1 = SPROM can be updated.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* |[3] |APUEN |APROM Update Enable Bit (Write Protection)
|
||||
* | | |0 = APROM cannot be updated when the chip runs in APROM.
|
||||
* | | |1 = APROM can be updated when the chip runs in APROM.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protection)
|
||||
* | | |0 = CONFIG cannot be updated.
|
||||
* | | |1 = CONFIG can be updated.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* |[5] |LDUEN |LDROM Update Enable Bit (Write Protection)
|
||||
* | | |LDROM update enable bit.
|
||||
* | | |0 = LDROM cannot be updated.
|
||||
* | | |1 = LDROM can be updated.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* |[6] |ISPFF |ISP Fail Flag (Write Protection)
|
||||
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
|
||||
* | | |This bit needs to be cleared by writing 1 to it.
|
||||
* | | |(1) APROM writes to itself if APUEN is set to 0.
|
||||
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
|
||||
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
|
||||
* | | |(4) SPROM is erased/programmed if SPUEN is set to 0.
|
||||
* | | |(5) SPROM is programmed at SPROM secured mode.
|
||||
* | | |(6) Page Erase command at LOCK mode with ICE connection.
|
||||
* | | |(7) Erase or Program command at brown-out detected.
|
||||
* | | |(8) Destination address is illegal, such as over an available range.
|
||||
* | | |(9) Invalid ISP commands.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* @var FMC_T::ISPADDR
|
||||
* Offset: 0x04 ISP Address Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |ISPADDR |ISP Address
|
||||
* | | |The NuMicro M031 series is equipped with embedded flash.
|
||||
* | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation and ISPADR[8:0] must be kept all 0 for Vector Page Re-map Command.
|
||||
* | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.
|
||||
* @var FMC_T::ISPDAT
|
||||
* Offset: 0x08 ISP Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |ISPDAT |ISP Data
|
||||
* | | |Write data to this register before ISP program operation.
|
||||
* | | |Read data from this register after ISP read operation.
|
||||
* | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 512 bytes alignment.
|
||||
* | | |For ISP Read Checksum command, ISPDAT is the checksum result.
|
||||
* | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect.
|
||||
* @var FMC_T::ISPCMD
|
||||
* Offset: 0x0C ISP Command Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[6:0] |CMD |ISP CMD
|
||||
* | | |ISP command table is shown below:
|
||||
* | | |0x00 = FLASH Read.
|
||||
* | | |0x04 = Read Unique ID..
|
||||
* | | |0x0B = Read Company ID.
|
||||
* | | |0x0C = Read Device ID.
|
||||
* | | |0x0D = Read CRC32 Checksum.
|
||||
* | | |0x21 = FLASH 32-bit Program.
|
||||
* | | |0x22 = FLASH Page Erase..
|
||||
* | | |0x2D = Run CRC32 Checksum Calculation.
|
||||
* | | |0x2E = Vector Remap.
|
||||
* | | |The other commands are invalid.
|
||||
* @var FMC_T::ISPTRG
|
||||
* Offset: 0x10 ISP Trigger Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ISPGO |ISP Start Trigger (Write Protection)
|
||||
* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
|
||||
* | | |0 = ISP operation is finished.
|
||||
* | | |1 = ISP is progressed.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* @var FMC_T::DFBA
|
||||
* Offset: 0x14 Data Flash Base Address
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |DFBA |Data Flash Base Address
|
||||
* | | |This register indicates Data Flash start address. It is a read only register.
|
||||
* | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1.
|
||||
* | | |This register is valid when DFEN (CONFIG0[0]) =0.
|
||||
* @var FMC_T::FTCTL
|
||||
* Offset: 0x18 Flash Access Time Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[6:4] |FOM |Frequency Optimization Mode (Write Protect)
|
||||
* | | |The NuMicro Mini58TM series support adjustable flash access timing to optimize the flash access cycles in different working frequency.
|
||||
* | | |0x1 = Frequency <= 24MHz..
|
||||
* | | |Others = Frequency <= 50MHz.
|
||||
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
|
||||
* @var FMC_T::ISPSTS
|
||||
* Offset: 0x40 ISP Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ISPBUSY |ISP BUSY (Read Only)
|
||||
* | | |0 = ISP operation is finished.
|
||||
* | | |1 = ISP operation is busy.
|
||||
* |[2:1] |CBS |Boot Selection of CONFIG (Read Only)
|
||||
* | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
|
||||
* | | |00 = LDROM with IAP mode.
|
||||
* | | |01 = LDROM without IAP mode.
|
||||
* | | |10 = APROM with IAP mode.
|
||||
* | | |11 = APROM without IAP mode.
|
||||
* |[6] |ISPFF |ISP Fail Flag (Write Protection)
|
||||
* | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
|
||||
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
|
||||
* | | |(1) APROM writes to itself if APUEN is set to 0.
|
||||
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
|
||||
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
|
||||
* | | |(4) SPROM is erased/programmed if SPUEN is set to 0.
|
||||
* | | |(5) SPROM is programmed at SPROM secured mode.
|
||||
* | | |(6) Page Erase command at LOCK mode with ICE connection.
|
||||
* | | |(7) Erase or Program command at brown-out detected.
|
||||
* | | |(8) Destination address is illegal, such as over an available range.
|
||||
* | | |(9) Invalid ISP commands.
|
||||
* |[29:9] |VECMAP |Vector Page Mapping Address (Read Only)
|
||||
* | | |All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}, except SPROM.
|
||||
* | | |VECMAP [20:19] = 00 system vector address is mapped to Flash memory.
|
||||
* | | |VECMAP [20:19] = 10 system vector address is mapped to SRAM memory.
|
||||
* | | |VECMAP [18:12] should be 0.All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}
|
||||
* |[31] |SCODE |Security Code Active Flag
|
||||
* | | |This bit is set to 1 by hardware when detecting SPROM secured code is active at flash initialization, or software writes 1 to this bit to make secured code active; this bit is only cleared by SPROM page erase operation.
|
||||
* | | |0 = SPROM secured code is inactive.
|
||||
* | | |1 = SPROM secured code is active.
|
||||
*/
|
||||
__IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */
|
||||
__IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */
|
||||
__IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */
|
||||
__IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */
|
||||
__IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */
|
||||
__I uint32_t DFBA; /*!< [0x0014] Data Flash Base Address */
|
||||
__IO uint32_t FTCTL; /*!< [0x0018] Flash Access Time Control Register */
|
||||
__IO uint32_t ICPCTL; /*!< [0x001C] Flash ICP Enable Control Register */
|
||||
__I uint32_t RESERVE0[8];
|
||||
__IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */
|
||||
__I uint32_t RESERVE1[15];
|
||||
__IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */
|
||||
__IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */
|
||||
__IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */
|
||||
__IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */
|
||||
__I uint32_t RESERVE2[12];
|
||||
__I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */
|
||||
__I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */
|
||||
__I uint32_t RESERVE3[0x3CD];
|
||||
__I uint32_t VERSION; /*!< [0x0FFC] FMC Version Register */
|
||||
} FMC_T;
|
||||
|
||||
/**
|
||||
@addtogroup FMC_CONST FMC Bit Field Definition
|
||||
Constant Definitions for FMC Controller
|
||||
@{ */
|
||||
|
||||
#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
|
||||
#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
|
||||
|
||||
#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
|
||||
#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
|
||||
|
||||
#define FMC_ISPCTL_SPUEN_Pos (2) /*!< FMC_T::ISPCTL: SPUEN Position */
|
||||
#define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) /*!< FMC_T::ISPCTL: SPUEN Mask */
|
||||
|
||||
#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
|
||||
#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
|
||||
|
||||
#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
|
||||
#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
|
||||
|
||||
#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
|
||||
#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
|
||||
|
||||
#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
|
||||
#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
|
||||
|
||||
#define FMC_ISPCTL_INTEN_Pos (24) /*!< FMC_T::ISPCTL: INTEN Position */
|
||||
#define FMC_ISPCTL_INTEN_Msk (0x1ul << FMC_ISPCTL_INTEN_Pos) /*!< FMC_T::ISPCTL: INTEN Mask */
|
||||
|
||||
#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
|
||||
#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
|
||||
|
||||
#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
|
||||
#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
|
||||
|
||||
#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
|
||||
#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
|
||||
|
||||
#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
|
||||
#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
|
||||
|
||||
#define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */
|
||||
#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */
|
||||
|
||||
#define FMC_FTCTL_FOM_Pos (4) /*!< FMC_T::FTCTL: FOM Position */
|
||||
#define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) /*!< FMC_T::FTCTL: FOM Mask */
|
||||
|
||||
#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
|
||||
#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
|
||||
|
||||
#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */
|
||||
#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
|
||||
|
||||
#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
|
||||
#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
|
||||
|
||||
#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
|
||||
#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
|
||||
|
||||
#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ISPFF Position */
|
||||
#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos)
|
||||
|
||||
#define FMC_ISPSTS_INTFLAG_Pos (8) /*!< FMC_T::ISPSTS: INTFLAG Position */
|
||||
#define FMC_ISPSTS_INTFLAG_Msk (0x1ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Mask */
|
||||
|
||||
#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
|
||||
#define FMC_ISPSTS_VECMAP_Msk (0x1ffffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
|
||||
|
||||
#define FMC_ISPSTS_SCODE_Pos (31) /*!< FMC_T::ISPSTS: SCODE Position */
|
||||
#define FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos) /*!< FMC_T::ISPSTS: SCODE Mask */
|
||||
|
||||
#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
|
||||
#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
|
||||
|
||||
#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
|
||||
#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
|
||||
|
||||
#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
|
||||
#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
|
||||
|
||||
#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
|
||||
#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
|
||||
|
||||
#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
|
||||
#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
|
||||
|
||||
#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
|
||||
#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
|
||||
|
||||
#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
|
||||
#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
|
||||
|
||||
#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
|
||||
#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
|
||||
|
||||
#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
|
||||
#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
|
||||
|
||||
#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
|
||||
#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
|
||||
|
||||
#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
|
||||
#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
|
||||
|
||||
#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
|
||||
#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
|
||||
|
||||
/**@}*/ /* FMC_CONST */
|
||||
/**@}*/ /* end of FMC register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __FMC_REG_H__ */
|
||||
|
|
@ -1,710 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file gpio_reg.h
|
||||
* @version V1.00
|
||||
* @brief GPIO register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __GPIO_REG_H__
|
||||
#define __GPIO_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup GPIO General Purpose Input/Output Controller (GPIO)
|
||||
Memory Mapped Structure for GPIO Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var GPIO_T::MODE
|
||||
* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 PA-PF I/O Mode Control
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[2n+1:2n]|MODEn |Port A-F I/O Pin[n] Mode Control
|
||||
* | | |Determine each I/O mode of Px.n pins.
|
||||
* | | |00 = Px.n is in Input mode.
|
||||
* | | |01 = Px.n is in Push-pull Output mode.
|
||||
* | | |10 = Px.n is in Open-drain Output mode.
|
||||
* | | |11 = Px.n is in Quasi-bidirectional mode.
|
||||
* | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]). If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on. If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
|
||||
* | | |Note2:
|
||||
* | | |The PC.8~13,15/PD.4~14/PF.7~13 pin is ignored.
|
||||
* @var GPIO_T::DINOFF
|
||||
* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 PA-PF Digital Input Path Disable Control
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[n+16] |DINOFFn |Port A-F Pin[n] Digital Input Path Disable Bit
|
||||
* | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
|
||||
* | | |0 = Px.n digital input path Enabled.
|
||||
* | | |1 = Px.n digital input path Disabled (digital input tied to low).
|
||||
* | | |Note:
|
||||
* | | |The PC.8~13,15/PD.4~14/PF.7~13 pin is ignored.
|
||||
* @var GPIO_T::DOUT
|
||||
* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 PA-PF Data Output Value
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[n] |DOUTn |Port A-F Pin[n] Output Value
|
||||
* | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
|
||||
* | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
|
||||
* | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
|
||||
* | | |Note:
|
||||
* | | |The PC.8~13,15/PD.4~14/PF.7~13 pin is ignored.
|
||||
* @var GPIO_T::DATMSK
|
||||
* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C PA-PF Data Output Write Mask
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[n] |DATMSKn |Port A-F Pin[n] Data Output Write Mask
|
||||
* | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
|
||||
* | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
|
||||
* | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
|
||||
* | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
|
||||
* | | |Note2:
|
||||
* | | |The PC.8~13,15/PD.4~14/PF.7~13 pin is ignored.
|
||||
* @var GPIO_T::PIN
|
||||
* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 PA-PF Pin Value
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[n] |PINn |Port A-F Pin[n] Pin Value
|
||||
* | | |Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
|
||||
* | | |Note:
|
||||
* | | |The PC.8~13,15/PD.4~14/PF.7~13 pin is ignored.
|
||||
* @var GPIO_T::DBEN
|
||||
* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 PA-PF De-Bounce Enable Control
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[n] |DBENn |Port A-F Pin[n] Input Signal De-bounce Enable Bit
|
||||
* | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
|
||||
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
|
||||
* | | |0 = Px.n de-bounce function Disabled.
|
||||
* | | |1 = Px.n de-bounce function Enabled.
|
||||
* | | |The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
|
||||
* | | |Note:
|
||||
* | | |The PC.8~13,15/PD.4~14/PF.7~13 pin is ignored.
|
||||
* @var GPIO_T::INTTYPE
|
||||
* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 PA-PF Interrupt Trigger Type Control
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[n] |TYPEn |Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
|
||||
* | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
|
||||
* | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
|
||||
* | | |0 = Edge trigger interrupt.
|
||||
* | | |1 = Level trigger interrupt.
|
||||
* | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
|
||||
* | | |The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
|
||||
* | | |Note:
|
||||
* | | |The PC.8~13,15/PD.4~14/PF.7~13 pin is ignored.
|
||||
* @var GPIO_T::INTEN
|
||||
* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C PA-PF Interrupt Enable Control
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[n] |FLIENn |Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
|
||||
* | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
|
||||
* | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
|
||||
* | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
|
||||
* | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
|
||||
* | | |0 = Px.n level low or high to low interrupt Disabled.
|
||||
* | | |1 = Px.n level low or high to low interrupt Enabled.
|
||||
* | | |Note:
|
||||
* | | |The PC.8~13,15/PD.4~14/PF.7~13 pin is ignored.
|
||||
* |[n+16] |RHIENn |Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
|
||||
* | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
|
||||
* | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
|
||||
* | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
|
||||
* | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
|
||||
* | | |0 = Px.n level high or low to high interrupt Disabled.
|
||||
* | | |1 = Px.n level high or low to high interrupt Enabled.
|
||||
* | | |Note:
|
||||
* | | |The PC.8~13,15/PD.4~14/PF.7~13 pin is ignored.
|
||||
* @var GPIO_T::INTSRC
|
||||
* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 PA-PF Interrupt Source Flag
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[n] |INTSRCn |Port A-F Pin[n] Interrupt Source Flag
|
||||
* | | |Write Operation :
|
||||
* | | |0 = No action.
|
||||
* | | |1 = Clear the corresponding pending interrupt.
|
||||
* | | |Read Operation :
|
||||
* | | |0 = No interrupt at Px.n.
|
||||
* | | |1 = Px.n generates an interrupt.
|
||||
* | | |Note:
|
||||
* | | |The PC.8~13,15/PD.4~14/PF.7~13 pin is ignored.
|
||||
*/
|
||||
|
||||
__IO uint32_t MODE; /*!< [0x0000] PA I/O Mode Control */
|
||||
__IO uint32_t DINOFF; /*!< [0x0004] PA Digital Input Path Disable Control */
|
||||
__IO uint32_t DOUT; /*!< [0x0008] PA Data Output Value */
|
||||
__IO uint32_t DATMSK; /*!< [0x000c] PA Data Output Write Mask */
|
||||
__I uint32_t PIN; /*!< [0x0010] PA Pin Value */
|
||||
__IO uint32_t DBEN; /*!< [0x0014] PA De-bounce Enable Control Register */
|
||||
__IO uint32_t INTTYPE; /*!< [0x0018] PA Interrupt Trigger Type Control */
|
||||
__IO uint32_t INTEN; /*!< [0x001c] PA Interrupt Enable Control Register */
|
||||
__IO uint32_t INTSRC; /*!< [0x0020] PA Interrupt Source Flag */
|
||||
} GPIO_T;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var GPIO_DBCTL_T::DBCTL
|
||||
* Offset: 0x180 Interrupt De-bounce Control
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |DBCLKSEL |De-bounce Sampling Cycle Selection
|
||||
* | | |0000 = Sample interrupt input once per 1 clocks.
|
||||
* | | |0001 = Sample interrupt input once per 2 clocks.
|
||||
* | | |0010 = Sample interrupt input once per 4 clocks.
|
||||
* | | |0011 = Sample interrupt input once per 8 clocks.
|
||||
* | | |0100 = Sample interrupt input once per 16 clocks.
|
||||
* | | |0101 = Sample interrupt input once per 32 clocks.
|
||||
* | | |0110 = Sample interrupt input once per 64 clocks.
|
||||
* | | |0111 = Sample interrupt input once per 128 clocks.
|
||||
* | | |1000 = Sample interrupt input once per 256 clocks.
|
||||
* | | |1001 = Sample interrupt input once per 2*256 clocks.
|
||||
* | | |1010 = Sample interrupt input once per 4*256 clocks.
|
||||
* | | |1011 = Sample interrupt input once per 8*256 clocks.
|
||||
* | | |1100 = Sample interrupt input once per 16*256 clocks.
|
||||
* | | |1101 = Sample interrupt input once per 32*256 clocks.
|
||||
* | | |1110 = Sample interrupt input once per 64*256 clocks.
|
||||
* | | |1111 = Sample interrupt input once per 128*256 clocks.
|
||||
* |[4] |DBCLKSRC |De-bounce Counter Clock Source Selection
|
||||
* | | |0 = De-bounce counter clock source is the HCLK.
|
||||
* | | |1 = De-bounce counter clock source is the 32 kHz internal low speed RC oscillator (LIRC).
|
||||
* |[5] |ICLKON |Interrupt Clock on Mode
|
||||
* | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
|
||||
* | | |1 = All I/O pins edge detection circuit is always active after reset.
|
||||
* | | |Note: It is recommended to disable this bit to save system power if no special application concern.
|
||||
*/
|
||||
|
||||
__IO uint32_t DBCTL; /*!< [0x0440] Interrupt De-bounce Control Register */
|
||||
} GPIO_DBCTL_T;
|
||||
|
||||
|
||||
/**
|
||||
@addtogroup GPIO_CONST GPIO Bit Field Definition
|
||||
Constant Definitions for GPIO Controller
|
||||
@{ */
|
||||
|
||||
#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */
|
||||
#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */
|
||||
#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */
|
||||
#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */
|
||||
#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */
|
||||
#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */
|
||||
#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */
|
||||
#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */
|
||||
#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */
|
||||
#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */
|
||||
#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */
|
||||
#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */
|
||||
#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */
|
||||
#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */
|
||||
#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */
|
||||
#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */
|
||||
|
||||
#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */
|
||||
#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */
|
||||
#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */
|
||||
#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */
|
||||
#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */
|
||||
#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */
|
||||
#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */
|
||||
#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */
|
||||
#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */
|
||||
#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */
|
||||
#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */
|
||||
#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */
|
||||
#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */
|
||||
#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */
|
||||
#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */
|
||||
#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */
|
||||
#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */
|
||||
|
||||
#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */
|
||||
#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */
|
||||
#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */
|
||||
#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */
|
||||
#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */
|
||||
#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */
|
||||
#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */
|
||||
#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */
|
||||
#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */
|
||||
#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */
|
||||
#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */
|
||||
#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */
|
||||
#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */
|
||||
#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */
|
||||
#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */
|
||||
#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */
|
||||
#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */
|
||||
|
||||
#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */
|
||||
#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */
|
||||
#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */
|
||||
#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */
|
||||
#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */
|
||||
#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */
|
||||
#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */
|
||||
#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */
|
||||
#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */
|
||||
#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */
|
||||
#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */
|
||||
#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */
|
||||
#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */
|
||||
#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */
|
||||
#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */
|
||||
#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */
|
||||
#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */
|
||||
|
||||
#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */
|
||||
#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */
|
||||
#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */
|
||||
#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */
|
||||
#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */
|
||||
#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */
|
||||
#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */
|
||||
#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */
|
||||
#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */
|
||||
#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */
|
||||
#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */
|
||||
#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */
|
||||
#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */
|
||||
#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */
|
||||
#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */
|
||||
#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */
|
||||
#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */
|
||||
|
||||
#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */
|
||||
#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */
|
||||
#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */
|
||||
#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */
|
||||
#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */
|
||||
#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */
|
||||
#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */
|
||||
#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */
|
||||
#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */
|
||||
#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */
|
||||
#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */
|
||||
#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */
|
||||
#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */
|
||||
#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */
|
||||
#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */
|
||||
#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */
|
||||
#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */
|
||||
|
||||
#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */
|
||||
#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */
|
||||
#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */
|
||||
#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */
|
||||
#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */
|
||||
#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */
|
||||
#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */
|
||||
#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */
|
||||
#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */
|
||||
#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */
|
||||
#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */
|
||||
#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */
|
||||
#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */
|
||||
#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */
|
||||
#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */
|
||||
#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */
|
||||
#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */
|
||||
|
||||
#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */
|
||||
#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */
|
||||
#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */
|
||||
#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */
|
||||
#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */
|
||||
#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */
|
||||
#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */
|
||||
#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */
|
||||
#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */
|
||||
#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */
|
||||
#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */
|
||||
#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */
|
||||
#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */
|
||||
#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */
|
||||
#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */
|
||||
#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */
|
||||
#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */
|
||||
|
||||
#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */
|
||||
#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */
|
||||
#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */
|
||||
#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */
|
||||
#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */
|
||||
#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */
|
||||
#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */
|
||||
#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */
|
||||
#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */
|
||||
#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */
|
||||
#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */
|
||||
#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */
|
||||
#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */
|
||||
#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */
|
||||
#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */
|
||||
#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */
|
||||
#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */
|
||||
|
||||
#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */
|
||||
#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */
|
||||
#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */
|
||||
#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */
|
||||
#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */
|
||||
#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */
|
||||
#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */
|
||||
#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */
|
||||
#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */
|
||||
#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */
|
||||
#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */
|
||||
#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */
|
||||
#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */
|
||||
#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */
|
||||
#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */
|
||||
#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */
|
||||
#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */
|
||||
|
||||
#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */
|
||||
#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */
|
||||
|
||||
#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_DBCTL_T::DBCTL: DBCLKSEL Position */
|
||||
#define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL_T::DBCTL: DBCLKSEL Mask */
|
||||
|
||||
#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_DBCTL_T::DBCTL: DBCLKSRC Position */
|
||||
#define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_DBCTL_T::DBCTL: DBCLKSRC Mask */
|
||||
|
||||
#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_DBCTL_T::DBCTL: ICLKON Position */
|
||||
#define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_DBCTL_T::DBCTL: ICLKON Mask */
|
||||
|
||||
#define GPIO_PDIO_PDIO_Pos (0) /*!< PDIO Position */
|
||||
#define GPIO_PDIO_PDIO_Msk (0x1ul << GPIO_PDIO_PDIO_Pos) /*!< PDIO Mask */
|
||||
|
||||
/**@}*/ /* GPIO_CONST */
|
||||
/**@}*/ /* end of GPIO register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __GPIO_REG_H__ */
|
||||
|
|
@ -1,130 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file hdiv_reg.h
|
||||
* @version V1.00
|
||||
* @brief HDIV register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __HDIV_REG_H__
|
||||
#define __HDIV_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup HDIV Hardware Divider (HDIV)
|
||||
Memory Mapped Structure for HDIV Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* DIVIDEND
|
||||
* ===================================================================================================
|
||||
* Offset: 0x00 Dividend Source Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |DIVIDEND |Dividend Source
|
||||
* | | |This register is given the dividend of divider before calculation starting.
|
||||
*/
|
||||
__IO uint32_t DIVIDEND;
|
||||
|
||||
/**
|
||||
* DIVISOR
|
||||
* ===================================================================================================
|
||||
* Offset: 0x04 Divisor Source Resister
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |DIVISOR |Divisor Source
|
||||
* | | |This register is given the divisor of divider before calculation starts.
|
||||
* | | |Note: When this register is written, hardware divider will start calculate.
|
||||
*/
|
||||
__IO uint32_t DIVISOR;
|
||||
|
||||
/**
|
||||
* QUOTIENT
|
||||
* ===================================================================================================
|
||||
* Offset: 0x08 Quotient Result Resister
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |QUOTIENT |Quotient Result
|
||||
* | | |This register holds the quotient result of divider after calculation complete.
|
||||
*/
|
||||
__IO uint32_t QUOTIENT;
|
||||
|
||||
/**
|
||||
* REM
|
||||
* ===================================================================================================
|
||||
* Offset: 0x0C Remainder Result Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |REM |Remainder Result
|
||||
* | | |The remainder of hardware divider is 16-bit sign integer (REM[15:0]) with sign extension
|
||||
* | | |(REM[31:16]) to 32-bit integer.
|
||||
*/
|
||||
__IO uint32_t REM;
|
||||
|
||||
/**
|
||||
* STATUS
|
||||
* ===================================================================================================
|
||||
* Offset: 0x10 Divider Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1] |DIVBYZERO |Divisor Zero Warning
|
||||
* | | |0 = The divisor is not 0.
|
||||
* | | |1 = The divisor is 0.
|
||||
* | | |Note: The DIVBYZERO flag is used to indicate divide-by-zero situation and updated whenever
|
||||
* | | |HDIV_DIVISOR is written.
|
||||
* | | |This register is read only.
|
||||
*/
|
||||
__I uint32_t STATUS;
|
||||
|
||||
} HDIV_T;
|
||||
|
||||
/**
|
||||
@addtogroup HDIV_CONST HDIV Bit Field Definition
|
||||
Constant Definitions for HDIV Controller
|
||||
@{ */
|
||||
|
||||
#define HDIV_DIVIDEND_DIVIDEND_Pos (0) /*!< HDIV_T::DIVIDEND: DIVIDEND Position */
|
||||
#define HDIV_DIVIDEND_DIVIDEND_Msk (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos) /*!< HDIV_T::DIVIDEND: DIVIDEND Mask */
|
||||
|
||||
#define HDIV_DIVISOR_DIVISOR_Pos (0) /*!< HDIV_T::DIVISOR: DIVISOR Position */
|
||||
#define HDIV_DIVISOR_DIVISOR_Msk (0xfffful << HDIV_DIVISOR_DIVISOR_Pos) /*!< HDIV_T::DIVISOR: DIVISOR Mask */
|
||||
|
||||
#define HDIV_QUOTIENT_QUOTIENT_Pos (0) /*!< HDIV_T::QUOTIENT: QUOTIENT Position */
|
||||
#define HDIV_QUOTIENT_QUOTIENT_Msk (0xfffffffful << HDIV_QUOTIENT_QUOTIENT_Pos) /*!< HDIV_T::QUOTIENT: QUOTIENT Mask */
|
||||
|
||||
#define HDIV_REM_REM_Pos (0) /*!< HDIV_T::REM: REM Position */
|
||||
#define HDIV_REM_REM_Msk (0xfffffffful << HDIV_REM_REM_Pos) /*!< HDIV_T::REM: REM Mask */
|
||||
|
||||
#define HDIV_STATUS_DIVBYZERO_Pos (1) /*!< HDIV_T::STATUS: DIVBYZERO Position */
|
||||
#define HDIV_STATUS_DIVBYZERO_Msk (0x1ul << HDIV_STATUS_DIVBYZERO_Pos) /*!< HDIV_T::STATUS: DIVBYZERO Mask */
|
||||
|
||||
/**@}*/ /* HDIV_CONST */
|
||||
/**@}*/ /* end of HDIV register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __HDIV_REG_H__ */
|
||||
|
||||
|
||||
/**@}*/ /* HDIV_CONST */
|
||||
/**@}*/ /* end of HDIV register group */
|
||||
|
|
@ -1,750 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file i2c_reg.h
|
||||
* @version V1.00
|
||||
* @brief I2C register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __I2C_REG_H__
|
||||
#define __I2C_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup I2C Inter-IC Bus Controller (I2C)
|
||||
Memory Mapped Structure for I2C Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var I2C_T::CTL0
|
||||
* Offset: 0x00 I2C Control Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[2] |AA |Assert Acknowledge Control
|
||||
* | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter.
|
||||
* | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
|
||||
* |[3] |SI |I2C Interrupt Flag
|
||||
* | | |When a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware.
|
||||
* | | |If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested.
|
||||
* | | |SI must be cleared by software.
|
||||
* | | |Clear SI by writing 1 to this bit.
|
||||
* |[4] |STO |I2C STOP Control
|
||||
* | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected.
|
||||
* | | |This bit will be cleared by hardware automatically.
|
||||
* |[5] |STA |I2C START Control
|
||||
* | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
|
||||
* |[6] |I2CEN |I2C Controller Enable Bit
|
||||
* | | |Set to enable I2C serial function controller.
|
||||
* | | |When I2CEN=1 the I2C serial function enable.
|
||||
* | | |The multi-function pin function must set to SDA, and SCL of I2C function first.
|
||||
* | | |0 = I2C controller Disabled.
|
||||
* | | |1 = I2C controller Enabled.
|
||||
* |[7] |INTEN |Enable Interrupt
|
||||
* | | |0 = I2C interrupt Disabled.
|
||||
* | | |1 = I2C interrupt Enabled.
|
||||
* @var I2C_T::ADDR0
|
||||
* Offset: 0x04 I2C Slave Address Register0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |GC |General Call Function
|
||||
* | | |0 = General Call Function Disabled.
|
||||
* | | |1 = General Call Function Enabled.
|
||||
* |[7:1] |ADDR |I2C Address
|
||||
* | | |The content of this register is irrelevant when I2C is in Master mode.
|
||||
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
|
||||
* | | |The I2C hardware will react if either of the address is matched.
|
||||
* | | |Note: When software set 7'h00, the address can not be used.
|
||||
* @var I2C_T::DAT
|
||||
* Offset: 0x08 I2C Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:0] |DAT |I2C Data
|
||||
* | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
|
||||
* @var I2C_T::STATUS0
|
||||
* Offset: 0x0C I2C Status Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:0] |STATUS |I2C Status
|
||||
* | | |The three least significant bits are always 0.
|
||||
* | | |The five most significant bits contain the status code.
|
||||
* | | |There are 28 possible status codes.
|
||||
* | | |When the content of I2C_STATUS0 is F8H, no serial interrupt is requested.
|
||||
* | | |Others I2C_STATUS0 values correspond to defined I2C states.
|
||||
* | | |When each of these states is entered, a status interrupt is requested (SI = 1).
|
||||
* | | |A valid status code is present in I2C_STATUS0 one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software.
|
||||
* | | |In addition, states 00H stands for a Bus Error.
|
||||
* | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame.
|
||||
* | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
|
||||
* @var I2C_T::CLKDIV
|
||||
* Offset: 0x10 I2C Clock Divided Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[9:0] |DIVIDER |I2C Clock Divided
|
||||
* | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
|
||||
* | | |Note: The minimum value of I2C_CLKDIV is 4.
|
||||
* @var I2C_T::TOCTL
|
||||
* Offset: 0x14 I2C Time-out Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |TOIF |Time-out Flag
|
||||
* | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
|
||||
* | | |Note: Software can write 1 to clear this bit.
|
||||
* |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4
|
||||
* | | |When enabled, the time-out period is extended 4 times.
|
||||
* | | |0 = Time-out period is extend 4 times Disabled.
|
||||
* | | |1 = Time-out period is extend 4 times Enabled.
|
||||
* |[2] |TOCEN |Time-out Counter Enable Bit
|
||||
* | | |When enabled, the 14-bit time-out counter will start counting when SI is cleared.
|
||||
* | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
|
||||
* | | |0 = Time-out counter Disabled.
|
||||
* | | |1 = Time-out counter Enabled.
|
||||
* @var I2C_T::ADDR1
|
||||
* Offset: 0x18 I2C Slave Address Register1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |GC |General Call Function
|
||||
* | | |0 = General Call Function Disabled.
|
||||
* | | |1 = General Call Function Enabled.
|
||||
* |[7:1] |ADDR |I2C Address
|
||||
* | | |The content of this register is irrelevant when I2C is in Master mode.
|
||||
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
|
||||
* | | |The I2C hardware will react if either of the address is matched.
|
||||
* | | |Note: When software set 7'h00, the address can not be used.
|
||||
* @var I2C_T::ADDR2
|
||||
* Offset: 0x1C I2C Slave Address Register2
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |GC |General Call Function
|
||||
* | | |0 = General Call Function Disabled.
|
||||
* | | |1 = General Call Function Enabled.
|
||||
* |[7:1] |ADDR |I2C Address
|
||||
* | | |The content of this register is irrelevant when I2C is in Master mode.
|
||||
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
|
||||
* | | |The I2C hardware will react if either of the address is matched.
|
||||
* | | |Note: When software set 7'h00, the address can not be used.
|
||||
* @var I2C_T::ADDR3
|
||||
* Offset: 0x20 I2C Slave Address Register3
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |GC |General Call Function
|
||||
* | | |0 = General Call Function Disabled.
|
||||
* | | |1 = General Call Function Enabled.
|
||||
* |[7:1] |ADDR |I2C Address
|
||||
* | | |The content of this register is irrelevant when I2C is in Master mode.
|
||||
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
|
||||
* | | |The I2C hardware will react if either of the address is matched.
|
||||
* | | |Note: When software set 7'h00, the address can not be used.
|
||||
* @var I2C_T::ADDRMSK0
|
||||
* Offset: 0x24 I2C Slave Address Mask Register0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:1] |ADDRMSK |I2C Address Mask
|
||||
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register).
|
||||
* | | |1 = Mask Enabled (the received corresponding address bit is don't care).
|
||||
* | | |I2C bus controllers support multiple address recognition with four address mask register.
|
||||
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
|
||||
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
|
||||
* | | |Note: The wake-up function can not use address mask.
|
||||
* @var I2C_T::ADDRMSK1
|
||||
* Offset: 0x28 I2C Slave Address Mask Register1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:1] |ADDRMSK |I2C Address Mask
|
||||
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register).
|
||||
* | | |1 = Mask Enabled (the received corresponding address bit is don't care).
|
||||
* | | |I2C bus controllers support multiple address recognition with four address mask register.
|
||||
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
|
||||
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
|
||||
* | | |Note: The wake-up function can not use address mask.
|
||||
* @var I2C_T::ADDRMSK2
|
||||
* Offset: 0x2C I2C Slave Address Mask Register2
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:1] |ADDRMSK |I2C Address Mask
|
||||
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register).
|
||||
* | | |1 = Mask Enabled (the received corresponding address bit is don't care).
|
||||
* | | |I2C bus controllers support multiple address recognition with four address mask register.
|
||||
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
|
||||
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
|
||||
* | | |Note: The wake-up function can not use address mask.
|
||||
* @var I2C_T::ADDRMSK3
|
||||
* Offset: 0x30 I2C Slave Address Mask Register3
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:1] |ADDRMSK |I2C Address Mask
|
||||
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register).
|
||||
* | | |1 = Mask Enabled (the received corresponding address bit is don't care).
|
||||
* | | |I2C bus controllers support multiple address recognition with four address mask register.
|
||||
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
|
||||
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
|
||||
* | | |Note: The wake-up function can not use address mask.
|
||||
* @var I2C_T::WKCTL
|
||||
* Offset: 0x3C I2C Wake-up Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WKEN |I2C Wake-up Enable Bit
|
||||
* | | |0 = I2C wake-up function Disabled.
|
||||
* | | |1= I2C wake-up function Enabled.
|
||||
* |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit
|
||||
* | | |0 = I2C hold bus after wake-up.
|
||||
* | | |1= I2C don't hold bus after wake-up.
|
||||
* | | |Note: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received.
|
||||
* | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
|
||||
* @var I2C_T::WKSTS
|
||||
* Offset: 0x40 I2C Wake-up Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WKIF |I2C Wake-up Flag
|
||||
* | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1.
|
||||
* | | |Software can write 1 to clear this bit.
|
||||
* |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done
|
||||
* | | |0 = The ACK bit cycle of address match frame isn't done.
|
||||
* | | |1 = The ACK bit cycle of address match frame is done in power-down.
|
||||
* | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit.
|
||||
* |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame (Read Only)
|
||||
* | | |0 = Write command be record on the address match wakeup frame.
|
||||
* | | |1 = Read command be record on the address match wakeup frame.
|
||||
* | | |Note: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit.
|
||||
* @var I2C_T::CTL1
|
||||
* Offset: 0x44 I2C Control Register 1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |TXPDMAEN |PDMA Transmit Channel Available
|
||||
* | | |0 = Transmit PDMA function Disabled.
|
||||
* | | |1 = Transmit PDMA function Enabled.
|
||||
* |[1] |RXPDMAEN |PDMA Receive Channel Available
|
||||
* | | |0 = Receive PDMA function Disabled.
|
||||
* | | |1 = Receive PDMA function Enabled.
|
||||
* |[2] |PDMARST |PDMA Reset
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset the I2C request to PDMA.
|
||||
* |[3] |OVRIEN |I2C over Run Interrupt Control Bit
|
||||
* | | |Setting OVRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received buffer.
|
||||
* |[4] |UDRIEN |I2C Under Run Interrupt Control Bit
|
||||
* | | |Setting UDRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted buffer.
|
||||
* |[5] |TWOBUFEN |Two-level BUFFER Enable Bit
|
||||
* | | |0 = Two-level buffer Disabled.
|
||||
* | | |1 = Two-level buffer Enabled.
|
||||
* | | |Set to enable the two-level buffer for I2C transmitted or received buffer.
|
||||
* | | |It is used to improve the performance of the I2C bus.
|
||||
* | | |If this bit is set = 1, the control bit of STA for repeat start or STO bit should be set after the current SI is cleared.
|
||||
* | | |For example: if there are 4 data shall be transmitted and then stop it.
|
||||
* | | |The STO bit shall be set after the 3rd data's SI event being clear.
|
||||
* | | |In this time, the 4th data can be transmitted and the I2C stop after the 4th data transmission done.
|
||||
* |[6] |BUFRST |Two-level BUFFER Reset
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset the related counters, two-level buffer state machine, and the content of data buffer.
|
||||
* |[7] |NSTRETCH |No Stretch on the I2C Bus
|
||||
* | | |0 = The I2C SCL bus is stretched by hardware if the SI is not cleared in master mode.
|
||||
* | | |1 = The I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode.
|
||||
* |[8] |PDMASTR |PDMA Stretch Bit
|
||||
* | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX)
|
||||
* | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared.
|
||||
* | | |(only master TX)
|
||||
* @var I2C_T::STATUS1
|
||||
* Offset: 0x48 I2C Status Register 1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[4] |FULL |TWO-lEVEL BUFFER FULL
|
||||
* | | |This bit indicates two-level buffer TX or RX full or not when the TWOBUFEN = 1.
|
||||
* | | |This bit is set when POINTER is equal to 2.
|
||||
* | | |Note:This bit is read only.
|
||||
* |[5] |EMPTY |TWO-lEVEL BUFFER EMPTY
|
||||
* | | |This bit indicates two-level buffer TX or RX empty or not when the TWOBUFEN = 1.
|
||||
* | | |This bit is set when POINTER is equal to 0.
|
||||
* | | |Note:This bit is read only.
|
||||
* |[6] |OVR |I2C over Run Status Bit
|
||||
* | | |This bit indicates the received two-level buffer TX or RX is over run when the TWOBUFEN = 1.
|
||||
* | | |Note:This bit is read only.
|
||||
* |[7] |UDR |I2C Under Run Status Bit
|
||||
* | | |This bit indicates the transmitted two-level buffer TX or RX is under run when the TWOBUFEN = 1.
|
||||
* | | |Note:This bit is read only.
|
||||
* |[8] |ONBUSY |On Bus Busy (Read Only)
|
||||
* | | |Indicates that a communication is in progress on the bus.
|
||||
* | | |It is set by hardware when a START condition is detected.
|
||||
* | | |It is cleared by hardware when a STOP condition is detected.
|
||||
* | | |0 = The bus is IDLE (both SCLK and SDA High).
|
||||
* | | |1 = The bus is busy.
|
||||
* @var I2C_T::TMCTL
|
||||
* Offset: 0x4C I2C Timing Configure Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |STCTL |Setup Time Configure Control
|
||||
* | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
|
||||
* | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK.
|
||||
* | | |Note: Setup time setting should not make SCL output less than three PCLKs.
|
||||
* |[24:16] |HTCTL |Hold Time Configure Control
|
||||
* | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
|
||||
* | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK.
|
||||
* @var I2C_T::BUSCTL
|
||||
* Offset: 0x50 I2C Bus Management Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ACKMEN |Acknowledge Control by Manual
|
||||
* | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
|
||||
* | | |0 = Slave byte control Disabled.
|
||||
* | | |1 = Slave byte control Enabled.
|
||||
* | | |The 9th bit can response the ACK or NACK according the received data by user.
|
||||
* | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
|
||||
* | | |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS0 will be fixed as 0xF0 in slave receive condition.
|
||||
* |[1] |PECEN |Packet Error Checking Calculation Enable Bit
|
||||
* | | |0 = Packet Error Checking Calculation Disabled.
|
||||
* | | |1 = Packet Error Checking Calculation Enabled.
|
||||
* | | |Note: When I2C enter powerdown mode, the bit should be enabled after wake-up if needed PEC calculation.
|
||||
* |[2] |BMDEN |Bus Management Device Default Address Enable Bit
|
||||
* | | |0 = Device default address Disable.
|
||||
* | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed
|
||||
* | | |1 = Device default address Enabled.
|
||||
* | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
|
||||
* |[3] |BMHEN |Bus Management Host Enable Bit
|
||||
* | | |0 = Host function Disabled.
|
||||
* | | |1 = Host function Enabled.
|
||||
* |[4] |ALERTEN |Bus Management Alert Enable Bit
|
||||
* | | |Device Mode (BMHEN =0).
|
||||
* | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
|
||||
* | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
|
||||
* | | |Host Mode (BMHEN =1).
|
||||
* | | |0 = BM_ALERT pin not supported.
|
||||
* | | |1 = BM_ALERT pin supported.
|
||||
* |[5] |SCTLOSTS |Suspend/Control Data Output Status
|
||||
* | | |0 = The output of SUSCON pin is low.
|
||||
* | | |1 = The output of SUSCON pin is high.
|
||||
* |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit
|
||||
* | | |0 = The SUSCON pin in input.
|
||||
* | | |1 = The output enable is active on the SUSCON pin.
|
||||
* |[7] |BUSEN |BUS Enable Bit
|
||||
* | | |0 = The system management function Disabled.
|
||||
* | | |1 = The system management function Enabled.
|
||||
* | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
|
||||
* |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception
|
||||
* | | |0 = No PEC transfer.
|
||||
* | | |1 = PEC transmission is requested.
|
||||
* | | |Note: 1.This bit has no effect in slave mode when ACKMEN =0.
|
||||
* |[9] |TIDLE |Timer Check in Idle State
|
||||
* | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle.
|
||||
* | | |This bit is used to define which condition is enabled.
|
||||
* | | |0 = BUSTOUT is used to calculate the clock low period in bus active.
|
||||
* | | |1 = BUSTOUT is used to calculate the IDLE period in bus Idle.
|
||||
* | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
|
||||
* |[10] |PECCLR |PEC Clear at Repeat Start
|
||||
* | | |The calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected.
|
||||
* | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
|
||||
* | | |0 = PEC calculation is cleared by "Repeat Start" function Disabled.
|
||||
* | | |1 = PEC calculation is cleared by "Repeat Start" function Enabled.
|
||||
* |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt
|
||||
* | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
|
||||
* | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
|
||||
* |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit
|
||||
* | | |0 = Byte count done interrupt Disabled.
|
||||
* | | |1 = Byte count done interrupt Enabled.
|
||||
* | | |Note: This bit is used in PECEN =1.
|
||||
* |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit
|
||||
* | | |0 = PEC transfer done interrupt Disabled.
|
||||
* | | |1 = PEC transfer done interrupt Enabled.
|
||||
* | | |Note: This bit is used in PECEN =1.
|
||||
* @var I2C_T::BUSTCTL
|
||||
* Offset: 0x54 I2C Bus Management Timer Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |BUSTOEN |Bus Time Out Enable Bit
|
||||
* | | |0 = Bus clock low time-out detection Disabled.
|
||||
* | | |1 = Bus clock low time-out detection Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1)
|
||||
* |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit
|
||||
* | | |0 = Cumulative clock low time-out detection Disabled.
|
||||
* | | |1 = Cumulative clock low time-out detection Enabled.
|
||||
* | | |For Master, it calculates the period from START to ACK
|
||||
* | | |For Slave, it calculates the period from START to STOP
|
||||
* |[2] |BUSTOIEN |Time-out Interrupt Enable Bit
|
||||
* | | |BUSY =1.
|
||||
* | | |0 = SCLK low time-out interrupt Disabled.
|
||||
* | | |1 = SCLK low time-out interrupt Enabled.
|
||||
* | | |BUSY =0.
|
||||
* | | |0 = Bus IDLE time-out interrupt Disabled.
|
||||
* | | |1 = Bus IDLE time-out interrupt Enabled.
|
||||
* |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit
|
||||
* | | |0 = Clock time out interrupt Disabled.
|
||||
* | | |1 = Clock time out interrupt Enabled.
|
||||
* |[4] |TORSTEN |Time Out Reset Enable Bit
|
||||
* | | |0 = I2C state machine reset Disabled.
|
||||
* | | |1 = I2C state machine reset Enabled. (The clock and data bus will be released to high)
|
||||
* @var I2C_T::BUSSTS
|
||||
* Offset: 0x58 I2C Bus Management Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |BUSY |Bus Busy (Read Only)
|
||||
* | | |Indicates that a communication is in progress on the bus.
|
||||
* | | |It is set by hardware when a START condition is detected.
|
||||
* | | |It is cleared by hardware when a STOP condition is detected.
|
||||
* | | |0 = Bus is IDLE (both SCLK and SDA High).
|
||||
* | | |1 = Bus is busy.
|
||||
* |[1] |BCDONE |Byte Count Transmission/Receive Done
|
||||
* | | |0 = Byte count transmission/ receive is not finished when the PECEN is set.
|
||||
* | | |1 = Byte count transmission/ receive is finished when the PECEN is set.
|
||||
* | | |Note: Software can write 1 to clear this bit.
|
||||
* |[2] |PECERR |PEC Error in Reception
|
||||
* | | |0 = PEC value equal the received PEC data packet.
|
||||
* | | |1 = PEC value doesn't match the receive PEC data packet.
|
||||
* | | |Note: Software can write 1 to clear this bit.
|
||||
* |[3] |ALERT |SMBus Alert Status
|
||||
* | | |Device Mode (BMHEN =0).
|
||||
* | | |0 = SMBALERT pin state is low.
|
||||
* | | |1 = SMBALERT pin state is high.
|
||||
* | | |Host Mode (BMHEN =1).
|
||||
* | | |0 = No SMBALERT event.
|
||||
* | | |1 = There is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
|
||||
* | | |Note:
|
||||
* | | |1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system
|
||||
* | | |2. Software can write 1 to clear this bit.
|
||||
* |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status (Read Only)
|
||||
* | | |0 = The input status of SUSCON pin is 0.
|
||||
* | | |1 = The input status of SUSCON pin is 1.
|
||||
* |[5] |BUSTO |Bus Time-out Status
|
||||
* | | |0 = There is no any time-out or external clock time-out.
|
||||
* | | |1 = A time-out or external clock time-out occurred.
|
||||
* | | |In bus busy, the bit indicates the total clock low time-out event occurred; otherwise, it indicates the bus idle time-out event occurred.
|
||||
* | | |Note: Software can write 1 to clear this bit.
|
||||
* |[6] |CLKTO |Clock Low Cumulate Time-out Status
|
||||
* | | |0 = Cumulative clock low is no any time-out.
|
||||
* | | |1 = Cumulative clock low time-out occurred.
|
||||
* | | |Note: Software can write 1 to clear this bit.
|
||||
* |[7] |PECDONE |PEC Byte Transmission/Receive Done
|
||||
* | | |0 = PEC transmission/ receive is not finished when the PECEN is set.
|
||||
* | | |1 = PEC transmission/ receive is finished when the PECEN is set.
|
||||
* | | |Note: Software can write 1 to clear this bit.
|
||||
* @var I2C_T::PKTSIZE
|
||||
* Offset: 0x5C I2C Packet Error Checking Byte Number Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |PLDSIZE |Transfer Byte Number
|
||||
* | | |The transmission or receive byte number in one transaction when the PECEN is set.
|
||||
* | | |The maximum transaction or receive byte is 256 Bytes.
|
||||
* | | |Note: The byte number counting includes address, command code, and data frame.
|
||||
* @var I2C_T::PKTCRC
|
||||
* Offset: 0x60 I2C Packet Error Checking Byte Value Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:0] |PECCRC |Packet Error Checking Byte Value
|
||||
* | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1.
|
||||
* | | |It is read only.
|
||||
* @var I2C_T::BUSTOUT
|
||||
* Offset: 0x64 I2C Bus Management Timer Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:0] |BUSTO |Bus Management Time-out Value
|
||||
* | | |Indicates the bus time-out value in bus is IDLE or SCLK low.
|
||||
* | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
|
||||
* @var I2C_T::CLKTOUT
|
||||
* Offset: 0x68 I2C Bus Management Clock Low Timer Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:0] |CLKTO |Bus Clock Low Timer
|
||||
* | | |The field is used to configure the cumulative clock extension time-out.
|
||||
* | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.
|
||||
*/
|
||||
__IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */
|
||||
__IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */
|
||||
__IO uint32_t DAT; /*!< [0x0008] I2C Data Register */
|
||||
__I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */
|
||||
__IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */
|
||||
__IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */
|
||||
__IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */
|
||||
__IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */
|
||||
__IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */
|
||||
__IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */
|
||||
__IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */
|
||||
__IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */
|
||||
__IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */
|
||||
__I uint32_t RESERVE0[2];
|
||||
__IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */
|
||||
__IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */
|
||||
__IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */
|
||||
__IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */
|
||||
__IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */
|
||||
__IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */
|
||||
__IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */
|
||||
__IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */
|
||||
__IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */
|
||||
__I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */
|
||||
__IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */
|
||||
__IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */
|
||||
} I2C_T;
|
||||
|
||||
/**
|
||||
@addtogroup I2C_CONST I2C Bit Field Definition
|
||||
Constant Definitions for I2C Controller
|
||||
@{ */
|
||||
|
||||
#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL0: AA Position */
|
||||
#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL0: AA Mask */
|
||||
|
||||
#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL0: SI Position */
|
||||
#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL0: SI Mask */
|
||||
|
||||
#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL0: STO Position */
|
||||
#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL0: STO Mask */
|
||||
|
||||
#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL0: STA Position */
|
||||
#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL0: STA Mask */
|
||||
|
||||
#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL0: I2CEN Position */
|
||||
#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL0: I2CEN Mask */
|
||||
|
||||
#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL0: INTEN Position */
|
||||
#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL0: INTEN Mask */
|
||||
|
||||
#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */
|
||||
#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */
|
||||
|
||||
#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */
|
||||
#define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */
|
||||
|
||||
#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */
|
||||
#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */
|
||||
|
||||
#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS0: STATUS Position */
|
||||
#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS0_STATUS_Pos) /*!< I2C_T::STATUS0: STATUS Mask */
|
||||
|
||||
#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */
|
||||
#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */
|
||||
|
||||
#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */
|
||||
#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */
|
||||
|
||||
#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */
|
||||
#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */
|
||||
|
||||
#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */
|
||||
#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */
|
||||
|
||||
#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */
|
||||
#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */
|
||||
|
||||
#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */
|
||||
#define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */
|
||||
|
||||
#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */
|
||||
#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */
|
||||
|
||||
#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */
|
||||
#define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */
|
||||
|
||||
#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */
|
||||
#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */
|
||||
|
||||
#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */
|
||||
#define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */
|
||||
|
||||
#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */
|
||||
#define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */
|
||||
|
||||
#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */
|
||||
#define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */
|
||||
|
||||
#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */
|
||||
#define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */
|
||||
|
||||
#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */
|
||||
#define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */
|
||||
|
||||
#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */
|
||||
#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */
|
||||
|
||||
#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */
|
||||
#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */
|
||||
|
||||
#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */
|
||||
#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */
|
||||
|
||||
#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */
|
||||
#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */
|
||||
|
||||
#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */
|
||||
#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */
|
||||
|
||||
#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */
|
||||
#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */
|
||||
|
||||
#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */
|
||||
#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */
|
||||
|
||||
#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */
|
||||
#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */
|
||||
|
||||
#define I2C_CTL1_OVRIEN_Pos (3) /*!< I2C_T::CTL1: OVRIEN Position */
|
||||
#define I2C_CTL1_OVRIEN_Msk (0x1ul << I2C_CTL1_OVRIEN_Pos) /*!< I2C_T::CTL1: OVRIEN Mask */
|
||||
|
||||
#define I2C_CTL1_UDRIEN_Pos (4) /*!< I2C_T::CTL1: UDRIEN Position */
|
||||
#define I2C_CTL1_UDRIEN_Msk (0x1ul << I2C_CTL1_UDRIEN_Pos) /*!< I2C_T::CTL1: UDRIEN Mask */
|
||||
|
||||
#define I2C_CTL1_TWOBUFEN_Pos (5) /*!< I2C_T::CTL1: TWOBUFEN Position */
|
||||
#define I2C_CTL1_TWOBUFEN_Msk (0x1ul << I2C_CTL1_TWOBUFEN_Pos) /*!< I2C_T::CTL1: TWOBUFEN Mask */
|
||||
|
||||
#define I2C_CTL1_BUFRST_Pos (6) /*!< I2C_T::CTL1: BUFRST Position */
|
||||
#define I2C_CTL1_BUFRST_Msk (0x1ul << I2C_CTL1_BUFRST_Pos) /*!< I2C_T::CTL1: BUFRST Mask */
|
||||
|
||||
#define I2C_CTL1_NSTRETCH_Pos (7) /*!< I2C_T::CTL1: NSTRETCH Position */
|
||||
#define I2C_CTL1_NSTRETCH_Msk (0x1ul << I2C_CTL1_NSTRETCH_Pos) /*!< I2C_T::CTL1: NSTRETCH Mask */
|
||||
|
||||
#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */
|
||||
#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */
|
||||
|
||||
#define I2C_STATUS1_FULL_Pos (4) /*!< I2C_T::STATUS1: FULL Position */
|
||||
#define I2C_STATUS1_FULL_Msk (0x1ul << I2C_STATUS1_FULL_Pos) /*!< I2C_T::STATUS1: FULL Mask */
|
||||
|
||||
#define I2C_STATUS1_EMPTY_Pos (5) /*!< I2C_T::STATUS1: EMPTY Position */
|
||||
#define I2C_STATUS1_EMPTY_Msk (0x1ul << I2C_STATUS1_EMPTY_Pos) /*!< I2C_T::STATUS1: EMPTY Mask */
|
||||
|
||||
#define I2C_STATUS1_OVR_Pos (6) /*!< I2C_T::STATUS1: OVR Position */
|
||||
#define I2C_STATUS1_OVR_Msk (0x1ul << I2C_STATUS1_OVR_Pos) /*!< I2C_T::STATUS1: OVR Mask */
|
||||
|
||||
#define I2C_STATUS1_UDR_Pos (7) /*!< I2C_T::STATUS1: UDR Position */
|
||||
#define I2C_STATUS1_UDR_Msk (0x1ul << I2C_STATUS1_UDR_Pos) /*!< I2C_T::STATUS1: UDR Mask */
|
||||
|
||||
#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */
|
||||
#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */
|
||||
|
||||
#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */
|
||||
#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */
|
||||
|
||||
#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */
|
||||
#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */
|
||||
|
||||
#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */
|
||||
#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */
|
||||
|
||||
#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */
|
||||
#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */
|
||||
|
||||
#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */
|
||||
#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */
|
||||
|
||||
#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */
|
||||
#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */
|
||||
|
||||
#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */
|
||||
#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */
|
||||
|
||||
#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */
|
||||
#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */
|
||||
|
||||
#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */
|
||||
#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */
|
||||
|
||||
#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */
|
||||
#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */
|
||||
|
||||
#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */
|
||||
#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */
|
||||
|
||||
#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */
|
||||
#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */
|
||||
|
||||
#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */
|
||||
#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */
|
||||
|
||||
#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */
|
||||
#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */
|
||||
|
||||
#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */
|
||||
#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */
|
||||
|
||||
#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */
|
||||
#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */
|
||||
|
||||
#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */
|
||||
#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */
|
||||
|
||||
#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */
|
||||
#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */
|
||||
|
||||
#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */
|
||||
#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */
|
||||
|
||||
#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */
|
||||
#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */
|
||||
|
||||
#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */
|
||||
#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */
|
||||
|
||||
#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */
|
||||
#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */
|
||||
|
||||
#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */
|
||||
#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */
|
||||
|
||||
#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */
|
||||
#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */
|
||||
|
||||
#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */
|
||||
#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */
|
||||
|
||||
#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */
|
||||
#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */
|
||||
|
||||
#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */
|
||||
#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */
|
||||
|
||||
#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */
|
||||
#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */
|
||||
|
||||
#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */
|
||||
#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */
|
||||
|
||||
#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */
|
||||
#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */
|
||||
|
||||
#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */
|
||||
#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */
|
||||
|
||||
#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */
|
||||
#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */
|
||||
|
||||
#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */
|
||||
#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */
|
||||
|
||||
/**@}*/ /* I2C_CONST */
|
||||
/**@}*/ /* end of I2C register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __I2C_REG_H__ */
|
||||
|
|
@ -1,675 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file pdma_reg.h
|
||||
* @version V1.00
|
||||
* @brief PDMA register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __PDMA_REG_H__
|
||||
#define __PDMA_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup PDMA Peripheral Direct Memory Access Controller (PDMA)
|
||||
Memory Mapped Structure for PDMA Controller
|
||||
@{ */
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var DSCT_T::CTL
|
||||
* Offset: 0x00 Descriptor Table Control Register of PDMA Channel n
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1:0] |OPMODE |PDMA Operation Mode Selection
|
||||
* | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
|
||||
* | | |01 = Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[1] will be asserted.
|
||||
* | | |10 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute.
|
||||
* | | |11 = Reserved.
|
||||
* | | |Note: Before filling new transfer task in the Descriptor Table, user must check the PDMA_INTSTS[1] to make sure the curren task is complete.
|
||||
* |[2] |TXTYPE |Transfer Type
|
||||
* | | |0 = Burst transfer type.
|
||||
* | | |1 = Single transfer type.
|
||||
* |[6:4] |BURSIZE |Burst Size
|
||||
* | | |000 = 128 Transfers.
|
||||
* | | |001 = 64 Transfers.
|
||||
* | | |010 = 32 Transfers.
|
||||
* | | |011 = 16 Transfers.
|
||||
* | | |100 = 8 Transfers.
|
||||
* | | |101 = 4 Transfers.
|
||||
* | | |110 = 2 Transfers.
|
||||
* | | |111 = 1 Transfers.
|
||||
* | | |Note: This field is only useful in burst transfer type.
|
||||
* |[7] |TBINTDIS |Table Interrupt Disable Bit
|
||||
* | | |This field can be used to decide whether to enable table interrupt or not.
|
||||
* | | |If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[8:0]) when PDMA controller finishes transfer task.
|
||||
* | | |0 = Table interrupt Enabled.
|
||||
* | | |1 = Table interrupt Disabled.
|
||||
* | | |Note: This function only for scatter-gather mode.
|
||||
* |[9:8] |SAINC |Source Address Increment
|
||||
* | | |This field is used to set the source address increment size.
|
||||
* | | |11 = No increment (fixed address).
|
||||
* | | |Others = Increment and size is depended on TXWIDTH selection.
|
||||
* | | |Note: This function do not support in memory to memory transfer type.
|
||||
* |[11:10] |DAINC |Destination Address Increment
|
||||
* | | |This field is used to set the destination address increment size.
|
||||
* | | |11 = No increment (fixed address).
|
||||
* | | |Others = Increment and size is depended on TXWIDTH selection.
|
||||
* | | |Note: This function do not support in memory to memory transfer type.
|
||||
* |[13:12] |TXWIDTH |Transfer Width Selection
|
||||
* | | |This field is used for transfer width.
|
||||
* | | |00 = One byte (8 bit) is transferred for every operation.
|
||||
* | | |01= One half-word (16 bit) is transferred for every operation.
|
||||
* | | |10 = One word (32-bit) is transferred for every operation.
|
||||
* | | |11 = Reserved.
|
||||
* | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
|
||||
* |[31:16] |TXCNT |Transfer Count
|
||||
* | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 65536, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
|
||||
* | | |Note: When PDMA finish each transfer data, this field will be decrease immediately.
|
||||
* @var DSCT_T::SA
|
||||
* Offset: 0x04 Source Address Register of PDMA Channel n
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |SA |PDMA Transfer Source Address
|
||||
* | | |This field indicates a 32-bit source address of PDMA controller.
|
||||
* @var DSCT_T::DA
|
||||
* Offset: 0x08 Destination Address Register of PDMA Channel n
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |DA |PDMA Transfer Destination Address
|
||||
* | | |This field indicates a 32-bit destination address of PDMA controller.
|
||||
* @var DSCT_T::NEXT
|
||||
* Offset: 0x0C Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |NEXT |PDMA Next Descriptor Table Offset
|
||||
* | | |This field indicates the offset of the next descriptor table address in system memory.
|
||||
* | | |Write Operation:
|
||||
* | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.
|
||||
* | | |Read Operation:
|
||||
* | | |When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory.
|
||||
* | | |Note1: The descriptor table address must be word boundary.
|
||||
* | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
|
||||
* |[31:16] |EXENEXT |PDMA Execution Next Descriptor Table Offset
|
||||
* | | |This field indicates the offset of next descriptor table address of current execution descriptor table in system memory.
|
||||
* | | |Note: write operation is useless in this field.
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] Descriptor Table Control Register of PDMA Channel n. */
|
||||
__IO uint32_t SA; /*!< [0x0004] Source Address Register of PDMA Channel n */
|
||||
__IO uint32_t DA; /*!< [0x0008] Destination Address Register of PDMA Channel n */
|
||||
__IO uint32_t NEXT; /*!< [0x000c] Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n */
|
||||
|
||||
} DSCT_T;
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var PDMA_T::CURSCAT
|
||||
* Offset: 0x100 Current Scatter-gather Descriptor Table Address of PDMA Channel n
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |CURADDR |PDMA Current Description Address (Read Only)
|
||||
* | | |This field indicates a 32-bit current external description address of PDMA controller.
|
||||
* | | |Note: This field is read only and used for Scatter-Gather mode only to indicate the current external description address.
|
||||
* @var PDMA_T::CHCTL
|
||||
* Offset: 0x400 PDMA Channel Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |CHENn |PDMA Channel Enable Bits
|
||||
* | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
|
||||
* | | |0 = PDMA channel [n] Disabled.
|
||||
* | | |1 = PDMA channel [n] Enabled.
|
||||
* | | |Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
|
||||
* @var PDMA_T::PAUSE
|
||||
* Offset: 0x404 PDMA Transfer Pause Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |PAUSEn |PDMA Channel N Transfer Pause Control (Write Only)
|
||||
* | | |User can set PAUSEn bit field to pause the PDMA transfer.
|
||||
* | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..8) and clear request active flag(PDMA_TRGSTS[n:0], n=0,1..8).
|
||||
* | | |If the paused channel is re-enabled again, the remaining transfers will be processed.
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Pause PDMA channel n transfer.
|
||||
* @var PDMA_T::SWREQ
|
||||
* Offset: 0x408 PDMA Software Request Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |SWREQn |PDMA Software Request (Write Only)
|
||||
* | | |Set this bit to 1 to generate a software request to PDMA [n].
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Generate a software request.
|
||||
* | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active.
|
||||
* | | |Active flag may be triggered by software request or peripheral request.
|
||||
* | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
|
||||
* @var PDMA_T::TRGSTS
|
||||
* Offset: 0x40C PDMA Channel Request Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |REQSTSn |PDMA Channel Request Status (Read Only)
|
||||
* | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral.
|
||||
* | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
|
||||
* | | |0 = PDMA Channel n has no request.
|
||||
* | | |1 = PDMA Channel n has a request.
|
||||
* | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
|
||||
* @var PDMA_T::PRISET
|
||||
* Offset: 0x410 PDMA Fixed Priority Setting Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |FPRISETn |PDMA Fixed Priority Setting
|
||||
* | | |Set this bit to 1 to enable fixed priority level.
|
||||
* | | |Write Operation:
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Set PDMA channel [n] to fixed priority channel.
|
||||
* | | |Read Operation:
|
||||
* | | |0 = Corresponding PDMA channel is round-robin priority.
|
||||
* | | |1 = Corresponding PDMA channel is fixed priority.
|
||||
* | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
|
||||
* @var PDMA_T::PRICLR
|
||||
* Offset: 0x414 PDMA Fixed Priority Clear Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |FPRICLRn |PDMA Fixed Priority Clear Bits (Write Only)
|
||||
* | | |Set this bit to 1 to clear fixed priority level.
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Clear PDMA channel [n] fixed priority setting.
|
||||
* | | |Note: User can read PDMA_PRISET register to know the channel priority.
|
||||
* @var PDMA_T::INTEN
|
||||
* Offset: 0x418 PDMA Interrupt Enable Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |INTENn |PDMA Interrupt Enable Bits
|
||||
* | | |This field is used to enable PDMA channel[n] interrupt.
|
||||
* | | |0 = PDMA channel n interrupt Disabled.
|
||||
* | | |1 = PDMA channel n interrupt Enabled.
|
||||
* @var PDMA_T::INTSTS
|
||||
* Offset: 0x41C PDMA Interrupt Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read Only)
|
||||
* | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
|
||||
* | | |0 = No AHB bus ERROR response received.
|
||||
* | | |1 = AHB bus ERROR response received.
|
||||
* |[1] |TDIF |Transfer Done Interrupt Flag (Read Only)
|
||||
* | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
|
||||
* | | |0 = Not finished yet.
|
||||
* | | |1 = PDMA channel has finished transmission.
|
||||
* |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only)
|
||||
* | | |0 = PDMA channel source address and destination address both follow transfer width setting.
|
||||
* | | |1 = PDMA channel source address or destination address is not follow transfer width setting.
|
||||
* |[8] |REQTOF0 |Request Time-out Flag for Channel 0
|
||||
* | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.
|
||||
* | | |0 = No request time-out.
|
||||
* | | |1 = Peripheral request time-out.
|
||||
* |[9] |REQTOF1 |Request Time-out Flag for Channel 1
|
||||
* | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.
|
||||
* | | |0 = No request time-out.
|
||||
* | | |1 = Peripheral request time-out.
|
||||
* @var PDMA_T::ABTSTS
|
||||
* Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag
|
||||
* | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
|
||||
* | | |0 = No AHB bus ERROR response received when channel n transfer.
|
||||
* | | |1 = AHB bus ERROR response received when channel n transfer.
|
||||
* @var PDMA_T::TDSTS
|
||||
* Offset: 0x424 PDMA Channel Transfer Done Flag Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |TDIFn |Transfer Done Flag
|
||||
* | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
|
||||
* | | |0 = PDMA channel transfer has not finished.
|
||||
* | | |1 = PDMA channel has finished transmission.
|
||||
* @var PDMA_T::ALIGN
|
||||
* Offset: 0x428 PDMA Transfer Alignment Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |ALIGNn |Transfer Alignment Flag
|
||||
* | | |0 = PDMA channel source address and destination address both follow transfer width setting.
|
||||
* | | |1 = PDMA channel source address or destination address is not follow transfer width setting.
|
||||
* @var PDMA_T::TACTSTS
|
||||
* Offset: 0x42C PDMA Transfer Active Flag Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |TXACTFn |Transfer on Active Flag (Read Only)
|
||||
* | | |This bit indicates which PDMA channel is in active.
|
||||
* | | |0 = PDMA channel is not finished.
|
||||
* | | |1 = PDMA channel is active.
|
||||
* @var PDMA_T::TOUTPSC
|
||||
* Offset: 0x430 PDMA Time-out Prescaler Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits
|
||||
* | | |000 = PDMA channel 0 time-out clock source is HCLK/2^8.
|
||||
* | | |001 = PDMA channel 0 time-out clock source is HCLK/2^9.
|
||||
* | | |010 = PDMA channel 0 time-out clock source is HCLK/2^10.
|
||||
* | | |011 = PDMA channel 0 time-out clock source is HCLK/2^11.
|
||||
* | | |100 = PDMA channel 0 time-out clock source is HCLK/2^12.
|
||||
* | | |101 = PDMA channel 0 time-out clock source is HCLK/2^13.
|
||||
* | | |110 = PDMA channel 0 time-out clock source is HCLK/2^14.
|
||||
* | | |111 = PDMA channel 0 time-out clock source is HCLK/2^15.
|
||||
* |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits
|
||||
* | | |000 = PDMA channel 1 time-out clock source is HCLK/2^8.
|
||||
* | | |001 = PDMA channel 1 time-out clock source is HCLK/2^9.
|
||||
* | | |010 = PDMA channel 1 time-out clock source is HCLK/2^10.
|
||||
* | | |011 = PDMA channel 1 time-out clock source is HCLK/2^11.
|
||||
* | | |100 = PDMA channel 1 time-out clock source is HCLK/2^12.
|
||||
* | | |101 = PDMA channel 1 time-out clock source is HCLK/2^13.
|
||||
* | | |110 = PDMA channel 1 time-out clock source is HCLK/2^14.
|
||||
* | | |111 = PDMA channel 1 time-out clock source is HCLK/2^15.
|
||||
* @var PDMA_T::TOUTEN
|
||||
* Offset: 0x434 PDMA Time-out Enable Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1:0] |TOUTENn |PDMA Time-out Enable Bits
|
||||
* | | |0 = PDMA Channel n time-out function Disabled.
|
||||
* | | |1 = PDMA Channel n time-out function Enabled.
|
||||
* @var PDMA_T::TOUTIEN
|
||||
* Offset: 0x438 PDMA Time-out Interrupt Enable Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1:0] |TOUTIENn |PDMA Time-out Interrupt Enable Bits
|
||||
* | | |0 = PDMA Channel n time-out interrupt Disabled.
|
||||
* | | |1 = PDMA Channel n time-out interrupt Enabled.
|
||||
* @var PDMA_T::SCATBA
|
||||
* Offset: 0x43C PDMA Scatter-gather Descriptor Table Base Address Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address
|
||||
* | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address.
|
||||
* | | |The next link address equation is
|
||||
* | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
|
||||
* | | |Note: Only useful in Scatter-Gather mode.
|
||||
* @var PDMA_T::TOC0_1
|
||||
* Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |TOC0 |Time-out Counter for Channel 0
|
||||
* | | |This controls the period of time-out function for channel 0.
|
||||
* | | |The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock.
|
||||
* | | |Time-out period = (Period of time-out clock) * (16-bit TOCn), n = 0,1.
|
||||
* |[31:16] |TOC1 |Time-out Counter for Channel 1
|
||||
* | | |This controls the period of time-out function for channel 1.
|
||||
* | | |The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[6:4]) clock.
|
||||
* | | |The example of time-out period can refer TOC0 bit description.
|
||||
* @var PDMA_T::CHRST
|
||||
* Offset: 0x460 PDMA Channel Reset Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |CHnRST |Channel N Reset
|
||||
* | | |0 = corresponding channel n is not reset.
|
||||
* | | |1 = corresponding channel n is reset.
|
||||
* @var PDMA_T::REQSEL0_3
|
||||
* Offset: 0x480 PDMA Request Source Select Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[5:0] |REQSRC0 |Channel 0 Request Source Selection
|
||||
* | | |This filed defines which peripheral is connected to PDMA channel 0.
|
||||
* | | |User can configure the peripheral by setting REQSRC0.
|
||||
* | | |0 = Disable PDMA peripheral request.
|
||||
* | | |1 = reserved.
|
||||
* | | |2 = reserved.
|
||||
* | | |3 = reserved.
|
||||
* | | |4 = Channel connects to UART0_TX.
|
||||
* | | |5 = Channel connects to UART0_RX.
|
||||
* | | |6 = Channel connects to UART1_TX.
|
||||
* | | |7 = Channel connects to UART1_RX.
|
||||
* | | |8 = Channel connects to UART2_TX.
|
||||
* | | |9 = Channel connects to UART2_RX.
|
||||
* | | |10 = Channel connects to USCI0_TX.
|
||||
* | | |11 = Channel connects to USCI0_RX.
|
||||
* | | |12 = Channel connects to USCI1_TX.
|
||||
* | | |13 = Channel connects to USCI1_RX.
|
||||
* | | |14 = Reserved.
|
||||
* | | |15 = Reserved.
|
||||
* | | |16 = Channel connects to QSPI0_TX.
|
||||
* | | |17 = Channel connects to QSPI0_RX.
|
||||
* | | |18 = Channel connects to SPI0_TX.
|
||||
* | | |19 = Channel connects to SPI0_RX.
|
||||
* | | |20 = Channel connects to ADC_RX.
|
||||
* | | |21 = Channel connects to PWM0_P1_RX.
|
||||
* | | |22 = Channel connects to PWM0_P2_RX.
|
||||
* | | |23 = Channel connects to PWM0_P3_RX.
|
||||
* | | |24 = Channel connects to PWM1_P1_RX.
|
||||
* | | |25 = Channel connects to PWM1_P2_RX.
|
||||
* | | |26 = Channel connects to PWM1_P3_RX.
|
||||
* | | |27 = Reserved.
|
||||
* | | |28 = Channel connects to I2C0_TX.
|
||||
* | | |29 = Channel connects to I2C0_RX.
|
||||
* | | |30 = Channel connects to I2C1_TX.
|
||||
* | | |31 = Channel connects to I2C1_RX.
|
||||
* | | |32 = Channel connects to TMR0.
|
||||
* | | |33 = Channel connects to TMR1.
|
||||
* | | |34 = Channel connects to TMR2.
|
||||
* | | |35 = Channel connects to TMR3.
|
||||
* | | |36 = Channel connects to UART3_TX.
|
||||
* | | |37 = Channel connects to UART3_RX.
|
||||
* | | |38 = Channel connects to UART4_TX.
|
||||
* | | |39 = Channel connects to UART4_RX.
|
||||
* | | |40 = Channel connects to UART5_TX.
|
||||
* | | |41 = Channel connects to UART5_RX.
|
||||
* | | |42 = Channel connects to UART6_TX.
|
||||
* | | |43 = Channel connects to UART6_RX.
|
||||
* | | |44 = Channel connects to UART7_TX.
|
||||
* | | |45 = Channel connects to UART7_RX.
|
||||
* | | |Others = Reserved.
|
||||
* | | |Note 1: A peripheral cannot be assigned to two channels at the same time.
|
||||
* | | |Note 2: This field is useless when transfer between memory and memory.
|
||||
* |[13:8] |REQSRC1 |Channel 1 Request Source Selection
|
||||
* | | |This filed defines which peripheral is connected to PDMA channel 1.
|
||||
* | | |User can configure the peripheral setting by REQSRC1.
|
||||
* | | |Note: The channel configuration is the same as REQSRC0 field.
|
||||
* | | |Please refer to the explanation of REQSRC0.
|
||||
* |[21:16] |REQSRC2 |Channel 2 Request Source Selection
|
||||
* | | |This filed defines which peripheral is connected to PDMA channel 2.
|
||||
* | | |User can configure the peripheral setting by REQSRC2.
|
||||
* | | |Note: The channel configuration is the same as REQSRC0 field.
|
||||
* | | |Please refer to the explanation of REQSRC0.
|
||||
* |[29:24] |REQSRC3 |Channel 3 Request Source Selection
|
||||
* | | |This filed defines which peripheral is connected to PDMA channel 3.
|
||||
* | | |User can configure the peripheral setting by REQSRC3.
|
||||
* | | |Note: The channel configuration is the same as REQSRC0 field.
|
||||
* | | |Please refer to the explanation of REQSRC0.
|
||||
* @var PDMA_T::REQSEL4_7
|
||||
* Offset: 0x484 PDMA Request Source Select Register 1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[5:0] |REQSRC4 |Channel 4 Request Source Selection
|
||||
* | | |This filed defines which peripheral is connected to PDMA channel 4.
|
||||
* | | |User can configure the peripheral setting by REQSRC4.
|
||||
* | | |Note: The channel configuration is the same as REQSRC0 field.
|
||||
* | | |Please refer to the explanation of REQSRC0.
|
||||
* |[13:8] |REQSRC5 |Channel 5 Request Source Selection
|
||||
* | | |This filed defines which peripheral is connected to PDMA channel 5.
|
||||
* | | |User can configure the peripheral setting by REQSRC5.
|
||||
* | | |Note: The channel configuration is the same as REQSRC0 field.
|
||||
* | | |Please refer to the explanation of REQSRC0.
|
||||
* |[21:16] |REQSRC6 |Channel 6 Request Source Selection
|
||||
* | | |This filed defines which peripheral is connected to PDMA channel 6.
|
||||
* | | |User can configure the peripheral setting by REQSRC6.
|
||||
* | | |Note: The channel configuration is the same as REQSRC0 field.
|
||||
* | | |Please refer to the explanation of REQSRC0.
|
||||
* |[29:24] |REQSRC7 |Channel 7 Request Source Selection
|
||||
* | | |This filed defines which peripheral is connected to PDMA channel 7.
|
||||
* | | |User can configure the peripheral setting by REQSRC7.
|
||||
* | | |Note: The channel configuration is the same as REQSRC0 field.
|
||||
* | | |Please refer to the explanation of REQSRC0.
|
||||
* @var PDMA_T::REQSEL8
|
||||
* Offset: 0x488 PDMA Request Source Select Register 2
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[5:0] |REQSRC8 |Channel 8 Request Source Selection
|
||||
* | | |This filed defines which peripheral is connected to PDMA channel 8.
|
||||
* | | |User can configure the peripheral setting by REQSRC8.
|
||||
* | | |Note: The channel configuration is the same as REQSRC0 field.
|
||||
* | | |Please refer to the explanation of REQSRC0.
|
||||
*/
|
||||
DSCT_T DSCT[9]; /*!< [0x0000 ~ 0x008C] Control Register of PDMA Channel 0 ~ 8 */
|
||||
__I uint32_t RESERVE0[28];
|
||||
__I uint32_t CURSCAT[9]; /*!< [0x0100 ~ 0x110] Current Scatter-gather Descriptor Table Address of PDMA Channel n */
|
||||
__I uint32_t RESERVE1[183];
|
||||
__IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */
|
||||
__O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */
|
||||
__O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */
|
||||
__I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */
|
||||
__IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */
|
||||
__O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */
|
||||
__IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */
|
||||
__IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */
|
||||
__IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */
|
||||
__IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */
|
||||
__IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */
|
||||
__I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */
|
||||
__IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */
|
||||
__IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */
|
||||
__IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */
|
||||
__IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-gather Descriptor Table Base Address Register */
|
||||
__IO uint32_t TOC0_1; /*!< [0x0440] PDMA Time-out Counter Ch1 and Ch0 Register */
|
||||
__I uint32_t RESERVE2[7];
|
||||
__IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */
|
||||
__I uint32_t RESERVE3[7];
|
||||
__IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Request Source Select Register 0 */
|
||||
__IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Request Source Select Register 1 */
|
||||
__IO uint32_t REQSEL8; /*!< [0x0488] PDMA Request Source Select Register 2 */
|
||||
} PDMA_T;
|
||||
|
||||
/**
|
||||
@addtogroup PDMA_CONST PDMA Bit Field Definition
|
||||
Constant Definitions for PDMA Controller
|
||||
@{ */
|
||||
|
||||
#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< DSCT_T::CTL: OPMODE Position */
|
||||
#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< DSCT_T::CTL: OPMODE Mask */
|
||||
|
||||
#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< DSCT_T::CTL: TXTYPE Position */
|
||||
#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< DSCT_T::CTL: TXTYPE Mask */
|
||||
|
||||
#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< DSCT_T::CTL: BURSIZE Position */
|
||||
#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< DSCT_T::CTL: BURSIZE Mask */
|
||||
|
||||
#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< DSCT_T::CTL: TBINTDIS Position */
|
||||
#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< DSCT_T::CTL: TBINTDIS Mask */
|
||||
|
||||
#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< DSCT_T::CTL: SAINC Position */
|
||||
#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< DSCT_T::CTL: SAINC Mask */
|
||||
|
||||
#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< DSCT_T::CTL: DAINC Position */
|
||||
#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< DSCT_T::CTL: DAINC Mask */
|
||||
|
||||
#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< DSCT_T::CTL: TXWIDTH Position */
|
||||
#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< DSCT_T::CTL: TXWIDTH Mask */
|
||||
|
||||
#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< DSCT_T::CTL: TXCNT Position */
|
||||
#define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< DSCT_T::CTL: TXCNT Mask */
|
||||
|
||||
#define PDMA_DSCT_SA_SA_Pos (0) /*!< DSCT_T::SA: SA Position */
|
||||
#define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< DSCT_T::SA: SA Mask */
|
||||
|
||||
#define PDMA_DSCT_DA_DA_Pos (0) /*!< DSCT_T::DA: DA Position */
|
||||
#define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< DSCT_T::DA: DA Mask */
|
||||
|
||||
#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< DSCT_T::NEXT: NEXT Position */
|
||||
#define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< DSCT_T::NEXT: NEXT Mask */
|
||||
|
||||
#define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< DSCT_T::NEXT: EXENEXT Position */
|
||||
#define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< DSCT_T::NEXT: EXENEXT Mask */
|
||||
|
||||
#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */
|
||||
#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */
|
||||
|
||||
#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */
|
||||
#define PDMA_CHCTL_CHENn_Msk (0x1fful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */
|
||||
|
||||
#define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */
|
||||
#define PDMA_PAUSE_PAUSEn_Msk (0x1fful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */
|
||||
|
||||
#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */
|
||||
#define PDMA_SWREQ_SWREQn_Msk (0x1fful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */
|
||||
|
||||
#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */
|
||||
#define PDMA_TRGSTS_REQSTSn_Msk (0x1fful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */
|
||||
|
||||
#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */
|
||||
#define PDMA_PRISET_FPRISETn_Msk (0x1fful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */
|
||||
|
||||
#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */
|
||||
#define PDMA_PRICLR_FPRICLRn_Msk (0x1fful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */
|
||||
|
||||
#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */
|
||||
#define PDMA_INTEN_INTENn_Msk (0x1fful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */
|
||||
|
||||
#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */
|
||||
#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */
|
||||
|
||||
#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */
|
||||
#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */
|
||||
|
||||
#define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */
|
||||
#define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */
|
||||
|
||||
#define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */
|
||||
#define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */
|
||||
|
||||
#define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */
|
||||
#define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */
|
||||
|
||||
#define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */
|
||||
#define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */
|
||||
|
||||
#define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */
|
||||
#define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */
|
||||
|
||||
#define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */
|
||||
#define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */
|
||||
|
||||
#define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */
|
||||
#define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */
|
||||
|
||||
#define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */
|
||||
#define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */
|
||||
|
||||
#define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */
|
||||
#define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */
|
||||
|
||||
#define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */
|
||||
#define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */
|
||||
|
||||
#define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */
|
||||
#define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */
|
||||
|
||||
#define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */
|
||||
#define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */
|
||||
|
||||
#define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */
|
||||
#define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */
|
||||
|
||||
#define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */
|
||||
#define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */
|
||||
|
||||
#define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */
|
||||
#define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */
|
||||
|
||||
#define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */
|
||||
#define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */
|
||||
|
||||
#define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */
|
||||
#define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */
|
||||
|
||||
#define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */
|
||||
#define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */
|
||||
|
||||
#define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */
|
||||
#define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */
|
||||
|
||||
#define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */
|
||||
#define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */
|
||||
|
||||
#define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */
|
||||
#define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */
|
||||
|
||||
#define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */
|
||||
#define PDMA_ALIGN_ALIGNn_Msk (0x1fful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */
|
||||
|
||||
#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */
|
||||
#define PDMA_TACTSTS_TXACTFn_Msk (0x1fful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */
|
||||
|
||||
#define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */
|
||||
#define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */
|
||||
|
||||
#define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */
|
||||
#define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */
|
||||
|
||||
#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */
|
||||
#define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */
|
||||
|
||||
#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */
|
||||
#define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */
|
||||
|
||||
#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */
|
||||
#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */
|
||||
|
||||
#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */
|
||||
#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */
|
||||
|
||||
#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */
|
||||
#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */
|
||||
|
||||
#define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */
|
||||
#define PDMA_CHRST_CHnRST_Msk (0x1fful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */
|
||||
|
||||
#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */
|
||||
#define PDMA_REQSEL0_3_REQSRC0_Msk (0x3ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */
|
||||
|
||||
#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */
|
||||
#define PDMA_REQSEL0_3_REQSRC1_Msk (0x3ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */
|
||||
|
||||
#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */
|
||||
#define PDMA_REQSEL0_3_REQSRC2_Msk (0x3ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */
|
||||
|
||||
#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */
|
||||
#define PDMA_REQSEL0_3_REQSRC3_Msk (0x3ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */
|
||||
|
||||
#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */
|
||||
#define PDMA_REQSEL4_7_REQSRC4_Msk (0x3ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */
|
||||
|
||||
#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */
|
||||
#define PDMA_REQSEL4_7_REQSRC5_Msk (0x3ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */
|
||||
|
||||
#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */
|
||||
#define PDMA_REQSEL4_7_REQSRC6_Msk (0x3ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */
|
||||
|
||||
#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */
|
||||
#define PDMA_REQSEL4_7_REQSRC7_Msk (0x3ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */
|
||||
|
||||
#define PDMA_REQSEL8_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8: REQSRC8 Position */
|
||||
#define PDMA_REQSEL8_REQSRC8_Msk (0x3ful << PDMA_REQSEL8_REQSRC8_Pos) /*!< PDMA_T::REQSEL8: REQSRC8 Mask */
|
||||
/**@}*/ /* PDMA_CONST */
|
||||
/**@}*/ /* end of PDMA register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __PDMA_REG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,586 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file qspi_reg.h
|
||||
* @version V1.00
|
||||
* @brief QSPI register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __QSPI_REG_H__
|
||||
#define __QSPI_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup QSPI Quad Serial Peripheral Interface Controller (QSPI)
|
||||
Memory Mapped Structure for QSPI Controller
|
||||
@{ */
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var QSPI_T::CTL
|
||||
* Offset: 0x00 QSPI Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |SPIEN |QSPI Transfer Control Enable Bit
|
||||
* | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1.
|
||||
* | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
|
||||
* | | |0 = Transfer control Disabled.
|
||||
* | | |1 = Transfer control Enabled.
|
||||
* | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0.
|
||||
* |[1] |RXNEG |Receive on Negative Edge
|
||||
* | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock.
|
||||
* | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock.
|
||||
* |[2] |TXNEG |Transmit on Negative Edge
|
||||
* | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock.
|
||||
* | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock.
|
||||
* |[3] |CLKPOL |Clock Polarity
|
||||
* | | |0 = QSPI bus clock is idle low.
|
||||
* | | |1 = QSPI bus clock is idle high.
|
||||
* |[7:4] |SUSPITV |Suspend Interval (Master Only)
|
||||
* | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
|
||||
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
|
||||
* | | |The default value is 0x3.
|
||||
* | | |The period of the suspend interval is obtained according to the following equation.
|
||||
* | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle
|
||||
* | | |Example:
|
||||
* | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle.
|
||||
* | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle.
|
||||
* | | |.....
|
||||
* | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle.
|
||||
* | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle.
|
||||
* |[12:8] |DWIDTH |Data Width
|
||||
* | | |This field specifies how many bits can be transmitted / received in one transaction.
|
||||
* | | |The minimum bit length is 8 bits and can up to 32 bits.
|
||||
* | | |DWIDTH = 0x08 .... 8 bits.
|
||||
* | | |DWIDTH = 0x09 .... 9 bits.
|
||||
* | | |.....
|
||||
* | | |DWIDTH = 0x1F .... 31 bits.
|
||||
* | | |DWIDTH = 0x00 .... 32 bits.
|
||||
* |[13] |LSB |Send LSB First
|
||||
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
|
||||
* | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX).
|
||||
* |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit
|
||||
* | | |This bit is used to select full-duplex or half-duplex for QSPI transfer.
|
||||
* | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
|
||||
* | | |0 = QSPI operates in full-duplex transfer.
|
||||
* | | |1 = QSPI operates in half-duplex transfer.
|
||||
* |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only)
|
||||
* | | |This bit field is only available in Master mode.
|
||||
* | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status.
|
||||
* | | |0 = Receive-only mode Disabled.
|
||||
* | | |1 = Receive-only mode Enabled.
|
||||
* |[16] |TWOBIT |2-bit Transfer Mode Enable Bit
|
||||
* | | |0 = 2-Bit Transfer mode Disabled.
|
||||
* | | |1 = 2-Bit Transfer mode Enabled.
|
||||
* | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data.
|
||||
* | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
|
||||
* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
|
||||
* | | |0 = QSPI unit transfer interrupt Disabled.
|
||||
* | | |1 = QSPI unit transfer interrupt Enabled.
|
||||
* |[18] |SLAVE |Slave Mode Control
|
||||
* | | |0 = Master mode.
|
||||
* | | |1 = Slave mode.
|
||||
* |[19] |REORDER |Byte Reorder Function Enable Bit
|
||||
* | | |0 = Byte Reorder function Disabled.
|
||||
* | | |1 = Byte Reorder function Enabled.
|
||||
* | | |A byte suspend interval will be inserted among each byte.
|
||||
* | | |The period of the byte suspend interval depends on the setting of SUSPITV.
|
||||
* | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
|
||||
* |[20] |DATDIR |Data Port Direction Control
|
||||
* | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer.
|
||||
* | | |0 = QSPI data is input direction.
|
||||
* | | |1 = QSPI data is output direction.
|
||||
* |[21] |DUALIOEN |Dual I/O Mode Enable Bit
|
||||
* | | |0 = Dual I/O mode Disabled.
|
||||
* | | |1 = Dual I/O mode Enabled.
|
||||
* |[22] |QUADIOEN |Quad I/O Mode Enable Bit
|
||||
* | | |0 = Quad I/O mode Disabled.
|
||||
* | | |1 = Quad I/O mode Enabled.
|
||||
* @var QSPI_T::CLKDIV
|
||||
* Offset: 0x04 QSPI Clock Divider Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |DIVIDER |Clock Divider
|
||||
* | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master.
|
||||
* | | |The frequency is obtained according to the following equation.
|
||||
* | | |fspi_eclk = fspi_clock_src / (DIVIDER + 1)
|
||||
* | | |where
|
||||
* | | |fspi_clock_src is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
|
||||
* | | |Note: The time interval must be larger than or equal 8 peripheral clock cycles between releasing QSPI IP software reset and setting this clock divider register.
|
||||
* @var QSPI_T::SSCTL
|
||||
* Offset: 0x08 QSPI Slave Select Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |SS |Slave Selection Control (Master Only)
|
||||
* | | |If AUTOSS bit is cleared to 0,
|
||||
* | | |0 = set the QSPIx_SS line to inactive state.
|
||||
* | | |1 = set the QSPIx_SS line to active state.
|
||||
* | | |If the AUTOSS bit is set to 1,
|
||||
* | | |0 = Keep the QSPIx_SS line at inactive state.
|
||||
* | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time.
|
||||
* | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]).
|
||||
* |[2] |SSACTPOL |Slave Selection Active Polarity
|
||||
* | | |This bit defines the active polarity of slave selection signal (QSPIx_SS).
|
||||
* | | |0 = The slave selection signal QSPIx_SS is active low.
|
||||
* | | |1 = The slave selection signal QSPIx_SS is active high.
|
||||
* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
|
||||
* | | |0 = Automatic slave selection function Disabled
|
||||
* | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]).
|
||||
* | | |1 = Automatic slave selection function Enabled.
|
||||
* |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit
|
||||
* | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins.
|
||||
* | | |0 = 4-wire bi-direction interface.
|
||||
* | | |1 = 3-wire bi-direction interface.
|
||||
* |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit
|
||||
* | | |0 = Slave mode time-out interrupt Disabled.
|
||||
* | | |1 = Slave mode time-out interrupt Enabled.
|
||||
* |[6] |SLVTORST |Slave Mode Time-out Reset Control
|
||||
* | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
|
||||
* | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
|
||||
* |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
|
||||
* | | |0 = Slave mode bit count error interrupt Disabled.
|
||||
* | | |1 = Slave mode bit count error interrupt Enabled.
|
||||
* |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
|
||||
* | | |0 = Slave mode TX under run interrupt Disabled.
|
||||
* | | |1 = Slave mode TX under run interrupt Enabled.
|
||||
* |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
|
||||
* | | |0 = Slave select active interrupt Disabled.
|
||||
* | | |1 = Slave select active interrupt Enabled.
|
||||
* |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
|
||||
* | | |0 = Slave select inactive interrupt Disabled.
|
||||
* | | |1 = Slave select inactive interrupt Enabled.
|
||||
* |[31:16] |SLVTOCNT |Slave Mode Time-out Period
|
||||
* | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active.
|
||||
* | | |The clock source of the time-out counter is Slave peripheral clock.
|
||||
* | | |If the value is 0, it indicates the slave mode time-out function is disabled.
|
||||
* @var QSPI_T::PDMACTL
|
||||
* Offset: 0x0C QSPI PDMA Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
|
||||
* | | |0 = Transmit PDMA function Disabled.
|
||||
* | | |1 = Transmit PDMA function Enabled.
|
||||
* | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function.
|
||||
* | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
|
||||
* |[1] |RXPDMAEN |Receive PDMA Enable Bit
|
||||
* | | |0 = Receive PDMA function Disabled.
|
||||
* | | |1 = Receive PDMA function Enabled.
|
||||
* |[2] |PDMARST |PDMA Reset
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0.
|
||||
* @var QSPI_T::FIFOCTL
|
||||
* Offset: 0x10 QSPI FIFO Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |RXRST |Receive Reset
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset receive FIFO pointer and receive circuit.
|
||||
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
|
||||
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1.
|
||||
* | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
|
||||
* |[1] |TXRST |Transmit Reset
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset transmit FIFO pointer and transmit circuit.
|
||||
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
|
||||
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1.
|
||||
* | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
|
||||
* | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state.
|
||||
* |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
|
||||
* | | |0 = RX FIFO threshold interrupt Disabled.
|
||||
* | | |1 = RX FIFO threshold interrupt Enabled.
|
||||
* |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
|
||||
* | | |0 = TX FIFO threshold interrupt Disabled.
|
||||
* | | |1 = TX FIFO threshold interrupt Enabled.
|
||||
* |[4] |RXTOIEN |Receive Time-out Interrupt Enable Bit
|
||||
* | | |0 = Receive time-out interrupt Disabled.
|
||||
* | | |1 = Receive time-out interrupt Enabled.
|
||||
* |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
|
||||
* | | |0 = Receive FIFO overrun interrupt Disabled.
|
||||
* | | |1 = Receive FIFO overrun interrupt Enabled.
|
||||
* |[6] |TXUFPOL |TX Underflow Data Polarity
|
||||
* | | |0 = The QSPI data out is keep 0 if there is TX underflow event in Slave mode.
|
||||
* | | |1 = The QSPI data out is keep 1 if there is TX underflow event in Slave mode.
|
||||
* | | |Note:
|
||||
* | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
|
||||
* | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward.
|
||||
* | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame.
|
||||
* |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
|
||||
* | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1
|
||||
* | | |This bit is used to enable the TX underflow interrupt.
|
||||
* | | |0 = Slave TX underflow interrupt Disabled.
|
||||
* | | |1 = Slave TX underflow interrupt Enabled.
|
||||
* |[8] |RXFBCLR |Receive FIFO Buffer Clear
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Clear receive FIFO pointer.
|
||||
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
|
||||
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
|
||||
* | | |Note: The RX shift register will not be cleared.
|
||||
* |[9] |TXFBCLR |Transmit FIFO Buffer Clear
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Clear transmit FIFO pointer.
|
||||
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
|
||||
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
|
||||
* | | |Note: The TX shift register will not be cleared.
|
||||
* |[26:24] |RXTH |Receive FIFO Threshold
|
||||
* | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
|
||||
* |[30:28] |TXTH |Transmit FIFO Threshold
|
||||
* | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
|
||||
* @var QSPI_T::STATUS
|
||||
* Offset: 0x14 QSPI Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |BUSY |Busy Status (Read Only)
|
||||
* | | |0 = QSPI controller is in idle state.
|
||||
* | | |1 = QSPI controller is in busy state.
|
||||
* | | |The following lists the bus busy conditions:
|
||||
* | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0.
|
||||
* | | |b. For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
|
||||
* | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1.
|
||||
* | | |d. For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active.
|
||||
* | | |e. For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
|
||||
* |[1] |UNITIF |Unit Transfer Interrupt Flag
|
||||
* | | |0 = No transaction has been finished since this bit was cleared to 0.
|
||||
* | | |1 = QSPI controller has finished one unit transfer.
|
||||
* | | |Note: This bit will be cleared by writing 1 to it.
|
||||
* |[2] |SSACTIF |Slave Select Active Interrupt Flag
|
||||
* | | |0 = Slave select active interrupt was cleared or not occurred.
|
||||
* | | |1 = Slave select active interrupt event occurred.
|
||||
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
|
||||
* |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
|
||||
* | | |0 = Slave select inactive interrupt was cleared or not occurred.
|
||||
* | | |1 = Slave select inactive interrupt event occurred.
|
||||
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
|
||||
* |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
|
||||
* | | |0 = The slave select line status is 0.
|
||||
* | | |1 = The slave select line status is 1.
|
||||
* | | |Note: This bit is only available in Slave mode.
|
||||
* | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status.
|
||||
* |[5] |SLVTOIF |Slave Time-out Interrupt Flag
|
||||
* | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in QSPI controller logic will be started.
|
||||
* | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
|
||||
* | | |0 = Slave time-out is not active.
|
||||
* | | |1 = Slave time-out is active.
|
||||
* | | |Note: This bit will be cleared by writing 1 to it.
|
||||
* |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
|
||||
* | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
|
||||
* | | |0 = No Slave mode bit count error event.
|
||||
* | | |1 = Slave mode bit count error event occurs.
|
||||
* | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state.
|
||||
* | | |This bit will be cleared by writing 1 to it.
|
||||
* |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
|
||||
* | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
|
||||
* | | |0 = No Slave TX under run event.
|
||||
* | | |1 = Slave TX under run event occurs.
|
||||
* | | |Note: This bit will be cleared by writing 1 to it.
|
||||
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
|
||||
* | | |0 = Receive FIFO buffer is not empty.
|
||||
* | | |1 = Receive FIFO buffer is empty.
|
||||
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
|
||||
* | | |0 = Receive FIFO buffer is not full.
|
||||
* | | |1 = Receive FIFO buffer is full.
|
||||
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
|
||||
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
|
||||
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
|
||||
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
|
||||
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
|
||||
* | | |0 = No FIFO is overrun.
|
||||
* | | |1 = Receive FIFO is overrun.
|
||||
* | | |Note: This bit will be cleared by writing 1 to it.
|
||||
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
|
||||
* | | |0 = No receive FIFO time-out event.
|
||||
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode.
|
||||
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
|
||||
* | | |Note: This bit will be cleared by writing 1 to it.
|
||||
* |[15] |SPIENSTS |QSPI Enable Status (Read Only)
|
||||
* | | |0 = The QSPI controller is disabled.
|
||||
* | | |1 = The QSPI controller is enabled.
|
||||
* | | |Note: The QSPI peripheral clock is asynchronous with the system clock.
|
||||
* | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller.
|
||||
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
|
||||
* | | |0 = Transmit FIFO buffer is not empty.
|
||||
* | | |1 = Transmit FIFO buffer is empty.
|
||||
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
|
||||
* | | |0 = Transmit FIFO buffer is not full.
|
||||
* | | |1 = Transmit FIFO buffer is full.
|
||||
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
|
||||
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
|
||||
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
|
||||
* |[19] |TXUFIF |TX Underflow Interrupt Flag
|
||||
* | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
|
||||
* | | |Note 1: This bit will be cleared by writing 1 to it.
|
||||
* | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
|
||||
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
|
||||
* | | |0 = The reset function of TXRST or RXRST is done.
|
||||
* | | |1 = Doing the reset function of TXRST or RXRST.
|
||||
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles.
|
||||
* | | |User can check the status of this bit to monitor the reset function is doing or done.
|
||||
* |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
|
||||
* | | |This bit field indicates the valid data count of receive FIFO buffer.
|
||||
* |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
|
||||
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
|
||||
* @var QSPI_T::TX
|
||||
* Offset: 0x20 QSPI Data Transmit Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |TX |Data Transmit Register
|
||||
* | | |The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers.
|
||||
* | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]).
|
||||
* | | |If DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
|
||||
* | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer.
|
||||
* | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
|
||||
* @var QSPI_T::RX
|
||||
* Offset: 0x30 QSPI Data Receive Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |RX |Data Receive Register (Read Only)
|
||||
* | | |There are 8-level FIFO buffers in this controller.
|
||||
* | | |The data receive register holds the data received from QSPI data input pin.
|
||||
* | | |If the RXEMPTY (QSPIx_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */
|
||||
__IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */
|
||||
__IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */
|
||||
__IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */
|
||||
__IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */
|
||||
__IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */
|
||||
__I uint32_t RESERVE0[2];
|
||||
__O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */
|
||||
__I uint32_t RESERVE1[3];
|
||||
__I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */
|
||||
|
||||
} QSPI_T;
|
||||
|
||||
/**
|
||||
@addtogroup QSPI_CONST QSPI Bit Field Definition
|
||||
Constant Definitions for QSPI Controller
|
||||
@{ */
|
||||
|
||||
#define QSPI_CTL_SPIEN_Pos (0) /*!< QSPI_T::CTL: SPIEN Position */
|
||||
#define QSPI_CTL_SPIEN_Msk (0x1ul << QSPI_CTL_SPIEN_Pos) /*!< QSPI_T::CTL: SPIEN Mask */
|
||||
|
||||
#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */
|
||||
#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */
|
||||
|
||||
#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */
|
||||
#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */
|
||||
|
||||
#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */
|
||||
#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */
|
||||
|
||||
#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */
|
||||
#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */
|
||||
|
||||
#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */
|
||||
#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */
|
||||
|
||||
#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */
|
||||
#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */
|
||||
|
||||
#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */
|
||||
#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */
|
||||
|
||||
#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */
|
||||
#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */
|
||||
|
||||
#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */
|
||||
#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */
|
||||
|
||||
#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */
|
||||
#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */
|
||||
|
||||
#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */
|
||||
#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */
|
||||
|
||||
#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */
|
||||
#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */
|
||||
|
||||
#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */
|
||||
#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */
|
||||
|
||||
#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */
|
||||
#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */
|
||||
|
||||
#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */
|
||||
#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */
|
||||
|
||||
#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */
|
||||
#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */
|
||||
|
||||
#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */
|
||||
#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */
|
||||
|
||||
#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */
|
||||
#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */
|
||||
|
||||
#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */
|
||||
#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */
|
||||
|
||||
#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */
|
||||
#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */
|
||||
|
||||
#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */
|
||||
#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */
|
||||
|
||||
#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */
|
||||
#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */
|
||||
|
||||
#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */
|
||||
#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */
|
||||
|
||||
#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */
|
||||
#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */
|
||||
|
||||
#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */
|
||||
#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */
|
||||
|
||||
#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */
|
||||
#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */
|
||||
|
||||
#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */
|
||||
#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */
|
||||
|
||||
#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */
|
||||
#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */
|
||||
|
||||
#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */
|
||||
#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */
|
||||
|
||||
#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */
|
||||
#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */
|
||||
|
||||
#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */
|
||||
#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */
|
||||
|
||||
#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */
|
||||
#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */
|
||||
|
||||
#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */
|
||||
#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */
|
||||
|
||||
#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */
|
||||
#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */
|
||||
|
||||
#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */
|
||||
#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */
|
||||
|
||||
#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */
|
||||
#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */
|
||||
|
||||
#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */
|
||||
#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */
|
||||
|
||||
#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */
|
||||
#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */
|
||||
|
||||
#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */
|
||||
#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */
|
||||
|
||||
#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */
|
||||
#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */
|
||||
|
||||
#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */
|
||||
#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */
|
||||
|
||||
#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */
|
||||
#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */
|
||||
|
||||
#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */
|
||||
#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */
|
||||
|
||||
#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */
|
||||
#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */
|
||||
|
||||
#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */
|
||||
#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */
|
||||
|
||||
#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */
|
||||
#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */
|
||||
|
||||
#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */
|
||||
#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */
|
||||
|
||||
#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */
|
||||
#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */
|
||||
|
||||
#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */
|
||||
#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */
|
||||
|
||||
#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */
|
||||
#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */
|
||||
|
||||
#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */
|
||||
#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */
|
||||
|
||||
#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */
|
||||
#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */
|
||||
|
||||
#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */
|
||||
#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */
|
||||
|
||||
#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */
|
||||
#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */
|
||||
|
||||
#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */
|
||||
#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */
|
||||
|
||||
#define QSPI_STATUS_SPIENSTS_Pos (15) /*!< QSPI_T::STATUS: SPIENSTS Position */
|
||||
#define QSPI_STATUS_SPIENSTS_Msk (0x1ul << QSPI_STATUS_SPIENSTS_Pos) /*!< QSPI_T::STATUS: SPIENSTS Mask */
|
||||
|
||||
#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */
|
||||
#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */
|
||||
|
||||
#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */
|
||||
#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */
|
||||
|
||||
#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */
|
||||
#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */
|
||||
|
||||
#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */
|
||||
#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */
|
||||
|
||||
#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */
|
||||
#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */
|
||||
|
||||
#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */
|
||||
#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */
|
||||
|
||||
#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */
|
||||
#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */
|
||||
|
||||
#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */
|
||||
#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */
|
||||
|
||||
#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */
|
||||
#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */
|
||||
|
||||
|
||||
|
||||
/**@}*/ /* QSPI_CONST */
|
||||
/**@}*/ /* end of QSPI register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __QSPI_REG_H__ */
|
||||
|
|
@ -1,419 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file rtc_reg.h
|
||||
* @version V1.00
|
||||
* @brief RTC register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __RTC_REG_H__
|
||||
#define __RTC_REG_H__
|
||||
|
||||
/** @addtogroup REGISTER Control Register
|
||||
|
||||
@{
|
||||
|
||||
*/
|
||||
|
||||
/*---------------------- Real Time Clock Controller -------------------------*/
|
||||
/**
|
||||
@addtogroup RTC Real Time Clock Controller(RTC)
|
||||
Memory Mapped Structure for RTC Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var RTC_T::INIT
|
||||
* Offset: 0x00 RTC Initiation Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |INIT_ACTIVE|RTC Active Status (Read Only)
|
||||
* | | |0 = RTC is at reset state.
|
||||
* | | |1 = RTC is at normal active state.
|
||||
* |[31:1] |INIT |RTC Initiation
|
||||
* | | |When RTC block is powered on, RTC is at reset state
|
||||
* | | |User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state
|
||||
* | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
|
||||
* | | |The INIT is a write-only field and read value will be always 0.
|
||||
* @var RTC_T::FREQADJ
|
||||
* Offset: 0x08 RTC Frequency Compensation Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[5:0] |FRACTION |Fraction Part
|
||||
* | | |Formula: FRACTION = (fraction part of detected value) X 64.
|
||||
* | | |Note: Digit in FCR must be expressed as hexadecimal number.
|
||||
* |[12:8] |INTEGER |Integer Part
|
||||
* | | |00000 = Integer part of detected value is 32752.
|
||||
* | | |00001 = Integer part of detected value is 32753.
|
||||
* | | |00010 = Integer part of detected value is 32754.
|
||||
* | | |00011 = Integer part of detected value is 32755.
|
||||
* | | |00100 = Integer part of detected value is 32756.
|
||||
* | | |00101 = Integer part of detected value is 32757.
|
||||
* | | |00110 = Integer part of detected value is 32758.
|
||||
* | | |00111 = Integer part of detected value is 32759.
|
||||
* | | |01000 = Integer part of detected value is 32760.
|
||||
* | | |01001 = Integer part of detected value is 32761.
|
||||
* | | |01010 = Integer part of detected value is 32762.
|
||||
* | | |01011 = Integer part of detected value is 32763.
|
||||
* | | |01100 = Integer part of detected value is 32764.
|
||||
* | | |01101 = Integer part of detected value is 32765.
|
||||
* | | |01110 = Integer part of detected value is 32766.
|
||||
* | | |01111 = Integer part of detected value is 32767.
|
||||
* | | |10000 = Integer part of detected value is 32768.
|
||||
* | | |10001 = Integer part of detected value is 32769.
|
||||
* | | |10010 = Integer part of detected value is 32770.
|
||||
* | | |10011 = Integer part of detected value is 32771.
|
||||
* | | |10100 = Integer part of detected value is 32772.
|
||||
* | | |10101 = Integer part of detected value is 32773.
|
||||
* | | |10110 = Integer part of detected value is 32774.
|
||||
* | | |10111 = Integer part of detected value is 32775.
|
||||
* | | |11000 = Integer part of detected value is 32776.
|
||||
* | | |11001 = Integer part of detected value is 32777.
|
||||
* | | |11010 = Integer part of detected value is 32778.
|
||||
* | | |11011 = Integer part of detected value is 32779.
|
||||
* | | |11100 = Integer part of detected value is 32780.
|
||||
* | | |11101 = Integer part of detected value is 32781.
|
||||
* | | |11110 = Integer part of detected value is 32782.
|
||||
* | | |11111 = Integer part of detected value is 32783.
|
||||
* @var RTC_T::TIME
|
||||
* Offset: 0x0C RTC Time Loading Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |SEC |1-Sec Time Digit (0~9)
|
||||
* |[6:4] |TENSEC |10-Sec Time Digit (0~5)
|
||||
* |[11:8] |MIN |1-Min Time Digit (0~9)
|
||||
* |[14:12] |TENMIN |10-Min Time Digit (0~5)
|
||||
* |[19:16] |HR |1-Hour Time Digit (0~9)
|
||||
* |[21:20] |TENHR |10-Hour Time Digit (0~2)
|
||||
* | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
|
||||
* |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F)
|
||||
* @var RTC_T::CAL
|
||||
* Offset: 0x10 RTC Calendar Loading Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |DAY |1-Day Calendar Digit (0~9)
|
||||
* |[5:4] |TENDAY |10-Day Calendar Digit (0~3)
|
||||
* |[11:8] |MON |1-Month Calendar Digit (0~9)
|
||||
* |[12] |TENMON |10-Month Calendar Digit (0~1)
|
||||
* |[19:16] |YEAR |1-Year Calendar Digit (0~9)
|
||||
* |[23:20] |TENYEAR |10-Year Calendar Digit (0~9)
|
||||
* @var RTC_T::CLKFMT
|
||||
* Offset: 0x14 RTC Time Scale Selection Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |24HEN |24-hour / 12-hour Time Scale Selection
|
||||
* | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
|
||||
* | | |0 = 12-hour time scale with AM and PM indication selected.
|
||||
* | | |1 = 24-hour time scale selected.
|
||||
* |[8] |HZCNTEN |Sub-second Counter Enable Bit
|
||||
* | | |0 = HZCNT disabled in RTC_TIME and RTC_TALM.
|
||||
* | | |1 = HZCNT enabled in RTC_TIME and RTC_TALM .
|
||||
* @var RTC_T::WEEKDAY
|
||||
* Offset: 0x18 RTC Day of the Week Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[2:0] |WEEKDAY |Day of the Week Register
|
||||
* | | |000 = Sunday.
|
||||
* | | |001 = Monday.
|
||||
* | | |010 = Tuesday.
|
||||
* | | |011 = Wednesday.
|
||||
* | | |100 = Thursday.
|
||||
* | | |101 = Friday.
|
||||
* | | |110 = Saturday.
|
||||
* | | |111 = Reserved.
|
||||
* @var RTC_T::TALM
|
||||
* Offset: 0x1C RTC Time Alarm Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9)
|
||||
* |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)
|
||||
* |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9)
|
||||
* |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)
|
||||
* |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9)
|
||||
* |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)
|
||||
* | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
|
||||
* |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F)
|
||||
* @var RTC_T::CALM
|
||||
* Offset: 0x20 RTC Calendar Alarm Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)
|
||||
* |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)
|
||||
* |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9)
|
||||
* |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)
|
||||
* |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)
|
||||
* |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)
|
||||
* @var RTC_T::LEAPYEAR
|
||||
* Offset: 0x24 RTC Leap Year Indicator Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |LEAPYEAR |Leap Year Indication Register (Read Only)
|
||||
* | | |0 = This year is not a leap year.
|
||||
* | | |1 = This year is leap year.
|
||||
* @var RTC_T::INTEN
|
||||
* Offset: 0x28 RTC Interrupt Enable Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ALMIEN |Alarm Interrupt Enable Bit
|
||||
* | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
|
||||
* | | |0 = RTC Alarm interrupt Disabled.
|
||||
* | | |1 = RTC Alarm interrupt Enabled.
|
||||
* |[1] |TICKIEN |Time Tick Interrupt Enable Bit
|
||||
* @var RTC_T::INTSTS
|
||||
* Offset: 0x2C RTC Interrupt Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ALMIF |RTC Alarm Interrupt Flag
|
||||
* | | |0 = Alarm condition is not matched.
|
||||
* | | |1 = Alarm condition is matched.
|
||||
* | | |Note: Write 1 to clear this bit.
|
||||
* |[1] |TICKIF |RTC Time Tick Interrupt Flag
|
||||
* @var RTC_T::TICK
|
||||
* Offset: 0x30 RTC Time Tick Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[2:0] |TICK |Time Tick Register
|
||||
* | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
|
||||
* | | |000 = Time tick is 1 second.
|
||||
* | | |001 = Time tick is 1/2 second.
|
||||
* | | |010 = Time tick is 1/4 second.
|
||||
* | | |011 = Time tick is 1/8 second.
|
||||
* | | |100 = Time tick is 1/16 second.
|
||||
* | | |101 = Time tick is 1/32 second.
|
||||
* | | |110 = Time tick is 1/64 second.
|
||||
* | | |111 = Time tick is 1/128 second.
|
||||
* | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
|
||||
* @var RTC_T::TAMSK
|
||||
* Offset: 0x34 RTC Time Alarm Mask Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)
|
||||
* |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)
|
||||
* |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)
|
||||
* |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)
|
||||
* |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)
|
||||
* | | |Note: MHR function is only for 24-hour time scale mode.
|
||||
* |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)
|
||||
* | | |Note: MTENHR function is only for 24-hour time scale mode.
|
||||
* @var RTC_T::CAMSK
|
||||
* Offset: 0x38 RTC Calendar Alarm Mask Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
|
||||
* |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
|
||||
* |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
|
||||
* |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
|
||||
* |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
|
||||
* |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
|
||||
* @var RTC_T::LXTCTL
|
||||
* Offset: 0x100 RTC 32.768 kHz Oscillator Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7] |C32KS |Clock 32K Source Selection:
|
||||
* | | |0 = Internal 32K clock is from 32K crystal .
|
||||
* | | |1 = Internal 32K clock is from LIRC32K.
|
||||
*/
|
||||
__IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */
|
||||
__I uint32_t RESERVE0[1];
|
||||
__IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */
|
||||
__IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */
|
||||
__IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */
|
||||
__IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */
|
||||
__IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */
|
||||
__IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */
|
||||
__IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */
|
||||
__I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */
|
||||
__IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */
|
||||
__IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */
|
||||
__IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */
|
||||
__IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */
|
||||
__IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */
|
||||
__I uint32_t RESERVE1[49]; /* 0x3C ~ 0xFC */
|
||||
__IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */
|
||||
|
||||
} RTC_T;
|
||||
|
||||
/**
|
||||
@addtogroup RTC_CONST RTC Bit Field Definition
|
||||
Constant Definitions for RTC Controller
|
||||
@{ */
|
||||
|
||||
#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */
|
||||
#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */
|
||||
|
||||
#define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */
|
||||
#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */
|
||||
|
||||
#define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */
|
||||
#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */
|
||||
|
||||
#define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */
|
||||
#define RTC_FREQADJ_INTEGER_Msk (0x1ful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */
|
||||
|
||||
#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */
|
||||
#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */
|
||||
|
||||
#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */
|
||||
#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */
|
||||
|
||||
#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */
|
||||
#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */
|
||||
|
||||
#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */
|
||||
#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */
|
||||
|
||||
#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */
|
||||
#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */
|
||||
|
||||
#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */
|
||||
#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */
|
||||
|
||||
#define RTC_TIME_HZCNT_Pos (24) /*!< RTC_T::TIME: HZCNT Position */
|
||||
#define RTC_TIME_HZCNT_Msk (0x7ful << RTC_TIME_HZCNT_Pos) /*!< RTC_T::TIME: HZCNT Mask */
|
||||
|
||||
#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */
|
||||
#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */
|
||||
|
||||
#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */
|
||||
#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */
|
||||
|
||||
#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */
|
||||
#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */
|
||||
|
||||
#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */
|
||||
#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */
|
||||
|
||||
#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */
|
||||
#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */
|
||||
|
||||
#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */
|
||||
#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */
|
||||
|
||||
#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */
|
||||
#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */
|
||||
|
||||
#define RTC_CLKFMT_HZCNTEN_Pos (8) /*!< RTC_T::CLKFMT: HZCNTEN Position */
|
||||
#define RTC_CLKFMT_HZCNTEN_Msk (0x1ul << RTC_CLKFMT_HZCNTEN_Pos) /*!< RTC_T::CLKFMT: HZCNTEN Mask */
|
||||
|
||||
#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */
|
||||
#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */
|
||||
|
||||
#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */
|
||||
#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */
|
||||
|
||||
#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */
|
||||
#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */
|
||||
|
||||
#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */
|
||||
#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */
|
||||
|
||||
#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */
|
||||
#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */
|
||||
|
||||
#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */
|
||||
#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */
|
||||
|
||||
#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */
|
||||
#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */
|
||||
|
||||
#define RTC_TALM_HZCNT_Pos (24) /*!< RTC_T::TALM: HZCNT Position */
|
||||
#define RTC_TALM_HZCNT_Msk (0x7ful << RTC_TALM_HZCNT_Pos) /*!< RTC_T::TALM: HZCNT Mask */
|
||||
|
||||
#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */
|
||||
#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */
|
||||
|
||||
#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */
|
||||
#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */
|
||||
|
||||
#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */
|
||||
#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */
|
||||
|
||||
#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */
|
||||
#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */
|
||||
|
||||
#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */
|
||||
#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */
|
||||
|
||||
#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */
|
||||
#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */
|
||||
|
||||
#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */
|
||||
#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */
|
||||
|
||||
#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */
|
||||
#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */
|
||||
|
||||
#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */
|
||||
#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */
|
||||
|
||||
#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */
|
||||
#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */
|
||||
|
||||
#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */
|
||||
#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */
|
||||
|
||||
#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */
|
||||
#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */
|
||||
|
||||
#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */
|
||||
#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */
|
||||
|
||||
#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */
|
||||
#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */
|
||||
|
||||
#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */
|
||||
#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */
|
||||
|
||||
#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */
|
||||
#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */
|
||||
|
||||
#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */
|
||||
#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */
|
||||
|
||||
#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */
|
||||
#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */
|
||||
|
||||
#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */
|
||||
#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */
|
||||
|
||||
#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */
|
||||
#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */
|
||||
|
||||
#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */
|
||||
#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */
|
||||
|
||||
#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */
|
||||
#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */
|
||||
|
||||
#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */
|
||||
#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */
|
||||
|
||||
#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */
|
||||
#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */
|
||||
|
||||
#define RTC_LXTCTL_C32KS_Pos (7) /*!< RTC_T::LXTCTL: C32KS Position */
|
||||
#define RTC_LXTCTL_C32KS_Msk (0x1ul << RTC_LXTCTL_C32KS_Pos) /*!< RTC_T::LXTCTL: C32KS Mask */
|
||||
|
||||
/**@}*/ /* RTC_CONST */
|
||||
/**@}*/ /* end of RTC register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#endif /* __RTC_REG_H__ */
|
||||
|
|
@ -1,788 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file spi_reg.h
|
||||
* @version V1.00
|
||||
* @brief SPI register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __SPI_REG_H__
|
||||
#define __SPI_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup SPI Serial Peripheral Interface Controller(SPI)
|
||||
Memory Mapped Structure for SPI Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var SPI_T::CTL
|
||||
* Offset: 0x00 SPI Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |SPIEN |SPI Transfer Control Enable Bit
|
||||
* | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1.
|
||||
* | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
|
||||
* | | |0 = Transfer control Disabled.
|
||||
* | | |1 = Transfer control Enabled.
|
||||
* | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
|
||||
* |[1] |RXNEG |Receive on Negative Edge
|
||||
* | | |0 = Received data input signal is latched on the rising edge of SPI bus clock.
|
||||
* | | |1 = Received data input signal is latched on the falling edge of SPI bus clock.
|
||||
* |[2] |TXNEG |Transmit on Negative Edge
|
||||
* | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
|
||||
* | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock.
|
||||
* |[3] |CLKPOL |Clock Polarity
|
||||
* | | |0 = SPI bus clock is idle low.
|
||||
* | | |1 = SPI bus clock is idle high.
|
||||
* |[7:4] |SUSPITV |Suspend Interval (Master Only)
|
||||
* | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
|
||||
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
|
||||
* | | |The default value is 0x3.
|
||||
* | | |The period of the suspend interval is obtained according to the following equation.
|
||||
* | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
|
||||
* | | |Example:
|
||||
* | | |SUSPITV = 0x0 u2026. 0.5 SPICLK clock cycle.
|
||||
* | | |SUSPITV = 0x1 u2026. 1.5 SPICLK clock cycle.
|
||||
* | | |......
|
||||
* | | |SUSPITV = 0xE u2026. 14.5 SPICLK clock cycle.
|
||||
* | | |SUSPITV = 0xF u2026. 15.5 SPICLK clock cycle.
|
||||
* |[12:8] |DWIDTH |Data Width
|
||||
* | | |This field specifies how many bits can be transmitted / received in one transaction
|
||||
* | | |The minimum bit length is 8 bits and can up to 32 bits.
|
||||
* | | |DWIDTH = 0x08 ... 8 bits.
|
||||
* | | |DWIDTH = 0x09 ... 9 bits.
|
||||
* | | |......
|
||||
* | | |DWIDTH = 0x1F ... 31 bits.
|
||||
* | | |DWIDTH = 0x00 ... 32 bits.
|
||||
* |[13] |LSB |Send LSB First
|
||||
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
|
||||
* | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
|
||||
* |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit
|
||||
* | | |This bit is used to select full-duplex or half-duplex for SPI transfer
|
||||
* | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction while in half-duplex transfer.
|
||||
* | | |0 = SPI operates in full-duplex transfer.
|
||||
* | | |1 = SPI operates in half-duplex transfer.
|
||||
* |[15] |RXONLY |Receive-only FUNCTION Mode Enable Bit (Master Only)
|
||||
* | | |This bit field is only available in Master mode.
|
||||
* | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
|
||||
* | | |If both AUTOSS (SPI_SSCTL[3]) and RXONLY are enabled, the output slave select signal will be activated.
|
||||
* | | |0 = Receive-only function mode Disabled.
|
||||
* | | |1 = Receive-only functionmode Enabled.
|
||||
* | | |Note: We suggest users switch to receive-only mode when BUSY (SPI_STATUS[0]) is low.
|
||||
* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
|
||||
* | | |0 = SPI unit transfer interrupt Disabled.
|
||||
* | | |1 = SPI unit transfer interrupt Enabled.
|
||||
* |[18] |SLAVE |Slave Mode Control
|
||||
* | | |0 = Master mode.
|
||||
* | | |1 = Slave mode.
|
||||
* |[19] |REORDER |Byte Reorder Function Enable Bit
|
||||
* | | |0 = Byte Reorder function Disabled.
|
||||
* | | |1 = Byte Reorder function Enabled.
|
||||
* | | |A byte suspend interval will be inserted among each byte.
|
||||
* | | |The period of the byte suspend interval depends on the setting of SUSPITV.
|
||||
* | | |Note:
|
||||
* | | |Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
|
||||
* |[20] |DATDIR |Data Port Direction Control
|
||||
* | | |This bit is used to select the data input/output direction while in half-duplex transfer.
|
||||
* | | |0 = SPI data is input direction.
|
||||
* | | |1 = SPI data is output direction.
|
||||
* @var SPI_T::CLKDIV
|
||||
* Offset: 0x04 SPI Clock Divider Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:0] |DIVIDER |Clock Divider
|
||||
* | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master
|
||||
* | | |The frequency is obtained according to the following equation.
|
||||
* | | | FREQ_spi_eclk = FREQ_spi_clock_src/(DIVIDER+1)
|
||||
* | | |where
|
||||
* | | | FREQ_spi_clock_src is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
|
||||
* | | |Note: Not supported in I2S mode.
|
||||
* @var SPI_T::SSCTL
|
||||
* Offset: 0x08 SPI Slave Select Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |SS |Slave Selection Control (Master Only)
|
||||
* | | |If AUTOSS bit is cleared to 0,
|
||||
* | | |0 = set the SPIx_SS line to inactive state.
|
||||
* | | |1 = set the SPIx_SS line to active state.
|
||||
* | | |If the AUTOSS bit is set to 1,
|
||||
* | | |0 = Keep the SPIx_SS line at inactive state.
|
||||
* | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time.
|
||||
* | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]).
|
||||
* |[2] |SSACTPOL |Slave Selection Active Polarity
|
||||
* | | |This bit defines the active polarity of slave selection signal (SPIx_SS).
|
||||
* | | |0 = The slave selection signal SPIx_SS is active low.
|
||||
* | | |1 = The slave selection signal SPIx_SS is active high.
|
||||
* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
|
||||
* | | |0 = Automatic slave selection function Disabled.
|
||||
* | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]).
|
||||
* | | |1 = Automatic slave selection function Enabled.
|
||||
* |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
|
||||
* | | |0 = Slave mode bit count error interrupt Disabled.
|
||||
* | | |1 = Slave mode bit count error interrupt Enabled.
|
||||
* |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
|
||||
* | | |0 = Slave mode TX under run interrupt Disabled.
|
||||
* | | |1 = Slave mode TX under run interrupt Enabled.
|
||||
* |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
|
||||
* | | |0 = Slave select active interrupt Disabled.
|
||||
* | | |1 = Slave select active interrupt Enabled.
|
||||
* |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
|
||||
* | | |0 = Slave select inactive interrupt Disabled.
|
||||
* | | |1 = Slave select inactive interrupt Enabled.
|
||||
* @var SPI_T::PDMACTL
|
||||
* Offset: 0x0C SPI PDMA Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
|
||||
* | | |0 = Transmit PDMA function Disabled.
|
||||
* | | |1 = Transmit PDMA function Enabled.
|
||||
* | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
|
||||
* | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
|
||||
* |[1] |RXPDMAEN |Receive PDMA Enable Bit
|
||||
* | | |0 = Receiver PDMA function Disabled.
|
||||
* | | |1 = Receiver PDMA function Enabled.
|
||||
* |[2] |PDMARST |PDMA Reset
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
|
||||
* @var SPI_T::FIFOCTL
|
||||
* Offset: 0x10 SPI FIFO Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |RXRST |Receive Reset
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset receive FIFO pointer and receive circuit.
|
||||
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
|
||||
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1.
|
||||
* | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
|
||||
* |[1] |TXRST |Transmit Reset
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset transmit FIFO pointer and transmit circuit.
|
||||
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
|
||||
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1.
|
||||
* | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
|
||||
* |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
|
||||
* | | |0 = RX FIFO threshold interrupt Disabled.
|
||||
* | | |1 = RX FIFO threshold interrupt Enabled.
|
||||
* |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
|
||||
* | | |0 = TX FIFO threshold interrupt Disabled.
|
||||
* | | |1 = TX FIFO threshold interrupt Enabled.
|
||||
* |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit
|
||||
* | | |0 = Receive time-out interrupt Disabled.
|
||||
* | | |1 = Receive time-out interrupt Enabled.
|
||||
* |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
|
||||
* | | |0 = Receive FIFO overrun interrupt Disabled.
|
||||
* | | |1 = Receive FIFO overrun interrupt Enabled.
|
||||
* |[6] |TXUFPOL |TX Underflow Data Polarity
|
||||
* | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
|
||||
* | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
|
||||
* | | |Note:
|
||||
* | | |1. The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.
|
||||
* | | |2. This bit should be set as 0 in I2S mode.
|
||||
* | | |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward.
|
||||
* | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
|
||||
* |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
|
||||
* | | |0 = Slave TX underflow interrupt Disabled.
|
||||
* | | |1 = Slave TX underflow interrupt Enabled.
|
||||
* |[8] |RXFBCLR |Receive FIFO Buffer Clear
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Clear receive FIFO pointer.
|
||||
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
|
||||
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
|
||||
* | | |Note: The RX shift register will not be cleared.
|
||||
* |[9] |TXFBCLR |Transmit FIFO Buffer Clear
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Clear transmit FIFO pointer.
|
||||
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
|
||||
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
|
||||
* | | |Note: The TX shift register will not be cleared.
|
||||
* |[25:24] |RXTH |Receive FIFO Threshold
|
||||
* | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
|
||||
* | | |The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
|
||||
* |[29:28] |TXTH |Transmit FIFO Threshold
|
||||
* | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
|
||||
* | | |The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
|
||||
* @var SPI_T::STATUS
|
||||
* Offset: 0x14 SPI Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |BUSY |Busy Status (Read Only)
|
||||
* | | |0 = SPI controller is in idle state.
|
||||
* | | |1 = SPI controller is in busy state.
|
||||
* | | |The following listing are the bus busy conditions:
|
||||
* | | |a. SPIx_CTL[0] = 1 and the TXEMPTY = 0.
|
||||
* | | |b. For SPI Master mode, SPIx_CTL[0] = 1 and the TXEMPTY = 1 but the current transaction is not finished yet.
|
||||
* | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1.
|
||||
* | | |d. For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
|
||||
* | | |e. For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
|
||||
* |[1] |UNITIF |Unit Transfer Interrupt Flag
|
||||
* | | |0 = No transaction has been finished since this bit was cleared to 0.
|
||||
* | | |1 = SPI controller has finished one unit transfer.
|
||||
* | | |Note: This bit will be cleared by writing 1 to it.
|
||||
* |[2] |SSACTIF |Slave Select Active Interrupt Flag
|
||||
* | | |0 = Slave select active interrupt was cleared or not occurred.
|
||||
* | | |1 = Slave select active interrupt event occurred.
|
||||
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
|
||||
* |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
|
||||
* | | |0 = Slave select inactive interrupt was cleared or not occurred.
|
||||
* | | |1 = Slave select inactive interrupt event occurred.
|
||||
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
|
||||
* |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
|
||||
* | | |0 = The slave select line status is 0.
|
||||
* | | |1 = The slave select line status is 1.
|
||||
* | | |Note: This bit is only available in Slave mode.
|
||||
* | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
|
||||
* |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
|
||||
* | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
|
||||
* | | |0 = No Slave mode bit count error event.
|
||||
* | | |1 = Slave mode bit count error event occurs.
|
||||
* | | |Note: If the slave select active but there is no any bus clock input, the SLVBCEEIF also active when the slave select goes to inactive state
|
||||
* | | |This bit will be cleared by writing 1 to it.
|
||||
* |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
|
||||
* | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
|
||||
* | | |0 = No Slave TX under run event.
|
||||
* | | |1 = Slave TX under run event occurs.
|
||||
* | | |Note: This bit will be cleared by writing 1 to it.
|
||||
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
|
||||
* | | |0 = Receive FIFO buffer is not empty.
|
||||
* | | |1 = Receive FIFO buffer is empty.
|
||||
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
|
||||
* | | |0 = Receive FIFO buffer is not full.
|
||||
* | | |1 = Receive FIFO buffer is full.
|
||||
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
|
||||
* | | |0 = The valid data count within the RXreceive FIFO buffer is smaller than or equal to the setting value of RXTH.
|
||||
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
|
||||
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
|
||||
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
|
||||
* | | |0 = No FIFO is over run.
|
||||
* | | |1 = Receive FIFO is over run.
|
||||
* | | |Note: This bit will be cleared by writing 1 to it.
|
||||
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
|
||||
* | | |0 = No receive FIFO time-out event.
|
||||
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode.
|
||||
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
|
||||
* | | |Note: This bit will be cleared by writing 1 to it.
|
||||
* |[15] |SPIENSTS |SPI Enable Status (Read Only)
|
||||
* | | |0 = The SPI controller is disabled.
|
||||
* | | |1 = The SPI controller is enabled.
|
||||
* | | |Note: The SPI peripheral clock is asynchronous with the system clock.
|
||||
* | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
|
||||
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
|
||||
* | | |0 = Transmit FIFO buffer is not empty.
|
||||
* | | |1 = Transmit FIFO buffer is empty.
|
||||
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
|
||||
* | | |0 = Transmit FIFO buffer is not full.
|
||||
* | | |1 = Transmit FIFO buffer is full.
|
||||
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
|
||||
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
|
||||
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
|
||||
* |[19] |TXUFIF |TX Underflow Interrupt Flag
|
||||
* | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
|
||||
* | | |Note 1: This bit will be cleared by writing 1 to it.
|
||||
* | | |Note 2: If reset slaveu2019s transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
|
||||
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
|
||||
* | | |0 = The reset function of TXRST or RXRST is done.
|
||||
* | | |1 = Doing the reset function of TXRST or RXRST.
|
||||
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles.
|
||||
* | | |User can check the status of this bit to monitor the reset function is doing or done.
|
||||
* |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
|
||||
* | | |This bit field indicates the valid data count of receive FIFO buffer.
|
||||
* |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
|
||||
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
|
||||
* @var SPI_T::TX
|
||||
* Offset: 0x20 SPI Data Transmit Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |TX |Data Transmit Register
|
||||
* | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers.
|
||||
* | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.
|
||||
* | | |For exampleIn SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
|
||||
* | | |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer.
|
||||
* | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[243:0].
|
||||
* | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section.
|
||||
* | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
|
||||
* @var SPI_T::RX
|
||||
* Offset: 0x30 SPI Data Receive Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |RX |Data Receive Register
|
||||
* | | |There are 8-/4-level FIFO buffers in this controller.
|
||||
* | | |The data receive register holds the data received from SPI data input pin.
|
||||
* | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
|
||||
* | | |This is a read only register.
|
||||
* @var SPI_T::I2SCTL
|
||||
* Offset: 0x60 I2S Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |I2SEN |I2S Controller Enable Bit
|
||||
* | | |0 = Disabled I2S mode.
|
||||
* | | |1 = Enabled I2S mode.
|
||||
* | | |Note:
|
||||
* | | |1. If enable this bit, I2Sx_BCLK will start to output in master Master mode.
|
||||
* | | |2. Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
|
||||
* |[1] |TXEN |Transmit Enable Bit
|
||||
* | | |0 = Data transmit Disabled.
|
||||
* | | |1 = Data transmit Enabled.
|
||||
* |[2] |RXEN |Receive Enable Bit
|
||||
* | | |0 = Data receiving receive Disabled.
|
||||
* | | |1 = Data receiving receive Enabled.
|
||||
* |[3] |MUTE |Transmit Mute Enable Bit
|
||||
* | | |0 = Transmit data is shifted from buffer.
|
||||
* | | |1 = Transmit channel zero.
|
||||
* |[5:4] |WDWIDTH |Word Width
|
||||
* | | |00 = data size is 8-bit.
|
||||
* | | |01 = data size is 16-bit.
|
||||
* | | |10 = data size is 24-bit.
|
||||
* | | |11 = data size is 32-bit.
|
||||
* |[6] |MONO |Monaural Data
|
||||
* | | |0 = Data is stereo format.
|
||||
* | | |1 = Data is monaural format.
|
||||
* |[7] |ORDER |Stereo Data Order in FIFO
|
||||
* | | |0 = Left channel data at high byte.
|
||||
* | | |1 = Left channel data at low byte.
|
||||
* |[8] |SLAVE |Slave Mode
|
||||
* | | |I2S can operate as master or slave
|
||||
* | | |In Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from M031 series to Audio audio CODEC chip.
|
||||
* | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer Audio audio CODEC chip.
|
||||
* | | |0 = Master mode.
|
||||
* | | |1 = Slave mode.
|
||||
* |[15] |MCLKEN |Master Clock Enable Bit
|
||||
* | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
|
||||
* | | |0 = Master clock Disabled.
|
||||
* | | |1 = Master clock Enabled.
|
||||
* |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit
|
||||
* | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1.
|
||||
* | | |This function is only available in transmit operation.
|
||||
* | | |0 = Right channel zero cross detection Disabled.
|
||||
* | | |1 = Right channel zero cross detection Enabled.
|
||||
* |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit
|
||||
* | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1.
|
||||
* | | |This function is only available in transmit operation.
|
||||
* | | |0 = Left channel zero cross detection Disabled.
|
||||
* | | |1 = Left channel zero cross detection Enabled.
|
||||
* |[23] |RXLCH |Receive Left Channel Enable Bit
|
||||
* | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
|
||||
* | | |0 = Receive right channel data in Mono mode.
|
||||
* | | |1 = Receive left channel data in Mono mode.
|
||||
* |[24] |RZCIEN |Right Channel Zero- CCross Interrupt Enable Bit
|
||||
* | | |Interrupt occurs if this bit is set to 1 and right channel zero- cross event occurs.
|
||||
* | | |0 = Interrupt Disabled.
|
||||
* | | |1 = Interrupt Enabled.
|
||||
* |[25] |LZCIEN |Left Channel Zero- CCross Interrupt Enable Bit
|
||||
* | | |Interrupt occurs if this bit is set to 1 and left channel zero- cross event occurs.
|
||||
* | | |0 = Interrupt Disabled.
|
||||
* | | |1 = Interrupt Enabled.
|
||||
* |[29:28] |FORMAT |Data Format Selection
|
||||
* | | |00 = I2S data format.
|
||||
* | | |01 = MSB justified data format.
|
||||
* | | |10 = PCM mode A.
|
||||
* | | |11 = PCM mode B.
|
||||
* @var SPI_T::I2SCLK
|
||||
* Offset: 0x64 I2S Clock Divider Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[6:0] |MCLKDIV |Master Clock Divider
|
||||
* | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices.
|
||||
* | | |The master clock rate, F_MCLK, is determined by the following expressions.
|
||||
* | | |If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)).
|
||||
* | | |If MCLKDIV = 0, F_MCLK = F_I2SCLK.
|
||||
* | | |F_I2SCLK is the frequency of I2S peripheral clock.
|
||||
* | | |In general, the master clock rate is 256 times sampling clock rate.
|
||||
* |[17:8] |BCLKDIV |Bit Clock Divider
|
||||
* | | |The I2S controller will generate bit clock in Master mode.
|
||||
* | | |The bit clock rate, F_BCLK, is determined by the following expression.
|
||||
* | | |F_BCLK = F_I2SCLK /(2x(BCLKDIV + 1)) , where F_I2SCLK is the frequency of I2S peripheral clock.
|
||||
* @var SPI_T::I2SSTS
|
||||
* Offset: 0x68 I2S Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[4] |RIGHT |Right Channel (Read Only)
|
||||
* | | |This bit indicates the current transmit data is belong to which channel.
|
||||
* | | |0 = Left channel.
|
||||
* | | |1 = Right channel.
|
||||
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
|
||||
* | | |0 = Receive FIFO buffer is not empty.
|
||||
* | | |1 = Receive FIFO buffer is empty.
|
||||
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
|
||||
* | | |0 = Receive FIFO buffer is not full.
|
||||
* | | |1 = Receive FIFO buffer is full.
|
||||
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
|
||||
* | | |0 = The valid data count within the Rxreceive FIFO buffer is smaller than or equal to the setting value of RXTH.
|
||||
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
|
||||
* | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
|
||||
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
|
||||
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
|
||||
* | | |Note: This bit will be cleared by writing 1 to it.
|
||||
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
|
||||
* | | |0 = No receive FIFO time-out event.
|
||||
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode.
|
||||
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
|
||||
* | | |Note: This bit will be cleared by writing 1 to it.
|
||||
* |[15] |I2SENSTS |I2S Enable Status (Read Only)
|
||||
* | | |0 = The SPI/I2S control logic is disabled.
|
||||
* | | |1 = The SPI/I2S control logic is enabled.
|
||||
* | | |Note: The SPI peripheral clock is asynchronous with the system clock
|
||||
* | | |In order to make sure the SPI/I2S controller logic is disabled, this bit indicates the real status of SPI/I2S controller logic for user.
|
||||
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
|
||||
* | | |0 = Transmit FIFO buffer is not empty.
|
||||
* | | |1 = Transmit FIFO buffer is empty.
|
||||
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
|
||||
* | | |0 = Transmit FIFO buffer is not full.
|
||||
* | | |1 = Transmit FIFO buffer is full.
|
||||
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
|
||||
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
|
||||
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
|
||||
* | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
|
||||
* |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag
|
||||
* | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.
|
||||
* | | |Note: This bit will be cleared by writing 1 to it.
|
||||
* |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag
|
||||
* | | |0 = No zero cross event occurred on right channel.
|
||||
* | | |1 = Zero cross event occurred on right channel.
|
||||
* |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag
|
||||
* | | |0 = No zero cross event occurred on left channel.
|
||||
* | | |1 = Zero cross event occurred on left channel.
|
||||
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
|
||||
* | | |0 = The reset function of TXRST or RXRST is done.
|
||||
* | | |1 = Doing the reset function of TXRST or RXRST.
|
||||
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles.
|
||||
* | | |User can check the status of this bit to monitor the reset function is doing or done.
|
||||
* |[26:24] |RXCNT |Receive FIFO Data Count (Read Only)
|
||||
* | | |This bit field indicates the valid data count of receive FIFO buffer.
|
||||
* |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only)
|
||||
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
|
||||
*/
|
||||
|
||||
__IO uint32_t CTL; /*!< [0x0000] SPI Control Register */
|
||||
__IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */
|
||||
__IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */
|
||||
__IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */
|
||||
__IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */
|
||||
__IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */
|
||||
__I uint32_t RESERVE0[2];
|
||||
__O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */
|
||||
__I uint32_t RESERVE1[3];
|
||||
__I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */
|
||||
__I uint32_t RESERVE2[5]; /*!< [0x0034] Reserved */
|
||||
__IO uint32_t INTERNAL; /*!< [0x0048] SPI Internal Control Register */
|
||||
__I uint32_t RESERVE3; /*!< [0x004C] Reserved */
|
||||
__I uint32_t VER_NUM; /*!< [0x0050] SPI Version Number Register */
|
||||
__I uint32_t RESERVE4[3]; /*!< [0x0054] Reserved */
|
||||
__IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */
|
||||
__IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */
|
||||
__IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */
|
||||
|
||||
} SPI_T;
|
||||
|
||||
/**
|
||||
@addtogroup SPI_CONST SPI Bit Field Definition
|
||||
Constant Definitions for SPI Controller
|
||||
@{ */
|
||||
|
||||
#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */
|
||||
#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */
|
||||
|
||||
#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */
|
||||
#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */
|
||||
|
||||
#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */
|
||||
#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */
|
||||
|
||||
#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */
|
||||
#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */
|
||||
|
||||
#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */
|
||||
#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */
|
||||
|
||||
#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */
|
||||
#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */
|
||||
|
||||
#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */
|
||||
#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */
|
||||
|
||||
#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */
|
||||
#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */
|
||||
|
||||
#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */
|
||||
#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */
|
||||
|
||||
#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */
|
||||
#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */
|
||||
|
||||
#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */
|
||||
#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */
|
||||
|
||||
#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */
|
||||
#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */
|
||||
|
||||
#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */
|
||||
#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */
|
||||
|
||||
#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */
|
||||
#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */
|
||||
|
||||
#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */
|
||||
#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */
|
||||
|
||||
#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */
|
||||
#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */
|
||||
|
||||
#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */
|
||||
#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */
|
||||
|
||||
#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */
|
||||
#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */
|
||||
|
||||
#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */
|
||||
#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */
|
||||
|
||||
#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */
|
||||
#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */
|
||||
|
||||
#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */
|
||||
#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */
|
||||
|
||||
#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */
|
||||
#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */
|
||||
|
||||
#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */
|
||||
#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */
|
||||
|
||||
#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */
|
||||
#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */
|
||||
|
||||
#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */
|
||||
#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */
|
||||
|
||||
#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */
|
||||
#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */
|
||||
|
||||
#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */
|
||||
#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */
|
||||
|
||||
#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */
|
||||
#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */
|
||||
|
||||
#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */
|
||||
#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */
|
||||
|
||||
#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */
|
||||
#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */
|
||||
|
||||
#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */
|
||||
#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */
|
||||
|
||||
#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */
|
||||
#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */
|
||||
|
||||
#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */
|
||||
#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */
|
||||
|
||||
#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */
|
||||
#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */
|
||||
|
||||
#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */
|
||||
#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */
|
||||
|
||||
#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */
|
||||
#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */
|
||||
|
||||
#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */
|
||||
#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */
|
||||
|
||||
#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */
|
||||
#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */
|
||||
|
||||
#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */
|
||||
#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */
|
||||
|
||||
#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */
|
||||
#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */
|
||||
|
||||
#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */
|
||||
#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */
|
||||
|
||||
#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */
|
||||
#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */
|
||||
|
||||
#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */
|
||||
#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */
|
||||
|
||||
#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */
|
||||
#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */
|
||||
|
||||
#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */
|
||||
#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */
|
||||
|
||||
#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */
|
||||
#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */
|
||||
|
||||
#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */
|
||||
#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */
|
||||
|
||||
#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */
|
||||
#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */
|
||||
|
||||
#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */
|
||||
#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */
|
||||
|
||||
#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */
|
||||
#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */
|
||||
|
||||
#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */
|
||||
#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */
|
||||
|
||||
#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */
|
||||
#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */
|
||||
|
||||
#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */
|
||||
#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */
|
||||
|
||||
#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */
|
||||
#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */
|
||||
|
||||
#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */
|
||||
#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */
|
||||
|
||||
#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */
|
||||
#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */
|
||||
|
||||
#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */
|
||||
#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */
|
||||
|
||||
#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */
|
||||
#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */
|
||||
|
||||
#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */
|
||||
#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */
|
||||
|
||||
#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */
|
||||
#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */
|
||||
|
||||
#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */
|
||||
#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */
|
||||
|
||||
#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */
|
||||
#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */
|
||||
|
||||
#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */
|
||||
#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */
|
||||
|
||||
#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */
|
||||
#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */
|
||||
|
||||
#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */
|
||||
#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */
|
||||
|
||||
#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */
|
||||
#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */
|
||||
|
||||
#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */
|
||||
#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */
|
||||
|
||||
#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */
|
||||
#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */
|
||||
|
||||
#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */
|
||||
#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */
|
||||
|
||||
#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */
|
||||
#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */
|
||||
|
||||
#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */
|
||||
#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */
|
||||
|
||||
#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */
|
||||
#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */
|
||||
|
||||
#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */
|
||||
#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */
|
||||
|
||||
#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */
|
||||
#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */
|
||||
|
||||
#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */
|
||||
#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */
|
||||
|
||||
#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */
|
||||
#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */
|
||||
|
||||
#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */
|
||||
#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */
|
||||
|
||||
#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */
|
||||
#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */
|
||||
|
||||
#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */
|
||||
#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */
|
||||
|
||||
#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */
|
||||
#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */
|
||||
|
||||
#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */
|
||||
#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */
|
||||
|
||||
#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */
|
||||
#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */
|
||||
|
||||
#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */
|
||||
#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */
|
||||
|
||||
#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */
|
||||
#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */
|
||||
|
||||
#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */
|
||||
#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */
|
||||
|
||||
#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */
|
||||
#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */
|
||||
|
||||
#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */
|
||||
#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */
|
||||
|
||||
#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */
|
||||
#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */
|
||||
|
||||
#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */
|
||||
#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */
|
||||
|
||||
#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */
|
||||
#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */
|
||||
|
||||
#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */
|
||||
#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */
|
||||
|
||||
/**@}*/ /* SPI_CONST */
|
||||
/**@}*/ /* end of SPI register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __SPI_REG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,105 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file system_M031Series.h
|
||||
* @version V3.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 18/05/29 5:31p $
|
||||
* @brief M031 Series System Setting Header File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
******************************************************************************/
|
||||
#ifndef __SYSTEM_M031_H__
|
||||
#define __SYSTEM_M031_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Macro Definition */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#ifndef DEBUG_PORT
|
||||
#define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
|
||||
#endif
|
||||
|
||||
/**
|
||||
*
|
||||
* @details This is used to enable PLL to speed up booting at startup. Remove it will cause system using
|
||||
* default clock source (External crystal or internal 22.1184MHz IRC).
|
||||
* Enable this option will cause system booting in 72MHz(By XTAL) or 71.8848MHz(By IRC22M) according to
|
||||
* user configuration setting in CONFIG0
|
||||
*
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define SYSCLK
|
||||
*----------------------------------------------------------------------------*/
|
||||
#ifndef __HXT
|
||||
#define __HXT (32000000UL) /*!< External Crystal Clock Frequency */
|
||||
#endif /*!defined(__HXT) */
|
||||
|
||||
#ifndef __LXT
|
||||
#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
|
||||
#endif /*!defined(__LXT) */
|
||||
|
||||
#define __LIRC (38400UL) /*!< Internal 38.4KHz RC Oscillator Frequency */
|
||||
#define __HIRC (48000000UL) /*!< Internal 48M RC Oscillator Frequency */
|
||||
#define __HSI (96000000UL) /*!< PLL default output is 96MHz from HIRC */
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
|
||||
extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
|
||||
|
||||
#if USE_ASSERT
|
||||
/**
|
||||
* @brief Assert Function
|
||||
*
|
||||
* @param[in] expr Expression to be evaluated
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details If the expression is false, an error message will be printed out
|
||||
* from debug port (UART0 or UART1).
|
||||
*/
|
||||
#define ASSERT_PARAM(expr) { if (!(expr)) { AssertError((uint8_t*)__FILE__, __LINE__); } }
|
||||
|
||||
void AssertError(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define ASSERT_PARAM(expr)
|
||||
#endif
|
||||
|
||||
#define assert_param(expr) ASSERT_PARAM(expr)
|
||||
|
||||
|
||||
/**
|
||||
* @brief System Initialization
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The necessary initialization of system.
|
||||
*/
|
||||
extern void SystemInit(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update the Variable SystemCoreClock
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to update the variable SystemCoreClock
|
||||
* and must be called whenever the core clock is changed.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. */
|
||||
|
|
@ -1,336 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file timer_reg.h
|
||||
* @version V1.00
|
||||
* @brief TIMER register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __TIMER_REG_H__
|
||||
#define __TIMER_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup TIMER Timer Controller (TIMER)
|
||||
Memory Mapped Structure for TIMER Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var TIMER_T::CTL
|
||||
* Offset: 0x00/0x20 Timer0~3 Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7:0] |PSC |Prescale Counter
|
||||
* | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter. If this field is 0 (PSC = 0), then there is no scaling.
|
||||
* | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
|
||||
* |[8] |TRGPDMA |Trigger PDMA Enable Bit
|
||||
* | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.
|
||||
* | | |0 = Timer interrupt trigger PDMA Disabled.
|
||||
* | | |1 = Timer interrupt trigger PDMA Enabled.
|
||||
* | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger PDMA. If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger PDMA.
|
||||
* |[9] |TRGBPWM |Trigger BPWM Enable Bit
|
||||
* | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM.
|
||||
* | | |0 = Timer interrupt trigger BPWM Disabled.
|
||||
* | | |1 = Timer interrupt trigger BPWM Enabled.
|
||||
* | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger BPWM. If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger BPWM.
|
||||
* |[10] |INTRGEN |Inter-timer Trigger Mode Enable Bit
|
||||
* | | |Setting this bit will enable the inter-timer trigger capture function.
|
||||
* | | |The Timer0/2 will be in event counter mode and counting with external clock source or event. Also, Timer1/3 will be in trigger-counting mode of capture function.
|
||||
* | | |0 = Inter-Timer Trigger mode Disabled.
|
||||
* | | |1 = Inter-Timer Trigger mode Enabled.
|
||||
* | | |Note: For Timer1/3, this bit is ignored and the read back value is always 0.
|
||||
* |[16] |CAPSRC |Capture Pin Source Selection
|
||||
* | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin.
|
||||
* | | |1 = Capture Function source is from internal ACMP output signal or LIRC. User can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which internal ACMP output signal or LIRC as timer capture source.
|
||||
* |[18] |TRGSSEL |Trigger Source Select Bit
|
||||
* | | |This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.
|
||||
* | | |0 = Timer time-out interrupt signal is used to trigger PWM, ADC and PDMA.
|
||||
* | | |1 = Capture interrupt signal is used to trigger PWM, ADC and PDMA.
|
||||
* |[19] |TRGPWM |Trigger PWM Enable Bit
|
||||
* | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM.
|
||||
* | | |0 = Timer interrupt trigger PWM Disabled.
|
||||
* | | |1 = Timer interrupt trigger PWM Enabled.
|
||||
* | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger PWM. If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger PWM.
|
||||
* |[21] |TRGADC |Trigger ADC Enable Bit
|
||||
* | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.
|
||||
* | | |0 = Timer interrupt trigger ADC Disabled.
|
||||
* | | |1 = Timer interrupt trigger ADC Enabled.
|
||||
* | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger ADC. If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger ADC.
|
||||
* |[22] |TGLPINSEL |Toggle-output Pin Select
|
||||
* | | |0 = Toggle mode output to Tx (Timer Event Counter Pin).
|
||||
* | | |1 = Toggle mode output to Tx_EXT (Timer External Capture Pin).
|
||||
* |[23] |WKEN |Wake-up Function Enable Bit
|
||||
* | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
|
||||
* | | |0 = Wake-up function Disabled if timer interrupt signal generated.
|
||||
* | | |1 = Wake-up function Enabled if timer interrupt signal generated.
|
||||
* |[24] |EXTCNTEN |Event Counter Mode Enable Bit
|
||||
* | | |This bit is for external counting pin function enabled.
|
||||
* | | |0 = Event counter mode Disabled.
|
||||
* | | |1 = Event counter mode Enabled.
|
||||
* | | |Note1: When timer is used as an event counter, this bit should be set to 1 and select PCLKx (x=0~1) as timer clock source.
|
||||
* | | |Note2: When TMR0/TMR2 INTRGEN is set to 1, this bit is forced to 1. When INTRGEN is 1 and TMR1/TMR3 CAPIF (TIMERx_EINTSTS[0]) is 1, this bit is forced to 0.
|
||||
* |[25] |ACTSTS |Timer Active Status Bit (Read Only)
|
||||
* | | |This bit indicates the 24-bit up counter status.
|
||||
* | | |0 = 24-bit up counter is not active.
|
||||
* | | |1 = 24-bit up counter is active.
|
||||
* | | |Note: This bit may active when CNT 0 transition to CNT 1.
|
||||
* |[26] |RSTCNT |Timer Counter Reset Bit
|
||||
* | | |Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit.
|
||||
* | | |Note: This bit will be auto cleared.
|
||||
* |[28:27] |OPMODE |Timer Counting Mode Select
|
||||
* | | |00 = The timer controller is operated in One-shot mode.
|
||||
* | | |01 = The timer controller is operated in Periodic mode.
|
||||
* | | |10 = The timer controller is operated in Toggle-output mode.
|
||||
* | | |11 = The timer controller is operated in Continuous Counting mode.
|
||||
* |[29] |INTEN |Timer Interrupt Enable Bit
|
||||
* | | |0 = Timer time-out interrupt Disabled.
|
||||
* | | |1 = Timer time-out interrupt Enabled.
|
||||
* | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
|
||||
* |[30] |CNTEN |Timer Counting Enable Bit
|
||||
* | | |0 = Stops/Suspends counting.
|
||||
* | | |1 = Starts counting.
|
||||
* | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
|
||||
* | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
|
||||
* | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
|
||||
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
|
||||
* | | |0 = ICE debug mode acknowledgement effects TIMER counting.
|
||||
* | | |TIMER counter will be held while CPU is held by ICE.
|
||||
* | | |1 = ICE debug mode acknowledgement Disabled.
|
||||
* | | |TIMER counter will keep going no matter CPU is held by ICE or not.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* @var TIMER_T::CMP
|
||||
* Offset: 0x04/0x24 Timer0~3 Comparator Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[23:0] |CMPDAT |Timer Comparator Value
|
||||
* | | |CMPDAT is a 24-bit compared value register
|
||||
* | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
|
||||
* | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
|
||||
* | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
|
||||
* | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
|
||||
* @var TIMER_T::INTSTS
|
||||
* Offset: 0x08/0x28 Timer0~3 Interrupt Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |TIF |Timer Interrupt Flag
|
||||
* | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = CNT value matches the CMPDAT value.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* |[1] |TWKF |Timer Wake-up Flag
|
||||
* | | |This bit indicates the interrupt wake-up flag status of timer.
|
||||
* | | |0 = Timer does not cause CPU wake-up.
|
||||
* | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* @var TIMER_T::CNT
|
||||
* Offset: 0x0C/0x2C Timer0~3 Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[23:0] |CNT |Timer Data Register
|
||||
* | | |Read this register to get CNT value. For example:
|
||||
* | | |If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.
|
||||
* | | |If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
|
||||
* @var TIMER_T::CAP
|
||||
* Offset: 0x10/0x30 Timer0~3 Capture Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[23:0] |CAPDAT |Timer Capture Data Register
|
||||
* | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
|
||||
* @var TIMER_T::EXTCTL
|
||||
* Offset: 0x14/0x34 Timer0~3 External Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CNTPHASE |Timer External Count Phase
|
||||
* | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3).
|
||||
* | | |0 = A falling edge of external counting pin will be counted.
|
||||
* | | |1 = A rising edge of external counting pin will be counted.
|
||||
* |[2:1] |CAPEDGE |Timer External Capture Pin Edge Detect
|
||||
* | | |00 = A Falling edge on Tx_EXT (x= 0~3) pin, LIRC or ACMPx (x=0~1) will be detected.
|
||||
* | | |01 = A Rising edge on Tx_EXT (x= 0~3) pin, LIRC or ACMPx (x=0~1) will be detected.
|
||||
* | | |10 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin, LIRC or ACMPx (x=0~1) will be detected.
|
||||
* | | |11 = Reserved.
|
||||
* |[3] |CAPEN |Timer Capture Enable Bit
|
||||
* | | |This bit enables the capture input function.
|
||||
* | | |0 =Capture source Disabled.
|
||||
* | | |1 =Capture source Enabled.
|
||||
* | | |Note: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled.
|
||||
* |[4] |CAPFUNCS |Capture Function Selection
|
||||
* | | |0 = External Capture Mode Enabled.
|
||||
* | | |1 = External Reset Mode Enabled.
|
||||
* | | |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field.
|
||||
* | | |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately.
|
||||
* |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit
|
||||
* | | |0 = TMx_EXT (x= 0~3) pin, LIRC, or ACMP detection Interrupt Disabled.
|
||||
* | | |1 = TMx_EXT (x= 0~3) pin, LIRC, or ACMP detection Interrupt Enabled.
|
||||
* | | |Note: CAPIEN is used to enable timer external interrupt
|
||||
* | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
|
||||
* | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the Tx_EXT (x= 0~3) pin, or ACMP will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
|
||||
* |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit
|
||||
* | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled.
|
||||
* | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled.
|
||||
* | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
|
||||
* |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit
|
||||
* | | |0 = TMx (x= 0~3) pin de-bounce Disabled.
|
||||
* | | |1 = TMx (x= 0~3) pin de-bounce Enabled.
|
||||
* | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
|
||||
* |[10:8] |INTERCAPSEL|Internal Capture Source Selection to Trigger Capture Function
|
||||
* | | |000 = Capture Function source is from internal ACMP0 output signal.
|
||||
* | | |001 = Capture Function source is from internal ACMP1 output signal.
|
||||
* | | |101 = Capture Function source is from LIRC.
|
||||
* | | |Others = Reserved.
|
||||
* | | |Note: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1.
|
||||
* |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function
|
||||
* | | |0 = Event Counter input source is from TMx (x= 0~3) pin.
|
||||
* | | |1 = Event Counter input source is from USB internal SOF output signal.
|
||||
* @var TIMER_T::EINTSTS
|
||||
* Offset: 0x18/0x38 Timer0~3 External Interrupt Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CAPIF |Timer External Capture Interrupt Flag
|
||||
* | | |This bit indicates the timer external capture interrupt flag status.
|
||||
* | | |0 = TMx_EXT (x= 0~3) pin interrupt did not occur.
|
||||
* | | |1 = TMx_EXT (x= 0~3) pin interrupt occurred.
|
||||
* | | |Note1: This bit is cleared by writing 1 to it.
|
||||
* | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
|
||||
* | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] Timer0 Control Register */
|
||||
__IO uint32_t CMP; /*!< [0x0004] Timer0 Comparator Register */
|
||||
__IO uint32_t INTSTS; /*!< [0x0008] Timer0 Interrupt Status Register */
|
||||
__I uint32_t CNT; /*!< [0x000c] Timer0 Data Register */
|
||||
__I uint32_t CAP; /*!< [0x0010] Timer0 Capture Data Register */
|
||||
__IO uint32_t EXTCTL; /*!< [0x0014] Timer0 External Control Register */
|
||||
__IO uint32_t EINTSTS; /*!< [0x0018] Timer0 External Interrupt Status Register */
|
||||
} TIMER_T;
|
||||
|
||||
/**
|
||||
@addtogroup TIMER_CONST TIMER Bit Field Definition
|
||||
Constant Definitions for TIMER Controller
|
||||
@{ */
|
||||
|
||||
#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */
|
||||
#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */
|
||||
|
||||
#define TIMER_CTL_TRGPDMA_Pos (8) /*!< TIMER_T::CTL: TRGPDMA Position */
|
||||
#define TIMER_CTL_TRGPDMA_Msk (0x1ul << TIMER_CTL_TRGPDMA_Pos) /*!< TIMER_T::CTL: TRGPDMA Mask */
|
||||
|
||||
#define TIMER_CTL_TRGBPWM_Pos (9) /*!< TIMER_T::CTL: TRGBPWM Position */
|
||||
#define TIMER_CTL_TRGBPWM_Msk (0x1ul << TIMER_CTL_TRGBPWM_Pos) /*!< TIMER_T::CTL: TRGBPWM Mask */
|
||||
|
||||
#define TIMER_CTL_INTRGEN_Pos (10) /*!< TIMER_T::CTL: INTRGEN Position */
|
||||
#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */
|
||||
|
||||
#define TIMER_CTL_CAPSRC_Pos (16) /*!< TIMER_T::CTL: CAPSRC Position */
|
||||
#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */
|
||||
|
||||
#define TIMER_CTL_TRGSSEL_Pos (18) /*!< TIMER_T::CTL: TRGSSEL Position */
|
||||
#define TIMER_CTL_TRGSSEL_Msk (0x1ul << TIMER_CTL_TRGSSEL_Pos) /*!< TIMER_T::CTL: TRGSSEL Mask */
|
||||
|
||||
#define TIMER_CTL_TRGPWM_Pos (19) /*!< TIMER_T::CTL: TRGPWM Position */
|
||||
#define TIMER_CTL_TRGPWM_Msk (0x1ul << TIMER_CTL_TRGPWM_Pos) /*!< TIMER_T::CTL: TRGPWM Mask */
|
||||
|
||||
#define TIMER_CTL_TRGADC_Pos (21) /*!< TIMER_T::CTL: TRGADC Position */
|
||||
#define TIMER_CTL_TRGADC_Msk (0x1ul << TIMER_CTL_TRGADC_Pos) /*!< TIMER_T::CTL: TRGADC Mask */
|
||||
|
||||
#define TIMER_CTL_TGLPINSEL_Pos (22) /*!< TIMER_T::CTL: TGLPINSEL Position */
|
||||
#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */
|
||||
|
||||
#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */
|
||||
#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */
|
||||
|
||||
#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */
|
||||
#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */
|
||||
|
||||
#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */
|
||||
#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */
|
||||
|
||||
#define TIMER_CTL_RSTCNT_Pos (26) /*!< TIMER_T::CTL: RSTCNT Position */
|
||||
#define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) /*!< TIMER_T::CTL: RSTCNT Mask */
|
||||
|
||||
#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */
|
||||
#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */
|
||||
|
||||
#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */
|
||||
#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */
|
||||
|
||||
#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */
|
||||
#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */
|
||||
|
||||
#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */
|
||||
#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */
|
||||
|
||||
#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */
|
||||
#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */
|
||||
|
||||
#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */
|
||||
#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */
|
||||
|
||||
#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */
|
||||
#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */
|
||||
|
||||
#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */
|
||||
#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */
|
||||
|
||||
#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */
|
||||
#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */
|
||||
|
||||
#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */
|
||||
#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */
|
||||
|
||||
#define TIMER_EXTCTL_CAPEDGE_Pos (1) /*!< TIMER_T::EXTCTL: CAPEDGE Position */
|
||||
#define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */
|
||||
|
||||
#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */
|
||||
#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */
|
||||
|
||||
#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */
|
||||
#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */
|
||||
|
||||
#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */
|
||||
#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */
|
||||
|
||||
#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */
|
||||
#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */
|
||||
|
||||
#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */
|
||||
#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */
|
||||
|
||||
#define TIMER_EXTCTL_INTERCAPSEL_Pos (8) /*!< TIMER_T::EXTCTL: INTERCAPSEL Position */
|
||||
#define TIMER_EXTCTL_INTERCAPSEL_Msk (0x7ul << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< TIMER_T::EXTCTL: INTERCAPSEL Mask */
|
||||
|
||||
#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */
|
||||
#define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */
|
||||
|
||||
#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */
|
||||
#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */
|
||||
|
||||
/**@}*/ /* TIMER_CONST */
|
||||
/**@}*/ /* end of TIMER register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __TIMER_REG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,570 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file ui2c_reg.h
|
||||
* @version V1.00
|
||||
* @brief UI2C register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __UI2C_REG_H__
|
||||
#define __UI2C_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup UI2C I2C Mode of USCI Controller (UI2C)
|
||||
Memory Mapped Structure for UI2C Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var UI2C_T::CTL
|
||||
* Offset: 0x00 USCI Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[2:0] |FUNMODE |Function Mode
|
||||
* | | |This bit field selects the protocol for this USCI controller.
|
||||
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI.
|
||||
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol.
|
||||
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
|
||||
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
|
||||
* | | |001 = The SPI protocol is selected.
|
||||
* | | |010 = The UART protocol is selected.
|
||||
* | | |100 = The I2C protocol is selected.
|
||||
* | | |Note: Other bit combinations are reserved.
|
||||
* @var UI2C_T::BRGEN
|
||||
* Offset: 0x08 USCI Baud Rate Generator Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |RCLKSEL |Reference Clock Source Selection
|
||||
* | | |This bit selects the source signal of reference clock (fREF_CLK).
|
||||
* | | |0 = Peripheral device clock fPCLK.
|
||||
* | | |1 = Reserved.
|
||||
* |[1] |PTCLKSEL |Protocol Clock Source Selection
|
||||
* | | |This bit selects the source signal of protocol clock (fPROT_CLK).
|
||||
* | | |0 = Reference clock fREF_CLK.
|
||||
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
|
||||
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
|
||||
* | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
|
||||
* | | |00 = fSAMP_CLK = fDIV_CLK.
|
||||
* | | |01 = fSAMP_CLK = fPROT_CLK.
|
||||
* | | |10 = fSAMP_CLK = fSCLK.
|
||||
* | | |11 = fSAMP_CLK = fREF_CLK.
|
||||
* |[4] |TMCNTEN |Time Measurement Counter Enable Bit
|
||||
* | | |This bit enables the 10-bit timing measurement counter.
|
||||
* | | |0 = Time measurement counter is Disabled.
|
||||
* | | |1 = Time measurement counter is Enabled.
|
||||
* |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection
|
||||
* | | |0 = Time measurement counter with fPROT_CLK.
|
||||
* | | |1 = Time measurement counter with fDIV_CLK.
|
||||
* |[9:8] |PDSCNT |Pre-divider for Sample Counter
|
||||
* | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK.
|
||||
* | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
|
||||
* |[14:10] |DSCNT |Denominator for Sample Counter
|
||||
* | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
|
||||
* | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
|
||||
* |[25:16] |CLKDIV |Clock Divider
|
||||
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
|
||||
* @var UI2C_T::LINECTL
|
||||
* Offset: 0x2C USCI Line Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |LSB |LSB First Transmission Selection
|
||||
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
|
||||
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
|
||||
* |[11:8] |DWIDTH |Word Length of Transmission
|
||||
* | | |This bit field defines the data word length (amount of bits) for reception and transmission.
|
||||
* | | |The data word is always right-aligned in the data buffer.
|
||||
* | | |USCI support word length from 4 to 16 bits.
|
||||
* | | |0x0: The data word contains 16 bits located at bit positions [15:0].
|
||||
* | | |0x1: Reserved.
|
||||
* | | |0x2: Reserved.
|
||||
* | | |0x3: Reserved.
|
||||
* | | |0x4: The data word contains 4 bits located at bit positions [3:0].
|
||||
* | | |0x5: The data word contains 5 bits located at bit positions [4:0].
|
||||
* | | |...
|
||||
* | | |0xF: The data word contains 15 bits located at bit positions [14:0].
|
||||
* @var UI2C_T::TXDAT
|
||||
* Offset: 0x30 USCI Transmit Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |TXDAT |Transmit Data
|
||||
* | | |Software can use this bit field to write 16-bit transmit data for transmission.
|
||||
* @var UI2C_T::RXDAT
|
||||
* Offset: 0x34 USCI Receive Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |RXDAT |Received Data
|
||||
* | | |This bit field monitors the received data which stored in receive data buffer.
|
||||
* | | |Note: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
|
||||
* @var UI2C_T::DEVADDR0
|
||||
* Offset: 0x44 USCI Device Address Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[9:0] |DEVADDR |Device Address
|
||||
* | | |In I2C protocol, this bit field contains the programmed slave address.
|
||||
* | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit.
|
||||
* | | |Then the second address byte is also compared to DEVADDR[7:0].
|
||||
* | | |Note1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
|
||||
* | | |Note2: When software set 10'h000, the address can not be used.
|
||||
* @var UI2C_T::DEVADDR1
|
||||
* Offset: 0x48 USCI Device Address Register 1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[9:0] |DEVADDR |Device Address
|
||||
* | | |In I2C protocol, this bit field contains the programmed slave address.
|
||||
* | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit.
|
||||
* | | |Then the second address byte is also compared to DEVADDR[7:0].
|
||||
* | | |Note1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
|
||||
* | | |Note2: When software set 10'h000, the address can not be used.
|
||||
* @var UI2C_T::ADDRMSK0
|
||||
* Offset: 0x4C USCI Device Address Mask Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[9:0] |ADDRMSK |USCI Device Address Mask
|
||||
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register).
|
||||
* | | |1 = Mask Enabled (the received corresponding address bit is don't care).
|
||||
* | | |USCI support multiple address recognition with two address mask register.
|
||||
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
|
||||
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
|
||||
* | | |Note: The wake-up function can not use address mask.
|
||||
* @var UI2C_T::ADDRMSK1
|
||||
* Offset: 0x50 USCI Device Address Mask Register 1
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[9:0] |ADDRMSK |USCI Device Address Mask
|
||||
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register).
|
||||
* | | |1 = Mask Enabled (the received corresponding address bit is don't care).
|
||||
* | | |USCI support multiple address recognition with two address mask register.
|
||||
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
|
||||
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
|
||||
* | | |Note: The wake-up function can not use address mask.
|
||||
* @var UI2C_T::WKCTL
|
||||
* Offset: 0x54 USCI Wake-up Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WKEN |Wake-up Enable Bit
|
||||
* | | |0 = Wake-up function Disabled.
|
||||
* | | |1 = Wake-up function Enabled.
|
||||
* |[1] |WKADDREN |Wake-up Address Match Enable Bit
|
||||
* | | |0 = The chip is woken up according data toggle.
|
||||
* | | |1 = The chip is woken up according address match.
|
||||
* @var UI2C_T::WKSTS
|
||||
* Offset: 0x58 USCI Wake-up Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WKF |Wake-up Flag
|
||||
* | | |When chip is woken up from Power-down mode, this bit is set to 1.
|
||||
* | | |Software can write 1 to clear this bit.
|
||||
* @var UI2C_T::PROTCTL
|
||||
* Offset: 0x5C USCI Protocol Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |GCFUNC |General Call Function
|
||||
* | | |0 = General Call Function Disabled.
|
||||
* | | |1 = General Call Function Enabled.
|
||||
* |[1] |AA |Assert Acknowledge Control
|
||||
* | | |When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter.
|
||||
* | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
|
||||
* |[2] |STO |I2C STOP Control
|
||||
* | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically.
|
||||
* | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode when bus error (UI2C_PROTSTS.ERRIF = 1).
|
||||
* |[3] |STA |I2C START Control
|
||||
* | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
|
||||
* |[4] |ADDR10EN |Address 10-bit Function Enable Bit
|
||||
* | | |0 = Address match 10 bit function Disabled.
|
||||
* | | |1 = Address match 10 bit function Enabled.
|
||||
* |[5] |PTRG |I2C Protocol Trigger (Write Only)
|
||||
* | | |When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested.
|
||||
* | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
|
||||
* | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead.
|
||||
* | | |1 = I2C's stretch active.
|
||||
* |[8] |SCLOUTEN |SCL Output Enable Bit
|
||||
* | | |This bit enables monitor pulling SCL to low.
|
||||
* | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
|
||||
* | | |0 = SCL output will be forced high due to open drain mechanism.
|
||||
* | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt.
|
||||
* |[9] |MONEN |Monitor Mode Enable Bit
|
||||
* | | |This bit enables monitor mode.
|
||||
* | | |In monitor mode the SDA output will be put in high impedance mode.
|
||||
* | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.
|
||||
* | | |0 = The monitor mode Disabled.
|
||||
* | | |1 = The monitor mode Enabled.
|
||||
* | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
|
||||
* |[25:16] |TOCNT |Time-out Clock Cycle
|
||||
* | | |This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear.
|
||||
* | | |The time-out is enable when TOCNT bigger than 0.
|
||||
* | | |Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode.
|
||||
* |[31] |PROTEN |I2C Protocol Enable Bit
|
||||
* | | |0 = I2C Protocol Disabled.
|
||||
* | | |1 = I2C Protocol Enabled.
|
||||
* @var UI2C_T::PROTIEN
|
||||
* Offset: 0x60 USCI Protocol Interrupt Enable Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |TOIEN |Time-out Interrupt Enable Bit
|
||||
* | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event.
|
||||
* | | |0 = The time-out interrupt Disabled.
|
||||
* | | |1 = The time-out interrupt Enabled.
|
||||
* |[1] |STARIEN |START Condition Received Interrupt Enable Bit
|
||||
* | | |This bit enables the generation of a protocol interrupt if a START condition is detected.
|
||||
* | | |0 = The start condition interrupt Disabled.
|
||||
* | | |1 = The start condition interrupt Enabled.
|
||||
* |[2] |STORIEN |STOP Condition Received Interrupt Enable Bit
|
||||
* | | |This bit enables the generation of a protocol interrupt if a STOP condition is detected.
|
||||
* | | |0 = The stop condition interrupt Disabled.
|
||||
* | | |1 = The stop condition interrupt Enabled.
|
||||
* |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Bit
|
||||
* | | |This bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master.
|
||||
* | | |0 = The non - acknowledge interrupt Disabled.
|
||||
* | | |1 = The non - acknowledge interrupt Enabled.
|
||||
* |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Bit
|
||||
* | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
|
||||
* | | |0 = The arbitration lost interrupt Disabled.
|
||||
* | | |1 = The arbitration lost interrupt Enabled.
|
||||
* |[5] |ERRIEN |Error Interrupt Enable Bit
|
||||
* | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERRIF (UI2C_PROTSTS [12])).
|
||||
* | | |0 = The error interrupt Disabled.
|
||||
* | | |1 = The error interrupt Enabled.
|
||||
* |[6] |ACKIEN |Acknowledge Interrupt Enable Bit
|
||||
* | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
|
||||
* | | |0 = The acknowledge interrupt Disabled.
|
||||
* | | |1 = The acknowledge interrupt Enabled.
|
||||
* @var UI2C_T::PROTSTS
|
||||
* Offset: 0x64 USCI Protocol Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[5] |TOIF |Time-out Interrupt Flag
|
||||
* | | |0 = A time-out interrupt status has not occurred.
|
||||
* | | |1 = A time-out interrupt status has occurred.
|
||||
* | | |Note: It is cleared by software writing 1 into this bit.
|
||||
* |[6] |ONBUSY |On Bus Busy
|
||||
* | | |Indicates that a communication is in progress on the bus.
|
||||
* | | |It is set by hardware when a START condition is detected.
|
||||
* | | |It is cleared by hardware when a STOP condition is detected.
|
||||
* | | |0 = The bus is IDLE (both SCLK and SDA High).
|
||||
* | | |1 = The bus is busy.
|
||||
* |[8] |STARIF |Start Condition Received Interrupt Flag
|
||||
* | | |This bit indicates that a start condition or repeated start condition has been detected on master mode.
|
||||
* | | |However, this bit also indicates that a repeated start condition has been detected on slave mode.
|
||||
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.STARIEN = 1.
|
||||
* | | |0 = A start condition has not yet been detected.
|
||||
* | | |1 = A start condition has been detected.
|
||||
* | | |Note: It is cleared by software writing 1 into this bit.
|
||||
* |[9] |STORIF |Stop Condition Received Interrupt Flag
|
||||
* | | |This bit indicates that a stop condition has been detected on the I2C bus lines.
|
||||
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.STORIEN = 1.
|
||||
* | | |0 = A stop condition has not yet been detected.
|
||||
* | | |1 = A stop condition has been detected.
|
||||
* | | |Note1: It is cleared by software writing 1 into this bit.
|
||||
* |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag
|
||||
* | | |This bit indicates that a non - acknowledge has been received in master mode.
|
||||
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.NACKIEN = 1.
|
||||
* | | |0 = A non - acknowledge has not been received.
|
||||
* | | |1 = A non - acknowledge has been received.
|
||||
* | | |Note: It is cleared by software writing 1 into this bit.
|
||||
* |[11] |ARBLOIF |Arbitration Lost Interrupt Flag
|
||||
* | | |This bit indicates that an arbitration has been lost.
|
||||
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.ARBLOIEN = 1.
|
||||
* | | |0 = An arbitration has not been lost.
|
||||
* | | |1 = An arbitration has been lost.
|
||||
* | | |Note: It is cleared by software writing 1 into this bit.
|
||||
* |[12] |ERRIF |Error Interrupt Flag
|
||||
* | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame.
|
||||
* | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
|
||||
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.ERRIEN = 1.
|
||||
* | | |0 = An I2C error has not been detected.
|
||||
* | | |1 = An I2C error has been detected.
|
||||
* | | |Note1: It is cleared by software writing 1 into this bit.
|
||||
* | | |Note2: This bit is set for slave mode, and user must write 1 into STO register to the defined "not addressed" slave mode.
|
||||
* |[13] |ACKIF |Acknowledge Received Interrupt Flag
|
||||
* | | |This bit indicates that an acknowledge has been received in master mode.
|
||||
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.ACKIEN = 1.
|
||||
* | | |0 = An acknowledge has not been received.
|
||||
* | | |1 = An acknowledge has been received.
|
||||
* | | |Note: It is cleared by software writing 1 into this bit.
|
||||
* |[14] |SLASEL |Slave Select Status
|
||||
* | | |This bit indicates that this device has been selected as slave.
|
||||
* | | |0 = The device is not selected as slave.
|
||||
* | | |1 = The device is selected as slave.
|
||||
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
|
||||
* |[15] |SLAREAD |Slave Read Request Status
|
||||
* | | |This bit indicates that a slave read request has been detected.
|
||||
* | | |0 = A slave R/W bit is 1 has not been detected.
|
||||
* | | |1 = A slave R/W bit is 1 has been detected.
|
||||
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
|
||||
* |[16] |WKAKDONE |Wake-up Address Frame Acknowledge Bit Done
|
||||
* | | |0 = The ACK bit cycle of address match frame isn't done.
|
||||
* | | |1 = The ACK bit cycle of address match frame is done in power-down.
|
||||
* | | |Note: This bit can't release when WKUPIF is set.
|
||||
* |[17] |WRSTSWK |Read/Write Status Bit in Address Wake-up Frame
|
||||
* | | |0 = Write command be record on the address match wake-up frame.
|
||||
* | | |1 = Read command be record on the address match wake-up frame.
|
||||
* |[18] |BUSHANG |Bus Hang-up
|
||||
* | | |This bit indicates bus hang-up status.
|
||||
* | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK.
|
||||
* | | |The hang-up counter will count to overflow and set this bit when SDA is low.
|
||||
* | | |The counter will be reset by falling edge of SCL signal.
|
||||
* | | |0 = The bus is normal status for transmission.
|
||||
* | | |1 = The bus is hang-up status for transmission.
|
||||
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
|
||||
* |[19] |ERRARBLO |Error Arbitration Lost
|
||||
* | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor.
|
||||
* | | |The I2C can send start condition when ERRARBLO is set.
|
||||
* | | |Thus this bit doesn't be cared on slave mode.
|
||||
* | | |0 = The bus is normal status for transmission.
|
||||
* | | |1 = The bus is error arbitration lost status for transmission.
|
||||
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
|
||||
* @var UI2C_T::ADMAT
|
||||
* Offset: 0x88 I2C Slave Match Address Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |ADMAT0 |USCI Address 0 Match Status Register
|
||||
* | | |When address 0 is matched, hardware will inform which address used.
|
||||
* | | |This bit will set to 1, and software can write 1 to clear this bit.
|
||||
* |[1] |ADMAT1 |USCI Address 1 Match Status Register
|
||||
* | | |When address 1 is matched, hardware will inform which address used.
|
||||
* | | |This bit will set to 1, and software can write 1 to clear this bit.
|
||||
* @var UI2C_T::TMCTL
|
||||
* Offset: 0x8C I2C Timing Configure Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |STCTL |Setup Time Configure Control
|
||||
* | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.
|
||||
* | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK.
|
||||
* |[24:16] |HTCTL |Hold Time Configure Control
|
||||
* | | |This field is used to generate the delay timing between SCL falling edge SDA edge in
|
||||
* | | |transmission mode.
|
||||
* | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK.
|
||||
* | | |Note: Hold time adjust function can only work in master mode, when slave mode, this field should set as 0.
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
|
||||
__I uint32_t RESERVE0[1];
|
||||
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
|
||||
__I uint32_t RESERVE1[8];
|
||||
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
|
||||
__O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
|
||||
__I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
|
||||
__I uint32_t RESERVE2[3];
|
||||
__IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */
|
||||
__IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */
|
||||
__IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */
|
||||
__IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */
|
||||
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
|
||||
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
|
||||
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
|
||||
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
|
||||
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
|
||||
__I uint32_t RESERVE3[8];
|
||||
__IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */
|
||||
__IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */
|
||||
|
||||
} UI2C_T;
|
||||
|
||||
/**
|
||||
@addtogroup UI2C_CONST UI2C Bit Field Definition
|
||||
Constant Definitions for UI2C Controller
|
||||
@{ */
|
||||
|
||||
#define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */
|
||||
#define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */
|
||||
|
||||
#define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */
|
||||
#define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */
|
||||
|
||||
#define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */
|
||||
#define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */
|
||||
|
||||
#define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */
|
||||
#define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */
|
||||
|
||||
#define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */
|
||||
#define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */
|
||||
|
||||
#define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */
|
||||
#define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */
|
||||
|
||||
#define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */
|
||||
#define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */
|
||||
|
||||
#define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */
|
||||
#define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */
|
||||
|
||||
#define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */
|
||||
#define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */
|
||||
|
||||
#define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */
|
||||
#define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */
|
||||
|
||||
#define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */
|
||||
#define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */
|
||||
|
||||
#define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */
|
||||
#define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */
|
||||
|
||||
#define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */
|
||||
#define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */
|
||||
|
||||
#define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */
|
||||
#define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */
|
||||
|
||||
#define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */
|
||||
#define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */
|
||||
|
||||
#define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */
|
||||
#define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */
|
||||
|
||||
#define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */
|
||||
#define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */
|
||||
|
||||
#define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */
|
||||
#define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */
|
||||
|
||||
#define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */
|
||||
#define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */
|
||||
|
||||
#define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */
|
||||
#define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */
|
||||
|
||||
#define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */
|
||||
#define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */
|
||||
|
||||
#define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */
|
||||
#define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */
|
||||
|
||||
#define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */
|
||||
#define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */
|
||||
|
||||
#define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */
|
||||
#define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */
|
||||
|
||||
#define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */
|
||||
#define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */
|
||||
|
||||
#define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */
|
||||
#define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */
|
||||
|
||||
#define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */
|
||||
#define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */
|
||||
|
||||
#define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */
|
||||
#define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */
|
||||
|
||||
#define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */
|
||||
#define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */
|
||||
|
||||
#define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */
|
||||
#define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */
|
||||
|
||||
#define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */
|
||||
#define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */
|
||||
|
||||
#define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */
|
||||
#define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */
|
||||
|
||||
#define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */
|
||||
#define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */
|
||||
|
||||
#define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */
|
||||
#define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */
|
||||
|
||||
#define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */
|
||||
#define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */
|
||||
|
||||
#define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */
|
||||
#define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */
|
||||
|
||||
#define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */
|
||||
#define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */
|
||||
|
||||
#define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */
|
||||
#define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */
|
||||
|
||||
#define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */
|
||||
#define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */
|
||||
|
||||
#define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */
|
||||
#define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */
|
||||
|
||||
#define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */
|
||||
#define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */
|
||||
|
||||
#define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */
|
||||
#define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */
|
||||
|
||||
#define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */
|
||||
#define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */
|
||||
|
||||
#define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */
|
||||
#define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */
|
||||
|
||||
#define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */
|
||||
#define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */
|
||||
|
||||
#define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */
|
||||
#define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */
|
||||
|
||||
#define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */
|
||||
#define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */
|
||||
|
||||
#define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */
|
||||
#define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */
|
||||
|
||||
#define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */
|
||||
#define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */
|
||||
|
||||
#define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */
|
||||
#define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */
|
||||
|
||||
#define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */
|
||||
#define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */
|
||||
|
||||
#define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */
|
||||
#define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */
|
||||
|
||||
#define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */
|
||||
#define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */
|
||||
|
||||
#define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */
|
||||
#define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */
|
||||
|
||||
#define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */
|
||||
#define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */
|
||||
|
||||
/**@}*/ /* UI2C_CONST */
|
||||
/**@}*/ /* end of UI2C register group */
|
||||
|
||||
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __UI2C_REG_H__ */
|
||||
|
|
@ -1,570 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file usbd_reg.h
|
||||
* @version V1.00
|
||||
* @brief USBD register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __USBD_REG_H__
|
||||
#define __USBD_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup USBD USB Device Controller(USBD)
|
||||
Memory Mapped Structure for USBD Controller
|
||||
@{ */
|
||||
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @var USBD_EP_T::BUFSEG
|
||||
* Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570 Endpoint Buffer Segmentation Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:3] |BUFSEG |Endpoint Buffer Segmentation
|
||||
* | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
|
||||
* | | |USBD_SRAM address + { BUFSEG[8:3], 3'b000}
|
||||
* | | |Where the USBD_SRAM address = USBD_BA+0x100h.
|
||||
* | | |Refer to the section 6.17.5.76.21.5.7 for the endpoint SRAM structure and its description.
|
||||
* @var USBD_EP_T::MXPLD
|
||||
* Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574 Endpoint Maximal Payload Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:0] |MXPLD |Maximal Payload
|
||||
* | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)
|
||||
* | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
|
||||
* | | |(1) When the register is written by CPU,
|
||||
* | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
|
||||
* | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
|
||||
* | | |(2) When the register is read by CPU,
|
||||
* | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
|
||||
* | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
|
||||
* | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
|
||||
* @var USBD_EP_T::CFG
|
||||
* Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578 Endpoint Configuration Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |EPNUM |Endpoint Number
|
||||
* | | |These bits are used to define the endpoint number of the current endpoint.
|
||||
* |[4] |ISOCH |Isochronous Endpoint
|
||||
* | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
|
||||
* | | |0 = No Isochronous endpoint.
|
||||
* | | |1 = Isochronous endpoint.
|
||||
* |[6:5] |STATE |Endpoint STATE
|
||||
* | | |00 = Endpoint is Disabled.
|
||||
* | | |01 = Out endpoint.
|
||||
* | | |10 = IN endpoint.
|
||||
* | | |11 = Undefined.
|
||||
* |[7] |DSQSYNC |Data Sequence Synchronization
|
||||
* | | |0 = DATA0 PID.
|
||||
* | | |1 = DATA1 PID.
|
||||
* | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction.
|
||||
* | | |Hardware will toggle automatically in IN token base on the bit.
|
||||
* |[9] |CSTALL |Clear STALL Response
|
||||
* | | |0 = Disable the device to clear the STALL handshake in setup stage.
|
||||
* | | |1 = Clear the device to response STALL handshake in setup stage.
|
||||
* @var USBD_EP_T::CFGP
|
||||
* Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C Endpoint Set Stall and Clear In/Out Ready Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CLRRDY |Clear Ready
|
||||
* | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data.
|
||||
* | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
|
||||
* | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
|
||||
* | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
|
||||
* | | |This bit is write 1 only and is always 0 when it is read back.
|
||||
* |[1] |SSTALL |Set STALL
|
||||
* | | |0 = Disable the device to response STALL.
|
||||
* | | |1 = Set the device to respond STALL automatically.
|
||||
*/
|
||||
__IO uint32_t BUFSEG; /*!< [0x0000] Endpoint Buffer Segmentation Register */
|
||||
__IO uint32_t MXPLD; /*!< [0x0004] Endpoint Maximal Payload Register */
|
||||
__IO uint32_t CFG; /*!< [0x0008] Endpoint Configuration Register */
|
||||
__IO uint32_t CFGP; /*!< [0x000c] Endpoint Set Stall and Clear In/Out Ready Control Register */
|
||||
|
||||
} USBD_EP_T;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @var USBD_T::INTEN
|
||||
* Offset: 0x00 USB Device Interrupt Enable Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |BUSIEN |Bus Event Interrupt Enable Bit
|
||||
* | | |0 = BUS event interrupt Disabled.
|
||||
* | | |1 = BUS event interrupt Enabled.
|
||||
* |[1] |USBIEN |USB Event Interrupt Enable Bit
|
||||
* | | |0 = USB event interrupt Disabled.
|
||||
* | | |1 = USB event interrupt Enabled.
|
||||
* |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit
|
||||
* | | |0 = VBUS detection Interrupt Disabled.
|
||||
* | | |1 = VBUS detection Interrupt Enabled.
|
||||
* |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit
|
||||
* | | |0 = No-event-wake-up Interrupt Disabled.
|
||||
* | | |1 = No-event-wake-up Interrupt Enabled.
|
||||
* |[4] |SOFIEN |Start of Frame Interrupt Enable Bit
|
||||
* | | |0 = SOF Interrupt Disabled.
|
||||
* | | |1 = SOF Interrupt Enabled.
|
||||
* |[8] |WKEN |Wake-up Function Enable Bit
|
||||
* | | |0 = USB wake-up function Disabled.
|
||||
* | | |1 = USB wake-up function Enabled.
|
||||
* |[15] |INNAKEN |Active NAK Function and Its Status in IN Token
|
||||
* | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 register, so that the USB interrupt event will not be asserted.
|
||||
* | | |1 = IN NAK status will be updated to USBD_EPSTS0 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token.
|
||||
* @var USBD_T::INTSTS
|
||||
* Offset: 0x04 USB Device Interrupt Event Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |BUSIF |BUS Interrupt Status
|
||||
* | | |The BUS event means that there is one of the suspense or the resume function in the bus.
|
||||
* | | |0 = No BUS event occurred.
|
||||
* | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0].
|
||||
* |[1] |USBIF |USB Event Interrupt Status
|
||||
* | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
|
||||
* | | |0 = No USB event occurred.
|
||||
* | | |1 = USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]).
|
||||
* |[2] |VBDETIF |VBUS Detection Interrupt Status
|
||||
* | | |0 = There is not attached/detached event in the USB.
|
||||
* | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2].
|
||||
* |[3] |NEVWKIF |No-event-wake-up Interrupt Status
|
||||
* | | |0 = NEVWK event does not occur.
|
||||
* | | |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3].
|
||||
* |[4] |SOFIF |Start of Frame Interrupt Status
|
||||
* | | |0 = SOF event does not occur.
|
||||
* | | |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4].
|
||||
* |[16] |EPEVT0 |Endpoint 0's USB Event Status
|
||||
* | | |0 = No event occurred in endpoint 0.
|
||||
* | | |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1].
|
||||
* |[17] |EPEVT1 |Endpoint 1's USB Event Status
|
||||
* | | |0 = No event occurred in endpoint 1.
|
||||
* | | |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1].
|
||||
* |[18] |EPEVT2 |Endpoint 2's USB Event Status
|
||||
* | | |0 = No event occurred in endpoint 2.
|
||||
* | | |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1].
|
||||
* |[19] |EPEVT3 |Endpoint 3's USB Event Status
|
||||
* | | |0 = No event occurred in endpoint 3.
|
||||
* | | |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1].
|
||||
* |[20] |EPEVT4 |Endpoint 4's USB Event Status
|
||||
* | | |0 = No event occurred in endpoint 4.
|
||||
* | | |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1].
|
||||
* |[21] |EPEVT5 |Endpoint 5's USB Event Status
|
||||
* | | |0 = No event occurred in endpoint 5.
|
||||
* | | |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1].
|
||||
* |[22] |EPEVT6 |Endpoint 6's USB Event Status
|
||||
* | | |0 = No event occurred in endpoint 6.
|
||||
* | | |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1].
|
||||
* |[23] |EPEVT7 |Endpoint 7's USB Event Status
|
||||
* | | |0 = No event occurred in endpoint 7.
|
||||
* | | |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1].
|
||||
* |[31] |SETUP |Setup Event Status
|
||||
* | | |0 = No Setup event.
|
||||
* | | |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31].
|
||||
* @var USBD_T::FADDR
|
||||
* Offset: 0x08 USB Device Function Address Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[6:0] |FADDR |USB Device Function Address
|
||||
* @var USBD_T::EPSTS
|
||||
* Offset: 0x0C USB Device Endpoint Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7] |OV |Overrun
|
||||
* | | |It indicates that the received data is over the maximum payload number or not.
|
||||
* | | |if received data is over the maximum payload number, the extra data will be ignored.
|
||||
* | | |0 = No overrun.
|
||||
* | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
|
||||
* @var USBD_T::ATTR
|
||||
* Offset: 0x10 USB Device Bus Status and Attribution Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |USBRST |USB Reset Status (Read Only)
|
||||
* | | |0 = Bus no reset.
|
||||
* | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us.
|
||||
* |[1] |SUSPEND |Suspend Status (Read Only)
|
||||
* | | |0 = Bus no suspend.
|
||||
* | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
|
||||
* |[2] |RESUME |Resume Status (Read Only)
|
||||
* | | |0 = No bus resume.
|
||||
* | | |1 = Resume from suspend.
|
||||
* |[3] |TOUT |Time-out Status (Read Only)
|
||||
* | | |When USB Device controller after received setup token or out token, USB controller stay J state to wait data package.
|
||||
* | | |If the waiting time exceeds 18-bit length timing, TOUT flag will be generated.
|
||||
* | | |0 = No time-out.
|
||||
* | | |1 = No Bus response more than 18 bits time.
|
||||
* |[4] |PHYEN |PHY Transceiver Function Enable Bit
|
||||
* | | |0 = PHY transceiver function Disabled.
|
||||
* | | |1 = PHY transceiver function Enabled.
|
||||
* |[5] |RWAKEUP |Remote Wake-up
|
||||
* | | |0 = Release the USB bus from K state.
|
||||
* | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up.
|
||||
* |[7] |USBEN |USB Controller Enable Bit
|
||||
* | | |0 = USB Controller Disabled.
|
||||
* | | |1 = USB Controller Enabled.
|
||||
* |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit
|
||||
* | | |0 = Pull-up resistor in USB_D+ bus Disabled.
|
||||
* | | |1 = Pull-up resistor in USB_D+ bus Active.
|
||||
* |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection
|
||||
* | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
|
||||
* | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
|
||||
* |[11] |LPMACK |LPM Token Acknowledge Enable Bit
|
||||
* | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively.
|
||||
* | | |0= the valid LPM Token will be NYET.
|
||||
* | | |1= the valid LPM Token will be ACK.
|
||||
* |[12] |L1SUSPEND |LPM L1 Suspend (Read Only)
|
||||
* | | |0 = Bus no L1 state suspend.
|
||||
* | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged.
|
||||
* |[13] |L1RESUME |LPM L1 Resume (Read Only)
|
||||
* | | |0 = Bus no LPM L1 state resume.
|
||||
* | | |1 = LPM L1 state Resume from LPM L1 state suspend.
|
||||
* @var USBD_T::VBUSDET
|
||||
* Offset: 0x14 USB Device VBUS Detection Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |VBUSDET |Device VBUS Detection
|
||||
* | | |0 = Controller is not attached to the USB host.
|
||||
* | | |1 = Controller is attached to the USB host.
|
||||
* @var USBD_T::STBUFSEG
|
||||
* Offset: 0x18 SETUP Token Buffer Segmentation Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation
|
||||
* | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
|
||||
* | | |USBD_SRAM address + {STBUFSEG, 3'b000}
|
||||
* | | |Where the USBD_SRAM address = USBD_BA+0x100h.
|
||||
* | | |Note: It is used for SETUP token only.
|
||||
* @var USBD_T::EPSTS0
|
||||
* Offset: 0x20 USB Device Endpoint Status Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |EPSTS0 |Endpoint 0 Status
|
||||
* | | |These bits are used to indicate the current status of this endpoint.
|
||||
* | | |0000 = In ACK.
|
||||
* | | |0001 = In NAK.
|
||||
* | | |0010 = Out Packet Data0 ACK.
|
||||
* | | |0011 = Setup ACK.
|
||||
* | | |0110 = Out Packet Data1 ACK.
|
||||
* | | |0111 = Isochronous transfer end.
|
||||
* |[7:4] |EPSTS1 |Endpoint 1 Status
|
||||
* | | |These bits are used to indicate the current status of this endpoint.
|
||||
* | | |0000 = In ACK.
|
||||
* | | |0001 = In NAK.
|
||||
* | | |0010 = Out Packet Data0 ACK.
|
||||
* | | |0011 = Setup ACK.
|
||||
* | | |0110 = Out Packet Data1 ACK.
|
||||
* | | |0111 = Isochronous transfer end.
|
||||
* |[11:8] |EPSTS2 |Endpoint 2 Status
|
||||
* | | |These bits are used to indicate the current status of this endpoint.
|
||||
* | | |0000 = In ACK.
|
||||
* | | |0001 = In NAK.
|
||||
* | | |0010 = Out Packet Data0 ACK.
|
||||
* | | |0011 = Setup ACK.
|
||||
* | | |0110 = Out Packet Data1 ACK.
|
||||
* | | |0111 = Isochronous transfer end.
|
||||
* |[15:12] |EPSTS3 |Endpoint 3 Status
|
||||
* | | |These bits are used to indicate the current status of this endpoint.
|
||||
* | | |0000 = In ACK.
|
||||
* | | |0001 = In NAK.
|
||||
* | | |0010 = Out Packet Data0 ACK.
|
||||
* | | |0011 = Setup ACK.
|
||||
* | | |0110 = Out Packet Data1 ACK.
|
||||
* | | |0111 = Isochronous transfer end.
|
||||
* |[19:16] |EPSTS4 |Endpoint 4 Status
|
||||
* | | |These bits are used to indicate the current status of this endpoint.
|
||||
* | | |0000 = In ACK.
|
||||
* | | |0001 = In NAK.
|
||||
* | | |0010 = Out Packet Data0 ACK.
|
||||
* | | |0011 = Setup ACK.
|
||||
* | | |0110 = Out Packet Data1 ACK.
|
||||
* | | |0111 = Isochronous transfer end.
|
||||
* |[23:20] |EPSTS5 |Endpoint 5 Status
|
||||
* | | |These bits are used to indicate the current status of this endpoint.
|
||||
* | | |0000 = In ACK.
|
||||
* | | |0001 = In NAK.
|
||||
* | | |0010 = Out Packet Data0 ACK.
|
||||
* | | |0011 = Setup ACK.
|
||||
* | | |0110 = Out Packet Data1 ACK.
|
||||
* | | |0111 = Isochronous transfer end.
|
||||
* |[27:24] |EPSTS6 |Endpoint 6 Status
|
||||
* | | |These bits are used to indicate the current status of this endpoint.
|
||||
* | | |0000 = In ACK.
|
||||
* | | |0001 = In NAK.
|
||||
* | | |0010 = Out Packet Data0 ACK.
|
||||
* | | |0011 = Setup ACK.
|
||||
* | | |0110 = Out Packet Data1 ACK.
|
||||
* | | |0111 = Isochronous transfer end.
|
||||
* |[31:28] |EPSTS7 |Endpoint 7 Status
|
||||
* | | |These bits are used to indicate the current status of this endpoint.
|
||||
* | | |0000 = In ACK.
|
||||
* | | |0001 = In NAK.
|
||||
* | | |0010 = Out Packet Data0 ACK.
|
||||
* | | |0011 = Setup ACK.
|
||||
* | | |0110 = Out Packet Data1 ACK.
|
||||
* | | |0111 = Isochronous transfer end.
|
||||
* @var USBD_T::LPMATTR
|
||||
* Offset: 0x88 USB LPM Attribution Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[3:0] |LPMLINKSTS|LPM Link State
|
||||
* | | |These bits contain the bLinkState received with last ACK LPM Token.
|
||||
* |[7:4] |LPMBESL |LPM Best Effort Service Latency
|
||||
* | | |These bits contain the BESL value received with last ACK LPM Token.
|
||||
* |[8] |LPMRWAKUP |LPM Remote Wakeup
|
||||
* | | |This bit contains the bRemoteWake value received with last ACK LPM Token.
|
||||
* @var USBD_T::FN
|
||||
* Offset: 0x8C USB Frame Number Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[10:0] |FN |Frame Number
|
||||
* | | |These bits contain the 11-bits frame number in the last received SOF packet.
|
||||
* @var USBD_T::SE0
|
||||
* Offset: 0x90 USB Device Drive SE0 Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |SE0 |Drive Single Ended Zero in USB Bus
|
||||
* | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
|
||||
* | | |0 = Normal operation.
|
||||
* | | |1 = Force USB PHY transceiver to drive SE0.
|
||||
*/
|
||||
__IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */
|
||||
__IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */
|
||||
__IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */
|
||||
__I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */
|
||||
__IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */
|
||||
__I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */
|
||||
__IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */
|
||||
/// @cond HIDDEN_SYMBOLS
|
||||
__I uint32_t RESERVE0[1];
|
||||
/// @endcond //HIDDEN_SYMBOLS
|
||||
__I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */
|
||||
/// @cond HIDDEN_SYMBOLS
|
||||
__I uint32_t RESERVE1[25];
|
||||
/// @endcond //HIDDEN_SYMBOLS
|
||||
__I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */
|
||||
__I uint32_t FN; /*!< [0x008c] USB Frame number Register */
|
||||
__IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */
|
||||
/// @cond HIDDEN_SYMBOLS
|
||||
__I uint32_t RESERVE2[283];
|
||||
/// @endcond //HIDDEN_SYMBOLS
|
||||
USBD_EP_T EP[8]; /*!< [0x0500~0x5BC] USB Device Endpoints(0~7) */
|
||||
|
||||
} USBD_T;
|
||||
|
||||
/**
|
||||
@addtogroup USBD_CONST USBD Bit Field Definition
|
||||
Constant Definitions for USBD Controller
|
||||
@{ */
|
||||
|
||||
#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */
|
||||
#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */
|
||||
|
||||
#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */
|
||||
#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */
|
||||
|
||||
#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */
|
||||
#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */
|
||||
|
||||
#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */
|
||||
#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */
|
||||
|
||||
#define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */
|
||||
#define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */
|
||||
|
||||
#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */
|
||||
#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */
|
||||
|
||||
#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */
|
||||
#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */
|
||||
|
||||
#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */
|
||||
#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */
|
||||
|
||||
#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */
|
||||
#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */
|
||||
|
||||
#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */
|
||||
#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */
|
||||
|
||||
#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */
|
||||
#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */
|
||||
|
||||
#define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */
|
||||
#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */
|
||||
|
||||
#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */
|
||||
#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */
|
||||
|
||||
#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */
|
||||
#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */
|
||||
|
||||
#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */
|
||||
#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */
|
||||
|
||||
#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */
|
||||
#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */
|
||||
|
||||
#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */
|
||||
#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */
|
||||
|
||||
#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */
|
||||
#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */
|
||||
|
||||
#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */
|
||||
#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */
|
||||
|
||||
#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */
|
||||
#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */
|
||||
|
||||
#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */
|
||||
#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */
|
||||
|
||||
#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */
|
||||
#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */
|
||||
|
||||
#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */
|
||||
#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */
|
||||
|
||||
#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */
|
||||
#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */
|
||||
|
||||
#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */
|
||||
#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */
|
||||
|
||||
#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */
|
||||
#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */
|
||||
|
||||
#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */
|
||||
#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */
|
||||
|
||||
#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */
|
||||
#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */
|
||||
|
||||
#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */
|
||||
#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */
|
||||
|
||||
#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */
|
||||
#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */
|
||||
|
||||
#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */
|
||||
#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */
|
||||
|
||||
#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */
|
||||
#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */
|
||||
|
||||
#define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */
|
||||
#define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */
|
||||
|
||||
#define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */
|
||||
#define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */
|
||||
|
||||
#define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */
|
||||
#define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */
|
||||
|
||||
#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */
|
||||
#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */
|
||||
|
||||
#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */
|
||||
#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */
|
||||
|
||||
#define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */
|
||||
#define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */
|
||||
|
||||
#define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */
|
||||
#define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */
|
||||
|
||||
#define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */
|
||||
#define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */
|
||||
|
||||
#define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */
|
||||
#define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */
|
||||
|
||||
#define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */
|
||||
#define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */
|
||||
#define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */
|
||||
#define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */
|
||||
|
||||
#define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */
|
||||
#define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */
|
||||
|
||||
#define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */
|
||||
#define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */
|
||||
|
||||
#define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */
|
||||
#define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */
|
||||
|
||||
#define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */
|
||||
#define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */
|
||||
|
||||
#define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */
|
||||
#define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */
|
||||
|
||||
#define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */
|
||||
#define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */
|
||||
|
||||
#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */
|
||||
#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */
|
||||
|
||||
#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */
|
||||
#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */
|
||||
|
||||
#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */
|
||||
#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */
|
||||
|
||||
#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */
|
||||
#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */
|
||||
|
||||
#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */
|
||||
#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */
|
||||
|
||||
#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */
|
||||
#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */
|
||||
|
||||
#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */
|
||||
#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */
|
||||
|
||||
#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */
|
||||
#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */
|
||||
|
||||
#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */
|
||||
#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */
|
||||
|
||||
#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */
|
||||
#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */
|
||||
|
||||
/**@}*/ /* USBD_CONST */
|
||||
/**@}*/ /* end of USBD register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __USBD_REG_H__ */
|
||||
|
||||
|
|
@ -1,673 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file uspi_reg.h
|
||||
* @version V1.00
|
||||
* @brief USPI register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __USPI_REG_H__
|
||||
#define __USPI_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup USPI SPI Mode of USCI Controller (USPI)
|
||||
Memory Mapped Structure for USPI Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var USPI_T::CTL
|
||||
* Offset: 0x00 USCI Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[2:0] |FUNMODE |Function Mode
|
||||
* | | |This bit field selects the protocol for this USCI controller.
|
||||
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI.
|
||||
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol.
|
||||
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
|
||||
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
|
||||
* | | |001 = The SPI protocol is selected.
|
||||
* | | |010 = The UART protocol is selected.
|
||||
* | | |100 = The I2C protocol is selected.
|
||||
* | | |Note: Other bit combinations are reserved.
|
||||
* @var USPI_T::INTEN
|
||||
* Offset: 0x04 USCI Interrupt Enable Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit
|
||||
* | | |This bit enables the interrupt generation in case of a transmit start event.
|
||||
* | | |0 = The transmit start interrupt Disabled.
|
||||
* | | |1 = The transmit start interrupt Enabled.
|
||||
* | | |Note: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
|
||||
* |[2] |TXENDIEN |Transmit End Interrupt Enable Bit
|
||||
* | | |This bit enables the interrupt generation in case of a transmit finish event.
|
||||
* | | |0 = The transmit finish interrupt Disabled.
|
||||
* | | |1 = The transmit finish interrupt Enabled.
|
||||
* | | |Note: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit.
|
||||
* |[3] |RXSTIEN |Receive Start Interrupt Enable Bit
|
||||
* | | |This bit enables the interrupt generation in case of a receive start event.
|
||||
* | | |0 = The receive start interrupt Disabled.
|
||||
* | | |1 = The receive start interrupt Enabled.
|
||||
* | | |Note: For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave.
|
||||
* | | |For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
|
||||
* |[4] |RXENDIEN |Receive End Interrupt Enable Bit
|
||||
* | | |This bit enables the interrupt generation in case of a receive finish event.
|
||||
* | | |0 = The receive end interrupt Disabled.
|
||||
* | | |1 = The receive end interrupt Enabled.
|
||||
* | | |Note: The receive finish event happens when hardware receives the last bit of RX data into shift data unit.
|
||||
* @var USPI_T::BRGEN
|
||||
* Offset: 0x08 USCI Baud Rate Generator Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |RCLKSEL |Reference Clock Source Selection
|
||||
* | | |This bit selects the source of reference clock (fREF_CLK).
|
||||
* | | |0 = Peripheral device clock fPCLK.
|
||||
* | | |1 = Reserved.
|
||||
* |[1] |PTCLKSEL |Protocol Clock Source Selection
|
||||
* | | |This bit selects the source of protocol clock (fPROT_CLK).
|
||||
* | | |0 = Reference clock fREF_CLK.
|
||||
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
|
||||
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
|
||||
* | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
|
||||
* | | |00 = fDIV_CLK.
|
||||
* | | |01 = fPROT_CLK.
|
||||
* | | |10 = fSCLK.
|
||||
* | | |11 = fREF_CLK.
|
||||
* |[4] |TMCNTEN |Time Measurement Counter Enable Bit
|
||||
* | | |This bit enables the 10-bit timing measurement counter.
|
||||
* | | |0 = Time measurement counter Disabled.
|
||||
* | | |1 = Time measurement counter Enabled.
|
||||
* |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection
|
||||
* | | |0 = Time measurement counter with fPROT_CLK.
|
||||
* | | |1 = Time measurement counter with fDIV_CLK.
|
||||
* |[25:16] |CLKDIV |Clock Divider
|
||||
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
|
||||
* @var USPI_T::DATIN0
|
||||
* Offset: 0x10 USCI Input Data Signal Configuration Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |SYNCSEL |Input Signal Synchronization Selection
|
||||
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.
|
||||
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
|
||||
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
|
||||
* | | |Note: In SPI protocol, it is suggested this bit should be set as 0.
|
||||
* |[2] |ININV |Input Signal Inverse Selection
|
||||
* | | |This bit defines the inverter enable of the input asynchronous signal.
|
||||
* | | |0 = The un-synchronized input signal will not be inverted.
|
||||
* | | |1 = The un-synchronized input signal will be inverted.
|
||||
* | | |Note: In SPI protocol, it is suggested this bit should be set as 0.
|
||||
* @var USPI_T::CTLIN0
|
||||
* Offset: 0x20 USCI Input Control Signal Configuration Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |SYNCSEL |Input Synchronization Signal Selection
|
||||
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.
|
||||
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
|
||||
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
|
||||
* | | |Note: In SPI protocol, it is suggested this bit should be set as 0.
|
||||
* |[2] |ININV |Input Signal Inverse Selection
|
||||
* | | |This bit defines the inverter enable of the input asynchronous signal.
|
||||
* | | |0 = The un-synchronized input signal will not be inverted.
|
||||
* | | |1 = The un-synchronized input signal will be inverted.
|
||||
* @var USPI_T::CLKIN
|
||||
* Offset: 0x28 USCI Input Clock Signal Configuration Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |SYNCSEL |Input Synchronization Signal Selection
|
||||
* | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.
|
||||
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
|
||||
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
|
||||
* | | |Note: In SPI protocol, it is suggested this bit should be set as 0.
|
||||
* @var USPI_T::LINECTL
|
||||
* Offset: 0x2C USCI Line Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |LSB |LSB First Transmission Selection
|
||||
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
|
||||
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
|
||||
* |[5] |DATOINV |Data Output Inverse Selection
|
||||
* | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.
|
||||
* | | |0 = Data output values of USCIx_DAT0/1 pins are not inverted.
|
||||
* | | |1 = Data output values of USCIx_DAT0/1 pins are inverted.
|
||||
* |[7] |CTLOINV |Control Signal Output Inverse Selection
|
||||
* | | |This bit defines the relation between the internal control signal and the output control signal.
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = The control signal will be inverted before its output.
|
||||
* | | |Note: The control signal has different definitions in different protocol.
|
||||
* | | |In SPI protocol, the control signal means slave select signal.
|
||||
* |[11:8] |DWIDTH |Word Length of Transmission
|
||||
* | | |This bit field defines the data word length (amount of bits) for reception and transmission.
|
||||
* | | |The data word is always right-aligned in the data buffer.
|
||||
* | | |USCI support word length from 4 to 16 bits.
|
||||
* | | |0x0: The data word contains 16 bits located at bit positions [15:0].
|
||||
* | | |0x1: Reserved.
|
||||
* | | |0x2: Reserved.
|
||||
* | | |0x3: Reserved.
|
||||
* | | |0x4: The data word contains 4 bits located at bit positions [3:0].
|
||||
* | | |0x5: The data word contains 5 bits located at bit positions [4:0].
|
||||
* | | |...
|
||||
* | | |0xF: The data word contains 15 bits located at bit positions [14:0].
|
||||
* @var USPI_T::TXDAT
|
||||
* Offset: 0x30 USCI Transmit Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |TXDAT |Transmit Data
|
||||
* | | |Software can use this bit field to write 16-bit transmit data for transmission.
|
||||
* | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
|
||||
* |[16] |PORTDIR |Port Direction Control
|
||||
* | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer.
|
||||
* | | |It is used to define the direction of the data port pin.
|
||||
* | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously.
|
||||
* | | |0 = The data pin is configured as output mode.
|
||||
* | | |1 = The data pin is configured as input mode.
|
||||
* @var USPI_T::RXDAT
|
||||
* Offset: 0x34 USCI Receive Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |RXDAT |Received Data
|
||||
* | | |This bit field monitors the received data which stored in receive data buffer.
|
||||
* @var USPI_T::BUFCTL
|
||||
* Offset: 0x38 USCI Transmit/Receive Buffer Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[6] |TXUDRIEN |Slave Transmit Under Run Interrupt Enable Bit
|
||||
* | | |0 = Transmit under-run interrupt Disabled.
|
||||
* | | |1 = Transmit under-run interrupt Enabled.
|
||||
* |[7] |TXCLR |Clear Transmit Buffer
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = The transmit buffer is cleared.
|
||||
* | | |Should only be used while the buffer is not taking part in data traffic.
|
||||
* | | |Note: It is cleared automatically after one PCLK cycle.
|
||||
* |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit
|
||||
* | | |0 = Receive overrun interrupt Disabled.
|
||||
* | | |1 = Receive overrun interrupt Enabled.
|
||||
* |[15] |RXCLR |Clear Receive Buffer
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = The receive buffer is cleared.
|
||||
* | | |Should only be used while the buffer is not taking part in data traffic.
|
||||
* | | |Note: It is cleared automatically after one PCLK cycle.
|
||||
* |[16] |TXRST |Transmit Reset
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
|
||||
* | | |Note1: It is cleared automatically after one PCLK cycle.
|
||||
* | | |Note2: Write 1 to this bit will set the output data pin to zero if USPI_PROTCTL[28]=0.
|
||||
* |[17] |RXRST |Receive Reset
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
|
||||
* | | |Note: It is cleared automatically after one PCLK cycle.
|
||||
* @var USPI_T::BUFSTS
|
||||
* Offset: 0x3C USCI Transmit/Receive Buffer Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |RXEMPTY |Receive Buffer Empty Indicator
|
||||
* | | |0 = Receive buffer is not empty.
|
||||
* | | |1 = Receive buffer is empty.
|
||||
* |[1] |RXFULL |Receive Buffer Full Indicator
|
||||
* | | |0 = Receive buffer is not full.
|
||||
* | | |1 = Receive buffer is full.
|
||||
* |[3] |RXOVIF |Receive Buffer Over-run Interrupt Status
|
||||
* | | |This bit indicates that a receive buffer overrun event has been detected.
|
||||
* | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated.
|
||||
* | | |It is cleared by software writes 1 to this bit.
|
||||
* | | |0 = A receive buffer overrun event has not been detected.
|
||||
* | | |1 = A receive buffer overrun event has been detected.
|
||||
* |[8] |TXEMPTY |Transmit Buffer Empty Indicator
|
||||
* | | |0 = Transmit buffer is not empty.
|
||||
* | | |1 = Transmit buffer is empty and available for the next transmission datum.
|
||||
* |[9] |TXFULL |Transmit Buffer Full Indicator
|
||||
* | | |0 = Transmit buffer is not full.
|
||||
* | | |1 = Transmit buffer is full.
|
||||
* |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status
|
||||
* | | |This bit indicates that a transmit buffer under-run event has been detected.
|
||||
* | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated.
|
||||
* | | |It is cleared by software writes 1 to this bit.
|
||||
* | | |0 = A transmit buffer under-run event has not been detected.
|
||||
* | | |1 = A transmit buffer under-run event has been detected.
|
||||
* @var USPI_T::PDMACTL
|
||||
* Offset: 0x40 USCI PDMA Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |PDMARST |PDMA Reset
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
|
||||
* |[1] |TXPDMAEN |PDMA Transmit Channel Available
|
||||
* | | |0 = Transmit PDMA function Disabled.
|
||||
* | | |1 = Transmit PDMA function Enabled.
|
||||
* |[2] |RXPDMAEN |PDMA Receive Channel Available
|
||||
* | | |0 = Receive PDMA function Disabled.
|
||||
* | | |1 = Receive PDMA function Enabled.
|
||||
* |[3] |PDMAEN |PDMA Mode Enable Bit
|
||||
* | | |0 = PDMA function Disabled.
|
||||
* | | |1 = PDMA function Enabled.
|
||||
* @var USPI_T::WKCTL
|
||||
* Offset: 0x54 USCI Wake-up Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WKEN |Wake-up Enable Bit
|
||||
* | | |0 = Wake-up function Disabled.
|
||||
* | | |1 = Wake-up function Enabled.
|
||||
* |[2] |PDBOPT |Power Down Blocking Option
|
||||
* | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
|
||||
* | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
|
||||
* @var USPI_T::WKSTS
|
||||
* Offset: 0x58 USCI Wake-up Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WKF |Wake-up Flag
|
||||
* | | |When chip is woken up from Power-down mode, this bit is set to 1.
|
||||
* | | |Software can write 1 to clear this bit.
|
||||
* @var USPI_T::PROTCTL
|
||||
* Offset: 0x5C USCI Protocol Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |SLAVE |Slave Mode Selection
|
||||
* | | |0 = Master mode.
|
||||
* | | |1 = Slave mode.
|
||||
* |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only)
|
||||
* | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
|
||||
* | | |0 = 4-wire bi-direction interface.
|
||||
* | | |1 = 3-wire bi-direction interface.
|
||||
* |[2] |SS |Slave Select Control (Master Only)
|
||||
* | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select back to inactive state.
|
||||
* | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal.
|
||||
* | | |Note: In SPI protocol, the internal slave select signal is active high.
|
||||
* |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only)
|
||||
* | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit.
|
||||
* | | |1 = Slave select signal will be generated automatically.
|
||||
* | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.
|
||||
* |[7:6] |SCLKMODE |Serial Bus Clock Mode
|
||||
* | | |This bit field defines the SCLK idle status, data transmit, and data receive edge.
|
||||
* | | |MODE0 = The idle state of SPI clock is low level.
|
||||
* | | |Data is transmitted with falling edge and received with rising edge.
|
||||
* | | |MODE1 = The idle state of SPI clock is low level.
|
||||
* | | |Data is transmitted with rising edge and received with falling edge.
|
||||
* | | |MODE2 = The idle state of SPI clock is high level.
|
||||
* | | |Data is transmitted with rising edge and received with falling edge.
|
||||
* | | |MODE3 = The idle state of SPI clock is high level.
|
||||
* | | |Data is transmitted with falling edge and received with rising edge.
|
||||
* |[11:8] |SUSPITV |Suspend Interval (Master Only)
|
||||
* | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer.
|
||||
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
|
||||
* | | |The default value is 0x3.
|
||||
* | | |The period of the suspend interval is obtained according to the following equation.
|
||||
* | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle
|
||||
* | | |Example:
|
||||
* | | |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle.
|
||||
* | | |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle.
|
||||
* | | |...
|
||||
* | | |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle.
|
||||
* | | |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle.
|
||||
* |[14:12] |TSMSEL |Transmit Data Mode Selection
|
||||
* | | |This bit field describes how receive and transmit data is shifted in and out.
|
||||
* | | |TSMSEL = 000b: Full-duplex SPI.
|
||||
* | | |TSMSEL = 100b: Half-duplex SPI.
|
||||
* | | |Other values are reserved.
|
||||
* | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
|
||||
* |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only)
|
||||
* | | |In Slave mode, this bit field is used for Slave time-out period.
|
||||
* | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event.
|
||||
* | | |Writing 0x0 into this bit field will disable the Slave time-out function.
|
||||
* | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
|
||||
* |[28] |TXUDRPOL |Transmit Under-run Data Polarity (for Slave)
|
||||
* | | |This bit defines the transmitting data value of USCIx_DAT1 when no data is available for transferring.
|
||||
* | | |0 = The output data value is 0 if TX under run event occurs.
|
||||
* | | |1 = The output data value is 1 if TX under run event occurs.
|
||||
* |[31] |PROTEN |SPI Protocol Enable Bit
|
||||
* | | |0 = SPI Protocol Disabled.
|
||||
* | | |1 = SPI Protocol Enabled.
|
||||
* @var USPI_T::PROTIEN
|
||||
* Offset: 0x60 USCI Protocol Interrupt Enable Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
|
||||
* | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
|
||||
* | | |0 = Slave select inactive interrupt generation Disabled.
|
||||
* | | |1 = Slave select inactive interrupt generation Enabled.
|
||||
* |[1] |SSACTIEN |Slave Select Active Interrupt Enable Bit
|
||||
* | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
|
||||
* | | |0 = Slave select active interrupt generation Disabled.
|
||||
* | | |1 = Slave select active interrupt generation Enabled.
|
||||
* |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Bit
|
||||
* | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
|
||||
* | | |0 = The Slave time-out interrupt Disabled.
|
||||
* | | |1 = The Slave time-out interrupt Enabled.
|
||||
* |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
|
||||
* | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]).
|
||||
* | | |Bit count error event occurs.
|
||||
* | | |0 = The Slave mode bit count error interrupt Disabled.
|
||||
* | | |1 = The Slave mode bit count error interrupt Enabled.
|
||||
* @var USPI_T::PROTSTS
|
||||
* Offset: 0x64 USCI Protocol Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1] |TXSTIF |Transmit Start Interrupt Flag
|
||||
* | | |0 = Transmit start event did not occur.
|
||||
* | | |1 = Transmit start event occurred.
|
||||
* | | |Note: It is cleared by software write 1 to this bit.
|
||||
* | | |The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
|
||||
* |[2] |TXENDIF |Transmit End Interrupt Flag
|
||||
* | | |0 = Transmit end event did not occur.
|
||||
* | | |1 = Transmit end event occurred.
|
||||
* | | |Note: It is cleared by software write 1 to this bit.
|
||||
* | | |The transmit end event happens when hardware sends the last bit of TX data from shift data unit.
|
||||
* |[3] |RXSTIF |Receive Start Interrupt Flag
|
||||
* | | |0 = Receive start event did not occur.
|
||||
* | | |1 = Receive start event occurred.
|
||||
* | | |Note: It is cleared by software write 1 to this bit.
|
||||
* | | |For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave.
|
||||
* | | |For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
|
||||
* |[4] |RXENDIF |Receive End Interrupt Flag
|
||||
* | | |0 = Receive end event did not occur.
|
||||
* | | |1 = Receive end event occurred.
|
||||
* | | |Note: It is cleared by software write 1 to this bit.
|
||||
* | | |The receive end event happens when hardware receives the last bit of RX data into shift data unit.
|
||||
* |[5] |SLVTOIF |Slave Time-out Interrupt Flag (for Slave Only)
|
||||
* | | |0 = Slave time-out event did not occur.
|
||||
* | | |1 = Slave time-out event occurred.
|
||||
* | | |Note: It is cleared by software write 1 to this bit.
|
||||
* |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (for Slave Only)
|
||||
* | | |0 = Slave bit count error event did not occur.
|
||||
* | | |1 = Slave bit count error event occurred.
|
||||
* | | |Note: It is cleared by software write 1 to this bit.
|
||||
* | | |If the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]), bit count error event occurs.It is cleared by software write 1 to this bit.
|
||||
* |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (for Slave Only)
|
||||
* | | |This bit indicates that the internal slave select signal has changed to inactive.
|
||||
* | | |It is cleared by software writes 1 to this bit.
|
||||
* | | |0 = The slave select signal has not changed to inactive.
|
||||
* | | |1 = The slave select signal has changed to inactive.
|
||||
* | | |Note: The internal slave select signal is active high.
|
||||
* |[9] |SSACTIF |Slave Select Active Interrupt Flag (for Slave Only)
|
||||
* | | |This bit indicates that the internal slave select signal has changed to active.
|
||||
* | | |It is cleared by software writes one to this bit.
|
||||
* | | |0 = The slave select signal has not changed to active.
|
||||
* | | |1 = The slave select signal has changed to active.
|
||||
* | | |Note: The internal slave select signal is active high.
|
||||
* |[16] |SSLINE |Slave Select Line Bus Status (Read Only)
|
||||
* | | |This bit is only available in Slave mode.
|
||||
* | | |It used to monitor the current status of the input slave select signal on the bus.
|
||||
* | | |0 = The slave select line status is 0.
|
||||
* | | |1 = The slave select line status is 1.
|
||||
* |[17] |BUSY |Busy Status (Read Only)
|
||||
* | | |0 = SPI is in idle state.
|
||||
* | | |1 = SPI is in busy state.
|
||||
* | | |The following listing are the bus busy conditions:
|
||||
* | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0.
|
||||
* | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
|
||||
* | | |c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active.
|
||||
* | | |d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
|
||||
* |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only)
|
||||
* | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1.
|
||||
* | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
|
||||
* | | |0 = Slave transmit under run event does not occur.
|
||||
* | | |1 = Slave transmit under run event occurs.
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
|
||||
__IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */
|
||||
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
|
||||
__I uint32_t RESERVE0[1];
|
||||
__IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */
|
||||
__I uint32_t RESERVE1[3];
|
||||
__IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */
|
||||
__I uint32_t RESERVE2[1];
|
||||
__IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */
|
||||
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
|
||||
__O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
|
||||
__I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
|
||||
__IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */
|
||||
__IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */
|
||||
__IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */
|
||||
__I uint32_t RESERVE3[4];
|
||||
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
|
||||
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
|
||||
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
|
||||
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
|
||||
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
|
||||
|
||||
} USPI_T;
|
||||
|
||||
/**
|
||||
@addtogroup USPI_CONST USPI Bit Field Definition
|
||||
Constant Definitions for USPI Controller
|
||||
@{ */
|
||||
|
||||
#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */
|
||||
#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */
|
||||
|
||||
#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */
|
||||
#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */
|
||||
|
||||
#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */
|
||||
#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */
|
||||
|
||||
#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */
|
||||
#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */
|
||||
|
||||
#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */
|
||||
#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */
|
||||
|
||||
#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */
|
||||
#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */
|
||||
|
||||
#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */
|
||||
#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */
|
||||
|
||||
#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */
|
||||
#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */
|
||||
|
||||
#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */
|
||||
#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */
|
||||
|
||||
#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */
|
||||
#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */
|
||||
|
||||
#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */
|
||||
#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */
|
||||
|
||||
#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */
|
||||
#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */
|
||||
|
||||
#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */
|
||||
#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */
|
||||
|
||||
#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */
|
||||
#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */
|
||||
|
||||
#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */
|
||||
#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */
|
||||
|
||||
#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */
|
||||
#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */
|
||||
|
||||
#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */
|
||||
#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */
|
||||
|
||||
#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */
|
||||
#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */
|
||||
|
||||
#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */
|
||||
#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */
|
||||
|
||||
#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */
|
||||
#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */
|
||||
|
||||
#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */
|
||||
#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */
|
||||
|
||||
#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */
|
||||
#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */
|
||||
|
||||
#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */
|
||||
#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */
|
||||
|
||||
#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */
|
||||
#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */
|
||||
|
||||
#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */
|
||||
#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */
|
||||
|
||||
#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */
|
||||
#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */
|
||||
|
||||
#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */
|
||||
#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */
|
||||
|
||||
#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */
|
||||
#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */
|
||||
|
||||
#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */
|
||||
#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */
|
||||
|
||||
#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */
|
||||
#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */
|
||||
|
||||
#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */
|
||||
#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */
|
||||
|
||||
#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */
|
||||
#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */
|
||||
|
||||
#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */
|
||||
#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */
|
||||
|
||||
#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */
|
||||
#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */
|
||||
|
||||
#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */
|
||||
#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */
|
||||
|
||||
#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */
|
||||
#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */
|
||||
|
||||
#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */
|
||||
#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */
|
||||
|
||||
#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */
|
||||
#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */
|
||||
|
||||
#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */
|
||||
#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */
|
||||
|
||||
#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */
|
||||
#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */
|
||||
|
||||
#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */
|
||||
#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */
|
||||
|
||||
#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */
|
||||
#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */
|
||||
|
||||
#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */
|
||||
#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */
|
||||
|
||||
#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */
|
||||
#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */
|
||||
|
||||
#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */
|
||||
#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */
|
||||
|
||||
#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */
|
||||
#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */
|
||||
|
||||
#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */
|
||||
#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */
|
||||
|
||||
#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */
|
||||
#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */
|
||||
|
||||
#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */
|
||||
#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */
|
||||
|
||||
#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */
|
||||
#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */
|
||||
|
||||
#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */
|
||||
#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */
|
||||
|
||||
#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */
|
||||
#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */
|
||||
|
||||
#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */
|
||||
#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */
|
||||
|
||||
#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */
|
||||
#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */
|
||||
|
||||
#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */
|
||||
#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */
|
||||
|
||||
#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */
|
||||
#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */
|
||||
|
||||
#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */
|
||||
#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */
|
||||
|
||||
#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */
|
||||
#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */
|
||||
|
||||
#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */
|
||||
#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */
|
||||
|
||||
#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */
|
||||
#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */
|
||||
|
||||
#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */
|
||||
#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */
|
||||
|
||||
#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */
|
||||
#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */
|
||||
|
||||
#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */
|
||||
#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */
|
||||
|
||||
#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */
|
||||
#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */
|
||||
|
||||
#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */
|
||||
#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */
|
||||
|
||||
#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */
|
||||
#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */
|
||||
|
||||
#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */
|
||||
#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */
|
||||
|
||||
/**@}*/ /* USPI_CONST */
|
||||
/**@}*/ /* end of USPI register group */
|
||||
|
||||
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __USPI_REG_H__ */
|
||||
|
|
@ -1,666 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file uuart_reg.h
|
||||
* @version V1.00
|
||||
* @brief UUART register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __UUART_REG_H__
|
||||
#define __UUART_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup UUART UART Mode of USCI Controller (UUART)
|
||||
Memory Mapped Structure for UUART Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var UUART_T::CTL
|
||||
* Offset: 0x00 USCI Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[2:0] |FUNMODE |Function Mode
|
||||
* | | |This bit field selects the protocol for this USCI controller.
|
||||
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI.
|
||||
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol.
|
||||
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
|
||||
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
|
||||
* | | |001 = The SPI protocol is selected.
|
||||
* | | |010 = The UART protocol is selected.
|
||||
* | | |100 = The I2C protocol is selected.
|
||||
* | | |Note: Other bit combinations are reserved.
|
||||
* @var UUART_T::INTEN
|
||||
* Offset: 0x04 USCI Interrupt Enable Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit
|
||||
* | | |This bit enables the interrupt generation in case of a transmit start event.
|
||||
* | | |0 = The transmit start interrupt Disabled.
|
||||
* | | |1 = The transmit start interrupt Enabled.
|
||||
* |[2] |TXENDIEN |Transmit End Interrupt Enable Bit
|
||||
* | | |This bit enables the interrupt generation in case of a transmit finish event.
|
||||
* | | |0 = The transmit finish interrupt Disabled.
|
||||
* | | |1 = The transmit finish interrupt Enabled.
|
||||
* |[3] |RXSTIEN |Receive Start Interrupt Enable BIt
|
||||
* | | |This bit enables the interrupt generation in case of a receive start event.
|
||||
* | | |0 = The receive start interrupt Disabled.
|
||||
* | | |1 = The receive start interrupt Enabled.
|
||||
* |[4] |RXENDIEN |Receive End Interrupt Enable Bit
|
||||
* | | |This bit enables the interrupt generation in case of a receive finish event.
|
||||
* | | |0 = The receive end interrupt Disabled.
|
||||
* | | |1 = The receive end interrupt Enabled.
|
||||
* @var UUART_T::BRGEN
|
||||
* Offset: 0x08 USCI Baud Rate Generator Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |RCLKSEL |Reference Clock Source Selection
|
||||
* | | |This bit selects the source signal of reference clock (fREF_CLK).
|
||||
* | | |0 = Peripheral device clock fPCLK.
|
||||
* | | |1 = Reserved.
|
||||
* |[1] |PTCLKSEL |Protocol Clock Source Selection
|
||||
* | | |This bit selects the source signal of protocol clock (fPROT_CLK).
|
||||
* | | |0 = Reference clock fREF_CLK.
|
||||
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
|
||||
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
|
||||
* | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
|
||||
* | | |00 = fSAMP_CLK = fDIV_CLK.
|
||||
* | | |01 = fSAMP_CLK = fPROT_CLK.
|
||||
* | | |10 = fSAMP_CLK = fSCLK.
|
||||
* | | |11 = fSAMP_CLK = fREF_CLK.
|
||||
* |[4] |TMCNTEN |Timing Measurement Counter Enable Bit
|
||||
* | | |This bit enables the 10-bit timing measurement counter.
|
||||
* | | |0 = Timing measurement counter is Disabled.
|
||||
* | | |1 = Timing measurement counter is Enabled.
|
||||
* |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection
|
||||
* | | |0 = Timing measurement counter with fPROT_CLK.
|
||||
* | | |1 = Timing measurement counter with fDIV_CLK.
|
||||
* |[9:8] |PDSCNT |Pre-divider for Sample Counter
|
||||
* | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK.
|
||||
* | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
|
||||
* |[14:10] |DSCNT |Denominator for Sample Counter
|
||||
* | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
|
||||
* | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
|
||||
* | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
|
||||
* |[25:16] |CLKDIV |Clock Divider
|
||||
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
|
||||
* | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled.
|
||||
* | | |The revised value is the average bit time between bit 5 and bit 6.
|
||||
* | | |The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.
|
||||
* @var UUART_T::DATIN0
|
||||
* Offset: 0x10 USCI Input Data Signal Configuration Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |SYNCSEL |Input Signal Synchronization Selection
|
||||
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
|
||||
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
|
||||
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
|
||||
* |[2] |ININV |Input Signal Inverse Selection
|
||||
* | | |This bit defines the inverter enable of the input asynchronous signal.
|
||||
* | | |0 = The un-synchronized input signal will not be inverted.
|
||||
* | | |1 = The un-synchronized input signal will be inverted.
|
||||
* |[4:3] |EDGEDET |Input Signal Edge Detection Mode
|
||||
* | | |This bit field selects which edge actives the trigger event of input data signal.
|
||||
* | | |00 = The trigger event activation is disabled.
|
||||
* | | |01 = A rising edge activates the trigger event of input data signal.
|
||||
* | | |10 = A falling edge activates the trigger event of input data signal.
|
||||
* | | |11 = Both edges activate the trigger event of input data signal.
|
||||
* | | |Note: In UART function mode, it is suggested to set this bit field as 10.
|
||||
* @var UUART_T::CTLIN0
|
||||
* Offset: 0x20 USCI Input Control Signal Configuration Register 0
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |SYNCSEL |Input Synchronization Signal Selection
|
||||
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
|
||||
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
|
||||
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
|
||||
* |[2] |ININV |Input Signal Inverse Selection
|
||||
* | | |This bit defines the inverter enable of the input asynchronous signal.
|
||||
* | | |0 = The un-synchronized input signal will not be inverted.
|
||||
* | | |1 = The un-synchronized input signal will be inverted.
|
||||
* @var UUART_T::CLKIN
|
||||
* Offset: 0x28 USCI Input Clock Signal Configuration Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |SYNCSEL |Input Synchronization Signal Selection
|
||||
* | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
|
||||
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
|
||||
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
|
||||
* @var UUART_T::LINECTL
|
||||
* Offset: 0x2C USCI Line Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |LSB |LSB First Transmission Selection
|
||||
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
|
||||
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
|
||||
* |[5] |DATOINV |Data Output Inverse Selection
|
||||
* | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
|
||||
* | | |0 = The value of USCIx_DAT1 is equal to the data shift register.
|
||||
* | | |1 = The value of USCIx_DAT1 is the inversion of data shift register.
|
||||
* |[7] |CTLOINV |Control Signal Output Inverse Selection
|
||||
* | | |This bit defines the relation between the internal control signal and the output control signal.
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = The control signal will be inverted before its output.
|
||||
* | | |Note: In UART protocol, the control signal means nRTS signal.
|
||||
* |[11:8] |DWIDTH |Word Length of Transmission
|
||||
* | | |This bit field defines the data word length (amount of bits) for reception and transmission.
|
||||
* | | |The data word is always right-aligned in the data buffer.
|
||||
* | | |USCI support word length from 4 to 16 bits.
|
||||
* | | |0x0: The data word contains 16 bits located at bit positions [15:0].
|
||||
* | | |0x1: Reserved.
|
||||
* | | |0x2: Reserved.
|
||||
* | | |0x3: Reserved.
|
||||
* | | |0x4: The data word contains 4 bits located at bit positions [3:0].
|
||||
* | | |0x5: The data word contains 5 bits located at bit positions [4:0].
|
||||
* | | |...
|
||||
* | | |0xF: The data word contains 15 bits located at bit positions [14:0].
|
||||
* | | |Note: In UART protocol, the length can be configured as 6~13 bits.
|
||||
* @var UUART_T::TXDAT
|
||||
* Offset: 0x30 USCI Transmit Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |TXDAT |Transmit Data
|
||||
* | | |Software can use this bit field to write 16-bit transmit data for transmission.
|
||||
* @var UUART_T::RXDAT
|
||||
* Offset: 0x34 USCI Receive Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |RXDAT |Received Data
|
||||
* | | |This bit field monitors the received data which stored in receive data buffer.
|
||||
* | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]).
|
||||
* @var UUART_T::BUFCTL
|
||||
* Offset: 0x38 USCI Transmit/Receive Buffer Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[7] |TXCLR |Clear Transmit Buffer
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value).
|
||||
* | | |Should only be used while the buffer is not taking part in data traffic.
|
||||
* | | |Note: It is cleared automatically after one PCLK cycle.
|
||||
* |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Bit
|
||||
* | | |0 = Receive overrun interrupt Disabled.
|
||||
* | | |1 = Receive overrun interrupt Enabled.
|
||||
* |[15] |RXCLR |Clear Receive Buffer
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value).
|
||||
* | | |Should only be used while the buffer is not taking part in data traffic.
|
||||
* | | |Note: It is cleared automatically after one PCLK cycle.
|
||||
* |[16] |TXRST |Transmit Reset
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
|
||||
* | | |Note: It is cleared automatically after one PCLK cycle.
|
||||
* |[17] |RXRST |Receive Reset
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
|
||||
* | | |Note1: It is cleared automatically after one PCLK cycle.
|
||||
* | | |Note2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.
|
||||
* @var UUART_T::BUFSTS
|
||||
* Offset: 0x3C USCI Transmit/Receive Buffer Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |RXEMPTY |Receive Buffer Empty Indicator
|
||||
* | | |0 = Receive buffer is not empty.
|
||||
* | | |1 = Receive buffer is empty.
|
||||
* |[1] |RXFULL |Receive Buffer Full Indicator
|
||||
* | | |0 = Receive buffer is not full.
|
||||
* | | |1 = Receive buffer is full.
|
||||
* |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status
|
||||
* | | |This bit indicates that a receive buffer overrun error event has been detected.
|
||||
* | | |If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated.
|
||||
* | | |It is cleared by software writes 1 to this bit.
|
||||
* | | |0 = A receive buffer overrun error event has not been detected.
|
||||
* | | |1 = A receive buffer overrun error event has been detected.
|
||||
* |[8] |TXEMPTY |Transmit Buffer Empty Indicator
|
||||
* | | |0 = Transmit buffer is not empty.
|
||||
* | | |1 = Transmit buffer is empty.
|
||||
* |[9] |TXFULL |Transmit Buffer Full Indicator
|
||||
* | | |0 = Transmit buffer is not full.
|
||||
* | | |1 = Transmit buffer is full.
|
||||
* @var UUART_T::PDMACTL
|
||||
* Offset: 0x40 USCI PDMA Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |PDMARST |PDMA Reset
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
|
||||
* |[1] |TXPDMAEN |PDMA Transmit Channel Available
|
||||
* | | |0 = Transmit PDMA function Disabled.
|
||||
* | | |1 = Transmit PDMA function Enabled.
|
||||
* |[2] |RXPDMAEN |PDMA Receive Channel Available
|
||||
* | | |0 = Receive PDMA function Disabled.
|
||||
* | | |1 = Receive PDMA function Enabled.
|
||||
* |[3] |PDMAEN |PDMA Mode Enable Bit
|
||||
* | | |0 = PDMA function Disabled.
|
||||
* | | |1 = PDMA function Enabled.
|
||||
* @var UUART_T::WKCTL
|
||||
* Offset: 0x54 USCI Wake-up Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WKEN |Wake-up Enable Bit
|
||||
* | | |0 = Wake-up function Disabled.
|
||||
* | | |1 = Wake-up function Enabled.
|
||||
* |[2] |PDBOPT |Power Down Blocking Option
|
||||
* | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
|
||||
* | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
|
||||
* @var UUART_T::WKSTS
|
||||
* Offset: 0x58 USCI Wake-up Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WKF |Wake-up Flag
|
||||
* | | |When chip is woken up from Power-down mode, this bit is set to 1.
|
||||
* | | |Software can write 1 to clear this bit.
|
||||
* @var UUART_T::PROTCTL
|
||||
* Offset: 0x5C USCI Protocol Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |STOPB |Stop Bits
|
||||
* | | |This bit defines the number of stop bits in an UART frame.
|
||||
* | | |0 = The number of stop bits is 1.
|
||||
* | | |1 = The number of stop bits is 2.
|
||||
* |[1] |PARITYEN |Parity Enable Bit
|
||||
* | | |This bit defines the parity bit is enabled in an UART frame.
|
||||
* | | |0 = The parity bit Disabled.
|
||||
* | | |1 = The parity bit Enabled.
|
||||
* |[2] |EVENPARITY|Even Parity Enable Bit
|
||||
* | | |0 = Odd number of logic 1's is transmitted and checked in each word.
|
||||
* | | |1 = Even number of logic 1's is transmitted and checked in each word.
|
||||
* | | |Note: This bit has effect only when PARITYEN is set.
|
||||
* |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit
|
||||
* | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (UUART_BUFSTS[1] =1), the UART will de-assert nRTS signal.
|
||||
* | | |0 = nRTS auto-flow control Disabled.
|
||||
* | | |1 = nRTS auto-flow control Enabled.
|
||||
* | | |Note: This bit has effect only when the RTSAUDIREN is not set.
|
||||
* |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit
|
||||
* | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
|
||||
* | | |0 = nCTS auto-flow control Disabled.
|
||||
* | | |1 = nCTS auto-flow control Enabled.
|
||||
* |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit
|
||||
* | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically.
|
||||
* | | |0 = nRTS auto direction control Disabled.
|
||||
* | | |1 = nRTS auto direction control Enabled.
|
||||
* | | |Note 1: This bit is used for nRTS auto direction control for RS485.
|
||||
* | | |Note 2: This bit has effect only when the RTSAUTOEN is not set.
|
||||
* |[6] |ABREN |Auto-baud Rate Detect Enable Bit
|
||||
* | | |0 = Auto-baud rate detect function Disabled.
|
||||
* | | |1 = Auto-baud rate detect function Enabled.
|
||||
* | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit.
|
||||
* | | |The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
|
||||
* |[9] |DATWKEN |Data Wake-up Mode Enable Bit
|
||||
* | | |0 = Data wake-up mode Disabled.
|
||||
* | | |1 = Data wake-up mode Enabled.
|
||||
* |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit
|
||||
* | | |0 = nCTS wake-up mode Disabled.
|
||||
* | | |1 = nCTS wake-up mode Enabled.
|
||||
* |[14:11] |WAKECNT |Wake-up Counter
|
||||
* | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode.
|
||||
* |[24:16] |BRDETITV |Baud Rate Detection Interval
|
||||
* | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits.
|
||||
* | | |The order of the bus shall be 1 and 0 step by step (e.g.
|
||||
* | | |the input data pattern shall be 0x55).
|
||||
* | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTSTS[9]) is set.
|
||||
* | | |Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV.
|
||||
* |[26] |STICKEN |Stick Parity Enable Bit
|
||||
* | | |0 = Stick parity Disabled.
|
||||
* | | |1 = Stick parity Enabled.
|
||||
* | | |Note: Refer to RS-485 Support section for detailed information.
|
||||
* |[29] |BCEN |Transmit Break Control Enable Bit
|
||||
* | | |0 = Transmit Break Control Disabled.
|
||||
* | | |1 = Transmit Break Control Enabled.
|
||||
* | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
|
||||
* | | |This bit acts only on TX line and has no effect on the transmitter logic.
|
||||
* |[31] |PROTEN |UART Protocol Enable Bit
|
||||
* | | |0 = UART Protocol Disabled.
|
||||
* | | |1 = UART Protocol Enabled.
|
||||
* @var UUART_T::PROTIEN
|
||||
* Offset: 0x60 USCI Protocol Interrupt Enable Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit
|
||||
* | | |0 = Auto-baud rate interrupt Disabled.
|
||||
* | | |1 = Auto-baud rate interrupt Enabled.
|
||||
* |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit
|
||||
* | | |0 = Receive line status interrupt Disabled.
|
||||
* | | |1 = Receive line status interrupt Enabled.
|
||||
* | | |Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
|
||||
* @var UUART_T::PROTSTS
|
||||
* Offset: 0x64 USCI Protocol Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1] |TXSTIF |Transmit Start Interrupt Flag
|
||||
* | | |0 = A transmit start interrupt status has not occurred.
|
||||
* | | |1 = A transmit start interrupt status has occurred.
|
||||
* | | |Note1: It is cleared by software writing one into this bit.
|
||||
* | | |Note2: Used for user to load next transmit data when there is no data in transmit buffer.
|
||||
* |[2] |TXENDIF |Transmit End Interrupt Flag
|
||||
* | | |0 = A transmit end interrupt status has not occurred.
|
||||
* | | |1 = A transmit end interrupt status has occurred.
|
||||
* | | |Note: It is cleared by software writing 1 into this bit.
|
||||
* |[3] |RXSTIF |Receive Start Interrupt Flag
|
||||
* | | |0 = A receive start interrupt status has not occurred.
|
||||
* | | |1 = A receive start interrupt status has occurred.
|
||||
* | | |Note: It is cleared by software writing 1 into this bit.
|
||||
* |[4] |RXENDIF |Receive End Interrupt Flag
|
||||
* | | |0 = A receive finish interrupt status has not occurred.
|
||||
* | | |1 = A receive finish interrupt status has occurred.
|
||||
* | | |Note: It is cleared by software writing 1 into this bit.
|
||||
* |[5] |PARITYERR |Parity Error Flag
|
||||
* | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit".
|
||||
* | | |0 = No parity error is generated.
|
||||
* | | |1 = Parity error is generated.
|
||||
* | | |Note: This bit can be cleared by writing "1" among the BREAK, FRMERR and PARITYERR bits.
|
||||
* |[6] |FRMERR |Framing Error Flag
|
||||
* | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
|
||||
* | | |0 = No framing error is generated.
|
||||
* | | |1 = Framing error is generated.
|
||||
* | | |Note: This bit can be cleared by writing "1" among the BREAK, FRMERR and PARITYERR bits.
|
||||
* |[7] |BREAK |Break Flag
|
||||
* | | |This bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
|
||||
* | | |0 = No Break is generated.
|
||||
* | | |1 = Break is generated in the receiver bus.
|
||||
* | | |Note: This bit can be cleared by writing "1" among the BREAK, FRMERR and PARITYERR bits.
|
||||
* |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag
|
||||
* | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data.
|
||||
* | | |If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated.
|
||||
* | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.
|
||||
* | | |0 = Auto-baud rate detect function is not done.
|
||||
* | | |1 = One Bit auto-baud rate detect function is done.
|
||||
* | | |Note: This bit can be cleared by writing "1" to it.
|
||||
* |[10] |RXBUSY |RX Bus Status Flag (Read Only)
|
||||
* | | |This bit indicates the busy status of the receiver.
|
||||
* | | |0 = The receiver is Idle.
|
||||
* | | |1 = The receiver is BUSY.
|
||||
* |[11] |ABERRSTS |Auto-baud Rate Error Status
|
||||
* | | |This bit is set when auto-baud rate detection counter overrun.
|
||||
* | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.
|
||||
* | | |0 = Auto-baud rate detect counter is not overrun.
|
||||
* | | |1 = Auto-baud rate detect counter is overrun.
|
||||
* | | |Note 1: This bit is set at the same time of ABRDETIF.
|
||||
* | | |Note 2: This bit can be cleared by writing "1" to ABRDETIF or ABERRSTS.
|
||||
* |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only)
|
||||
* | | |This bit used to indicate the current status of the internal synchronized nCTS signal.
|
||||
* | | |0 = The internal synchronized nCTS is low.
|
||||
* | | |1 = The internal synchronized nCTS is high.
|
||||
* |[17] |CTSLV |nCTS Pin Status (Read Only)
|
||||
* | | |This bit used to monitor the current status of nCTS pin input.
|
||||
* | | |0 = nCTS pin input is low level voltage logic state.
|
||||
* | | |1 = nCTS pin input is high level voltage logic state.
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
|
||||
__IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */
|
||||
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
|
||||
__I uint32_t RESERVE0[1];
|
||||
__IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */
|
||||
__I uint32_t RESERVE1[3];
|
||||
__IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */
|
||||
__I uint32_t RESERVE2[1];
|
||||
__IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */
|
||||
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
|
||||
__O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
|
||||
__I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
|
||||
__IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */
|
||||
__IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */
|
||||
__IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */
|
||||
__I uint32_t RESERVE3[4];
|
||||
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
|
||||
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
|
||||
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
|
||||
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
|
||||
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
|
||||
|
||||
} UUART_T;
|
||||
|
||||
/**
|
||||
@addtogroup UUART_CONST UUART Bit Field Definition
|
||||
Constant Definitions for UUART Controller
|
||||
@{ */
|
||||
|
||||
#define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */
|
||||
#define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */
|
||||
|
||||
#define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */
|
||||
#define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */
|
||||
|
||||
#define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */
|
||||
#define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */
|
||||
|
||||
#define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */
|
||||
#define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */
|
||||
|
||||
#define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */
|
||||
#define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */
|
||||
|
||||
#define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */
|
||||
#define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */
|
||||
|
||||
#define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */
|
||||
#define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */
|
||||
|
||||
#define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */
|
||||
#define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */
|
||||
|
||||
#define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */
|
||||
#define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */
|
||||
|
||||
#define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */
|
||||
#define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */
|
||||
|
||||
#define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */
|
||||
#define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */
|
||||
|
||||
#define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */
|
||||
#define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */
|
||||
|
||||
#define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */
|
||||
#define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */
|
||||
|
||||
#define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */
|
||||
#define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */
|
||||
|
||||
#define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */
|
||||
#define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */
|
||||
|
||||
#define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */
|
||||
#define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */
|
||||
|
||||
#define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */
|
||||
#define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */
|
||||
|
||||
#define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */
|
||||
#define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */
|
||||
|
||||
#define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */
|
||||
#define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */
|
||||
|
||||
#define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */
|
||||
#define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */
|
||||
|
||||
#define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */
|
||||
#define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */
|
||||
|
||||
#define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */
|
||||
#define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */
|
||||
|
||||
#define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */
|
||||
#define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */
|
||||
|
||||
#define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */
|
||||
#define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */
|
||||
|
||||
#define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */
|
||||
#define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */
|
||||
|
||||
#define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */
|
||||
#define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */
|
||||
|
||||
#define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */
|
||||
#define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */
|
||||
|
||||
#define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */
|
||||
#define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */
|
||||
|
||||
#define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */
|
||||
#define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */
|
||||
|
||||
#define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */
|
||||
#define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */
|
||||
|
||||
#define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */
|
||||
#define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */
|
||||
|
||||
#define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */
|
||||
#define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */
|
||||
|
||||
#define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */
|
||||
#define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */
|
||||
|
||||
#define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */
|
||||
#define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */
|
||||
|
||||
#define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */
|
||||
#define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */
|
||||
|
||||
#define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */
|
||||
#define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */
|
||||
|
||||
#define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position*/
|
||||
#define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */
|
||||
|
||||
#define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position*/
|
||||
#define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */
|
||||
|
||||
#define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */
|
||||
#define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */
|
||||
|
||||
#define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */
|
||||
#define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */
|
||||
|
||||
#define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */
|
||||
#define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */
|
||||
|
||||
#define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */
|
||||
#define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */
|
||||
|
||||
#define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */
|
||||
#define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */
|
||||
|
||||
#define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position*/
|
||||
#define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */
|
||||
|
||||
#define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position*/
|
||||
#define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */
|
||||
|
||||
#define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position*/
|
||||
#define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */
|
||||
|
||||
#define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position*/
|
||||
#define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */
|
||||
|
||||
#define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position*/
|
||||
#define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */
|
||||
|
||||
#define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */
|
||||
#define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */
|
||||
|
||||
#define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */
|
||||
#define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */
|
||||
|
||||
#define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */
|
||||
#define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */
|
||||
|
||||
#define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */
|
||||
#define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */
|
||||
|
||||
#define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position*/
|
||||
#define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */
|
||||
|
||||
#define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */
|
||||
#define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */
|
||||
|
||||
#define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */
|
||||
#define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */
|
||||
|
||||
#define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */
|
||||
#define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */
|
||||
|
||||
#define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */
|
||||
#define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */
|
||||
|
||||
#define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */
|
||||
#define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */
|
||||
|
||||
#define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */
|
||||
#define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */
|
||||
|
||||
#define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */
|
||||
#define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */
|
||||
|
||||
#define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */
|
||||
#define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */
|
||||
|
||||
#define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */
|
||||
#define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */
|
||||
|
||||
#define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position*/
|
||||
#define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */
|
||||
|
||||
#define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */
|
||||
#define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */
|
||||
|
||||
#define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */
|
||||
#define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */
|
||||
|
||||
#define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position*/
|
||||
#define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */
|
||||
|
||||
#define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */
|
||||
#define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */
|
||||
|
||||
#define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position*/
|
||||
#define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */
|
||||
|
||||
#define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position*/
|
||||
#define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */
|
||||
|
||||
#define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */
|
||||
#define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */
|
||||
|
||||
/**@}*/ /* UUART_CONST */
|
||||
/**@}*/ /* end of UUART register group */
|
||||
|
||||
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __UUART_REG_H__ */
|
||||
|
|
@ -1,174 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file wdt_reg.h
|
||||
* @version V1.00
|
||||
* @brief WDT register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __WDT_REG_H__
|
||||
#define __WDT_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup WDT Watch Dog Timer Controller(WDT)
|
||||
Memory Mapped Structure for WDT Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @var WDT_T::CTL
|
||||
* Offset: 0x00 WDT Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1] |RSTEN |WDT Time-out Reset Enable Bit (Write Protect)
|
||||
* | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
|
||||
* | | |0 = WDT time-out reset function Disabled.
|
||||
* | | |1 = WDT time-out reset function Enabled.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[2] |RSTF |WDT Time-out Reset Flag
|
||||
* | | |This bit indicates the system has been reset by WDT time-out reset or not.
|
||||
* | | |0 = WDT time-out reset did not occur.
|
||||
* | | |1 = WDT time-out reset occurred.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* |[3] |IF |WDT Time-out Interrupt Flag
|
||||
* | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.
|
||||
* | | |0 = WDT time-out interrupt did not occur.
|
||||
* | | |1 = WDT time-out interrupt occurred.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect)
|
||||
* | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
|
||||
* | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
|
||||
* | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
|
||||
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* | | |Note2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT.
|
||||
* |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect)
|
||||
* | | |This bit indicates the interrupt wake-up flag status of WDT.
|
||||
* | | |0 = WDT does not cause chip wake-up.
|
||||
* | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
|
||||
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* | | |Note2: This bit is cleared by writing 1 to it.
|
||||
* |[6] |INTEN |WDT Time-out Interrupt Enable Bit (Write Protect)
|
||||
* | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
|
||||
* | | |0 = WDT time-out interrupt Disabled.
|
||||
* | | |1 = WDT time-out interrupt Enabled.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[7] |WDTEN |WDT Enable Bit (Write Protect)
|
||||
* | | |0 = WDT Disabled (This action will reset the internal up counter value).
|
||||
* | | |1 = WDT Enabled.
|
||||
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0.
|
||||
* |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect)
|
||||
* | | |These four bits select the time-out interval period for the WDT.
|
||||
* | | |0000 = 24 * WDT_CLK.
|
||||
* | | |0001 = 26 * WDT_CLK.
|
||||
* | | |0010 = 28 * WDT_CLK.
|
||||
* | | |0011 = 210 * WDT_CLK.
|
||||
* | | |0100 = 212 * WDT_CLK.
|
||||
* | | |0101 = 214 * WDT_CLK.
|
||||
* | | |0110 = 216 * WDT_CLK.
|
||||
* | | |0111 = 218 * WDT_CLK.
|
||||
* | | |1000 = 220 * WDT_CLK.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only)
|
||||
* | | |If user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.
|
||||
* | | |0 = Set WDTEN bit is completed.
|
||||
* | | |1 = Set WDTEN bit is synchronizing and not become active yet.
|
||||
* | | |Note: Performing enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
|
||||
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
|
||||
* | | |0 = ICE debug mode acknowledgement affects WDT counting.
|
||||
* | | |WDT up counter will be held while CPU is held by ICE.
|
||||
* | | |1 = ICE debug mode acknowledgement Disabled.
|
||||
* | | |WDT up counter will keep going no matter CPU is held by ICE or not.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* @var WDT_T::ALTCTL
|
||||
* Offset: 0x04 WDT Alternative Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect).
|
||||
* | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened.
|
||||
* | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
|
||||
* | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
|
||||
* | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
|
||||
* | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
|
||||
* | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
|
||||
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* | | |Note2: This register will be reset to 0 if WDT time-out reset happened.
|
||||
* @var WDT_T::RSTCNT
|
||||
* Offset: 0x08 WDT Reset Counter Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |RSTCNT |WDT Reset Counter Register
|
||||
* | | |Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.
|
||||
* | | |Note1: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] WDT Control Register */
|
||||
__IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */
|
||||
__O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */
|
||||
|
||||
} WDT_T;
|
||||
|
||||
/**
|
||||
@addtogroup WDT_CONST WDT Bit Field Definition
|
||||
Constant Definitions for WDT Controller
|
||||
@{ */
|
||||
|
||||
#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
|
||||
#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
|
||||
|
||||
#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
|
||||
#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
|
||||
|
||||
#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
|
||||
#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
|
||||
|
||||
#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
|
||||
#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
|
||||
|
||||
#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
|
||||
#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
|
||||
|
||||
#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
|
||||
#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
|
||||
|
||||
#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
|
||||
#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
|
||||
|
||||
#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
|
||||
#define WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
|
||||
|
||||
#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */
|
||||
#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */
|
||||
|
||||
#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
|
||||
#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
|
||||
|
||||
#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
|
||||
#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
|
||||
|
||||
#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */
|
||||
#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */
|
||||
|
||||
/**@}*/ /* WDT_CONST */
|
||||
/**@}*/ /* end of WDT register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __WDT_REG_H__ */
|
||||
|
||||
|
|
@ -1,148 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file wwdt_reg.h
|
||||
* @version V1.00
|
||||
* @brief WWDT register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __WWDT_REG_H__
|
||||
#define __WWDT_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup WWDT Window Watchdog Timer(WWDT)
|
||||
Memory Mapped Structure for WWDT Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var WWDT_T::RLDCNT
|
||||
* Offset: 0x00 WWDT Reload Counter Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |RLDCNT |WWDT Reload Counter Register
|
||||
* | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
|
||||
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]).
|
||||
* | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately.
|
||||
* @var WWDT_T::CTL
|
||||
* Offset: 0x04 WWDT Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WWDTEN |WWDT Enable Bit
|
||||
* | | |0 = WWDT counter is stopped.
|
||||
* | | |1 = WWDT counter starts counting.
|
||||
* |[1] |INTEN |WWDT Interrupt Enable Bit
|
||||
* | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
|
||||
* | | |0 = WWDT counter compare match interrupt Disabled.
|
||||
* | | |1 = WWDT counter compare match interrupt Enabled.
|
||||
* |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
|
||||
* | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
|
||||
* | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
|
||||
* | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
|
||||
* | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
|
||||
* | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
|
||||
* | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
|
||||
* | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
|
||||
* | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
|
||||
* | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
|
||||
* | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
|
||||
* | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
|
||||
* | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
|
||||
* | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
|
||||
* | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
|
||||
* | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
|
||||
* | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
|
||||
* |[21:16] |CMPDAT |WWDT Window Compare Register
|
||||
* | | |Set this register to adjust the valid reload window.
|
||||
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
|
||||
* | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
|
||||
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit
|
||||
* | | |0 = ICE debug mode acknowledgement effects WWDT counting.
|
||||
* | | |WWDT down counter will be held while CPU is held by ICE.
|
||||
* | | |1 = ICE debug mode acknowledgement Disabled.
|
||||
* | | |Note: WWDT down counter will keep going no matter CPU is held by ICE or not.
|
||||
* @var WWDT_T::STATUS
|
||||
* Offset: 0x08 WWDT Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
|
||||
* | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = WWDT counter value matches CMPDAT.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* |[1] |WWDTRF |WWDT Timer-out Reset Flag
|
||||
* | | |This bit indicates the system has been reset by WWDT time-out reset or not.
|
||||
* | | |0 = WWDT time-out reset did not occur.
|
||||
* | | |1 = WWDT time-out reset occurred.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* @var WWDT_T::CNT
|
||||
* Offset: 0x0C WWDT Counter Value Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[5:0] |CNTDAT |WWDT Counter Value
|
||||
* | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
|
||||
*/
|
||||
__O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */
|
||||
__IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */
|
||||
__IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */
|
||||
__I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */
|
||||
|
||||
} WWDT_T;
|
||||
|
||||
/**
|
||||
@addtogroup WWDT_CONST WWDT Bit Field Definition
|
||||
Constant Definitions for WWDT Controller
|
||||
@{ */
|
||||
|
||||
#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */
|
||||
#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */
|
||||
|
||||
#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */
|
||||
#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */
|
||||
|
||||
#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */
|
||||
#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */
|
||||
|
||||
#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */
|
||||
#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */
|
||||
|
||||
#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */
|
||||
#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */
|
||||
|
||||
#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */
|
||||
#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */
|
||||
|
||||
#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */
|
||||
#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */
|
||||
|
||||
#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */
|
||||
#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */
|
||||
|
||||
#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */
|
||||
#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */
|
||||
|
||||
/**@}*/ /* WWDT_CONST */
|
||||
/**@}*/ /* end of WWDT register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __WWDT_REG_H__ */
|
||||
|
|
@ -1,259 +0,0 @@
|
|||
;/**************************************************************************//**
|
||||
; * @file startup_m031series.s
|
||||
; * @version V2.00
|
||||
; * $Revision: 4 $
|
||||
; * $Date: 18/04/02 4:02p $
|
||||
; * @brief M031 Series Startup Source File
|
||||
; *
|
||||
; * @note
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
IF :LNOT: :DEF: Stack_Size
|
||||
Stack_Size EQU 0x00002000
|
||||
ENDIF
|
||||
|
||||
AREA |.STACK|, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
IF :LNOT: :DEF: Heap_Size
|
||||
Heap_Size EQU 0x00000000
|
||||
ENDIF
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT g_pfnVectors
|
||||
|
||||
g_pfnVectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
; maximum of 32 External Interrupts are possible
|
||||
DCD BOD_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD EINT024_IRQHandler
|
||||
DCD EINT135_IRQHandler
|
||||
DCD GPABGH_IRQHandler
|
||||
DCD GPCDEF_IRQHandler
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PWM1_IRQHandler
|
||||
DCD TMR0_IRQHandler
|
||||
DCD TMR1_IRQHandler
|
||||
DCD TMR2_IRQHandler
|
||||
DCD TMR3_IRQHandler
|
||||
DCD UART02_IRQHandler
|
||||
DCD UART13_IRQHandler
|
||||
DCD SPI0_IRQHandler
|
||||
DCD QSPI0_IRQHandler
|
||||
DCD ISP_IRQHandler
|
||||
DCD UART57_IRQHandler
|
||||
DCD I2C0_IRQHandler
|
||||
DCD I2C1_IRQHandler
|
||||
DCD BPWM0_IRQHandler
|
||||
DCD BPWM1_IRQHandler
|
||||
DCD USCI01_IRQHandler
|
||||
DCD USBD_IRQHandler
|
||||
DCD Default_Handler
|
||||
DCD ACMP01_IRQHandler
|
||||
DCD PDMA_IRQHandler
|
||||
DCD UART46_IRQHandler
|
||||
DCD PWRWU_IRQHandler
|
||||
DCD ADC_IRQHandler
|
||||
DCD CKFAIL_IRQHandler
|
||||
DCD RTC_IRQHandler
|
||||
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
|
||||
; Reset Handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
|
||||
LDR R0, =0x40000100
|
||||
; Unlock Register
|
||||
|
||||
LDR R1, =0x59
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x16
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x88
|
||||
STR R1, [R0]
|
||||
|
||||
; Init POR
|
||||
LDR R2, =0x40000024
|
||||
LDR R1, =0x00005AA5
|
||||
STR R1, [R2]
|
||||
|
||||
; Init LDO_RDY
|
||||
LDR R2, =0x40000280
|
||||
LDR R1, =0x00000001
|
||||
STR R1, [R2]
|
||||
|
||||
; Lock register
|
||||
MOVS R1, #0
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT EINT024_IRQHandler [WEAK]
|
||||
EXPORT EINT135_IRQHandler [WEAK]
|
||||
EXPORT GPABGH_IRQHandler [WEAK]
|
||||
EXPORT GPCDEF_IRQHandler [WEAK]
|
||||
EXPORT PWM0_IRQHandler [WEAK]
|
||||
EXPORT PWM1_IRQHandler [WEAK]
|
||||
EXPORT TMR0_IRQHandler [WEAK]
|
||||
EXPORT TMR1_IRQHandler [WEAK]
|
||||
EXPORT TMR2_IRQHandler [WEAK]
|
||||
EXPORT TMR3_IRQHandler [WEAK]
|
||||
EXPORT UART02_IRQHandler [WEAK]
|
||||
EXPORT UART13_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT QSPI0_IRQHandler [WEAK]
|
||||
EXPORT ISP_IRQHandler [WEAK]
|
||||
EXPORT UART57_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT BPWM0_IRQHandler [WEAK]
|
||||
EXPORT BPWM1_IRQHandler [WEAK]
|
||||
EXPORT USCI01_IRQHandler [WEAK]
|
||||
EXPORT USBD_IRQHandler [WEAK]
|
||||
EXPORT ACMP01_IRQHandler [WEAK]
|
||||
EXPORT PDMA_IRQHandler [WEAK]
|
||||
EXPORT UART46_IRQHandler [WEAK]
|
||||
EXPORT PWRWU_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT CKFAIL_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
|
||||
BOD_IRQHandler
|
||||
WDT_IRQHandler
|
||||
EINT024_IRQHandler
|
||||
EINT135_IRQHandler
|
||||
GPABGH_IRQHandler
|
||||
GPCDEF_IRQHandler
|
||||
PWM0_IRQHandler
|
||||
PWM1_IRQHandler
|
||||
TMR0_IRQHandler
|
||||
TMR1_IRQHandler
|
||||
TMR2_IRQHandler
|
||||
TMR3_IRQHandler
|
||||
UART02_IRQHandler
|
||||
UART13_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
QSPI0_IRQHandler
|
||||
ISP_IRQHandler
|
||||
UART57_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
BPWM0_IRQHandler
|
||||
BPWM1_IRQHandler
|
||||
USCI01_IRQHandler
|
||||
USBD_IRQHandler
|
||||
ACMP01_IRQHandler
|
||||
PDMA_IRQHandler
|
||||
UART46_IRQHandler
|
||||
PWRWU_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CKFAIL_IRQHandler
|
||||
RTC_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
|
@ -1,229 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file startup_m031series.s
|
||||
* @version V2.00
|
||||
* $Revision: 6 $
|
||||
* $Date: 18/04/12 4:44p $
|
||||
* @brief CMSIS Cortex-M0 Core Device Startup File for M031
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
******************************************************************************/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m0
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Unlock Register */
|
||||
ldr r0, =0x40000100
|
||||
ldr r1, =0x59
|
||||
str r1, [r0]
|
||||
ldr r1, =0x16
|
||||
str r1, [r0]
|
||||
ldr r1, =0x88
|
||||
str r1, [r0]
|
||||
|
||||
#if 1
|
||||
/* Init POR */
|
||||
ldr r0, =0x40000024
|
||||
ldr r1, =0x00005AA5
|
||||
str r1, [r0]
|
||||
|
||||
/* Init LDO_RDY */
|
||||
ldr r0, =0x40000280
|
||||
ldr r1, =0x00000001
|
||||
str r1, [r0]
|
||||
#endif
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2, #4]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Lock register */
|
||||
ldr r0, =0x40000100
|
||||
ldr r1, =0
|
||||
str r1, [r0]
|
||||
|
||||
/* Call the application entry point.*/
|
||||
|
||||
bl entry
|
||||
bx lr
|
||||
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/*******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M0. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.long _estack /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long BOD_IRQHandler /* 0: BOD */
|
||||
.long WDT_IRQHandler /* 1: WDT */
|
||||
.long EINT024_IRQHandler /* 2: EINT0 */
|
||||
.long EINT135_IRQHandler /* 3: EINT1 */
|
||||
.long GPABGH_IRQHandler /* 4: GPAB */
|
||||
.long GPCDEF_IRQHandler /* 5: GPCDEF */
|
||||
.long PWM0_IRQHandler /* 6: PWM0 */
|
||||
.long PWM1_IRQHandler /* 7: PWM1 */
|
||||
.long TMR0_IRQHandler /* 8: TIMER0 */
|
||||
.long TMR1_IRQHandler /* 9: TIMER1 */
|
||||
.long TMR2_IRQHandler /* 10: TIMER2 */
|
||||
.long TMR3_IRQHandler /* 11: TIMER3 */
|
||||
.long UART02_IRQHandler /* 12: UART02 */
|
||||
.long UART13_IRQHandler /* 13: UART13 */
|
||||
.long SPI0_IRQHandler /* 14: SPI0 */
|
||||
.long QSPI0_IRQHandler /* 15: QSPI0 */
|
||||
.long ISP_IRQHandler /* 16: Reserved */
|
||||
.long UART57_IRQHandler /* 17: UART57 */
|
||||
.long I2C0_IRQHandler /* 18: I2C0 */
|
||||
.long I2C1_IRQHandler /* 19: I2C1 */
|
||||
.long BPWM0_IRQHandler /* 20: BPWM0 */
|
||||
.long BPWM1_IRQHandler /* 21: BPWM1 */
|
||||
.long USCI01_IRQHandler /* 22: USCI01 */
|
||||
.long USBD_IRQHandler /* 23: USBD */
|
||||
.long Default_Handler /* 24: Reserved */
|
||||
.long ACMP01_IRQHandler /* 25: ACMP01 */
|
||||
.long PDMA_IRQHandler /* 26: PDMA */
|
||||
.long UART46_IRQHandler /* 27: UART46 */
|
||||
.long PWRWU_IRQHandler /* 28: PWRWU */
|
||||
.long ADC_IRQHandler /* 29: ADC */
|
||||
.long CKFAIL_IRQHandler /* 30: CLK Fail Detect */
|
||||
.long RTC_IRQHandler /* 31: RTC */
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
def_irq_handler BOD_IRQHandler
|
||||
def_irq_handler WDT_IRQHandler
|
||||
def_irq_handler EINT024_IRQHandler
|
||||
def_irq_handler EINT135_IRQHandler
|
||||
def_irq_handler GPABGH_IRQHandler
|
||||
def_irq_handler GPCDEF_IRQHandler
|
||||
def_irq_handler PWM0_IRQHandler
|
||||
def_irq_handler PWM1_IRQHandler
|
||||
def_irq_handler TMR0_IRQHandler
|
||||
def_irq_handler TMR1_IRQHandler
|
||||
def_irq_handler TMR2_IRQHandler
|
||||
def_irq_handler TMR3_IRQHandler
|
||||
def_irq_handler UART02_IRQHandler
|
||||
def_irq_handler UART13_IRQHandler
|
||||
def_irq_handler SPI0_IRQHandler
|
||||
def_irq_handler QSPI0_IRQHandler
|
||||
def_irq_handler ISP_IRQHandler
|
||||
def_irq_handler UART57_IRQHandler
|
||||
def_irq_handler I2C0_IRQHandler
|
||||
def_irq_handler I2C1_IRQHandler
|
||||
def_irq_handler BPWM0_IRQHandler
|
||||
def_irq_handler BPWM1_IRQHandler
|
||||
def_irq_handler USCI01_IRQHandler
|
||||
def_irq_handler USBD_IRQHandler
|
||||
def_irq_handler ACMP01_IRQHandler
|
||||
def_irq_handler PDMA_IRQHandler
|
||||
def_irq_handler UART46_IRQHandler
|
||||
def_irq_handler PWRWU_IRQHandler
|
||||
def_irq_handler ADC_IRQHandler
|
||||
def_irq_handler CKFAIL_IRQHandler
|
||||
def_irq_handler RTC_IRQHandler
|
||||
|
||||
|
||||
|
||||
.end
|
||||
|
|
@ -1,202 +0,0 @@
|
|||
;/**************************************************************************//**
|
||||
; * @file startup_M031Series.s
|
||||
; * @version V3.00
|
||||
; * $Revision: 5 $
|
||||
; * $Date: 18/04/02 4:02p $
|
||||
; * @brief M031 Series Startup Source File for IAR Platform
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3) ;; 8 bytes alignment
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2);; 4 bytes alignment
|
||||
|
||||
EXTERN SystemInit
|
||||
EXTERN __iar_program_start
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD SVC_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD BOD_IRQHandler ; Brownout low voltage detected interrupt
|
||||
DCD WDT_IRQHandler ; Watch Dog Timer interrupt
|
||||
DCD EINT024_IRQHandler
|
||||
DCD EINT135_IRQHandler
|
||||
DCD GPABGH_IRQHandler
|
||||
DCD GPCDEF_IRQHandler
|
||||
DCD PWM0_IRQHandler ; PWM0 or PWM2 interrupt
|
||||
DCD PWM1_IRQHandler ; PWM1 or PWM3 interrupt
|
||||
DCD TMR0_IRQHandler ; Timer 0 interrupt
|
||||
DCD TMR1_IRQHandler ; Timer 1 interrupt
|
||||
DCD TMR2_IRQHandler ; Timer 2 interrupt
|
||||
DCD TMR3_IRQHandler ; Timer 3 interrupt
|
||||
DCD UART02_IRQHandler
|
||||
DCD UART13_IRQHandler
|
||||
DCD SPI0_IRQHandler
|
||||
DCD QSPI0_IRQHandler
|
||||
DCD ISP_IRQHandler
|
||||
DCD UART57_IRQHandler
|
||||
DCD I2C0_IRQHandler
|
||||
DCD I2C1_IRQHandler
|
||||
DCD BPWM0_IRQHandler
|
||||
DCD BPWM1_IRQHandler
|
||||
DCD USCI01_IRQHandler
|
||||
DCD USBD_IRQHandler
|
||||
DCD Default_Handler
|
||||
DCD ACMP01_IRQHandler
|
||||
DCD PDMA_IRQHandler
|
||||
DCD UART46_IRQHandler
|
||||
DCD PWRWU_IRQHandler ; Clock controller interrupt for chip wake up from power-down
|
||||
DCD ADC_IRQHandler ; ADC interrupt
|
||||
DCD CKFAIL_IRQHandler ; Clock fail detect and IRC TRIM interrupt
|
||||
DCD RTC_IRQHandler
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2) ; 4 bytes alignment
|
||||
Reset_Handler
|
||||
LDR R0, =0x40000100
|
||||
; Unlock Register
|
||||
LDR R1, =0x59
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x16
|
||||
STR R1, [R0]
|
||||
LDR R1, =0x88
|
||||
STR R1, [R0]
|
||||
|
||||
; Init POR
|
||||
LDR R2, =0x40000024
|
||||
LDR R1, =0x00005AA5
|
||||
STR R1, [R2]
|
||||
|
||||
; Init LDO_RDY
|
||||
LDR R2, =0x40000280
|
||||
LDR R1, =0x00000001
|
||||
STR R1, [R2]
|
||||
|
||||
; Disable NMI (Assign to reserved IRQ)
|
||||
LDR R2, =0x40000380
|
||||
LDR R1, =0x0000001F
|
||||
STR R1, [R2]
|
||||
|
||||
; Lock register
|
||||
MOVS R1, #0
|
||||
STR R1, [R0]
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
PUBWEAK NMI_Handler
|
||||
PUBWEAK SVC_Handler
|
||||
PUBWEAK PendSV_Handler
|
||||
PUBWEAK SysTick_Handler
|
||||
PUBWEAK BOD_IRQHandler
|
||||
PUBWEAK WDT_IRQHandler
|
||||
PUBWEAK EINT024_IRQHandler
|
||||
PUBWEAK EINT135_IRQHandler
|
||||
PUBWEAK GPABGH_IRQHandler
|
||||
PUBWEAK GPCDEF_IRQHandler
|
||||
PUBWEAK PWM0_IRQHandler
|
||||
PUBWEAK PWM1_IRQHandler
|
||||
PUBWEAK TMR0_IRQHandler
|
||||
PUBWEAK TMR1_IRQHandler
|
||||
PUBWEAK TMR2_IRQHandler
|
||||
PUBWEAK TMR3_IRQHandler
|
||||
PUBWEAK UART02_IRQHandler
|
||||
PUBWEAK UART13_IRQHandler
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
PUBWEAK QSPI0_IRQHandler
|
||||
PUBWEAK ISP_IRQHandler
|
||||
PUBWEAK UART57_IRQHandler
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
PUBWEAK BPWM0_IRQHandler
|
||||
PUBWEAK BPWM1_IRQHandler
|
||||
PUBWEAK USCI01_IRQHandler
|
||||
PUBWEAK USBD_IRQHandler
|
||||
PUBWEAK ACMP01_IRQHandler
|
||||
PUBWEAK PDMA_IRQHandler
|
||||
PUBWEAK UART46_IRQHandler
|
||||
PUBWEAK PWRWU_IRQHandler
|
||||
PUBWEAK ADC_IRQHandler
|
||||
PUBWEAK CKFAIL_IRQHandler
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
|
||||
HardFault_Handler
|
||||
NMI_Handler
|
||||
SVC_Handler
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
BOD_IRQHandler
|
||||
WDT_IRQHandler
|
||||
EINT024_IRQHandler
|
||||
EINT135_IRQHandler
|
||||
GPABGH_IRQHandler
|
||||
GPCDEF_IRQHandler
|
||||
PWM0_IRQHandler
|
||||
PWM1_IRQHandler
|
||||
TMR0_IRQHandler
|
||||
TMR1_IRQHandler
|
||||
TMR2_IRQHandler
|
||||
TMR3_IRQHandler
|
||||
UART02_IRQHandler
|
||||
UART13_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
QSPI0_IRQHandler
|
||||
ISP_IRQHandler
|
||||
UART57_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
BPWM0_IRQHandler
|
||||
BPWM1_IRQHandler
|
||||
USCI01_IRQHandler
|
||||
USBD_IRQHandler
|
||||
ACMP01_IRQHandler
|
||||
PDMA_IRQHandler
|
||||
UART46_IRQHandler
|
||||
PWRWU_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CKFAIL_IRQHandler
|
||||
RTC_IRQHandler
|
||||
Default_Handler
|
||||
|
||||
B Default_Handler
|
||||
|
||||
|
||||
END
|
||||
|
||||
|
|
@ -1,130 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file system_M031Series.c
|
||||
* @version V2.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 18/07/19 1:44p $
|
||||
* @brief M031 Series System Setting Source File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*
|
||||
******************************************************************************/
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include "NuMicro.h"
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */
|
||||
uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
|
||||
uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
|
||||
const uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, __HSI, __LIRC, __HIRC, 0UL, 0UL, __HIRC};
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update the Variable SystemCoreClock
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to update the variable SystemCoreClock
|
||||
* and must be called whenever the core clock is changed.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t u32Freq, u32ClkSrc;
|
||||
uint32_t u32HclkDiv;
|
||||
|
||||
u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
|
||||
|
||||
/* Update PLL Clock */
|
||||
PllClock = CLK_GetPLLClockFreq();
|
||||
|
||||
if(u32ClkSrc != CLK_CLKSEL0_HCLKSEL_PLL)
|
||||
{
|
||||
/* Use the clock sources directly */
|
||||
u32Freq = gau32ClkSrcTbl[u32ClkSrc];
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Use PLL clock */
|
||||
u32Freq = PllClock;
|
||||
}
|
||||
|
||||
u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
|
||||
|
||||
/* Update System Core Clock */
|
||||
SystemCoreClock = u32Freq / u32HclkDiv;
|
||||
|
||||
CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief System Initialization
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The necessary initialization of system. Global variables are forbidden here.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Unlock protected registers */
|
||||
SYS_UnlockReg();
|
||||
|
||||
/* Set HXTGain Level dependend on HXT Frequency */
|
||||
CLK->PWRCTL = CLK->PWRCTL & ~CLK_PWRCTL_HXTGAIN_Msk;
|
||||
if ((__HXT >= FREQ_4MHZ) && (__HXT < FREQ_8MHZ))
|
||||
{
|
||||
CLK->PWRCTL |= (1 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
else if ((__HXT >= FREQ_8MHZ) && (__HXT < FREQ_12MHZ))
|
||||
{
|
||||
CLK->PWRCTL |= (2 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
else if ((__HXT >= FREQ_12MHZ) && (__HXT < FREQ_16MHZ))
|
||||
{
|
||||
CLK->PWRCTL |= (3 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
else if ((__HXT >= FREQ_16MHZ) && (__HXT < FREQ_24MHZ))
|
||||
{
|
||||
CLK->PWRCTL |= (4 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLK->PWRCTL |= (7 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
|
||||
/* Lock protected registers */
|
||||
SYS_LockReg();
|
||||
}
|
||||
|
||||
#if USE_ASSERT
|
||||
|
||||
/**
|
||||
* @brief Assert Error Message
|
||||
*
|
||||
* @param[in] file the source file name
|
||||
* @param[in] line line number
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function prints the source file name and line number where
|
||||
* the ASSERT_PARAM() error occurs, and then stops in an infinite loop.
|
||||
*/
|
||||
void AssertError(uint8_t * file, uint32_t line)
|
||||
{
|
||||
|
||||
printf("[%s] line %d : wrong parameters.\r\n", file, line);
|
||||
|
||||
/* Infinite loop */
|
||||
while(1) ;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
import rtconfig
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
src = Split("""
|
||||
Nuvoton/M031/Source/system_M031Series.c
|
||||
""")
|
||||
|
||||
# add for startup script
|
||||
if rtconfig.PLATFORM in ['gcc']:
|
||||
src = src + ['Nuvoton/M031/Source/GCC/startup_M031Series.S']
|
||||
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
src = src + ['Nuvoton/M031/Source/ARM/startup_M031Series.s']
|
||||
elif rtconfig.PLATFORM in ['iccarm']:
|
||||
src = src + ['Nuvoton/M031/Source/IAR/startup_M031Series.s']
|
||||
|
||||
path = [cwd + '/Nuvoton/M031/Include',]
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
# RT-Thread building script for component
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
libs = []
|
||||
src = Glob('*src/*.c') + Glob('src/*.cpp')
|
||||
cpppath = [cwd + '/inc']
|
||||
libpath = [cwd + '/lib']
|
||||
|
||||
if not GetDepend('BSP_USE_STDDRIVER_SOURCE'):
|
||||
if rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
if GetOption('target') == 'mdk5' and os.path.isfile('./lib/libstddriver_keil.lib'):
|
||||
libs += ['libstddriver_keil']
|
||||
elif GetOption('target') == 'mdk4' and os.path.isfile('./lib/libstddriver_keil4.lib'):
|
||||
libs += ['libstddriver_keil4']
|
||||
elif rtconfig.PLATFORM in ['gcc'] and os.path.isfile('./lib/libstddriver_gcc.a'):
|
||||
libs += ['libstddriver_gcc']
|
||||
elif os.path.isfile('./lib/libstddriver_iar.a'):
|
||||
libs += ['libstddriver_iar']
|
||||
|
||||
if not libs:
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath)
|
||||
else:
|
||||
src = []
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath, LIBS = libs, LIBPATH = libpath)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -1,401 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_acmp.h
|
||||
* @version V0.10
|
||||
* $Revision: 2 $
|
||||
* $Date: 18/12/21 10:53a $
|
||||
* @brief M031 Series ACMP Driver Header File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_ACMP_H__
|
||||
#define __NU_ACMP_H__
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Include related headers */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#include "M031Series.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup ACMP_Driver ACMP Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* ACMP_CTL constant definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define ACMP_CTL_FILTSEL_OFF (0UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for filter function disabled. \hideinitializer */
|
||||
#define ACMP_CTL_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 1 PCLK filter count. \hideinitializer */
|
||||
#define ACMP_CTL_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 2 PCLK filter count. \hideinitializer */
|
||||
#define ACMP_CTL_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 4 PCLK filter count. \hideinitializer */
|
||||
#define ACMP_CTL_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 8 PCLK filter count. \hideinitializer */
|
||||
#define ACMP_CTL_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 16 PCLK filter count. \hideinitializer */
|
||||
#define ACMP_CTL_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 32 PCLK filter count. \hideinitializer */
|
||||
#define ACMP_CTL_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 64 PCLK filter count. \hideinitializer */
|
||||
#define ACMP_CTL_INTPOL_RF (0UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. \hideinitializer */
|
||||
#define ACMP_CTL_INTPOL_R (1UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. \hideinitializer */
|
||||
#define ACMP_CTL_INTPOL_F (2UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. \hideinitializer */
|
||||
#define ACMP_CTL_POSSEL_P0 (0UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. \hideinitializer */
|
||||
#define ACMP_CTL_POSSEL_P1 (1UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. \hideinitializer */
|
||||
#define ACMP_CTL_POSSEL_P2 (2UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. \hideinitializer */
|
||||
#define ACMP_CTL_POSSEL_P3 (3UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. \hideinitializer */
|
||||
#define ACMP_CTL_NEGSEL_PIN (0UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. \hideinitializer */
|
||||
#define ACMP_CTL_NEGSEL_CRV (1UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. \hideinitializer */
|
||||
#define ACMP_CTL_NEGSEL_VBG (2UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. \hideinitializer */
|
||||
#define ACMP_CTL_HYSTERESIS_ENABLE (1UL << ACMP_CTL_HYSEN_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function. \hideinitializer */
|
||||
#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << ACMP_CTL_HYSEN_Pos) /*!< ACMP_CTL setting for disabling the hysteresis function. \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* ACMP_VREF constant definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define ACMP_VREF_CRVSSEL_VDDA (0UL << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage \hideinitializer */
|
||||
#define ACMP_VREF_CRVSSEL_INTVREF (1UL << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage \hideinitializer */
|
||||
|
||||
|
||||
/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Define Macros and functions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief This macro is used to enable output inverse function
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to disable output inverse function
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to select ACMP negative input source
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @param[in] u32Src is comparator negative input selection. Including:
|
||||
* - \ref ACMP_CTL_NEGSEL_PIN
|
||||
* - \ref ACMP_CTL_NEGSEL_CRV
|
||||
* - \ref ACMP_CTL_NEGSEL_VBG
|
||||
* @return None
|
||||
* @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src))
|
||||
|
||||
/**
|
||||
* @brief This macro is used to enable hysteresis function
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will set HYSEN bit of ACMP_CTL register to enable hysteresis function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to disable hysteresis function
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will clear HYSEN bit of ACMP_CTL register to disable hysteresis function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to enable interrupt
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function.
|
||||
* If wake-up function is enabled, the wake-up interrupt will be enabled as well.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to disable interrupt
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to enable ACMP
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to disable ACMP
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to get ACMP output value
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return ACMP output value
|
||||
* @details This macro will return the ACMP output value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to get ACMP interrupt flag
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return ACMP interrupt occurred (1) or not (0)
|
||||
* @details This macro will return the ACMP interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to clear ACMP interrupt flag
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))
|
||||
|
||||
/**
|
||||
* @brief This macro is used to clear ACMP wake-up interrupt flag
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum))))
|
||||
|
||||
/**
|
||||
* @brief This macro is used to enable ACMP wake-up function
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to disable ACMP wake-up function
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to select ACMP positive input pin
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @param[in] u32Pin Comparator positive pin selection. Including:
|
||||
* - \ref ACMP_CTL_POSSEL_P0
|
||||
* - \ref ACMP_CTL_POSSEL_P1
|
||||
* - \ref ACMP_CTL_POSSEL_P2
|
||||
* - \ref ACMP_CTL_POSSEL_P3
|
||||
* @return None
|
||||
* @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
|
||||
|
||||
/**
|
||||
* @brief This macro is used to enable ACMP filter function
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to disable ACMP filter function
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to set ACMP filter function
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @param[in] u32Cnt is comparator filter count setting.
|
||||
* - \ref ACMP_CTL_FILTSEL_OFF
|
||||
* - \ref ACMP_CTL_FILTSEL_1PCLK
|
||||
* - \ref ACMP_CTL_FILTSEL_2PCLK
|
||||
* - \ref ACMP_CTL_FILTSEL_4PCLK
|
||||
* - \ref ACMP_CTL_FILTSEL_8PCLK
|
||||
* - \ref ACMP_CTL_FILTSEL_16PCLK
|
||||
* - \ref ACMP_CTL_FILTSEL_32PCLK
|
||||
* - \ref ACMP_CTL_FILTSEL_64PCLK
|
||||
* @return None
|
||||
* @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))
|
||||
|
||||
/**
|
||||
* @brief This macro is used to select comparator reference voltage
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32Level The comparator reference voltage setting.
|
||||
* The formula is:
|
||||
* comparator reference voltage = CRV source voltage x (1/6 + u32Level/24)
|
||||
* The range of u32Level is 0 ~ 15.
|
||||
* @return None
|
||||
* @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<<ACMP_VREF_CRVCTL_Pos))
|
||||
|
||||
/**
|
||||
* @brief This macro is used to select the source of CRV
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32Src is the source of CRV. Including:
|
||||
* - \ref ACMP_VREF_CRVSSEL_VDDA
|
||||
* - \ref ACMP_VREF_CRVSSEL_INTVREF
|
||||
* @return None
|
||||
* @details The source of CRV can be VDDA or internal reference voltage. The internal reference voltage level is determined by SYS_VREFCTL register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_SELECT_CRV_SRC(acmp, u32Src) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src))
|
||||
|
||||
/**
|
||||
* @brief This macro is used to select ACMP interrupt condition
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @param[in] u32Cond Comparator interrupt condition selection. Including:
|
||||
* - \ref ACMP_CTL_INTPOL_RF
|
||||
* - \ref ACMP_CTL_INTPOL_R
|
||||
* - \ref ACMP_CTL_INTPOL_F
|
||||
* @return None
|
||||
* @details The ACMP output interrupt condition can be rising edge, falling edge or any edge.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond))
|
||||
|
||||
/**
|
||||
* @brief This macro is used to enable ACMP window latch mode
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode.
|
||||
* When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch
|
||||
* block; when ACMP0/1_WLAT pin is at low level, the output of window latch block,
|
||||
* WLATOUT, is frozen.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to disable ACMP window latch mode
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to enable ACMP window compare mode
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode.
|
||||
* When window compare mode is enabled, user can connect the specific analog voltage
|
||||
* source to either the positive inputs of both comparators or the negative inputs of
|
||||
* both comparators. The upper bound and lower bound of the designated range are
|
||||
* determined by the voltages applied to the other inputs of both comparators. If the
|
||||
* output of a comparator is low and the other comparator outputs high, which means two
|
||||
* comparators implies the upper and lower bound. User can directly monitor a specific
|
||||
* analog voltage source via ACMPWO (ACMP_STATUS[16]).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to disable ACMP window compare mode
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk)
|
||||
|
||||
|
||||
/* Function prototype declaration */
|
||||
void ACMP_Open(ACMP_T *, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn);
|
||||
void ACMP_Close(ACMP_T *, uint32_t u32ChNum);
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group ACMP_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif //__NU_ACMP_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,418 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_adc.h
|
||||
* @version V0.10
|
||||
* $Revision: 2 $
|
||||
* $Date: 19/01/11 11:23a $
|
||||
* @brief M031 Series ADC Driver Header File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_ADC_H__
|
||||
#define __NU_ADC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Driver ADC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_EXPORTED_CONSTANTS ADC Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* ADCR Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define ADC_ADCR_ADEN_CONVERTER_DISABLE (0UL<<ADC_ADCR_ADEN_Pos) /*!< ADC converter disable \hideinitializer */
|
||||
#define ADC_ADCR_ADEN_CONVERTER_ENABLE (1UL<<ADC_ADCR_ADEN_Pos) /*!< ADC converter enable \hideinitializer */
|
||||
|
||||
#define ADC_ADCR_ADMD_SINGLE (0UL<<ADC_ADCR_ADMD_Pos) /*!< Single mode \hideinitializer */
|
||||
#define ADC_ADCR_ADMD_BURST (1UL<<ADC_ADCR_ADMD_Pos) /*!< Burst mode \hideinitializer */
|
||||
#define ADC_ADCR_ADMD_SINGLE_CYCLE (2UL<<ADC_ADCR_ADMD_Pos) /*!< Single cycle scan mode \hideinitializer */
|
||||
#define ADC_ADCR_ADMD_CONTINUOUS (3UL<<ADC_ADCR_ADMD_Pos) /*!< Continuous scan mode \hideinitializer */
|
||||
|
||||
#define ADC_ADCR_DIFFEN_SINGLE_END (0UL<<ADC_ADCR_DIFFEN_Pos) /*!< Single-end input mode \hideinitializer */
|
||||
#define ADC_ADCR_DIFFEN_DIFFERENTIAL (1UL<<ADC_ADCR_DIFFEN_Pos) /*!< Differential input mode \hideinitializer */
|
||||
|
||||
#define ADC_ADCR_DMOF_UNSIGNED_OUTPUT (0UL<<ADC_ADCR_DMOF_Pos) /*!< Select the straight binary format as the output format of the conversion result \hideinitializer */
|
||||
#define ADC_ADCR_DMOF_TWOS_COMPLEMENT (1UL<<ADC_ADCR_DMOF_Pos) /*!< Select the 2's complement format as the output format of the conversion result \hideinitializer */
|
||||
|
||||
#define ADC_ADCR_TRGEN_DISABLE (0UL<<ADC_ADCR_TRGEN_Pos) /*!< Disable triggering of A/D conversion by external STADC pin or PWM \hideinitializer */
|
||||
#define ADC_ADCR_TRGEN_ENABLE (1UL<<ADC_ADCR_TRGEN_Pos) /*!< Enable triggering of A/D conversion by external STADC pin or PWM \hideinitializer */
|
||||
|
||||
#define ADC_ADCR_TRGS_STADC (0UL<<ADC_ADCR_TRGS_Pos) /*!< A/D conversion is started by external STADC pin \hideinitializer */
|
||||
#define ADC_ADCR_TRGS_TIMER (1UL<<ADC_ADCR_TRGS_Pos) /*!< A/D conversion is started by Timer \hideinitializer */
|
||||
#define ADC_ADCR_TRGS_BPWM (2UL<<ADC_ADCR_TRGS_Pos) /*!< A/D conversion is started by BPWM \hideinitializer */
|
||||
#define ADC_ADCR_TRGS_PWM (3UL<<ADC_ADCR_TRGS_Pos) /*!< A/D conversion is started by PWM \hideinitializer */
|
||||
|
||||
#define ADC_ADCR_TRGCOND_LOW_LEVEL (0UL<<ADC_ADCR_TRGCOND_Pos) /*!< STADC Low level active \hideinitializer */
|
||||
#define ADC_ADCR_TRGCOND_HIGH_LEVEL (1UL<<ADC_ADCR_TRGCOND_Pos) /*!< STADC High level active \hideinitializer */
|
||||
#define ADC_ADCR_TRGCOND_FALLING_EDGE (2UL<<ADC_ADCR_TRGCOND_Pos) /*!< STADC Falling edge active \hideinitializer */
|
||||
#define ADC_ADCR_TRGCOND_RISING_EDGE (3UL<<ADC_ADCR_TRGCOND_Pos) /*!< STADC Rising edge active \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* ADCMPR Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define ADC_ADCMPR_CMPD(x) ((x) << ADC_ADCMPR_CMPD_Pos) /*!< Compare value for compare function \hideinitializer */
|
||||
#define ADC_ADCMPR_CMPMATCNT(x) (((x)-1) << ADC_ADCMPR_CMPMATCNT_Pos) /*!< Match count for compare function \hideinitializer */
|
||||
#define ADC_ADCMPR_CMPCH(x) ((x) << ADC_ADCMPR_CMPCH_Pos) /*!< Compare channel for compare function \hideinitializer */
|
||||
#define ADC_ADCMPR_CMPCOND_LESS_THAN (0<<ADC_ADCMPR_CMPCOND_Pos) /*!< The compare condition is "less than" \hideinitializer */
|
||||
#define ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL (1<<ADC_ADCMPR_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" \hideinitializer */
|
||||
#define ADC_ADCMPR_CMPIE_INTERRUPT_ENABLE (ADC_ADCMPR_CMPIE_Msk) /*!< The compare function interrupt enable \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* ADC Interrupt Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define ADC_ADF_INT (ADC_ADSR0_ADF_Msk) /*!< ADC convert complete interrupt \hideinitializer */
|
||||
#define ADC_CMP0_INT (ADC_ADSR0_CMPF0_Msk) /*!< ADC comparator 0 interrupt \hideinitializer */
|
||||
#define ADC_CMP1_INT (ADC_ADSR0_CMPF1_Msk) /*!< ADC comparator 1 interrupt \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* ADC Operation Mode Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define ADC_SINGLE_MODE 0 /*!< ADC single mode \hideinitializer */
|
||||
#define ADC_BURST_MODE 1 /*!< ADC burst mode \hideinitializer */
|
||||
#define ADC_SINGLE_CYCLE_MODE 2 /*!< ADC single-cycle scan mode \hideinitializer */
|
||||
#define ADC_CONTINUOUS_MODE 3 /*!< ADC continuous scan mode \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* ADC Trigger Condition Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define ADC_LOW_LEVEL 0 /*!< ADC external trigger condition is low level trigger \hideinitializer */
|
||||
#define ADC_HIGH_LEVEL 1 /*!< ADC external trigger condition is high level trigger \hideinitializer */
|
||||
#define ADC_FALLING_EDGE 2 /*!< ADC external trigger condition is falling edge trigger \hideinitializer */
|
||||
#define ADC_RISING_EDGE 3 /*!< ADC external trigger condition is rising edge trigger \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* ADC Compare Condition Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define ADC_LESS_THAN 0 /*!< ADC compare condition is "less than the compare value" \hideinitializer */
|
||||
#define ADC_GREATER_OR_EQUAL 1 /*!< ADC compare condition is "greater than or equal to the compare value" \hideinitializer */
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group ADC_EXPORTED_CONSTANTS */
|
||||
|
||||
/** @addtogroup ADC_EXPORTED_FUNCTIONS ADC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get conversion data of specified channel.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @param[in] u32ChNum ADC Channel, valid value are from 0 to 15 and 29.
|
||||
* @return 16-bit data.
|
||||
* @details Read RSLT bit field to get conversion data.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ((adc)->ADDR[(u32ChNum)] & ADC_ADDR_RSLT_Msk)
|
||||
|
||||
/**
|
||||
* @brief Return the user-specified interrupt flags.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
|
||||
* Valid values are:
|
||||
* - \ref ADC_ADF_INT :Convert complete interrupt flag.
|
||||
* - \ref ADC_CMP0_INT :Comparator 0 interrupt flag.
|
||||
* - \ref ADC_CMP1_INT :Comparator 1 interrupt flag.
|
||||
* @return User specified interrupt flags.
|
||||
* @details Get the status of the ADC interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_GET_INT_FLAG(adc, u32Mask) ((adc)->ADSR0 & (u32Mask))
|
||||
|
||||
/**
|
||||
* @brief This macro clear the selected interrupt status bits.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
|
||||
* Valid values are:
|
||||
* - \ref ADC_ADF_INT :Convert complete interrupt flag.
|
||||
* - \ref ADC_CMP0_INT :Comparator 0 interrupt flag.
|
||||
* - \ref ADC_CMP1_INT :Comparator 1 interrupt flag.
|
||||
* @return None
|
||||
* @details ADF (ADSR0[0])/CMPF0 (ADSR0[1])/CMPF1 (ADSR0[2]) can be cleared by writing 1 to itself.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_CLR_INT_FLAG(adc, u32Mask) ((adc)->ADSR0 = (u32Mask))
|
||||
|
||||
/**
|
||||
* @brief Get the busy state of ADC.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @retval 0 ADC is not busy.
|
||||
* @retval 1 ADC is busy.
|
||||
* @details ADSR0[7] (BUSY) is a mirror of ADCR[11] (ADST).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_IS_BUSY(adc) ((adc)->ADSR0 & ADC_ADSR0_BUSY_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Check if the ADC conversion data is over written or not.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @param[in] u32ChNum ADC Channel, valid value are from 0 to 15 and 29.
|
||||
* @retval 0 ADC data is not overrun.
|
||||
* @retval 1 ADC data is overrun.
|
||||
* @details ADSR2[31:0] (OVERRUN) is the mirror of ADDR0~31[16] OVERRUN bits.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) (((adc)->ADSR2 & (1<<(u32ChNum))) ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Check if the ADC conversion data is valid or not.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @param[in] u32ChNum ADC Channel, valid value are from 0 to 15 and 29.
|
||||
* @retval 0 ADC data is not valid.
|
||||
* @retval 1 ADC data is valid.
|
||||
* @details VALID (ADDR0~31[17]) is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_IS_DATA_VALID(adc, u32ChNum) ((adc)->ADSR1 & (0x1<<(u32ChNum)) ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Power down ADC module.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @return None
|
||||
* @details Disable A/D converter analog circuit for saving power consumption.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_POWER_DOWN(adc) ((adc)->ADCR &= ~ADC_ADCR_ADEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Power on ADC module.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @return None
|
||||
* @details Before starting A/D conversion function, ADEN bit (ADCR[0]) should be set to 1.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_POWER_ON(adc) ((adc)->ADCR |= ADC_ADCR_ADEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Configure the comparator 0 and enable it.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 15 and 29.
|
||||
* @param[in] u32Condition Specifies the compare condition. Valid values are:
|
||||
* - \ref ADC_ADCMPR_CMPCOND_LESS_THAN :The compare condition is "less than the compare value".
|
||||
* - \ref ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value".
|
||||
* @param[in] u32Data Specifies the compare value, valid value are between 0 ~ 0xFFF.
|
||||
* @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16.
|
||||
* @return None
|
||||
* @details For example, ADC_ENABLE_CMP0(ADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10);
|
||||
* means ADC will assert comparator 0 flag if channel 5 conversion result is greater than or
|
||||
* equal to 0x800 for 10 times continuously.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_ENABLE_CMP0(adc, \
|
||||
u32ChNum, \
|
||||
u32Condition, \
|
||||
u32Data, \
|
||||
u32MatchCount) ((adc)->ADCMPR[0] = ((u32ChNum) << ADC_ADCMPR_CMPCH_Pos) | \
|
||||
(u32Condition) | \
|
||||
((u32Data) << ADC_ADCMPR_CMPD_Pos) | \
|
||||
(((u32MatchCount) - 1) << ADC_ADCMPR_CMPMATCNT_Pos) |\
|
||||
ADC_ADCMPR_CMPEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable comparator 0
|
||||
* @param[in] adc The pointer of the specified ADC module
|
||||
* @return None
|
||||
* @details Set CMPEN (ADCMPR0[0]) to 0 and reset comparator 0 configurations to disable ADC compare function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_DISABLE_CMP0(adc) ((adc)->ADCMPR[0] = 0)
|
||||
|
||||
/**
|
||||
* @brief Configure the comparator 1 and enable it.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 15 and 29.
|
||||
* @param[in] u32Condition Specifies the compare condition. Valid values are:
|
||||
* - \ref ADC_ADCMPR_CMPCOND_LESS_THAN :The compare condition is "less than the compare value".
|
||||
* - \ref ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value".
|
||||
* @param[in] u32Data Specifies the compare value, valid value are between 0 ~ 0xFFF.
|
||||
* @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16.
|
||||
* @return None
|
||||
* @details For example, ADC_ENABLE_CMP1(ADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10);
|
||||
* means ADC will assert comparator 1 flag if channel 5 conversion result is greater than or
|
||||
* equal to 0x800 for 10 times continuously.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_ENABLE_CMP1(adc, \
|
||||
u32ChNum, \
|
||||
u32Condition, \
|
||||
u32Data, \
|
||||
u32MatchCount) ((adc)->ADCMPR[1] = ((u32ChNum) << ADC_ADCMPR_CMPCH_Pos) | \
|
||||
(u32Condition) | \
|
||||
((u32Data) << ADC_ADCMPR_CMPD_Pos) | \
|
||||
(((u32MatchCount) - 1) << ADC_ADCMPR_CMPMATCNT_Pos) |\
|
||||
ADC_ADCMPR_CMPEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable comparator 1.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @return None
|
||||
* @details Set CMPEN (ADCMPR1[0]) to 0 and reset comparator 1 configurations to disable ADC compare function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_DISABLE_CMP1(adc) ((adc)->ADCMPR[1] = 0)
|
||||
|
||||
/**
|
||||
* @brief Enable the compare window mode.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @param[in] u32CMP Specifies the compare register, valid value are 0.
|
||||
* @return None
|
||||
* @details CMPF0 (ADSR0[1]) will be set when both ADC_CMP0 and ADC_CMP1 compared condition matched.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_ENABLE_CMP_WINDOW_MODE(adc, u32CMP) ((adc)->ADCMPR[(u32CMP)] |= ADC_ADCMPR_CMPWEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable the compare window mode.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @param[in] u32CMP Specifies the compare register, valid value are 0.
|
||||
* @return None
|
||||
* @details Disable the compare window mode for specified ADC module.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_DISABLE_CMP_WINDOW_MODE(adc, u32CMP) ((adc)->ADCMPR[(u32CMP)] &= ~ADC_ADCMPR_CMPWEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set ADC input channel.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1..., bit 15 is channel 15.
|
||||
* @return None
|
||||
* @details Enabled channel will be converted while ADC starts.
|
||||
* @note In single mode, ADC can only convert 1 channel. If more than 1 channel are enabled, only the channel with smallest number will be converted.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) ((adc)->ADCHER = ((adc)->ADCHER & ~ADC_ADCHER_CHEN_Msk) | (u32Mask))
|
||||
|
||||
/**
|
||||
* @brief Set the output format mode.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @param[in] u32Format Decides the output format. Valid values are:
|
||||
* - \ref ADC_ADCR_DMOF_UNSIGNED_OUTPUT : Select the straight binary format as the output format of the conversion result.
|
||||
* - \ref ADC_ADCR_DMOF_TWOS_COMPLEMENT : Select the 2's complement format as the output format of the conversion result.
|
||||
* @return None
|
||||
* @details The macro is used to set the output format of ADC differential input mode.
|
||||
* @note ADC compare function can not support 2's complement output format, u32Format should be set to ADC_ADCR_DMOF_UNSIGNED_OUTPUT.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_SET_DMOF(adc, u32Format) ((adc)->ADCR = ((adc)->ADCR & ~ADC_ADCR_DMOF_Msk) | (u32Format))
|
||||
|
||||
/**
|
||||
* @brief Start the A/D conversion.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @return None
|
||||
* @details Set ADST bit to 1 to start the A/D conversion.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_START_CONV(adc) ((adc)->ADCR |= ADC_ADCR_ADST_Msk)
|
||||
|
||||
/**
|
||||
* @brief Stop the A/D conversion.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @return None
|
||||
* @details ADST (ADCR[11]) will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode.
|
||||
* In continuous scan mode and burst mode, A/D conversion is continuously performed until software writes 0 to this bit.
|
||||
* @note When the ADST bit is cleared to 0, the ADST bit must be kept at 0 at least one ADC peripheral clock period
|
||||
* before setting it to 1 again, otherwise the A/D converter may not work.
|
||||
* If ADST bit is cleared to 0 when ADC is in converting, the BUSY bit will be cleared to 0 immediately,
|
||||
* ADC will terminate the current conversion and enter idle state directly.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_STOP_CONV(adc) ((adc)->ADCR &= ~ADC_ADCR_ADST_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable PDMA transfer.
|
||||
* @param[in] adc The pointer of the specified ADC module
|
||||
* @return None
|
||||
* @details Enable PDMA to transfer the conversion data.
|
||||
* @note While enable PDMA transfer, software must set ADIE = 0 to disable interrupt.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_ENABLE_PDMA(adc) ((adc)->ADCR |= ADC_ADCR_PTEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable PDMA transfer.
|
||||
* @param[in] adc The pointer of the specified ADC module
|
||||
* @return None
|
||||
* @details Disable PDMA to transfer the conversion data.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_DISABLE_PDMA(adc) ((adc)->ADCR &= ~ADC_ADCR_PTEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get PDMA current transfer data
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @return PDMA current transfer data
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_GET_PDMA_DATA(adc) ((adc)->ADPDMA & ADC_ADPDMA_CURDAT_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable the interrupt(s) selected by u32Mask parameter.
|
||||
* @param[in] adc The pointer of the specified ADC module
|
||||
* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
|
||||
* corresponds to a interrupt status. This parameter decides which
|
||||
* interrupts will be enabled.
|
||||
* - \ref ADC_ADF_INT :ADC convert complete interrupt
|
||||
* - \ref ADC_CMP0_INT :ADC comparator 0 interrupt
|
||||
* - \ref ADC_CMP1_INT :ADC comparator 1 interrupt
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_ENABLE_INT ADC_EnableInt
|
||||
|
||||
/**
|
||||
* @brief Disable the interrupt(s) selected by u32Mask parameter.
|
||||
* @param[in] adc The pointer of the specified ADC module
|
||||
* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
|
||||
* corresponds to a interrupt status. This parameter decides which
|
||||
* interrupts will be disabled.
|
||||
* - \ref ADC_ADF_INT :ADC convert complete interrupt
|
||||
* - \ref ADC_CMP0_INT :ADC comparator 0 interrupt
|
||||
* - \ref ADC_CMP1_INT :ADC comparator 1 interrupt
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_DISABLE_INT ADC_DisableInt
|
||||
|
||||
|
||||
void ADC_Open(ADC_T *adc,
|
||||
uint32_t u32InputMode,
|
||||
uint32_t u32OpMode,
|
||||
uint32_t u32ChMask);
|
||||
void ADC_Close(ADC_T *adc);
|
||||
void ADC_EnableHWTrigger(ADC_T *adc,
|
||||
uint32_t u32Source,
|
||||
uint32_t u32Param);
|
||||
void ADC_DisableHWTrigger(ADC_T *adc);
|
||||
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
|
||||
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
|
||||
void ADC_SetExtendSampleTime(ADC_T *adc,
|
||||
uint32_t u32ModuleNum,
|
||||
uint32_t u32ExtendSampleTime);
|
||||
|
||||
|
||||
/*@}*/ /* end of group ADC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group ADC_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__NU_ADC_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,379 +0,0 @@
|
|||
/******************************************************************************
|
||||
* @file nu_bpwm.h
|
||||
* @version V1.00
|
||||
* $Revision: 9 $
|
||||
* $Date: 18/06/07 3:47p $
|
||||
* @brief M031 series BPWM driver header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_BPWM_H__
|
||||
#define __NU_BPWM_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup BPWM_Driver BPWM Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define BPWM_CHANNEL_NUM (6UL) /*!< BPWM channel number */
|
||||
#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask */
|
||||
#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask */
|
||||
#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask */
|
||||
#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask */
|
||||
#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask */
|
||||
#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Counter Type Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define BPWM_UP_COUNTER (0UL) /*!< Up counter type */
|
||||
#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type */
|
||||
#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Aligned Type Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) */
|
||||
#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Output Level Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing */
|
||||
#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low */
|
||||
#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high */
|
||||
#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Synchronous Start Function Control Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define BPWM_SSCTL_SSRC_PWM0 (0UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM0 */
|
||||
#define BPWM_SSCTL_SSRC_PWM1 (1UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM1 */
|
||||
#define BPWM_SSCTL_SSRC_BPWM0 (2UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM0 */
|
||||
#define BPWM_SSCTL_SSRC_BPWM1 (3UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM1 */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Trigger Source Select Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define BPWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< BPWM trigger ADC while counter of even channel matches zero point */
|
||||
#define BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< BPWM trigger ADC while counter of even channel matches period point */
|
||||
#define BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< BPWM trigger ADC while counter of even channel matches zero or period point */
|
||||
#define BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT (3UL) /*!< BPWM trigger ADC while counter of even channel matches up count to comparator point */
|
||||
#define BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT (4UL) /*!< BPWM trigger ADC while counter of even channel matches down count to comparator point */
|
||||
#define BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT (8UL) /*!< BPWM trigger ADC while counter of odd channel matches up count to comparator point */
|
||||
#define BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT (9UL) /*!< BPWM trigger ADC while counter of odd channel matches down count to comparator point */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Capture Control Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define BPWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< BPWM capture interrupt if channel has rising transition */
|
||||
#define BPWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< BPWM capture interrupt if channel has falling transition */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Duty Interrupt Type Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (BPWM_INTEN_CMPDIEN0_Msk) /*!< BPWM duty interrupt triggered if down count match comparator */
|
||||
#define BPWM_DUTY_INT_UP_COUNT_MATCH_CMP (BPWM_INTEN_CMPUIEN0_Msk) /*!< BPWM duty interrupt triggered if up down match comparator */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Load Mode Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define BPWM_LOAD_MODE_IMMEDIATE (BPWM_CTL0_IMMLDEN0_Msk) /*!< BPWM immediately load mode */
|
||||
#define BPWM_LOAD_MODE_CENTER (BPWM_CTL0_CTRLD0_Msk) /*!< BPWM center load mode */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Clock Source Select Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define BPWM_CLKSRC_BPWM_CLK (0UL) /*!< BPWM Clock source selects to BPWM0_CLK or BPWM1_CLK */
|
||||
#define BPWM_CLKSRC_TIMER0 (1UL) /*!< BPWM Clock source selects to TIMER0 overflow */
|
||||
#define BPWM_CLKSRC_TIMER1 (2UL) /*!< BPWM Clock source selects to TIMER1 overflow */
|
||||
#define BPWM_CLKSRC_TIMER2 (3UL) /*!< BPWM Clock source selects to TIMER2 overflow */
|
||||
#define BPWM_CLKSRC_TIMER3 (4UL) /*!< BPWM Clock source selects to TIMER3 overflow */
|
||||
|
||||
/*@}*/ /* end of group BPWM_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable timer synchronous start counting function of specified channel(s)
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
|
||||
* @param[in] u32SyncSrc Synchronous start source selection, valid values are:
|
||||
* - \ref BPWM_SSCTL_SSRC_PWM0
|
||||
* - \ref BPWM_SSCTL_SSRC_PWM1
|
||||
* - \ref BPWM_SSCTL_SSRC_BPWM0
|
||||
* - \ref BPWM_SSCTL_SSRC_BPWM1
|
||||
* @return None
|
||||
* @details This macro is used to enable timer synchronous start counting function of specified channel(s).
|
||||
* @note All channels share channel 0's setting.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_ENABLE_TIMER_SYNC(bpwm, u32ChannelMask, u32SyncSrc) ((bpwm)->SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable timer synchronous start counting function of specified channel(s)
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
|
||||
* @return None
|
||||
* @details This macro is used to disable timer synchronous start counting function of specified channel(s).
|
||||
* @note All channels share channel 0's setting.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro enable BPWM counter synchronous start counting function.
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @return None
|
||||
* @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time.
|
||||
* To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC().
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro enable output inverter of specified channel(s)
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask))
|
||||
|
||||
/**
|
||||
* @brief This macro get captured rising data
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT)
|
||||
|
||||
/**
|
||||
* @brief This macro get captured falling data
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT)
|
||||
|
||||
/**
|
||||
* @brief This macro mask output logic to high or low
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||
* @param[in] u32LevelMask Output logic to high or low
|
||||
* @return None
|
||||
* @details This macro is used to mask output logic to high or low of specified channel(s).
|
||||
* @note If u32ChannelMask parameter is 0, then mask function will be disabled.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \
|
||||
{ \
|
||||
(bpwm)->MSKEN = (u32ChannelMask); \
|
||||
(bpwm)->MSK = (u32LevelMask); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This macro set the prescaler of all channels
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||
* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler))
|
||||
|
||||
/**
|
||||
* @brief This macro get the prescaler of the selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5. This parameter is not used.
|
||||
* @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
|
||||
* @details This macro is used to get the prescaler of specified channel.
|
||||
* @note All channels share channel 0's setting.
|
||||
* The clock of BPWM counter is divided by (u32Prescaler + 1).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_GET_PRESCALER(bpwm, u32ChannelNum) (bpwm)->CLKPSC
|
||||
|
||||
/**
|
||||
* @brief This macro set the duty of the selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
|
||||
* @return None
|
||||
* @note This new setting will take effect on next BPWM period
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
|
||||
|
||||
/**
|
||||
* @brief This macro get the duty of the selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @return Return the duty of specified channel. Valid values are between 0~0xFFFF
|
||||
* @details This macro is used to get the duty of specified channel.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)])
|
||||
|
||||
/**
|
||||
* @brief This macro set the period of all channels
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||
* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
|
||||
* @return None
|
||||
* @note This new setting will take effect on next BPWM period
|
||||
* @note BPWM counter will stop if period length set to 0
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR))
|
||||
|
||||
/**
|
||||
* @brief This macro get the period of all channels
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||
* @return Return the period of specified channel.
|
||||
* @details This macro is used to get the period of specified channel.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD)
|
||||
|
||||
/**
|
||||
* @brief This macro set the BPWM aligned type
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
|
||||
* @param[in] u32AlignedType BPWM aligned type, valid values are:
|
||||
* - \ref BPWM_UP_COUNTER
|
||||
* - \ref BPWM_DOWN_COUNTER
|
||||
* - \ref BPWM_UP_DOWN_COUNTER
|
||||
* @return None
|
||||
* @note All channels share channel 0's setting.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType))
|
||||
|
||||
/**
|
||||
* @brief Clear counter of channel 0
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
|
||||
* @return None
|
||||
* @details This macro is used to clear counter of channel 0
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk))
|
||||
|
||||
/**
|
||||
* @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||
* @param[in] u32ZeroLevel output level at zero point, valid values are:
|
||||
* - \ref BPWM_OUTPUT_NOTHING
|
||||
* - \ref BPWM_OUTPUT_LOW
|
||||
* - \ref BPWM_OUTPUT_HIGH
|
||||
* - \ref BPWM_OUTPUT_TOGGLE
|
||||
* @param[in] u32CmpUpLevel output level at compare up point, valid values are:
|
||||
* - \ref BPWM_OUTPUT_NOTHING
|
||||
* - \ref BPWM_OUTPUT_LOW
|
||||
* - \ref BPWM_OUTPUT_HIGH
|
||||
* - \ref BPWM_OUTPUT_TOGGLE
|
||||
* @param[in] u32PeriodLevel output level at period(center) point, valid values are:
|
||||
* - \ref BPWM_OUTPUT_NOTHING
|
||||
* - \ref BPWM_OUTPUT_LOW
|
||||
* - \ref BPWM_OUTPUT_HIGH
|
||||
* - \ref BPWM_OUTPUT_TOGGLE
|
||||
* @param[in] u32CmpDownLevel output level at compare down point, valid values are:
|
||||
* - \ref BPWM_OUTPUT_NOTHING
|
||||
* - \ref BPWM_OUTPUT_LOW
|
||||
* - \ref BPWM_OUTPUT_HIGH
|
||||
* - \ref BPWM_OUTPUT_TOGGLE
|
||||
* @return None
|
||||
* @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s)
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
|
||||
do{ \
|
||||
uint32_t i; \
|
||||
for(i = 0UL; i < 6UL; i++) { \
|
||||
if((u32ChannelMask) & (1UL << i)) { \
|
||||
(bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (i << 1UL))) | ((u32ZeroLevel) << (i << 1UL))); \
|
||||
(bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1UL)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1UL)))); \
|
||||
(bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (i << 1UL))) | ((u32CmpUpLevel) << (i << 1UL))); \
|
||||
(bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1UL)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1UL)))); \
|
||||
} \
|
||||
} \
|
||||
}while(0)
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Define BPWM functions prototype */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
|
||||
uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
|
||||
void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask);
|
||||
void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask);
|
||||
void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask);
|
||||
void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
||||
void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
||||
uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
|
||||
void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
|
||||
void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
|
||||
void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
|
||||
void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||
void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||
void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||
uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
|
||||
void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
|
||||
void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
|
||||
void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
|
||||
void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
|
||||
uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||
|
||||
|
||||
/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group BPWM_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __NU_BPWM_H__ */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,600 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_clk.h
|
||||
* @version V0.10
|
||||
* $Revision: 12 $
|
||||
* $Date: 18/07/05 4:42p $
|
||||
* @brief M031 Series Clock Controller (CLK) Driver Header File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_CLK_H__
|
||||
#define __NU_CLK_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup CLK_Driver CLK Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
#define FREQ_4MHZ 4000000 /*!< Define frequency macro 4MHz \hideinitializer */
|
||||
#define FREQ_8MHZ 8000000 /*!< Define frequency macro 8MHz \hideinitializer */
|
||||
#define FREQ_12MHZ 12000000 /*!< Define frequency macro 12MHz \hideinitializer */
|
||||
#define FREQ_16MHZ 16000000 /*!< Define frequency macro 16MHz \hideinitializer */
|
||||
#define FREQ_24MHZ 24000000 /*!< Define frequency macro 24MHz \hideinitializer */
|
||||
#define FREQ_25MHZ 25000000 /*!< Define frequency macro 25MHz \hideinitializer */
|
||||
#define FREQ_32MHZ 32000000 /*!< Define frequency macro 32MHz \hideinitializer */
|
||||
#define FREQ_48MHZ 48000000 /*!< Define frequency macro 48MHz \hideinitializer */
|
||||
#define FREQ_50MHZ 50000000 /*!< Define frequency macro 50MHz \hideinitializer */
|
||||
#define FREQ_51MHZ 51000000 /*!< Define frequency macro 51MHz \hideinitializer */
|
||||
#define FREQ_64MHZ 64000000 /*!< Define frequency macro 64MHz \hideinitializer */
|
||||
#define FREQ_68MHZ 68000000 /*!< Define frequency macro 68MHz \hideinitializer */
|
||||
#define FREQ_72MHZ 72000000 /*!< Define frequency macro 72MHz \hideinitializer */
|
||||
#define FREQ_96MHZ 96000000 /*!< Define frequency macro 96MHz \hideinitializer */
|
||||
#define FREQ_100MHZ 100000000 /*!< Define frequency macro 100MHz \hideinitializer */
|
||||
#define FREQ_144MHZ 144000000 /*!< Define frequency macro 144MHz \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* PWRCTL constant definitions. (Write-protection) */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_PWRCTL_HXTGAIN_L0 (0) /*!< Setting HXT Gain Control to level 0 for lower than 4MHz external crystal \hideinitializer */
|
||||
#define CLK_PWRCTL_HXTGAIN_L1 (1) /*!< Setting HXT Gain Control to level 1 for 4MHz ~ 8MHz external crystal \hideinitializer */
|
||||
#define CLK_PWRCTL_HXTGAIN_L2 (2) /*!< Setting HXT Gain Control to level 2 for 8MHz ~ 12MHz external crystal \hideinitializer */
|
||||
#define CLK_PWRCTL_HXTGAIN_L3 (3) /*!< Setting HXT Gain Control to level 3 for 12MHz ~ 16MHz external crystal \hideinitializer */
|
||||
#define CLK_PWRCTL_HXTGAIN_L4 (4) /*!< Setting HXT Gain Control to level 4 for 16MHz ~ 24MHz external crystal \hideinitializer */
|
||||
#define CLK_PWRCTL_HXTGAIN_L5 (5) /*!< Setting HXT Gain Control to level 5 \hideinitializer */
|
||||
#define CLK_PWRCTL_HXTGAIN_L6 (6) /*!< Setting HXT Gain Control to level 6 \hideinitializer */
|
||||
#define CLK_PWRCTL_HXTGAIN_L7 (7) /*!< Setting HXT Gain Control to level 7 for 24MHz ~ 32MHz external crystal \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CLKSEL0 constant definitions. (Write-protection) */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL0_HCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL0_HCLKSEL_PLL (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as PLL output \hideinitializer */
|
||||
#define CLK_CLKSEL0_HCLKSEL_LIRC (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as internal low speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL0_HCLKSEL_HIRC (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as internal high speed RC clock \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL0_STCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL0_STCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as external X'tal/2 \hideinitializer */
|
||||
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HCLK/2 \hideinitializer */
|
||||
#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as internal high speed RC clock/2 \hideinitializer */
|
||||
#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos) /*!< Setting SysTick clock source as HCLK \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL0_USBDSEL_HIRC (0x00UL<<CLK_CLKSEL0_USBDSEL_Pos) /*!< Setting USBD clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL0_USBDSEL_PLL (0x01UL<<CLK_CLKSEL0_USBDSEL_Pos) /*!< Setting USBD clock source as PLL output \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CLKSEL1 constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as HCLK/2048 \hideinitializer */
|
||||
#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as internal low speed RC clock \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting WWDT clock source as HCLK/2048 \hideinitializer */
|
||||
#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting WWDT clock source as internal low speed RC clock \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HCLK \hideinitializer */
|
||||
#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external internal high speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL1_CLKOSEL_LIRC (0x4UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external internal low speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL1_CLKOSEL_PLL (0x6UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as PLL \hideinitializer */
|
||||
#define CLK_CLKSEL1_CLKOSEL_SOF (0x7UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as USB SOF \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as PCLK0 \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR0SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external trigger \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as internal low speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as internal high speed RC clock \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as PCLK0 \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR1SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external trigger \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as internal low speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as internal high speed RC clock \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as PCLK1 \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR2SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external trigger \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as internal low speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as internal high speed RC clock \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as PCLK1 \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR3SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external trigger \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as internal low speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as internal high speed RC clock \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL1_UART0SEL_HXT (0x0UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL1_UART0SEL_PLL (0x1UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as external PLL \hideinitializer */
|
||||
#define CLK_CLKSEL1_UART0SEL_LXT (0x2UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as external internal high speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL1_UART0SEL_PCLK0 (0x4UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as external PCLK0 \hideinitializer */
|
||||
#define CLK_CLKSEL1_UART0SEL_LIRC (0x5UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as external LIRC \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL1_UART1SEL_HXT (0x0UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL1_UART1SEL_PLL (0x1UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as external PLL \hideinitializer */
|
||||
#define CLK_CLKSEL1_UART1SEL_LXT (0x2UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as external internal high speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL1_UART1SEL_PCLK1 (0x4UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as external PCLK1 \hideinitializer */
|
||||
#define CLK_CLKSEL1_UART1SEL_LIRC (0x5UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as external LIRC \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CLKSEL2 constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_CLKSEL2_PWM0SEL_PLL (0x0UL<<CLK_CLKSEL2_PWM0SEL_Pos) /*!< Setting PWM0 clock source as PLL \hideinitializer */
|
||||
#define CLK_CLKSEL2_PWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL2_PWM0SEL_Pos) /*!< Setting PWM0 clock source as PCLK0 \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL2_PWM1SEL_PLL (0x0UL<<CLK_CLKSEL2_PWM1SEL_Pos) /*!< Setting PWM1 clock source as PLL \hideinitializer */
|
||||
#define CLK_CLKSEL2_PWM1SEL_PCLK1 (0x1UL<<CLK_CLKSEL2_PWM1SEL_Pos) /*!< Setting PWM1 clock source as PCLK1 \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting QSPI clock source as HXT \hideinitializer */
|
||||
#define CLK_CLKSEL2_QSPI0SEL_PLL (0x1UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting QSPI clock source as PLL \hideinitializer */
|
||||
#define CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting QSPI clock source as PCLK0 \hideinitializer */
|
||||
#define CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting QSPI clock source as HIRC \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI clock source as HXT \hideinitializer */
|
||||
#define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI clock source as PLL \hideinitializer */
|
||||
#define CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI clock source as PCLK1 \hideinitializer */
|
||||
#define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI clock source as HIRC \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL2_BPWM0SEL_PLL (0x0UL<<CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Setting BPWM0 clock source as PLL \hideinitializer */
|
||||
#define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Setting BPWM0 clock source as PCLK0 \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL2_BPWM1SEL_PLL (0x0UL<<CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Setting BPWM1 clock source as PLL \hideinitializer */
|
||||
#define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL<<CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Setting BPWM1 clock source as PCLK1 \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL2_ADCSEL_HXT (0x0UL<<CLK_CLKSEL2_ADCSEL_Pos) /*!< Setting ADC clock source as HXT \hideinitializer */
|
||||
#define CLK_CLKSEL2_ADCSEL_PLL (0x1UL<<CLK_CLKSEL2_ADCSEL_Pos) /*!< Setting ADC clock source as PLL \hideinitializer */
|
||||
#define CLK_CLKSEL2_ADCSEL_PCLK1 (0x2UL<<CLK_CLKSEL2_ADCSEL_Pos) /*!< Setting ADC clock source as PCLK1 \hideinitializer */
|
||||
#define CLK_CLKSEL2_ADCSEL_HIRC (0x3UL<<CLK_CLKSEL2_ADCSEL_Pos) /*!< Setting ADC clock source as HIRC \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CLKSEL3 constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_CLKSEL3_UART3SEL_HXT (0x0UL<<CLK_CLKSEL3_UART3SEL_Pos) /*!< Setting UART3 clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART3SEL_PLL (0x1UL<<CLK_CLKSEL3_UART3SEL_Pos) /*!< Setting UART3 clock source as external PLL \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART3SEL_LXT (0x2UL<<CLK_CLKSEL3_UART3SEL_Pos) /*!< Setting UART3 clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART3SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART3SEL_Pos) /*!< Setting UART3 clock source as external internal high speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART3SEL_PCLK1 (0x4UL<<CLK_CLKSEL3_UART3SEL_Pos) /*!< Setting UART3 clock source as external PCLK1 \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART3SEL_LIRC (0x5UL<<CLK_CLKSEL3_UART3SEL_Pos) /*!< Setting UART3 clock source as external LIRC \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL3_UART2SEL_HXT (0x0UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART2SEL_PLL (0x1UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as external PLL \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART2SEL_LXT (0x2UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART2SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as external internal high speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART2SEL_PCLK0 (0x4UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as external PCLK0 \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART2SEL_LIRC (0x5UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as external LIRC \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL3_UART5SEL_HXT (0x0UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART5SEL_PLL (0x1UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as external PLL \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART5SEL_LXT (0x2UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART5SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as external internal high speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART5SEL_PCLK1 (0x4UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as external PCLK1 \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART5SEL_LIRC (0x5UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as external LIRC \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL3_UART4SEL_HXT (0x0UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART4SEL_PLL (0x1UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as external PLL \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART4SEL_LXT (0x2UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART4SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as external internal high speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART4SEL_PCLK0 (0x4UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as external PCLK0 \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART4SEL_LIRC (0x5UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as external LIRC \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL3_UART7SEL_HXT (0x0UL<<CLK_CLKSEL3_UART7SEL_Pos) /*!< Setting UART7 clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART7SEL_PLL (0x1UL<<CLK_CLKSEL3_UART7SEL_Pos) /*!< Setting UART7 clock source as external PLL \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART7SEL_LXT (0x2UL<<CLK_CLKSEL3_UART7SEL_Pos) /*!< Setting UART7 clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART7SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART7SEL_Pos) /*!< Setting UART7 clock source as external internal high speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART7SEL_PCLK1 (0x4UL<<CLK_CLKSEL3_UART7SEL_Pos) /*!< Setting UART7 clock source as external PCLK1 \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART7SEL_LIRC (0x5UL<<CLK_CLKSEL3_UART7SEL_Pos) /*!< Setting UART7 clock source as external LIRC \hideinitializer */
|
||||
|
||||
#define CLK_CLKSEL3_UART6SEL_HXT (0x0UL<<CLK_CLKSEL3_UART6SEL_Pos) /*!< Setting UART6 clock source as external X'tal \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART6SEL_PLL (0x1UL<<CLK_CLKSEL3_UART6SEL_Pos) /*!< Setting UART6 clock source as external PLL \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART6SEL_LXT (0x2UL<<CLK_CLKSEL3_UART6SEL_Pos) /*!< Setting UART6 clock source as external X'tal 32.768KHz \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART6SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART6SEL_Pos) /*!< Setting UART6 clock source as external internal high speed RC clock \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART6SEL_PCLK0 (0x4UL<<CLK_CLKSEL3_UART6SEL_Pos) /*!< Setting UART6 clock source as external PCLK0 \hideinitializer */
|
||||
#define CLK_CLKSEL3_UART6SEL_LIRC (0x5UL<<CLK_CLKSEL3_UART6SEL_Pos) /*!< Setting UART6 clock source as external LIRC \hideinitializer */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CLKDIV0 constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_CLKDIV0_HCLK(x) (((x)-1) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV Setting for HCLK clock divider. It could be 1~16 \hideinitializer */
|
||||
#define CLK_CLKDIV0_USB(x) (((x)-1) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV Setting for USB clock divider. It could be 1~16 \hideinitializer */
|
||||
#define CLK_CLKDIV0_UART0(x) (((x)-1) << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLKDIV Setting for UART0 clock divider. It could be 1~16 \hideinitializer */
|
||||
#define CLK_CLKDIV0_UART1(x) (((x)-1) << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLKDIV Setting for UART1 clock divider. It could be 1~16 \hideinitializer */
|
||||
#define CLK_CLKDIV0_ADC(x) (((x)-1) << CLK_CLKDIV0_ADCDIV_Pos) /*!< CLKDIV Setting for ADC clock divider. It could be 1~256 \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CLKDIV4 constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_CLKDIV4_UART2(x) (((x)-1) << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLKDIV Setting for UART2 clock divider. It could be 1~16 \hideinitializer */
|
||||
#define CLK_CLKDIV4_UART3(x) (((x)-1) << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLKDIV Setting for UART3 clock divider. It could be 1~16 \hideinitializer */
|
||||
#define CLK_CLKDIV4_UART4(x) (((x)-1) << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLKDIV Setting for UART4 clock divider. It could be 1~16 \hideinitializer */
|
||||
#define CLK_CLKDIV4_UART5(x) (((x)-1) << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLKDIV Setting for UART5 clock divider. It could be 1~16 \hideinitializer */
|
||||
#define CLK_CLKDIV4_UART6(x) (((x)-1) << CLK_CLKDIV4_UART6DIV_Pos) /*!< CLKDIV Setting for UART6 clock divider. It could be 1~16 \hideinitializer */
|
||||
#define CLK_CLKDIV4_UART7(x) (((x)-1) << CLK_CLKDIV4_UART7DIV_Pos) /*!< CLKDIV Setting for UART7 clock divider. It could be 1~16 \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* PCLKDIV constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_PCLKDIV_APB0DIV_DIV1 (0x0UL<<CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for APB0 clock divider 1. \hideinitializer */
|
||||
#define CLK_PCLKDIV_APB0DIV_DIV2 (0x1UL<<CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for APB0 clock divider 2. \hideinitializer */
|
||||
#define CLK_PCLKDIV_APB0DIV_DIV4 (0x2UL<<CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for APB0 clock divider 4. \hideinitializer */
|
||||
#define CLK_PCLKDIV_APB0DIV_DIV8 (0x3UL<<CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for APB0 clock divider 8. \hideinitializer */
|
||||
#define CLK_PCLKDIV_APB0DIV_DIV16 (0x4UL<<CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for APB0 clock divider 16. \hideinitializer */
|
||||
|
||||
#define CLK_PCLKDIV_APB1DIV_DIV1 (0x0UL<<CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for APB1 clock divider 1. \hideinitializer */
|
||||
#define CLK_PCLKDIV_APB1DIV_DIV2 (0x1UL<<CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for APB1 clock divider 2. \hideinitializer */
|
||||
#define CLK_PCLKDIV_APB1DIV_DIV4 (0x2UL<<CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for APB1 clock divider 4. \hideinitializer */
|
||||
#define CLK_PCLKDIV_APB1DIV_DIV8 (0x3UL<<CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for APB1 clock divider 8. \hideinitializer */
|
||||
#define CLK_PCLKDIV_APB1DIV_DIV16 (0x4UL<<CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for APB1 clock divider 16. \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* PLLCTL constant definitions. PLL = FIN * NF / NR / NO */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_PLLCTL_PLLSRC_HXT (0x0UL << CLK_PLLCTL_PLLSRC_Pos) /*!< For PLL clock source is HXT. 4~12MHz < FIN < 24MHz \hideinitializer */
|
||||
#define CLK_PLLCTL_PLLSRC_HIRC_DIV4 (0x1UL << CLK_PLLCTL_PLLSRC_Pos) /*!< For PLL clock source is HIRC/4. 12 MHz< FIN < 12MHz \hideinitializer */
|
||||
|
||||
#define CLK_PLLCTL_NR(x) ((x-2)<<CLK_PLLCTL_INDIV_Pos) /*!< For PLL input divider. x must be constant and 2 <= x <= 7 since constraint 1.6MHz < FIN/NR < 16MHz and NR = INDIV+2 >= 2 \hideinitializer */
|
||||
#define CLK_PLLCTL_NF(x) ((x-2)<<CLK_PLLCTL_FBDIV_Pos) /*!< For PLL feedback divider. x must be constant and 17 <= x/NR <= 41 since constraint 200MHz < FIN*NF/NR < 500MHz. \hideinitializer */
|
||||
|
||||
#define CLK_PLLCTL_NO_1 (0x0UL << CLK_PLLCTL_OUTDIV_Pos) /*!< For PLL output divider is 1 \hideinitializer */
|
||||
#define CLK_PLLCTL_NO_2 (0x1UL << CLK_PLLCTL_OUTDIV_Pos) /*!< For PLL output divider is 2 \hideinitializer */
|
||||
#define CLK_PLLCTL_NO_4 (0x3UL << CLK_PLLCTL_OUTDIV_Pos) /*!< For PLL output divider is 4 \hideinitializer */
|
||||
|
||||
#define CLK_PLLCTL_64MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(8) | CLK_PLLCTL_NF(64) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 64MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
|
||||
#define CLK_PLLCTL_68MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(8) | CLK_PLLCTL_NF(68) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 68MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
|
||||
#define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(8) | CLK_PLLCTL_NF(72) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
|
||||
#define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(8) | CLK_PLLCTL_NF(96) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 96MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
|
||||
#define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(8) | CLK_PLLCTL_NF(72) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
|
||||
#define CLK_PLLCTL_64MHz_HIRC_DIV4 (CLK_PLLCTL_PLLSRC_HIRC_DIV4 | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF(64) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 64MHz PLL output with HIRC_DIV4(12MHz IRC) \hideinitializer */
|
||||
#define CLK_PLLCTL_68MHz_HIRC_DIV4 (CLK_PLLCTL_PLLSRC_HIRC_DIV4 | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF(68) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 68MHz PLL output with HIRC_DIV4(12MHz IRC) \hideinitializer */
|
||||
#define CLK_PLLCTL_72MHz_HIRC_DIV4 (CLK_PLLCTL_PLLSRC_HIRC_DIV4 | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF(72) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HIRC_DIV4(12MHz IRC) \hideinitializer */
|
||||
#define CLK_PLLCTL_96MHz_HIRC_DIV4 (CLK_PLLCTL_PLLSRC_HIRC_DIV4 | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF(96) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 96MHz PLL output with HIRC_DIV4(12MHz IRC) \hideinitializer */
|
||||
#define CLK_PLLCTL_144MHz_HIRC_DIV4 (CLK_PLLCTL_PLLSRC_HIRC_DIV4 | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF(72) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HIRC_DIV4(12MHz IRC) \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* MODULE constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
|
||||
|
||||
#define MODULE_APBCLK(x) (((x) >>30) & 0x3UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */
|
||||
#define MODULE_CLKSEL(x) (((x) >>28) & 0x3UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */
|
||||
#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7UL) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */
|
||||
#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */
|
||||
#define MODULE_CLKDIV(x) (((x) >>18) & 0x3UL) /*!< Calculate CLKDIV offset on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */
|
||||
#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xffUL) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */
|
||||
#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */
|
||||
#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */
|
||||
#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index \hideinitializer */
|
||||
#define NA MODULE_NoMsk /*!< Not Available \hideinitializer */
|
||||
|
||||
#define MODULE_APBCLK_ENC(x) (((x) & 0x03UL) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */
|
||||
#define MODULE_CLKSEL_ENC(x) (((x) & 0x03UL) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */
|
||||
#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 25) /*!< CLKSEL mask offset on MODULE index \hideinitializer */
|
||||
#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 20) /*!< CLKSEL position offset on MODULE index \hideinitializer */
|
||||
#define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */
|
||||
#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xffUL) << 10) /*!< CLKDIV mask offset on MODULE index \hideinitializer */
|
||||
#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index \hideinitializer */
|
||||
#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */
|
||||
|
||||
|
||||
//AHBCLK
|
||||
#define PDMA_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_PDMACKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module \hideinitializer */
|
||||
|
||||
#define ISP_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_ISPCKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ISP Module \hideinitializer */
|
||||
|
||||
#define EBI_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_EBICKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EBI Module \hideinitializer */
|
||||
|
||||
#define HDIV_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_HDIVCKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< HDIV Module \hideinitializer */
|
||||
|
||||
#define CRC_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_CRCCKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module \hideinitializer */
|
||||
|
||||
//APBCLK0
|
||||
#define WDT_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_WDTCKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL1_WDTSEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WDT Module \hideinitializer */
|
||||
|
||||
#define WWDT_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_WDTCKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL1_WWDTSEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WWDT Module \hideinitializer */
|
||||
|
||||
#define RTC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_RTCCKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< RTC Module \hideinitializer */
|
||||
|
||||
#define TMR0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR0CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL1_TMR0SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR0 Module \hideinitializer */
|
||||
|
||||
#define TMR1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR1CKEN_Pos) |\
|
||||
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL1_TMR1SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR1 Module \hideinitializer */
|
||||
|
||||
#define TMR2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR2CKEN_Pos) |\
|
||||
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL1_TMR2SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR2 Module \hideinitializer */
|
||||
|
||||
#define TMR3_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR3CKEN_Pos) |\
|
||||
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL1_TMR3SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR3 Module \hideinitializer */
|
||||
|
||||
#define CLKO_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_CLKOCKEN_Pos) |\
|
||||
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL1_CLKOSEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CLKO Module \hideinitializer */
|
||||
|
||||
#define UART0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART0CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL1_UART0SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0xF)|MODULE_CLKDIV_Pos_ENC(CLK_CLKDIV0_UART0DIV_Pos)) /*!< UART0 Module \hideinitializer */
|
||||
|
||||
#define UART1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART1CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL1_UART1SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0xF)|MODULE_CLKDIV_Pos_ENC(CLK_CLKDIV0_UART1DIV_Pos)) /*!< UART1 Module \hideinitializer */
|
||||
|
||||
#define UART2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART2CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL3_UART2SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC( 3)|MODULE_CLKDIV_Msk_ENC(0xF)|MODULE_CLKDIV_Pos_ENC(CLK_CLKDIV4_UART2DIV_Pos)) /*!< UART2 Module \hideinitializer */
|
||||
|
||||
#define UART3_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART3CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL3_UART3SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC( 3)|MODULE_CLKDIV_Msk_ENC(0xF)|MODULE_CLKDIV_Pos_ENC(CLK_CLKDIV4_UART3DIV_Pos)) /*!< UART3 Module \hideinitializer */
|
||||
|
||||
#define UART4_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART4CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL3_UART4SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC( 3)|MODULE_CLKDIV_Msk_ENC(0xF)|MODULE_CLKDIV_Pos_ENC(CLK_CLKDIV4_UART4DIV_Pos)) /*!< UART4 Module \hideinitializer */
|
||||
|
||||
#define UART5_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART5CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL3_UART5SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC( 3)|MODULE_CLKDIV_Msk_ENC(0xF)|MODULE_CLKDIV_Pos_ENC(CLK_CLKDIV4_UART5DIV_Pos)) /*!< UART5 Module \hideinitializer */
|
||||
|
||||
#define UART6_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART6CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL3_UART6SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC( 3)|MODULE_CLKDIV_Msk_ENC(0xF)|MODULE_CLKDIV_Pos_ENC(CLK_CLKDIV4_UART6DIV_Pos)) /*!< UART6 Module \hideinitializer */
|
||||
|
||||
#define UART7_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART7CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL3_UART7SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC( 3)|MODULE_CLKDIV_Msk_ENC(0xF)|MODULE_CLKDIV_Pos_ENC(CLK_CLKDIV4_UART7DIV_Pos)) /*!< UART7 Module \hideinitializer */
|
||||
|
||||
#define I2C0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C0CKEN_Pos) |\
|
||||
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C0 Module \hideinitializer */
|
||||
|
||||
#define I2C1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C1CKEN_Pos) |\
|
||||
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C1 Module \hideinitializer */
|
||||
|
||||
#define QSPI0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_QSPI0CKEN_Pos) |\
|
||||
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL2_QSPI0SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QSPI0 Module \hideinitializer */
|
||||
|
||||
#define SPI0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI0CKEN_Pos) |\
|
||||
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL2_SPI0SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI0 Module \hideinitializer */
|
||||
|
||||
#define ADC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_ADCCKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL2_ADCSEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC(CLK_CLKDIV0_ADCDIV_Pos)) /*!< ADC Module \hideinitializer */
|
||||
|
||||
#define ACMP01_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_ACMP01CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP Module \hideinitializer */
|
||||
|
||||
#define USBD_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_USBDCKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 0)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL0_USBDSEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0xF)|MODULE_CLKDIV_Pos_ENC(CLK_CLKDIV0_USBDIV_Pos)) /*!< USBD Module \hideinitializer */
|
||||
|
||||
//APBCLK1
|
||||
#define PWM0_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PWM0CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL2_PWM0SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM0 Module \hideinitializer */
|
||||
|
||||
#define PWM1_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PWM1CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL2_PWM1SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM1 Module \hideinitializer */
|
||||
|
||||
#define BPWM0_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_BPWM0CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL2_BPWM0SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM0 Module \hideinitializer */
|
||||
|
||||
#define BPWM1_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_BPWM1CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC(CLK_CLKSEL2_BPWM1SEL_Pos)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM1 Module \hideinitializer */
|
||||
|
||||
#define USCI0_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_USCI0CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI0 Module \hideinitializer */
|
||||
|
||||
#define USCI1_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_USCI1CKEN_Pos)|\
|
||||
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI1 Module \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */
|
||||
|
||||
/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* static inline functions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Get PLL Clock Output Frequency
|
||||
* @param None
|
||||
* @return PLL clock output frequency
|
||||
* @details To get actual PLL clock output frequency. The clock uint is in Hz.
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE uint32_t CLK_GetPLLClockFreq(void)
|
||||
{
|
||||
uint32_t u32PllFreq;
|
||||
uint32_t u32FIN, u32NF, u32NR, u32NO;
|
||||
uint8_t au8NoTbl[4] = {1, 2, 2, 4}; /* OUTDIV :DEF: {1, 2, 2, 4} */
|
||||
uint32_t u32Reg;
|
||||
|
||||
u32PllFreq = 0;
|
||||
u32Reg = CLK->PLLCTL;
|
||||
|
||||
if ((u32Reg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) == 0)
|
||||
{
|
||||
/* PLL is enabled and output enabled */
|
||||
if (u32Reg & CLK_PLLCTL_PLLSRC_Msk)
|
||||
{
|
||||
u32FIN = (__HIRC >> 2);
|
||||
} else
|
||||
u32FIN = __HXT;
|
||||
|
||||
if (u32Reg & CLK_PLLCTL_BP_Msk)
|
||||
{
|
||||
/* PLL is in bypass mode */
|
||||
u32PllFreq = u32FIN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* PLL is in normal work mode */
|
||||
u32NO = au8NoTbl[((u32Reg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
|
||||
u32NF = ((u32Reg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2;
|
||||
u32NR = ((u32Reg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 2;
|
||||
/* u32FIN is shifted 2 bits to avoid overflow */
|
||||
u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2);
|
||||
}
|
||||
}
|
||||
|
||||
return u32PllFreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function execute delay function.
|
||||
* @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
|
||||
* 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...
|
||||
* @return None
|
||||
* @details Use the SysTick to generate the delay time and the UNIT is in us.
|
||||
* The SysTick clock source is from HCLK, i.e. the same as system core clock.
|
||||
* User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
|
||||
{
|
||||
SysTick->LOAD = us * CyclesPerUs;
|
||||
SysTick->VAL = (0x00);
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
|
||||
|
||||
/* Waiting for down-count to zero */
|
||||
while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
|
||||
|
||||
/* Disable SysTick counter */
|
||||
SysTick->CTRL = 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get current UART0 clock frquency.
|
||||
* @param None.
|
||||
* @return UART0 clock frquency. The clock UNIT is in Hz.
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE uint32_t CLK_GetUARTFreq(void)
|
||||
{
|
||||
uint32_t u32Freqout, u32AHBDivider, u32ClkSel, PCLK0Div;
|
||||
|
||||
u32Freqout = 0;
|
||||
u32ClkSel = CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk ;
|
||||
|
||||
if (u32ClkSel == CLK_CLKSEL1_UART0SEL_HXT) /* external HXT crystal clock */
|
||||
{
|
||||
u32Freqout = __HXT;
|
||||
}
|
||||
else if(u32ClkSel == CLK_CLKSEL1_UART0SEL_PLL) /* PLL clock */
|
||||
{
|
||||
u32Freqout = CLK_GetPLLClockFreq();
|
||||
}
|
||||
else if(u32ClkSel == CLK_CLKSEL1_UART0SEL_LXT) /* LXT clock */
|
||||
{
|
||||
u32Freqout = __LXT;
|
||||
}
|
||||
else if(u32ClkSel == CLK_CLKSEL1_UART0SEL_HIRC) /* HIRC clock */
|
||||
{
|
||||
u32Freqout = __HIRC;
|
||||
}
|
||||
else if(u32ClkSel == CLK_CLKSEL1_UART0SEL_PCLK0) /* PCLK0 clock */
|
||||
{
|
||||
PCLK0Div = (CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) >> CLK_PCLKDIV_APB0DIV_Pos;
|
||||
u32Freqout = (SystemCoreClock >> PCLK0Div);
|
||||
}
|
||||
else if(u32ClkSel == CLK_CLKSEL1_UART0SEL_LIRC) /* LIRC clock */
|
||||
{
|
||||
u32Freqout = __LIRC;
|
||||
}
|
||||
|
||||
u32AHBDivider = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) + 1 ;
|
||||
|
||||
return (u32Freqout/u32AHBDivider);
|
||||
}
|
||||
|
||||
|
||||
uint32_t CLK_WaitClockReady(uint32_t);
|
||||
void CLK_DisableCKO(void);
|
||||
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
|
||||
uint32_t CLK_GetHCLKFreq(void);
|
||||
uint32_t CLK_GetCPUFreq(void);
|
||||
uint32_t CLK_GetLXTFreq(void);
|
||||
uint32_t CLK_GetHXTFreq(void);
|
||||
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
|
||||
uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
|
||||
uint32_t CLK_GetPCLK0Freq(void);
|
||||
uint32_t CLK_GetPCLK1Freq(void);
|
||||
void CLK_EnableXtalRC(uint32_t u32ClkMask);
|
||||
void CLK_DisableXtalRC(uint32_t u32ClkMask);
|
||||
void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
|
||||
void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
|
||||
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
|
||||
void CLK_DisablePLL(void);
|
||||
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
|
||||
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
|
||||
void CLK_DisableSysTick(void);
|
||||
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
|
||||
void CLK_PowerDown(void);
|
||||
void CLK_Idle(void);
|
||||
|
||||
/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group CLK_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __NU_CLK_H__ */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,117 +0,0 @@
|
|||
/******************************************************************************
|
||||
* @file nu_crc.h
|
||||
* @version V1.00
|
||||
* $Revision: 9 $
|
||||
* $Date: 18/07/09 4:18p $
|
||||
* @brief M031 series CRC driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __NU_CRC_H__
|
||||
#define __NU_CRC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Driver CRC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants
|
||||
@{
|
||||
*/
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CRC Polynomial Mode Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CRC_CCITT (0UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CCITT \hideinitializer */
|
||||
#define CRC_8 (1UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC8 \hideinitializer */
|
||||
#define CRC_16 (2UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC16 \hideinitializer */
|
||||
#define CRC_32 (3UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC32 \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Checksum, Write data Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CRC_CHECKSUM_COM (CRC_CTL_CHKSFMT_Msk) /*!<CRC Checksum Complement \hideinitializer */
|
||||
#define CRC_CHECKSUM_RVS (CRC_CTL_CHKSREV_Msk) /*!<CRC Checksum Reverse \hideinitializer */
|
||||
#define CRC_WDATA_COM (CRC_CTL_DATFMT_Msk) /*!<CRC Write Data Complement \hideinitializer */
|
||||
#define CRC_WDATA_RVS (CRC_CTL_DATREV_Msk) /*!<CRC Write Data Reverse \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Write Data Length Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CRC_WDATA_8 (0UL << CRC_CTL_DATLEN_Pos) /*!<CRC Write Data length is 8-bit \hideinitializer */
|
||||
#define CRC_WDATA_16 (1UL << CRC_CTL_DATLEN_Pos) /*!<CRC Write Data length is 16-bit \hideinitializer */
|
||||
#define CRC_WDATA_32 (2UL << CRC_CTL_DATLEN_Pos) /*!<CRC Write Data length is 32-bit \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group CRC_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set CRC Seed Value
|
||||
*
|
||||
* @param[in] u32Seed Seed value
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to set CRC seed value.
|
||||
*
|
||||
* @note User must to perform CRC_CHKSINIT(CRC_CTL[1] CRC Engine Reset) to reload the new seed value
|
||||
* to CRC controller.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define CRC_SET_SEED(u32Seed) do{ CRC->SEED = (u32Seed); CRC->CTL |= CRC_CTL_CHKSINIT_Msk; }while(0)
|
||||
|
||||
/**
|
||||
* @brief Get CRC Seed Value
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return CRC seed value
|
||||
*
|
||||
* @details This macro gets the current CRC seed value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define CRC_GET_SEED() (CRC->SEED)
|
||||
|
||||
/**
|
||||
* @brief CRC Write Data
|
||||
*
|
||||
* @param[in] u32Data Write data
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define CRC_WRITE_DATA(u32Data) (CRC->DAT = (u32Data))
|
||||
|
||||
void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
|
||||
uint32_t CRC_GetChecksum(void);
|
||||
|
||||
/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group CRC_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,260 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_ebi.h
|
||||
* @version V1.00
|
||||
* $Revision: 3 $
|
||||
* $Date: 18/06/07 2:32p $
|
||||
* @brief M031 series External Bus Interface(EBI) driver header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_EBI_H__
|
||||
#define __NU_EBI_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup EBI_Driver EBI Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants
|
||||
@{
|
||||
*/
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Miscellaneous Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address \hideinitializer */
|
||||
#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address \hideinitializer */
|
||||
#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Constants for EBI bank number */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */
|
||||
#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Constants for EBI data bus width */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */
|
||||
#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Constants for EBI CS Active Level */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */
|
||||
#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Constants for EBI MCLK divider and Timing */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */
|
||||
#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */
|
||||
#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */
|
||||
#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */
|
||||
#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */
|
||||
#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */
|
||||
|
||||
#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */
|
||||
#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */
|
||||
#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */
|
||||
#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */
|
||||
#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */
|
||||
#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */
|
||||
#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */
|
||||
|
||||
#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */
|
||||
#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Read 8-bit data on EBI bank0
|
||||
*
|
||||
* @param[in] u32Addr The data address on EBI bank0.
|
||||
*
|
||||
* @return 8-bit Data
|
||||
*
|
||||
* @details This macro is used to read 8-bit data from specify address on EBI bank0.
|
||||
*/
|
||||
#define EBI0_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
|
||||
|
||||
/**
|
||||
* @brief Write 8-bit data to EBI bank0
|
||||
*
|
||||
* @param[in] u32Addr The data address on EBI bank0.
|
||||
* @param[in] u32Data Specify data to be written.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to write 8-bit data to specify address on EBI bank0.
|
||||
*/
|
||||
#define EBI0_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||
|
||||
/**
|
||||
* @brief Read 16-bit data on EBI bank0
|
||||
*
|
||||
* @param[in] u32Addr The data address on EBI bank0.
|
||||
*
|
||||
* @return 16-bit Data
|
||||
*
|
||||
* @details This macro is used to read 16-bit data from specify address on EBI bank0.
|
||||
*/
|
||||
#define EBI0_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
|
||||
|
||||
/**
|
||||
* @brief Write 16-bit data to EBI bank0
|
||||
*
|
||||
* @param[in] u32Addr The data address on EBI bank0.
|
||||
* @param[in] u32Data Specify data to be written.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to write 16-bit data to specify address on EBI bank0.
|
||||
*/
|
||||
#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||
|
||||
/**
|
||||
* @brief Read 32-bit data on EBI bank0
|
||||
*
|
||||
* @param[in] u32Addr The data address on EBI bank0.
|
||||
*
|
||||
* @return 32-bit Data
|
||||
*
|
||||
* @details This macro is used to read 32-bit data from specify address on EBI bank0.
|
||||
*/
|
||||
#define EBI0_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
|
||||
|
||||
/**
|
||||
* @brief Write 32-bit data to EBI bank0
|
||||
*
|
||||
* @param[in] u32Addr The data address on EBI bank0.
|
||||
* @param[in] u32Data Specify data to be written.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to write 32-bit data to specify address on EBI bank0.
|
||||
*/
|
||||
#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||
|
||||
/**
|
||||
* @brief Read 8-bit data on EBI bank1
|
||||
*
|
||||
* @param[in] u32Addr The data address on EBI bank1.
|
||||
*
|
||||
* @return 8-bit Data
|
||||
*
|
||||
* @details This macro is used to read 8-bit data from specify address on EBI bank1.
|
||||
*/
|
||||
#define EBI1_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
|
||||
|
||||
/**
|
||||
* @brief Write 8-bit data to EBI bank1
|
||||
*
|
||||
* @param[in] u32Addr The data address on EBI bank1.
|
||||
* @param[in] u32Data Specify data to be written.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to write 8-bit data to specify address on EBI bank1.
|
||||
*/
|
||||
#define EBI1_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||
|
||||
/**
|
||||
* @brief Read 16-bit data on EBI bank1
|
||||
*
|
||||
* @param[in] u32Addr The data address on EBI bank1.
|
||||
*
|
||||
* @return 16-bit Data
|
||||
*
|
||||
* @details This macro is used to read 16-bit data from specify address on EBI bank1.
|
||||
*/
|
||||
#define EBI1_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
|
||||
|
||||
/**
|
||||
* @brief Write 16-bit data to EBI bank1
|
||||
*
|
||||
* @param[in] u32Addr The data address on EBI bank1.
|
||||
* @param[in] u32Data Specify data to be written.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to write 16-bit data to specify address on EBI bank1.
|
||||
*/
|
||||
#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||
|
||||
/**
|
||||
* @brief Read 32-bit data on EBI bank1
|
||||
*
|
||||
* @param[in] u32Addr The data address on EBI bank1.
|
||||
*
|
||||
* @return 32-bit Data
|
||||
*
|
||||
* @details This macro is used to read 32-bit data from specify address on EBI bank1.
|
||||
*/
|
||||
#define EBI1_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
|
||||
|
||||
/**
|
||||
* @brief Write 32-bit data to EBI bank1
|
||||
*
|
||||
* @param[in] u32Addr The data address on EBI bank1.
|
||||
* @param[in] u32Data Specify data to be written.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to write 32-bit data to specify address on EBI bank1.
|
||||
*/
|
||||
#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||
|
||||
/**
|
||||
* @brief Enable EBI Write Buffer
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to improve EBI write operation for EBI bank0 and bank1.
|
||||
*/
|
||||
#define EBI_ENABLE_WRITE_BUFFER() (EBI->CTL0 |= EBI_CTL_WBUFEN_Msk);
|
||||
|
||||
/**
|
||||
* @brief Disable EBI Write Buffer
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to disable EBI write buffer function.
|
||||
*/
|
||||
#define EBI_DISABLE_WRITE_BUFFER() (EBI->CTL0 &= ~EBI_CTL_WBUFEN_Msk);
|
||||
|
||||
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
|
||||
void EBI_Close(uint32_t u32Bank);
|
||||
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
|
||||
|
||||
/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group EBI_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__NU_EBI_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,269 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_fmc.h
|
||||
* @version V1.00
|
||||
* $Revision: 11 $
|
||||
* $Date: 18/06/20 3:38p $
|
||||
* @brief M031 Series Flash Memory Controller Driver Header File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
******************************************************************************/
|
||||
#ifndef __NU_FMC_H__
|
||||
#define __NU_FMC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup FMC_Driver FMC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
//#define PAGE_SIZE_2048 /*!< Please enable the compiler option for 2K page size */
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* Define Base Address */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
#define FMC_APROM_BASE 0x00000000UL /*!< APROM base address \hideinitializer */
|
||||
#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address \hideinitializer */
|
||||
#define FMC_SPROM_BASE 0x00200000UL /*!< SPROM Base Address \hideinitializer */
|
||||
#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address \hideinitializer */
|
||||
#define FMC_USER_CONFIG_0 0x00300000UL /*!< User Config 0 address \hideinitializer */
|
||||
#define FMC_USER_CONFIG_1 0x00300004UL /*!< User Config 1 address \hideinitializer */
|
||||
#define FMC_USER_CONFIG_2 0x00300008UL /*!< User Config 2 address \hideinitializer */
|
||||
|
||||
#ifndef PAGE_SIZE_2048
|
||||
#define FMC_FLASH_PAGE_SIZE (0x200) /*!< Flash Page Size (512 bytes) \hideinitializer */
|
||||
#define FMC_PAGE_ADDR_MASK (0xFFFFFE00UL) /*!< Flash page address mask \hideinitializer */
|
||||
|
||||
#define FMC_SPROM_SIZE (0x200) /*!< SPROM Size (512 bytes) \hideinitializer */
|
||||
#else
|
||||
#define FMC_FLASH_PAGE_SIZE (0x800) /*!< Flash Page Size (2048 bytes) \hideinitializer */
|
||||
#define FMC_PAGE_ADDR_MASK (0xFFFFF800UL) /*!< Flash page address mask \hideinitializer */
|
||||
|
||||
#define FMC_SPROM_SIZE (0x800) /*!< SPROM Size (2048 bytes) \hideinitializer */
|
||||
#endif
|
||||
|
||||
#define FMC_MULTI_WORD_PROG_LEN (256UL) /*!< The length of a multi-word program. \hideinitializer */
|
||||
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
/* ISPCMD constant definitions */
|
||||
/*----------------------------------------------------------------------------------------------------------*/
|
||||
#define FMC_ISPCMD_READ 0x00UL /*!< ISP Command: Read flash word \hideinitializer */
|
||||
#define FMC_ISPCMD_READ_UID 0x04UL /*!< ISP Command: Read Unique ID \hideinitializer */
|
||||
#define FMC_ISPCMD_READ_ALL1 0x08UL /*!< ISP Command: Read all-one result \hideinitializer */ // I version
|
||||
#define FMC_ISPCMD_READ_CID 0x0BUL /*!< ISP Command: Read Company ID \hideinitializer */
|
||||
#define FMC_ISPCMD_READ_DID 0x0CUL /*!< ISP Command: Read Device ID \hideinitializer */
|
||||
#define FMC_ISPCMD_READ_CKS 0x0DUL /*!< ISP Command: Read checksum \hideinitializer */
|
||||
#define FMC_ISPCMD_PROGRAM 0x21UL /*!< ISP Command: Write flash word \hideinitializer */
|
||||
#define FMC_ISPCMD_PROGRAM_64 0x61UL /*!< ISP Command: 64-bit program Flash \hideinitializer */
|
||||
#define FMC_ISPCMD_PAGE_ERASE 0x22UL /*!< ISP Command: Page Erase Flash \hideinitializer */
|
||||
#define FMC_ISPCMD_BANK_ERASE 0x23UL /*!< ISP Command: Bank Erase Flash \hideinitializer */
|
||||
#define FMC_ISPCMD_MULTI_PROG 0x27UL /*!< ISP Command: Flash Multi-Word Program \hideinitializer */
|
||||
#define FMC_ISPCMD_RUN_ALL1 0x28UL /*!< ISP Command: Run all-one verification \hideinitializer */ // I version
|
||||
#define FMC_ISPCMD_RUN_CKS 0x2DUL /*!< ISP Command: Run checksum calculation \hideinitializer */
|
||||
#define FMC_ISPCMD_BANK_REMAP 0x2CUL /*!< ISP Command: Bank Remap \hideinitializer */
|
||||
#define FMC_ISPCMD_VECMAP 0x2EUL /*!< ISP Command: Vector Page Remap \hideinitializer */
|
||||
|
||||
#define IS_BOOT_FROM_APROM 0UL /*!< Is booting from APROM \hideinitializer */
|
||||
#define IS_BOOT_FROM_LDROM 1UL /*!< Is booting from LDROM \hideinitializer */
|
||||
|
||||
#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. \hideinitializer */
|
||||
#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. \hideinitializer */
|
||||
#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. \hideinitializer */
|
||||
/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Macros */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
#define FMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk) /*!< Select booting from APROM \hideinitializer */
|
||||
#define FMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk) /*!< Select booting from LDROM \hideinitializer */
|
||||
#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM update \hideinitializer */
|
||||
#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM update \hideinitializer */
|
||||
#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable User Config update \hideinitializer */
|
||||
#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable User Config update \hideinitializer */
|
||||
#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM update \hideinitializer */
|
||||
#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM update \hideinitializer */
|
||||
#define FMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk) /*!< Enable SPROM update \hideinitializer */
|
||||
#define FMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk) /*!< Disable SPROM update \hideinitializer */
|
||||
#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP function \hideinitializer */
|
||||
#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP function \hideinitializer */
|
||||
#define FMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL) /*!< Get ISP fail flag \hideinitializer */
|
||||
#define FMC_CLR_FAIL_FLAG() (FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk) /*!< Clear ISP fail flag \hideinitializer */
|
||||
#define FMC_ENABLE_ISP_INT() (FMC->ISPCTL |= FMC_ISPCTL_INTEN_Msk) /*!< Enable ISP interrupt */
|
||||
#define FMC_DISABLE_ISP_INT() (FMC->ISPCTL &= ~FMC_ISPCTL_INTEN_Msk) /*!< Disable ISP interrupt */
|
||||
#define FMC_GET_ISP_INT_FLAG() ((FMC->ISPSTS & FMC_ISPSTS_INTFLAG_Msk) ? 1UL : 0UL) /*!< Get ISP interrupt flag Status */
|
||||
#define FMC_CLEAR_ISP_INT_FLAG() (FMC->ISPSTS = FMC_ISPSTS_INTFLAG_Msk) /*!< Clear ISP interrupt flag*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
__STATIC_INLINE uint32_t FMC_ReadCID(void);
|
||||
__STATIC_INLINE uint32_t FMC_ReadPID(void);
|
||||
__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index);
|
||||
__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index);
|
||||
__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr);
|
||||
__STATIC_INLINE uint32_t FMC_GetVECMAP(void);
|
||||
|
||||
/**
|
||||
* @brief Get current vector mapping address.
|
||||
* @param None
|
||||
* @return The current vector mapping address.
|
||||
* @details To get VECMAP value which is the page address for remapping to vector page (0x0).
|
||||
* @note
|
||||
* VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FMC_GetVECMAP(void)
|
||||
{
|
||||
return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read company ID
|
||||
* @param None
|
||||
* @return The company ID (32-bit)
|
||||
* @details The company ID of Nuvoton is fixed to be 0xDA
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FMC_ReadCID(void)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */
|
||||
FMC->ISPADDR = 0x0u; /* Must keep 0x0 when read CID */
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
|
||||
#if ISBEN
|
||||
__ISB();
|
||||
#endif /* To make sure ISP/CPU be Synchronized */
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
|
||||
|
||||
return FMC->ISPDAT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read product ID
|
||||
* @param None
|
||||
* @return The product ID (32-bit)
|
||||
* @details This function is used to read product ID.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FMC_ReadPID(void)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */
|
||||
FMC->ISPADDR = 0x04u; /* Must keep 0x4 when read PID */
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
|
||||
#if ISBEN
|
||||
__ISB();
|
||||
#endif /* To make sure ISP/CPU be Synchronized */
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
|
||||
|
||||
return FMC->ISPDAT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read Unique ID
|
||||
* @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]
|
||||
* @return The 32-bit unique ID data of specified UID index.
|
||||
* @details To read out 96-bit Unique ID.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ_UID;
|
||||
FMC->ISPADDR = ((uint32_t)u8Index << 2u);
|
||||
FMC->ISPDAT = 0u;
|
||||
FMC->ISPTRG = 0x1u;
|
||||
#if ISBEN
|
||||
__ISB();
|
||||
#endif
|
||||
while (FMC->ISPTRG) {}
|
||||
|
||||
return FMC->ISPDAT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief To read UCID
|
||||
* @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
|
||||
* @return The UCID of specified index
|
||||
* @details This function is used to read unique chip ID (UCID).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
|
||||
FMC->ISPADDR = (0x04u * u32Index) + 0x10u; /* The UCID is at offset 0x10 with word alignment. */
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
|
||||
#if ISBEN
|
||||
__ISB();
|
||||
#endif /* To make sure ISP/CPU be Synchronized */
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
|
||||
|
||||
return FMC->ISPDAT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set vector mapping address
|
||||
* @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment.
|
||||
* @return To set VECMAP to remap specified page address to 0x0.
|
||||
* @details This function is used to set VECMAP to map specified page to vector page (0x0).
|
||||
* @note
|
||||
* VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
|
||||
*/
|
||||
__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */
|
||||
FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */
|
||||
FMC->ISPTRG = 0x1u; /* Trigger to start ISP procedure */
|
||||
#if ISBEN
|
||||
__ISB();
|
||||
#endif /* To make sure ISP/CPU be Synchronized */
|
||||
while (FMC->ISPTRG) {} /* Waiting for ISP Done */
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Functions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
extern void FMC_Close(void);
|
||||
extern int32_t FMC_Erase(uint32_t u32PageAddr);
|
||||
extern int32_t FMC_Erase_SPROM(void);
|
||||
extern int32_t FMC_Erase_Bank(uint32_t u32BankAddr);
|
||||
extern int32_t FMC_GetBootSource(void);
|
||||
extern void FMC_Open(void);
|
||||
extern uint32_t FMC_Read(uint32_t u32Addr);
|
||||
extern uint32_t FMC_ReadDataFlashBaseAddr(void);
|
||||
extern void FMC_SetBootSource(int32_t i32BootSrc);
|
||||
extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data);
|
||||
extern int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1);
|
||||
extern int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count);
|
||||
extern int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count);
|
||||
extern uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count);
|
||||
extern uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count);
|
||||
extern int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len);
|
||||
extern int32_t FMC_RemapBank(uint32_t u32BankIdx);
|
||||
|
||||
/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group FMC_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __NU_FMC_H__ */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,481 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_gpio.h
|
||||
* @version V0.10
|
||||
* $Revision: 2 $
|
||||
* $Date: 18/12/20 6:49p $
|
||||
* @brief M031 Series General Purpose I/O (GPIO) Driver Header File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_GPIO_H__
|
||||
#define __NU_GPIO_H__
|
||||
|
||||
#include "M031Series.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Driver GPIO Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
#define GPIO_PIN_MAX 16 /*!< Specify Maximum Pins of Each GPIO Port \hideinitializer */
|
||||
|
||||
|
||||
/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
|
||||
Example 1:
|
||||
|
||||
PA0 = 1;
|
||||
|
||||
It is used to set GPIO PA.0 to high;
|
||||
|
||||
Example 2:
|
||||
|
||||
if (PA0)
|
||||
PA0 = 0;
|
||||
|
||||
If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low.
|
||||
*/
|
||||
#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) /*!< Specify GPIO Pin Data Input/Output \hideinitializer */
|
||||
#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output \hideinitializer */
|
||||
#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output \hideinitializer */
|
||||
#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output \hideinitializer */
|
||||
#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output \hideinitializer */
|
||||
#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output \hideinitializer */
|
||||
#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output \hideinitializer */
|
||||
#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output \hideinitializer */
|
||||
#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output \hideinitializer */
|
||||
#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output \hideinitializer */
|
||||
#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output \hideinitializer */
|
||||
#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output \hideinitializer */
|
||||
#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output \hideinitializer */
|
||||
#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output \hideinitializer */
|
||||
#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output \hideinitializer */
|
||||
#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output \hideinitializer */
|
||||
#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output \hideinitializer */
|
||||
|
||||
#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output \hideinitializer */
|
||||
#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output \hideinitializer */
|
||||
#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output \hideinitializer */
|
||||
#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output \hideinitializer */
|
||||
#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output \hideinitializer */
|
||||
#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output \hideinitializer */
|
||||
#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output \hideinitializer */
|
||||
#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output \hideinitializer */
|
||||
#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output \hideinitializer */
|
||||
#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output \hideinitializer */
|
||||
#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output \hideinitializer */
|
||||
#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output \hideinitializer */
|
||||
#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output \hideinitializer */
|
||||
#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output \hideinitializer */
|
||||
#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output \hideinitializer */
|
||||
#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output \hideinitializer */
|
||||
|
||||
#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output \hideinitializer */
|
||||
#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output \hideinitializer */
|
||||
#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output \hideinitializer */
|
||||
#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output \hideinitializer */
|
||||
#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output \hideinitializer */
|
||||
#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output \hideinitializer */
|
||||
#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output \hideinitializer */
|
||||
#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output \hideinitializer */
|
||||
#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output \hideinitializer */
|
||||
#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output \hideinitializer */
|
||||
#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output \hideinitializer */
|
||||
#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output \hideinitializer */
|
||||
#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output \hideinitializer */
|
||||
#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output \hideinitializer */
|
||||
#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output \hideinitializer */
|
||||
|
||||
#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output \hideinitializer */
|
||||
#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output \hideinitializer */
|
||||
#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output \hideinitializer */
|
||||
#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output \hideinitializer */
|
||||
#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output \hideinitializer */
|
||||
#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output \hideinitializer */
|
||||
#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output \hideinitializer */
|
||||
#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output \hideinitializer */
|
||||
#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output \hideinitializer */
|
||||
#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output \hideinitializer */
|
||||
#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output \hideinitializer */
|
||||
#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output \hideinitializer */
|
||||
#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output \hideinitializer */
|
||||
#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output \hideinitializer */
|
||||
#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output \hideinitializer */
|
||||
#define PD15 GPIO_PIN_DATA(3, 15) /*!< Specify PD.15 Pin Data Input/Output \hideinitializer */
|
||||
|
||||
#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output \hideinitializer */
|
||||
#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output \hideinitializer */
|
||||
#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output \hideinitializer */
|
||||
#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output \hideinitializer */
|
||||
#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output \hideinitializer */
|
||||
#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output \hideinitializer */
|
||||
#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output \hideinitializer */
|
||||
#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output \hideinitializer */
|
||||
#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output \hideinitializer */
|
||||
#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output \hideinitializer */
|
||||
#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output \hideinitializer */
|
||||
#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output \hideinitializer */
|
||||
#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output \hideinitializer */
|
||||
#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output \hideinitializer */
|
||||
#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output \hideinitializer */
|
||||
#define PE15 GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output \hideinitializer */
|
||||
|
||||
#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output \hideinitializer */
|
||||
#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output \hideinitializer */
|
||||
#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output \hideinitializer */
|
||||
#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output \hideinitializer */
|
||||
#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output \hideinitializer */
|
||||
#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output \hideinitializer */
|
||||
#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output \hideinitializer */
|
||||
#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output \hideinitializer */
|
||||
#define PF8 GPIO_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output \hideinitializer */
|
||||
#define PF9 GPIO_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output \hideinitializer */
|
||||
#define PF10 GPIO_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output \hideinitializer */
|
||||
#define PF11 GPIO_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output \hideinitializer */
|
||||
#define PF14 GPIO_PIN_DATA(5, 14) /*!< Specify PF.14 Pin Data Input/Output \hideinitializer */
|
||||
#define PF15 GPIO_PIN_DATA(5, 15) /*!< Specify PF.15 Pin Data Input/Output \hideinitializer */
|
||||
|
||||
#define PG2 GPIO_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output \hideinitializer */
|
||||
#define PG3 GPIO_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output \hideinitializer */
|
||||
#define PG4 GPIO_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output \hideinitializer */
|
||||
#define PG9 GPIO_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output \hideinitializer */
|
||||
#define PG10 GPIO_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output \hideinitializer */
|
||||
#define PG11 GPIO_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output \hideinitializer */
|
||||
#define PG12 GPIO_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output \hideinitializer */
|
||||
#define PG13 GPIO_PIN_DATA(6, 13) /*!< Specify PG.13 Pin Data Input/Output \hideinitializer */
|
||||
#define PG14 GPIO_PIN_DATA(6, 14) /*!< Specify PG.14 Pin Data Input/Output \hideinitializer */
|
||||
#define PG15 GPIO_PIN_DATA(6, 15) /*!< Specify PG.15 Pin Data Input/Output \hideinitializer */
|
||||
|
||||
#define PH4 GPIO_PIN_DATA(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output \hideinitializer */
|
||||
#define PH5 GPIO_PIN_DATA(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output \hideinitializer */
|
||||
#define PH6 GPIO_PIN_DATA(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output \hideinitializer */
|
||||
#define PH7 GPIO_PIN_DATA(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output \hideinitializer */
|
||||
#define PH8 GPIO_PIN_DATA(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output \hideinitializer */
|
||||
#define PH9 GPIO_PIN_DATA(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output \hideinitializer */
|
||||
#define PH10 GPIO_PIN_DATA(7, 10) /*!< Specify PH.10 Pin Data Input/Output \hideinitializer */
|
||||
#define PH11 GPIO_PIN_DATA(7, 11) /*!< Specify PH.11 Pin Data Input/Output \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* GPIO_MODE Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode \hideinitializer */
|
||||
#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode \hideinitializer */
|
||||
#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode \hideinitializer */
|
||||
#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode \hideinitializer */
|
||||
#define GPIO_MODE(pin, mode) ((mode) << ((pin)<<1)) /*!< Generate the PMD mode setting for each pin \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* GPIO Interrupt Type Constant Definitions (Parameter of GPIO_EnableInt()) */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge \hideinitializer */
|
||||
#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge \hideinitializer */
|
||||
#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge \hideinitializer */
|
||||
#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High \hideinitializer */
|
||||
#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Low \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* GPIO_INTTYPE Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode \hideinitializer */
|
||||
#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Level Mode \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* GPIO_DBCTL Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define GPIO_DBCTL_ICLK_OFF (0x0UL<<GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 \hideinitializer */
|
||||
#define GPIO_DBCTL_ICLK_ON (0x1UL<<GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset \hideinitializer */
|
||||
|
||||
#define GPIO_DBCTL_DBCLKSRC_HCLK (0x0UL<<GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSRC_LIRC (0x1UL<<GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_DBCTL setting for de-bounce counter clock source is the LIRC \hideinitializer */
|
||||
|
||||
#define GPIO_DBCTL_DBCLKSEL_1 (0x0UL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_2 (0x1UL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_4 (0x2UL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_8 (0x3UL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_16 (0x4UL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_32 (0x5UL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_64 (0x6UL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_128 (0x7UL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_256 (0x8UL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_512 (0x9UL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_1024 (0xAUL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_2048 (0xBUL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_4096 (0xCUL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_8192 (0xDUL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_16384 (0xEUL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks \hideinitializer */
|
||||
#define GPIO_DBCTL_DBCLKSEL_32768 (0xFUL<<GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks \hideinitializer */
|
||||
|
||||
|
||||
/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */
|
||||
|
||||
/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clear GPIO Pin Interrupt Flag
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, or PH.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
|
||||
* It could be BIT0 ~ BIT15 for PA, PB, PD, and PE.
|
||||
* It could be BIT0 ~ BIT14 for PC.
|
||||
* It could be BIT0 ~ BIT11, BIT14, and BIT15 for PF.
|
||||
* It could be BIT2 ~ BIT4, and BIT9 ~ BIT15 for PG.
|
||||
* It could be BIT4 ~ BIT11 for PH.
|
||||
* @return None
|
||||
* @details Clear the interrupt status of specified GPIO pin.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask))
|
||||
|
||||
/**
|
||||
* @brief Disable Pin De-bounce Function
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, or PH.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
|
||||
* It could be BIT0 ~ BIT15 for PA, PB, PD, and PE.
|
||||
* It could be BIT0 ~ BIT14 for PC.
|
||||
* It could be BIT0 ~ BIT11, BIT14, and BIT15 for PF.
|
||||
* It could be BIT2 ~ BIT4, and BIT9 ~ BIT15 for PG.
|
||||
* It could be BIT4 ~ BIT11 for PH.
|
||||
* @return None
|
||||
* @details Disable the interrupt de-bounce function of specified GPIO pin.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask))
|
||||
|
||||
/**
|
||||
* @brief Enable Pin De-bounce Function
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, or PH.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
|
||||
* It could be BIT0 ~ BIT15 for PA, PB, PD, and PE.
|
||||
* It could be BIT0 ~ BIT14 for PC.
|
||||
* It could be BIT0 ~ BIT11, BIT14, and BIT15 for PF.
|
||||
* It could be BIT2 ~ BIT4, and BIT9 ~ BIT15 for PG.
|
||||
* It could be BIT4 ~ BIT11 for PH.
|
||||
* @return None
|
||||
* @details Enable the interrupt de-bounce function of specified GPIO pin.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask))
|
||||
|
||||
/**
|
||||
* @brief Disable I/O Digital Input Path
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, or PH.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
|
||||
* It could be BIT0 ~ BIT15 for PA, PB, PD, and PE.
|
||||
* It could be BIT0 ~ BIT14 for PC.
|
||||
* It could be BIT0 ~ BIT11, BIT14, and BIT15 for PF.
|
||||
* It could be BIT2 ~ BIT4, and BIT9 ~ BIT15 for PG.
|
||||
* It could be BIT4 ~ BIT11 for PH.
|
||||
* @return None
|
||||
* @details Disable I/O digital input path of specified GPIO pin.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16))
|
||||
|
||||
/**
|
||||
* @brief Enable I/O Digital Input Path
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, or PH.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
|
||||
* It could be BIT0 ~ BIT15 for PA, PB, PD, and PE.
|
||||
* It could be BIT0 ~ BIT14 for PC.
|
||||
* It could be BIT0 ~ BIT11, BIT14, and BIT15 for PF.
|
||||
* It could be BIT2 ~ BIT4, and BIT9 ~ BIT15 for PG.
|
||||
* It could be BIT4 ~ BIT11 for PH.
|
||||
* @return None
|
||||
* @details Enable I/O digital input path of specified GPIO pin.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16))
|
||||
|
||||
/**
|
||||
* @brief Disable I/O DOUT mask
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, or PH.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
|
||||
* It could be BIT0 ~ BIT15 for PA, PB, PD, and PE.
|
||||
* It could be BIT0 ~ BIT14 for PC.
|
||||
* It could be BIT0 ~ BIT11, BIT14, and BIT15 for PF.
|
||||
* It could be BIT2 ~ BIT4, and BIT9 ~ BIT15 for PG.
|
||||
* It could be BIT4 ~ BIT11 for PH.
|
||||
* @return None
|
||||
* @details Disable I/O DOUT mask of specified GPIO pin.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask))
|
||||
|
||||
/**
|
||||
* @brief Enable I/O DOUT mask
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, or PH.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
|
||||
* It could be BIT0 ~ BIT15 for PA, PB, PD, and PE.
|
||||
* It could be BIT0 ~ BIT14 for PC.
|
||||
* It could be BIT0 ~ BIT11, BIT14, and BIT15 for PF.
|
||||
* It could be BIT2 ~ BIT4, and BIT9 ~ BIT15 for PG.
|
||||
* It could be BIT4 ~ BIT11 for PH.
|
||||
* @return None
|
||||
* @details Enable I/O DOUT mask of specified GPIO pin.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask))
|
||||
|
||||
/**
|
||||
* @brief Get GPIO Pin Interrupt Flag
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, or PH.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
|
||||
* It could be BIT0 ~ BIT15 for PA, PB, PD, and PE.
|
||||
* It could be BIT0 ~ BIT14 for PC.
|
||||
* It could be BIT0 ~ BIT11, BIT14, and BIT15 for PF.
|
||||
* It could be BIT2 ~ BIT4, and BIT9 ~ BIT15 for PG.
|
||||
* It could be BIT4 ~ BIT11 for PH.
|
||||
* @retval 0 No interrupt at specified GPIO pin
|
||||
* @retval 1 The specified GPIO pin generate an interrupt
|
||||
* @details Get the interrupt status of specified GPIO pin.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask))
|
||||
|
||||
/**
|
||||
* @brief Set De-bounce Sampling Cycle Time
|
||||
* @param[in] u32ClkSrc The de-bounce counter clock source. It could be
|
||||
* - \ref GPIO_DBCTL_DBCLKSRC_HCLK
|
||||
* - \ref GPIO_DBCTL_DBCLKSRC_LIRC
|
||||
* @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_1
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_2
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_4
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_8
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_16
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_32
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_64
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_128
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_256
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_512
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_1024
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_2048
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_4096
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_8192
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_16384
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_32768
|
||||
* @return None
|
||||
* @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
|
||||
* Example: GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n
|
||||
* It's meaning the de-bounce counter clock source is LIRC (38.4 KHz) and sampling cycle selection is 4. \n
|
||||
* Then the target de-bounce sampling cycle time is (4)*(1/38400) s = 4*26.042 us = 104.168 us,
|
||||
* and system will sampling interrupt input once per 104.168 us.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel)))
|
||||
|
||||
/**
|
||||
* @brief Set GPIO Interrupt Clock on bit
|
||||
* @param[in] port Not used in M031.
|
||||
* @return None
|
||||
* @details Set the I/O pins edge detection circuit always active after reset for specified port.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_SET_DEBOUNCE_ICLKON(port) (GPIO->DBCTL |= GPIO_DBCTL_ICLKON_Msk)
|
||||
|
||||
/**
|
||||
* @brief Clear GPIO Interrupt Clock on bit
|
||||
* @param[in] port Not used in M031.
|
||||
* @return None
|
||||
* @details Set edge detection circuit active only if I/O pin edge interrupt enabled for specified port
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_CLR_DEBOUNCE_ICLKON(port) (GPIO->DBCTL &= ~(GPIO_DBCTL_ICLKON_Msk))
|
||||
|
||||
/**
|
||||
* @brief Get GPIO Port IN Data
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, or PH.
|
||||
* @return The specified port data
|
||||
* @details Get the PIN register of specified GPIO port.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_GET_IN_DATA(port) ((port)->PIN)
|
||||
|
||||
/**
|
||||
* @brief Set GPIO Port OUT Data
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, or PH.
|
||||
* @param[in] u32Data GPIO port data.
|
||||
* @return None
|
||||
* @details Set the Data into specified GPIO port.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data))
|
||||
|
||||
/**
|
||||
* @brief Toggle Specified GPIO pin
|
||||
* @param[in] u32Pin Pxy
|
||||
* @return None
|
||||
* @details Toggle the specified GPIO pint.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
|
||||
|
||||
/**
|
||||
* @brief Enable External GPIO interrupt
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, or PF.
|
||||
* @param[in] u32Pin The pin of specified GPIO port.
|
||||
* It could be 0 ~ 15 for PA, PB, PD, and PE.
|
||||
* It could be 0 ~ 14 for PC.
|
||||
* It could be 0 ~ 11, 14, and 15 for PF.
|
||||
* It could be 2 ~ 4, and 9 ~ 15 for PG.
|
||||
* It could be 4 ~ 11 for PH.
|
||||
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be
|
||||
* - \ref GPIO_INT_RISING
|
||||
* - \ref GPIO_INT_FALLING
|
||||
* - \ref GPIO_INT_BOTH_EDGE
|
||||
* - \ref GPIO_INT_HIGH
|
||||
* - \ref GPIO_INT_LOW
|
||||
* @return None
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_EnableEINT GPIO_EnableInt
|
||||
|
||||
/**
|
||||
* @brief Disable External GPIO interrupt
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, or PF.
|
||||
* @param[in] u32Pin The pin of specified GPIO port.
|
||||
* It could be 0 ~ 15 for PA, PB, PD, and PE.
|
||||
* It could be 0 ~ 14 for PC.
|
||||
* It could be 0 ~ 11, 14, and 15 for PF.
|
||||
* It could be 2 ~ 4, and 9 ~ 15 for PG.
|
||||
* It could be 4 ~ 11 for PH.
|
||||
* @return None
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define GPIO_DisableEINT GPIO_DisableInt
|
||||
|
||||
|
||||
void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
|
||||
void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);
|
||||
void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);
|
||||
|
||||
|
||||
/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group GPIO_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __NU_GPIO_H__ */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,88 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_hdiv.h
|
||||
* @version V1.00
|
||||
* $Revision: 1 $
|
||||
* $Date: 18/07/25 3:42p $
|
||||
* @brief M031 series Hardware Divider(HDIV) driver header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
******************************************************************************/
|
||||
#ifndef __NU_HDIV_H__
|
||||
#define __NU_HDIV_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup HDIV_Driver HDIV Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup HDIV_EXPORTED_FUNCTIONS HDIV Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Division function to calculate (x/y)
|
||||
*
|
||||
* @param[in] x the dividend of the division
|
||||
* @param[in] y the divisor of the division
|
||||
*
|
||||
* @return The result of (x/y)
|
||||
*
|
||||
* @details This is a division function to calculate x/y
|
||||
*
|
||||
*/
|
||||
static __INLINE int32_t HDIV_Div(int32_t x, int16_t y)
|
||||
{
|
||||
uint32_t *p32;
|
||||
|
||||
p32 = (uint32_t *)HDIV_BASE;
|
||||
*p32++ = x;
|
||||
*p32++ = y;
|
||||
return *p32;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief To calculate the remainder of x/y, i.e., the result of x mod y.
|
||||
*
|
||||
* @param[in] x the dividend of the division
|
||||
* @param[in] y the divisor of the division
|
||||
*
|
||||
* @return The remainder of (x/y)
|
||||
*
|
||||
* @details This function is used to calculate the remainder of x/y.
|
||||
*/
|
||||
static __INLINE int16_t HDIV_Mod(int32_t x, int16_t y)
|
||||
{
|
||||
uint32_t *p32;
|
||||
|
||||
p32 = (uint32_t *)HDIV_BASE;
|
||||
*p32++ = x;
|
||||
*p32++ = y;
|
||||
return p32[1];
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group HDIV_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group HDIV_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__NU_HDIV_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||
|
||||
|
||||
|
|
@ -1,540 +0,0 @@
|
|||
/****************************************************************************//**
|
||||
* @file nu_i2c.h
|
||||
* @version V1.00
|
||||
* @brief M031 series I2C driver header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_I2C_H__
|
||||
#define __NU_I2C_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Driver I2C Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* I2C_CTL constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define I2C_CTL_STA_SI 0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits \hideinitializer */
|
||||
#define I2C_CTL_STA_SI_AA 0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits \hideinitializer */
|
||||
#define I2C_CTL_STO_SI 0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits \hideinitializer */
|
||||
#define I2C_CTL_STO_SI_AA 0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits \hideinitializer */
|
||||
#define I2C_CTL_SI 0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit \hideinitializer */
|
||||
#define I2C_CTL_SI_AA 0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits \hideinitializer */
|
||||
#define I2C_CTL_STA 0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit \hideinitializer */
|
||||
#define I2C_CTL_STO 0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit \hideinitializer */
|
||||
#define I2C_CTL_AA 0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* I2C GCMode constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode \hideinitializer */
|
||||
#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* I2C SMBUS constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define I2C_SMBH_ENABLE 1 /*!< Enable SMBus Host Mode enable \hideinitializer */
|
||||
#define I2C_SMBD_ENABLE 0 /*!< Enable SMBus Device Mode enable \hideinitializer */
|
||||
#define I2C_PECTX_ENABLE 1 /*!< Enable SMBus Packet Error Check Transmit function \hideinitializer */
|
||||
#define I2C_PECTX_DISABLE 0 /*!< Disable SMBus Packet Error Check Transmit function \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */
|
||||
|
||||
/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
|
||||
@{
|
||||
*/
|
||||
/**
|
||||
* @brief The macro is used to set I2C bus condition at One Time
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
* @param[in] u8Ctrl A byte writes to I2C control register
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3C) | (u8Ctrl))
|
||||
|
||||
/**
|
||||
* @brief The macro is used to set START condition of I2C Bus
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Set the I2C bus START condition in I2C_CTL register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 | I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk)
|
||||
|
||||
/**
|
||||
* @brief The macro is used to wait I2C bus status get ready
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk))
|
||||
|
||||
/**
|
||||
* @brief The macro is used to Read I2C Bus Data Register
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return A byte of I2C data register
|
||||
*
|
||||
* @details I2C controller read data from bus and save it in I2C_DAT register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_GET_DATA(i2c) ((i2c)->DAT)
|
||||
|
||||
/**
|
||||
* @brief Write a Data to I2C Data Register
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
* @param[in] u8Data A byte that writes to data register
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
|
||||
|
||||
/**
|
||||
* @brief Get I2C Bus status code
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return I2C status code
|
||||
*
|
||||
* @details To get this status code to monitor I2C bus event.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0)
|
||||
|
||||
/**
|
||||
* @brief Get Time-out flag from I2C Bus
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @retval 0 I2C Bus time-out is not happened
|
||||
* @retval 1 I2C Bus time-out is happened
|
||||
*
|
||||
* @details When I2C bus occurs time-out event, the time-out flag will be set.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief To get wake-up flag from I2C Bus
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @retval 0 Chip is not woken-up from power-down mode
|
||||
* @retval 1 Chip is woken-up from power-down mode
|
||||
*
|
||||
* @details I2C bus occurs wake-up event, wake-up flag will be set.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief To clear wake-up flag
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details If wake-up flag is set, use this macro to clear it.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
|
||||
|
||||
/**
|
||||
* @brief To get wake-up address frame ACK done flag from I2C Bus
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @retval 0 The ACK bit cycle of address match frame is not done
|
||||
* @retval 1 The ACK bit cycle of address match frame is done in power-down
|
||||
*
|
||||
* @details I2C bus occurs wake-up event and address frame ACK is done, this flag will be set.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_GET_WAKEUP_DONE(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKAKDONE_Msk) == I2C_WKSTS_WKAKDONE_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief To clear address frame ACK done flag
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details If wake-up done is set, use this macro to clear it.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_CLEAR_WAKEUP_DONE(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKAKDONE_Msk)
|
||||
|
||||
/**
|
||||
* @brief To get read/write status bit in address wakeup frame
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @retval 0 Write command be record on the address match wakeup frame
|
||||
* @retval 1 Read command be record on the address match wakeup frame.
|
||||
*
|
||||
* @details I2C bus occurs wake-up event and address frame is received, this bit will record read/write status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_GET_WAKEUP_WR_STATUS(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WRSTSWK_Msk) == I2C_WKSTS_WRSTSWK_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief To get SMBus Status
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return SMBus status
|
||||
*
|
||||
* @details To get the Bus Management status of I2C_BUSSTS register
|
||||
* \hideinitializer
|
||||
*
|
||||
*/
|
||||
#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS)
|
||||
|
||||
/**
|
||||
* @brief Get SMBus CRC value
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return Packet error check byte value
|
||||
*
|
||||
* @details The CRC check value after a transmission or a reception by count by using CRC8
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC)
|
||||
|
||||
/**
|
||||
* @brief Set SMBus Bytes number of Transmission or reception
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
* @param[in] u32PktSize Transmit / Receive bytes
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize))
|
||||
|
||||
/**
|
||||
* @brief Enable SMBus Alert function
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host
|
||||
* Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger)
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable SMBus Alert pin function
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host
|
||||
* Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger)
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set SMBus SUSCON pin is output mode
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set SMBus SUSCON pin is input mode
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set SMBus SUSCON pin output high state
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set SMBus SUSCON pin output low state
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable SMBus Acknowledge control by manual
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable SMBus Acknowledge control by manual
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Disable acknowledge response control by user.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable SMBus Acknowledge manual interrupt
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable SMBus Acknowledge manual interrupt
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable SMBus PEC clear at REPEAT START
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable the condition of REAEAT START can clear the PEC calculation.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable SMBus PEC clear at Repeat START
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to disable the condition of Repeat START can clear the PEC calculation.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable RX PDMA function.
|
||||
* @param[in] i2c The pointer of the specified I2C module.
|
||||
* @return None.
|
||||
* @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable TX PDMA function.
|
||||
* @param[in] i2c The pointer of the specified I2C module.
|
||||
* @return None.
|
||||
* @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable RX PDMA transfer.
|
||||
* @param[in] i2c The pointer of the specified I2C module.
|
||||
* @return None.
|
||||
* @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable TX PDMA transfer.
|
||||
* @param[in] i2c The pointer of the specified I2C module.
|
||||
* @return None.
|
||||
* @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable PDMA stretch function.
|
||||
* @param[in] i2c The pointer of the specified I2C module.
|
||||
* @return None.
|
||||
* @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable PDMA stretch function.
|
||||
* @param[in] i2c The pointer of the specified I2C module.
|
||||
* @return None.
|
||||
* @details I2C will send STOP after PDMA transfers done automatically.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk)
|
||||
|
||||
/**
|
||||
* @brief Reset PDMA function.
|
||||
* @param[in] i2c The pointer of the specified I2C module.
|
||||
* @return None.
|
||||
* @details I2C PDMA engine will be reset after this function is called.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk)
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* inline functions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
|
||||
__STATIC_INLINE void I2C_STOP(I2C_T *i2c);
|
||||
|
||||
/**
|
||||
* @brief The macro is used to set STOP condition of I2C Bus
|
||||
*
|
||||
* @param[in] i2c Specify I2C port
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Set the I2C bus STOP condition in I2C_CTL register.
|
||||
*/
|
||||
__STATIC_INLINE void I2C_STOP(I2C_T *i2c)
|
||||
{
|
||||
|
||||
(i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk);
|
||||
while(i2c->CTL0 & I2C_CTL0_STO_Msk)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void I2C_ClearTimeoutFlag(I2C_T *i2c);
|
||||
void I2C_Close(I2C_T *i2c);
|
||||
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
|
||||
void I2C_DisableInt(I2C_T *i2c);
|
||||
void I2C_EnableInt(I2C_T *i2c);
|
||||
uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
|
||||
uint32_t I2C_GetIntFlag(I2C_T *i2c);
|
||||
uint32_t I2C_GetStatus(I2C_T *i2c);
|
||||
uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
|
||||
uint8_t I2C_GetData(I2C_T *i2c);
|
||||
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
|
||||
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
|
||||
uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
|
||||
void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
|
||||
void I2C_DisableTimeout(I2C_T *i2c);
|
||||
void I2C_EnableWakeup(I2C_T *i2c);
|
||||
void I2C_DisableWakeup(I2C_T *i2c);
|
||||
void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
|
||||
uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data);
|
||||
uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen);
|
||||
uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data);
|
||||
uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen);
|
||||
uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data);
|
||||
uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen);
|
||||
uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr);
|
||||
uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen);
|
||||
uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
|
||||
uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen);
|
||||
uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
|
||||
uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen);
|
||||
uint32_t I2C_SMBusGetStatus(I2C_T *i2c);
|
||||
void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag);
|
||||
void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);
|
||||
void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);
|
||||
void I2C_SMBusClose(I2C_T *i2c);
|
||||
void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);
|
||||
uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);
|
||||
void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk);
|
||||
void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
|
||||
void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
|
||||
|
||||
/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group I2C_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,358 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_pdma.h
|
||||
* @version V1.00
|
||||
* @brief M031 series PDMA driver header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_PDMA_H__
|
||||
#define __NU_PDMA_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup PDMA_Driver PDMA Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define PDMA_CH_MAX 9UL /*!< Specify Maximum Channels of PDMA \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Operation Mode Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PDMA_OP_STOP 0x00000000UL /*!<DMA Stop Mode \hideinitializer */
|
||||
#define PDMA_OP_BASIC 0x00000001UL /*!<DMA Basic Mode \hideinitializer */
|
||||
#define PDMA_OP_SCATTER 0x00000002UL /*!<DMA Scatter-gather Mode \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Data Width Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PDMA_WIDTH_8 0x00000000UL /*!<DMA Transfer Width 8-bit \hideinitializer */
|
||||
#define PDMA_WIDTH_16 0x00001000UL /*!<DMA Transfer Width 16-bit \hideinitializer */
|
||||
#define PDMA_WIDTH_32 0x00002000UL /*!<DMA Transfer Width 32-bit \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Address Attribute Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment \hideinitializer */
|
||||
#define PDMA_SAR_FIX 0x00000300UL /*!<DMA SAR fix address \hideinitializer */
|
||||
#define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment \hideinitializer */
|
||||
#define PDMA_DAR_FIX 0x00000C00UL /*!<DMA DAR fix address \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Burst Mode Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PDMA_REQ_SINGLE 0x00000004UL /*!<DMA Single Request \hideinitializer */
|
||||
#define PDMA_REQ_BURST 0x00000000UL /*!<DMA Burst Request \hideinitializer */
|
||||
|
||||
#define PDMA_BURST_128 0x00000000UL /*!<DMA Burst 128 Transfers \hideinitializer */
|
||||
#define PDMA_BURST_64 0x00000010UL /*!<DMA Burst 64 Transfers \hideinitializer */
|
||||
#define PDMA_BURST_32 0x00000020UL /*!<DMA Burst 32 Transfers \hideinitializer */
|
||||
#define PDMA_BURST_16 0x00000030UL /*!<DMA Burst 16 Transfers \hideinitializer */
|
||||
#define PDMA_BURST_8 0x00000040UL /*!<DMA Burst 8 Transfers \hideinitializer */
|
||||
#define PDMA_BURST_4 0x00000050UL /*!<DMA Burst 4 Transfers \hideinitializer */
|
||||
#define PDMA_BURST_2 0x00000060UL /*!<DMA Burst 2 Transfers \hideinitializer */
|
||||
#define PDMA_BURST_1 0x00000070UL /*!<DMA Burst 1 Transfers \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Table Interrupt Disable Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PDMA_TBINTDIS_ENABLE (0x0UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Enabled \hideinitializer */
|
||||
#define PDMA_TBINTDIS_DISABLE (0x1UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Disabled \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Peripheral Transfer Mode Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PDMA_MEM 0UL /*!<DMA Connect to Memory \hideinitializer */
|
||||
#define PDMA_UART0_TX 4UL /*!<DMA Connect to UART0_TX \hideinitializer */
|
||||
#define PDMA_UART0_RX 5UL /*!<DMA Connect to UART0_RX \hideinitializer */
|
||||
#define PDMA_UART1_TX 6UL /*!<DMA Connect to UART1_TX \hideinitializer */
|
||||
#define PDMA_UART1_RX 7UL /*!<DMA Connect to UART1_RX \hideinitializer */
|
||||
#define PDMA_UART2_TX 8UL /*!<DMA Connect to UART2_TX \hideinitializer */
|
||||
#define PDMA_UART2_RX 9UL /*!<DMA Connect to UART2_RX \hideinitializer */
|
||||
#define PDMA_USCI0_TX 10UL /*!<DMA Connect to USCI0_TX \hideinitializer */
|
||||
#define PDMA_USCI0_RX 11UL /*!<DMA Connect to USCI0_RX \hideinitializer */
|
||||
#define PDMA_USCI1_TX 12UL /*!<DMA Connect to USCI1_TX \hideinitializer */
|
||||
#define PDMA_USCI1_RX 13UL /*!<DMA Connect to USCI1_RX \hideinitializer */
|
||||
#define PDMA_QSPI0_TX 16UL /*!<DMA Connect to QSPI0_TX \hideinitializer */
|
||||
#define PDMA_QSPI0_RX 17UL /*!<DMA Connect to QSPI0_RX \hideinitializer */
|
||||
#define PDMA_SPI0_TX 18UL /*!<DMA Connect to SPI0_TX \hideinitializer */
|
||||
#define PDMA_SPI0_RX 19UL /*!<DMA Connect to SPI0_RX \hideinitializer */
|
||||
#define PDMA_ADC_RX 20UL /*!<DMA Connect to ADC_RX \hideinitializer */
|
||||
#define PDMA_PWM0_P1_RX 21UL /*!<DMA Connect to PWM0_P1 \hideinitializer */
|
||||
#define PDMA_PWM0_P2_RX 22UL /*!<DMA Connect to PWM0_P2 \hideinitializer */
|
||||
#define PDMA_PWM0_P3_RX 23UL /*!<DMA Connect to PWM0_P3 \hideinitializer */
|
||||
#define PDMA_PWM1_P1_RX 24UL /*!<DMA Connect to PWM1_P1 \hideinitializer */
|
||||
#define PDMA_PWM1_P2_RX 25UL /*!<DMA Connect to PWM1_P2 \hideinitializer */
|
||||
#define PDMA_PWM1_P3_RX 26UL /*!<DMA Connect to PWM1_P3 \hideinitializer */
|
||||
#define PDMA_I2C0_TX 28UL /*!<DMA Connect to I2C0_TX \hideinitializer */
|
||||
#define PDMA_I2C0_RX 29UL /*!<DMA Connect to I2C0_RX \hideinitializer */
|
||||
#define PDMA_I2C1_TX 30UL /*!<DMA Connect to I2C1_TX \hideinitializer */
|
||||
#define PDMA_I2C1_RX 31UL /*!<DMA Connect to I2C1_RX \hideinitializer */
|
||||
#define PDMA_TMR0 32UL /*!<DMA Connect to TMR0 \hideinitializer */
|
||||
#define PDMA_TMR1 33UL /*!<DMA Connect to TMR1 \hideinitializer */
|
||||
#define PDMA_TMR2 34UL /*!<DMA Connect to TMR2 \hideinitializer */
|
||||
#define PDMA_TMR3 35UL /*!<DMA Connect to TMR3 \hideinitializer */
|
||||
#define PDMA_UART3_TX 36UL /*!<DMA Connect to UART3_TX \hideinitializer */
|
||||
#define PDMA_UART3_RX 37UL /*!<DMA Connect to UART3_RX \hideinitializer */
|
||||
#define PDMA_UART4_TX 38UL /*!<DMA Connect to UART4_TX \hideinitializer */
|
||||
#define PDMA_UART4_RX 39UL /*!<DMA Connect to UART4_RX \hideinitializer */
|
||||
#define PDMA_UART5_TX 40UL /*!<DMA Connect to UART5_TX \hideinitializer */
|
||||
#define PDMA_UART5_RX 41UL /*!<DMA Connect to UART5_RX \hideinitializer */
|
||||
#define PDMA_UART6_TX 42UL /*!<DMA Connect to UART6_TX \hideinitializer */
|
||||
#define PDMA_UART6_RX 43UL /*!<DMA Connect to UART6_RX \hideinitializer */
|
||||
#define PDMA_UART7_TX 44UL /*!<DMA Connect to UART7_TX \hideinitializer */
|
||||
#define PDMA_UART7_RX 45UL /*!<DMA Connect to UART7_RX \hideinitializer */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Interrupt Type Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PDMA_INT_TRANS_DONE 0x00000000UL /*!<Transfer Done Interrupt \hideinitializer */
|
||||
#define PDMA_INT_TEMPTY 0x00000001UL /*!<Table Empty Interrupt \hideinitializer */
|
||||
#define PDMA_INT_TIMEOUT 0x00000002UL /*!<Timeout Interrupt \hideinitializer */
|
||||
|
||||
|
||||
/*@}*/ /* end of group PDMA_EXPORTED_CONSTANTS */
|
||||
|
||||
/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get PDMA Interrupt Status
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro gets the interrupt status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_GET_INT_STATUS(pdma) ((uint32_t)((pdma)->INTSTS))
|
||||
|
||||
/**
|
||||
* @brief Get Transfer Done Interrupt Status
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Get the transfer done Interrupt status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_GET_TD_STS(pdma) ((uint32_t)((pdma)->TDSTS))
|
||||
|
||||
/**
|
||||
* @brief Clear Transfer Done Interrupt Status
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Mask The channel mask
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Clear the transfer done Interrupt status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_CLR_TD_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->TDSTS = (u32Mask)))
|
||||
|
||||
/**
|
||||
* @brief Get Target Abort Interrupt Status
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Get the target abort Interrupt status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)((pdma)->ABTSTS))
|
||||
|
||||
/**
|
||||
* @brief Clear Target Abort Interrupt Status
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Mask The channel mask
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Clear the target abort Interrupt status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_CLR_ABORT_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ABTSTS = (u32Mask)))
|
||||
|
||||
/**
|
||||
* @brief Get Alignment Interrupt Status
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Get Alignment Interrupt status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)((pdma)->ALIGN))
|
||||
|
||||
/**
|
||||
* @brief Clear Alignment Interrupt Status
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Mask The channel mask
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Clear the Alignment Interrupt status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_CLR_ALIGN_FLAG(pdma,u32Mask) ((uint32_t)((pdma)->ALIGN = (u32Mask)))
|
||||
|
||||
/**
|
||||
* @brief Clear Timeout Interrupt Status
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Clear the selected channel timeout interrupt status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_CLR_TMOUT_FLAG(pdma, u32Ch) ((uint32_t)((pdma)->INTSTS = (1UL << ((u32Ch) + 8UL))))
|
||||
|
||||
/**
|
||||
* @brief Check Channel Status
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
*
|
||||
* @retval 0 Idle state
|
||||
* @retval 1 Busy state
|
||||
*
|
||||
* @details Check the selected channel is busy or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_IS_CH_BUSY(pdma, u32Ch) ((uint32_t)((pdma)->TRGSTS & (1UL << (u32Ch)))? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Set Source Address
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
* @param[in] u32Addr The selected address
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro set the selected channel source address.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_SET_SRC_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].SA = (u32Addr)))
|
||||
|
||||
/**
|
||||
* @brief Set Destination Address
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
* @param[in] u32Addr The selected address
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro set the selected channel destination address.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_SET_DST_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].DA = (u32Addr)))
|
||||
|
||||
/**
|
||||
* @brief Set Transfer Count
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
* @param[in] u32TransCount Transfer Count
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro set the selected channel transfer count.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_SET_TRANS_CNT(pdma, u32Ch, u32TransCount) ((uint32_t)((pdma)->DSCT[(u32Ch)].CTL=((pdma)->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1UL) << PDMA_DSCT_CTL_TXCNT_Pos)))
|
||||
|
||||
/**
|
||||
* @brief Set Scatter-gather descriptor Address
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
* @param[in] u32Addr The descriptor address
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro set the selected channel scatter-gather descriptor address.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_SET_SCATTER_DESC(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].NEXT = (u32Addr) - ((pdma)->SCATBA)))
|
||||
|
||||
/**
|
||||
* @brief Stop the channel
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro stop the selected channel.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_STOP(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch))))
|
||||
|
||||
/**
|
||||
* @brief Pause the channel
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro pause the selected channel.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PDMA_PAUSE(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch))))
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Define PDMA functions prototype */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask);
|
||||
void PDMA_Close(PDMA_T *pdma);
|
||||
void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
|
||||
void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
|
||||
void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
|
||||
void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize);
|
||||
void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask);
|
||||
void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask);
|
||||
void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
|
||||
void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch);
|
||||
void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask);
|
||||
void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask);
|
||||
|
||||
|
||||
/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group PDMA_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __NU_PDMA_H__ */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,514 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_pwm.h
|
||||
* @version V1.00
|
||||
* $Revision: 9 $
|
||||
* $Date: 18/06/07 3:47p $
|
||||
* @brief M031 series PWM driver header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_PWM_H__
|
||||
#define __NU_PWM_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWM_Driver PWM Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWM_EXPORTED_CONSTANTS PWM Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define PWM_CHANNEL_NUM (6UL) /*!< PWM channel number \hideinitializer */
|
||||
#define PWM_CH_0_MASK (0x1UL) /*!< PWM channel 0 mask \hideinitializer */
|
||||
#define PWM_CH_1_MASK (0x2UL) /*!< PWM channel 1 mask \hideinitializer */
|
||||
#define PWM_CH_2_MASK (0x4UL) /*!< PWM channel 2 mask \hideinitializer */
|
||||
#define PWM_CH_3_MASK (0x8UL) /*!< PWM channel 3 mask \hideinitializer */
|
||||
#define PWM_CH_4_MASK (0x10UL) /*!< PWM channel 4 mask \hideinitializer */
|
||||
#define PWM_CH_5_MASK (0x20UL) /*!< PWM channel 5 mask \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Counter Type Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PWM_UP_COUNTER (0UL) /*!< Up counter type \hideinitializer */
|
||||
#define PWM_DOWN_COUNTER (1UL) /*!< Down counter type \hideinitializer */
|
||||
#define PWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Aligned Type Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PWM_EDGE_ALIGNED (1UL) /*!< PWM working in edge aligned type(down count) \hideinitializer */
|
||||
#define PWM_CENTER_ALIGNED (2UL) /*!< PWM working in center aligned type \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Output Level Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PWM_OUTPUT_NOTHING (0UL) /*!< PWM output nothing \hideinitializer */
|
||||
#define PWM_OUTPUT_LOW (1UL) /*!< PWM output low \hideinitializer */
|
||||
#define PWM_OUTPUT_HIGH (2UL) /*!< PWM output high \hideinitializer */
|
||||
#define PWM_OUTPUT_TOGGLE (3UL) /*!< PWM output toggle \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Synchronous Start Function Control Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PWM_SSCTL_SSRC_PWM0 (0UL<<PWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM0 \hideinitializer */
|
||||
#define PWM_SSCTL_SSRC_PWM1 (1UL<<PWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM1 \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Trigger Source Select Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< PWM trigger ADC while counter of even channel matches zero point \hideinitializer */
|
||||
#define PWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< PWM trigger ADC while counter of even channel matches period point \hideinitializer */
|
||||
#define PWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< PWM trigger ADC while counter of even channel matches zero or period point \hideinitializer */
|
||||
#define PWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT (3UL) /*!< PWM trigger ADC while counter of even channel matches up count to comparator point \hideinitializer */
|
||||
#define PWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT (4UL) /*!< PWM trigger ADC while counter of even channel matches down count to comparator point \hideinitializer */
|
||||
#define PWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT (8UL) /*!< PWM trigger ADC while counter of odd channel matches up count to comparator point \hideinitializer */
|
||||
#define PWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT (9UL) /*!< PWM trigger ADC while counter of odd channel matches down count to comparator point \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Fail brake Control Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PWM_FB_EDGE_ACMP0 (PWM_BRKCTL0_1_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */
|
||||
#define PWM_FB_EDGE_ACMP1 (PWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */
|
||||
#define PWM_FB_EDGE_BKP0 (PWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source \hideinitializer */
|
||||
#define PWM_FB_EDGE_BKP1 (PWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source \hideinitializer */
|
||||
#define PWM_FB_EDGE_ADCRM (PWM_BRKCTL0_1_ADCEBEN_Msk) /*!< ADC Result Monitor (ADCRM) as edge-detect fault brake source \hideinitializer */
|
||||
#define PWM_FB_EDGE_SYS_CSS (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */
|
||||
#define PWM_FB_EDGE_SYS_BOD (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */
|
||||
#define PWM_FB_EDGE_SYS_COR (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */
|
||||
|
||||
#define PWM_FB_LEVEL_ACMP0 (PWM_BRKCTL0_1_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */
|
||||
#define PWM_FB_LEVEL_ACMP1 (PWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */
|
||||
#define PWM_FB_LEVEL_BKP0 (PWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source \hideinitializer */
|
||||
#define PWM_FB_LEVEL_BKP1 (PWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source \hideinitializer */
|
||||
#define PWM_FB_LEVEL_ADCRM (PWM_BRKCTL0_1_ADCLBEN_Msk) /*!< ADC Result Monitor (ADCRM) as level-detect fault brake source \hideinitializer */
|
||||
#define PWM_FB_LEVEL_SYS_CSS (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */
|
||||
#define PWM_FB_LEVEL_SYS_BOD (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */
|
||||
#define PWM_FB_LEVEL_SYS_COR (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */
|
||||
|
||||
#define PWM_FB_EDGE (0UL) /*!< Edge-detect fault brake \hideinitializer */
|
||||
#define PWM_FB_LEVEL (8UL) /*!< Level-detect fault brake \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Capture Control Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< PWM capture interrupt if channel has rising transition \hideinitializer */
|
||||
#define PWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< PWM capture interrupt if channel has falling transition \hideinitializer */
|
||||
|
||||
#define PWM_CAPTURE_PDMA_RISING_LATCH (0x2UL) /*!< PWM capture rising latched data transfer by PDMA \hideinitializer */
|
||||
#define PWM_CAPTURE_PDMA_FALLING_LATCH (0x4UL) /*!< PWM capture falling latched data transfer by PDMA \hideinitializer */
|
||||
#define PWM_CAPTURE_PDMA_RISING_FALLING_LATCH (0x6UL) /*!< PWM capture rising and falling latched data transfer by PDMA \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Duty Interrupt Type Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (PWM_INTEN0_CMPDIEN0_Msk) /*!< PWM duty interrupt triggered if down count match comparator \hideinitializer */
|
||||
#define PWM_DUTY_INT_UP_COUNT_MATCH_CMP (PWM_INTEN0_CMPUIEN0_Msk) /*!< PWM duty interrupt triggered if up count match comparator \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Load Mode Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PWM_LOAD_MODE_IMMEDIATE (PWM_CTL0_IMMLDEN0_Msk) /*!< PWM immediately load mode \hideinitializer */
|
||||
#define PWM_LOAD_MODE_CENTER (PWM_CTL0_CTRLD0_Msk) /*!< PWM center load mode \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Synchronize Control Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PWM_SYNC_OUT_FROM_SYNCIN_SWSYNC (0UL) /*!< Synchronize source from SYNC_IN or SWSYNC \hideinitializer */
|
||||
#define PWM_SYNC_OUT_FROM_COUNT_TO_ZERO (1UL) /*!< Synchronize source from counter equal to 0 \hideinitializer */
|
||||
#define PWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR (2UL) /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */
|
||||
#define PWM_SYNC_OUT_DISABLE (3UL) /*!< SYNC_OUT will not be generated \hideinitializer */
|
||||
#define PWM_PHS_DIR_DECREMENT (0UL) /*!< PWM counter count decrement \hideinitializer */
|
||||
#define PWM_PHS_DIR_INCREMENT (1UL) /*!< PWM counter count increment \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Noise Filter Clock Divide Select Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PWM_NF_CLK_DIV_1 (0UL) /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */
|
||||
#define PWM_NF_CLK_DIV_2 (1UL) /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */
|
||||
#define PWM_NF_CLK_DIV_4 (2UL) /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */
|
||||
#define PWM_NF_CLK_DIV_8 (3UL) /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */
|
||||
#define PWM_NF_CLK_DIV_16 (4UL) /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */
|
||||
#define PWM_NF_CLK_DIV_32 (5UL) /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */
|
||||
#define PWM_NF_CLK_DIV_64 (6UL) /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */
|
||||
#define PWM_NF_CLK_DIV_128 (7UL) /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Clock Source Select Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PWM_CLKSRC_PWM_CLK (0UL) /*!< PWM Clock source selects to PWM0_CLK or PWM1_CLK \hideinitializer */
|
||||
#define PWM_CLKSRC_TIMER0 (1UL) /*!< PWM Clock source selects to TIMER0 overflow \hideinitializer */
|
||||
#define PWM_CLKSRC_TIMER1 (2UL) /*!< PWM Clock source selects to TIMER1 overflow \hideinitializer */
|
||||
#define PWM_CLKSRC_TIMER2 (3UL) /*!< PWM Clock source selects to TIMER2 overflow \hideinitializer */
|
||||
#define PWM_CLKSRC_TIMER3 (4UL) /*!< PWM Clock source selects to TIMER3 overflow \hideinitializer */
|
||||
|
||||
|
||||
/*@}*/ /* end of group PWM_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This macro enable complementary mode
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @return None
|
||||
* @details This macro is used to enable complementary mode of PWM module.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 | (0x7ul<<PWM_CTL1_OUTMODE0_Pos))
|
||||
|
||||
/**
|
||||
* @brief This macro disable complementary mode, and enable independent mode.
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @return None
|
||||
* @details This macro is used to disable complementary mode of PWM module.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 & ~(0x7ul<<PWM_CTL1_OUTMODE0_Pos))
|
||||
|
||||
/**
|
||||
* @brief Enable timer synchronous start counting function of specified channel(s)
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||
* @param[in] u32SyncSrc Synchronous start source selection, valid values are:
|
||||
* - \ref PWM_SSCTL_SSRC_PWM0
|
||||
* - \ref PWM_SSCTL_SSRC_PWM1
|
||||
* @return None
|
||||
* @details This macro is used to enable timer synchronous start counting function of specified channel(s).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_ENABLE_TIMER_SYNC(pwm, u32ChannelMask, u32SyncSrc) ((pwm)->SSCTL = ((pwm)->SSCTL & ~PWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask))
|
||||
|
||||
/**
|
||||
* @brief Disable timer synchronous start counting function of specified channel(s)
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||
* @return None
|
||||
* @details This macro is used to disable timer synchronous start counting function of specified channel(s).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_DISABLE_TIMER_SYNC(pwm, u32ChannelMask) \
|
||||
do{ \
|
||||
int i;\
|
||||
for(i = 0; i < 6; i++) { \
|
||||
if((u32ChannelMask) & (1 << i)) \
|
||||
(pwm)->SSCTL &= ~(1UL << i); \
|
||||
} \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief This macro enable PWM counter synchronous start counting function.
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @return None
|
||||
* @details This macro is used to make selected PWM0 and PWM1 channel(s) start counting at the same time.
|
||||
* To configure synchronous start counting channel(s) by PWM_ENABLE_TIMER_SYNC() and PWM_DISABLE_TIMER_SYNC().
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_TRIGGER_SYNC_START(pwm) ((pwm)->SSTRG = PWM_SSTRG_CNTSEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro enable output inverter of specified channel(s)
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||
* @return None
|
||||
* @details This macro is used to enable output inverter of specified channel(s).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->POLCTL = (u32ChannelMask))
|
||||
|
||||
/**
|
||||
* @brief This macro get captured rising data
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
* @details This macro is used to get captured rising data of specified channel.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->RCAPDAT0) + ((u32ChannelNum) << 1)))
|
||||
|
||||
/**
|
||||
* @brief This macro get captured falling data
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
* @details This macro is used to get captured falling data of specified channel.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->FCAPDAT0) + ((u32ChannelNum) << 1)))
|
||||
|
||||
/**
|
||||
* @brief This macro mask output logic to high or low
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||
* @param[in] u32LevelMask Output logic to high or low
|
||||
* @return None
|
||||
* @details This macro is used to mask output logic to high or low of specified channel(s).
|
||||
* @note If u32ChannelMask parameter is 0, then mask function will be disabled.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) \
|
||||
{ \
|
||||
(pwm)->MSKEN = (u32ChannelMask); \
|
||||
(pwm)->MSK = (u32LevelMask); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This macro set the prescaler of the selected channel
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
|
||||
* @return None
|
||||
* @details This macro is used to set the prescaler of specified channel.
|
||||
* @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
|
||||
* The clock of PWM counter is divided by (u32Prescaler + 1).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) ((pwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler))
|
||||
|
||||
/**
|
||||
* @brief This macro get the prescaler of the selected channel
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
|
||||
* @details This macro is used to get the prescaler of specified channel.
|
||||
* @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
|
||||
* The clock of PWM counter is divided by (u32Prescaler + 1).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_GET_PRESCALER(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->CLKPSC[0]) + ((u32ChannelNum) >> 1)))
|
||||
|
||||
/**
|
||||
* @brief This macro set the comparator of the selected channel
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF
|
||||
* @return None
|
||||
* @details This macro is used to set the comparator of specified channel.
|
||||
* @note This new setting will take effect on next PWM period.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)]= (u32CMR))
|
||||
|
||||
/**
|
||||
* @brief This macro get the comparator of the selected channel
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return Return the comparator of specified channel. Valid values are between 0~0xFFFF
|
||||
* @details This macro is used to get the comparator of specified channel.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_GET_CMR(pwm, u32ChannelNum) ((pwm)->CMPDAT[(u32ChannelNum)])
|
||||
|
||||
/**
|
||||
* @brief This macro set the period of the selected channel
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
|
||||
* @return None
|
||||
* @details This macro is used to set the period of specified channel.
|
||||
* @note This new setting will take effect on next PWM period.
|
||||
* @note PWM counter will stop if period length set to 0.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[(u32ChannelNum>>1)<<1] = (u32CNR))
|
||||
|
||||
/**
|
||||
* @brief This macro get the period of the selected channel
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return Return the period of specified channel. Valid values are between 0~0xFFFF
|
||||
* @details This macro is used to get the period of specified channel.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_GET_CNR(pwm, u32ChannelNum) ((pwm)->PERIOD[(u32ChannelNum>>1)<<1])
|
||||
|
||||
/**
|
||||
* @brief This macro set the PWM aligned type
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||
* @param[in] u32AlignedType PWM aligned type, valid values are:
|
||||
* - \ref PWM_EDGE_ALIGNED
|
||||
* - \ref PWM_CENTER_ALIGNED
|
||||
* @return None
|
||||
* @details This macro is used to set the PWM aligned type of specified channel(s).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
|
||||
do{ \
|
||||
int i; \
|
||||
for(i = 0; i < 6; i++) { \
|
||||
if((u32ChannelMask) & (1 << i)) \
|
||||
(pwm)->CTL1 = (((pwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \
|
||||
} \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Clear counter of specified channel(s)
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||
* @return None
|
||||
* @details This macro is used to clear counter of specified channel(s).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_CLR_COUNTER(pwm, u32ChannelMask) \
|
||||
do{ \
|
||||
uint32_t i; \
|
||||
for(i = 0UL; i < 6UL; i++) { \
|
||||
if((u32ChannelMask) & (1UL << i)) \
|
||||
((pwm)->CNTCLR |= (1UL << ((i >> 1UL) << 1UL))); \
|
||||
} \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||
* @param[in] u32ZeroLevel output level at zero point, valid values are:
|
||||
* - \ref PWM_OUTPUT_NOTHING
|
||||
* - \ref PWM_OUTPUT_LOW
|
||||
* - \ref PWM_OUTPUT_HIGH
|
||||
* - \ref PWM_OUTPUT_TOGGLE
|
||||
* @param[in] u32CmpUpLevel output level at compare up point, valid values are:
|
||||
* - \ref PWM_OUTPUT_NOTHING
|
||||
* - \ref PWM_OUTPUT_LOW
|
||||
* - \ref PWM_OUTPUT_HIGH
|
||||
* - \ref PWM_OUTPUT_TOGGLE
|
||||
* @param[in] u32PeriodLevel output level at period(center) point, valid values are:
|
||||
* - \ref PWM_OUTPUT_NOTHING
|
||||
* - \ref PWM_OUTPUT_LOW
|
||||
* - \ref PWM_OUTPUT_HIGH
|
||||
* - \ref PWM_OUTPUT_TOGGLE
|
||||
* @param[in] u32CmpDownLevel output level at compare down point, valid values are:
|
||||
* - \ref PWM_OUTPUT_NOTHING
|
||||
* - \ref PWM_OUTPUT_LOW
|
||||
* - \ref PWM_OUTPUT_HIGH
|
||||
* - \ref PWM_OUTPUT_TOGGLE
|
||||
* @return None
|
||||
* @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_OUTPUT_LEVEL(pwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
|
||||
do{ \
|
||||
int i; \
|
||||
for(i = 0; i < 6; i++) { \
|
||||
if((u32ChannelMask) & (1 << i)) { \
|
||||
(pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \
|
||||
(pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (PWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (PWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \
|
||||
(pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \
|
||||
(pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (PWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (PWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \
|
||||
} \
|
||||
} \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Trigger brake event from specified channel(s)
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
|
||||
* @param[in] u32BrakeType Type of brake trigger. PWM_FB_EDGE of this macro is only supported in M45xD/M45xC.
|
||||
* - \ref PWM_FB_EDGE
|
||||
* - \ref PWM_FB_LEVEL
|
||||
* @return None
|
||||
* @details This macro is used to trigger brake event from specified channel(s).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_TRIGGER_BRAKE(pwm, u32ChannelMask, u32BrakeType) ((pwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType)))
|
||||
|
||||
/**
|
||||
* @brief Set Dead zone clock source
|
||||
* @param[in] pwm The pointer of the specified PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
|
||||
* @return None
|
||||
* @details This macro is used to set Dead zone clock source. Every two channels share the same setting.
|
||||
* @note The write-protection function should be disabled before using this function.
|
||||
* @note This function is only supported in M45xD/M45xC.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_DEADZONE_CLK_SRC(pwm, u32ChannelNum, u32AfterPrescaler) \
|
||||
((pwm)->DTCTL[(u32ChannelNum) >> 1] = (((pwm)->DTCTL[(u32ChannelNum) >> 1] & ~PWM_DTCTL0_1_DTCKSEL_Msk) | \
|
||||
((u32AfterPrescaler) << PWM_DTCTL0_1_DTCKSEL_Pos)))
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Define PWM functions prototype */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
|
||||
uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
|
||||
void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
||||
void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
||||
uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource);
|
||||
void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
|
||||
void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
|
||||
void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||
void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||
void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||
uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
|
||||
void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
|
||||
void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
|
||||
void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
|
||||
uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
|
||||
void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
|
||||
void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
|
||||
void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
|
||||
void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
|
||||
void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
|
||||
void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum);
|
||||
void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
|
||||
void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
|
||||
void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule);
|
||||
uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
|
||||
/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group PWM_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__NU_PWM_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,412 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_qspi.h
|
||||
* @version V1.00
|
||||
* @brief M031 series QSPI driver header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_QSPI_H__
|
||||
#define __NU_QSPI_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Driver QSPI Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
#define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */
|
||||
#define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */
|
||||
#define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */
|
||||
#define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */
|
||||
|
||||
#define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
|
||||
#define QSPI_MASTER (0x0UL) /*!< Set as master \hideinitializer */
|
||||
|
||||
#define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */
|
||||
#define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */
|
||||
#define QSPI_SS_ACTIVE_LOW (0x0UL) /*!< SS active low \hideinitializer */
|
||||
|
||||
/* QSPI Interrupt Mask */
|
||||
#define QSPI_UNIT_INT_MASK (0x001UL) /*!< Unit transfer interrupt mask \hideinitializer */
|
||||
#define QSPI_SSACT_INT_MASK (0x002UL) /*!< Slave selection signal active interrupt mask \hideinitializer */
|
||||
#define QSPI_SSINACT_INT_MASK (0x004UL) /*!< Slave selection signal inactive interrupt mask \hideinitializer */
|
||||
#define QSPI_SLVUR_INT_MASK (0x008UL) /*!< Slave under run interrupt mask \hideinitializer */
|
||||
#define QSPI_SLVBE_INT_MASK (0x010UL) /*!< Slave bit count error interrupt mask \hideinitializer */
|
||||
#define QSPI_SLVTO_INT_MASK (0x020UL) /*!< Slave Mode Time-out interrupt mask \hideinitializer */
|
||||
#define QSPI_TXUF_INT_MASK (0x040UL) /*!< Slave TX underflow interrupt mask \hideinitializer */
|
||||
#define QSPI_FIFO_TXTH_INT_MASK (0x080UL) /*!< FIFO TX threshold interrupt mask \hideinitializer */
|
||||
#define QSPI_FIFO_RXTH_INT_MASK (0x100UL) /*!< FIFO RX threshold interrupt mask \hideinitializer */
|
||||
#define QSPI_FIFO_RXOV_INT_MASK (0x200UL) /*!< FIFO RX overrun interrupt mask \hideinitializer */
|
||||
#define QSPI_FIFO_RXTO_INT_MASK (0x400UL) /*!< FIFO RX time-out interrupt mask \hideinitializer */
|
||||
|
||||
/* QSPI Status Mask */
|
||||
#define QSPI_BUSY_MASK (0x01UL) /*!< Busy status mask \hideinitializer */
|
||||
#define QSPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask \hideinitializer */
|
||||
#define QSPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask \hideinitializer */
|
||||
#define QSPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask \hideinitializer */
|
||||
#define QSPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask \hideinitializer */
|
||||
#define QSPI_TXRX_RESET_MASK (0x20UL) /*!< TX or RX reset status mask \hideinitializer */
|
||||
#define QSPI_SPIEN_STS_MASK (0x40UL) /*!< SPIEN status mask \hideinitializer */
|
||||
#define QSPI_SSLINE_STS_MASK (0x80UL) /*!< QSPIx_SS line status mask \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clear the unit transfer interrupt flag.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ((qspi)->STATUS = QSPI_STATUS_UNITIF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Trigger RX PDMA function.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_TRIGGER_RX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Trigger TX PDMA function.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_TRIGGER_TX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Trigger TX and RX PDMA function.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Set TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to enable TX and RX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_TRIGGER_TX_RX_PDMA(qspi) ((qspi)->PDMACTL |= (QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk))
|
||||
|
||||
/**
|
||||
* @brief Disable RX PDMA transfer.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable TX PDMA transfer.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable TX and RX PDMA transfer.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Clear TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to disable TX and RX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_DISABLE_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~(QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) )
|
||||
|
||||
/**
|
||||
* @brief Get the count of available data in RX FIFO.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return The count of available data in RX FIFO.
|
||||
* @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_GET_RX_FIFO_COUNT(qspi) (((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos)
|
||||
|
||||
/**
|
||||
* @brief Get the RX FIFO empty flag.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @retval 0 RX FIFO is not empty.
|
||||
* @retval 1 RX FIFO is empty.
|
||||
* @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk)>>QSPI_STATUS_RXEMPTY_Pos)
|
||||
|
||||
/**
|
||||
* @brief Get the TX FIFO empty flag.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @retval 0 TX FIFO is not empty.
|
||||
* @retval 1 TX FIFO is empty.
|
||||
* @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk)>>QSPI_STATUS_TXEMPTY_Pos)
|
||||
|
||||
/**
|
||||
* @brief Get the TX FIFO full flag.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @retval 0 TX FIFO is not full.
|
||||
* @retval 1 TX FIFO is full.
|
||||
* @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk)>>QSPI_STATUS_TXFULL_Pos)
|
||||
|
||||
/**
|
||||
* @brief Get the datum read from RX register.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return Data in RX register.
|
||||
* @details Read QSPI_RX register to get the received datum.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_READ_RX(qspi) ((qspi)->RX)
|
||||
|
||||
/**
|
||||
* @brief Write datum to TX register.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @param[in] u32TxData The datum which user attempt to transfer through QSPI bus.
|
||||
* @return None.
|
||||
* @details Write u32TxData to QSPI_TX register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_WRITE_TX(qspi, u32TxData) ((qspi)->TX = (u32TxData))
|
||||
|
||||
/**
|
||||
* @brief Set QSPIx_SS pin to high state.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Disable automatic slave selection function and set QSPIx_SS pin to high state.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_SET_SS_HIGH(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))
|
||||
|
||||
/**
|
||||
* @brief Set QSPIx_SS pin to low state.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Disable automatic slave selection function and set QSPIx_SS pin to low state.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_SET_SS_LOW(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable Byte Reorder function.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_ENABLE_BYTE_REORDER(qspi) ((qspi)->CTL |= QSPI_CTL_REORDER_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable Byte Reorder function.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_DISABLE_BYTE_REORDER(qspi) ((qspi)->CTL &= ~QSPI_CTL_REORDER_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set the length of suspend interval.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
|
||||
* @return None.
|
||||
* @details Set the length of suspend interval according to u32SuspCycle.
|
||||
* The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle).
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos))
|
||||
|
||||
/**
|
||||
* @brief Set the QSPI transfer sequence with LSB first.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_SET_LSB_FIRST(qspi) ((qspi)->CTL |= QSPI_CTL_LSB_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set the QSPI transfer sequence with MSB first.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_SET_MSB_FIRST(qspi) ((qspi)->CTL &= ~QSPI_CTL_LSB_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set the data width of a QSPI transaction.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @param[in] u32Width The bit width of one transaction.
|
||||
* @return None.
|
||||
* @details The data width can be 8 ~ 32 bits.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_SET_DATA_WIDTH(qspi, u32Width) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << QSPI_CTL_DWIDTH_Pos))
|
||||
|
||||
/**
|
||||
* @brief Get the QSPI busy state.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @retval 0 QSPI controller is not busy.
|
||||
* @retval 1 QSPI controller is busy.
|
||||
* @details This macro will return the busy state of QSPI controller.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk)>>QSPI_STATUS_BUSY_Pos )
|
||||
|
||||
/**
|
||||
* @brief Enable QSPI controller.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Set SPIEN (QSPI_CTL[0]) to enable QSPI controller.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_ENABLE(qspi) ((qspi)->CTL |= QSPI_CTL_SPIEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable QSPI controller.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Clear SPIEN (QSPI_CTL[0]) to disable QSPI controller.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_DISABLE(qspi) ((qspi)->CTL &= ~QSPI_CTL_SPIEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable 2-bit Transfer mode.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Clear TWOBIT bit of QSPI_CTL register to disable 2-bit Transfer mode.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_DISABLE_2BIT_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TWOBIT_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable 2-bit Transfer mode.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Set TWOBIT bit of QSPI_CTL register to enable 2-bit Transfer mode.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_ENABLE_2BIT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TWOBIT_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable Slave 3-wire mode.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Clear SLV3WIRE bit of QSPI_SSCTL register to disable Slave 3-wire mode.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_DISABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL &= ~QSPI_SSCTL_SLV3WIRE_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable Slave 3-wire mode.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None.
|
||||
* @details Set SLV3WIRE bit of QSPI_SSCTL register to enable Slave 3-wire mode.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_ENABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL |= QSPI_SSCTL_SLV3WIRE_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable QSPI Dual IO function.
|
||||
* @param[in] qspi is the base address of QSPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable Dual IO function and set QSPI Dual IO direction to input.
|
||||
* @param[in] qspi is the base address of QSPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_DUALIOEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable Dual IO function and set QSPI Dual IO direction to output.
|
||||
* @param[in] qspi is the base address of QSPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable QSPI Quad IO function.
|
||||
* @param[in] qspi is the base address of QSPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Set QSPI Quad IO direction to input.
|
||||
* @param[in] qspi is the base address of QSPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_QUADIOEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Set QSPI Quad IO direction to output.
|
||||
* @param[in] qspi is the base address of QSPI module.
|
||||
* @return none
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk )
|
||||
|
||||
|
||||
|
||||
|
||||
/* Function prototype declaration */
|
||||
uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
|
||||
void QSPI_Close(QSPI_T *qspi);
|
||||
void QSPI_ClearRxFIFO(QSPI_T *qspi);
|
||||
void QSPI_ClearTxFIFO(QSPI_T *qspi);
|
||||
void QSPI_DisableAutoSS(QSPI_T *qspi);
|
||||
void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
|
||||
uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock);
|
||||
void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
|
||||
uint32_t QSPI_GetBusClock(QSPI_T *qspi);
|
||||
void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask);
|
||||
void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask);
|
||||
uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask);
|
||||
void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask);
|
||||
uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask);
|
||||
|
||||
|
||||
/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group QSPI_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __NU_QSPI_H__ */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,300 +0,0 @@
|
|||
/******************************************************************************
|
||||
* @file nu_rtc.h
|
||||
* @version V1.00
|
||||
* $Revision: 4 $
|
||||
* $Date: 18/06/07 2:32p $
|
||||
* @brief M031 series Real Time Clock(RTC) driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __NU_RTC_H__
|
||||
#define __NU_RTC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Driver RTC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants
|
||||
@{
|
||||
*/
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* RTC Initial Keyword Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */
|
||||
#define RTC_WRITE_KEY 0x0000A965UL /*!< RTC Register Access Enable Key to enable RTC read/write accessible and kept 1024 RTC clock \hideinitializer */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* RTC Frequency Compensation Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define RTC_INTEGER_32752 (0x0ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32752HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32753 (0x1ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32753HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32754 (0x2ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32754HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32755 (0x3ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32755HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32756 (0x4ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32756HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32757 (0x5ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32757HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32758 (0x6ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32758HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32759 (0x7ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32759HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32760 (0x8ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32760HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32761 (0x9ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32761HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32762 (0xaul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32762HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32763 (0xbul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32763HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32764 (0xcul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32764HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32765 (0xdul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32765HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32766 (0xeul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32766HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32767 (0xful << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32767HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32768 (0x10ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32768HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32769 (0x11ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32769HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32770 (0x12ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32770HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32771 (0x13ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32771HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32772 (0x14ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32772HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32773 (0x15ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32773HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32774 (0x16ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32774HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32775 (0x17ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32775HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32776 (0x18ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32776HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32777 (0x19ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32777HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32778 (0x1aul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32778HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32779 (0x1bul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32779HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32780 (0x1cul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32780HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32781 (0x1dul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32781HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32782 (0x1eul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32782HZ \hideinitializer */
|
||||
#define RTC_INTEGER_32783 (0x1ful << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32783HZ \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* RTC Time Attribute Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */
|
||||
#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */
|
||||
#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */
|
||||
#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* RTC Tick Period Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */
|
||||
#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */
|
||||
#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */
|
||||
#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */
|
||||
#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */
|
||||
#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */
|
||||
#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */
|
||||
#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* RTC Day of Week Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */
|
||||
#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */
|
||||
#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */
|
||||
#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */
|
||||
#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */
|
||||
#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */
|
||||
#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* RTC Miscellaneous Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */
|
||||
#define RTC_FCR_REFERENCE 32761UL /*!< RTC Reference for frequency compensation \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* RTC Clock Source Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define RTC_CLKSRC_LXT 0x0UL /*!< Clock Source from LXT \hideinitializer */
|
||||
#define RTC_CLKSRC_LIRC 0x1UL /*!< Clock Source from LIRC \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs
|
||||
@{
|
||||
*/
|
||||
/**
|
||||
* @details RTC define Time Data Struct
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t u32Year; /*!< Year value */
|
||||
uint32_t u32Month; /*!< Month value */
|
||||
uint32_t u32Day; /*!< Day value */
|
||||
uint32_t u32DayOfWeek; /*!< Day of week value */
|
||||
uint32_t u32Hour; /*!< Hour value */
|
||||
uint32_t u32Minute; /*!< Minute value */
|
||||
uint32_t u32Second; /*!< Second value */
|
||||
uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */
|
||||
uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */
|
||||
} S_RTC_TIME_DATA_T;
|
||||
|
||||
/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */
|
||||
|
||||
|
||||
/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Indicate is Leap Year or not
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 0 This year is not a leap year
|
||||
* @retval 1 This year is a leap year
|
||||
*
|
||||
* @details According to current date, return this year is leap year or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define RTC_IS_LEAP_YEAR() (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0)
|
||||
|
||||
/**
|
||||
* @brief Clear RTC Alarm Interrupt Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to clear RTC alarm interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Clear RTC Tick Interrupt Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to clear RTC tick interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define RTC_CLEAR_TICK_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get RTC Alarm Interrupt Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 0 RTC alarm interrupt did not occur
|
||||
* @retval 1 RTC alarm interrupt occurred
|
||||
*
|
||||
* @details This macro indicates RTC alarm interrupt occurred or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define RTC_GET_ALARM_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0)
|
||||
|
||||
/**
|
||||
* @brief Get RTC Time Tick Interrupt Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 0 RTC time tick interrupt did not occur
|
||||
* @retval 1 RTC time tick interrupt occurred
|
||||
*
|
||||
* @details This macro indicates RTC time tick interrupt occurred or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define RTC_GET_TICK_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0)
|
||||
|
||||
/**
|
||||
* @brief Enable RTC Tick Wake-up Function
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to enable RTC tick interrupt wake-up function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define RTC_ENABLE_TICK_WAKEUP() ((RTC->INTEN |= RTC_INTEN_TICKIEN_Msk))
|
||||
|
||||
/**
|
||||
* @brief Disable RTC Tick Wake-up Function
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to disable RTC tick interrupt wake-up function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define RTC_DISABLE_TICK_WAKEUP() ((RTC->INTEN &= ~RTC_INTEN_TICKIEN_Msk));
|
||||
|
||||
/**
|
||||
* @brief Enable RTC Alarm Wake-up Function
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to enable RTC Alarm interrupt wake-up function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define RTC_ENABLE_ALARM_WAKEUP() ((RTC->INTEN |= RTC_INTEN_ALMIEN_Msk))
|
||||
|
||||
/**
|
||||
* @brief Disable RTC Alarm Wake-up Function
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to disable RTC Alarm interrupt wake-up function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define RTC_DISABLE_ALARM_WAKEUP() ((RTC->INTEN &= ~RTC_INTEN_ALMIEN_Msk));
|
||||
|
||||
/**
|
||||
* @brief Select RTC Clock Source
|
||||
*
|
||||
* @param[in] u32ClkSrc Specify the clock source. It consists of:
|
||||
* - \ref RTC_CLKSRC_LXT : Clock source from LXT
|
||||
* - \ref RTC_CLKSRC_LIRC : Clock source from LIRC
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to select RTC clock source.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define RTC_CLKSRCSEL(u32ClkSrc) ((RTC->LXTCTL &= ~RTC_LXTCTL_C32KS_Msk) | u32ClkSrc);
|
||||
|
||||
void RTC_Open(S_RTC_TIME_DATA_T *psPt);
|
||||
void RTC_Close(void);
|
||||
void RTC_32KCalibration(int32_t i32FrequencyX10000);
|
||||
void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *psPt);
|
||||
void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *psPt);
|
||||
void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *psPt);
|
||||
void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *psPt);
|
||||
void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
|
||||
void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
|
||||
void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
|
||||
void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
|
||||
void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk);
|
||||
void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk);
|
||||
uint32_t RTC_GetDayOfWeek(void);
|
||||
void RTC_SetTickPeriod(uint32_t u32TickSelection);
|
||||
void RTC_EnableInt(uint32_t u32IntFlagMask);
|
||||
void RTC_DisableInt(uint32_t u32IntFlagMask);
|
||||
|
||||
/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group RTC_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __NU_RTC_H__ */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,558 +0,0 @@
|
|||
/******************************************************************************
|
||||
* @file nu_spi.h
|
||||
* @version V1.00
|
||||
* $Revision: 4 $
|
||||
* $Date: 18/06/07 2:32p $
|
||||
* @brief M031 series SPI driver header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_SPI_H__
|
||||
#define __NU_SPI_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Driver SPI Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define SPI_NONE (0x00ul) /*!< SPI interface not existed \hideinitializer */
|
||||
#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */
|
||||
#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */
|
||||
#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */
|
||||
#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */
|
||||
#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
|
||||
#define SPI_MASTER (0x0ul) /*!< Set as master \hideinitializer */
|
||||
#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */
|
||||
#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */
|
||||
#define SPI_SS_ACTIVE_LOW (0x0ul) /*!< SS active low \hideinitializer */
|
||||
|
||||
/* SPI Interrupt Mask */
|
||||
#define SPI_UNIT_INT_MASK (0x001ul) /*!< Unit transfer interrupt mask \hideinitializer */
|
||||
#define SPI_SSACT_INT_MASK (0x002ul) /*!< Slave selection signal active interrupt mask \hideinitializer */
|
||||
#define SPI_SSINACT_INT_MASK (0x004ul) /*!< Slave selection signal inactive interrupt mask \hideinitializer */
|
||||
#define SPI_SLVUR_INT_MASK (0x008ul) /*!< Slave under run interrupt mask \hideinitializer */
|
||||
#define SPI_SLVBE_INT_MASK (0x010ul) /*!< Slave bit count error interrupt mask \hideinitializer */
|
||||
#define SPI_TXUF_INT_MASK (0x040ul) /*!< Slave TX underflow interrupt mask \hideinitializer */
|
||||
#define SPI_FIFO_TXTH_INT_MASK (0x080ul) /*!< FIFO TX threshold interrupt mask \hideinitializer */
|
||||
#define SPI_FIFO_RXTH_INT_MASK (0x100ul) /*!< FIFO RX threshold interrupt mask \hideinitializer */
|
||||
#define SPI_FIFO_RXOV_INT_MASK (0x200ul) /*!< FIFO RX overrun interrupt mask \hideinitializer */
|
||||
#define SPI_FIFO_RXTO_INT_MASK (0x400ul) /*!< FIFO RX time-out interrupt mask \hideinitializer */
|
||||
|
||||
/* SPI Status Mask */
|
||||
#define SPI_BUSY_MASK (0x01ul) /*!< Busy status mask \hideinitializer */
|
||||
#define SPI_RX_EMPTY_MASK (0x02ul) /*!< RX empty status mask \hideinitializer */
|
||||
#define SPI_RX_FULL_MASK (0x04ul) /*!< RX full status mask \hideinitializer */
|
||||
#define SPI_TX_EMPTY_MASK (0x08ul) /*!< TX empty status mask \hideinitializer */
|
||||
#define SPI_TX_FULL_MASK (0x10ul) /*!< TX full status mask \hideinitializer */
|
||||
#define SPI_TXRX_RESET_MASK (0x20ul) /*!< TX or RX reset status mask \hideinitializer */
|
||||
#define SPI_SPIEN_STS_MASK (0x40ul) /*!< SPIEN status mask \hideinitializer */
|
||||
#define SPI_SSLINE_STS_MASK (0x80ul) /*!< SPIx_SS line status mask \hideinitializer */
|
||||
|
||||
|
||||
/* SPII2S Data Width */
|
||||
#define SPII2S_DATABIT_8 (0ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPII2S data width is 8-bit \hideinitializer */
|
||||
#define SPII2S_DATABIT_16 (1ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPII2S data width is 16-bit \hideinitializer */
|
||||
#define SPII2S_DATABIT_24 (2ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPII2S data width is 24-bit \hideinitializer */
|
||||
#define SPII2S_DATABIT_32 (3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPII2S data width is 32-bit \hideinitializer */
|
||||
|
||||
/* SPII2S Audio Format */
|
||||
#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel \hideinitializer */
|
||||
#define SPII2S_STEREO (0x0ul) /*!< Stereo channel \hideinitializer */
|
||||
|
||||
/* SPII2S Data Format */
|
||||
#define SPII2S_FORMAT_I2S (0ul<<SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format \hideinitializer */
|
||||
#define SPII2S_FORMAT_MSB (1ul<<SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format \hideinitializer */
|
||||
#define SPII2S_FORMAT_PCMA (2ul<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format \hideinitializer */
|
||||
#define SPII2S_FORMAT_PCMB (3ul<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format \hideinitializer */
|
||||
|
||||
/* SPII2S Operation mode */
|
||||
#define SPII2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode \hideinitializer */
|
||||
#define SPII2S_MODE_MASTER (0x0ul) /*!< As master mode \hideinitializer */
|
||||
|
||||
/* SPII2S TX FIFO Threshold */
|
||||
#define SPII2S_FIFO_TX_LEVEL_WORD_0 (0ul) /*!< TX threshold is 0 word \hideinitializer */
|
||||
#define SPII2S_FIFO_TX_LEVEL_WORD_1 (1ul << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */
|
||||
#define SPII2S_FIFO_TX_LEVEL_WORD_2 (2ul << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */
|
||||
#define SPII2S_FIFO_TX_LEVEL_WORD_3 (3ul << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */
|
||||
/* SPII2S RX FIFO Threshold */
|
||||
#define SPII2S_FIFO_RX_LEVEL_WORD_1 (0ul) /*!< RX threshold is 1 word \hideinitializer */
|
||||
#define SPII2S_FIFO_RX_LEVEL_WORD_2 (1ul << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */
|
||||
#define SPII2S_FIFO_RX_LEVEL_WORD_3 (2ul << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */
|
||||
#define SPII2S_FIFO_RX_LEVEL_WORD_4 (3ul << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */
|
||||
|
||||
/* SPII2S Record Channel */
|
||||
#define SPII2S_MONO_RIGHT (0ul) /*!< Record mono right channel \hideinitializer */
|
||||
#define SPII2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
|
||||
|
||||
/* SPII2S Channel */
|
||||
#define SPII2S_RIGHT (0ul) /*!< Select right channel \hideinitializer */
|
||||
#define SPII2S_LEFT (1ul) /*!< Select left channel \hideinitializer */
|
||||
|
||||
/* SPII2S Interrupt Mask */
|
||||
#define SPII2S_FIFO_TXTH_INT_MASK (0x01ul) /*!< TX FIFO threshold interrupt mask \hideinitializer */
|
||||
#define SPII2S_FIFO_RXTH_INT_MASK (0x02ul) /*!< RX FIFO threshold interrupt mask \hideinitializer */
|
||||
#define SPII2S_FIFO_RXOV_INT_MASK (0x04ul) /*!< RX FIFO overrun interrupt mask \hideinitializer */
|
||||
#define SPII2S_FIFO_RXTO_INT_MASK (0x08ul) /*!< RX FIFO time-out interrupt mask \hideinitializer */
|
||||
#define SPII2S_TXUF_INT_MASK (0x10ul) /*!< TX FIFO underflow interrupt mask \hideinitializer */
|
||||
#define SPII2S_RIGHT_ZC_INT_MASK (0x20ul) /*!< Right channel zero cross interrupt mask \hideinitializer */
|
||||
#define SPII2S_LEFT_ZC_INT_MASK (0x40ul) /*!< Left channel zero cross interrupt mask \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group SPI_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clear the unit transfer interrupt flag.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
|
||||
*/
|
||||
#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_UNITIF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Trigger RX PDMA function.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
|
||||
*/
|
||||
#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Trigger TX PDMA function.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
|
||||
*/
|
||||
#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Trigger TX and RX PDMA function.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Set TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to enable TX and RX PDMA transfer function.
|
||||
*/
|
||||
#define SPI_TRIGGER_TX_RX_PDMA(spi) ( (spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )
|
||||
|
||||
/**
|
||||
* @brief Disable RX PDMA transfer.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
|
||||
*/
|
||||
#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable TX PDMA transfer.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
|
||||
*/
|
||||
#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable TX and RX PDMA transfer.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Clear TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to disable TX and RX PDMA transfer function.
|
||||
*/
|
||||
#define SPI_DISABLE_TX_RX_PDMA(spi) ( (spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )
|
||||
|
||||
/**
|
||||
* @brief Get the count of available data in RX FIFO.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return The count of available data in RX FIFO.
|
||||
* @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
|
||||
*/
|
||||
#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
|
||||
|
||||
/**
|
||||
* @brief Get the RX FIFO empty flag.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @retval 0 RX FIFO is not empty.
|
||||
* @retval 1 RX FIFO is empty.
|
||||
* @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
|
||||
*/
|
||||
#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
|
||||
|
||||
/**
|
||||
* @brief Get the TX FIFO empty flag.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @retval 0 TX FIFO is not empty.
|
||||
* @retval 1 TX FIFO is empty.
|
||||
* @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
|
||||
*/
|
||||
#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
|
||||
|
||||
/**
|
||||
* @brief Get the TX FIFO full flag.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @retval 0 TX FIFO is not full.
|
||||
* @retval 1 TX FIFO is full.
|
||||
* @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
|
||||
*/
|
||||
#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
|
||||
|
||||
/**
|
||||
* @brief Get the datum read from RX register.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return Data in RX register.
|
||||
* @details Read SPI_RX register to get the received datum.
|
||||
*/
|
||||
#define SPI_READ_RX(spi) ((spi)->RX)
|
||||
|
||||
/**
|
||||
* @brief Write datum to TX register.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
|
||||
* @return None.
|
||||
* @details Write u32TxData to SPI_TX register.
|
||||
*/
|
||||
#define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData))
|
||||
|
||||
/**
|
||||
* @brief Set SPIx_SS pin to high state.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Disable automatic slave selection function and set SPIx_SS pin to high state.
|
||||
*/
|
||||
#define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
|
||||
|
||||
/**
|
||||
* @brief Set SPIx_SS pin to low state.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Disable automatic slave selection function and set SPIx_SS pin to low state.
|
||||
*/
|
||||
#define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable Byte Reorder function.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
|
||||
*/
|
||||
#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable Byte Reorder function.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
|
||||
*/
|
||||
#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set the length of suspend interval.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
|
||||
* @return None.
|
||||
* @details Set the length of suspend interval according to u32SuspCycle.
|
||||
* The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
|
||||
*/
|
||||
#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
|
||||
|
||||
/**
|
||||
* @brief Set the SPI transfer sequence with LSB first.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
|
||||
*/
|
||||
#define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set the SPI transfer sequence with MSB first.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
|
||||
*/
|
||||
#define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set the data width of a SPI transaction.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @param[in] u32Width The bit width of one transaction.
|
||||
* @return None.
|
||||
* @details The data width can be 8 ~ 32 bits.
|
||||
*/
|
||||
#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
|
||||
|
||||
/**
|
||||
* @brief Get the SPI busy state.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @retval 0 SPI controller is not busy.
|
||||
* @retval 1 SPI controller is busy.
|
||||
* @details This macro will return the busy state of SPI controller.
|
||||
*/
|
||||
#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )
|
||||
|
||||
/**
|
||||
* @brief Enable SPI controller.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Set SPIEN (SPI_CTL[0]) to enable SPI controller.
|
||||
*/
|
||||
#define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable SPI controller.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None.
|
||||
* @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
|
||||
*/
|
||||
#define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable zero cross detection function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @param[in] u32ChMask The mask for left or right channel. Valid values are:
|
||||
* - \ref SPII2S_RIGHT
|
||||
* - \ref SPII2S_LEFT
|
||||
* @return None
|
||||
* @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
|
||||
*/
|
||||
static __INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
|
||||
{
|
||||
if (u32ChMask == SPII2S_RIGHT)
|
||||
i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
|
||||
else
|
||||
i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable zero cross detection function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @param[in] u32ChMask The mask for left or right channel. Valid values are:
|
||||
* - \ref SPII2S_RIGHT
|
||||
* - \ref SPII2S_LEFT
|
||||
* @return None
|
||||
* @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
|
||||
*/
|
||||
static __INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
|
||||
{
|
||||
if (u32ChMask == SPII2S_RIGHT)
|
||||
i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
|
||||
else
|
||||
i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable SPII2S TX DMA function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return None
|
||||
* @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
|
||||
*/
|
||||
#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable SPII2S TX DMA function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return None
|
||||
* @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
|
||||
*/
|
||||
#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable SPII2S RX DMA function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return None
|
||||
* @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
|
||||
*/
|
||||
#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable SPII2S RX DMA function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return None
|
||||
* @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
|
||||
*/
|
||||
#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable SPII2S TX function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return None
|
||||
* @details This macro will set TXEN bit of SPI_I2SCTL register to enable SPII2S TX function.
|
||||
*/
|
||||
#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable SPII2S TX function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return None
|
||||
* @details This macro will clear TXEN bit of SPI_I2SCTL register to disable SPII2S TX function.
|
||||
*/
|
||||
#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable SPII2S RX function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return None
|
||||
* @details This macro will set RXEN bit of SPI_I2SCTL register to enable SPII2S RX function.
|
||||
*/
|
||||
#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable SPII2S RX function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return None
|
||||
* @details This macro will clear RXEN bit of SPI_I2SCTL register to disable SPII2S RX function.
|
||||
*/
|
||||
#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable TX Mute function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return None
|
||||
* @details This macro will set MUTE bit of SPI_I2SCTL register to enable SPII2S TX mute function.
|
||||
*/
|
||||
#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable TX Mute function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return None
|
||||
* @details This macro will clear MUTE bit of SPI_I2SCTL register to disable SPII2S TX mute function.
|
||||
*/
|
||||
#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
|
||||
|
||||
/**
|
||||
* @brief Clear TX FIFO.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return None
|
||||
* @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
|
||||
*/
|
||||
#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
|
||||
|
||||
/**
|
||||
* @brief Clear RX FIFO.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return None
|
||||
* @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
|
||||
*/
|
||||
#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
|
||||
|
||||
/**
|
||||
* @brief This function sets the recording source channel when mono mode is used.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @param[in] u32Ch left or right channel. Valid values are:
|
||||
* - \ref SPII2S_MONO_LEFT
|
||||
* - \ref SPII2S_MONO_RIGHT
|
||||
* @return None
|
||||
* @details This function selects the recording source channel of monaural mode.
|
||||
*/
|
||||
static __INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
|
||||
{
|
||||
u32Ch == SPII2S_MONO_LEFT ?
|
||||
(i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
|
||||
(i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write data to SPII2S TX FIFO.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @param[in] u32Data The value written to TX FIFO.
|
||||
* @return None
|
||||
* @details This macro will write a value to TX FIFO.
|
||||
*/
|
||||
#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) )
|
||||
|
||||
/**
|
||||
* @brief Read RX FIFO.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return The value read from RX FIFO.
|
||||
* @details This function will return a value read from RX FIFO.
|
||||
*/
|
||||
#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
|
||||
|
||||
/**
|
||||
* @brief Get the interrupt flag.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @param[in] u32Mask The mask value for all interrupt flags.
|
||||
* @return The interrupt flags specified by the u32mask parameter.
|
||||
* @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
|
||||
*/
|
||||
#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
|
||||
|
||||
/**
|
||||
* @brief Clear the interrupt flag.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @param[in] u32Mask The mask value for all interrupt flags.
|
||||
* @return None
|
||||
* @details This macro will clear the interrupt flags specified by the u32mask parameter.
|
||||
* @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
|
||||
*/
|
||||
#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
|
||||
|
||||
/**
|
||||
* @brief Get transmit FIFO level
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return TX FIFO level
|
||||
* @details This macro will return the number of available words in TX FIFO.
|
||||
*/
|
||||
#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )
|
||||
|
||||
/**
|
||||
* @brief Get receive FIFO level
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return RX FIFO level
|
||||
* @details This macro will return the number of available words in RX FIFO.
|
||||
*/
|
||||
#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
|
||||
|
||||
|
||||
|
||||
/* Function prototype declaration */
|
||||
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
|
||||
void SPI_Close(SPI_T *spi);
|
||||
void SPI_ClearRxFIFO(SPI_T *spi);
|
||||
void SPI_ClearTxFIFO(SPI_T *spi);
|
||||
void SPI_DisableAutoSS(SPI_T *spi);
|
||||
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
|
||||
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
|
||||
void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
|
||||
uint32_t SPI_GetBusClock(SPI_T *spi);
|
||||
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
|
||||
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
|
||||
uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
|
||||
void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
|
||||
uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
|
||||
|
||||
uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
|
||||
void SPII2S_Close(SPI_T *i2s);
|
||||
void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
|
||||
void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
|
||||
uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
|
||||
void SPII2S_DisableMCLK(SPI_T *i2s);
|
||||
void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
|
||||
|
||||
|
||||
/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group SPI_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__NU_SPI_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,507 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_timer.h
|
||||
* @version V0.10
|
||||
* $Revision: 6 $
|
||||
* $Date: 18/07/13 4:59p $
|
||||
* @brief M031 Series Timer Controller (TIMER) Driver Header File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_TIMER_H__
|
||||
#define __NU_TIMER_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMER_Driver TIMER Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode \hideinitializer */
|
||||
#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode \hideinitializer */
|
||||
#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode \hideinitializer */
|
||||
#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode \hideinitializer */
|
||||
|
||||
#define TIMER_TOUT_PIN_FROM_TX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from Tx pin \hideinitializer */
|
||||
#define TIMER_TOUT_PIN_FROM_TX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from Tx_EXT pin \hideinitializer */
|
||||
|
||||
#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value \hideinitializer */
|
||||
#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter \hideinitializer */
|
||||
|
||||
#define TIMER_CAPTURE_FALLING_EDGE (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger timer capture \hideinitializer */
|
||||
#define TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger timer capture \hideinitializer */
|
||||
#define TIMER_CAPTURE_FALLING_AND_RISING_EDGE (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger timer capture \hideinitializer */
|
||||
|
||||
#define TIMER_COUNTER_FALLING_EDGE (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection \hideinitializer */
|
||||
#define TIMER_COUNTER_RISING_EDGE (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection \hideinitializer */
|
||||
|
||||
#define TIMER_TRGSRC_TIMEOUT_EVENT (0UL << TIMER_CTL_TRGSSEL_Pos) /*!< Trigger source from Timeout event \hideinitializer */
|
||||
#define TIMER_TRGSRC_CAPTURE_EVENT (1UL << TIMER_CTL_TRGSSEL_Pos) /*!< Trigger source from Capture event \hideinitializer */
|
||||
|
||||
#define TIMER_CAPSRC_TX_EXT (0UL << TIMER_CTL_CAPSRC_Pos) /*!< Capture source from Tx_EXT pin \hideinitializer */
|
||||
#define TIMER_CAPSRC_INTERNAL (1UL << TIMER_CTL_CAPSRC_Pos) /*!< Capture source from Internal event such as LIRC or ACMP0/1 \hideinitializer */
|
||||
|
||||
#define TIMER_INTERCAPSEL_ACMP0 (0UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from Internal event ACMP0 \hideinitializer */
|
||||
#define TIMER_INTERCAPSEL_ACMP1 (1UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from Internal event ACMP1 \hideinitializer */
|
||||
#define TIMER_INTERCAPSEL_LIRC (5UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from Internal event LIRC \hideinitializer */
|
||||
|
||||
#define TIMER_TRG_TO_PWM (TIMER_CTL_TRGPWM_Msk) /*!< Timer trigger PWM \hideinitializer */
|
||||
#define TIMER_TRG_TO_ADC (TIMER_CTL_TRGADC_Msk) /*!< Timer trigger ADC \hideinitializer */
|
||||
#define TIMER_TRG_TO_PDMA (TIMER_CTL_TRGPDMA_Msk) /*!< Timer trigger PDMA \hideinitializer */
|
||||
#define TIMER_TRG_TO_BPWM (TIMER_CTL_TRGBPWM_Msk) /*!< Timer trigger BPWM \hideinitializer */
|
||||
|
||||
#define TIMER_CMP_MAX_VALUE (0xFFFFFFUL) /*!< Max Timer compare value \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set Timer Compared Value
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
* @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to set timer compared value to adjust timer time-out interval.
|
||||
* @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state.
|
||||
* @note 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously.
|
||||
* But if timer is operating at other modes, the timer up counter will restart counting and start from 0.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value))
|
||||
|
||||
/**
|
||||
* @brief Set Timer Prescale Value
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
* @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n
|
||||
* before it is fed into timer.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
|
||||
|
||||
/**
|
||||
* @brief Check specify Timer Status
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @retval 0 Timer 24-bit up counter is inactive
|
||||
* @retval 1 Timer 24-bit up counter is active
|
||||
*
|
||||
* @details This macro is used to check if specify Timer counter is inactive or active.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Select Toggle-output Pin
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
* @param[in] u32ToutSel Toggle-output pin selection, valid values are:
|
||||
* - \ref TIMER_TOUT_PIN_FROM_TX
|
||||
* - \ref TIMER_TOUT_PIN_FROM_TX_EXT
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to select timer toggle-output pin is output on Tx or Tx_EXT pin.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))
|
||||
|
||||
/**
|
||||
* @brief Start Timer Counting
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to start Timer counting.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_Start(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL |= TIMER_CTL_CNTEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop Timer Counting
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to stop/suspend Timer counting.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_Stop(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL &= ~TIMER_CTL_CNTEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Timer Interrupt Wake-up Function
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n
|
||||
* counter event interrupt or capture trigger interrupt.
|
||||
* @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_EnableWakeup(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL |= TIMER_CTL_WKEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Timer Wake-up Function
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to disable the timer interrupt wake-up function.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_DisableWakeup(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL &= ~TIMER_CTL_WKEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Capture Pin De-bounce
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable the detect de-bounce function of capture pin.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
|
||||
{
|
||||
timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Capture Pin De-bounce
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to disable the detect de-bounce function of capture pin.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
|
||||
{
|
||||
timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Counter Pin De-bounce
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable the detect de-bounce function of counter pin.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
|
||||
{
|
||||
timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Counter Pin De-bounce
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to disable the detect de-bounce function of counter pin.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
|
||||
{
|
||||
timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Timer Time-out Interrupt
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable the timer time-out interrupt function.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_EnableInt(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL |= TIMER_CTL_INTEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Timer Time-out Interrupt
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to disable the timer time-out interrupt function.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_DisableInt(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL &= ~TIMER_CTL_INTEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Capture Trigger Interrupt
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable the timer capture trigger interrupt function.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
|
||||
{
|
||||
timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Capture Trigger Interrupt
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to disable the timer capture trigger interrupt function.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
|
||||
{
|
||||
timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Timer Time-out Interrupt Flag
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @retval 0 Timer time-out interrupt did not occur
|
||||
* @retval 1 Timer time-out interrupt occurred
|
||||
*
|
||||
* @details This function indicates timer time-out interrupt occurred or not.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
|
||||
{
|
||||
return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Timer Time-out Interrupt Flag
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function clears timer time-out interrupt flag to 0.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
|
||||
{
|
||||
timer->INTSTS = TIMER_INTSTS_TIF_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Timer Capture Interrupt Flag
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @retval 0 Timer capture interrupt did not occur
|
||||
* @retval 1 Timer capture interrupt occurred
|
||||
*
|
||||
* @details This function indicates timer capture trigger interrupt occurred or not.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
|
||||
{
|
||||
return timer->EINTSTS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Timer Capture Interrupt Flag
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function clears timer capture trigger interrupt flag to 0.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
|
||||
{
|
||||
timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Timer Wake-up Flag
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @retval 0 Timer does not cause CPU wake-up
|
||||
* @retval 1 Timer interrupt event cause CPU wake-up
|
||||
*
|
||||
* @details This function indicates timer interrupt event has waked up system or not.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
|
||||
{
|
||||
return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1 : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Timer Wake-up Flag
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function clears the timer wake-up system flag to 0.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
|
||||
{
|
||||
timer->INTSTS = TIMER_INTSTS_TWKF_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Capture value
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return 24-bit Capture Value
|
||||
*
|
||||
* @details This function reports the current 24-bit timer capture value.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
|
||||
{
|
||||
return timer->CAP;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Counter value
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return 24-bit Counter Value
|
||||
*
|
||||
* @details This function reports the current 24-bit timer counter value.
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
static __INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
|
||||
{
|
||||
return timer->CNT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset Counter
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to reset current counter value and internal prescale counter value.
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL |= TIMER_CTL_RSTCNT_Msk;
|
||||
}
|
||||
|
||||
uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
|
||||
void TIMER_Close(TIMER_T *timer);
|
||||
void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
|
||||
void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
|
||||
void TIMER_DisableCapture(TIMER_T *timer);
|
||||
void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
|
||||
void TIMER_DisableEventCounter(TIMER_T *timer);
|
||||
uint32_t TIMER_GetModuleClock(TIMER_T *timer);
|
||||
void TIMER_EnableFreqCounter(TIMER_T *timer,
|
||||
uint32_t u32DropCount,
|
||||
uint32_t u32Timeout,
|
||||
uint32_t u32EnableInt);
|
||||
void TIMER_DisableFreqCounter(TIMER_T *timer);
|
||||
void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src);
|
||||
void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask);
|
||||
|
||||
/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group TIMER_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__NU_TIMER_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,495 +0,0 @@
|
|||
/****************************************************************************
|
||||
* @file nu_uart.h
|
||||
* @version V1.00
|
||||
* @brief M031 series UART driver source file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_UART_H__
|
||||
#define __NU_UART_H__
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup UART_Driver UART Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup UART_EXPORTED_CONSTANTS UART Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UART FIFO size constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
#define UART0_FIFO_SIZE 16ul /*!< UART0 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
|
||||
#define UART1_FIFO_SIZE 16ul /*!< UART1 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
|
||||
#define UART2_FIFO_SIZE 1ul /*!< UART2 supports separated receive/transmit 1/1 bytes entry FIFO \hideinitializer */
|
||||
#define UART3_FIFO_SIZE 1ul /*!< UART3 supports separated receive/transmit 1/1 bytes entry FIFO \hideinitializer */
|
||||
#define UART4_FIFO_SIZE 16ul /*!< UART4 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
|
||||
#define UART5_FIFO_SIZE 16ul /*!< UART5 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
|
||||
#define UART6_FIFO_SIZE 1ul /*!< UART6 supports separated receive/transmit 1/1 bytes entry FIFO \hideinitializer */
|
||||
#define UART7_FIFO_SIZE 1ul /*!< UART7 supports separated receive/transmit 1/1 bytes entry FIFO \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UART_FIFO constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
#define UART_FIFO_RFITL_1BYTE (0x0ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 byte \hideinitializer */
|
||||
#define UART_FIFO_RFITL_4BYTES (0x1ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bytes \hideinitializer */
|
||||
#define UART_FIFO_RFITL_8BYTES (0x2ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bytes \hideinitializer */
|
||||
#define UART_FIFO_RFITL_14BYTES (0x3ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bytes \hideinitializer */
|
||||
|
||||
#define UART_FIFO_RTSTRGLV_1BYTE (0x0ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 1 byte \hideinitializer */
|
||||
#define UART_FIFO_RTSTRGLV_4BYTES (0x1ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 4 bytes \hideinitializer */
|
||||
#define UART_FIFO_RTSTRGLV_8BYTES (0x2ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 8 bytes \hideinitializer */
|
||||
#define UART_FIFO_RTSTRGLV_14BYTES (0x3ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 14 bytes \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UART_LINE constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UART_WORD_LEN_5 (0ul) /*!< UART_LINE setting to set UART word length to 5 bits \hideinitializer */
|
||||
#define UART_WORD_LEN_6 (1ul) /*!< UART_LINE setting to set UART word length to 6 bits \hideinitializer */
|
||||
#define UART_WORD_LEN_7 (2ul) /*!< UART_LINE setting to set UART word length to 7 bits \hideinitializer */
|
||||
#define UART_WORD_LEN_8 (3ul) /*!< UART_LINE setting to set UART word length to 8 bits \hideinitializer */
|
||||
|
||||
#define UART_PARITY_NONE (0x0ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity \hideinitializer */
|
||||
#define UART_PARITY_ODD (0x1ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity \hideinitializer */
|
||||
#define UART_PARITY_EVEN (0x3ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity \hideinitializer */
|
||||
#define UART_PARITY_MARK (0x5ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' \hideinitializer */
|
||||
#define UART_PARITY_SPACE (0x7ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' \hideinitializer */
|
||||
|
||||
#define UART_STOP_BIT_1 (0x0ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit \hideinitializer */
|
||||
#define UART_STOP_BIT_1_5 (0x1ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length \hideinitializer */
|
||||
#define UART_STOP_BIT_2 (0x1ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length \hideinitializer */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UART RTS ACTIVE LEVEL constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UART_RTS_IS_LOW_LEV_ACTIVE (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Active \hideinitializer */
|
||||
#define UART_RTS_IS_HIGH_LEV_ACTIVE (0x0ul << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Active \hideinitializer */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UART_IRDA constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UART_IRDA_TXEN (0x1ul << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Tx mode \hideinitializer */
|
||||
#define UART_IRDA_RXEN (0x0ul << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Rx mode \hideinitializer */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UART_FUNCSEL constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UART_FUNCSEL_UART (0x0ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) \hideinitializer */
|
||||
#define UART_FUNCSEL_LIN (0x1ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function \hideinitializer */
|
||||
#define UART_FUNCSEL_IrDA (0x2ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function \hideinitializer */
|
||||
#define UART_FUNCSEL_RS485 (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function \hideinitializer */
|
||||
#define UART_FUNCSEL_SINGLE_WIRE (0x4ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set Single Wire Function \hideinitializer */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UART BAUDRATE MODE constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UART_BAUD_MODE0 (0ul) /*!< Set UART Baudrate Mode is Mode0 \hideinitializer */
|
||||
#define UART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk) /*!< Set UART Baudrate Mode is Mode2 \hideinitializer */
|
||||
|
||||
|
||||
/*@}*/ /* end of group UART_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Calculate UART baudrate mode0 divider
|
||||
*
|
||||
* @param[in] u32SrcFreq UART clock frequency
|
||||
* @param[in] u32BaudRate Baudrate of UART module
|
||||
*
|
||||
* @return UART baudrate mode0 divider
|
||||
*
|
||||
* @details This macro calculate UART baudrate mode0 divider.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)*8ul)) / (u32BaudRate) >> 4ul)-2ul)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Calculate UART baudrate mode2 divider
|
||||
*
|
||||
* @param[in] u32SrcFreq UART clock frequency
|
||||
* @param[in] u32BaudRate Baudrate of UART module
|
||||
*
|
||||
* @return UART baudrate mode2 divider
|
||||
*
|
||||
* @details This macro calculate UART baudrate mode2 divider.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write UART data
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
* @param[in] u8Data Data byte to transmit.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro write Data to Tx data register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Read UART data
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @return The oldest data byte in RX FIFO.
|
||||
*
|
||||
* @details This macro read Rx data register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_READ(uart) ((uart)->DAT)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Tx empty
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @retval 0 Tx FIFO is not empty
|
||||
* @retval >=1 Tx FIFO is empty
|
||||
*
|
||||
* @details This macro get Transmitter FIFO empty register value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Rx empty
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @retval 0 Rx FIFO is not empty
|
||||
* @retval >=1 Rx FIFO is empty
|
||||
*
|
||||
* @details This macro get Receiver FIFO empty register value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check specified UART port transmission is over.
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @retval 0 Tx transmission is not over
|
||||
* @retval 1 Tx transmission is over
|
||||
*
|
||||
* @details This macro return Transmitter Empty Flag register bit value.
|
||||
* It indicates if specified UART port transmission is over nor not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Wait specified UART port transmission is over
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro wait specified UART port transmission is over.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check RX is ready or not
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @retval 0 The number of bytes in the RX FIFO is less than the RFITL
|
||||
* @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL
|
||||
*
|
||||
* @details This macro check receive data available interrupt flag is set or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check TX FIFO is full or not
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @retval 1 TX FIFO is full
|
||||
* @retval 0 TX FIFO is not full
|
||||
*
|
||||
* @details This macro check TX FIFO is full or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check RX FIFO is full or not
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @retval 1 RX FIFO is full
|
||||
* @retval 0 RX FIFO is not full
|
||||
*
|
||||
* @details This macro check RX FIFO is full or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Tx full register value
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @retval 0 Tx FIFO is not full.
|
||||
* @retval >=1 Tx FIFO is full.
|
||||
*
|
||||
* @details This macro get Tx full register value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Rx full register value
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @retval 0 Rx FIFO is not full.
|
||||
* @retval >=1 Rx FIFO is full.
|
||||
*
|
||||
* @details This macro get Rx full register value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
|
||||
|
||||
/**
|
||||
* @brief Rx Idle Status register value
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @retval 0 Rx is busy.
|
||||
* @retval 1 Rx is Idle(Default)
|
||||
*
|
||||
* @details This macro get Rx Idle Status register value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_RX_IDLE(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXIDLE_Msk )>> UART_FIFOSTS_RXIDLE_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable specified UART interrupt
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
* @param[in] u32eIntSel Interrupt type select
|
||||
* - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty interrupt
|
||||
* - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
|
||||
* - \ref UART_INTEN_SWBEIEN_Msk : Single-wire bit error detection interrupt
|
||||
* - \ref UART_INTEN_RXPDMAEN_Msk : RX PDMA interrupt
|
||||
* - \ref UART_INTEN_TXPDMAEN_Msk : TX PDMA interrupt
|
||||
* - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt
|
||||
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
|
||||
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
|
||||
* - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
|
||||
* - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
|
||||
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
|
||||
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro enable specified UART interrupt.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable specified UART interrupt
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
* @param[in] u32eIntSel Interrupt type select
|
||||
* - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty interrupt
|
||||
* - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
|
||||
* - \ref UART_INTEN_SWBEIEN_Msk : Single-wire bit error detection interrupt
|
||||
* - \ref UART_INTEN_RXPDMAEN_Msk : RX PDMA interrupt
|
||||
* - \ref UART_INTEN_TXPDMAEN_Msk : TX PDMA interrupt
|
||||
* - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt
|
||||
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
|
||||
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
|
||||
* - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
|
||||
* - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
|
||||
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
|
||||
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro enable specified UART interrupt.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get specified interrupt flag/status
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
* @param[in] u32eIntTypeFlag Interrupt Type Flag, should be
|
||||
* - \ref UART_INTSTS_ABRINT_Msk : Auto-baud Rate Interrupt Indicator
|
||||
* - \ref UART_INTSTS_TXENDINT_Msk : Transmitter Empty Interrupt Indicator
|
||||
* - \ref UART_INTSTS_HWBUFEINT_Msk : In PDMA Mode, Buffer Error Interrupt Indicator
|
||||
* - \ref UART_INTSTS_HWTOINT_Msk : In PDMA Mode, Time-out Interrupt Indicator
|
||||
* - \ref UART_INTSTS_HWMODINT_Msk : In PDMA Mode, MODEM Status Interrupt Indicator
|
||||
* - \ref UART_INTSTS_HWRLSINT_Msk : In PDMA Mode, Receive Line Status Interrupt Indicator
|
||||
* - \ref UART_INTSTS_SWBEINT_Msk : In Single-wire Mode, Bit Error Detect Interrupt Indicator
|
||||
* - \ref UART_INTSTS_TXENDIF_Msk : Transmitter Empty Interrupt Flag
|
||||
* - \ref UART_INTSTS_HWBUFEIF_Msk : In PDMA Mode, Buffer Error Interrupt Flag
|
||||
* - \ref UART_INTSTS_HWTOIF_Msk : In PDMA Mode, Time-out Interrupt Flag
|
||||
* - \ref UART_INTSTS_HWMODIF_Msk : In PDMA Mode, MODEM Interrupt Flag
|
||||
* - \ref UART_INTSTS_HWRLSIF_Msk : In PDMA Mode, Receive Line Status Flag
|
||||
* - \ref UART_INTSTS_SWBEIF_Msk : In Single-wire Mode, Bit Error Detection Interrupt Flag
|
||||
* - \ref UART_INTSTS_WKINT_Msk : Wake-up Interrupt Indicator
|
||||
* - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator
|
||||
* - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator
|
||||
* - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator
|
||||
* - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator
|
||||
* - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator
|
||||
* - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator
|
||||
* - \ref UART_INTSTS_WKIF_Msk : Wake-up Interrupt Flag
|
||||
* - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag
|
||||
* - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag
|
||||
* - \ref UART_INTSTS_MODEMIF_Msk : Modem Interrupt Flag
|
||||
* - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag
|
||||
* - \ref UART_INTSTS_THREIF_Msk : Tx Empty Interrupt Flag
|
||||
* - \ref UART_INTSTS_RDAIF_Msk : Rx Ready Interrupt Flag
|
||||
*
|
||||
* @retval 0 The specified interrupt is not happened.
|
||||
* @retval 1 The specified interrupt is happened.
|
||||
*
|
||||
* @details This macro get specified interrupt flag or interrupt indicator status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear RS-485 Address Byte Detection Flag
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro clear RS-485 address byte detection flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get RS-485 Address Byte Detection Flag
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @retval 0 Receiver detects a data that is not an address bit.
|
||||
* @retval 1 Receiver detects a data that is an address bit.
|
||||
*
|
||||
* @details This macro get RS-485 address byte detection flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
|
||||
|
||||
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
|
||||
__STATIC_INLINE void UART_CLEAR_RTS(UART_T *uart);
|
||||
__STATIC_INLINE void UART_SET_RTS(UART_T *uart);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set RTS pin to low
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro set RTS pin to low.
|
||||
*/
|
||||
__STATIC_INLINE void UART_CLEAR_RTS(UART_T *uart)
|
||||
{
|
||||
uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
|
||||
uart->MODEM &= ~UART_MODEM_RTS_Msk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set RTS pin to high
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro set RTS pin to high.
|
||||
*/
|
||||
__STATIC_INLINE void UART_SET_RTS(UART_T *uart)
|
||||
{
|
||||
uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;
|
||||
}
|
||||
|
||||
|
||||
void UART_ClearIntFlag(UART_T *uart, uint32_t u32InterruptFlag);
|
||||
void UART_Close(UART_T *uart);
|
||||
void UART_DisableFlowCtrl(UART_T *uart);
|
||||
void UART_DisableInt(UART_T *uart, uint32_t u32InterruptFlag);
|
||||
void UART_EnableFlowCtrl(UART_T *uart);
|
||||
void UART_EnableInt(UART_T *uart, uint32_t u32InterruptFlag);
|
||||
void UART_Open(UART_T *uart, uint32_t u32baudrate);
|
||||
uint32_t UART_Read(UART_T *uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
|
||||
void UART_SetLine_Config(UART_T *uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
|
||||
void UART_SetTimeoutCnt(UART_T *uart, uint32_t u32TOC);
|
||||
void UART_SelectIrDAMode(UART_T *uart, uint32_t u32Buadrate, uint32_t u32Direction);
|
||||
void UART_SelectRS485Mode(UART_T *uart, uint32_t u32Mode, uint32_t u32Addr);
|
||||
uint32_t UART_Write(UART_T *uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
|
||||
void UART_SelectSingleWireMode(UART_T *uart);
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group UART_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__NU_UART_H__*/
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,699 +0,0 @@
|
|||
|
||||
/**************************************************************************//**
|
||||
* @file usbd.H
|
||||
* @version V1.00
|
||||
* $Revision: 9 $
|
||||
* $Date: 18/07/13 3:05p $
|
||||
* @brief M031 series USB driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_USBD_H__
|
||||
#define __NU_USBD_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup USBD_Driver USBD Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup USBD_EXPORTED_STRUCT USBD Exported Struct
|
||||
@{
|
||||
*/
|
||||
typedef struct s_usbd_info
|
||||
{
|
||||
uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */
|
||||
uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */
|
||||
uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */
|
||||
uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */
|
||||
uint8_t *gu8BosDesc; /*!< Pointer for USB BOS Descriptor */
|
||||
uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */
|
||||
uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */
|
||||
|
||||
} S_USBD_INFO_T; /*!< Device description structure */
|
||||
|
||||
extern const S_USBD_INFO_T gsInfo;
|
||||
|
||||
/*@}*/ /* end of group USBD_EXPORTED_STRUCTS */
|
||||
|
||||
|
||||
|
||||
|
||||
/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define USBD_BUF_BASE (USBD_BASE+0x100ul) /*!< USBD buffer base address \hideinitializer */
|
||||
#define USBD_MAX_EP 8ul /*!< Total EP number \hideinitializer */
|
||||
|
||||
#define EP0 0ul /*!< Endpoint 0 \hideinitializer */
|
||||
#define EP1 1ul /*!< Endpoint 1 \hideinitializer */
|
||||
#define EP2 2ul /*!< Endpoint 2 \hideinitializer */
|
||||
#define EP3 3ul /*!< Endpoint 3 \hideinitializer */
|
||||
#define EP4 4ul /*!< Endpoint 4 \hideinitializer */
|
||||
#define EP5 5ul /*!< Endpoint 5 \hideinitializer */
|
||||
#define EP6 6ul /*!< Endpoint 6 \hideinitializer */
|
||||
#define EP7 7ul /*!< Endpoint 7 \hideinitializer */
|
||||
|
||||
/** @cond HIDDEN_SYMBOLS */
|
||||
/* USB Request Type */
|
||||
#define REQ_STANDARD 0x00ul
|
||||
#define REQ_CLASS 0x20ul
|
||||
#define REQ_VENDOR 0x40ul
|
||||
|
||||
/* USB Standard Request */
|
||||
#define GET_STATUS 0x00ul
|
||||
#define CLEAR_FEATURE 0x01ul
|
||||
#define SET_FEATURE 0x03ul
|
||||
#define SET_ADDRESS 0x05ul
|
||||
#define GET_DESCRIPTOR 0x06ul
|
||||
#define SET_DESCRIPTOR 0x07ul
|
||||
#define GET_CONFIGURATION 0x08ul
|
||||
#define SET_CONFIGURATION 0x09ul
|
||||
#define GET_INTERFACE 0x0Aul
|
||||
#define SET_INTERFACE 0x0Bul
|
||||
#define SYNC_FRAME 0x0Cul
|
||||
|
||||
/* USB Descriptor Type */
|
||||
#define DESC_DEVICE 0x01ul
|
||||
#define DESC_CONFIG 0x02ul
|
||||
#define DESC_STRING 0x03ul
|
||||
#define DESC_INTERFACE 0x04ul
|
||||
#define DESC_ENDPOINT 0x05ul
|
||||
#define DESC_QUALIFIER 0x06ul
|
||||
#define DESC_OTHERSPEED 0x07ul
|
||||
#define DESC_IFPOWER 0x08ul
|
||||
#define DESC_OTG 0x09ul
|
||||
#define DESC_BOS 0x0Ful
|
||||
#define DESC_CAPABILITY 0x10ul
|
||||
|
||||
/* USB Device Capability Type */
|
||||
#define CAP_WIRELESS 0x01ul
|
||||
#define CAP_USB20_EXT 0x02ul
|
||||
|
||||
/* USB HID Descriptor Type */
|
||||
#define DESC_HID 0x21ul
|
||||
#define DESC_HID_RPT 0x22ul
|
||||
|
||||
/* USB Descriptor Length */
|
||||
#define LEN_DEVICE 18ul
|
||||
#define LEN_QUALIFIER 10ul
|
||||
#define LEN_CONFIG 9ul
|
||||
#define LEN_INTERFACE 9ul
|
||||
#define LEN_ENDPOINT 7ul
|
||||
#define LEN_OTG 5ul
|
||||
#define LEN_BOS 5ul
|
||||
#define LEN_HID 9ul
|
||||
#define LEN_CCID 0x36ul
|
||||
#define LEN_BOSCAP 7ul
|
||||
|
||||
/*!<USB Endpoint Type */
|
||||
#define EP_ISO 0x01
|
||||
#define EP_BULK 0x02
|
||||
#define EP_INT 0x03
|
||||
|
||||
#define EP_INPUT 0x80
|
||||
#define EP_OUTPUT 0x00
|
||||
|
||||
/* USB Feature Selector */
|
||||
#define FEATURE_DEVICE_REMOTE_WAKEUP 0x01ul
|
||||
#define FEATURE_ENDPOINT_HALT 0x00ul
|
||||
/** @endcond HIDDEN_SYMBOLS */
|
||||
|
||||
/******************************************************************************/
|
||||
/* USB Specific Macros */
|
||||
/******************************************************************************/
|
||||
|
||||
#define USBD_WAKEUP_EN USBD_INTEN_WKEN_Msk /*!< USB Wake-up Enable \hideinitializer */
|
||||
#define USBD_DRVSE0 USBD_SE0_SE0_Msk /*!< Drive SE0 \hideinitializer */
|
||||
#define USBD_L1RESUME USBD_ATTR_L1RESUME_Msk /*!< LPM L1 Resume \hideinitializer */
|
||||
#define USBD_L1SUSPEND USBD_ATTR_L1SUSPEND_Msk /*!< LPM L1 Suspend \hideinitializer */
|
||||
#define USBD_LPMACK USBD_ATTR_LPMACK_Msk /*!< LPM Enable \hideinitializer */
|
||||
#define USBD_BYTEM USBD_ATTR_BYTEM_Msk /*!< CPU Access USB SRAM Size Mode Selection \hideinitializer */
|
||||
#define USBD_DPPU_EN USBD_ATTR_DPPUEN_Msk /*!< USB D+ Pull-up Enable \hideinitializer */
|
||||
#define USBD_USB_EN USBD_ATTR_USBEN_Msk /*!< USB Enable \hideinitializer */
|
||||
#define USBD_RWAKEUP USBD_ATTR_RWAKEUP_Msk /*!< Remote Wake-up \hideinitializer */
|
||||
#define USBD_PHY_EN USBD_ATTR_PHYEN_Msk /*!< PHY Enable \hideinitializer */
|
||||
|
||||
#define USBD_INT_BUS USBD_INTEN_BUSIEN_Msk /*!< USB Bus Event Interrupt \hideinitializer */
|
||||
#define USBD_INT_USB USBD_INTEN_USBIEN_Msk /*!< USB Event Interrupt \hideinitializer */
|
||||
#define USBD_INT_FLDET USBD_INTEN_VBDETIEN_Msk /*!< USB VBUS Detection Interrupt \hideinitializer */
|
||||
#define USBD_INT_VBDET USBD_INTEN_VBDETIEN_Msk /*!< USB VBUS Detection Interrupt \hideinitializer */
|
||||
#define USBD_INT_WAKEUP (USBD_INTEN_NEVWKIEN_Msk | USBD_INTEN_WKEN_Msk) /*!< USB No-Event-Wake-Up Interrupt \hideinitializer */
|
||||
|
||||
#define USBD_INTSTS_SOF USBD_INTSTS_SOFIF_Msk /*!< USB Start of Frame Interrupt Status \hideinitializer */
|
||||
#define USBD_INTSTS_WAKEUP USBD_INTSTS_NEVWKIF_Msk /*!< USB No-Event-Wake-Up Interrupt Status \hideinitializer */
|
||||
#define USBD_INTSTS_FLDET USBD_INTSTS_VBDETIF_Msk /*!< USB Float Detect Interrupt Status \hideinitializer */
|
||||
#define USBD_INTSTS_VBDET USBD_INTSTS_VBDETIF_Msk /*!< USB Float Detect Interrupt Status \hideinitializer */
|
||||
#define USBD_INTSTS_BUS USBD_INTSTS_BUSIF_Msk /*!< USB Bus Event Interrupt Status \hideinitializer */
|
||||
#define USBD_INTSTS_USB USBD_INTSTS_USBIF_Msk /*!< USB Event Interrupt Status \hideinitializer */
|
||||
#define USBD_INTSTS_SETUP USBD_INTSTS_SETUP_Msk /*!< USB Setup Event \hideinitializer */
|
||||
#define USBD_INTSTS_EP0 USBD_INTSTS_EPEVT0_Msk /*!< USB Endpoint 0 Event \hideinitializer */
|
||||
#define USBD_INTSTS_EP1 USBD_INTSTS_EPEVT1_Msk /*!< USB Endpoint 1 Event \hideinitializer */
|
||||
#define USBD_INTSTS_EP2 USBD_INTSTS_EPEVT2_Msk /*!< USB Endpoint 2 Event \hideinitializer */
|
||||
#define USBD_INTSTS_EP3 USBD_INTSTS_EPEVT3_Msk /*!< USB Endpoint 3 Event \hideinitializer */
|
||||
#define USBD_INTSTS_EP4 USBD_INTSTS_EPEVT4_Msk /*!< USB Endpoint 4 Event \hideinitializer */
|
||||
#define USBD_INTSTS_EP5 USBD_INTSTS_EPEVT5_Msk /*!< USB Endpoint 5 Event \hideinitializer */
|
||||
#define USBD_INTSTS_EP6 USBD_INTSTS_EPEVT6_Msk /*!< USB Endpoint 6 Event \hideinitializer */
|
||||
#define USBD_INTSTS_EP7 USBD_INTSTS_EPEVT7_Msk /*!< USB Endpoint 7 Event \hideinitializer */
|
||||
|
||||
#define USBD_STATE_USBRST USBD_ATTR_USBRST_Msk /*!< USB Bus Reset \hideinitializer */
|
||||
#define USBD_STATE_SUSPEND USBD_ATTR_SUSPEND_Msk /*!< USB Bus Suspend \hideinitializer */
|
||||
#define USBD_STATE_RESUME USBD_ATTR_RESUME_Msk /*!< USB Bus Resume \hideinitializer */
|
||||
#define USBD_STATE_TIMEOUT USBD_ATTR_TOUT_Msk /*!< USB Bus Timeout \hideinitializer */
|
||||
#define USBD_STATE_L1RESUME USBD_ATTR_L1RESUME_Msk /*!< USB Bus L1RESUME \hideinitializer */
|
||||
#define USBD_STATE_L1SUSPEND USBD_ATTR_L1SUSPEND_Msk /*!< USB BUS L1SUSPEND \hideinitializer */
|
||||
|
||||
#define USBD_CFGP_SSTALL USBD_CFGP_SSTALL_Msk /*!< Set Stall \hideinitializer */
|
||||
#define USBD_CFGP_CLRRDY USBD_CFGP_CLRRDY_Msk
|
||||
|
||||
#define USBD_CFG_CSTALL USBD_CFG_CSTALL_Msk /*!< Clear Stall \hideinitializer */
|
||||
#define USBD_CFG_EPMODE_DISABLE (0ul << USBD_CFG_STATE_Pos) /*!< Endpoint Disable \hideinitializer */
|
||||
#define USBD_CFG_EPMODE_OUT (1ul << USBD_CFG_STATE_Pos) /*!< Out Endpoint \hideinitializer */
|
||||
#define USBD_CFG_EPMODE_IN (2ul << USBD_CFG_STATE_Pos) /*!< In Endpoint \hideinitializer */
|
||||
#define USBD_CFG_TYPE_ISO (1ul << USBD_CFG_ISOCH_Pos) /*!< Isochronous \hideinitializer */
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group USBD_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Compare two input numbers and return maximum one.
|
||||
*
|
||||
* @param[in] a First number to be compared.
|
||||
* @param[in] b Second number to be compared.
|
||||
*
|
||||
* @return Maximum value between a and b.
|
||||
*
|
||||
* @details If a > b, then return a. Otherwise, return b.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_Maximum(a,b) ((a)>(b) ? (a) : (b))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Compare two input numbers and return minimum one
|
||||
*
|
||||
* @param[in] a First number to be compared
|
||||
* @param[in] b Second number to be compared
|
||||
*
|
||||
* @return Minimum value between a and b
|
||||
*
|
||||
* @details If a < b, then return a. Otherwise, return b.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_Minimum(a,b) ((a)<(b) ? (a) : (b))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable USB
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details To set USB ATTR control register to enable USB and PHY.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_ENABLE_USB() ((uint32_t)(USBD->ATTR |= 0x7D0))
|
||||
|
||||
/**
|
||||
* @brief Disable USB
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details To set USB ATTR control register to disable USB.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_DISABLE_USB() ((uint32_t)(USBD->ATTR &= ~USBD_USB_EN))
|
||||
|
||||
/**
|
||||
* @brief Enable USB PHY
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details To set USB ATTR control register to enable USB PHY.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_ENABLE_PHY() ((uint32_t)(USBD->ATTR |= USBD_PHY_EN))
|
||||
|
||||
/**
|
||||
* @brief Disable USB PHY
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details To set USB ATTR control register to disable USB PHY.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_DISABLE_PHY() ((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN))
|
||||
|
||||
/**
|
||||
* @brief Enable SE0. Force USB PHY transceiver to drive SE0.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_SET_SE0() ((uint32_t)(USBD->SE0 |= USBD_DRVSE0))
|
||||
|
||||
/**
|
||||
* @brief Disable SE0
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_CLR_SE0() ((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0))
|
||||
|
||||
/**
|
||||
* @brief Set USB device address
|
||||
*
|
||||
* @param[in] addr The USB device address.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Write USB device address to USB_FADDR register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr))
|
||||
|
||||
/**
|
||||
* @brief Get USB device address
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return USB device address
|
||||
*
|
||||
* @details Read USB_FADDR register to get USB device address.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR))
|
||||
|
||||
/**
|
||||
* @brief Enable USB interrupt function
|
||||
*
|
||||
* @param[in] intr The combination of the specified interrupt enable bits.
|
||||
* Each bit corresponds to a interrupt enable bit.
|
||||
* This parameter decides which interrupts will be enabled.
|
||||
* (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS)
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Enable USB related interrupt functions specified by intr parameter.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr))
|
||||
|
||||
/**
|
||||
* @brief Get interrupt status
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return The value of USB_INTSTS register
|
||||
*
|
||||
* @details Return all interrupt flags of USB_INTSTS register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS))
|
||||
|
||||
/**
|
||||
* @brief Clear USB interrupt flag
|
||||
*
|
||||
* @param[in] flag The combination of the specified interrupt flags.
|
||||
* Each bit corresponds to a interrupt source.
|
||||
* This parameter decides which interrupt flags will be cleared.
|
||||
* (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB)
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Clear USB related interrupt flags specified by flag parameter.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = (flag))
|
||||
|
||||
/**
|
||||
* @brief Get endpoint status
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return The value of USB_EPSTS register.
|
||||
*
|
||||
* @details Return all endpoint status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS))
|
||||
|
||||
/**
|
||||
* @brief Get USB bus state
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return The value of USB_ATTR[3:0].
|
||||
* Bit 0 indicates USB bus reset status.
|
||||
* Bit 1 indicates USB bus suspend status.
|
||||
* Bit 2 indicates USB bus resume status.
|
||||
* Bit 3 indicates USB bus time-out status.
|
||||
*
|
||||
* @details Return USB_ATTR[3:0] for USB bus events.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->ATTR & 0xf))
|
||||
|
||||
/**
|
||||
* @brief Check cable connection state
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 0 USB cable is not attached.
|
||||
* @retval 1 USB cable is attached.
|
||||
*
|
||||
* @details Check the connection state by FLDET bit of USB_FLDET register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_IS_ATTACHED() ((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk))
|
||||
|
||||
/**
|
||||
* @brief Stop USB transaction of the specified endpoint ID
|
||||
*
|
||||
* @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set USB DATA1 PID for the specified endpoint ID
|
||||
*
|
||||
* @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction.
|
||||
* Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set USB DATA0 PID for the specified endpoint ID
|
||||
*
|
||||
* @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction.
|
||||
* Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk))
|
||||
|
||||
/**
|
||||
* @brief Set USB payload size (IN data)
|
||||
*
|
||||
* @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
|
||||
*
|
||||
* @param[in] size The transfer length.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size))
|
||||
|
||||
/**
|
||||
* @brief Get USB payload size (OUT data)
|
||||
*
|
||||
* @param[in] ep The USB endpoint ID. M451 Series supports 8 endpoint ID. This parameter could be 0 ~ 7.
|
||||
*
|
||||
* @return The value of USB_MXPLDx register.
|
||||
*
|
||||
* @details Get the data length of OUT data transaction by reading USB_MXPLDx register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))))
|
||||
|
||||
/**
|
||||
* @brief Configure endpoint
|
||||
*
|
||||
* @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
|
||||
*
|
||||
* @param[in] config The USB configuration.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro will write config parameter to USB_CFGx register of specified endpoint ID.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config))
|
||||
|
||||
/**
|
||||
* @brief Set USB endpoint buffer
|
||||
*
|
||||
* @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
|
||||
*
|
||||
* @param[in] offset The SRAM offset.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro will set the SRAM offset for the specified endpoint ID.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset))
|
||||
|
||||
/**
|
||||
* @brief Get the offset of the specified USB endpoint buffer
|
||||
*
|
||||
* @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
|
||||
*
|
||||
* @return The offset of the specified endpoint buffer.
|
||||
*
|
||||
* @details This macro will return the SRAM offset of the specified endpoint ID.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))))
|
||||
|
||||
/**
|
||||
* @brief Set USB endpoint stall state
|
||||
*
|
||||
* @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0ul].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk)
|
||||
|
||||
/**
|
||||
* @brief Clear USB endpoint stall state
|
||||
*
|
||||
* @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get USB endpoint stall state
|
||||
*
|
||||
* @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
|
||||
*
|
||||
* @retval 0 USB endpoint is not stalled.
|
||||
* @retval Others USB endpoint is stalled.
|
||||
*
|
||||
* @details Get USB endpoint stall state of the specified endpoint ID.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk)
|
||||
|
||||
/**
|
||||
* @brief To support byte access between USB SRAM and system SRAM
|
||||
*
|
||||
* @param[in] dest Destination pointer.
|
||||
*
|
||||
* @param[in] src Source pointer.
|
||||
*
|
||||
* @param[in] size Byte count.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size)
|
||||
{
|
||||
uint32_t volatile i = 0ul;
|
||||
|
||||
while (size--)
|
||||
{
|
||||
dest[i] = src[i];
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set USB endpoint stall state
|
||||
*
|
||||
* @param[in] epnum USB endpoint number
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Set USB endpoint stall state. Endpoint will respond STALL token automatically.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void USBD_SetStall(uint8_t epnum)
|
||||
{
|
||||
uint32_t u32CfgAddr;
|
||||
uint32_t u32Cfg;
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0ul; i < USBD_MAX_EP; i++)
|
||||
{
|
||||
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
|
||||
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||
|
||||
if ((u32Cfg & 0xful) == epnum)
|
||||
{
|
||||
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
|
||||
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||
|
||||
*((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear USB endpoint stall state
|
||||
*
|
||||
* @param[in] epnum USB endpoint number
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token.
|
||||
*/
|
||||
__STATIC_INLINE void USBD_ClearStall(uint8_t epnum)
|
||||
{
|
||||
uint32_t u32CfgAddr;
|
||||
uint32_t u32Cfg;
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0ul; i < USBD_MAX_EP; i++)
|
||||
{
|
||||
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
|
||||
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||
|
||||
if ((u32Cfg & 0xful) == epnum)
|
||||
{
|
||||
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
|
||||
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||
|
||||
*((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get USB endpoint stall state
|
||||
*
|
||||
* @param[in] epnum USB endpoint number
|
||||
*
|
||||
* @retval 0 USB endpoint is not stalled.
|
||||
* @retval Others USB endpoint is stalled.
|
||||
*
|
||||
* @details Get USB endpoint stall state.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum)
|
||||
{
|
||||
uint32_t u32CfgAddr;
|
||||
uint32_t u32Cfg;
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0ul; i < USBD_MAX_EP; i++)
|
||||
{
|
||||
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
|
||||
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||
|
||||
if ((u32Cfg & 0xful) == epnum)
|
||||
{
|
||||
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL);
|
||||
}
|
||||
|
||||
|
||||
extern volatile uint8_t g_usbd_RemoteWakeupEn;
|
||||
|
||||
|
||||
typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */
|
||||
typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */
|
||||
typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!< Functional pointer type declaration for USB set interface request callback handler */
|
||||
typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */
|
||||
|
||||
|
||||
/*--------------------------------------------------------------------*/
|
||||
void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
|
||||
void USBD_Start(void);
|
||||
void USBD_GetSetupPacket(uint8_t *buf);
|
||||
void USBD_ProcessSetupPacket(void);
|
||||
void USBD_StandardRequest(void);
|
||||
void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size);
|
||||
void USBD_CtrlIn(void);
|
||||
void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size);
|
||||
void USBD_CtrlOut(void);
|
||||
void USBD_SwReset(void);
|
||||
void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq);
|
||||
void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback);
|
||||
void USBD_LockEpStall(uint32_t u32EpBitmap);
|
||||
|
||||
/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group USBD_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__NU_USBD_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,332 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_usci_i2c.h
|
||||
* @version V1.00
|
||||
* @brief M031 series USCI I2C(UI2C) driver header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
******************************************************************************/
|
||||
#ifndef __NU_USCI_I2C_H__
|
||||
#define __NU_USCI_I2C_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup USCI_I2C_Driver USCI_I2C Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* USCI_I2C master event definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
enum UI2C_MASTER_EVENT
|
||||
{
|
||||
MASTER_SEND_ADDRESS = 10u, /*!< Master send address to Slave */
|
||||
MASTER_SEND_H_WR_ADDRESS, /*!< Master send High address to Slave */
|
||||
MASTER_SEND_H_RD_ADDRESS, /*!< Master send address to Slave (Read ADDR) */
|
||||
MASTER_SEND_L_ADDRESS, /*!< Master send Low address to Slave */
|
||||
MASTER_SEND_DATA, /*!< Master Send Data to Slave */
|
||||
MASTER_SEND_REPEAT_START, /*!< Master send repeat start to Slave */
|
||||
MASTER_READ_DATA, /*!< Master Get Data from Slave */
|
||||
MASTER_STOP, /*!< Master send stop to Slave */
|
||||
MASTER_SEND_START /*!< Master send start to Slave */
|
||||
};
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* USCI_I2C slave event definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
enum UI2C_SLAVE_EVENT
|
||||
{
|
||||
SLAVE_ADDRESS_ACK = 100u, /*!< Slave send address ACK */
|
||||
SLAVE_H_WR_ADDRESS_ACK, /*!< Slave send High address ACK */
|
||||
SLAVE_L_WR_ADDRESS_ACK, /*!< Slave send Low address ACK */
|
||||
SLAVE_GET_DATA, /*!< Slave Get Data from Master (Write CMD) */
|
||||
SLAVE_SEND_DATA, /*!< Slave Send Data to Master (Read CMD) */
|
||||
SLAVE_H_RD_ADDRESS_ACK, /*!< Slave send High address ACK */
|
||||
SLAVE_L_RD_ADDRESS_ACK /*!< Slave send Low address ACK */
|
||||
};
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* USCI_CTL constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UI2C_CTL_PTRG 0x20UL /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit \hideinitializer */
|
||||
#define UI2C_CTL_STA 0x08UL /*!< USCI_CTL setting for I2C control bits. It would set STA bit \hideinitializer */
|
||||
#define UI2C_CTL_STO 0x04UL /*!< USCI_CTL setting for I2C control bits. It would set STO bit \hideinitializer */
|
||||
#define UI2C_CTL_AA 0x02UL /*!< USCI_CTL setting for I2C control bits. It would set AA bit \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* USCI_I2C GCMode constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UI2C_GCMODE_ENABLE (1U) /*!< Enable USCI_I2C GC Mode \hideinitializer */
|
||||
#define UI2C_GCMODE_DISABLE (0U) /*!< Disable USCI_I2C GC Mode \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* USCI_I2C Wakeup Mode constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UI2C_DATA_TOGGLE_WK (0x0U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according data toggle \hideinitializer */
|
||||
#define UI2C_ADDR_MATCH_WK (0x1U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according address match \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* USCI_I2C interrupt mask definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UI2C_TO_INT_MASK (0x001U) /*!< Time-out interrupt mask \hideinitializer */
|
||||
#define UI2C_STAR_INT_MASK (0x002U) /*!< Start condition received interrupt mask \hideinitializer */
|
||||
#define UI2C_STOR_INT_MASK (0x004U) /*!< Stop condition received interrupt mask \hideinitializer */
|
||||
#define UI2C_NACK_INT_MASK (0x008U) /*!< Non-acknowledge interrupt mask \hideinitializer */
|
||||
#define UI2C_ARBLO_INT_MASK (0x010U) /*!< Arbitration lost interrupt mask \hideinitializer */
|
||||
#define UI2C_ERR_INT_MASK (0x020U) /*!< Error interrupt mask \hideinitializer */
|
||||
#define UI2C_ACK_INT_MASK (0x040U) /*!< Acknowledge interrupt mask \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This macro sets the USCI_I2C protocol control register at one time
|
||||
*
|
||||
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||
* @param[in] u8Ctrl Set the register value of USCI_I2C control register.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, PTRG, ACK.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UI2C_SET_CONTROL_REG(ui2c, u8Ctrl) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2EU) | (u8Ctrl))
|
||||
|
||||
/**
|
||||
* @brief This macro only set START bit to protocol control register of USCI_I2C module.
|
||||
*
|
||||
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Set the USCI_I2C bus START condition in UI2C_PROTCTL register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UI2C_START(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro only set STOP bit to the control register of USCI_I2C module
|
||||
*
|
||||
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UI2C_STOP(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk))
|
||||
|
||||
/**
|
||||
* @brief This macro returns the data stored in data register of USCI_I2C module
|
||||
*
|
||||
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||
*
|
||||
* @return Data
|
||||
*
|
||||
* @details Read a byte data value of UI2C_RXDAT register from USCI_I2C bus
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UI2C_GET_DATA(ui2c) ((ui2c)->RXDAT)
|
||||
|
||||
/**
|
||||
* @brief This macro writes the data to data register of USCI_I2C module
|
||||
*
|
||||
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||
* @param[in] u8Data The data which will be written to data register of USCI_I2C module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UI2C_SET_DATA(ui2c, u8Data) ((ui2c)->TXDAT = (u8Data))
|
||||
|
||||
/**
|
||||
* @brief This macro returns time-out flag
|
||||
*
|
||||
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||
*
|
||||
* @retval 0 USCI_I2C bus time-out is not happened
|
||||
* @retval 1 USCI_I2C bus time-out is happened
|
||||
*
|
||||
* @details USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UI2C_GET_TIMEOUT_FLAG(ui2c) (((ui2c)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0)
|
||||
|
||||
/**
|
||||
* @brief This macro returns wake-up flag
|
||||
*
|
||||
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||
*
|
||||
* @retval 0 Chip is not woken-up from power-down mode
|
||||
* @retval 1 Chip is woken-up from power-down mode
|
||||
*
|
||||
* @details USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UI2C_GET_WAKEUP_FLAG(ui2c) (((ui2c)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to clear USCI_I2C wake-up flag
|
||||
*
|
||||
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details If USCI_I2C wake-up flag is set, use this macro to clear it.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UI2C_CLR_WAKEUP_FLAG(ui2c) ((ui2c)->WKSTS = UI2C_WKSTS_WKF_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro disables the USCI_I2C 10-bit address mode
|
||||
*
|
||||
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UI2C_DISABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk))
|
||||
|
||||
/**
|
||||
* @brief This macro enables the 10-bit address mode
|
||||
*
|
||||
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details To enable USCI_I2C 10-bit address match function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UI2C_ENABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro gets USCI_I2C protocol interrupt flag or bus status
|
||||
*
|
||||
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||
*
|
||||
* @return A word data of USCI_I2C_PROTSTS register
|
||||
*
|
||||
* @details Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UI2C_GET_PROT_STATUS(ui2c) ((ui2c)->PROTSTS)
|
||||
|
||||
/**
|
||||
* @brief This macro clears specified protocol interrupt flag
|
||||
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
|
||||
* - \ref UI2C_PROTSTS_ACKIF_Msk
|
||||
* - \ref UI2C_PROTSTS_ERRIF_Msk
|
||||
* - \ref UI2C_PROTSTS_ARBLOIF_Msk
|
||||
* - \ref UI2C_PROTSTS_NACKIF_Msk
|
||||
* - \ref UI2C_PROTSTS_STORIF_Msk
|
||||
* - \ref UI2C_PROTSTS_STARIF_Msk
|
||||
* - \ref UI2C_PROTSTS_TOIF_Msk
|
||||
* @return None
|
||||
*
|
||||
* @details To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UI2C_CLR_PROT_INT_FLAG(ui2c,u32IntTypeFlag) ((ui2c)->PROTSTS = (u32IntTypeFlag))
|
||||
|
||||
/**
|
||||
* @brief This macro enables specified protocol interrupt
|
||||
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||
* @param[in] u32IntSel Interrupt Type, should be
|
||||
* - \ref UI2C_PROTIEN_ACKIEN_Msk
|
||||
* - \ref UI2C_PROTIEN_ERRIEN_Msk
|
||||
* - \ref UI2C_PROTIEN_ARBLOIEN_Msk
|
||||
* - \ref UI2C_PROTIEN_NACKIEN_Msk
|
||||
* - \ref UI2C_PROTIEN_STORIEN_Msk
|
||||
* - \ref UI2C_PROTIEN_STARIEN_Msk
|
||||
* - \ref UI2C_PROTIEN_TOIEN_Msk
|
||||
* @return None
|
||||
*
|
||||
* @details Set specified USCI_I2C protocol interrupt bits to enable interrupt function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UI2C_ENABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN |= (u32IntSel))
|
||||
|
||||
/**
|
||||
* @brief This macro disables specified protocol interrupt
|
||||
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||
* @param[in] u32IntSel Interrupt Type, should be
|
||||
* - \ref UI2C_PROTIEN_ACKIEN_Msk
|
||||
* - \ref UI2C_PROTIEN_ERRIEN_Msk
|
||||
* - \ref UI2C_PROTIEN_ARBLOIEN_Msk
|
||||
* - \ref UI2C_PROTIEN_NACKIEN_Msk
|
||||
* - \ref UI2C_PROTIEN_STORIEN_Msk
|
||||
* - \ref UI2C_PROTIEN_STARIEN_Msk
|
||||
* - \ref UI2C_PROTIEN_TOIEN_Msk
|
||||
* @return None
|
||||
*
|
||||
* @details Clear specified USCI_I2C protocol interrupt bits to disable interrupt function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UI2C_DISABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN &= ~ (u32IntSel))
|
||||
|
||||
|
||||
uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock);
|
||||
void UI2C_Close(UI2C_T *ui2c);
|
||||
void UI2C_ClearTimeoutFlag(UI2C_T *ui2c);
|
||||
void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack);
|
||||
void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask);
|
||||
void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask);
|
||||
uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c);
|
||||
uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock);
|
||||
uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask);
|
||||
void UI2C_ClearIntFlag(UI2C_T *ui2c , uint32_t u32Mask);
|
||||
uint32_t UI2C_GetData(UI2C_T *ui2c);
|
||||
void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data);
|
||||
void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode);
|
||||
void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask);
|
||||
void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt);
|
||||
void UI2C_DisableTimeout(UI2C_T *ui2c);
|
||||
void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode);
|
||||
void UI2C_DisableWakeup(UI2C_T *ui2c);
|
||||
uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, const uint8_t data);
|
||||
uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, const uint8_t *data, uint32_t u32wLen);
|
||||
uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, const uint8_t data);
|
||||
uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, const uint8_t *data, uint32_t u32wLen);
|
||||
uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, const uint8_t data);
|
||||
uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, const uint8_t *data, uint32_t u32wLen);
|
||||
uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr);
|
||||
uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen);
|
||||
uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
|
||||
uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen);
|
||||
uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
|
||||
uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen);
|
||||
|
||||
/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group USCI_I2C_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __NU_USCI_I2C_H__ */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,428 +0,0 @@
|
|||
/****************************************************************************//**
|
||||
* @file nu_usci_spi.h
|
||||
* @version V1.00
|
||||
* @brief M031 series USCI_SPI driver header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_USCI_SPI_H__
|
||||
#define __NU_USCI_SPI_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup USCI_SPI_Driver USCI_SPI Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
#define USPI_MODE_0 (0x0UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with falling edge and receive with rising edge \hideinitializer */
|
||||
#define USPI_MODE_1 (0x1UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with rising edge and receive with falling edge \hideinitializer */
|
||||
#define USPI_MODE_2 (0x2UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with rising edge and receive with falling edge \hideinitializer */
|
||||
#define USPI_MODE_3 (0x3UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with falling edge and receive with rising edge \hideinitializer */
|
||||
|
||||
#define USPI_SLAVE (USPI_PROTCTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
|
||||
#define USPI_MASTER (0x0UL) /*!< Set as master \hideinitializer */
|
||||
|
||||
#define USPI_SS (USPI_PROTCTL_SS_Msk) /*!< Set SS \hideinitializer */
|
||||
#define USPI_SS_ACTIVE_HIGH (0x0UL) /*!< SS active high \hideinitializer */
|
||||
#define USPI_SS_ACTIVE_LOW (USPI_LINECTL_CTLOINV_Msk) /*!< SS active low \hideinitializer */
|
||||
|
||||
/* USCI_SPI Interrupt Mask */
|
||||
#define USPI_SSINACT_INT_MASK (0x001UL) /*!< Slave Select Inactive interrupt mask \hideinitializer */
|
||||
#define USPI_SSACT_INT_MASK (0x002UL) /*!< Slave Select Active interrupt mask \hideinitializer */
|
||||
#define USPI_SLVTO_INT_MASK (0x004UL) /*!< Slave Mode Time-out interrupt mask \hideinitializer */
|
||||
#define USPI_SLVBE_INT_MASK (0x008UL) /*!< Slave Mode Bit Count Error interrupt mask \hideinitializer */
|
||||
#define USPI_TXUDR_INT_MASK (0x010UL) /*!< Slave Transmit Under Run interrupt mask \hideinitializer */
|
||||
#define USPI_RXOV_INT_MASK (0x020UL) /*!< Receive Buffer Overrun interrupt mask \hideinitializer */
|
||||
#define USPI_TXST_INT_MASK (0x040UL) /*!< Transmit Start interrupt mask \hideinitializer */
|
||||
#define USPI_TXEND_INT_MASK (0x080UL) /*!< Transmit End interrupt mask \hideinitializer */
|
||||
#define USPI_RXST_INT_MASK (0x100UL) /*!< Receive Start interrupt mask \hideinitializer */
|
||||
#define USPI_RXEND_INT_MASK (0x200UL) /*!< Receive End interrupt mask \hideinitializer */
|
||||
|
||||
/* USCI_SPI Status Mask */
|
||||
#define USPI_BUSY_MASK (0x01UL) /*!< Busy status mask \hideinitializer */
|
||||
#define USPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask \hideinitializer */
|
||||
#define USPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask \hideinitializer */
|
||||
#define USPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask \hideinitializer */
|
||||
#define USPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask \hideinitializer */
|
||||
#define USPI_SSLINE_STS_MASK (0x20UL) /*!< USCI_SPI_SS line status mask \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Disable slave 3-wire mode.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_DISABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable slave 3-wire mode.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_ENABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk )
|
||||
|
||||
/**
|
||||
* @brief Get the Rx buffer empty flag.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return Rx buffer flag
|
||||
* @retval 0: Rx buffer is not empty
|
||||
* @retval 1: Rx buffer is empty
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_GET_RX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief Get the Tx buffer empty flag.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return Tx buffer flag
|
||||
* @retval 0: Tx buffer is not empty
|
||||
* @retval 1: Tx buffer is empty
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_GET_TX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief Get the Tx buffer full flag.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return Tx buffer flag
|
||||
* @retval 0: Tx buffer is not full
|
||||
* @retval 1: Tx buffer is full
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_GET_TX_FULL_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief Get the datum read from RX register.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return data in Rx register
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_READ_RX(uspi) ( (uspi)->RXDAT )
|
||||
|
||||
/**
|
||||
* @brief Write datum to TX register.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32TxData The datum which user attempt to transfer through USCI_SPI bus.
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_WRITE_TX(uspi, u32TxData) ( (uspi)->TXDAT = (u32TxData) )
|
||||
|
||||
/**
|
||||
* @brief Set USCI_SPI_SS pin to high state.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None.
|
||||
* @details Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_SET_SS_HIGH(uspi) \
|
||||
do{ \
|
||||
(uspi)->LINECTL &= ~(USPI_LINECTL_CTLOINV_Msk); \
|
||||
(uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Set USCI_SPI_SS pin to low state.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None.
|
||||
* @details Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_SET_SS_LOW(uspi) \
|
||||
do{ \
|
||||
(uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \
|
||||
(uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Set the length of suspend interval.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32SuspCycle Decide the length of suspend interval.
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_SET_SUSPEND_CYCLE(uspi, u32SuspCycle) ( (uspi)->PROTCTL = ((uspi)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | ((u32SuspCycle) << USPI_PROTCTL_SUSPITV_Pos) )
|
||||
|
||||
/**
|
||||
* @brief Set the USCI_SPI transfer sequence with LSB first.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_SET_LSB_FIRST(uspi) ( (uspi)->LINECTL |= USPI_LINECTL_LSB_Msk )
|
||||
|
||||
/**
|
||||
* @brief Set the USCI_SPI transfer sequence with MSB first.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_SET_MSB_FIRST(uspi) ( (uspi)->LINECTL &= ~USPI_LINECTL_LSB_Msk )
|
||||
|
||||
/**
|
||||
* @brief Set the data width of a USCI_SPI transaction.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32Width The data width
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_SET_DATA_WIDTH(uspi, u32Width) \
|
||||
do{ \
|
||||
if((u32Width) == 16ul){ \
|
||||
(uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (0 << USPI_LINECTL_DWIDTH_Pos); \
|
||||
}else { \
|
||||
(uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | ((u32Width) << USPI_LINECTL_DWIDTH_Pos); \
|
||||
} \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Get the USCI_SPI busy state.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return USCI_SPI busy status
|
||||
* @retval 0: USCI_SPI module is not busy
|
||||
* @retval 1: USCI_SPI module is busy
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_IS_BUSY(uspi) ( ((uspi)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief Get the USCI_SPI wakeup flag.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return Wakeup status.
|
||||
* @retval 0 Flag is not set.
|
||||
* @retval 1 Flag is set.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_GET_WAKEUP_FLAG(uspi) ( ((uspi)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief Clear the USCI_SPI wakeup flag.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_CLR_WAKEUP_FLAG(uspi) ( (uspi)->WKSTS |= USPI_WKSTS_WKF_Msk )
|
||||
|
||||
/**
|
||||
* @brief Get protocol interrupt flag/status.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return The interrupt flag/status of protocol status register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_GET_PROT_STATUS(uspi) ( (uspi)->PROTSTS )
|
||||
|
||||
/**
|
||||
* @brief Clear specified protocol interrupt flag.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
|
||||
* - \ref USPI_PROTSTS_SSACTIF_Msk
|
||||
* - \ref USPI_PROTSTS_SSINAIF_Msk
|
||||
* - \ref USPI_PROTSTS_SLVBEIF_Msk
|
||||
* - \ref USPI_PROTSTS_SLVTOIF_Msk
|
||||
* - \ref USPI_PROTSTS_RXENDIF_Msk
|
||||
* - \ref USPI_PROTSTS_RXSTIF_Msk
|
||||
* - \ref USPI_PROTSTS_TXENDIF_Msk
|
||||
* - \ref USPI_PROTSTS_TXSTIF_Msk
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_CLR_PROT_INT_FLAG(uspi, u32IntTypeFlag) ( (uspi)->PROTSTS = (u32IntTypeFlag) )
|
||||
|
||||
/**
|
||||
* @brief Get buffer interrupt flag/status.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return The interrupt flag/status of buffer status register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_GET_BUF_STATUS(uspi) ( (uspi)->BUFSTS )
|
||||
|
||||
/**
|
||||
* @brief Clear specified buffer interrupt flag.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
|
||||
* - \ref USPI_BUFSTS_TXUDRIF_Msk
|
||||
* - \ref USPI_BUFSTS_RXOVIF_Msk
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_CLR_BUF_INT_FLAG(uspi, u32IntTypeFlag) ( (uspi)->BUFSTS = (u32IntTypeFlag) )
|
||||
|
||||
/**
|
||||
* @brief Enable specified protocol interrupt.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32IntSel Interrupt Type, should be
|
||||
* - \ref USPI_PROTIEN_SLVBEIEN_Msk
|
||||
* - \ref USPI_PROTIEN_SLVTOIEN_Msk
|
||||
* - \ref USPI_PROTIEN_SSACTIEN_Msk
|
||||
* - \ref USPI_PROTIEN_SSINAIEN_Msk
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_ENABLE_PROT_INT(uspi, u32IntSel) ( (uspi)->PROTIEN |= (u32IntSel) )
|
||||
|
||||
/**
|
||||
* @brief Disable specified protocol interrupt.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32IntSel Interrupt Type, should be
|
||||
* - \ref USPI_PROTIEN_SLVBEIEN_Msk
|
||||
* - \ref USPI_PROTIEN_SLVTOIEN_Msk
|
||||
* - \ref USPI_PROTIEN_SSACTIEN_Msk
|
||||
* - \ref USPI_PROTIEN_SSINAIEN_Msk
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_DISABLE_PROT_INT(uspi, u32IntSel) ( (uspi)->PROTIEN &= ~ (u32IntSel) )
|
||||
|
||||
/**
|
||||
* @brief Enable specified buffer interrupt.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32IntSel Interrupt Type, should be
|
||||
* - \ref USPI_BUFCTL_RXOVIEN_Msk
|
||||
* - \ref USPI_BUFCTL_TXUDRIEN_Msk
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_ENABLE_BUF_INT(uspi, u32IntSel) ( (uspi)->BUFCTL |= (u32IntSel) )
|
||||
|
||||
/**
|
||||
* @brief Disable specified buffer interrupt.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32IntSel Interrupt Type, should be
|
||||
* - \ref USPI_BUFCTL_RXOVIEN_Msk
|
||||
* - \ref USPI_BUFCTL_TXUDRIEN_Msk
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_DISABLE_BUF_INT(uspi, u32IntSel) ( (uspi)->BUFCTL &= ~ (u32IntSel) )
|
||||
|
||||
/**
|
||||
* @brief Enable specified transfer interrupt.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32IntSel Interrupt Type, should be
|
||||
* - \ref USPI_INTEN_RXENDIEN_Msk
|
||||
* - \ref USPI_INTEN_RXSTIEN_Msk
|
||||
* - \ref USPI_INTEN_TXENDIEN_Msk
|
||||
* - \ref USPI_INTEN_TXSTIEN_Msk
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_ENABLE_TRANS_INT(uspi, u32IntSel) ( (uspi)->INTEN |= (u32IntSel) )
|
||||
|
||||
/**
|
||||
* @brief Disable specified transfer interrupt.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32IntSel Interrupt Type, should be
|
||||
* - \ref USPI_INTEN_RXENDIEN_Msk
|
||||
* - \ref USPI_INTEN_RXSTIEN_Msk
|
||||
* - \ref USPI_INTEN_TXENDIEN_Msk
|
||||
* - \ref USPI_INTEN_TXSTIEN_Msk
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_DISABLE_TRANS_INT(uspi, u32IntSel) ( (uspi)->INTEN &= ~ (u32IntSel) )
|
||||
|
||||
/**
|
||||
* @brief Trigger RX PDMA function.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None.
|
||||
* @details Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_TRIGGER_RX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Trigger TX PDMA function.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None.
|
||||
* @details Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_TRIGGER_TX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Trigger TX and RX PDMA function.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None.
|
||||
* @details Set TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to enable TX and RX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_TRIGGER_TX_RX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_RXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable RX PDMA transfer.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None.
|
||||
* @details Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_DISABLE_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable TX PDMA transfer.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None.
|
||||
* @details Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable TX and RX PDMA transfer.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None.
|
||||
* @details Clear TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to disable TX and RX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define USPI_DISABLE_TX_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~(USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_RXPDMAEN_Msk))
|
||||
|
||||
uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
|
||||
void USPI_Close(USPI_T *uspi);
|
||||
void USPI_ClearRxBuf(USPI_T *uspi);
|
||||
void USPI_ClearTxBuf(USPI_T *uspi);
|
||||
void USPI_DisableAutoSS(USPI_T *uspi);
|
||||
void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
|
||||
uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock);
|
||||
uint32_t USPI_GetBusClock(USPI_T *uspi);
|
||||
void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask);
|
||||
void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask);
|
||||
uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask);
|
||||
void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask);
|
||||
uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask);
|
||||
void USPI_EnableWakeup(USPI_T *uspi);
|
||||
void USPI_DisableWakeup(USPI_T *uspi);
|
||||
|
||||
|
||||
/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group USCI_SPI_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __NU_USCI_SPI_H__ */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,523 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_usci_uart.h
|
||||
* @version V1.00
|
||||
* @brief M031 series USCI UART (UUART) driver header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_USCI_UART_H__
|
||||
#define __NU_USCI_UART_H__
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup USCI_UART_Driver USCI_UART Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UUART_LINECTL constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UUART_WORD_LEN_6 (6ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits \hideinitializer */
|
||||
#define UUART_WORD_LEN_7 (7ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits \hideinitializer */
|
||||
#define UUART_WORD_LEN_8 (8ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits \hideinitializer */
|
||||
#define UUART_WORD_LEN_9 (9ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UUART_PROTCTL constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UUART_PARITY_NONE (0x0ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as no parity \hideinitializer */
|
||||
#define UUART_PARITY_ODD (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as odd parity \hideinitializer */
|
||||
#define UUART_PARITY_EVEN (0x3ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as even parity \hideinitializer */
|
||||
|
||||
#define UUART_STOP_BIT_1 (0x0ul) /*!< UUART_PROTCTL setting for one stop bit \hideinitializer */
|
||||
#define UUART_STOP_BIT_2 (0x1ul) /*!< UUART_PROTCTL setting for two stop bit \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* USCI UART interrupt mask definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UUART_ABR_INT_MASK (0x002ul) /*!< Auto-baud rate interrupt mask \hideinitializer */
|
||||
#define UUART_RLS_INT_MASK (0x004ul) /*!< Receive line status interrupt mask \hideinitializer */
|
||||
#define UUART_BUF_RXOV_INT_MASK (0x008ul) /*!< Buffer RX overrun interrupt mask \hideinitializer */
|
||||
#define UUART_TXST_INT_MASK (0x010ul) /*!< TX start interrupt mask \hideinitializer */
|
||||
#define UUART_TXEND_INT_MASK (0x020ul) /*!< Tx end interrupt mask \hideinitializer */
|
||||
#define UUART_RXST_INT_MASK (0x040ul) /*!< RX start interrupt mask \hideinitializer */
|
||||
#define UUART_RXEND_INT_MASK (0x080ul) /*!< RX end interrupt mask \hideinitializer */
|
||||
|
||||
|
||||
/*@}*/ /* end of group USCI_UART_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write USCI_UART data
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
* @param[in] u8Data Data byte to transmit.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro write Data to Tx data register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_WRITE(uuart, u8Data) ((uuart)->TXDAT = (u8Data))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Read USCI_UART data
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
*
|
||||
* @return The oldest data byte in RX buffer.
|
||||
*
|
||||
* @details This macro read Rx data register.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_READ(uuart) ((uuart)->RXDAT)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Tx empty
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
*
|
||||
* @retval 0 Tx buffer is not empty
|
||||
* @retval >=1 Tx buffer is empty
|
||||
*
|
||||
* @details This macro get Transmitter buffer empty register value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_GET_TX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Rx empty
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
*
|
||||
* @retval 0 Rx buffer is not empty
|
||||
* @retval >=1 Rx buffer is empty
|
||||
*
|
||||
* @details This macro get Receiver buffer empty register value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_GET_RX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check specified usci_uart port transmission is over.
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
*
|
||||
* @retval 0 Tx transmission is not over
|
||||
* @retval 1 Tx transmission is over
|
||||
*
|
||||
* @details This macro return Transmitter Empty Flag register bit value. \n
|
||||
* It indicates if specified usci_uart port transmission is over nor not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_IS_TX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check specified usci_uart port receiver is empty.
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
*
|
||||
* @retval 0 Rx receiver is not empty
|
||||
* @retval 1 Rx receiver is empty
|
||||
*
|
||||
* @details This macro return Receive Empty Flag register bit value. \n
|
||||
* It indicates if specified usci_uart port receiver is empty nor not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_IS_RX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Wait specified usci_uart port transmission is over
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro wait specified usci_uart port transmission is over.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_WAIT_TX_EMPTY(uuart) while(!((((uuart)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check TX buffer is full or not
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
*
|
||||
* @retval 1 TX buffer is full
|
||||
* @retval 0 TX buffer is not full
|
||||
*
|
||||
* @details This macro check TX buffer is full or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_IS_TX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check RX buffer is full or not
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
*
|
||||
* @retval 1 RX buffer is full
|
||||
* @retval 0 RX buffer is not full
|
||||
*
|
||||
* @details This macro check RX buffer is full or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_IS_RX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Tx full register value
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
*
|
||||
* @retval 0 Tx buffer is not full.
|
||||
* @retval >=1 Tx buffer is full.
|
||||
*
|
||||
* @details This macro get Tx full register value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_GET_TX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Rx full register value
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
*
|
||||
* @retval 0 Rx buffer is not full.
|
||||
* @retval >=1 Rx buffer is full.
|
||||
*
|
||||
* @details This macro get Rx full register value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_GET_RX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable specified USCI_UART protocol interrupt
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
* @param[in] u32IntSel Interrupt type select
|
||||
* - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt
|
||||
* - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro enable specified USCI_UART protocol interrupt.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_ENABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN |= (u32IntSel))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable specified USCI_UART protocol interrupt
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
* @param[in] u32IntSel Interrupt type select
|
||||
* - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt
|
||||
* - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro disable specified USCI_UART protocol interrupt.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_DISABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN &= ~(u32IntSel))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable specified USCI_UART buffer interrupt
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
* @param[in] u32IntSel Interrupt type select
|
||||
* - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro enable specified USCI_UART buffer interrupt.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_ENABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL |= (u32IntSel))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable specified USCI_UART buffer interrupt
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
* @param[in] u32IntSel Interrupt type select
|
||||
* - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro disable specified USCI_UART buffer interrupt.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_DISABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL &= ~ (u32IntSel))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable specified USCI_UART transfer interrupt
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
* @param[in] u32IntSel Interrupt type select
|
||||
* - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt
|
||||
* - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt
|
||||
* - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt
|
||||
* - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro enable specified USCI_UART transfer interrupt.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_ENABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN |= (u32IntSel))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable specified USCI_UART transfer interrupt
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
* @param[in] u32IntSel Interrupt type select
|
||||
* - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt
|
||||
* - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt
|
||||
* - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt
|
||||
* - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro disable specified USCI_UART transfer interrupt.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_DISABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN &= ~(u32IntSel))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get protocol interrupt flag/status
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
*
|
||||
* @return The interrupt flag/status of protocol status register.
|
||||
*
|
||||
* @details This macro get protocol status register value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_GET_PROT_STATUS(uuart) ((uuart)->PROTSTS)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear specified protocol interrupt flag
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
|
||||
* - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator
|
||||
* - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag
|
||||
* - \ref UUART_PROTSTS_BREAK_Msk : Break Flag
|
||||
* - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag
|
||||
* - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag
|
||||
* - \ref UUART_PROTSTS_RXENDIF_Msk : Receive End Interrupt Flag
|
||||
* - \ref UUART_PROTSTS_RXSTIF_Msk : Receive Start Interrupt Flag
|
||||
* - \ref UUART_PROTSTS_TXENDIF_Msk : Transmit End Interrupt Flag
|
||||
* - \ref UUART_PROTSTS_TXSTIF_Msk : Transmit Start Interrupt Flag
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro clear specified protocol interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_CLR_PROT_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->PROTSTS = (u32IntTypeFlag))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get transmit/receive buffer interrupt flag/status
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
*
|
||||
* @return The interrupt flag/status of buffer status register.
|
||||
*
|
||||
* @details This macro get buffer status register value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_GET_BUF_STATUS(uuart) ((uuart)->BUFSTS)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear specified buffer interrupt flag
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
|
||||
* - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error Interrupt Indicator
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro clear specified buffer interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_CLR_BUF_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->BUFSTS = (u32IntTypeFlag))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get wakeup flag
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
*
|
||||
* @retval 0 Chip did not wake up from power-down mode.
|
||||
* @retval 1 Chip waked up from power-down mode.
|
||||
*
|
||||
* @details This macro get wakeup flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_GET_WAKEUP_FLAG(uuart) ((uuart)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 )
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear wakeup flag
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro clear wakeup flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_CLR_WAKEUP_FLAG(uuart) ((uuart)->WKSTS = UUART_WKSTS_WKF_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable specified USCI_UART PDMA function
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
* @param[in] u32FuncSel Combination of following functions
|
||||
* - \ref UUART_PDMACTL_TXPDMAEN_Msk
|
||||
* - \ref UUART_PDMACTL_RXPDMAEN_Msk
|
||||
* - \ref UUART_PDMACTL_PDMAEN_Msk
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_PDMA_ENABLE(uuart, u32FuncSel) ((uuart)->PDMACTL |= (u32FuncSel))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable specified USCI_UART PDMA function
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||
* @param[in] u32FuncSel Combination of following functions
|
||||
* - \ref UUART_PDMACTL_TXPDMAEN_Msk
|
||||
* - \ref UUART_PDMACTL_RXPDMAEN_Msk
|
||||
* - \ref UUART_PDMACTL_PDMAEN_Msk
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_PDMA_DISABLE(uuart, u32FuncSel) ((uuart)->PDMACTL &= ~(u32FuncSel))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Trigger RX PDMA function.
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @details Set RXPDMAEN bit of UUART_PDMACTL register to enable RX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_TRIGGER_RX_PDMA(uuart) ((uuart)->PDMACTL |= UUART_PDMACTL_RXPDMAEN_Msk|UUART_PDMACTL_PDMAEN_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Trigger TX PDMA function.
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @details Set TXPDMAEN bit of UUART_PDMACTL register to enable TX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_TRIGGER_TX_PDMA(uuart) ((uuart)->PDMACTL |= UUART_PDMACTL_TXPDMAEN_Msk|UUART_PDMACTL_PDMAEN_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable RX PDMA transfer.
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @details Clear RXPDMAEN bit of UUART_PDMACTL register to disable RX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_DISABLE_RX_PDMA(uuart) ( (uuart)->PDMACTL &= ~UUART_PDMACTL_RXPDMAEN_Msk )
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable TX PDMA transfer.
|
||||
*
|
||||
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @details Clear TXPDMAEN bit of UUART_PDMACTL register to disable TX PDMA transfer function.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define UUART_DISABLE_TX_PDMA(uuart) ( (uuart)->PDMACTL &= ~UUART_PDMACTL_TXPDMAEN_Msk )
|
||||
|
||||
|
||||
void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask);
|
||||
uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask);
|
||||
void UUART_Close(UUART_T* uuart);
|
||||
void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask);
|
||||
void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask);
|
||||
uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate);
|
||||
uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
|
||||
uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
|
||||
uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
|
||||
void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode);
|
||||
void UUART_DisableWakeup(UUART_T* uuart);
|
||||
void UUART_EnableFlowCtrl(UUART_T* uuart);
|
||||
void UUART_DisableFlowCtrl(UUART_T* uuart);
|
||||
|
||||
|
||||
/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group USCI_UART_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __NU_USCI_UART_H__ */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,220 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_wdt.h
|
||||
* @version V3.00
|
||||
* $Revision: 6 $
|
||||
* $Date: 18/06/08 11:34a $
|
||||
* @brief M031 series Watchdog Timer(WDT) driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_WDT_H__
|
||||
#define __NU_WDT_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup WDT_Driver WDT Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants
|
||||
@{
|
||||
*/
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* WDT Time-out Interval Period Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks \hideinitializer */
|
||||
#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks \hideinitializer */
|
||||
#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks \hideinitializer */
|
||||
#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks \hideinitializer */
|
||||
#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks \hideinitializer */
|
||||
#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks \hideinitializer */
|
||||
#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks \hideinitializer */
|
||||
#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks \hideinitializer */
|
||||
#define WDT_TIMEOUT_2POW20 (8UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^20 * WDT clocks \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* WDT Reset Delay Period Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks \hideinitializer */
|
||||
#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks \hideinitializer */
|
||||
#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks \hideinitializer */
|
||||
#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* WDT Free Reset Counter Keyword Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define WDT_RESET_COUNTER_KEYWORD (0x00005AA5UL) /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clear WDT Reset System Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro clears WDT time-out reset system flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Clear WDT Time-out Interrupt Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro clears WDT time-out interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Clear WDT Wake-up Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro clears WDT time-out wake-up system flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get WDT Time-out Reset Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 0 WDT time-out reset system did not occur
|
||||
* @retval 1 WDT time-out reset system occurred
|
||||
*
|
||||
* @details This macro indicates system has been reset by WDT time-out reset or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL)
|
||||
|
||||
/**
|
||||
* @brief Get WDT Time-out Interrupt Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 0 WDT time-out interrupt did not occur
|
||||
* @retval 1 WDT time-out interrupt occurred
|
||||
*
|
||||
* @details This macro indicates WDT time-out interrupt occurred or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL)
|
||||
|
||||
/**
|
||||
* @brief Get WDT Time-out Wake-up Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 0 WDT time-out interrupt does not cause CPU wake-up
|
||||
* @retval 1 WDT time-out interrupt event cause CPU wake-up
|
||||
*
|
||||
* @details This macro indicates WDT time-out interrupt event has waked up system or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL)
|
||||
|
||||
/**
|
||||
* @brief Reset WDT Counter
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to reset the internal 18-bit WDT up counter value.
|
||||
* @note If WDT is activated and time-out reset system function is enabled also, user should \n
|
||||
* reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n
|
||||
* reset system before the WDT time-out reset delay period expires.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_RESET_COUNTER() (WDT->RSTCNT = WDT_RESET_COUNTER_KEYWORD)
|
||||
|
||||
__STATIC_INLINE void WDT_Close(void);
|
||||
__STATIC_INLINE void WDT_EnableInt(void);
|
||||
__STATIC_INLINE void WDT_DisableInt(void);
|
||||
/**
|
||||
* @brief Stop WDT Counting
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function will stop WDT counting and disable WDT module.
|
||||
*/
|
||||
__STATIC_INLINE void WDT_Close(void)
|
||||
{
|
||||
WDT->CTL = 0UL;
|
||||
while(WDT->CTL & WDT_CTL_SYNC_Msk); // Wait disable WDTEN bit completed, it needs 2 * WDT_CLK.
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable WDT Time-out Interrupt
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function will enable the WDT time-out interrupt function.
|
||||
*/
|
||||
__STATIC_INLINE void WDT_EnableInt(void)
|
||||
{
|
||||
WDT->CTL |= WDT_CTL_INTEN_Msk;
|
||||
while(WDT->CTL & WDT_CTL_SYNC_Msk); // Wait enable WDTEN bit completed, it needs 2 * WDT_CLK.
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable WDT Time-out Interrupt
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function will disable the WDT time-out interrupt function.
|
||||
*/
|
||||
__STATIC_INLINE void WDT_DisableInt(void)
|
||||
{
|
||||
/* Do not touch another write 1 clear bits */
|
||||
WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup);
|
||||
|
||||
/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group WDT_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__NU_WDT_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,155 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file nu_wwdt.h
|
||||
* @version V3.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 18/06/07 9:48a $
|
||||
* @brief M031 series Window Watchdog Timet(WWDT) driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_WWDT_H__
|
||||
#define __NU_WWDT_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDT_Driver WWDT Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
|
||||
@{
|
||||
*/
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* WWDT Prescale Period Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* WWDT Reload Counter Keyword Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clear WWDT Reset System Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to clear WWDT time-out reset system flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Clear WWDT Compared Match Interrupt Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to clear WWDT compared match interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get WWDT Reset System Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 0 WWDT time-out reset system did not occur
|
||||
* @retval 1 WWDT time-out reset system occurred
|
||||
*
|
||||
* @details This macro is used to indicate system has been reset by WWDT time-out reset or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Get WWDT Compared Match Interrupt Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 0 WWDT compare match interrupt did not occur
|
||||
* @retval 1 WWDT compare match interrupt occurred
|
||||
*
|
||||
* @details This macro is used to indicate WWDT counter value matches CMPDAT value or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Get WWDT Counter
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return WWDT Counter Value
|
||||
*
|
||||
* @details This macro reflects the current WWDT counter value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_GET_COUNTER() (WWDT->CNT)
|
||||
|
||||
/**
|
||||
* @brief Reload WWDT Counter
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to reload the WWDT counter value to 0x3F.
|
||||
* @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n
|
||||
* between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n
|
||||
* WWDT reset signal will generate immediately to reset system.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)
|
||||
|
||||
void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
|
||||
|
||||
/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group WWDT_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__NU_WWDT_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,10 +0,0 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\libStdDriver.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
|
|
@ -1,513 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>libstddriver-m031</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pArmCC>5060750::V5.06 update 6 (build 750)::ARMCC</pArmCC>
|
||||
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>M032KIAAE</Device>
|
||||
<Vendor>Nuvoton</Vendor>
|
||||
<PackID>Nuvoton.NuMicro_DFP.1.3.10</PackID>
|
||||
<PackURL>http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x18000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M0") CLOCK(12000000)</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M031_AP_512 -FS00 -FL080000 -FP0($$Device:M032KIAAE$Flash\M031_AP_512.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:M032KIAAE$Device\M031\Include\M031Series.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:M032KIAAE$SVD\Nuvoton\M031AE_v1.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\keil5\</OutputDirectory>
|
||||
<OutputName>libstddriver_keil</OutputName>
|
||||
<CreateExecutable>0</CreateExecutable>
|
||||
<CreateLib>1</CreateLib>
|
||||
<CreateHexFile>1</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\build\keil5\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>1</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name>xcopy /y ".\build\keil5\@L.lib" "."</UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>1</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> </SimDllArguments>
|
||||
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM0</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments> </TargetDllArguments>
|
||||
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M0"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x18000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x18000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>0</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>5</v6Lang>
|
||||
<v6LangP>3</v6LangP>
|
||||
<vShortEn>0</vShortEn>
|
||||
<vShortWch>0</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>1</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\inc;..\..\CMSIS\Include;..\..\Device\Nuvoton\M031\Include;.</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>1</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>1</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>src</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>nu_acmp.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_acmp.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_adc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_adc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_bpwm.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_bpwm.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_clk.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_clk.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_crc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_crc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_ebi.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_ebi.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_fmc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_fmc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_gpio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_i2c.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_i2c.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_pdma.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_pdma.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_pwm.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_pwm.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_qspi.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_qspi.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_rtc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_rtc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_spi.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_spi.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_sys.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_sys.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_timer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_timer.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_uart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_uart.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_usbd.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_usbd.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_usci_i2c.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_usci_i2c.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_usci_spi.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_usci_spi.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_usci_uart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_usci_uart.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_wdt.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_wdt.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>nu_wwdt.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\src\nu_wwdt.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components/>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
/****************************************************************************
|
||||
* @file nutool_clkcfg.h
|
||||
* @version V1.05
|
||||
* @Date 2020/09/15-18:09:27
|
||||
* @brief NuMicro generated code file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __NUTOOL_CLKCFG_H__
|
||||
#define __NUTOOL_CLKCFG_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
#undef __HXT
|
||||
#define __HXT (32000000UL) /*!< High Speed External Crystal Clock Frequency */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /*__NUTOOL_CLKCFG_H__*/
|
||||
|
||||
/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file acmp.c
|
||||
* @version V3.00
|
||||
* $Revision: 3 $
|
||||
* $Date: 18/03/16 11:13a $
|
||||
* @brief M031 Series Analog Comparator(ACMP) Driver Source File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "M031Series.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup ACMP_Driver ACMP Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configure the specified ACMP module
|
||||
*
|
||||
* @param[in] Acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum Comparator number.
|
||||
* @param[in] u32NegSrc Comparator negative input selection. Including:
|
||||
* - \ref ACMP_CTL_NEGSEL_PIN
|
||||
* - \ref ACMP_CTL_NEGSEL_CRV
|
||||
* - \ref ACMP_CTL_NEGSEL_VBG
|
||||
* @param[in] u32HysteresisEn The hysteresis function option. Including:
|
||||
* - \ref ACMP_CTL_HYSTERESIS_ENABLE
|
||||
* - \ref ACMP_CTL_HYSTERESIS_DISABLE
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Configure hysteresis function, select the source of negative input and enable analog comparator.
|
||||
*/
|
||||
void ACMP_Open(ACMP_T *Acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn)
|
||||
{
|
||||
Acmp->CTL[u32ChNum] = (Acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSEN_Msk))) | (u32NegSrc | u32HysteresisEn | ACMP_CTL_ACMPEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Close analog comparator
|
||||
*
|
||||
* @param[in] Acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum Comparator number.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
|
||||
*/
|
||||
void ACMP_Close(ACMP_T *Acmp, uint32_t u32ChNum)
|
||||
{
|
||||
Acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group ACMP_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,200 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file adc.c
|
||||
* @version V3.00
|
||||
* $Revision: 7 $
|
||||
* $Date: 18/07/24 2:17p $
|
||||
* @brief M031 Series ADC Driver Source File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "M031Series.h"
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Driver ADC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_EXPORTED_FUNCTIONS ADC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This API configures ADC module to be ready for convert the input from selected channel
|
||||
* @param[in] adc The pointer of the specified ADC module
|
||||
* @param[in] u32InputMode Decides the ADC analog input mode. Valid values are:
|
||||
* - \ref ADC_ADCR_DIFFEN_SINGLE_END :Single-end input mode
|
||||
* - \ref ADC_ADCR_DIFFEN_DIFFERENTIAL :Differential input mode
|
||||
* @param[in] u32OpMode Decides the ADC operation mode. Valid values are:
|
||||
* - \ref ADC_ADCR_ADMD_SINGLE :Single mode.
|
||||
* - \ref ADC_ADCR_ADMD_BURST :Burst mode.
|
||||
* - \ref ADC_ADCR_ADMD_SINGLE_CYCLE :Single cycle scan mode.
|
||||
* - \ref ADC_ADCR_ADMD_CONTINUOUS :Continuous scan mode.
|
||||
* @param[in] u32ChMask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1..., bit 15 is channel 15.
|
||||
* @return None
|
||||
* @note M031 series MCU ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel
|
||||
* with smallest number will be convert.
|
||||
* @note This API does not turn on ADC power nor does trigger ADC conversion.
|
||||
* @note This API will reset and calibrate ADC if ADC never be calibrated after chip power on.
|
||||
*/
|
||||
void ADC_Open(ADC_T *adc,
|
||||
uint32_t u32InputMode,
|
||||
uint32_t u32OpMode,
|
||||
uint32_t u32ChMask)
|
||||
{
|
||||
/* Do calibration for ADC to decrease the effect of electrical random noise. */
|
||||
if ((adc->ADCALSTSR & ADC_ADCALSTSR_CALIF_Msk) == 0)
|
||||
{
|
||||
/* Must reset ADC before ADC calibration */
|
||||
adc->ADCR |= ADC_ADCR_RESET_Msk;
|
||||
while((adc->ADCR & ADC_ADCR_RESET_Msk) == ADC_ADCR_RESET_Msk);
|
||||
|
||||
adc->ADCALSTSR |= ADC_ADCALSTSR_CALIF_Msk; /* Clear Calibration Finish Interrupt Flag */
|
||||
adc->ADCALR |= ADC_ADCALR_CALEN_Msk; /* Enable Calibration function */
|
||||
ADC_START_CONV(adc); /* Start to calibration */
|
||||
while((adc->ADCALSTSR & ADC_ADCALSTSR_CALIF_Msk) != ADC_ADCALSTSR_CALIF_Msk); /* Wait calibration finish */
|
||||
}
|
||||
|
||||
adc->ADCR = (adc->ADCR & (~(ADC_ADCR_DIFFEN_Msk | ADC_ADCR_ADMD_Msk))) | \
|
||||
(u32InputMode) | \
|
||||
(u32OpMode);
|
||||
|
||||
adc->ADCHER = (adc->ADCHER & ~ADC_ADCHER_CHEN_Msk) | (u32ChMask);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ADC module
|
||||
* @param[in] adc The pointer of the specified ADC module
|
||||
* @return None
|
||||
*/
|
||||
void ADC_Close(ADC_T *adc)
|
||||
{
|
||||
SYS->IPRST1 |= SYS_IPRST1_ADCRST_Msk;
|
||||
SYS->IPRST1 &= ~SYS_IPRST1_ADCRST_Msk;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the hardware trigger condition and enable hardware trigger
|
||||
* @param[in] adc The pointer of the specified ADC module
|
||||
* @param[in] u32Source Decides the hardware trigger source. Valid values are:
|
||||
* - \ref ADC_ADCR_TRGS_STADC :A/D conversion is started by external STADC pin.
|
||||
* - \ref ADC_ADCR_TRGS_TIMER :A/D conversion is started by Timer.
|
||||
* - \ref ADC_ADCR_TRGS_PWM :A/D conversion is started by PWM.
|
||||
* @param[in] u32Param While ADC trigger by PWM or Timer, this parameter is unused.
|
||||
* While ADC trigger by external pin, this parameter is used to set trigger condition.
|
||||
* Valid values are:
|
||||
* - \ref ADC_ADCR_TRGCOND_LOW_LEVEL :STADC Low level active
|
||||
* - \ref ADC_ADCR_TRGCOND_HIGH_LEVEL :STADC High level active
|
||||
* - \ref ADC_ADCR_TRGCOND_FALLING_EDGE :STADC Falling edge active
|
||||
* - \ref ADC_ADCR_TRGCOND_RISING_EDGE :STADC Rising edge active
|
||||
* @return None
|
||||
* @note Software should disable TRGEN (ADCR[8]) and ADST (ADCR[11]) before change TRGS(ADCR[5:4]).
|
||||
*/
|
||||
void ADC_EnableHWTrigger(ADC_T *adc,
|
||||
uint32_t u32Source,
|
||||
uint32_t u32Param)
|
||||
{
|
||||
if(u32Source == ADC_ADCR_TRGS_STADC)
|
||||
{
|
||||
adc->ADCR = (adc->ADCR & ~(ADC_ADCR_TRGS_Msk | ADC_ADCR_TRGCOND_Msk | ADC_ADCR_TRGEN_Msk)) |
|
||||
((u32Source) | (u32Param) | ADC_ADCR_TRGEN_Msk);
|
||||
}
|
||||
else if(u32Source == ADC_ADCR_TRGS_TIMER)
|
||||
{
|
||||
adc->ADCR = (adc->ADCR & ~(ADC_ADCR_TRGS_Msk | ADC_ADCR_TRGCOND_Msk | ADC_ADCR_TRGEN_Msk)) |
|
||||
((u32Source) | ADC_ADCR_TRGEN_Msk);
|
||||
}
|
||||
else
|
||||
{
|
||||
adc->ADCR = (adc->ADCR & ~(ADC_ADCR_TRGS_Msk | ADC_ADCR_TRGCOND_Msk | ADC_ADCR_TRGEN_Msk)) |
|
||||
((u32Source) | ADC_ADCR_TRGEN_Msk);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable hardware trigger ADC function.
|
||||
* @param[in] adc The pointer of the specified ADC module
|
||||
* @return None
|
||||
*/
|
||||
void ADC_DisableHWTrigger(ADC_T *adc)
|
||||
{
|
||||
adc->ADCR &= ~(ADC_ADCR_TRGS_Msk | ADC_ADCR_TRGCOND_Msk | ADC_ADCR_TRGEN_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the interrupt(s) selected by u32Mask parameter.
|
||||
* @param[in] adc The pointer of the specified ADC module
|
||||
* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
|
||||
* corresponds to a interrupt status. This parameter decides which
|
||||
* interrupts will be enabled.
|
||||
* - \ref ADC_ADF_INT :ADC convert complete interrupt
|
||||
* - \ref ADC_CMP0_INT :ADC comparator 0 interrupt
|
||||
* - \ref ADC_CMP1_INT :ADC comparator 1 interrupt
|
||||
* @return None
|
||||
*/
|
||||
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
|
||||
{
|
||||
if((u32Mask) & ADC_ADF_INT)
|
||||
adc->ADCR |= ADC_ADCR_ADIE_Msk;
|
||||
if((u32Mask) & ADC_CMP0_INT)
|
||||
adc->ADCMPR[0] |= ADC_ADCMPR_CMPIE_Msk;
|
||||
if((u32Mask) & ADC_CMP1_INT)
|
||||
adc->ADCMPR[1] |= ADC_ADCMPR_CMPIE_Msk;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the interrupt(s) selected by u32Mask parameter.
|
||||
* @param[in] adc The pointer of the specified ADC module
|
||||
* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
|
||||
* corresponds to a interrupt status. This parameter decides which
|
||||
* interrupts will be disabled.
|
||||
* - \ref ADC_ADF_INT :ADC convert complete interrupt
|
||||
* - \ref ADC_CMP0_INT :ADC comparator 0 interrupt
|
||||
* - \ref ADC_CMP1_INT :ADC comparator 1 interrupt
|
||||
* @return None
|
||||
*/
|
||||
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
|
||||
{
|
||||
if((u32Mask) & ADC_ADF_INT)
|
||||
adc->ADCR &= ~ADC_ADCR_ADIE_Msk;
|
||||
if((u32Mask) & ADC_CMP0_INT)
|
||||
adc->ADCMPR[0] &= ~ADC_ADCMPR_CMPIE_Msk;
|
||||
if((u32Mask) & ADC_CMP1_INT)
|
||||
adc->ADCMPR[1] &= ~ADC_ADCMPR_CMPIE_Msk;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set ADC extend sample time.
|
||||
* @param[in] adc The pointer of the specified ADC module.
|
||||
* @param[in] u32ModuleNum Decides the sample module number, valid value are 0.
|
||||
* @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF.
|
||||
* @return None
|
||||
* @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy,
|
||||
* user can extend A/D sampling time after trigger source is coming to get enough sampling time.
|
||||
*/
|
||||
void ADC_SetExtendSampleTime(ADC_T *adc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
|
||||
{
|
||||
adc->ESMPCTL = (adc->ESMPCTL & ~ADC_ESMPCTL_EXTSMPT_Msk) |
|
||||
(u32ExtendSampleTime << ADC_ESMPCTL_EXTSMPT_Pos);
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group ADC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group ADC_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,751 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file bpwm.c
|
||||
* @version V1.00
|
||||
* $Revision: 4 $
|
||||
* $Date: 18/04/24 3:49p $
|
||||
* @brief M031 series BPWM driver source file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "NuMicro.h"
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup BPWM_Driver BPWM Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure BPWM capture and get the nearest unit time.
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32UnitTimeNsec The unit time of counter
|
||||
* @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
|
||||
* @return The nearest unit time in nano second.
|
||||
* @details This function is used to Configure BPWM capture and get the nearest unit time.
|
||||
*/
|
||||
uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
|
||||
{
|
||||
uint32_t u32Src;
|
||||
uint32_t u32BPWMClockSrc;
|
||||
uint32_t u32NearestUnitTimeNsec;
|
||||
uint16_t u16Prescale = 1UL, u16CNR = 0xFFFFUL;
|
||||
uint8_t u8BreakLoop = 0UL;
|
||||
|
||||
if (bpwm == BPWM0)
|
||||
{
|
||||
u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk;
|
||||
}
|
||||
else /* (bpwm == BPWM1) */
|
||||
{
|
||||
u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk;
|
||||
}
|
||||
|
||||
if (u32Src == 0UL)
|
||||
{
|
||||
//clock source is from PLL clock
|
||||
u32BPWMClockSrc = CLK_GetPLLClockFreq();
|
||||
}
|
||||
else
|
||||
{
|
||||
//clock source is from PCLK
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
if (bpwm == BPWM0)
|
||||
{
|
||||
u32BPWMClockSrc = CLK_GetPCLK0Freq();
|
||||
}
|
||||
else /* (bpwm == BPWM1) */
|
||||
{
|
||||
u32BPWMClockSrc = CLK_GetPCLK1Freq();
|
||||
}
|
||||
}
|
||||
|
||||
u32BPWMClockSrc /= 1000UL;
|
||||
|
||||
for (u16Prescale = 1UL; u16Prescale <= 0x1000UL; u16Prescale++)
|
||||
{
|
||||
u32NearestUnitTimeNsec = (1000000UL * u16Prescale) / u32BPWMClockSrc;
|
||||
|
||||
if (u32NearestUnitTimeNsec < u32UnitTimeNsec)
|
||||
{
|
||||
if (u16Prescale == 0x1000UL)
|
||||
{
|
||||
/* limit to the maximum unit time(nano second) */
|
||||
u8BreakLoop = 1UL;
|
||||
}
|
||||
|
||||
if (!((1000000UL * (u16Prescale + 1UL) > (u32NearestUnitTimeNsec * u32BPWMClockSrc))))
|
||||
{
|
||||
u8BreakLoop = 1UL;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
u8BreakLoop = 1UL;
|
||||
}
|
||||
|
||||
if (u8BreakLoop)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// convert to real register value
|
||||
u16Prescale = u16Prescale - 1UL;
|
||||
// all channels share a prescaler
|
||||
BPWM_SET_PRESCALER(bpwm, u32ChannelNum, (uint32_t)u16Prescale);
|
||||
|
||||
// set BPWM to down count type(edge aligned)
|
||||
(bpwm)->CTL1 = BPWM_DOWN_COUNTER;
|
||||
|
||||
BPWM_SET_CNR(bpwm, u32ChannelNum, u16CNR);
|
||||
|
||||
return (u32NearestUnitTimeNsec);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function Configure BPWM generator and get the nearest frequency in edge aligned(down countertype) auto-reload mode
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Frequency Target generator frequency
|
||||
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
|
||||
* @return Nearest frequency clock in nano second
|
||||
* @note Since all channels shares a prescaler. Call this API to configure BPWM frequency may affect
|
||||
* existing frequency of other channel.
|
||||
*/
|
||||
uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
|
||||
{
|
||||
uint32_t u32Src;
|
||||
uint32_t u32BPWMClockSrc;
|
||||
uint32_t i;
|
||||
uint16_t u16Prescale = 1UL, u16CNR = 0xFFFFUL;
|
||||
|
||||
if (bpwm == BPWM0)
|
||||
{
|
||||
u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk;
|
||||
}
|
||||
else /* (bpwm == BPWM1) */
|
||||
{
|
||||
u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk;
|
||||
}
|
||||
|
||||
if (u32Src == 0UL)
|
||||
{
|
||||
//clock source is from PLL clock
|
||||
u32BPWMClockSrc = CLK_GetPLLClockFreq();
|
||||
}
|
||||
else
|
||||
{
|
||||
//clock source is from PCLK
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
if (bpwm == BPWM0)
|
||||
{
|
||||
u32BPWMClockSrc = CLK_GetPCLK0Freq();
|
||||
}
|
||||
else /* (bpwm == BPWM1) */
|
||||
{
|
||||
u32BPWMClockSrc = CLK_GetPCLK1Freq();
|
||||
}
|
||||
}
|
||||
|
||||
for (u16Prescale = 1UL; u16Prescale < 0xFFFUL; u16Prescale++) //prescale could be 0~0xFFF
|
||||
{
|
||||
i = (u32BPWMClockSrc / u32Frequency) / u16Prescale;
|
||||
|
||||
// If target value is larger than CNR, need to use a larger prescaler
|
||||
if (i <= (0x10000UL))
|
||||
{
|
||||
u16CNR = (uint16_t)i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register
|
||||
i = u32BPWMClockSrc / ((uint32_t)u16Prescale * (uint32_t)u16CNR);
|
||||
|
||||
// convert to real register value
|
||||
u16Prescale = u16Prescale - 1UL;
|
||||
// all channels share a prescaler
|
||||
BPWM_SET_PRESCALER(bpwm, u32ChannelNum, (uint32_t)u16Prescale);
|
||||
// set BPWM to down count type
|
||||
(bpwm)->CTL1 = BPWM_DOWN_COUNTER;
|
||||
|
||||
u16CNR = u16CNR - 1UL;
|
||||
BPWM_SET_CNR(bpwm, u32ChannelNum, u16CNR);
|
||||
|
||||
if (u32DutyCycle)
|
||||
{
|
||||
if (u32DutyCycle >= 100UL)
|
||||
BPWM_SET_CMR(bpwm, u32ChannelNum, u16CNR);
|
||||
else
|
||||
BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1UL) / 100UL);
|
||||
|
||||
(bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1UL));
|
||||
(bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << ((u32ChannelNum << 1UL) + BPWM_WGCTL0_PRDPCTL0_Pos));
|
||||
(bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1UL));
|
||||
(bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << ((u32ChannelNum << 1UL) + BPWM_WGCTL1_CMPDCTL0_Pos));
|
||||
}
|
||||
else
|
||||
{
|
||||
BPWM_SET_CMR(bpwm, u32ChannelNum, 0UL);
|
||||
(bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1UL));
|
||||
(bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << ((u32ChannelNum << 1UL) + BPWM_WGCTL0_ZPCTL0_Pos));
|
||||
(bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1UL));
|
||||
(bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << ((u32ChannelNum << 1UL) + BPWM_WGCTL1_CMPDCTL0_Pos));
|
||||
}
|
||||
|
||||
return (i);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start BPWM module
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
|
||||
* @return None
|
||||
* @details This function is used to start BPWM module.
|
||||
* @note All channels share one counter.
|
||||
*/
|
||||
void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask)
|
||||
{
|
||||
(bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop BPWM module
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
|
||||
* @return None
|
||||
* @details This function is used to stop BPWM module.
|
||||
* @note All channels share one period.
|
||||
*/
|
||||
void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask)
|
||||
{
|
||||
(bpwm)->PERIOD = 0UL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop BPWM generation immediately by clear channel enable bit
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
|
||||
* @return None
|
||||
* @details This function is used to stop BPWM generation immediately by clear channel enable bit.
|
||||
* @note All channels share one counter.
|
||||
*/
|
||||
void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask)
|
||||
{
|
||||
(bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable selected channel to trigger ADC
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
|
||||
* - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_POINT
|
||||
* - \ref BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT
|
||||
* - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT
|
||||
* - \ref BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT
|
||||
* - \ref BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT
|
||||
* - \ref BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT
|
||||
* - \ref BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT
|
||||
* @return None
|
||||
* @details This function is used to enable selected channel to trigger ADC
|
||||
*/
|
||||
void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
|
||||
{
|
||||
if (u32ChannelNum < 4UL)
|
||||
{
|
||||
(bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3UL));
|
||||
(bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
(bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4UL) << 3UL));
|
||||
(bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4UL) << 3UL));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable selected channel to trigger ADC
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
* @details This function is used to disable selected channel to trigger ADC
|
||||
*/
|
||||
void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
if (u32ChannelNum < 4UL)
|
||||
{
|
||||
(bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
(bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4UL) << 3UL));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear selected channel trigger ADC flag
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Condition This parameter is not used
|
||||
* @return None
|
||||
* @details This function is used to clear selected channel trigger ADC flag
|
||||
*/
|
||||
void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
|
||||
{
|
||||
(bpwm)->STATUS = (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get selected channel trigger ADC flag
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @retval 0 The specified channel trigger ADC to start of conversion flag is not set
|
||||
* @retval 1 The specified channel trigger ADC to start of conversion flag is set
|
||||
* @details This function is used to get BPWM trigger ADC to start of conversion flag for specified channel
|
||||
*/
|
||||
uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable capture of selected channel(s)
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
|
||||
* Bit 0 is channel 0, bit 1 is channel 1...
|
||||
* @return None
|
||||
* @details This function is used to enable capture of selected channel(s)
|
||||
*/
|
||||
void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
|
||||
{
|
||||
(bpwm)->CAPINEN |= u32ChannelMask;
|
||||
(bpwm)->CAPCTL |= u32ChannelMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable capture of selected channel(s)
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
|
||||
* Bit 0 is channel 0, bit 1 is channel 1...
|
||||
* @return None
|
||||
* @details This function is used to disable capture of selected channel(s)
|
||||
*/
|
||||
void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
|
||||
{
|
||||
(bpwm)->CAPINEN &= ~u32ChannelMask;
|
||||
(bpwm)->CAPCTL &= ~u32ChannelMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables BPWM output generation of selected channel(s)
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
|
||||
* Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
|
||||
* @return None
|
||||
* @details This function is used to enables BPWM output generation of selected channel(s)
|
||||
*/
|
||||
void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
|
||||
{
|
||||
(bpwm)->POEN |= u32ChannelMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables BPWM output generation of selected channel(s)
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
|
||||
* @return None
|
||||
* @details This function is used to disables BPWM output generation of selected channel(s)
|
||||
*/
|
||||
void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
|
||||
{
|
||||
(bpwm)->POEN &= ~u32ChannelMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable capture interrupt of selected channel.
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Edge Rising or falling edge to latch counter.
|
||||
* - \ref BPWM_CAPTURE_INT_RISING_LATCH
|
||||
* - \ref BPWM_CAPTURE_INT_FALLING_LATCH
|
||||
* @return None
|
||||
* @details This function is used to enable capture interrupt of selected channel.
|
||||
*/
|
||||
void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
|
||||
{
|
||||
(bpwm)->CAPIEN |= (u32Edge << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable capture interrupt of selected channel.
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Edge Rising or falling edge to latch counter.
|
||||
* - \ref BPWM_CAPTURE_INT_RISING_LATCH
|
||||
* - \ref BPWM_CAPTURE_INT_FALLING_LATCH
|
||||
* @return None
|
||||
* @details This function is used to disable capture interrupt of selected channel.
|
||||
*/
|
||||
void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
|
||||
{
|
||||
(bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear capture interrupt of selected channel.
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Edge Rising or falling edge to latch counter.
|
||||
* - \ref BPWM_CAPTURE_INT_RISING_LATCH
|
||||
* - \ref BPWM_CAPTURE_INT_FALLING_LATCH
|
||||
* @return None
|
||||
* @details This function is used to clear capture interrupt of selected channel.
|
||||
*/
|
||||
void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
|
||||
{
|
||||
(bpwm)->CAPIF = (u32Edge << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get capture interrupt of selected channel.
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @retval 0 No capture interrupt
|
||||
* @retval 1 Rising edge latch interrupt
|
||||
* @retval 2 Falling edge latch interrupt
|
||||
* @retval 3 Rising and falling latch interrupt
|
||||
* @details This function is used to get capture interrupt of selected channel.
|
||||
*/
|
||||
uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
return (((((bpwm)->CAPIF & (BPWM_CAPIF_CAPFIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1UL) | \
|
||||
(((bpwm)->CAPIF & (BPWM_CAPIF_CAPRIF0_Msk << u32ChannelNum)) ? 1UL : 0UL));
|
||||
}
|
||||
/**
|
||||
* @brief Enable duty interrupt of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32IntDutyType Duty interrupt type, could be either
|
||||
* - \ref BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
|
||||
* - \ref BPWM_DUTY_INT_UP_COUNT_MATCH_CMP
|
||||
* @return None
|
||||
* @details This function is used to enable duty interrupt of selected channel.
|
||||
*/
|
||||
void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
|
||||
{
|
||||
(bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable duty interrupt of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
* @details This function is used to disable duty interrupt of selected channel
|
||||
*/
|
||||
void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
(bpwm)->INTEN &= ~((uint32_t)(BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear duty interrupt flag of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
* @details This function is used to clear duty interrupt flag of selected channel
|
||||
*/
|
||||
void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
(bpwm)->INTSTS = (BPWM_INTSTS_CMPUIF0_Msk | BPWM_INTSTS_CMPDIF0_Msk) << u32ChannelNum;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get duty interrupt flag of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @return Duty interrupt flag of specified channel
|
||||
* @retval 0 Duty interrupt did not occur
|
||||
* @retval 1 Duty interrupt occurred
|
||||
* @details This function is used to get duty interrupt flag of selected channel
|
||||
*/
|
||||
uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
return ((((bpwm)->INTSTS & ((BPWM_INTSTS_CMPDIF0_Msk | BPWM_INTSTS_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable period interrupt of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||
* @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.
|
||||
* @return None
|
||||
* @details This function is used to enable period interrupt of selected channel.
|
||||
* @note All channels share channel 0's setting.
|
||||
*/
|
||||
void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
|
||||
{
|
||||
(bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable period interrupt of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||
* @return None
|
||||
* @details This function is used to disable period interrupt of selected channel.
|
||||
* @note All channels share channel 0's setting.
|
||||
*/
|
||||
void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
(bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear period interrupt of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||
* @return None
|
||||
* @details This function is used to clear period interrupt of selected channel
|
||||
* @note All channels share channel 0's setting.
|
||||
*/
|
||||
void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
(bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get period interrupt of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||
* @return Period interrupt flag of specified channel
|
||||
* @retval 0 Period interrupt did not occur
|
||||
* @retval 1 Period interrupt occurred
|
||||
* @details This function is used to get period interrupt of selected channel
|
||||
* @note All channels share channel 0's setting.
|
||||
*/
|
||||
uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable zero interrupt of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||
* @return None
|
||||
* @details This function is used to enable zero interrupt of selected channel.
|
||||
* @note All channels share channel 0's setting.
|
||||
*/
|
||||
void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
(bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable zero interrupt of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||
* @return None
|
||||
* @details This function is used to disable zero interrupt of selected channel.
|
||||
* @note All channels share channel 0's setting.
|
||||
*/
|
||||
void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
(bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear zero interrupt of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||
* @return None
|
||||
* @details This function is used to clear zero interrupt of selected channel.
|
||||
* @note All channels share channel 0's setting.
|
||||
*/
|
||||
void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
(bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get zero interrupt of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||
* @return zero interrupt flag of specified channel
|
||||
* @retval 0 zero interrupt did not occur
|
||||
* @retval 1 zero interrupt occurred
|
||||
* @details This function is used to get zero interrupt of selected channel.
|
||||
* @note All channels share channel 0's setting.
|
||||
*/
|
||||
uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable load mode of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32LoadMode BPWM counter loading mode.
|
||||
* - \ref BPWM_LOAD_MODE_IMMEDIATE
|
||||
* - \ref BPWM_LOAD_MODE_CENTER
|
||||
* @return None
|
||||
* @details This function is used to enable load mode of selected channel.
|
||||
*/
|
||||
void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
|
||||
{
|
||||
(bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable load mode of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32LoadMode BPWM counter loading mode.
|
||||
* - \ref BPWM_LOAD_MODE_IMMEDIATE
|
||||
* - \ref BPWM_LOAD_MODE_CENTER
|
||||
* @return None
|
||||
* @details This function is used to disable load mode of selected channel.
|
||||
*/
|
||||
void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
|
||||
{
|
||||
(bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set BPWM clock source
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||
* @param[in] u32ClkSrcSel BPWM external clock source.
|
||||
* - \ref BPWM_CLKSRC_BPWM_CLK
|
||||
* - \ref BPWM_CLKSRC_TIMER0
|
||||
* - \ref BPWM_CLKSRC_TIMER1
|
||||
* - \ref BPWM_CLKSRC_TIMER2
|
||||
* - \ref BPWM_CLKSRC_TIMER3
|
||||
* @return None
|
||||
* @details This function is used to set BPWM clock source.
|
||||
* @note All channels share channel 0's setting.
|
||||
*/
|
||||
void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
|
||||
{
|
||||
(bpwm)->CLKSRC = (u32ClkSrcSel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the time-base counter reached its maximum value flag of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||
* @return Count to max interrupt flag of specified channel
|
||||
* @retval 0 Count to max interrupt did not occur
|
||||
* @retval 1 Count to max interrupt occurred
|
||||
* @details This function is used to get the time-base counter reached its maximum value flag of selected channel.
|
||||
* @note All channels share channel 0's setting.
|
||||
*/
|
||||
uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the time-base counter reached its maximum value flag of selected channel
|
||||
* @param[in] bpwm The pointer of the specified BPWM module
|
||||
* - BPWM0 : BPWM Group 0
|
||||
* - BPWM1 : BPWM Group 1
|
||||
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||
* @return None
|
||||
* @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.
|
||||
* @note All channels share channel 0's setting.
|
||||
*/
|
||||
void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
(bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk;
|
||||
}
|
||||
|
||||
|
||||
/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group BPWM_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,836 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file clk.c
|
||||
* @version V3.00
|
||||
* $Revision: 6 $
|
||||
* $Date: 18/07/05 4:42p $
|
||||
* @brief M031 Series Clock Controller (CLK) Driver Source File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "M031Series.h"
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup CLK_Driver CLK Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Disable frequency output function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function disable frequency output function.
|
||||
*/
|
||||
void CLK_DisableCKO(void)
|
||||
{
|
||||
/* Disable CKO clock source */
|
||||
CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enable frequency output function and
|
||||
* configure frequency clock source and divider.
|
||||
* @param[in] u32ClkSrc is frequency output function clock source. Including :
|
||||
* - \ref CLK_CLKSEL1_CLKOSEL_HXT
|
||||
* - \ref CLK_CLKSEL1_CLKOSEL_LXT
|
||||
* - \ref CLK_CLKSEL1_CLKOSEL_HCLK
|
||||
* - \ref CLK_CLKSEL1_CLKOSEL_HIRC
|
||||
* - \ref CLK_CLKSEL1_CLKOSEL_LIRC
|
||||
* - \ref CLK_CLKSEL1_CLKOSEL_PLL
|
||||
* - \ref CLK_CLKSEL1_CLKOSEL_SOF
|
||||
* @param[in] u32ClkDiv is divider selection for output frequency.
|
||||
* @param[in] u32ClkDivBy1En is frequency divided by one enable.
|
||||
* @return None
|
||||
*
|
||||
* @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv.
|
||||
* The formula is:
|
||||
* CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1)
|
||||
* This function is just used to set CKO clock.
|
||||
* User must enable I/O for CKO clock output pin by themselves.
|
||||
*/
|
||||
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
|
||||
{
|
||||
/* CKO = clock source / 2^(u32ClkDiv + 1) */
|
||||
CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
|
||||
|
||||
/* Enable CKO clock source */
|
||||
CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk;
|
||||
|
||||
/* Select CKO clock source */
|
||||
CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | (u32ClkSrc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enter to Power-down mode
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is used to let system enter to Power-down mode. \n
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
* @note Must be care of HIRC/MIRC auto trim is disabled when using this function.
|
||||
*/
|
||||
void CLK_PowerDown(void)
|
||||
{
|
||||
volatile uint32_t u32SysTickTICKINT = 0; /* Backup Systick interrupt enable bit */
|
||||
|
||||
/* Check HIRC/MIRC auto trim function disable */
|
||||
if(SYS->HIRCTRIMCTL & SYS_HIRCTRIMCTL_FREQSEL_Msk)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set the processor uses deep sleep as its low power mode */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Set system Power-down enabled */
|
||||
CLK->PWRCTL |= CLK_PWRCTL_PDEN_Msk;
|
||||
|
||||
/* Backup systick interrupt setting */
|
||||
u32SysTickTICKINT = SysTick->CTRL & SysTick_CTRL_TICKINT_Msk;
|
||||
|
||||
/* Disable systick interrupt */
|
||||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
|
||||
|
||||
/* Chip enter Power-down mode after CPU run WFI instruction */
|
||||
__WFI();
|
||||
|
||||
/* Restore systick interrupt setting */
|
||||
if(u32SysTickTICKINT) SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enter to Idle mode
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function let system enter to Idle mode. \n
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
void CLK_Idle(void)
|
||||
{
|
||||
/* Set the processor uses sleep as its low power mode */
|
||||
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Set chip in idle mode because of WFI command */
|
||||
CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
|
||||
|
||||
/* Chip enter idle mode after CPU run WFI instruction */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get external high speed crystal clock frequency
|
||||
* @param None
|
||||
* @return External high frequency crystal frequency
|
||||
* @details This function get external high frequency crystal frequency. The frequency unit is Hz.
|
||||
*/
|
||||
uint32_t CLK_GetHXTFreq(void)
|
||||
{
|
||||
if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk)
|
||||
return __HXT;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get external low speed crystal clock frequency
|
||||
* @param None
|
||||
* @return External low speed crystal clock frequency
|
||||
* @details This function get external low frequency crystal frequency. The frequency unit is Hz.
|
||||
*/
|
||||
uint32_t CLK_GetLXTFreq(void)
|
||||
{
|
||||
if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk)
|
||||
return __LXT;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get PCLK0 frequency
|
||||
* @param None
|
||||
* @return PCLK0 frequency
|
||||
* @details This function get PCLK0 frequency. The frequency unit is Hz.
|
||||
*/
|
||||
uint32_t CLK_GetPCLK0Freq(void)
|
||||
{
|
||||
uint32_t PCLK0Div;
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
PCLK0Div = (CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) >> CLK_PCLKDIV_APB0DIV_Pos;
|
||||
return (SystemCoreClock >> PCLK0Div);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get PCLK1 frequency
|
||||
* @param None
|
||||
* @return PCLK1 frequency
|
||||
* @details This function get PCLK1 frequency. The frequency unit is Hz.
|
||||
*/
|
||||
uint32_t CLK_GetPCLK1Freq(void)
|
||||
{
|
||||
uint32_t PCLK1Div;
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
PCLK1Div = (CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) >> CLK_PCLKDIV_APB1DIV_Pos;
|
||||
return (SystemCoreClock >> PCLK1Div);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get HCLK frequency
|
||||
* @param None
|
||||
* @return HCLK frequency
|
||||
* @details This function get HCLK frequency. The frequency unit is Hz.
|
||||
*/
|
||||
uint32_t CLK_GetHCLKFreq(void)
|
||||
{
|
||||
SystemCoreClockUpdate();
|
||||
return SystemCoreClock;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CPU frequency
|
||||
* @param None
|
||||
* @return CPU frequency
|
||||
* @details This function get CPU frequency. The frequency unit is Hz.
|
||||
*/
|
||||
uint32_t CLK_GetCPUFreq(void)
|
||||
{
|
||||
SystemCoreClockUpdate();
|
||||
return SystemCoreClock;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set HCLK frequency
|
||||
* @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is 25.5MHz ~ 48MHz.
|
||||
* NOTE: For M031_G/I, the HCLK frequency up to 72MHz.
|
||||
* @return HCLK frequency
|
||||
* @details This function is used to set HCLK frequency. The frequency unit is Hz. \n
|
||||
* It would configure PLL frequency to 51MHz ~ 96MHz,
|
||||
* set HCLK clock divider as 2 and switch HCLK clock source to PLL. \n
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
* NOTE: For M031_G/I, the PLL frequency up to 144MHz.
|
||||
*/
|
||||
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
|
||||
{
|
||||
uint32_t u32HIRCSTB;
|
||||
uint32_t u32HCLK_UpperLimit;
|
||||
|
||||
/* Read HIRC clock source stable flag */
|
||||
u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
|
||||
|
||||
/* The range of u32Hclk is 25.5 MHz ~ 48 MHz or 72 MHz */
|
||||
if ((GET_CHIP_SERIES_NUM == CHIP_SERIES_NUM_G) || (GET_CHIP_SERIES_NUM == CHIP_SERIES_NUM_I))
|
||||
u32HCLK_UpperLimit = FREQ_72MHZ;
|
||||
else
|
||||
u32HCLK_UpperLimit = FREQ_48MHZ;
|
||||
|
||||
if(u32Hclk > u32HCLK_UpperLimit)
|
||||
u32Hclk = u32HCLK_UpperLimit;
|
||||
if(u32Hclk < (FREQ_51MHZ >> 1))
|
||||
u32Hclk = (FREQ_51MHZ >> 1);
|
||||
|
||||
/* Switch HCLK clock source to HIRC clock for safe */
|
||||
CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
|
||||
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
|
||||
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
|
||||
CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
|
||||
|
||||
/* Configure PLL setting if HXT clock is stable */
|
||||
if(CLK->STATUS & CLK_STATUS_HXTSTB_Msk)
|
||||
u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, (u32Hclk << 1));
|
||||
|
||||
/* Configure PLL setting if HXT clock is not stable */
|
||||
else
|
||||
{
|
||||
u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC_DIV4, (u32Hclk << 1));
|
||||
|
||||
/* Read HIRC clock source stable flag */
|
||||
u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
|
||||
}
|
||||
|
||||
/* Select HCLK clock source to PLL,
|
||||
Select HCLK clock source divider as 2
|
||||
and update system core clock
|
||||
*/
|
||||
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(2));
|
||||
|
||||
/* Disable HIRC if HIRC is disabled before setting core clock */
|
||||
if(u32HIRCSTB == 0)
|
||||
CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
|
||||
|
||||
/* Return actually HCLK frequency is PLL frequency divide 2 */
|
||||
return u32Hclk >> 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set HCLK clock source and HCLK clock divider
|
||||
* @param[in] u32ClkSrc is HCLK clock source. Including :
|
||||
* - \ref CLK_CLKSEL0_HCLKSEL_HXT
|
||||
* - \ref CLK_CLKSEL0_HCLKSEL_LXT
|
||||
* - \ref CLK_CLKSEL0_HCLKSEL_PLL
|
||||
* - \ref CLK_CLKSEL0_HCLKSEL_LIRC
|
||||
* - \ref CLK_CLKSEL0_HCLKSEL_HIRC
|
||||
* @param[in] u32ClkDiv is HCLK clock divider. Including :
|
||||
* - \ref CLK_CLKDIV0_HCLK(x)
|
||||
* @return None
|
||||
* @details This function set HCLK clock source and HCLK clock divider. The HCLK clock divider is set by CLK_CLKDIV0_HCLK(x) where x = 1~16.
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
|
||||
{
|
||||
uint32_t u32HIRCSTB;
|
||||
|
||||
/* Read HIRC clock source stable flag */
|
||||
u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
|
||||
|
||||
/* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
|
||||
CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
|
||||
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
|
||||
CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
|
||||
|
||||
/* Apply new Divider */
|
||||
CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
|
||||
|
||||
/* Switch HCLK to new HCLK source */
|
||||
CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
|
||||
|
||||
/* Update System Core Clock */
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
/* Disable HIRC if HIRC is disabled before switching HCLK source */
|
||||
if(u32HIRCSTB == 0)
|
||||
CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function set selected module clock source and module clock divider
|
||||
* @param[in] u32ModuleIdx is module index.
|
||||
* @param[in] u32ClkSrc is module clock source.
|
||||
* @param[in] u32ClkDiv is module clock divider.
|
||||
* @return None
|
||||
* @details Valid parameter combinations listed in following table:
|
||||
*
|
||||
* |Module index |Clock source |Divider |
|
||||
* | :---------------- | :----------------------------------- | :----------------------- |
|
||||
* |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBDSEL_HIRC |\ref CLK_CLKDIV0_USB(x) |
|
||||
* |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBDSEL_PLL |\ref CLK_CLKDIV0_USB(x) |
|
||||
* |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x |
|
||||
* |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x |
|
||||
* |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x |
|
||||
* |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x |
|
||||
* |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x |
|
||||
* |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x |
|
||||
* |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x |
|
||||
* |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x |
|
||||
* |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x |
|
||||
* |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LIRC | x |
|
||||
* |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_PLL | x |
|
||||
* |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_SOF | x |
|
||||
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x |
|
||||
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x |
|
||||
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x |
|
||||
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT_TRG | x |
|
||||
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x |
|
||||
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x |
|
||||
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x |
|
||||
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x |
|
||||
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x |
|
||||
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT_TRG | x |
|
||||
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x |
|
||||
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x |
|
||||
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x |
|
||||
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x |
|
||||
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x |
|
||||
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT_TRG | x |
|
||||
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x |
|
||||
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x |
|
||||
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x |
|
||||
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x |
|
||||
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x |
|
||||
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT_TRG | x |
|
||||
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x |
|
||||
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x |
|
||||
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HXT |\ref CLK_CLKDIV0_UART0(x) |
|
||||
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_PLL |\ref CLK_CLKDIV0_UART0(x) |
|
||||
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_LXT |\ref CLK_CLKDIV0_UART0(x) |
|
||||
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HIRC |\ref CLK_CLKDIV0_UART0(x) |
|
||||
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_PCLK0 |\ref CLK_CLKDIV0_UART0(x) |
|
||||
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_LIRC |\ref CLK_CLKDIV0_UART0(x) |
|
||||
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HXT |\ref CLK_CLKDIV0_UART1(x) |
|
||||
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_PLL |\ref CLK_CLKDIV0_UART1(x) |
|
||||
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_LXT |\ref CLK_CLKDIV0_UART1(x) |
|
||||
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HIRC |\ref CLK_CLKDIV0_UART1(x) |
|
||||
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_PCLK1 |\ref CLK_CLKDIV0_UART1(x) |
|
||||
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_LIRC |\ref CLK_CLKDIV0_UART1(x) |
|
||||
* |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HXT |\ref CLK_CLKDIV4_UART2(x) |
|
||||
* |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_PLL |\ref CLK_CLKDIV4_UART2(x) |
|
||||
* |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_LXT |\ref CLK_CLKDIV4_UART2(x) |
|
||||
* |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HIRC |\ref CLK_CLKDIV4_UART2(x) |
|
||||
* |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_PCLK0 |\ref CLK_CLKDIV4_UART2(x) |
|
||||
* |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_LIRC |\ref CLK_CLKDIV4_UART2(x) |
|
||||
* |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HXT |\ref CLK_CLKDIV4_UART3(x) |
|
||||
* |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_PLL |\ref CLK_CLKDIV4_UART3(x) |
|
||||
* |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_LXT |\ref CLK_CLKDIV4_UART3(x) |
|
||||
* |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HIRC |\ref CLK_CLKDIV4_UART3(x) |
|
||||
* |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_PCLK1 |\ref CLK_CLKDIV4_UART3(x) |
|
||||
* |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_LIRC |\ref CLK_CLKDIV4_UART3(x) |
|
||||
* |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HXT |\ref CLK_CLKDIV4_UART4(x) |
|
||||
* |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PLL |\ref CLK_CLKDIV4_UART4(x) |
|
||||
* |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_LXT |\ref CLK_CLKDIV4_UART4(x) |
|
||||
* |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HIRC |\ref CLK_CLKDIV4_UART4(x) |
|
||||
* |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PCLK0 |\ref CLK_CLKDIV4_UART4(x) |
|
||||
* |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_LIRC |\ref CLK_CLKDIV4_UART4(x) |
|
||||
* |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HXT |\ref CLK_CLKDIV4_UART5(x) |
|
||||
* |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PLL |\ref CLK_CLKDIV4_UART5(x) |
|
||||
* |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_LXT |\ref CLK_CLKDIV4_UART5(x) |
|
||||
* |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HIRC |\ref CLK_CLKDIV4_UART5(x) |
|
||||
* |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PCLK1 |\ref CLK_CLKDIV4_UART5(x) |
|
||||
* |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_LIRC |\ref CLK_CLKDIV4_UART5(x) |
|
||||
* |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_HXT |\ref CLK_CLKDIV4_UART6(x) |
|
||||
* |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_PLL |\ref CLK_CLKDIV4_UART6(x) |
|
||||
* |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_LXT |\ref CLK_CLKDIV4_UART6(x) |
|
||||
* |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_HIRC |\ref CLK_CLKDIV4_UART6(x) |
|
||||
* |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_PCLK0 |\ref CLK_CLKDIV4_UART6(x) |
|
||||
* |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_LIRC |\ref CLK_CLKDIV4_UART6(x) |
|
||||
* |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_HXT |\ref CLK_CLKDIV4_UART7(x) |
|
||||
* |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_PLL |\ref CLK_CLKDIV4_UART7(x) |
|
||||
* |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_LXT |\ref CLK_CLKDIV4_UART7(x) |
|
||||
* |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_HIRC |\ref CLK_CLKDIV4_UART7(x) |
|
||||
* |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_PCLK1 |\ref CLK_CLKDIV4_UART7(x) |
|
||||
* |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_LIRC |\ref CLK_CLKDIV4_UART7(x) |
|
||||
* |\ref PWM0_MODULE |\ref CLK_CLKSEL2_PWM0SEL_PLL | x |
|
||||
* |\ref PWM0_MODULE |\ref CLK_CLKSEL2_PWM0SEL_PCLK0 | x |
|
||||
* |\ref PWM1_MODULE |\ref CLK_CLKSEL2_PWM1SEL_PLL | x |
|
||||
* |\ref PWM1_MODULE |\ref CLK_CLKSEL2_PWM1SEL_PCLK1 | x |
|
||||
* |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HXT | x |
|
||||
* |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PLL | x |
|
||||
* |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PCLK0 | x |
|
||||
* |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HIRC | x |
|
||||
* |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x |
|
||||
* |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x |
|
||||
* |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK1 | x |
|
||||
* |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x |
|
||||
* |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PLL | x |
|
||||
* |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PCLK0 | x |
|
||||
* |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PLL | x |
|
||||
* |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PCLK1 | x |
|
||||
* |\ref ADC_MODULE |\ref CLK_CLKSEL2_ADCSEL_HXT |\ref CLK_CLKDIV0_ADC(x) |
|
||||
* |\ref ADC_MODULE |\ref CLK_CLKSEL2_ADCSEL_PLL |\ref CLK_CLKDIV0_ADC(x) |
|
||||
* |\ref ADC_MODULE |\ref CLK_CLKSEL2_ADCSEL_PCLK1 |\ref CLK_CLKDIV0_ADC(x) |
|
||||
* |\ref ADC_MODULE |\ref CLK_CLKSEL2_ADCSEL_HIRC |\ref CLK_CLKDIV0_ADC(x) |
|
||||
*/
|
||||
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
|
||||
{
|
||||
uint32_t u32sel = 0, u32div = 0;
|
||||
uint32_t u32SelTbl[4] = {0x0, 0x4, 0x8, 0xC}; /* CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
|
||||
uint32_t u32DivTbl[4] = {0x0, 0x0, 0x0, 0x10}; /* CLKDIV offset on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 */
|
||||
|
||||
if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
|
||||
{
|
||||
/* Get clock divider control register address */
|
||||
u32div = (uint32_t)&CLK->CLKDIV0 + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
|
||||
/* Apply new divider */
|
||||
M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
|
||||
}
|
||||
|
||||
if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
|
||||
{
|
||||
/* Get clock select control register address */
|
||||
u32sel = (uint32_t)&CLK->CLKSEL0 + (u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
|
||||
/* Set new clock selection setting */
|
||||
M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SysTick clock source
|
||||
* @param[in] u32ClkSrc is module clock source. Including:
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HXT
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_LXT
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
|
||||
* @return None
|
||||
* @details This function set SysTick clock source. \n
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
|
||||
{
|
||||
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable clock source
|
||||
* @param[in] u32ClkMask is clock source mask. Including :
|
||||
* - \ref CLK_PWRCTL_HXTEN_Msk
|
||||
* - \ref CLK_PWRCTL_LXTEN_Msk
|
||||
* - \ref CLK_PWRCTL_HIRCEN_Msk
|
||||
* - \ref CLK_PWRCTL_LIRCEN_Msk
|
||||
* @return None
|
||||
* @details This function enable clock source. \n
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
void CLK_EnableXtalRC(uint32_t u32ClkMask)
|
||||
{
|
||||
CLK->PWRCTL |= u32ClkMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable clock source
|
||||
* @param[in] u32ClkMask is clock source mask. Including :
|
||||
* - \ref CLK_PWRCTL_HXTEN_Msk
|
||||
* - \ref CLK_PWRCTL_LXTEN_Msk
|
||||
* - \ref CLK_PWRCTL_HIRCEN_Msk
|
||||
* - \ref CLK_PWRCTL_LIRCEN_Msk
|
||||
* @return None
|
||||
* @details This function disable clock source. \n
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
void CLK_DisableXtalRC(uint32_t u32ClkMask)
|
||||
{
|
||||
CLK->PWRCTL &= ~u32ClkMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enable module clock
|
||||
* @param[in] u32ModuleIdx is module index. Including :
|
||||
* - \ref PDMA_MODULE
|
||||
* - \ref ISP_MODULE
|
||||
* - \ref EBI_MODULE
|
||||
* - \ref HDIV_MODULE
|
||||
* - \ref CRC_MODULE
|
||||
* - \ref WDT_MODULE
|
||||
* - \ref WWDT_MODULE
|
||||
* - \ref RTC_MODULE
|
||||
* - \ref TMR0_MODULE
|
||||
* - \ref TMR1_MODULE
|
||||
* - \ref TMR2_MODULE
|
||||
* - \ref TMR3_MODULE
|
||||
* - \ref CLKO_MODULE
|
||||
* - \ref UART0_MODULE
|
||||
* - \ref UART1_MODULE
|
||||
* - \ref UART2_MODULE
|
||||
* - \ref UART3_MODULE
|
||||
* - \ref UART4_MODULE
|
||||
* - \ref UART5_MODULE
|
||||
* - \ref UART6_MODULE
|
||||
* - \ref UART7_MODULE
|
||||
* - \ref I2C0_MODULE
|
||||
* - \ref I2C1_MODULE
|
||||
* - \ref QSPI0_MODULE
|
||||
* - \ref SPI0_MODULE
|
||||
* - \ref ADC_MODULE
|
||||
* - \ref ACMP01_MODULE
|
||||
* - \ref USBD_MODULE
|
||||
* - \ref PWM0_MODULE
|
||||
* - \ref PWM1_MODULE
|
||||
* - \ref BPWM0_MODULE
|
||||
* - \ref BPWM1_MODULE
|
||||
* - \ref USCI0_MODULE
|
||||
* - \ref USCI1_MODULE
|
||||
* @return None
|
||||
* @details This function enable module clock.
|
||||
*/
|
||||
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
|
||||
{
|
||||
uint32_t u32ClkTbl[3] = {0x0, 0x4, 0x8}; /* AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
|
||||
|
||||
*(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (u32ClkTbl[MODULE_APBCLK(u32ModuleIdx)])) |= 1 << MODULE_IP_EN_Pos(u32ModuleIdx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disable module clock
|
||||
* @param[in] u32ModuleIdx is module index
|
||||
* - \ref PDMA_MODULE
|
||||
* - \ref ISP_MODULE
|
||||
* - \ref EBI_MODULE
|
||||
* - \ref HDIV_MODULE
|
||||
* - \ref CRC_MODULE
|
||||
* - \ref WDT_MODULE
|
||||
* - \ref WWDT_MODULE
|
||||
* - \ref RTC_MODULE
|
||||
* - \ref TMR0_MODULE
|
||||
* - \ref TMR1_MODULE
|
||||
* - \ref TMR2_MODULE
|
||||
* - \ref TMR3_MODULE
|
||||
* - \ref CLKO_MODULE
|
||||
* - \ref UART0_MODULE
|
||||
* - \ref UART1_MODULE
|
||||
* - \ref UART2_MODULE
|
||||
* - \ref UART3_MODULE
|
||||
* - \ref UART4_MODULE
|
||||
* - \ref UART5_MODULE
|
||||
* - \ref UART6_MODULE
|
||||
* - \ref UART7_MODULE
|
||||
* - \ref I2C0_MODULE
|
||||
* - \ref I2C1_MODULE
|
||||
* - \ref QSPI0_MODULE
|
||||
* - \ref SPI0_MODULE
|
||||
* - \ref ADC_MODULE
|
||||
* - \ref ACMP01_MODULE
|
||||
* - \ref USBD_MODULE
|
||||
* - \ref PWM0_MODULE
|
||||
* - \ref PWM1_MODULE
|
||||
* - \ref BPWM0_MODULE
|
||||
* - \ref BPWM1_MODULE
|
||||
* - \ref USCI0_MODULE
|
||||
* - \ref USCI1_MODULE
|
||||
* @return None
|
||||
* @details This function disable module clock.
|
||||
*/
|
||||
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
|
||||
{
|
||||
uint32_t u32ClkTbl[3] = {0x0, 0x4, 0x8}; /* AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
|
||||
|
||||
*(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (u32ClkTbl[MODULE_APBCLK(u32ModuleIdx)])) &= ~(1 << MODULE_IP_EN_Pos(u32ModuleIdx));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PLL frequency
|
||||
* @param[in] u32PllClkSrc is PLL clock source. Including :
|
||||
* - \ref CLK_PLLCTL_PLLSRC_HXT
|
||||
* - \ref CLK_PLLCTL_PLLSRC_HIRC_DIV4
|
||||
* @param[in] u32PllFreq is PLL frequency. The frequency unit is Hz.
|
||||
* @return Actual PLL frequency
|
||||
* @details This function is used to configure PLLCTL register to set specified PLL frequency. \n
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
|
||||
{
|
||||
uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC, u32Outdiv;
|
||||
uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR;
|
||||
uint32_t u32PLL_UpperLimit;
|
||||
|
||||
/* Disable PLL first to avoid unstable when setting PLL */
|
||||
CLK_DisablePLL();
|
||||
|
||||
/* PLL source clock is from HXT */
|
||||
if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
|
||||
{
|
||||
/* Enable HXT clock */
|
||||
CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
|
||||
|
||||
/* Wait for HXT clock ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
|
||||
|
||||
/* Select PLL source clock from HXT */
|
||||
u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT;
|
||||
u32PllSrcClk = __HXT;
|
||||
|
||||
/* u32NR start from 2 since NR = INDIV + 2 */
|
||||
u32NR = 2;
|
||||
}
|
||||
|
||||
/* PLL source clock is from HIRC/4 */
|
||||
else
|
||||
{
|
||||
/* Enable HIRC clock */
|
||||
CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
|
||||
|
||||
/* Wait for HIRC clock ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
|
||||
|
||||
/* Select PLL source clock from HIRC */
|
||||
u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC_DIV4;
|
||||
u32PllSrcClk = __HIRC >> 2;
|
||||
|
||||
/* u32NR start from 2 since NR = INDIV + 2 */
|
||||
u32NR = 2;
|
||||
}
|
||||
|
||||
/* Select "NO" according to request frequency */
|
||||
/* Constraint: PLL output frequency must <= 96MHz */
|
||||
/* PLL output frequency must > 50.14MHz to meet all constraints */
|
||||
if ((GET_CHIP_SERIES_NUM == CHIP_SERIES_NUM_G) || (GET_CHIP_SERIES_NUM == CHIP_SERIES_NUM_I))
|
||||
u32PLL_UpperLimit = FREQ_144MHZ;
|
||||
else
|
||||
u32PLL_UpperLimit = FREQ_96MHZ;
|
||||
|
||||
if((u32PllFreq <= u32PLL_UpperLimit) && (u32PllFreq >= FREQ_51MHZ))
|
||||
{
|
||||
if (u32PllFreq <= FREQ_96MHZ)
|
||||
{
|
||||
u32NO = 4;
|
||||
u32Outdiv = 3;
|
||||
u32PllFreq = u32PllFreq << 2; /* u32PllFreq = (FIN * NF / NR) now */
|
||||
}
|
||||
else
|
||||
{
|
||||
u32NO = 2;
|
||||
u32Outdiv = 2;
|
||||
u32PllFreq = u32PllFreq << 1; /* u32PllFreq = (FIN * NF / NR) now */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Wrong frequency request. Just return default setting. */
|
||||
goto lexit;
|
||||
}
|
||||
|
||||
/* Find best solution */
|
||||
u32Min = (uint32_t) 0xFFFFFFFF; /* initial u32Min to max value of uint32_t */
|
||||
u32MinNR = 0;
|
||||
u32MinNF = 0;
|
||||
for(; u32NR <= 33; u32NR++) /* max NR = 33 since NR = INDIV + 2 and INDIV = 0 ~ 31 */
|
||||
{
|
||||
u32Tmp = u32PllSrcClk / u32NR;
|
||||
/* Constraint 2: 800KHz < (FIN / (2*NR)) < 8MHz */
|
||||
if((u32Tmp > 1600000) && (u32Tmp < 16000000))
|
||||
{
|
||||
for(u32NF = 2; u32NF <= 513; u32NF++) /* NF = 2~513 since NF = FBDIV + 2 and FBDIV = 0 ~ 511 */
|
||||
{
|
||||
u32Tmp2 = u32Tmp * u32NF;
|
||||
/* Constraint 3: 200MHz < (FIN * NF / NR) < 500MHz */
|
||||
if((u32Tmp2 >= 200000000) && (u32Tmp2 < 500000000))
|
||||
{
|
||||
u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
|
||||
if(u32Tmp3 < u32Min)
|
||||
{
|
||||
u32Min = u32Tmp3;
|
||||
u32MinNR = u32NR;
|
||||
u32MinNF = u32NF;
|
||||
|
||||
/* Break when get good results */
|
||||
if(u32Min == 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable and apply new PLL setting. */
|
||||
CLK->PLLCTL = u32CLK_SRC |
|
||||
(u32Outdiv << CLK_PLLCTL_OUTDIV_Pos) |
|
||||
((u32MinNR - 2) << CLK_PLLCTL_INDIV_Pos) |
|
||||
((u32MinNF - 2) << CLK_PLLCTL_FBDIV_Pos);
|
||||
|
||||
/* Wait for PLL clock stable */
|
||||
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
|
||||
|
||||
/* Return actual PLL output clock frequency */
|
||||
return (u32PllSrcClk / (u32NO * u32MinNR) * u32MinNF);
|
||||
|
||||
lexit:
|
||||
|
||||
/* Apply default PLL setting and return */
|
||||
if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
|
||||
CLK->PLLCTL = CLK_PLLCTL_96MHz_HXT;
|
||||
else
|
||||
CLK->PLLCTL = CLK_PLLCTL_96MHz_HIRC_DIV4;
|
||||
|
||||
/* Wait for PLL clock stable */
|
||||
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
|
||||
|
||||
return CLK_GetPLLClockFreq();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable PLL
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function set PLL in Power-down mode. \n
|
||||
* If the current HCLK is PLL, this function will switch HCLK to HIRC before disable PLL. \n
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
void CLK_DisablePLL(void)
|
||||
{
|
||||
/* Switch HCLK to HIRC before disable PLL if current HCLK is PLL */
|
||||
if ((CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk) == CLK_CLKSEL0_HCLKSEL_PLL)
|
||||
{
|
||||
CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
|
||||
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
|
||||
CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
|
||||
}
|
||||
|
||||
CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function check selected clock source status
|
||||
* @param[in] u32ClkMask is selected clock source. Including :
|
||||
* - \ref CLK_STATUS_HXTSTB_Msk
|
||||
* - \ref CLK_STATUS_LXTSTB_Msk
|
||||
* - \ref CLK_STATUS_HIRCSTB_Msk
|
||||
* - \ref CLK_STATUS_LIRCSTB_Msk
|
||||
* - \ref CLK_STATUS_PLLSTB_Msk
|
||||
* @retval 0 clock is not stable
|
||||
* @retval 1 clock is stable
|
||||
* @details To wait for clock ready by specified clock source stable flag or timeout (~300ms)
|
||||
*/
|
||||
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
|
||||
{
|
||||
int32_t i32TimeOutCnt = 2160000;
|
||||
|
||||
while((CLK->STATUS & u32ClkMask) != u32ClkMask)
|
||||
{
|
||||
if(i32TimeOutCnt-- <= 0)
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable System Tick counter
|
||||
* @param[in] u32ClkSrc is System Tick clock source. Including:
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HXT
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_LXT
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HCLK
|
||||
* @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF.
|
||||
* @return None
|
||||
* @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
|
||||
{
|
||||
/* Set System Tick counter disabled */
|
||||
SysTick->CTRL = 0;
|
||||
|
||||
/* Set System Tick clock source */
|
||||
if(u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK)
|
||||
SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
|
||||
else
|
||||
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
|
||||
|
||||
/* Set System Tick reload value */
|
||||
SysTick->LOAD = u32Count;
|
||||
|
||||
/* Clear System Tick current value and counter flag */
|
||||
SysTick->VAL = 0;
|
||||
|
||||
/* Set System Tick interrupt enabled and counter enabled */
|
||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable System Tick counter
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function disable System Tick counter.
|
||||
*/
|
||||
void CLK_DisableSysTick(void)
|
||||
{
|
||||
/* Set System Tick counter disabled */
|
||||
SysTick->CTRL = 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group CLK_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,99 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file crc.c
|
||||
* @version V3.00
|
||||
* $Revision: 4 $
|
||||
* $Date: 18/04/24 3:49p $
|
||||
* @brief M031 series Cyclic Redundancy Check(CRC) driver source file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "NuMicro.h"
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Driver CRC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRC Open
|
||||
*
|
||||
* @param[in] u32Mode CRC operation polynomial mode. Valid values are:
|
||||
* - \ref CRC_CCITT
|
||||
* - \ref CRC_8
|
||||
* - \ref CRC_16
|
||||
* - \ref CRC_32
|
||||
* @param[in] u32Attribute CRC operation data attribute. Valid values are combined with:
|
||||
* - \ref CRC_CHECKSUM_COM
|
||||
* - \ref CRC_CHECKSUM_RVS
|
||||
* - \ref CRC_WDATA_COM
|
||||
* - \ref CRC_WDATA_RVS
|
||||
* @param[in] u32Seed Seed value.
|
||||
* @param[in] u32DataLen CPU Write Data Length. Valid values are:
|
||||
* - \ref CRC_CPU_WDATA_8
|
||||
* - \ref CRC_CPU_WDATA_16
|
||||
* - \ref CRC_CPU_WDATA_32
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n
|
||||
* After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly.
|
||||
*/
|
||||
void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
|
||||
{
|
||||
CRC->SEED = u32Seed;
|
||||
CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;
|
||||
|
||||
/* Setting CRCRST bit will reload the initial seed value(CRC_SEED register) to CRC controller */
|
||||
CRC->CTL |= CRC_CTL_CHKSINIT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC Checksum
|
||||
*
|
||||
* @param[in] None
|
||||
*
|
||||
* @return Checksum Result
|
||||
*
|
||||
* @details This macro gets the CRC checksum result by current CRC polynomial mode.
|
||||
*/
|
||||
uint32_t CRC_GetChecksum(void)
|
||||
{
|
||||
uint32_t ret;
|
||||
|
||||
switch(CRC->CTL & CRC_CTL_CRCMODE_Msk)
|
||||
{
|
||||
case CRC_CCITT:
|
||||
case CRC_16:
|
||||
ret = (CRC->CHECKSUM & 0xFFFFU);
|
||||
break;
|
||||
case CRC_32:
|
||||
ret = (CRC->CHECKSUM);
|
||||
break;
|
||||
case CRC_8:
|
||||
ret = (CRC->CHECKSUM & 0xFFU);
|
||||
break;
|
||||
default:
|
||||
ret = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group CRC_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,182 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file ebi.c
|
||||
* @version V1.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 18/08/20 11:48a $
|
||||
* @brief M031 series External Bus Interface(EBI) driver source file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "NuMicro.h"
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup EBI_Driver EBI Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize EBI for specify Bank
|
||||
*
|
||||
* @param[in] u32Bank Bank number for EBI. Valid values are:
|
||||
* - \ref EBI_BANK0
|
||||
* - \ref EBI_BANK1
|
||||
* @param[in] u32DataWidth Data bus width. Valid values are:
|
||||
* - \ref EBI_BUSWIDTH_8BIT
|
||||
* - \ref EBI_BUSWIDTH_16BIT
|
||||
* @param[in] u32TimingClass Default timing configuration. Valid values are:
|
||||
* - \ref EBI_TIMING_FASTEST
|
||||
* - \ref EBI_TIMING_VERYFAST
|
||||
* - \ref EBI_TIMING_FAST
|
||||
* - \ref EBI_TIMING_NORMAL
|
||||
* - \ref EBI_TIMING_SLOW
|
||||
* - \ref EBI_TIMING_VERYSLOW
|
||||
* - \ref EBI_TIMING_SLOWEST
|
||||
* @param[in] u32BusMode Set EBI bus operate mode. Valid values are:
|
||||
* - \ref EBI_OPMODE_NORMAL
|
||||
* - \ref EBI_OPMODE_CACCESS
|
||||
* @param[in] u32CSActiveLevel CS is active High/Low. Valid values are:
|
||||
* - \ref EBI_CS_ACTIVE_HIGH
|
||||
* - \ref EBI_CS_ACTIVE_LOW
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to open specify EBI bank with different bus width, timing setting and \n
|
||||
* active level of CS pin to access EBI device.
|
||||
* @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register.
|
||||
*/
|
||||
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
|
||||
{
|
||||
volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10));
|
||||
volatile uint32_t *pu32EBITCTL = (uint32_t *)((uint32_t)&EBI->TCTL0 + (u32Bank * 0x10));
|
||||
|
||||
if(u32DataWidth == EBI_BUSWIDTH_8BIT)
|
||||
*pu32EBICTL &= ~EBI_CTL_DW16_Msk;
|
||||
else
|
||||
*pu32EBICTL |= EBI_CTL_DW16_Msk;
|
||||
|
||||
*pu32EBICTL |= u32BusMode;
|
||||
|
||||
switch (u32TimingClass)
|
||||
{
|
||||
case EBI_TIMING_FASTEST:
|
||||
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||
(EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
|
||||
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
|
||||
*pu32EBITCTL = 0x0U;
|
||||
break;
|
||||
|
||||
case EBI_TIMING_VERYFAST:
|
||||
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||
(EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
|
||||
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||
(0x3U << EBI_CTL_TALE_Pos) ;
|
||||
*pu32EBITCTL = 0x03003318U;
|
||||
break;
|
||||
|
||||
case EBI_TIMING_FAST:
|
||||
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
|
||||
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
|
||||
*pu32EBITCTL = 0x0U;
|
||||
break;
|
||||
|
||||
case EBI_TIMING_NORMAL:
|
||||
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
|
||||
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||
(0x3U << EBI_CTL_TALE_Pos) ;
|
||||
*pu32EBITCTL = 0x03003318U;
|
||||
break;
|
||||
|
||||
case EBI_TIMING_SLOW:
|
||||
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
|
||||
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||
(0x7U << EBI_CTL_TALE_Pos) ;
|
||||
*pu32EBITCTL = 0x07007738U;
|
||||
break;
|
||||
|
||||
case EBI_TIMING_VERYSLOW:
|
||||
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||
(EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) |
|
||||
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||
(0x7U << EBI_CTL_TALE_Pos) ;
|
||||
*pu32EBITCTL = 0x07007738U;
|
||||
break;
|
||||
|
||||
case EBI_TIMING_SLOWEST:
|
||||
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||
(EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) |
|
||||
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||
(0x7U << EBI_CTL_TALE_Pos) ;
|
||||
*pu32EBITCTL = 0x07007738U;
|
||||
break;
|
||||
|
||||
default:
|
||||
*pu32EBICTL &= ~EBI_CTL_EN_Msk;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable EBI on specify Bank
|
||||
*
|
||||
* @param[in] u32Bank Bank number for EBI. Valid values are:
|
||||
* - \ref EBI_BANK0
|
||||
* - \ref EBI_BANK1
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to close specify EBI function.
|
||||
*/
|
||||
void EBI_Close(uint32_t u32Bank)
|
||||
{
|
||||
volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10U));
|
||||
|
||||
*pu32EBICTL &= ~EBI_CTL_EN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set EBI Bus Timing for specify Bank
|
||||
*
|
||||
* @param[in] u32Bank Bank number for EBI. Valid values are:
|
||||
* - \ref EBI_BANK0
|
||||
* - \ref EBI_BANK1
|
||||
* @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting.
|
||||
* @param[in] u32MclkDiv Divider for MCLK. Valid values are:
|
||||
* - \ref EBI_MCLKDIV_1
|
||||
* - \ref EBI_MCLKDIV_2
|
||||
* - \ref EBI_MCLKDIV_4
|
||||
* - \ref EBI_MCLKDIV_8
|
||||
* - \ref EBI_MCLKDIV_16
|
||||
* - \ref EBI_MCLKDIV_32
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to configure specify EBI bus timing for access EBI device.
|
||||
*/
|
||||
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
|
||||
{
|
||||
volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10U));
|
||||
volatile uint32_t *pu32EBITCTL = (uint32_t *)((uint32_t)&EBI->TCTL0 + (u32Bank * 0x10U));
|
||||
|
||||
*pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos);
|
||||
*pu32EBITCTL = u32TimingConfig;
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group EBI_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,572 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file fmc.c
|
||||
* @version V1.00
|
||||
* $Revision: 3 $
|
||||
* $Date: 18/04/24 3:05p $
|
||||
* @brief M031 series FMC driver source file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#include "NuMicro.h"
|
||||
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup FMC_Driver FMC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable FMC ISP function.
|
||||
* @return None
|
||||
*/
|
||||
void FMC_Close(void)
|
||||
{
|
||||
FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase a flash page. The page size is 4096 bytes.
|
||||
* @param[in] u32PageAddr Address of the flash page to be erased.
|
||||
* It must be a 4096 bytes aligned address.
|
||||
* @return ISP page erase success or not.
|
||||
* @retval 0 Success
|
||||
* @retval -1 Erase failed
|
||||
*/
|
||||
int32_t FMC_Erase(uint32_t u32PageAddr)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
|
||||
if (u32PageAddr == FMC_SPROM_BASE)
|
||||
{
|
||||
ret = FMC_Erase_SPROM();
|
||||
}
|
||||
else
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
|
||||
FMC->ISPADDR = u32PageAddr;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
|
||||
|
||||
if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
|
||||
{
|
||||
FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
|
||||
ret = -1;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Execute Flash Bank erase
|
||||
*
|
||||
* @param[in] u32BankAddr Base address of the flash bank to be erased.
|
||||
*
|
||||
* @return ISP bank erase success or not.
|
||||
* @retval 0 Success
|
||||
* @retval -1 Erase failed
|
||||
*
|
||||
* @details Execute FMC_ISPCMD_BANK_ERASE command to erase a flash bank.
|
||||
*/
|
||||
int32_t FMC_Erase_Bank(uint32_t u32BankAddr)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
|
||||
FMC->ISPCMD = FMC_ISPCMD_BANK_ERASE;
|
||||
FMC->ISPADDR = u32BankAddr;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
|
||||
|
||||
if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
|
||||
{
|
||||
FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
|
||||
ret = -1;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase SPROM. The page size is 4096 bytes.
|
||||
* @return SPROM page erase success or not.
|
||||
* @retval 0 Success
|
||||
* @retval -1 Erase failed
|
||||
*/
|
||||
int32_t FMC_Erase_SPROM(void)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
|
||||
FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
|
||||
FMC->ISPADDR = FMC_SPROM_BASE;
|
||||
FMC->ISPDAT = 0x0055AA03UL;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
|
||||
|
||||
if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
|
||||
{
|
||||
FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
|
||||
ret = -1;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Execute FMC_ISPCMD_BANK_REMAP command to remap bank.
|
||||
* @return Bank remap success or not.
|
||||
* @retval 0 Success
|
||||
* @retval -1 Erase failed
|
||||
*/
|
||||
int32_t FMC_RemapBank(uint32_t u32BankIdx)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
|
||||
FMC->ISPCMD = FMC_ISPCMD_BANK_REMAP;
|
||||
FMC->ISPADDR = u32BankIdx;
|
||||
FMC->ISPDAT = 0x5AA55AA5UL;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
|
||||
|
||||
if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
|
||||
{
|
||||
FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
|
||||
ret = -1;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the current boot source.
|
||||
* @return The current boot source.
|
||||
* @retval 0 Is boot from APROM.
|
||||
* @retval 1 Is boot from LDROM.
|
||||
*/
|
||||
int32_t FMC_GetBootSource (void)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
|
||||
if (FMC->ISPCTL & FMC_ISPCTL_BS_Msk)
|
||||
{
|
||||
ret = 1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable FMC ISP function
|
||||
* @return None
|
||||
*/
|
||||
void FMC_Open(void)
|
||||
{
|
||||
FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Execute FMC_ISPCMD_READ command to read a word from flash.
|
||||
* @param[in] u32Addr Address of the flash location to be read.
|
||||
* It must be a word aligned address.
|
||||
* @return The word data read from specified flash address.
|
||||
*/
|
||||
uint32_t FMC_Read(uint32_t u32Addr)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ;
|
||||
FMC->ISPADDR = u32Addr;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
|
||||
|
||||
return FMC->ISPDAT;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the base address of Data Flash if enabled.
|
||||
* @retval The base address of Data Flash
|
||||
*/
|
||||
uint32_t FMC_ReadDataFlashBaseAddr(void)
|
||||
{
|
||||
return FMC->DFBA;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set boot source from LDROM or APROM after next software reset
|
||||
* @param[in] i32BootSrc
|
||||
* 1: Boot from LDROM
|
||||
* 0: Boot from APROM
|
||||
* @return None
|
||||
* @details This function is used to switch APROM boot or LDROM boot. User need to call
|
||||
* FMC_SetBootSource to select boot source first, then use CPU reset or
|
||||
* System Reset Request to reset system.
|
||||
*/
|
||||
void FMC_SetBootSource(int32_t i32BootSrc)
|
||||
{
|
||||
if(i32BootSrc)
|
||||
{
|
||||
FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */
|
||||
}
|
||||
else
|
||||
{
|
||||
FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Execute ISP FMC_ISPCMD_PROGRAM to program a word to flash.
|
||||
* @param[in] u32Addr Address of the flash location to be programmed.
|
||||
* It must be a word aligned address.
|
||||
* @param[in] u32Data The word data to be programmed.
|
||||
* @return None
|
||||
*/
|
||||
void FMC_Write(uint32_t u32Addr, uint32_t u32Data)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
|
||||
FMC->ISPADDR = u32Addr;
|
||||
FMC->ISPDAT = u32Data;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Execute ISP FMC_ISPCMD_PROGRAM_64 to program a double-word to flash.
|
||||
* @param[in] u32addr Address of the flash location to be programmed.
|
||||
* It must be a double-word aligned address.
|
||||
* @param[in] u32data0 The word data to be programmed to flash address u32addr.
|
||||
* @param[in] u32data1 The word data to be programmed to flash address u32addr+4.
|
||||
* @return 0 Success
|
||||
* @return -1 Failed
|
||||
*/
|
||||
int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
|
||||
FMC->ISPCMD = FMC_ISPCMD_PROGRAM_64;
|
||||
FMC->ISPADDR = u32addr;
|
||||
FMC->MPDAT0 = u32data0;
|
||||
FMC->MPDAT1 = u32data1;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
|
||||
|
||||
if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
|
||||
{
|
||||
FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
|
||||
ret = -1;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Execute FMC_ISPCMD_READ command to read User Configuration.
|
||||
* @param[out] u32Config A three-word array.
|
||||
* u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1.
|
||||
* @param[in] u32Count Available word count in u32Config.
|
||||
* @return Success or not.
|
||||
* @retval 0 Success.
|
||||
* @retval -1 Invalid parameter.
|
||||
*/
|
||||
int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
|
||||
u32Config[0] = FMC_Read(FMC_CONFIG_BASE);
|
||||
|
||||
if (u32Count > 3UL)
|
||||
{
|
||||
ret = -1;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(u32Count > 1UL)
|
||||
{
|
||||
u32Config[1] = FMC_Read(FMC_CONFIG_BASE+4UL);
|
||||
}
|
||||
if(u32Count > 2UL)
|
||||
{
|
||||
u32Config[2] = FMC_Read(FMC_CONFIG_BASE+8UL);
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Execute ISP commands to erase then write User Configuration.
|
||||
* @param[in] u32Config A two-word array.
|
||||
* u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1.
|
||||
* @param[in] u32Count Always be 2 in this BSP.
|
||||
* @return Success or not.
|
||||
* @retval 0 Success.
|
||||
* @retval -1 Invalid parameter.
|
||||
*/
|
||||
int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0u; i < u32Count; i++)
|
||||
{
|
||||
FMC_Write(FMC_CONFIG_BASE + i * 4u, u32Config[i]);
|
||||
|
||||
if (FMC_Read(FMC_CONFIG_BASE + i * 4u) != u32Config[i])
|
||||
{
|
||||
ret = -1;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Run CRC32 checksum calculation and get result.
|
||||
* @param[in] u32addr Starting flash address. It must be a page aligned address.
|
||||
* @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes.
|
||||
* @return Success or not.
|
||||
* @retval 0 Success.
|
||||
* @retval 0xFFFFFFFF Invalid parameter.
|
||||
*/
|
||||
uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count)
|
||||
{
|
||||
uint32_t ret;
|
||||
|
||||
if ((u32addr % 512UL) || (u32count % 512UL))
|
||||
{
|
||||
ret = 0xFFFFFFFF;
|
||||
}
|
||||
else
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_RUN_CKS;
|
||||
FMC->ISPADDR = u32addr;
|
||||
FMC->ISPDAT = u32count;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
|
||||
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ_CKS;
|
||||
FMC->ISPADDR = u32addr;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
|
||||
|
||||
ret = FMC->ISPDAT;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Run flash all one verification and get result.
|
||||
*
|
||||
* @param[in] u32addr Starting flash address. It must be a page aligned address.
|
||||
* @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes.
|
||||
*
|
||||
* @retval READ_ALLONE_YES The contents of verified flash area are 0xFFFFFFFF.
|
||||
* @retval READ_ALLONE_NOT Some contents of verified flash area are not 0xFFFFFFFF.
|
||||
* @retval READ_ALLONE_CMD_FAIL Unexpected error occurred.
|
||||
*
|
||||
* @details Run ISP check all one command to check specify area is all one or not.
|
||||
*/
|
||||
#define FMC_APROM_BANK1_BASE (0x40000)
|
||||
#define FMC_CHECKALLONE_UNIT (512)
|
||||
uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count)
|
||||
{
|
||||
uint32_t ret = READ_ALLONE_CMD_FAIL;
|
||||
|
||||
/** Workaround solution for M031 with 512KB Flash uses FMC Read command instead of FMC All-One-Verification command to
|
||||
* check the Flash content from 0x40000 to 0x401FF.
|
||||
*/
|
||||
if(u32addr == FMC_APROM_BANK1_BASE)
|
||||
{
|
||||
uint32_t i;
|
||||
u32count = u32count - FMC_CHECKALLONE_UNIT;
|
||||
for(i = FMC_APROM_BANK1_BASE; i < (FMC_APROM_BANK1_BASE + FMC_CHECKALLONE_UNIT); i = i+4)
|
||||
{
|
||||
if( FMC_Read(i) != 0xFFFFFFFF)
|
||||
return READ_ALLONE_NOT;
|
||||
}
|
||||
|
||||
if(u32count == 0)
|
||||
return READ_ALLONE_YES;
|
||||
else
|
||||
u32addr = u32addr + FMC_CHECKALLONE_UNIT;
|
||||
}
|
||||
|
||||
FMC->ISPSTS = 0x80UL; /* clear check all one bit */
|
||||
|
||||
FMC->ISPCMD = FMC_ISPCMD_RUN_ALL1;
|
||||
FMC->ISPADDR = u32addr;
|
||||
FMC->ISPDAT = u32count;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
|
||||
|
||||
do
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ_ALL1;
|
||||
FMC->ISPADDR = u32addr;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
|
||||
}
|
||||
while (FMC->ISPDAT == 0UL);
|
||||
|
||||
if (FMC->ISPDAT == READ_ALLONE_YES)
|
||||
{
|
||||
ret = FMC->ISPDAT;
|
||||
}
|
||||
|
||||
if (FMC->ISPDAT == READ_ALLONE_NOT)
|
||||
{
|
||||
ret = FMC->ISPDAT;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write Multi-Word bytes to flash
|
||||
*
|
||||
* @param[in] u32Addr Start flash address in APROM where the data chunk to be programmed into.
|
||||
* This address must be 8-bytes aligned to flash address.
|
||||
* @param[in] pu32Buf Buffer that carry the data chunk.
|
||||
* @param[in] u32Len Length of the data chunk in bytes.
|
||||
*
|
||||
* @retval >=0 Number of data bytes were programmed.
|
||||
* @return -1 Invalid address.
|
||||
*
|
||||
* @detail Program Multi-Word data into specified address of flash.
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma arm section code="fastcode"
|
||||
int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len)
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len) @ "fastcode"
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#pragma GCC push_options
|
||||
#pragma GCC optimize ("O0")
|
||||
__attribute__ ((used, long_call, section(".fastcode"))) int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len)
|
||||
|
||||
#else
|
||||
int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len)
|
||||
#endif
|
||||
{
|
||||
|
||||
uint32_t i, idx, u32OnProg, retval = 0;
|
||||
int32_t err;
|
||||
|
||||
if ((u32Addr % 8) != 0)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
idx = 0u;
|
||||
FMC->ISPCMD = FMC_ISPCMD_MULTI_PROG;
|
||||
FMC->ISPADDR = u32Addr;
|
||||
retval += 16;
|
||||
do
|
||||
{
|
||||
err = 0;
|
||||
u32OnProg = 1u;
|
||||
FMC->MPDAT0 = pu32Buf[idx + 0u];
|
||||
FMC->MPDAT1 = pu32Buf[idx + 1u];
|
||||
FMC->MPDAT2 = pu32Buf[idx + 2u];
|
||||
FMC->MPDAT3 = pu32Buf[idx + 3u];
|
||||
FMC->ISPTRG = 0x1u;
|
||||
idx += 4u;
|
||||
|
||||
for (i = idx; i < (FMC_MULTI_WORD_PROG_LEN / 4u); i += 4u) /* Max data length is 256 bytes (512/4 words)*/
|
||||
{
|
||||
__set_PRIMASK(1u); /* Mask interrupt to avoid status check coherence error*/
|
||||
do
|
||||
{
|
||||
if ((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u)
|
||||
{
|
||||
__set_PRIMASK(0u);
|
||||
|
||||
FMC->ISPADDR = FMC->MPADDR & (~0xful);
|
||||
idx = (FMC->ISPADDR - u32Addr) / 4u;
|
||||
err = -1;
|
||||
}
|
||||
}
|
||||
while ((FMC->MPSTS & (3u << FMC_MPSTS_D0_Pos)) && (err == 0));
|
||||
|
||||
if (err == 0)
|
||||
{
|
||||
retval += 8;
|
||||
|
||||
/* Update new data for D0 */
|
||||
FMC->MPDAT0 = pu32Buf[i];
|
||||
FMC->MPDAT1 = pu32Buf[i + 1u];
|
||||
do
|
||||
{
|
||||
if ((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u)
|
||||
{
|
||||
__set_PRIMASK(0u);
|
||||
FMC->ISPADDR = FMC->MPADDR & (~0xful);
|
||||
idx = (FMC->ISPADDR - u32Addr) / 4u;
|
||||
err = -1;
|
||||
}
|
||||
}
|
||||
while ((FMC->MPSTS & (3u << FMC_MPSTS_D2_Pos)) && (err == 0));
|
||||
|
||||
if (err == 0)
|
||||
{
|
||||
retval += 8;
|
||||
|
||||
/* Update new data for D2*/
|
||||
FMC->MPDAT2 = pu32Buf[i + 2u];
|
||||
FMC->MPDAT3 = pu32Buf[i + 3u];
|
||||
__set_PRIMASK(0u);
|
||||
}
|
||||
}
|
||||
|
||||
if (err < 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (err == 0)
|
||||
{
|
||||
u32OnProg = 0u;
|
||||
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
|
||||
}
|
||||
}
|
||||
while (u32OnProg);
|
||||
return retval;
|
||||
}
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma arm section
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#pragma GCC pop_options
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group FMC_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
||||
|
||||
|
|
@ -1,108 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file gpio.c
|
||||
* @version V3.00
|
||||
* $Revision: 2 $
|
||||
* $Date: 18/03/28 5:52p $
|
||||
* @brief M031 Series General Purpose I/O (GPIO) Driver Source File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "M031Series.h"
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Driver GPIO Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set GPIO operation mode
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, or PF.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
|
||||
* It could be BIT0 ~ BIT15 for PA and PB.
|
||||
* It could be BIT0 ~ BIT7, and BIT14 for PC.
|
||||
* It could be BIT0 ~ BIT3, and BIT15 for PD.
|
||||
* It could be BIT0 ~ BIT6, BIT14, and BIT15 for PF.
|
||||
* @param[in] u32Mode Operation mode. It could be
|
||||
* - \ref GPIO_MODE_INPUT
|
||||
* - \ref GPIO_MODE_OUTPUT
|
||||
* - \ref GPIO_MODE_OPEN_DRAIN
|
||||
* - \ref GPIO_MODE_QUASI
|
||||
* @return None
|
||||
* @details This function is used to set specified GPIO operation mode.
|
||||
*/
|
||||
void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for(i = 0; i < GPIO_PIN_MAX; i++)
|
||||
{
|
||||
if(u32PinMask & (1 << i))
|
||||
{
|
||||
port->MODE = (port->MODE & ~(GPIO_MODE_MODE0_Msk << (i << 1))) | (u32Mode << (i << 1));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable GPIO interrupt
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, or PF.
|
||||
* @param[in] u32Pin The pin of specified GPIO port.
|
||||
* It could be 0 ~ 15 for PA and PB.
|
||||
* It could be 0 ~ 7, and 14 for PC.
|
||||
* It could be 0 ~ 3, and 15 for PD.
|
||||
* It could be 0 ~ 6, 14, and 15 for PF.
|
||||
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be
|
||||
* - \ref GPIO_INT_RISING
|
||||
* - \ref GPIO_INT_FALLING
|
||||
* - \ref GPIO_INT_BOTH_EDGE
|
||||
* - \ref GPIO_INT_HIGH
|
||||
* - \ref GPIO_INT_LOW
|
||||
* @return None
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
*/
|
||||
void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
|
||||
{
|
||||
/* Configure interrupt mode of specified pin */
|
||||
port->INTTYPE |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
|
||||
|
||||
/* Enable interrupt function of specified pin */
|
||||
port->INTEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable GPIO interrupt
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, or PF.
|
||||
* @param[in] u32Pin The pin of specified GPIO port.
|
||||
* It could be 0 ~ 15 for PA and PB.
|
||||
* It could be 0 ~ 7, and 14 for PC.
|
||||
* It could be 0 ~ 3, and 15 for PD.
|
||||
* It could be 0 ~ 6, 14, and 15 for PF.
|
||||
* @return None
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
*/
|
||||
void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
|
||||
{
|
||||
/* Configure interrupt mode of specified pin */
|
||||
port->INTTYPE &= ~(1UL << u32Pin);
|
||||
|
||||
/* Disable interrupt function of specified pin */
|
||||
port->INTEN &= ~((0x00010001UL) << u32Pin);
|
||||
}
|
||||
|
||||
|
||||
/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group GPIO_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,379 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file pdma.c
|
||||
* @version V1.00
|
||||
* @brief M031 series PDMA driver source file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "M031Series.h"
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup PDMA_Driver PDMA Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PDMA Open
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
*
|
||||
* @param[in] u32Mask Channel enable bits.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function enable the PDMA channels.
|
||||
*/
|
||||
void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0UL; i < PDMA_CH_MAX; i++)
|
||||
{
|
||||
if ((1 << i) & u32Mask)
|
||||
{
|
||||
pdma->DSCT[i].CTL = 0UL;
|
||||
}
|
||||
}
|
||||
|
||||
pdma->CHCTL |= u32Mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PDMA Close
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function disable all PDMA channels.
|
||||
*/
|
||||
void PDMA_Close(PDMA_T *pdma)
|
||||
{
|
||||
pdma->CHCTL = 0UL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PDMA Transfer Count
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
* @param[in] u32Width Data width. Valid values are
|
||||
* - \ref PDMA_WIDTH_8
|
||||
* - \ref PDMA_WIDTH_16
|
||||
* - \ref PDMA_WIDTH_32
|
||||
* @param[in] u32TransCount Transfer count
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function set the selected channel data width and transfer count.
|
||||
*/
|
||||
void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
|
||||
{
|
||||
pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);
|
||||
pdma->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PDMA Transfer Address
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
* @param[in] u32SrcAddr Source address
|
||||
* @param[in] u32SrcCtrl Source control attribute. Valid values are
|
||||
* - \ref PDMA_SAR_INC
|
||||
* - \ref PDMA_SAR_FIX
|
||||
* @param[in] u32DstAddr Destination address
|
||||
* @param[in] u32DstCtrl Destination control attribute. Valid values are
|
||||
* - \ref PDMA_DAR_INC
|
||||
* - \ref PDMA_DAR_FIX
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function set the selected channel source/destination address and attribute.
|
||||
*/
|
||||
void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
|
||||
{
|
||||
pdma->DSCT[u32Ch].SA = u32SrcAddr;
|
||||
pdma->DSCT[u32Ch].DA = u32DstAddr;
|
||||
pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);
|
||||
pdma->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PDMA Transfer Mode
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
* @param[in] u32Peripheral The selected peripheral. Valid values are
|
||||
* - \ref PDMA_MEM
|
||||
* - \ref PDMA_UART0_TX
|
||||
* - \ref PDMA_UART0_RX
|
||||
* - \ref PDMA_UART1_TX
|
||||
* - \ref PDMA_UART1_RX
|
||||
* - \ref PDMA_UART2_TX
|
||||
* - \ref PDMA_UART2_RX
|
||||
* - \ref PDMA_USCI0_TX
|
||||
* - \ref PDMA_USCI0_RX
|
||||
* - \ref PDMA_USCI1_TX
|
||||
* - \ref PDMA_USCI1_RX
|
||||
* - \ref PDMA_QSPI0_TX
|
||||
* - \ref PDMA_QSPI0_RX
|
||||
* - \ref PDMA_SPI0_TX
|
||||
* - \ref PDMA_SPI0_RX
|
||||
* - \ref PDMA_ADC_RX
|
||||
* - \ref PDMA_PWM0_P1_RX
|
||||
* - \ref PDMA_PWM0_P2_RX
|
||||
* - \ref PDMA_PWM0_P3_RX
|
||||
* - \ref PDMA_PWM1_P1_RX
|
||||
* - \ref PDMA_PWM1_P2_RX
|
||||
* - \ref PDMA_PWM1_P3_RX
|
||||
* - \ref PDMA_I2C0_TX
|
||||
* - \ref PDMA_I2C0_RX
|
||||
* - \ref PDMA_I2C1_TX
|
||||
* - \ref PDMA_I2C1_RX
|
||||
* - \ref PDMA_TMR0
|
||||
* - \ref PDMA_TMR1
|
||||
* - \ref PDMA_TMR2
|
||||
* - \ref PDMA_TMR3
|
||||
* - \ref PDMA_UART3_TX
|
||||
* - \ref PDMA_UART3_RX
|
||||
* - \ref PDMA_UART4_TX
|
||||
* - \ref PDMA_UART4_RX
|
||||
* - \ref PDMA_UART5_TX
|
||||
* - \ref PDMA_UART5_RX
|
||||
* - \ref PDMA_UART6_TX
|
||||
* - \ref PDMA_UART6_RX
|
||||
* - \ref PDMA_UART7_TX
|
||||
* - \ref PDMA_UART7_RX
|
||||
* @param[in] u32ScatterEn Scatter-gather mode enable
|
||||
* @param[in] u32DescAddr Scatter-gather descriptor address
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function set the selected channel transfer mode. Include peripheral setting.
|
||||
*/
|
||||
void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
|
||||
{
|
||||
if (u32Ch < PDMA_CH_MAX)
|
||||
{
|
||||
__IO uint32_t *pau32REQSEL = (__IO uint32_t *)&pdma->REQSEL0_3;
|
||||
uint32_t u32REQSEL_Pos, u32REQSEL_Msk;
|
||||
|
||||
u32REQSEL_Pos = (u32Ch % 4) * 8 ;
|
||||
u32REQSEL_Msk = PDMA_REQSEL0_3_REQSRC0_Msk << u32REQSEL_Pos;
|
||||
pau32REQSEL[u32Ch / 4] = (pau32REQSEL[u32Ch / 4] & ~u32REQSEL_Msk) | (u32Peripheral << u32REQSEL_Pos);
|
||||
|
||||
if (u32ScatterEn)
|
||||
{
|
||||
pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
|
||||
pdma->DSCT[u32Ch].NEXT = u32DescAddr - (pdma->SCATBA);
|
||||
}
|
||||
else
|
||||
{
|
||||
pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
|
||||
}
|
||||
}
|
||||
else {}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PDMA Burst Type and Size
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
* @param[in] u32BurstType Burst mode or single mode. Valid values are
|
||||
* - \ref PDMA_REQ_SINGLE
|
||||
* - \ref PDMA_REQ_BURST
|
||||
* @param[in] u32BurstSize Set the size of burst mode. Valid values are
|
||||
* - \ref PDMA_BURST_128
|
||||
* - \ref PDMA_BURST_64
|
||||
* - \ref PDMA_BURST_32
|
||||
* - \ref PDMA_BURST_16
|
||||
* - \ref PDMA_BURST_8
|
||||
* - \ref PDMA_BURST_4
|
||||
* - \ref PDMA_BURST_2
|
||||
* - \ref PDMA_BURST_1
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function set the selected channel burst type and size.
|
||||
*/
|
||||
void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
|
||||
{
|
||||
pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);
|
||||
pdma->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable timeout function
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
*
|
||||
* @param[in] u32Mask Channel enable bits.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function enable timeout function of the selected channel(s).
|
||||
*/
|
||||
void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask)
|
||||
{
|
||||
pdma->TOUTEN |= u32Mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable timeout function
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
*
|
||||
* @param[in] u32Mask Channel enable bits.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function disable timeout function of the selected channel(s).
|
||||
*/
|
||||
void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask)
|
||||
{
|
||||
pdma->TOUTEN &= ~u32Mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PDMA Timeout Count
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
* @param[in] u32OnOff Enable/disable time out function
|
||||
* @param[in] u32TimeOutCnt Timeout count
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function set the timeout count.
|
||||
* @note M031 only supported channel 0/1.
|
||||
*/
|
||||
void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
|
||||
{
|
||||
if (u32Ch < 2)
|
||||
{
|
||||
__IO uint32_t *pau32TOC = (__IO uint32_t *)&pdma->TOC0_1;
|
||||
uint32_t u32TOC_Pos, u32TOC_Msk;
|
||||
|
||||
u32TOC_Pos = (u32Ch % 2) * 16 ;
|
||||
u32TOC_Msk = PDMA_TOC0_1_TOC0_Msk << u32TOC_Pos;
|
||||
pau32TOC[u32Ch / 2] = (pau32TOC[u32Ch / 2] & ~u32TOC_Msk) | (u32TimeOutCnt << u32TOC_Pos);
|
||||
|
||||
if (u32OnOff)
|
||||
pdma->TOUTEN |= (1 << u32Ch);
|
||||
else
|
||||
pdma->TOUTEN &= ~(1 << u32Ch);
|
||||
}
|
||||
else {}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Trigger PDMA
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function trigger the selected channel.
|
||||
*/
|
||||
void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch)
|
||||
{
|
||||
__IO uint32_t *pau32REQSEL = (__IO uint32_t *)&pdma->REQSEL0_3;
|
||||
uint32_t u32REQSEL_Pos, u32REQSEL_Msk, u32ChReq;
|
||||
|
||||
u32REQSEL_Pos = (u32Ch % 4) * 8 ;
|
||||
u32REQSEL_Msk = PDMA_REQSEL0_3_REQSRC0_Msk << u32REQSEL_Pos;
|
||||
|
||||
u32ChReq = (pau32REQSEL[u32Ch / 4] & u32REQSEL_Msk) >> u32REQSEL_Pos;
|
||||
|
||||
if (u32ChReq == PDMA_MEM)
|
||||
{
|
||||
pdma->SWREQ = (1ul << u32Ch);
|
||||
}
|
||||
else {}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Interrupt
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
* @param[in] u32Mask The Interrupt Type. Valid values are
|
||||
* - \ref PDMA_INT_TRANS_DONE
|
||||
* - \ref PDMA_INT_TEMPTY
|
||||
* - \ref PDMA_INT_TIMEOUT
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function enable the selected channel interrupt.
|
||||
*/
|
||||
void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask)
|
||||
{
|
||||
switch (u32Mask)
|
||||
{
|
||||
case PDMA_INT_TRANS_DONE:
|
||||
pdma->INTEN |= (1ul << u32Ch);
|
||||
break;
|
||||
case PDMA_INT_TEMPTY:
|
||||
pdma->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk;
|
||||
break;
|
||||
case PDMA_INT_TIMEOUT:
|
||||
pdma->TOUTIEN |= (1ul << u32Ch);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Interrupt
|
||||
*
|
||||
* @param[in] pdma The pointer of the specified PDMA module
|
||||
* @param[in] u32Ch The selected channel
|
||||
* @param[in] u32Mask The Interrupt Type. Valid values are
|
||||
* - \ref PDMA_INT_TRANS_DONE
|
||||
* - \ref PDMA_INT_TEMPTY
|
||||
* - \ref PDMA_INT_TIMEOUT
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function disable the selected channel interrupt.
|
||||
*/
|
||||
void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask)
|
||||
{
|
||||
switch (u32Mask)
|
||||
{
|
||||
case PDMA_INT_TRANS_DONE:
|
||||
pdma->INTEN &= ~(1ul << u32Ch);
|
||||
break;
|
||||
case PDMA_INT_TEMPTY:
|
||||
pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk;
|
||||
break;
|
||||
case PDMA_INT_TIMEOUT:
|
||||
pdma->TOUTIEN &= ~(1ul << u32Ch);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group PDMA_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,813 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file qspi.c
|
||||
* @version V1.00
|
||||
* @brief M031 series QSPI driver source file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "M031Series.h"
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Driver QSPI Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function make QSPI module be ready to transfer.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @param[in] u32MasterSlave Decides the QSPI module is operating in master mode or in slave mode. (QSPI_SLAVE, QSPI_MASTER)
|
||||
* @param[in] u32QSPIMode Decides the transfer timing. (QSPI_MODE_0, QSPI_MODE_1, QSPI_MODE_2, QSPI_MODE_3)
|
||||
* @param[in] u32DataWidth Decides the data width of a QSPI transaction.
|
||||
* @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz.
|
||||
* @return Actual frequency of QSPI peripheral clock.
|
||||
* @details By default, the QSPI transfer sequence is MSB first, the slave selection signal is active low and the automatic
|
||||
* slave selection function is disabled.
|
||||
* In Slave mode, the u32BusClock shall be NULL and the QSPI clock divider setting will be 0.
|
||||
* The actual clock rate may be different from the target QSPI clock rate.
|
||||
* For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the
|
||||
* actual QSPI clock rate will be 6MHz.
|
||||
* @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
|
||||
* @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
|
||||
* @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0.
|
||||
* @note In slave mode, the QSPI peripheral clock rate will be equal to APB clock rate.
|
||||
*/
|
||||
uint32_t QSPI_Open(QSPI_T *qspi,
|
||||
uint32_t u32MasterSlave,
|
||||
uint32_t u32QSPIMode,
|
||||
uint32_t u32DataWidth,
|
||||
uint32_t u32BusClock)
|
||||
{
|
||||
uint32_t u32ClkSrc = 0UL, u32Div, u32HCLKFreq, u32RetValue = 0UL;
|
||||
|
||||
if (u32DataWidth == 32UL)
|
||||
{
|
||||
u32DataWidth = 0UL;
|
||||
}
|
||||
|
||||
/* Get system clock frequency */
|
||||
u32HCLKFreq = CLK_GetHCLKFreq();
|
||||
|
||||
if (u32MasterSlave == QSPI_MASTER)
|
||||
{
|
||||
/* Default setting: slave selection signal is active low; disable automatic slave selection function. */
|
||||
qspi->SSCTL = QSPI_SS_ACTIVE_LOW;
|
||||
|
||||
/* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
|
||||
qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_SPIEN_Msk;
|
||||
|
||||
if (u32BusClock >= u32HCLKFreq)
|
||||
{
|
||||
/* Select PCLK as the clock source of QSPI */
|
||||
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
|
||||
}
|
||||
|
||||
/* Check clock source of QSPI */
|
||||
if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
|
||||
{
|
||||
u32ClkSrc = __HXT; /* Clock source is HXT */
|
||||
}
|
||||
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
|
||||
{
|
||||
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
|
||||
}
|
||||
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
|
||||
{
|
||||
/* Clock source is PCLK0 */
|
||||
u32ClkSrc = CLK_GetPCLK0Freq();
|
||||
}
|
||||
else
|
||||
{
|
||||
u32ClkSrc = __HIRC; /* Clock source is HIRC */
|
||||
}
|
||||
|
||||
if (u32BusClock >= u32HCLKFreq)
|
||||
{
|
||||
/* Set DIVIDER = 0 */
|
||||
qspi->CLKDIV = 0UL;
|
||||
/* Return master peripheral clock rate */
|
||||
u32RetValue = u32ClkSrc;
|
||||
}
|
||||
else if (u32BusClock >= u32ClkSrc)
|
||||
{
|
||||
/* Set DIVIDER = 0 */
|
||||
qspi->CLKDIV = 0UL;
|
||||
/* Return master peripheral clock rate */
|
||||
u32RetValue = u32ClkSrc;
|
||||
}
|
||||
else if (u32BusClock == 0UL)
|
||||
{
|
||||
/* Set DIVIDER to the maximum value 0x1FF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */
|
||||
qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
|
||||
/* Return master peripheral clock rate */
|
||||
u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */
|
||||
|
||||
if (u32Div > 0x1FFUL)
|
||||
{
|
||||
u32Div = 0x1FFUL;
|
||||
qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
|
||||
/* Return master peripheral clock rate */
|
||||
u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos);
|
||||
/* Return master peripheral clock rate */
|
||||
u32RetValue = (u32ClkSrc / (u32Div + 1UL));
|
||||
}
|
||||
}
|
||||
}
|
||||
else /* For slave mode, force the QSPI peripheral clock rate to equal APB clock rate. */
|
||||
{
|
||||
/* Default setting: slave selection signal is low level active. */
|
||||
qspi->SSCTL = QSPI_SS_ACTIVE_LOW;
|
||||
|
||||
/* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
|
||||
qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_SPIEN_Msk;
|
||||
|
||||
/* Set DIVIDER = 0 */
|
||||
qspi->CLKDIV = 0UL;
|
||||
|
||||
/* Select PCLK as the clock source of QSPI */
|
||||
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
|
||||
/* Return slave peripheral clock rate */
|
||||
u32RetValue = CLK_GetPCLK0Freq();
|
||||
}
|
||||
|
||||
return u32RetValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable QSPI controller.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None
|
||||
* @details This function will reset QSPI controller.
|
||||
*/
|
||||
void QSPI_Close(QSPI_T *qspi)
|
||||
{
|
||||
/* Reset QSPI */
|
||||
SYS->IPRST1 |= SYS_IPRST1_QSPI0RST_Msk;
|
||||
SYS->IPRST1 &= ~SYS_IPRST1_QSPI0RST_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear RX FIFO buffer.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None
|
||||
* @details This function will clear QSPI RX FIFO buffer. The RXEMPTY (QSPI_STATUS[8]) will be set to 1.
|
||||
*/
|
||||
void QSPI_ClearRxFIFO(QSPI_T *qspi)
|
||||
{
|
||||
qspi->FIFOCTL |= QSPI_FIFOCTL_RXFBCLR_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear TX FIFO buffer.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None
|
||||
* @details This function will clear QSPI TX FIFO buffer. The TXEMPTY (QSPI_STATUS[16]) will be set to 1.
|
||||
* @note The TX shift register will not be cleared.
|
||||
*/
|
||||
void QSPI_ClearTxFIFO(QSPI_T *qspi)
|
||||
{
|
||||
qspi->FIFOCTL |= QSPI_FIFOCTL_TXFBCLR_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the automatic slave selection function.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return None
|
||||
* @details This function will disable the automatic slave selection function and set slave selection signal to inactive state.
|
||||
*/
|
||||
void QSPI_DisableAutoSS(QSPI_T *qspi)
|
||||
{
|
||||
qspi->SSCTL &= ~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the automatic slave selection function.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @param[in] u32SSPinMask Specifies slave selection pins. (QSPI_SS)
|
||||
* @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (QSPI_SS_ACTIVE_HIGH, QSPI_SS_ACTIVE_LOW)
|
||||
* @return None
|
||||
* @details This function will enable the automatic slave selection function. Only available in Master mode.
|
||||
* The slave selection pin and the active level will be set in this function.
|
||||
*/
|
||||
void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
|
||||
{
|
||||
qspi->SSCTL = (qspi->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | QSPI_SSCTL_AUTOSS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the QSPI bus clock.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz.
|
||||
* @return Actual frequency of QSPI bus clock.
|
||||
* @details This function is only available in Master mode. The actual clock rate may be different from the target QSPI bus clock rate.
|
||||
* For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the actual QSPI bus clock
|
||||
* rate will be 6 MHz.
|
||||
* @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
|
||||
* @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
|
||||
* @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0.
|
||||
*/
|
||||
uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
|
||||
{
|
||||
uint32_t u32ClkSrc, u32HCLKFreq;
|
||||
uint32_t u32Div, u32RetValue;
|
||||
|
||||
/* Get system clock frequency */
|
||||
u32HCLKFreq = CLK_GetHCLKFreq();
|
||||
|
||||
if (u32BusClock >= u32HCLKFreq)
|
||||
{
|
||||
/* Select PCLK as the clock source of QSPI */
|
||||
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
|
||||
}
|
||||
|
||||
/* Check clock source of QSPI */
|
||||
if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
|
||||
{
|
||||
u32ClkSrc = __HXT; /* Clock source is HXT */
|
||||
}
|
||||
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
|
||||
{
|
||||
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
|
||||
}
|
||||
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
|
||||
{
|
||||
/* Clock source is PCLK0 */
|
||||
u32ClkSrc = CLK_GetPCLK0Freq();
|
||||
}
|
||||
else
|
||||
{
|
||||
u32ClkSrc = __HIRC; /* Clock source is HIRC */
|
||||
}
|
||||
|
||||
if (u32BusClock >= u32HCLKFreq)
|
||||
{
|
||||
/* Set DIVIDER = 0 */
|
||||
qspi->CLKDIV = 0UL;
|
||||
/* Return master peripheral clock rate */
|
||||
u32RetValue = u32ClkSrc;
|
||||
}
|
||||
else if (u32BusClock >= u32ClkSrc)
|
||||
{
|
||||
/* Set DIVIDER = 0 */
|
||||
qspi->CLKDIV = 0UL;
|
||||
/* Return master peripheral clock rate */
|
||||
u32RetValue = u32ClkSrc;
|
||||
}
|
||||
else if (u32BusClock == 0UL)
|
||||
{
|
||||
/* Set DIVIDER to the maximum value 0x1FF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */
|
||||
qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
|
||||
/* Return master peripheral clock rate */
|
||||
u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */
|
||||
|
||||
if (u32Div > 0x1FFUL)
|
||||
{
|
||||
u32Div = 0x1FFUL;
|
||||
qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
|
||||
/* Return master peripheral clock rate */
|
||||
u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos);
|
||||
/* Return master peripheral clock rate */
|
||||
u32RetValue = (u32ClkSrc / (u32Div + 1UL));
|
||||
}
|
||||
}
|
||||
|
||||
return u32RetValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure FIFO threshold setting.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7.
|
||||
* @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7.
|
||||
* @return None
|
||||
* @details Set TX FIFO threshold and RX FIFO threshold configurations.
|
||||
*/
|
||||
void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
|
||||
{
|
||||
qspi->FIFOCTL = (qspi->FIFOCTL & ~(QSPI_FIFOCTL_TXTH_Msk | QSPI_FIFOCTL_RXTH_Msk)) |
|
||||
(u32TxThreshold << QSPI_FIFOCTL_TXTH_Pos) |
|
||||
(u32RxThreshold << QSPI_FIFOCTL_RXTH_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the actual frequency of QSPI bus clock. Only available in Master mode.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @return Actual QSPI bus clock frequency in Hz.
|
||||
* @details This function will calculate the actual QSPI bus clock rate according to the QSPInSEL and DIVIDER settings. Only available in Master mode.
|
||||
*/
|
||||
uint32_t QSPI_GetBusClock(QSPI_T *qspi)
|
||||
{
|
||||
uint32_t u32Div;
|
||||
uint32_t u32ClkSrc;
|
||||
|
||||
/* Get DIVIDER setting */
|
||||
u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos;
|
||||
|
||||
/* Check clock source of QSPI */
|
||||
if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
|
||||
{
|
||||
u32ClkSrc = __HXT; /* Clock source is HXT */
|
||||
}
|
||||
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
|
||||
{
|
||||
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
|
||||
}
|
||||
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
|
||||
{
|
||||
/* Clock source is PCLK0 */
|
||||
u32ClkSrc = CLK_GetPCLK0Freq();
|
||||
}
|
||||
else
|
||||
{
|
||||
u32ClkSrc = __HIRC; /* Clock source is HIRC */
|
||||
}
|
||||
|
||||
/* Return QSPI bus clock rate */
|
||||
return (u32ClkSrc / (u32Div + 1UL));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt function.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @param[in] u32Mask The combination of all related interrupt enable bits.
|
||||
* Each bit corresponds to a interrupt enable bit.
|
||||
* This parameter decides which interrupts will be enabled. It is combination of:
|
||||
* - \ref QSPI_UNIT_INT_MASK
|
||||
* - \ref QSPI_SSACT_INT_MASK
|
||||
* - \ref QSPI_SSINACT_INT_MASK
|
||||
* - \ref QSPI_SLVUR_INT_MASK
|
||||
* - \ref QSPI_SLVBE_INT_MASK
|
||||
* - \ref QSPI_SLVTO_INT_MASK
|
||||
* - \ref QSPI_TXUF_INT_MASK
|
||||
* - \ref QSPI_FIFO_TXTH_INT_MASK
|
||||
* - \ref QSPI_FIFO_RXTH_INT_MASK
|
||||
* - \ref QSPI_FIFO_RXOV_INT_MASK
|
||||
* - \ref QSPI_FIFO_RXTO_INT_MASK
|
||||
*
|
||||
* @return None
|
||||
* @details Enable QSPI related interrupts specified by u32Mask parameter.
|
||||
*/
|
||||
void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask)
|
||||
{
|
||||
/* Enable unit transfer interrupt flag */
|
||||
if ((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
|
||||
{
|
||||
qspi->CTL |= QSPI_CTL_UNITIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable slave selection signal active interrupt flag */
|
||||
if ((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
|
||||
{
|
||||
qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable slave selection signal inactive interrupt flag */
|
||||
if ((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
|
||||
{
|
||||
qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable slave TX under run interrupt flag */
|
||||
if ((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
|
||||
{
|
||||
qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable slave bit count error interrupt flag */
|
||||
if ((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
|
||||
{
|
||||
qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable slave mode time-out interrupt flag */
|
||||
if ((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK)
|
||||
{
|
||||
qspi->SSCTL |= QSPI_SSCTL_SLVTOIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable slave TX underflow interrupt flag */
|
||||
if ((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
|
||||
{
|
||||
qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable TX threshold interrupt flag */
|
||||
if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
|
||||
{
|
||||
qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable RX threshold interrupt flag */
|
||||
if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
|
||||
{
|
||||
qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable RX overrun interrupt flag */
|
||||
if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
|
||||
{
|
||||
qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable RX time-out interrupt flag */
|
||||
if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
|
||||
{
|
||||
qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt function.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @param[in] u32Mask The combination of all related interrupt enable bits.
|
||||
* Each bit corresponds to a interrupt bit.
|
||||
* This parameter decides which interrupts will be disabled. It is combination of:
|
||||
* - \ref QSPI_UNIT_INT_MASK
|
||||
* - \ref QSPI_SSACT_INT_MASK
|
||||
* - \ref QSPI_SSINACT_INT_MASK
|
||||
* - \ref QSPI_SLVUR_INT_MASK
|
||||
* - \ref QSPI_SLVBE_INT_MASK
|
||||
* - \ref QSPI_SLVTO_INT_MASK
|
||||
* - \ref QSPI_TXUF_INT_MASK
|
||||
* - \ref QSPI_FIFO_TXTH_INT_MASK
|
||||
* - \ref QSPI_FIFO_RXTH_INT_MASK
|
||||
* - \ref QSPI_FIFO_RXOV_INT_MASK
|
||||
* - \ref QSPI_FIFO_RXTO_INT_MASK
|
||||
*
|
||||
* @return None
|
||||
* @details Disable QSPI related interrupts specified by u32Mask parameter.
|
||||
*/
|
||||
void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask)
|
||||
{
|
||||
/* Disable unit transfer interrupt flag */
|
||||
if ((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
|
||||
{
|
||||
qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable slave selection signal active interrupt flag */
|
||||
if ((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
|
||||
{
|
||||
qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable slave selection signal inactive interrupt flag */
|
||||
if ((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
|
||||
{
|
||||
qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable slave TX under run interrupt flag */
|
||||
if ((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
|
||||
{
|
||||
qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable slave bit count error interrupt flag */
|
||||
if ((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
|
||||
{
|
||||
qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable slave mode time-out interrupt flag */
|
||||
if ((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK)
|
||||
{
|
||||
qspi->SSCTL &= ~QSPI_SSCTL_SLVTOIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable slave TX underflow interrupt flag */
|
||||
if ((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
|
||||
{
|
||||
qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable TX threshold interrupt flag */
|
||||
if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
|
||||
{
|
||||
qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable RX threshold interrupt flag */
|
||||
if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
|
||||
{
|
||||
qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable RX overrun interrupt flag */
|
||||
if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
|
||||
{
|
||||
qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable RX time-out interrupt flag */
|
||||
if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
|
||||
{
|
||||
qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt flag.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @param[in] u32Mask The combination of all related interrupt sources.
|
||||
* Each bit corresponds to a interrupt source.
|
||||
* This parameter decides which interrupt flags will be read. It is combination of:
|
||||
* - \ref QSPI_UNIT_INT_MASK
|
||||
* - \ref QSPI_SSACT_INT_MASK
|
||||
* - \ref QSPI_SSINACT_INT_MASK
|
||||
* - \ref QSPI_SLVUR_INT_MASK
|
||||
* - \ref QSPI_SLVBE_INT_MASK
|
||||
* - \ref QSPI_SLVTO_INT_MASK
|
||||
* - \ref QSPI_TXUF_INT_MASK
|
||||
* - \ref QSPI_FIFO_TXTH_INT_MASK
|
||||
* - \ref QSPI_FIFO_RXTH_INT_MASK
|
||||
* - \ref QSPI_FIFO_RXOV_INT_MASK
|
||||
* - \ref QSPI_FIFO_RXTO_INT_MASK
|
||||
*
|
||||
* @return Interrupt flags of selected sources.
|
||||
* @details Get QSPI related interrupt flags specified by u32Mask parameter.
|
||||
*/
|
||||
uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask)
|
||||
{
|
||||
uint32_t u32IntFlag = 0U, u32TmpVal;
|
||||
|
||||
u32TmpVal = qspi->STATUS & QSPI_STATUS_UNITIF_Msk;
|
||||
|
||||
/* Check unit transfer interrupt flag */
|
||||
if ((u32Mask & QSPI_UNIT_INT_MASK) && (u32TmpVal))
|
||||
{
|
||||
u32IntFlag |= QSPI_UNIT_INT_MASK;
|
||||
}
|
||||
|
||||
u32TmpVal = qspi->STATUS & QSPI_STATUS_SSACTIF_Msk;
|
||||
|
||||
/* Check slave selection signal active interrupt flag */
|
||||
if ((u32Mask & QSPI_SSACT_INT_MASK) && (u32TmpVal))
|
||||
{
|
||||
u32IntFlag |= QSPI_SSACT_INT_MASK;
|
||||
}
|
||||
|
||||
u32TmpVal = qspi->STATUS & QSPI_STATUS_SSINAIF_Msk;
|
||||
|
||||
/* Check slave selection signal inactive interrupt flag */
|
||||
if ((u32Mask & QSPI_SSINACT_INT_MASK) && (u32TmpVal))
|
||||
{
|
||||
u32IntFlag |= QSPI_SSINACT_INT_MASK;
|
||||
}
|
||||
|
||||
u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVURIF_Msk;
|
||||
|
||||
/* Check slave TX under run interrupt flag */
|
||||
if ((u32Mask & QSPI_SLVUR_INT_MASK) && (u32TmpVal))
|
||||
{
|
||||
u32IntFlag |= QSPI_SLVUR_INT_MASK;
|
||||
}
|
||||
|
||||
u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVBEIF_Msk;
|
||||
|
||||
/* Check slave bit count error interrupt flag */
|
||||
if ((u32Mask & QSPI_SLVBE_INT_MASK) && (u32TmpVal))
|
||||
{
|
||||
u32IntFlag |= QSPI_SLVBE_INT_MASK;
|
||||
}
|
||||
|
||||
u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVTOIF_Msk;
|
||||
|
||||
/* Check slave mode time-out interrupt flag */
|
||||
if ((u32Mask & QSPI_SLVTO_INT_MASK) && (u32TmpVal))
|
||||
{
|
||||
u32IntFlag |= QSPI_SLVTO_INT_MASK;
|
||||
}
|
||||
|
||||
u32TmpVal = qspi->STATUS & QSPI_STATUS_TXUFIF_Msk;
|
||||
|
||||
/* Check slave TX underflow interrupt flag */
|
||||
if ((u32Mask & QSPI_TXUF_INT_MASK) && (u32TmpVal))
|
||||
{
|
||||
u32IntFlag |= QSPI_TXUF_INT_MASK;
|
||||
}
|
||||
|
||||
u32TmpVal = qspi->STATUS & QSPI_STATUS_TXTHIF_Msk;
|
||||
|
||||
/* Check TX threshold interrupt flag */
|
||||
if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32TmpVal))
|
||||
{
|
||||
u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK;
|
||||
}
|
||||
|
||||
u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTHIF_Msk;
|
||||
|
||||
/* Check RX threshold interrupt flag */
|
||||
if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32TmpVal))
|
||||
{
|
||||
u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK;
|
||||
}
|
||||
|
||||
u32TmpVal = qspi->STATUS & QSPI_STATUS_RXOVIF_Msk;
|
||||
|
||||
/* Check RX overrun interrupt flag */
|
||||
if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32TmpVal))
|
||||
{
|
||||
u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK;
|
||||
}
|
||||
|
||||
u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTOIF_Msk;
|
||||
|
||||
/* Check RX time-out interrupt flag */
|
||||
if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32TmpVal))
|
||||
{
|
||||
u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK;
|
||||
}
|
||||
|
||||
return u32IntFlag;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt flag.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @param[in] u32Mask The combination of all related interrupt sources.
|
||||
* Each bit corresponds to a interrupt source.
|
||||
* This parameter decides which interrupt flags will be cleared. It could be the combination of:
|
||||
* - \ref QSPI_UNIT_INT_MASK
|
||||
* - \ref QSPI_SSACT_INT_MASK
|
||||
* - \ref QSPI_SSINACT_INT_MASK
|
||||
* - \ref QSPI_SLVUR_INT_MASK
|
||||
* - \ref QSPI_SLVBE_INT_MASK
|
||||
* - \ref QSPI_SLVTO_INT_MASK
|
||||
* - \ref QSPI_TXUF_INT_MASK
|
||||
* - \ref QSPI_FIFO_RXOV_INT_MASK
|
||||
* - \ref QSPI_FIFO_RXTO_INT_MASK
|
||||
*
|
||||
* @return None
|
||||
* @details Clear QSPI related interrupt flags specified by u32Mask parameter.
|
||||
*/
|
||||
void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask)
|
||||
{
|
||||
if (u32Mask & QSPI_UNIT_INT_MASK)
|
||||
{
|
||||
qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
|
||||
}
|
||||
|
||||
if (u32Mask & QSPI_SSACT_INT_MASK)
|
||||
{
|
||||
qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
|
||||
}
|
||||
|
||||
if (u32Mask & QSPI_SSINACT_INT_MASK)
|
||||
{
|
||||
qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
|
||||
}
|
||||
|
||||
if (u32Mask & QSPI_SLVUR_INT_MASK)
|
||||
{
|
||||
qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
|
||||
}
|
||||
|
||||
if (u32Mask & QSPI_SLVBE_INT_MASK)
|
||||
{
|
||||
qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
|
||||
}
|
||||
|
||||
if (u32Mask & QSPI_SLVTO_INT_MASK)
|
||||
{
|
||||
qspi->STATUS = QSPI_STATUS_SLVTOIF_Msk; /* Clear slave mode time-out interrupt flag */
|
||||
}
|
||||
|
||||
if (u32Mask & QSPI_TXUF_INT_MASK)
|
||||
{
|
||||
qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
|
||||
}
|
||||
|
||||
if (u32Mask & QSPI_FIFO_RXOV_INT_MASK)
|
||||
{
|
||||
qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
|
||||
}
|
||||
|
||||
if (u32Mask & QSPI_FIFO_RXTO_INT_MASK)
|
||||
{
|
||||
qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get QSPI status.
|
||||
* @param[in] qspi The pointer of the specified QSPI module.
|
||||
* @param[in] u32Mask The combination of all related sources.
|
||||
* Each bit corresponds to a source.
|
||||
* This parameter decides which flags will be read. It is combination of:
|
||||
* - \ref QSPI_BUSY_MASK
|
||||
* - \ref QSPI_RX_EMPTY_MASK
|
||||
* - \ref QSPI_RX_FULL_MASK
|
||||
* - \ref QSPI_TX_EMPTY_MASK
|
||||
* - \ref QSPI_TX_FULL_MASK
|
||||
* - \ref QSPI_TXRX_RESET_MASK
|
||||
* - \ref QSPI_SPIEN_STS_MASK
|
||||
* - \ref QSPI_SSLINE_STS_MASK
|
||||
*
|
||||
* @return Flags of selected sources.
|
||||
* @details Get QSPI related status specified by u32Mask parameter.
|
||||
*/
|
||||
uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask)
|
||||
{
|
||||
uint32_t u32Flag = 0UL, u32TmpValue;
|
||||
|
||||
u32TmpValue = qspi->STATUS & QSPI_STATUS_BUSY_Msk;
|
||||
|
||||
/* Check busy status */
|
||||
if ((u32Mask & QSPI_BUSY_MASK) && (u32TmpValue))
|
||||
{
|
||||
u32Flag |= QSPI_BUSY_MASK;
|
||||
}
|
||||
|
||||
u32TmpValue = qspi->STATUS & QSPI_STATUS_RXEMPTY_Msk;
|
||||
|
||||
/* Check RX empty flag */
|
||||
if ((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpValue))
|
||||
{
|
||||
u32Flag |= QSPI_RX_EMPTY_MASK;
|
||||
}
|
||||
|
||||
u32TmpValue = qspi->STATUS & QSPI_STATUS_RXFULL_Msk;
|
||||
|
||||
/* Check RX full flag */
|
||||
if ((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpValue))
|
||||
{
|
||||
u32Flag |= QSPI_RX_FULL_MASK;
|
||||
}
|
||||
|
||||
u32TmpValue = qspi->STATUS & QSPI_STATUS_TXEMPTY_Msk;
|
||||
|
||||
/* Check TX empty flag */
|
||||
if ((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpValue))
|
||||
{
|
||||
u32Flag |= QSPI_TX_EMPTY_MASK;
|
||||
}
|
||||
|
||||
u32TmpValue = qspi->STATUS & QSPI_STATUS_TXFULL_Msk;
|
||||
|
||||
/* Check TX full flag */
|
||||
if ((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpValue))
|
||||
{
|
||||
u32Flag |= QSPI_TX_FULL_MASK;
|
||||
}
|
||||
|
||||
u32TmpValue = qspi->STATUS & QSPI_STATUS_TXRXRST_Msk;
|
||||
|
||||
/* Check TX/RX reset flag */
|
||||
if ((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpValue))
|
||||
{
|
||||
u32Flag |= QSPI_TXRX_RESET_MASK;
|
||||
}
|
||||
|
||||
u32TmpValue = qspi->STATUS & QSPI_STATUS_SPIENSTS_Msk;
|
||||
|
||||
/* Check SPIEN flag */
|
||||
if ((u32Mask & QSPI_SPIEN_STS_MASK) && (u32TmpValue))
|
||||
{
|
||||
u32Flag |= QSPI_SPIEN_STS_MASK;
|
||||
}
|
||||
|
||||
u32TmpValue = qspi->STATUS & QSPI_STATUS_SSLINE_Msk;
|
||||
|
||||
/* Check QSPIx_SS line status */
|
||||
if ((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpValue))
|
||||
{
|
||||
u32Flag |= QSPI_SSLINE_STS_MASK;
|
||||
}
|
||||
|
||||
return u32Flag;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group QSPI_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,782 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file rtc.c
|
||||
* @version V1.00
|
||||
* $Revision: 4 $
|
||||
* $Date: 18/04/25 11:43a $
|
||||
* @brief M031 series Real Time Clock(RTC) driver source file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "M031Series.h"
|
||||
|
||||
|
||||
/** @cond HIDDEN_SYMBOLS */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Macro, type and constant definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define RTC_GLOBALS
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Global file scope (static) variables */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
static volatile uint32_t g_u32HiYear, g_u32LoYear, g_u32HiMonth, g_u32LoMonth, g_u32HiDay, g_u32LoDay;
|
||||
static volatile uint32_t g_u32HiHour, g_u32LoHour, g_u32HiMin, g_u32LoMin, g_u32HiSec, g_u32LoSec;
|
||||
|
||||
/** @endcond HIDDEN_SYMBOLS */
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Driver RTC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize RTC module and start counting
|
||||
*
|
||||
* @param[in] psPt Specify the time property and current date and time. It includes: \n
|
||||
* u32Year: Year value, range between 2000 ~ 2099. \n
|
||||
* u32Month: Month value, range between 1 ~ 12. \n
|
||||
* u32Day: Day value, range between 1 ~ 31. \n
|
||||
* u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
|
||||
* RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
|
||||
* RTC_SATURDAY] \n
|
||||
* u32Hour: Hour value, range between 0 ~ 23. \n
|
||||
* u32Minute: Minute value, range between 0 ~ 59. \n
|
||||
* u32Second: Second value, range between 0 ~ 59. \n
|
||||
* u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
|
||||
* u8AmPm: [RTC_AM / RTC_PM] \n
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to: \n
|
||||
* 1. Write initial key to let RTC start count. \n
|
||||
* 2. Input parameter indicates start date/time. \n
|
||||
* 3. User has to make sure that parameters of RTC date/time are reasonable. \n
|
||||
* @note Null pointer for using default starting date/time.
|
||||
*/
|
||||
void RTC_Open(S_RTC_TIME_DATA_T *psPt)
|
||||
{
|
||||
RTC->INIT = RTC_INIT_KEY;
|
||||
|
||||
if (RTC->INIT != RTC_INIT_ACTIVE_Msk)
|
||||
{
|
||||
RTC->INIT = RTC_INIT_KEY;
|
||||
|
||||
while (RTC->INIT != RTC_INIT_ACTIVE_Msk)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
if (psPt == NULL)
|
||||
{
|
||||
/* No RTC date/time data */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set RTC date and time */
|
||||
RTC_SetDateAndTime(psPt);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable RTC Clock
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API will disable RTC peripheral clock and stops RTC counting.
|
||||
*/
|
||||
void RTC_Close(void)
|
||||
{
|
||||
CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Frequency Compensation Data
|
||||
*
|
||||
* @param[in] i32FrequencyX10000 Specify the RTC clock X 10000, ex: 327736512 means 32773.6512.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*/
|
||||
void RTC_32KCalibration(int32_t i32FrequencyX10000)
|
||||
{
|
||||
|
||||
/*
|
||||
Frequency counter measurement : 32773.6512 Hz
|
||||
*/
|
||||
uint32_t u32Index;
|
||||
uint32_t u32Compensate;
|
||||
|
||||
/* 327736512 %10000 = 6512 */
|
||||
u32Compensate = (uint32_t)(i32FrequencyX10000 % 10000);
|
||||
/*Fraction Part: (6512 X 64)/10000 = 41.6768(0x2A) => RTC_FREQADJ[5:0]=0x2A*/
|
||||
u32Compensate = ((u32Compensate * 64) / 10000);
|
||||
u32Compensate &= 0x3F;
|
||||
/*
|
||||
Formula for 32K compensation is
|
||||
FREQADJ = 0~0x00001F00 (Frequency range : 32752Hz ~ 32783Hz)
|
||||
*/
|
||||
|
||||
if (i32FrequencyX10000 >= (uint32_t)327840000)
|
||||
{
|
||||
u32Compensate = 0x1F3F;
|
||||
}
|
||||
else if (i32FrequencyX10000 < (uint32_t)327520000)
|
||||
{
|
||||
u32Compensate = 0x0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Integer Part: 32773 => RTC_FREQADJ[12:8] = 0x15 */
|
||||
for (u32Index = 0; u32Index < 0x20 ; u32Index++)
|
||||
{
|
||||
if ((i32FrequencyX10000 >= 327520000 + (u32Index * 10000)) && (i32FrequencyX10000 < 327520000 + ((u32Index + 1) * 10000)))
|
||||
{
|
||||
u32Compensate += (u32Index << RTC_FREQADJ_INTEGER_Pos);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
RTC->FREQADJ = (uint32_t)u32Compensate;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Current RTC Date and Time
|
||||
*
|
||||
* @param[out] psPt The returned pointer is specified the current RTC value. It includes: \n
|
||||
* u32Year: Year value \n
|
||||
* u32Month: Month value \n
|
||||
* u32Day: Day value \n
|
||||
* u32DayOfWeek: Day of week \n
|
||||
* u32Hour: Hour value \n
|
||||
* u32Minute: Minute value \n
|
||||
* u32Second: Second value \n
|
||||
* u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
|
||||
* u8AmPm: [RTC_AM / RTC_PM] \n
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to get the current RTC date and time value.
|
||||
*/
|
||||
void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *psPt)
|
||||
{
|
||||
uint32_t u32Tmp;
|
||||
|
||||
psPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */
|
||||
psPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
|
||||
|
||||
/* Get [Date digit] data */
|
||||
g_u32HiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos;
|
||||
g_u32LoYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos;
|
||||
g_u32HiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos;
|
||||
g_u32LoMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos;
|
||||
g_u32HiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos;
|
||||
g_u32LoDay = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos;
|
||||
|
||||
/* Get [Time digit] data */
|
||||
g_u32HiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos;
|
||||
g_u32LoHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos;
|
||||
g_u32HiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos;
|
||||
g_u32LoMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos;
|
||||
g_u32HiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos;
|
||||
g_u32LoSec = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos;
|
||||
|
||||
/* Compute to 20XX year */
|
||||
u32Tmp = (g_u32HiYear * 10ul);
|
||||
u32Tmp += g_u32LoYear;
|
||||
psPt->u32Year = u32Tmp + RTC_YEAR2000;
|
||||
|
||||
/* Compute 0~12 month */
|
||||
u32Tmp = (g_u32HiMonth * 10ul);
|
||||
psPt->u32Month = u32Tmp + g_u32LoMonth;
|
||||
|
||||
/* Compute 0~31 day */
|
||||
u32Tmp = (g_u32HiDay * 10ul);
|
||||
psPt->u32Day = u32Tmp + g_u32LoDay;
|
||||
|
||||
/* Compute 12/24 hour */
|
||||
if (psPt->u32TimeScale == RTC_CLOCK_12)
|
||||
{
|
||||
u32Tmp = (g_u32HiHour * 10ul);
|
||||
u32Tmp += g_u32LoHour;
|
||||
psPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
|
||||
|
||||
if (psPt->u32Hour >= 21ul)
|
||||
{
|
||||
psPt->u32AmPm = RTC_PM;
|
||||
psPt->u32Hour -= 20ul;
|
||||
}
|
||||
else
|
||||
{
|
||||
psPt->u32AmPm = RTC_AM;
|
||||
}
|
||||
|
||||
u32Tmp = (g_u32HiMin * 10ul);
|
||||
u32Tmp += g_u32LoMin;
|
||||
psPt->u32Minute = u32Tmp;
|
||||
|
||||
u32Tmp = (g_u32HiSec * 10ul);
|
||||
u32Tmp += g_u32LoSec;
|
||||
psPt->u32Second = u32Tmp;
|
||||
}
|
||||
else
|
||||
{
|
||||
u32Tmp = (g_u32HiHour * 10ul);
|
||||
u32Tmp += g_u32LoHour;
|
||||
psPt->u32Hour = u32Tmp;
|
||||
|
||||
u32Tmp = (g_u32HiMin * 10ul);
|
||||
u32Tmp += g_u32LoMin;
|
||||
psPt->u32Minute = u32Tmp;
|
||||
|
||||
u32Tmp = (g_u32HiSec * 10ul);
|
||||
u32Tmp += g_u32LoSec;
|
||||
psPt->u32Second = u32Tmp;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get RTC Alarm Date and Time
|
||||
*
|
||||
* @param[out] psPt The returned pointer is specified the RTC alarm value. It includes: \n
|
||||
* u32Year: Year value \n
|
||||
* u32Month: Month value \n
|
||||
* u32Day: Day value \n
|
||||
* u32DayOfWeek: Day of week \n
|
||||
* u32Hour: Hour value \n
|
||||
* u32Minute: Minute value \n
|
||||
* u32Second: Second value \n
|
||||
* u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
|
||||
* u8AmPm: [RTC_AM / RTC_PM] \n
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to get the RTC alarm date and time setting.
|
||||
*/
|
||||
void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *psPt)
|
||||
{
|
||||
uint32_t u32Tmp;
|
||||
|
||||
psPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */
|
||||
psPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
|
||||
|
||||
/* Get alarm [Date digit] data */
|
||||
g_u32HiYear = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos;
|
||||
g_u32LoYear = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos;
|
||||
g_u32HiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos;
|
||||
g_u32LoMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos;
|
||||
g_u32HiDay = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos;
|
||||
g_u32LoDay = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos;
|
||||
|
||||
/* Get alarm [Time digit] data */
|
||||
g_u32HiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos;
|
||||
g_u32LoHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos;
|
||||
g_u32HiMin = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos;
|
||||
g_u32LoMin = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos;
|
||||
g_u32HiSec = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos;
|
||||
g_u32LoSec = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos;
|
||||
|
||||
/* Compute to 20XX year */
|
||||
u32Tmp = (g_u32HiYear * 10ul);
|
||||
u32Tmp += g_u32LoYear;
|
||||
psPt->u32Year = u32Tmp + RTC_YEAR2000;
|
||||
|
||||
/* Compute 0~12 month */
|
||||
u32Tmp = (g_u32HiMonth * 10ul);
|
||||
psPt->u32Month = u32Tmp + g_u32LoMonth;
|
||||
|
||||
/* Compute 0~31 day */
|
||||
u32Tmp = (g_u32HiDay * 10ul);
|
||||
psPt->u32Day = u32Tmp + g_u32LoDay;
|
||||
|
||||
/* Compute 12/24 hour */
|
||||
if (psPt->u32TimeScale == RTC_CLOCK_12)
|
||||
{
|
||||
u32Tmp = (g_u32HiHour * 10ul);
|
||||
u32Tmp += g_u32LoHour;
|
||||
psPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
|
||||
|
||||
if (psPt->u32Hour >= 21ul)
|
||||
{
|
||||
psPt->u32AmPm = RTC_PM;
|
||||
psPt->u32Hour -= 20ul;
|
||||
}
|
||||
else
|
||||
{
|
||||
psPt->u32AmPm = RTC_AM;
|
||||
}
|
||||
|
||||
u32Tmp = (g_u32HiMin * 10ul);
|
||||
u32Tmp += g_u32LoMin;
|
||||
psPt->u32Minute = u32Tmp;
|
||||
|
||||
u32Tmp = (g_u32HiSec * 10ul);
|
||||
u32Tmp += g_u32LoSec;
|
||||
psPt->u32Second = u32Tmp;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
u32Tmp = (g_u32HiHour * 10ul);
|
||||
u32Tmp += g_u32LoHour;
|
||||
psPt->u32Hour = u32Tmp;
|
||||
|
||||
u32Tmp = (g_u32HiMin * 10ul);
|
||||
u32Tmp += g_u32LoMin;
|
||||
psPt->u32Minute = u32Tmp;
|
||||
|
||||
u32Tmp = (g_u32HiSec * 10ul);
|
||||
u32Tmp += g_u32LoSec;
|
||||
psPt->u32Second = u32Tmp;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update Current RTC Date and Time
|
||||
*
|
||||
* @param[in] psPt Specify the time property and current date and time. It includes: \n
|
||||
* u32Year: Year value, range between 2000 ~ 2099. \n
|
||||
* u32Month: Month value, range between 1 ~ 12. \n
|
||||
* u32Day: Day value, range between 1 ~ 31. \n
|
||||
* u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
|
||||
* RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
|
||||
* RTC_SATURDAY] \n
|
||||
* u32Hour: Hour value, range between 0 ~ 23. \n
|
||||
* u32Minute: Minute value, range between 0 ~ 59. \n
|
||||
* u32Second: Second value, range between 0 ~ 59. \n
|
||||
* u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
|
||||
* u8AmPm: [RTC_AM / RTC_PM] \n
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to update current date and time to RTC.
|
||||
*/
|
||||
void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *psPt)
|
||||
{
|
||||
uint32_t u32RegCAL, u32RegTIME;
|
||||
|
||||
if (psPt == NULL)
|
||||
{
|
||||
/* No RTC date/time data */
|
||||
}
|
||||
else
|
||||
{
|
||||
/*-----------------------------------------------------------------------------------------------------*/
|
||||
/* Set RTC 24/12 hour setting and Day of the Week */
|
||||
/*-----------------------------------------------------------------------------------------------------*/
|
||||
|
||||
if (psPt->u32TimeScale == RTC_CLOCK_12)
|
||||
{
|
||||
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
|
||||
|
||||
/*-------------------------------------------------------------------------------------------------*/
|
||||
/* Important, range of 12-hour PM mode is 21 up to 32 */
|
||||
/*-------------------------------------------------------------------------------------------------*/
|
||||
if (psPt->u32AmPm == RTC_PM)
|
||||
{
|
||||
psPt->u32Hour += 20ul;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
|
||||
}
|
||||
|
||||
/* Set Day of the Week */
|
||||
RTC->WEEKDAY = psPt->u32DayOfWeek;
|
||||
|
||||
/*-----------------------------------------------------------------------------------------------------*/
|
||||
/* Set RTC Current Date and Time */
|
||||
/*-----------------------------------------------------------------------------------------------------*/
|
||||
u32RegCAL = ((psPt->u32Year - RTC_YEAR2000) / 10ul) << 20;
|
||||
u32RegCAL |= (((psPt->u32Year - RTC_YEAR2000) % 10ul) << 16);
|
||||
u32RegCAL |= ((psPt->u32Month / 10ul) << 12);
|
||||
u32RegCAL |= ((psPt->u32Month % 10ul) << 8);
|
||||
u32RegCAL |= ((psPt->u32Day / 10ul) << 4);
|
||||
u32RegCAL |= (psPt->u32Day % 10ul);
|
||||
|
||||
u32RegTIME = ((psPt->u32Hour / 10ul) << 20);
|
||||
u32RegTIME |= ((psPt->u32Hour % 10ul) << 16);
|
||||
u32RegTIME |= ((psPt->u32Minute / 10ul) << 12);
|
||||
u32RegTIME |= ((psPt->u32Minute % 10ul) << 8);
|
||||
u32RegTIME |= ((psPt->u32Second / 10ul) << 4);
|
||||
u32RegTIME |= (psPt->u32Second % 10ul);
|
||||
|
||||
/*-----------------------------------------------------------------------------------------------------*/
|
||||
/* Set RTC Calender and Time Loading */
|
||||
/*-----------------------------------------------------------------------------------------------------*/
|
||||
|
||||
RTC->CAL = (uint32_t)u32RegCAL;
|
||||
RTC->TIME = (uint32_t)u32RegTIME;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update RTC Alarm Date and Time
|
||||
*
|
||||
* @param[in] psPt Specify the time property and alarm date and time. It includes: \n
|
||||
* u32Year: Year value, range between 2000 ~ 2099. \n
|
||||
* u32Month: Month value, range between 1 ~ 12. \n
|
||||
* u32Day: Day value, range between 1 ~ 31. \n
|
||||
* u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
|
||||
* RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
|
||||
* RTC_SATURDAY] \n
|
||||
* u32Hour: Hour value, range between 0 ~ 23. \n
|
||||
* u32Minute: Minute value, range between 0 ~ 59. \n
|
||||
* u32Second: Second value, range between 0 ~ 59. \n
|
||||
* u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
|
||||
* u8AmPm: [RTC_AM / RTC_PM] \n
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to update alarm date and time setting to RTC.
|
||||
*/
|
||||
void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *psPt)
|
||||
{
|
||||
uint32_t u32RegCALM, u32RegTALM;
|
||||
|
||||
if (psPt == NULL)
|
||||
{
|
||||
/* No RTC date/time data */
|
||||
}
|
||||
else
|
||||
{
|
||||
/*-----------------------------------------------------------------------------------------------------*/
|
||||
/* Set RTC 24/12 hour setting and Day of the Week */
|
||||
/*-----------------------------------------------------------------------------------------------------*/
|
||||
|
||||
if (psPt->u32TimeScale == RTC_CLOCK_12)
|
||||
{
|
||||
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
|
||||
|
||||
/*-------------------------------------------------------------------------------------------------*/
|
||||
/* Important, range of 12-hour PM mode is 21 up to 32 */
|
||||
/*-------------------------------------------------------------------------------------------------*/
|
||||
if (psPt->u32AmPm == RTC_PM)
|
||||
{
|
||||
psPt->u32Hour += 20ul;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------------------------------*/
|
||||
/* Set RTC Alarm Date and Time */
|
||||
/*-----------------------------------------------------------------------------------------------------*/
|
||||
u32RegCALM = ((psPt->u32Year - RTC_YEAR2000) / 10ul) << 20;
|
||||
u32RegCALM |= (((psPt->u32Year - RTC_YEAR2000) % 10ul) << 16);
|
||||
u32RegCALM |= ((psPt->u32Month / 10ul) << 12);
|
||||
u32RegCALM |= ((psPt->u32Month % 10ul) << 8);
|
||||
u32RegCALM |= ((psPt->u32Day / 10ul) << 4);
|
||||
u32RegCALM |= (psPt->u32Day % 10ul);
|
||||
|
||||
u32RegTALM = ((psPt->u32Hour / 10ul) << 20);
|
||||
u32RegTALM |= ((psPt->u32Hour % 10ul) << 16);
|
||||
u32RegTALM |= ((psPt->u32Minute / 10ul) << 12);
|
||||
u32RegTALM |= ((psPt->u32Minute % 10ul) << 8);
|
||||
u32RegTALM |= ((psPt->u32Second / 10ul) << 4);
|
||||
u32RegTALM |= (psPt->u32Second % 10ul);
|
||||
|
||||
|
||||
RTC->CALM = (uint32_t)u32RegCALM;
|
||||
RTC->TALM = (uint32_t)u32RegTALM;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update RTC Current Date
|
||||
*
|
||||
* @param[in] u32Year The year calendar digit of current RTC setting.
|
||||
* @param[in] u32Month The month calendar digit of current RTC setting.
|
||||
* @param[in] u32Day The day calendar digit of current RTC setting.
|
||||
* @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
|
||||
* RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
|
||||
* RTC_SATURDAY]
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to update current date to RTC.
|
||||
*/
|
||||
void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek)
|
||||
{
|
||||
uint32_t u32RegCAL;
|
||||
|
||||
u32RegCAL = ((u32Year - RTC_YEAR2000) / 10ul) << 20;
|
||||
u32RegCAL |= (((u32Year - RTC_YEAR2000) % 10ul) << 16);
|
||||
u32RegCAL |= ((u32Month / 10ul) << 12);
|
||||
u32RegCAL |= ((u32Month % 10ul) << 8);
|
||||
u32RegCAL |= ((u32Day / 10ul) << 4);
|
||||
u32RegCAL |= (u32Day % 10ul);
|
||||
|
||||
/* Set Day of the Week */
|
||||
RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk;
|
||||
|
||||
/* Set RTC Calender Loading */
|
||||
RTC->CAL = (uint32_t)u32RegCAL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update RTC Current Time
|
||||
*
|
||||
* @param[in] u32Hour The hour time digit of current RTC setting.
|
||||
* @param[in] u32Minute The minute time digit of current RTC setting.
|
||||
* @param[in] u32Second The second time digit of current RTC setting.
|
||||
* @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
|
||||
* @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to update current time to RTC.
|
||||
*/
|
||||
void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
|
||||
{
|
||||
uint32_t u32RegTIME;
|
||||
|
||||
/* Important, range of 12-hour PM mode is 21 up to 32 */
|
||||
if ((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
|
||||
{
|
||||
u32Hour += 20ul;
|
||||
}
|
||||
|
||||
u32RegTIME = ((u32Hour / 10ul) << 20);
|
||||
u32RegTIME |= ((u32Hour % 10ul) << 16);
|
||||
u32RegTIME |= ((u32Minute / 10ul) << 12);
|
||||
u32RegTIME |= ((u32Minute % 10ul) << 8);
|
||||
u32RegTIME |= ((u32Second / 10ul) << 4);
|
||||
u32RegTIME |= (u32Second % 10ul);
|
||||
|
||||
/*-----------------------------------------------------------------------------------------------------*/
|
||||
/* Set RTC 24/12 hour setting and Day of the Week */
|
||||
/*-----------------------------------------------------------------------------------------------------*/
|
||||
if (u32TimeMode == RTC_CLOCK_12)
|
||||
{
|
||||
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
|
||||
}
|
||||
else
|
||||
{
|
||||
RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
|
||||
}
|
||||
|
||||
RTC->TIME = (uint32_t)u32RegTIME;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update RTC Alarm Date
|
||||
*
|
||||
* @param[in] u32Year The year calendar digit of RTC alarm setting.
|
||||
* @param[in] u32Month The month calendar digit of RTC alarm setting.
|
||||
* @param[in] u32Day The day calendar digit of RTC alarm setting.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to update alarm date setting to RTC.
|
||||
*/
|
||||
void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day)
|
||||
{
|
||||
uint32_t u32RegCALM;
|
||||
|
||||
u32RegCALM = ((u32Year - RTC_YEAR2000) / 10ul) << 20;
|
||||
u32RegCALM |= (((u32Year - RTC_YEAR2000) % 10ul) << 16);
|
||||
u32RegCALM |= ((u32Month / 10ul) << 12);
|
||||
u32RegCALM |= ((u32Month % 10ul) << 8);
|
||||
u32RegCALM |= ((u32Day / 10ul) << 4);
|
||||
u32RegCALM |= (u32Day % 10ul);
|
||||
|
||||
/* Set RTC Alarm Date */
|
||||
RTC->CALM = (uint32_t)u32RegCALM;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update RTC Alarm Time
|
||||
*
|
||||
* @param[in] u32Hour The hour time digit of RTC alarm setting.
|
||||
* @param[in] u32Minute The minute time digit of RTC alarm setting.
|
||||
* @param[in] u32Second The second time digit of RTC alarm setting.
|
||||
* @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
|
||||
* @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to update alarm time setting to RTC.
|
||||
*/
|
||||
void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
|
||||
{
|
||||
uint32_t u32RegTALM;
|
||||
|
||||
/* Important, range of 12-hour PM mode is 21 up to 32 */
|
||||
if((u32TimeMode == (uint32_t)RTC_CLOCK_12) && (u32AmPm == (uint32_t)RTC_PM))
|
||||
{
|
||||
u32Hour += 20ul;
|
||||
}
|
||||
|
||||
u32RegTALM = ((u32Hour / 10ul) << 20);
|
||||
u32RegTALM |= ((u32Hour % 10ul) << 16);
|
||||
u32RegTALM |= ((u32Minute / 10ul) << 12);
|
||||
u32RegTALM |= ((u32Minute % 10ul) << 8);
|
||||
u32RegTALM |= ((u32Second / 10ul) << 4);
|
||||
u32RegTALM |= (u32Second % 10ul);
|
||||
|
||||
/*-----------------------------------------------------------------------------------------------------*/
|
||||
/* Set RTC 24/12 hour setting and Day of the Week */
|
||||
/*-----------------------------------------------------------------------------------------------------*/
|
||||
if(u32TimeMode == (uint32_t)RTC_CLOCK_12)
|
||||
{
|
||||
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
|
||||
}
|
||||
else
|
||||
{
|
||||
RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
|
||||
}
|
||||
|
||||
/* Set RTC Alarm Time */
|
||||
RTC->TALM = (uint32_t)u32RegTALM;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set RTC Alarm Date Mask Function
|
||||
*
|
||||
* @param[in] u8IsTenYMsk 1: enable 10-Year digit alarm mask; 0: disabled.
|
||||
* @param[in] u8IsYMsk 1: enable 1-Year digit alarm mask; 0: disabled.
|
||||
* @param[in] u8IsTenMMsk 1: enable 10-Mon digit alarm mask; 0: disabled.
|
||||
* @param[in] u8IsMMsk 1: enable 1-Mon digit alarm mask; 0: disabled.
|
||||
* @param[in] u8IsTenDMsk 1: enable 10-Day digit alarm mask; 0: disabled.
|
||||
* @param[in] u8IsDMsk 1: enable 1-Day digit alarm mask; 0: disabled.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to enable or disable RTC alarm date mask function.
|
||||
*/
|
||||
void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk)
|
||||
{
|
||||
RTC->CAMSK = ((uint32_t)u8IsTenYMsk << RTC_CAMSK_MTENYEAR_Pos) |
|
||||
((uint32_t)u8IsYMsk << RTC_CAMSK_MYEAR_Pos) |
|
||||
((uint32_t)u8IsTenMMsk << RTC_CAMSK_MTENMON_Pos) |
|
||||
((uint32_t)u8IsMMsk << RTC_CAMSK_MMON_Pos) |
|
||||
((uint32_t)u8IsTenDMsk << RTC_CAMSK_MTENDAY_Pos) |
|
||||
((uint32_t)u8IsDMsk << RTC_CAMSK_MDAY_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set RTC Alarm Time Mask Function
|
||||
*
|
||||
* @param[in] u8IsTenHMsk 1: enable 10-Hour digit alarm mask; 0: disabled.
|
||||
* @param[in] u8IsHMsk 1: enable 1-Hour digit alarm mask; 0: disabled.
|
||||
* @param[in] u8IsTenMMsk 1: enable 10-Min digit alarm mask; 0: disabled.
|
||||
* @param[in] u8IsMMsk 1: enable 1-Min digit alarm mask; 0: disabled.
|
||||
* @param[in] u8IsTenSMsk 1: enable 10-Sec digit alarm mask; 0: disabled.
|
||||
* @param[in] u8IsSMsk 1: enable 1-Sec digit alarm mask; 0: disabled.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to enable or disable RTC alarm time mask function.
|
||||
*/
|
||||
void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk)
|
||||
{
|
||||
RTC->TAMSK = ((uint32_t)u8IsTenHMsk << RTC_TAMSK_MTENHR_Pos) |
|
||||
((uint32_t)u8IsHMsk << RTC_TAMSK_MHR_Pos) |
|
||||
((uint32_t)u8IsTenMMsk << RTC_TAMSK_MTENMIN_Pos) |
|
||||
((uint32_t)u8IsMMsk << RTC_TAMSK_MMIN_Pos) |
|
||||
((uint32_t)u8IsTenSMsk << RTC_TAMSK_MTENSEC_Pos) |
|
||||
((uint32_t)u8IsSMsk << RTC_TAMSK_MSEC_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Day of the Week
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 0 Sunday
|
||||
* @retval 1 Monday
|
||||
* @retval 2 Tuesday
|
||||
* @retval 3 Wednesday
|
||||
* @retval 4 Thursday
|
||||
* @retval 5 Friday
|
||||
* @retval 6 Saturday
|
||||
*
|
||||
* @details This API is used to get day of the week of current RTC date.
|
||||
*/
|
||||
uint32_t RTC_GetDayOfWeek(void)
|
||||
{
|
||||
return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set RTC Tick Period Time
|
||||
*
|
||||
* @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n
|
||||
* It consists of:
|
||||
* - \ref RTC_TICK_1_SEC : Time tick is 1 second
|
||||
* - \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second
|
||||
* - \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second
|
||||
* - \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second
|
||||
* - \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second
|
||||
* - \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second
|
||||
* - \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second
|
||||
* - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to set RTC tick period time for each tick interrupt.
|
||||
*/
|
||||
void RTC_SetTickPeriod(uint32_t u32TickSelection)
|
||||
{
|
||||
RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable RTC Interrupt
|
||||
*
|
||||
* @param[in] u32IntFlagMask Specify the interrupt source. It consists of:
|
||||
* - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt
|
||||
* - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to enable the specify RTC interrupt function.
|
||||
*/
|
||||
void RTC_EnableInt(uint32_t u32IntFlagMask)
|
||||
{
|
||||
RTC->INTEN |= u32IntFlagMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable RTC Interrupt
|
||||
*
|
||||
* @param[in] u32IntFlagMask Specify the interrupt source. It consists of:
|
||||
* - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt
|
||||
* - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to disable the specify RTC interrupt function.
|
||||
*/
|
||||
void RTC_DisableInt(uint32_t u32IntFlagMask)
|
||||
{
|
||||
RTC->INTEN &= ~u32IntFlagMask;
|
||||
RTC->INTSTS = u32IntFlagMask;
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group RTC_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
||||
|
|
@ -1,934 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file spi.c
|
||||
* @version V1.00
|
||||
* $Revision: 4 $
|
||||
* $Date: 18/04/25 11:43a $
|
||||
* @brief M031 series SPI driver source file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "M031Series.h"
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Driver SPI Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function make SPI module be ready to transfer.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER)
|
||||
* @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3)
|
||||
* @param[in] u32DataWidth Decides the data width of a SPI transaction.
|
||||
* @param[in] u32BusClock The expected frequency of SPI bus clock in Hz.
|
||||
* @return Actual frequency of SPI peripheral clock.
|
||||
* @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic
|
||||
* slave selection function is disabled.
|
||||
* In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0.
|
||||
* The actual clock rate may be different from the target SPI clock rate.
|
||||
* For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the
|
||||
* actual SPI clock rate will be 6MHz.
|
||||
* @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
|
||||
* @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
|
||||
* @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.
|
||||
* @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate.
|
||||
*/
|
||||
uint32_t SPI_Open(SPI_T *spi,
|
||||
uint32_t u32MasterSlave,
|
||||
uint32_t u32SPIMode,
|
||||
uint32_t u32DataWidth,
|
||||
uint32_t u32BusClock)
|
||||
{
|
||||
uint32_t u32ClkSrc = 0, u32Div, u32HCLKFreq;
|
||||
|
||||
/* check SPI interface */
|
||||
if (spi != SPI0) return SPI_NONE;
|
||||
|
||||
/* Disable I2S mode */
|
||||
spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
|
||||
|
||||
if (u32DataWidth == 32)
|
||||
u32DataWidth = 0;
|
||||
|
||||
/* Get system clock frequency */
|
||||
u32HCLKFreq = CLK_GetHCLKFreq();
|
||||
|
||||
if (u32MasterSlave == SPI_MASTER)
|
||||
{
|
||||
/* Default setting: slave selection signal is active low; disable automatic slave selection function. */
|
||||
spi->SSCTL = SPI_SS_ACTIVE_LOW;
|
||||
|
||||
/* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
|
||||
spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
|
||||
|
||||
if (u32BusClock >= u32HCLKFreq)
|
||||
{
|
||||
/* Select PCLK as the clock source of SPI */
|
||||
if (spi == SPI0)
|
||||
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;
|
||||
}
|
||||
|
||||
/* Check clock source of SPI */
|
||||
if (spi == SPI0)
|
||||
{
|
||||
if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
|
||||
u32ClkSrc = __HXT; /* Clock source is HXT */
|
||||
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
|
||||
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
|
||||
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1)
|
||||
u32ClkSrc = u32HCLKFreq / ((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) + 1);
|
||||
else
|
||||
u32ClkSrc = 48000000; /* Clock source is HIRC48 */
|
||||
}
|
||||
|
||||
if (u32BusClock >= u32HCLKFreq)
|
||||
{
|
||||
/* Set DIVIDER = 0 */
|
||||
spi->CLKDIV = 0;
|
||||
/* Return master peripheral clock rate */
|
||||
return u32ClkSrc;
|
||||
}
|
||||
else if (u32BusClock >= u32ClkSrc)
|
||||
{
|
||||
/* Set DIVIDER = 0 */
|
||||
spi->CLKDIV = 0;
|
||||
/* Return master peripheral clock rate */
|
||||
return u32ClkSrc;
|
||||
}
|
||||
else if (u32BusClock == 0)
|
||||
{
|
||||
/* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
|
||||
spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
|
||||
/* Return master peripheral clock rate */
|
||||
return (u32ClkSrc / (0xFF + 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
|
||||
if (u32Div > 0xFF)
|
||||
{
|
||||
u32Div = 0xFF;
|
||||
spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
|
||||
/* Return master peripheral clock rate */
|
||||
return (u32ClkSrc / (0xFF + 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
|
||||
/* Return master peripheral clock rate */
|
||||
return (u32ClkSrc / (u32Div + 1));
|
||||
}
|
||||
}
|
||||
}
|
||||
else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */
|
||||
{
|
||||
/* Default setting: slave selection signal is low level active. */
|
||||
spi->SSCTL = SPI_SS_ACTIVE_LOW;
|
||||
|
||||
/* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
|
||||
spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
|
||||
|
||||
/* Set DIVIDER = 0 */
|
||||
spi->CLKDIV = 0;
|
||||
|
||||
/* Select PCLK as the clock source of SPI */
|
||||
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;
|
||||
/* Return slave peripheral clock rate */
|
||||
return (CLK_GetHCLKFreq() / ((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) + 1));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SPI controller.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None
|
||||
* @details This function will reset SPI controller.
|
||||
*/
|
||||
void SPI_Close(SPI_T *spi)
|
||||
{
|
||||
if (spi == SPI0)
|
||||
{
|
||||
/* Reset SPI */
|
||||
SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
|
||||
SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear RX FIFO buffer.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None
|
||||
* @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1.
|
||||
*/
|
||||
void SPI_ClearRxFIFO(SPI_T *spi)
|
||||
{
|
||||
spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear TX FIFO buffer.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None
|
||||
* @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1.
|
||||
* @note The TX shift register will not be cleared.
|
||||
*/
|
||||
void SPI_ClearTxFIFO(SPI_T *spi)
|
||||
{
|
||||
spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the automatic slave selection function.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return None
|
||||
* @details This function will disable the automatic slave selection function and set slave selection signal to inactive state.
|
||||
*/
|
||||
void SPI_DisableAutoSS(SPI_T *spi)
|
||||
{
|
||||
spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the automatic slave selection function.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS)
|
||||
* @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW)
|
||||
* @return None
|
||||
* @details This function will enable the automatic slave selection function. Only available in Master mode.
|
||||
* The slave selection pin and the active level will be set in this function.
|
||||
*/
|
||||
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
|
||||
{
|
||||
spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the SPI bus clock.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @param[in] u32BusClock The expected frequency of SPI bus clock in Hz.
|
||||
* @return Actual frequency of SPI bus clock.
|
||||
* @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate.
|
||||
* For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the actual SPI bus clock
|
||||
* rate will be 6 MHz.
|
||||
* @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
|
||||
* @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
|
||||
* @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.
|
||||
*/
|
||||
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
|
||||
{
|
||||
uint32_t u32ClkSrc, u32HCLKFreq;
|
||||
uint32_t u32Div;
|
||||
|
||||
/* check SPI interface */
|
||||
if (spi != SPI0) return SPI_NONE;
|
||||
|
||||
/* Get system clock frequency */
|
||||
u32HCLKFreq = CLK_GetHCLKFreq();
|
||||
|
||||
if (u32BusClock >= u32HCLKFreq)
|
||||
{
|
||||
/* Select PCLK as the clock source of SPI */
|
||||
if (spi == SPI0)
|
||||
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;
|
||||
}
|
||||
|
||||
/* Check clock source of SPI */
|
||||
if (spi == SPI0)
|
||||
{
|
||||
if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
|
||||
u32ClkSrc = __HXT; /* Clock source is HXT */
|
||||
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
|
||||
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
|
||||
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1)
|
||||
u32ClkSrc = CLK_GetHCLKFreq() / ((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) + 1);
|
||||
else
|
||||
u32ClkSrc = 48000000; /* Clock source is HIRC48 */
|
||||
}
|
||||
|
||||
if (u32BusClock >= u32HCLKFreq)
|
||||
{
|
||||
/* Set DIVIDER = 0 */
|
||||
spi->CLKDIV = 0;
|
||||
/* Return master peripheral clock rate */
|
||||
return u32ClkSrc;
|
||||
}
|
||||
else if (u32BusClock >= u32ClkSrc)
|
||||
{
|
||||
/* Set DIVIDER = 0 */
|
||||
spi->CLKDIV = 0;
|
||||
/* Return master peripheral clock rate */
|
||||
return u32ClkSrc;
|
||||
}
|
||||
else if (u32BusClock == 0)
|
||||
{
|
||||
/* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
|
||||
spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
|
||||
/* Return master peripheral clock rate */
|
||||
return (u32ClkSrc / (0xFF + 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
|
||||
if (u32Div > 0xFF)
|
||||
{
|
||||
u32Div = 0xFF;
|
||||
spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
|
||||
/* Return master peripheral clock rate */
|
||||
return (u32ClkSrc / (0xFF + 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
|
||||
/* Return master peripheral clock rate */
|
||||
return (u32ClkSrc / (u32Div + 1));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure FIFO threshold setting.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3.
|
||||
* @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3.
|
||||
* @return None
|
||||
* @details Set TX FIFO threshold and RX FIFO threshold configurations.
|
||||
*/
|
||||
void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
|
||||
{
|
||||
spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) |
|
||||
(u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
|
||||
(u32RxThreshold << SPI_FIFOCTL_RXTH_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the actual frequency of SPI bus clock. Only available in Master mode.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @return Actual SPI bus clock frequency in Hz.
|
||||
* @details This function will calculate the actual SPI bus clock rate according to the SPInSEL and DIVIDER settings. Only available in Master mode.
|
||||
*/
|
||||
uint32_t SPI_GetBusClock(SPI_T *spi)
|
||||
{
|
||||
uint32_t u32Div;
|
||||
uint32_t u32ClkSrc = 0, u32HCLKFreq;
|
||||
|
||||
/* check SPI interface */
|
||||
if (spi != SPI0) return SPI_NONE;
|
||||
|
||||
/* Get DIVIDER setting */
|
||||
u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos;
|
||||
|
||||
/* Get system clock frequency */
|
||||
u32HCLKFreq = CLK_GetHCLKFreq();
|
||||
|
||||
/* Check clock source of SPI */
|
||||
if (spi == SPI0)
|
||||
{
|
||||
if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
|
||||
u32ClkSrc = __HXT; /* Clock source is HXT */
|
||||
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
|
||||
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
|
||||
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1)
|
||||
u32ClkSrc = u32HCLKFreq / ((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) + 1);
|
||||
else
|
||||
u32ClkSrc = 48000000; /* Clock source is HIRC48 */
|
||||
}
|
||||
|
||||
/* Return SPI bus clock rate */
|
||||
return (u32ClkSrc / (u32Div + 1));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt function.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @param[in] u32Mask The combination of all related interrupt enable bits.
|
||||
* Each bit corresponds to a interrupt enable bit.
|
||||
* This parameter decides which interrupts will be enabled. It is combination of:
|
||||
* - \ref SPI_UNIT_INT_MASK
|
||||
* - \ref SPI_SSACT_INT_MASK
|
||||
* - \ref SPI_SSINACT_INT_MASK
|
||||
* - \ref SPI_SLVUR_INT_MASK
|
||||
* - \ref SPI_SLVBE_INT_MASK
|
||||
* - \ref SPI_TXUF_INT_MASK
|
||||
* - \ref SPI_FIFO_TXTH_INT_MASK
|
||||
* - \ref SPI_FIFO_RXTH_INT_MASK
|
||||
* - \ref SPI_FIFO_RXOV_INT_MASK
|
||||
* - \ref SPI_FIFO_RXTO_INT_MASK
|
||||
*
|
||||
* @return None
|
||||
* @details Enable SPI related interrupts specified by u32Mask parameter.
|
||||
*/
|
||||
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
|
||||
{
|
||||
/* Enable unit transfer interrupt flag */
|
||||
if ((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
|
||||
spi->CTL |= SPI_CTL_UNITIEN_Msk;
|
||||
|
||||
/* Enable slave selection signal active interrupt flag */
|
||||
if ((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)
|
||||
spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk;
|
||||
|
||||
/* Enable slave selection signal inactive interrupt flag */
|
||||
if ((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK)
|
||||
spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk;
|
||||
|
||||
/* Enable slave TX under run interrupt flag */
|
||||
if ((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)
|
||||
spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk;
|
||||
|
||||
/* Enable slave bit count error interrupt flag */
|
||||
if ((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)
|
||||
spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk;
|
||||
|
||||
/* Enable slave TX underflow interrupt flag */
|
||||
if ((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)
|
||||
spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
|
||||
|
||||
/* Enable TX threshold interrupt flag */
|
||||
if ((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK)
|
||||
spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
|
||||
|
||||
/* Enable RX threshold interrupt flag */
|
||||
if ((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK)
|
||||
spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
|
||||
|
||||
/* Enable RX overrun interrupt flag */
|
||||
if ((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)
|
||||
spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
|
||||
|
||||
/* Enable RX time-out interrupt flag */
|
||||
if ((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK)
|
||||
spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt function.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @param[in] u32Mask The combination of all related interrupt enable bits.
|
||||
* Each bit corresponds to a interrupt bit.
|
||||
* This parameter decides which interrupts will be disabled. It is combination of:
|
||||
* - \ref SPI_UNIT_INT_MASK
|
||||
* - \ref SPI_SSACT_INT_MASK
|
||||
* - \ref SPI_SSINACT_INT_MASK
|
||||
* - \ref SPI_SLVUR_INT_MASK
|
||||
* - \ref SPI_SLVBE_INT_MASK
|
||||
* - \ref SPI_TXUF_INT_MASK
|
||||
* - \ref SPI_FIFO_TXTH_INT_MASK
|
||||
* - \ref SPI_FIFO_RXTH_INT_MASK
|
||||
* - \ref SPI_FIFO_RXOV_INT_MASK
|
||||
* - \ref SPI_FIFO_RXTO_INT_MASK
|
||||
*
|
||||
* @return None
|
||||
* @details Disable SPI related interrupts specified by u32Mask parameter.
|
||||
*/
|
||||
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
|
||||
{
|
||||
/* Disable unit transfer interrupt flag */
|
||||
if ((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
|
||||
spi->CTL &= ~SPI_CTL_UNITIEN_Msk;
|
||||
|
||||
/* Disable slave selection signal active interrupt flag */
|
||||
if ((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)
|
||||
spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk;
|
||||
|
||||
/* Disable slave selection signal inactive interrupt flag */
|
||||
if ((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK)
|
||||
spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk;
|
||||
|
||||
/* Disable slave TX under run interrupt flag */
|
||||
if ((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)
|
||||
spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk;
|
||||
|
||||
/* Disable slave bit count error interrupt flag */
|
||||
if ((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)
|
||||
spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk;
|
||||
|
||||
/* Disable slave TX underflow interrupt flag */
|
||||
if ((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)
|
||||
spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
|
||||
|
||||
/* Disable TX threshold interrupt flag */
|
||||
if ((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK)
|
||||
spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
|
||||
|
||||
/* Disable RX threshold interrupt flag */
|
||||
if ((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK)
|
||||
spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
|
||||
|
||||
/* Disable RX overrun interrupt flag */
|
||||
if ((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)
|
||||
spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
|
||||
|
||||
/* Disable RX time-out interrupt flag */
|
||||
if ((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK)
|
||||
spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt flag.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @param[in] u32Mask The combination of all related interrupt sources.
|
||||
* Each bit corresponds to a interrupt source.
|
||||
* This parameter decides which interrupt flags will be read. It is combination of:
|
||||
* - \ref SPI_UNIT_INT_MASK
|
||||
* - \ref SPI_SSACT_INT_MASK
|
||||
* - \ref SPI_SSINACT_INT_MASK
|
||||
* - \ref SPI_SLVUR_INT_MASK
|
||||
* - \ref SPI_SLVBE_INT_MASK
|
||||
* - \ref SPI_TXUF_INT_MASK
|
||||
* - \ref SPI_FIFO_TXTH_INT_MASK
|
||||
* - \ref SPI_FIFO_RXTH_INT_MASK
|
||||
* - \ref SPI_FIFO_RXOV_INT_MASK
|
||||
* - \ref SPI_FIFO_RXTO_INT_MASK
|
||||
*
|
||||
* @return Interrupt flags of selected sources.
|
||||
* @details Get SPI related interrupt flags specified by u32Mask parameter.
|
||||
*/
|
||||
uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask)
|
||||
{
|
||||
uint32_t u32IntFlag = 0;
|
||||
|
||||
/* Check unit transfer interrupt flag */
|
||||
if ((u32Mask & SPI_UNIT_INT_MASK) && (spi->STATUS & SPI_STATUS_UNITIF_Msk))
|
||||
u32IntFlag |= SPI_UNIT_INT_MASK;
|
||||
|
||||
/* Check slave selection signal active interrupt flag */
|
||||
if ((u32Mask & SPI_SSACT_INT_MASK) && (spi->STATUS & SPI_STATUS_SSACTIF_Msk))
|
||||
u32IntFlag |= SPI_SSACT_INT_MASK;
|
||||
|
||||
/* Check slave selection signal inactive interrupt flag */
|
||||
if ((u32Mask & SPI_SSINACT_INT_MASK) && (spi->STATUS & SPI_STATUS_SSINAIF_Msk))
|
||||
u32IntFlag |= SPI_SSINACT_INT_MASK;
|
||||
|
||||
/* Check slave TX under run interrupt flag */
|
||||
if ((u32Mask & SPI_SLVUR_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVURIF_Msk))
|
||||
u32IntFlag |= SPI_SLVUR_INT_MASK;
|
||||
|
||||
/* Check slave bit count error interrupt flag */
|
||||
if ((u32Mask & SPI_SLVBE_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVBEIF_Msk))
|
||||
u32IntFlag |= SPI_SLVBE_INT_MASK;
|
||||
|
||||
/* Check slave TX underflow interrupt flag */
|
||||
if ((u32Mask & SPI_TXUF_INT_MASK) && (spi->STATUS & SPI_STATUS_TXUFIF_Msk))
|
||||
u32IntFlag |= SPI_TXUF_INT_MASK;
|
||||
|
||||
/* Check TX threshold interrupt flag */
|
||||
if ((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (spi->STATUS & SPI_STATUS_TXTHIF_Msk))
|
||||
u32IntFlag |= SPI_FIFO_TXTH_INT_MASK;
|
||||
|
||||
/* Check RX threshold interrupt flag */
|
||||
if ((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (spi->STATUS & SPI_STATUS_RXTHIF_Msk))
|
||||
u32IntFlag |= SPI_FIFO_RXTH_INT_MASK;
|
||||
|
||||
/* Check RX overrun interrupt flag */
|
||||
if ((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (spi->STATUS & SPI_STATUS_RXOVIF_Msk))
|
||||
u32IntFlag |= SPI_FIFO_RXOV_INT_MASK;
|
||||
|
||||
/* Check RX time-out interrupt flag */
|
||||
if ((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (spi->STATUS & SPI_STATUS_RXTOIF_Msk))
|
||||
u32IntFlag |= SPI_FIFO_RXTO_INT_MASK;
|
||||
|
||||
return u32IntFlag;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt flag.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @param[in] u32Mask The combination of all related interrupt sources.
|
||||
* Each bit corresponds to a interrupt source.
|
||||
* This parameter decides which interrupt flags will be cleared. It could be the combination of:
|
||||
* - \ref SPI_UNIT_INT_MASK
|
||||
* - \ref SPI_SSACT_INT_MASK
|
||||
* - \ref SPI_SSINACT_INT_MASK
|
||||
* - \ref SPI_SLVUR_INT_MASK
|
||||
* - \ref SPI_SLVBE_INT_MASK
|
||||
* - \ref SPI_TXUF_INT_MASK
|
||||
* - \ref SPI_FIFO_RXOV_INT_MASK
|
||||
* - \ref SPI_FIFO_RXTO_INT_MASK
|
||||
*
|
||||
* @return None
|
||||
* @details Clear SPI related interrupt flags specified by u32Mask parameter.
|
||||
*/
|
||||
void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask)
|
||||
{
|
||||
if (u32Mask & SPI_UNIT_INT_MASK)
|
||||
spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
|
||||
|
||||
if (u32Mask & SPI_SSACT_INT_MASK)
|
||||
spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
|
||||
|
||||
if (u32Mask & SPI_SSINACT_INT_MASK)
|
||||
spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
|
||||
|
||||
if (u32Mask & SPI_SLVUR_INT_MASK)
|
||||
spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
|
||||
|
||||
if (u32Mask & SPI_SLVBE_INT_MASK)
|
||||
spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
|
||||
|
||||
if (u32Mask & SPI_TXUF_INT_MASK)
|
||||
spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
|
||||
|
||||
if (u32Mask & SPI_FIFO_RXOV_INT_MASK)
|
||||
spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
|
||||
|
||||
if (u32Mask & SPI_FIFO_RXTO_INT_MASK)
|
||||
spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SPI status.
|
||||
* @param[in] spi The pointer of the specified SPI module.
|
||||
* @param[in] u32Mask The combination of all related sources.
|
||||
* Each bit corresponds to a source.
|
||||
* This parameter decides which flags will be read. It is combination of:
|
||||
* - \ref SPI_BUSY_MASK
|
||||
* - \ref SPI_RX_EMPTY_MASK
|
||||
* - \ref SPI_RX_FULL_MASK
|
||||
* - \ref SPI_TX_EMPTY_MASK
|
||||
* - \ref SPI_TX_FULL_MASK
|
||||
* - \ref SPI_TXRX_RESET_MASK
|
||||
* - \ref SPI_SPIEN_STS_MASK
|
||||
* - \ref SPI_SSLINE_STS_MASK
|
||||
*
|
||||
* @return Flags of selected sources.
|
||||
* @details Get SPI related status specified by u32Mask parameter.
|
||||
*/
|
||||
uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask)
|
||||
{
|
||||
uint32_t u32Flag = 0;
|
||||
|
||||
/* Check busy status */
|
||||
if ((u32Mask & SPI_BUSY_MASK) && (spi->STATUS & SPI_STATUS_BUSY_Msk))
|
||||
u32Flag |= SPI_BUSY_MASK;
|
||||
|
||||
/* Check RX empty flag */
|
||||
if ((u32Mask & SPI_RX_EMPTY_MASK) && (spi->STATUS & SPI_STATUS_RXEMPTY_Msk))
|
||||
u32Flag |= SPI_RX_EMPTY_MASK;
|
||||
|
||||
/* Check RX full flag */
|
||||
if ((u32Mask & SPI_RX_FULL_MASK) && (spi->STATUS & SPI_STATUS_RXFULL_Msk))
|
||||
u32Flag |= SPI_RX_FULL_MASK;
|
||||
|
||||
/* Check TX empty flag */
|
||||
if ((u32Mask & SPI_TX_EMPTY_MASK) && (spi->STATUS & SPI_STATUS_TXEMPTY_Msk))
|
||||
u32Flag |= SPI_TX_EMPTY_MASK;
|
||||
|
||||
/* Check TX full flag */
|
||||
if ((u32Mask & SPI_TX_FULL_MASK) && (spi->STATUS & SPI_STATUS_TXFULL_Msk))
|
||||
u32Flag |= SPI_TX_FULL_MASK;
|
||||
|
||||
/* Check TX/RX reset flag */
|
||||
if ((u32Mask & SPI_TXRX_RESET_MASK) && (spi->STATUS & SPI_STATUS_TXRXRST_Msk))
|
||||
u32Flag |= SPI_TXRX_RESET_MASK;
|
||||
|
||||
/* Check SPIEN flag */
|
||||
if ((u32Mask & SPI_SPIEN_STS_MASK) && (spi->STATUS & SPI_STATUS_SPIENSTS_Msk))
|
||||
u32Flag |= SPI_SPIEN_STS_MASK;
|
||||
|
||||
/* Check SPIx_SS line status */
|
||||
if ((u32Mask & SPI_SSLINE_STS_MASK) && (spi->STATUS & SPI_STATUS_SSLINE_Msk))
|
||||
u32Flag |= SPI_SSLINE_STS_MASK;
|
||||
|
||||
return u32Flag;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function is used to get SPII2S source clock frequency.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return SPII2S source clock frequency (Hz).
|
||||
* @details Return the source clock frequency according to the setting of SPI0SEL (CLKSEL2[25:24])
|
||||
*/
|
||||
static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s)
|
||||
{
|
||||
uint32_t u32Freq = 0, u32HCLKFreq;
|
||||
|
||||
/* check SPI interface */
|
||||
if (i2s != SPI0) return SPI_NONE;
|
||||
|
||||
if (i2s == SPI0)
|
||||
{
|
||||
if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
|
||||
u32Freq = __HXT; /* Clock source is HXT */
|
||||
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
|
||||
u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
|
||||
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1)
|
||||
{
|
||||
/* Get system clock frequency */
|
||||
u32HCLKFreq = CLK_GetHCLKFreq();
|
||||
/* Clock source is PCLK0 */
|
||||
u32Freq = u32HCLKFreq / ((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) + 1);
|
||||
}
|
||||
else
|
||||
u32Freq = 48000000; /* Clock source is HIRC48 */
|
||||
}
|
||||
|
||||
return u32Freq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configures some parameters of SPII2S interface for general purpose use.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @param[in] u32MasterSlave SPII2S operation mode. Valid values are listed below.
|
||||
* - \ref SPII2S_MODE_MASTER
|
||||
* - \ref SPII2S_MODE_SLAVE
|
||||
* @param[in] u32SampleRate Sample rate
|
||||
* @param[in] u32WordWidth Data length. Valid values are listed below.
|
||||
* - \ref SPII2S_DATABIT_8
|
||||
* - \ref SPII2S_DATABIT_16
|
||||
* - \ref SPII2S_DATABIT_24
|
||||
* - \ref SPII2S_DATABIT_32
|
||||
* @param[in] u32Channels Audio format. Valid values are listed below.
|
||||
* - \ref SPII2S_MONO
|
||||
* - \ref SPII2S_STEREO
|
||||
* @param[in] u32DataFormat Data format. Valid values are listed below.
|
||||
* - \ref SPII2S_FORMAT_I2S
|
||||
* - \ref SPII2S_FORMAT_MSB
|
||||
* - \ref SPII2S_FORMAT_PCMA
|
||||
* - \ref SPII2S_FORMAT_PCMB
|
||||
* @return Real sample rate of master mode or peripheral clock rate of slave mode.
|
||||
* @details This function will reset SPI/I2S controller and configure SPII2S controller according to the input parameters.
|
||||
* Set TX FIFO threshold to 2 and RX FIFO threshold to 1. Both the TX and RX functions will be enabled.
|
||||
* The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference.
|
||||
* @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate.
|
||||
*/
|
||||
uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat)
|
||||
{
|
||||
uint32_t u32Divider;
|
||||
uint32_t u32BitRate, u32SrcClk;
|
||||
uint32_t u32HCLKFreq;
|
||||
|
||||
/* check SPI interface */
|
||||
if (i2s != SPI0) return SPI_NONE;
|
||||
|
||||
/* Reset SPI/I2S */
|
||||
if (i2s == SPI0)
|
||||
{
|
||||
SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
|
||||
SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
|
||||
}
|
||||
|
||||
/* Configure SPII2S controller */
|
||||
i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat;
|
||||
/* Set TX FIFO threshold to 2 and RX FIFO threshold to 1 */
|
||||
i2s->FIFOCTL = SPII2S_FIFO_TX_LEVEL_WORD_2 | SPII2S_FIFO_RX_LEVEL_WORD_2;
|
||||
|
||||
if (u32MasterSlave == SPI_MASTER)
|
||||
{
|
||||
/* Get the source clock rate */
|
||||
u32SrcClk = SPII2S_GetSourceClockFreq(i2s);
|
||||
|
||||
/* Calculate the bit clock rate */
|
||||
u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1) * 16;
|
||||
u32Divider = ((u32SrcClk / u32BitRate) >> 1) - 1;
|
||||
/* Set BCLKDIV setting */
|
||||
i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos);
|
||||
|
||||
/* Calculate bit clock rate */
|
||||
u32BitRate = u32SrcClk / ((u32Divider + 1) * 2);
|
||||
/* Calculate real sample rate */
|
||||
u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1) * 16);
|
||||
|
||||
/* Enable TX function, RX function and SPII2S mode. */
|
||||
i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
|
||||
|
||||
/* Return the real sample rate */
|
||||
return u32SampleRate;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set BCLKDIV = 0 */
|
||||
i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk;
|
||||
/* Get system clock frequency */
|
||||
u32HCLKFreq = CLK_GetHCLKFreq();
|
||||
|
||||
/* Set the peripheral clock rate to equal APB clock rate */
|
||||
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;
|
||||
/* Enable TX function, RX function and SPII2S mode. */
|
||||
i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
|
||||
/* Return slave peripheral clock rate */
|
||||
return (u32HCLKFreq / ((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) + 1));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SPII2S function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return None
|
||||
* @details Disable SPII2S function.
|
||||
*/
|
||||
void SPII2S_Close(SPI_T *i2s)
|
||||
{
|
||||
i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @param[in] u32Mask The combination of all related interrupt enable bits.
|
||||
* Each bit corresponds to a interrupt source. Valid values are listed below.
|
||||
* - \ref SPII2S_FIFO_TXTH_INT_MASK
|
||||
* - \ref SPII2S_FIFO_RXTH_INT_MASK
|
||||
* - \ref SPII2S_FIFO_RXOV_INT_MASK
|
||||
* - \ref SPII2S_FIFO_RXTO_INT_MASK
|
||||
* - \ref SPII2S_TXUF_INT_MASK
|
||||
* - \ref SPII2S_RIGHT_ZC_INT_MASK
|
||||
* - \ref SPII2S_LEFT_ZC_INT_MASK
|
||||
* @return None
|
||||
* @details This function enables the interrupt according to the u32Mask parameter.
|
||||
*/
|
||||
void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask)
|
||||
{
|
||||
/* Enable TX threshold interrupt flag */
|
||||
if ((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK)
|
||||
i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
|
||||
|
||||
/* Enable RX threshold interrupt flag */
|
||||
if ((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK)
|
||||
i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
|
||||
|
||||
/* Enable RX overrun interrupt flag */
|
||||
if ((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK)
|
||||
i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
|
||||
|
||||
/* Enable RX time-out interrupt flag */
|
||||
if ((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK)
|
||||
i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
|
||||
|
||||
/* Enable TX underflow interrupt flag */
|
||||
if ((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK)
|
||||
i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
|
||||
|
||||
/* Enable right channel zero cross interrupt flag */
|
||||
if ((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK)
|
||||
i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk;
|
||||
|
||||
/* Enable left channel zero cross interrupt flag */
|
||||
if ((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK)
|
||||
i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt function.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @param[in] u32Mask The combination of all related interrupt enable bits.
|
||||
* Each bit corresponds to a interrupt source. Valid values are listed below.
|
||||
* - \ref SPII2S_FIFO_TXTH_INT_MASK
|
||||
* - \ref SPII2S_FIFO_RXTH_INT_MASK
|
||||
* - \ref SPII2S_FIFO_RXOV_INT_MASK
|
||||
* - \ref SPII2S_FIFO_RXTO_INT_MASK
|
||||
* - \ref SPII2S_TXUF_INT_MASK
|
||||
* - \ref SPII2S_RIGHT_ZC_INT_MASK
|
||||
* - \ref SPII2S_LEFT_ZC_INT_MASK
|
||||
* @return None
|
||||
* @details This function disables the interrupt according to the u32Mask parameter.
|
||||
*/
|
||||
void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask)
|
||||
{
|
||||
/* Disable TX threshold interrupt flag */
|
||||
if ((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK)
|
||||
i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
|
||||
|
||||
/* Disable RX threshold interrupt flag */
|
||||
if ((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK)
|
||||
i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
|
||||
|
||||
/* Disable RX overrun interrupt flag */
|
||||
if ((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK)
|
||||
i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
|
||||
|
||||
/* Disable RX time-out interrupt flag */
|
||||
if ((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK)
|
||||
i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
|
||||
|
||||
/* Disable TX underflow interrupt flag */
|
||||
if ((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK)
|
||||
i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
|
||||
|
||||
/* Disable right channel zero cross interrupt flag */
|
||||
if ((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK)
|
||||
i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk;
|
||||
|
||||
/* Disable left channel zero cross interrupt flag */
|
||||
if ((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK)
|
||||
i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable master clock (MCLK).
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @param[in] u32BusClock The target MCLK clock rate.
|
||||
* @return Actual MCLK clock rate
|
||||
* @details Set the master clock rate according to u32BusClock parameter and enable master clock output.
|
||||
* The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference.
|
||||
*/
|
||||
uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock)
|
||||
{
|
||||
uint32_t u32Divider;
|
||||
uint32_t u32SrcClk;
|
||||
|
||||
u32SrcClk = SPII2S_GetSourceClockFreq(i2s);
|
||||
if (u32BusClock == u32SrcClk)
|
||||
u32Divider = 0;
|
||||
else
|
||||
{
|
||||
u32Divider = (u32SrcClk / u32BusClock) >> 1;
|
||||
/* MCLKDIV is a 7-bit width configuration. The maximum value is 0xFF. */
|
||||
if (u32Divider > 0xFF)
|
||||
u32Divider = 0xFF;
|
||||
}
|
||||
|
||||
/* Write u32Divider to MCLKDIV (SPI_I2SCLK[5:0]) */
|
||||
i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos);
|
||||
|
||||
/* Enable MCLK output */
|
||||
i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk;
|
||||
|
||||
if (u32Divider == 0)
|
||||
return u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */
|
||||
else
|
||||
return ((u32SrcClk >> 1) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable master clock (MCLK).
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @return None
|
||||
* @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output.
|
||||
*/
|
||||
void SPII2S_DisableMCLK(SPI_T *i2s)
|
||||
{
|
||||
i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure FIFO threshold setting.
|
||||
* @param[in] i2s The pointer of the specified SPII2S module.
|
||||
* @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3.
|
||||
* @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3.
|
||||
* @return None
|
||||
* @details Set TX FIFO threshold and RX FIFO threshold configurations.
|
||||
*/
|
||||
void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
|
||||
{
|
||||
i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) |
|
||||
(u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
|
||||
(u32RxThreshold << SPI_FIFOCTL_RXTH_Pos);
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group SPI_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,205 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file sys.c
|
||||
* @version V3.00
|
||||
* $Revision: 3 $
|
||||
* $Date: 18/07/05 4:42p $
|
||||
* @brief M031 Series System Manager (SYS) Driver Source File
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*****************************************************************************/
|
||||
#include "M031Series.h"
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup SYS_Driver SYS Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clear reset source
|
||||
* @param[in] u32Src is reset source. Including :
|
||||
* - \ref SYS_RSTSTS_CPULKRF_Msk
|
||||
* - \ref SYS_RSTSTS_CPURF_Msk
|
||||
* - \ref SYS_RSTSTS_SYSRF_Msk
|
||||
* - \ref SYS_RSTSTS_BODRF_Msk
|
||||
* - \ref SYS_RSTSTS_LVRF_Msk
|
||||
* - \ref SYS_RSTSTS_WDTRF_Msk
|
||||
* - \ref SYS_RSTSTS_PINRF_Msk
|
||||
* - \ref SYS_RSTSTS_PORF_Msk
|
||||
* @return None
|
||||
* @details This function clear the selected reset source.
|
||||
*/
|
||||
void SYS_ClearResetSrc(uint32_t u32Src)
|
||||
{
|
||||
SYS->RSTSTS = u32Src;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Brown-out detector output status
|
||||
* @param None
|
||||
* @retval 0 System voltage is higher than BODVL setting or BODEN is 0.
|
||||
* @retval 1 System voltage is lower than BODVL setting.
|
||||
* @details This function get Brown-out detector output status.
|
||||
*/
|
||||
uint32_t SYS_GetBODStatus(void)
|
||||
{
|
||||
return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get reset status register value
|
||||
* @param None
|
||||
* @return Reset source
|
||||
* @details This function get the system reset status register value.
|
||||
*/
|
||||
uint32_t SYS_GetResetSrc(void)
|
||||
{
|
||||
return (SYS->RSTSTS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if register is locked or not
|
||||
* @param None
|
||||
* @retval 0 Write-protection function is disabled.
|
||||
* 1 Write-protection function is enabled.
|
||||
* @details This function check register write-protection bit setting.
|
||||
*/
|
||||
uint32_t SYS_IsRegLocked(void)
|
||||
{
|
||||
return !(SYS->REGLCTL & 0x1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get product ID
|
||||
* @param None
|
||||
* @return Product ID
|
||||
* @details This function get product ID.
|
||||
*/
|
||||
uint32_t SYS_ReadPDID(void)
|
||||
{
|
||||
return SYS->PDID;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset chip with chip reset
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function reset chip with chip reset.
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
void SYS_ResetChip(void)
|
||||
{
|
||||
SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset chip with CPU reset
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function reset CPU with CPU reset.
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
void SYS_ResetCPU(void)
|
||||
{
|
||||
SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset selected module
|
||||
* @param[in] u32ModuleIndex is module index. Including :
|
||||
* - \ref PDMA_RST
|
||||
* - \ref EBI_RST
|
||||
* - \ref HDIV_RST
|
||||
* - \ref CRC_RST
|
||||
* - \ref GPIO_RST
|
||||
* - \ref TMR0_RST
|
||||
* - \ref TMR1_RST
|
||||
* - \ref TMR2_RST
|
||||
* - \ref TMR3_RST
|
||||
* - \ref ACMP01_RST
|
||||
* - \ref I2C0_RST
|
||||
* - \ref I2C1_RST
|
||||
* - \ref QSPI0_RST
|
||||
* - \ref SPI0_RST
|
||||
* - \ref UART0_RST
|
||||
* - \ref UART1_RST
|
||||
* - \ref UART2_RST
|
||||
* - \ref UART3_RST
|
||||
* - \ref UART4_RST
|
||||
* - \ref UART5_RST
|
||||
* - \ref UART6_RST
|
||||
* - \ref UART7_RST
|
||||
* - \ref USBD_RST
|
||||
* - \ref ADC_RST
|
||||
* - \ref USCI0_RST
|
||||
* - \ref USCI1_RST
|
||||
* - \ref PWM0_RST
|
||||
* - \ref PWM1_RST
|
||||
* - \ref BPWM0_RST
|
||||
* - \ref BPWM1_RST
|
||||
* @return None
|
||||
* @details This function reset selected module.
|
||||
*/
|
||||
void SYS_ResetModule(uint32_t u32ModuleIndex)
|
||||
{
|
||||
/* Generate reset signal to the corresponding module */
|
||||
*(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24)) |= 1 << (u32ModuleIndex & 0x00ffffff);
|
||||
|
||||
/* Release corresponding module from reset state */
|
||||
*(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24)) &= ~(1 << (u32ModuleIndex & 0x00ffffff));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable and configure Brown-out detector function
|
||||
* @param[in] i32Mode is reset or interrupt mode. Including :
|
||||
* - \ref SYS_BODCTL_BOD_RST_EN
|
||||
* - \ref SYS_BODCTL_BOD_INTERRUPT_EN
|
||||
* @param[in] u32BODLevel is Brown-out voltage level. Including :
|
||||
* - \ref SYS_BODCTL_BODVL_2_5V
|
||||
* - \ref SYS_BODCTL_BODVL_2_0V
|
||||
* @return None
|
||||
* @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level.
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
|
||||
{
|
||||
/* Enable Brown-out Detector function */
|
||||
SYS->BODCTL |= SYS_BODCTL_BODEN_Msk;
|
||||
|
||||
/* Enable Brown-out interrupt or reset function */
|
||||
SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | i32Mode;
|
||||
|
||||
/* Select Brown-out Detector threshold voltage */
|
||||
SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Brown-out detector function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function disable Brown-out detector function.
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
void SYS_DisableBOD(void)
|
||||
{
|
||||
SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group SYS_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,333 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file timer.c
|
||||
* @version V3.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 18/07/13 5:00p $
|
||||
* @brief M031 Series Timer Controller (TIMER) Driver Source File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "M031Series.h"
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMER_Driver TIMER Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Open Timer with Operate Mode and Frequency
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
* @param[in] u32Mode Operation mode. Possible options are
|
||||
* - \ref TIMER_ONESHOT_MODE
|
||||
* - \ref TIMER_PERIODIC_MODE
|
||||
* - \ref TIMER_TOGGLE_MODE
|
||||
* - \ref TIMER_CONTINUOUS_MODE
|
||||
* @param[in] u32Freq Target working frequency
|
||||
*
|
||||
* @return Real timer working frequency
|
||||
*
|
||||
* @details This API is used to configure timer to operate in specified mode and frequency.
|
||||
* If timer cannot work in target frequency, a closest frequency will be chose and returned.
|
||||
* @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling
|
||||
* \ref TIMER_Start macro or program registers directly.
|
||||
*/
|
||||
uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
|
||||
{
|
||||
uint32_t u32Clk = TIMER_GetModuleClock(timer);
|
||||
uint32_t u32Cmpr = 0, u32Prescale = 0;
|
||||
|
||||
/* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, pre-scale = 0. */
|
||||
if(u32Freq >= (u32Clk >> 1))
|
||||
{
|
||||
u32Cmpr = 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
u32Cmpr = u32Clk / u32Freq;
|
||||
u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */
|
||||
if (u32Prescale > 0)
|
||||
u32Cmpr = u32Cmpr / (u32Prescale + 1);
|
||||
}
|
||||
|
||||
timer->CTL = u32Mode | u32Prescale;
|
||||
timer->CMP = u32Cmpr;
|
||||
|
||||
return(u32Clk / (u32Cmpr * (u32Prescale + 1)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop Timer Counting
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API stops timer counting and disable all timer interrupt function.
|
||||
*/
|
||||
void TIMER_Close(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL = 0;
|
||||
timer->EXTCTL = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Create a specify Delay Time
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
* @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second).
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to create a delay loop for u32Usec micro seconds by using timer one-shot mode.
|
||||
* @note This API overwrites the register setting of the timer used to count the delay time.
|
||||
* @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay.
|
||||
*/
|
||||
void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
|
||||
{
|
||||
uint32_t u32Clk = TIMER_GetModuleClock(timer);
|
||||
uint32_t u32Prescale = 0, delay = (SystemCoreClock / u32Clk) + 1;
|
||||
uint32_t u32Cmpr, u32NsecPerTick;
|
||||
|
||||
/* Clear current timer configuration */
|
||||
timer->CTL = 0;
|
||||
timer->EXTCTL = 0;
|
||||
|
||||
if(u32Clk <= 1000000) /* min delay is 1000 us if timer clock source is <= 1 MHz */
|
||||
{
|
||||
if(u32Usec < 1000)
|
||||
u32Usec = 1000;
|
||||
if(u32Usec > 1000000)
|
||||
u32Usec = 1000000;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(u32Usec < 100)
|
||||
u32Usec = 100;
|
||||
if(u32Usec > 1000000)
|
||||
u32Usec = 1000000;
|
||||
}
|
||||
|
||||
if(u32Clk <= 1000000)
|
||||
{
|
||||
u32Prescale = 0;
|
||||
u32NsecPerTick = 1000000000 / u32Clk;
|
||||
u32Cmpr = (u32Usec * 1000) / u32NsecPerTick;
|
||||
}
|
||||
else
|
||||
{
|
||||
u32Cmpr = u32Usec * (u32Clk / 1000000);
|
||||
u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */
|
||||
if (u32Prescale > 0)
|
||||
u32Cmpr = u32Cmpr / (u32Prescale + 1);
|
||||
}
|
||||
|
||||
timer->CMP = u32Cmpr;
|
||||
timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale;
|
||||
|
||||
/* When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it. */
|
||||
/* And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag. */
|
||||
for(; delay > 0; delay--)
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
|
||||
while(timer->CTL & TIMER_CTL_ACTSTS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Timer Capture Function
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
* @param[in] u32CapMode Timer capture mode. Could be
|
||||
* - \ref TIMER_CAPTURE_FREE_COUNTING_MODE
|
||||
* - \ref TIMER_CAPTURE_COUNTER_RESET_MODE
|
||||
* @param[in] u32Edge Timer capture event trigger edge. Possible values are
|
||||
* - \ref TIMER_CAPTURE_FALLING_EDGE
|
||||
* - \ref TIMER_CAPTURE_RISING_EDGE
|
||||
* - \ref TIMER_CAPTURE_FALLING_AND_RISING_EDGE
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to enable timer capture function with specify capture trigger edge \n
|
||||
* to get current counter value or reset counter value to 0.
|
||||
* @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly.
|
||||
*/
|
||||
void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
|
||||
{
|
||||
timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) |
|
||||
u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Timer Capture Function
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to disable the timer capture function.
|
||||
*/
|
||||
void TIMER_DisableCapture(TIMER_T *timer)
|
||||
{
|
||||
timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Timer Counter Function
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
* @param[in] u32Edge Detection edge of counter pin. Could be ether
|
||||
* - \ref TIMER_COUNTER_FALLING_EDGE, or
|
||||
* - \ref TIMER_COUNTER_RISING_EDGE
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable the timer counter function with specify detection edge.
|
||||
* @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly.
|
||||
* @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode.
|
||||
*/
|
||||
void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
|
||||
{
|
||||
timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge;
|
||||
timer->CTL |= TIMER_CTL_EXTCNTEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Timer Counter Function
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This API is used to disable the timer event counter function.
|
||||
*/
|
||||
void TIMER_DisableEventCounter(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Timer Clock Frequency
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return Timer clock frequency
|
||||
*
|
||||
* @details This API is used to get the timer clock frequency.
|
||||
* @note This API cannot return correct clock rate if timer source is from external clock input.
|
||||
*/
|
||||
uint32_t TIMER_GetModuleClock(TIMER_T *timer)
|
||||
{
|
||||
uint32_t u32Src;
|
||||
const uint32_t au32Clk[] = {__HXT, __LXT, 0, 0, 0, __LIRC, 0, __HIRC};
|
||||
|
||||
if(timer == TIMER0)
|
||||
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos;
|
||||
else if(timer == TIMER1)
|
||||
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos;
|
||||
else if(timer == TIMER2)
|
||||
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos;
|
||||
else /* Timer 3 */
|
||||
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos;
|
||||
|
||||
if(u32Src == 2)
|
||||
{
|
||||
if ((timer == TIMER0) || (timer == TIMER1))
|
||||
return CLK_GetPCLK0Freq();
|
||||
else
|
||||
return CLK_GetPCLK1Freq();
|
||||
}
|
||||
|
||||
return (au32Clk[u32Src]);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Timer Frequency Counter Function
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
* @param[in] u32DropCount This parameter has no effect in M031 series BSP.
|
||||
* @param[in] u32Timeout This parameter has no effect in M031 series BSP.
|
||||
* @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to calculate input event frequency. After enable
|
||||
* this function, a pair of timers, such as TIMER0 and TIMER1,
|
||||
* will be configured for this function. The mode used to calculate input
|
||||
* event frequency is mentioned as "Inter Timer Trigger Mode" in Technical
|
||||
* Reference Manual
|
||||
*/
|
||||
void TIMER_EnableFreqCounter(TIMER_T *timer, uint32_t u32DropCount, uint32_t u32Timeout, uint32_t u32EnableInt)
|
||||
{
|
||||
TIMER_T *t; /* store the timer base to configure compare value */
|
||||
|
||||
t = (timer == TIMER0) ? TIMER1 : TIMER3;
|
||||
|
||||
t->CMP = 0xFFFFFF;
|
||||
t->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0;
|
||||
timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Timer Frequency Counter Function
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void TIMER_DisableFreqCounter(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL &= ~TIMER_CTL_INTRGEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select Other Modules Triggered Source
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
* @param[in] u32Src Selects the interrupt source to trigger other modules. Could be:
|
||||
* - \ref TIMER_TRGSRC_TIMEOUT_EVENT
|
||||
* - \ref TIMER_TRGSRC_CAPTURE_EVENT
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src)
|
||||
{
|
||||
timer->CTL = (timer->CTL & ~TIMER_CTL_TRGSSEL_Msk) | u32Src;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Modules Trigger by Timer Interrupt Event
|
||||
*
|
||||
* @param[in] timer The pointer of the specified Timer module.
|
||||
* @param[in] u32Mask The mask of modules (PWM, ADC, BPWM and PDMA) trigger by timer. Is the combination of
|
||||
* - \ref TIMER_TRG_TO_PWM
|
||||
* - \ref TIMER_TRG_TO_ADC
|
||||
* - \ref TIMER_TRG_TO_PDMA
|
||||
* - \ref TIMER_TRG_TO_BPWM
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask)
|
||||
{
|
||||
timer->CTL = (timer->CTL & ~(TIMER_CTL_TRGPWM_Msk | TIMER_CTL_TRGADC_Msk | TIMER_CTL_TRGPDMA_Msk | TIMER_CTL_TRGBPWM_Msk)) | (u32Mask);
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group TIMER_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
|
@ -1,722 +0,0 @@
|
|||
/****************************************************************************
|
||||
* @file uart.c
|
||||
* @version V1.00
|
||||
* @brief M031 series UART driver source file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "NuMicro.h"
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup UART_Driver UART Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clear UART specified interrupt flag
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module.
|
||||
* @param[in] u32InterruptFlag The specified interrupt of UART module.
|
||||
* - \ref UART_INTSTS_SWBEINT_Msk : Single-wire Bit Error Detect Interrupt
|
||||
* - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
|
||||
* - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt
|
||||
* - \ref UART_INTSTS_MODEMINT_Msk : Modem Status interrupt
|
||||
* - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function is used to clear UART specified interrupt flag.
|
||||
*/
|
||||
|
||||
void UART_ClearIntFlag(UART_T *uart, uint32_t u32InterruptFlag)
|
||||
{
|
||||
|
||||
|
||||
if (u32InterruptFlag & UART_INTSTS_SWBEINT_Msk) /* Clear Bit Error Detection Interrupt */
|
||||
{
|
||||
uart->INTSTS = UART_INTSTS_SWBEIF_Msk;
|
||||
}
|
||||
|
||||
if (u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */
|
||||
{
|
||||
uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk;
|
||||
uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk;
|
||||
}
|
||||
|
||||
if (u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear Modem Status Interrupt */
|
||||
{
|
||||
uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
|
||||
}
|
||||
|
||||
if (u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */
|
||||
{
|
||||
uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
|
||||
}
|
||||
|
||||
if (u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */
|
||||
{
|
||||
uart->WKSTS = UART_WKSTS_CTSWKF_Msk | UART_WKSTS_DATWKF_Msk |
|
||||
UART_WKSTS_RFRTWKF_Msk | UART_WKSTS_RS485WKF_Msk |
|
||||
UART_WKSTS_TOUTWKF_Msk;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable UART interrupt
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function is used to disable UART interrupt.
|
||||
*/
|
||||
void UART_Close(UART_T *uart)
|
||||
{
|
||||
uart->INTEN = 0ul;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable UART auto flow control function
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function is used to disable UART auto flow control.
|
||||
*/
|
||||
void UART_DisableFlowCtrl(UART_T *uart)
|
||||
{
|
||||
uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable UART specified interrupt
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module.
|
||||
* @param[in] u32InterruptFlag The specified interrupt of UART module.
|
||||
* - \ref UART_INTSTS_SWBEINT_Msk : Single-wire Bit Error Detect Interrupt
|
||||
* - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
|
||||
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
|
||||
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
|
||||
* - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
|
||||
* - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
|
||||
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
|
||||
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt *
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
|
||||
*/
|
||||
void UART_DisableInt(UART_T *uart, uint32_t u32InterruptFlag)
|
||||
{
|
||||
/* Disable UART specified interrupt */
|
||||
UART_DISABLE_INT(uart, u32InterruptFlag);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable UART auto flow control function
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function is used to Enable UART auto flow control.
|
||||
*/
|
||||
void UART_EnableFlowCtrl(UART_T *uart)
|
||||
{
|
||||
/* Set RTS pin output is low level active */
|
||||
uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
|
||||
|
||||
/* Set CTS pin input is low level active */
|
||||
uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
|
||||
|
||||
/* Set RTS and CTS auto flow control enable */
|
||||
uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module.
|
||||
* @param[in] u32InterruptFlag The specified interrupt of UART module:
|
||||
* - \ref UART_INTSTS_SWBEINT_Msk : Single-wire Bit Error Detect Interrupt
|
||||
* - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
|
||||
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
|
||||
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
|
||||
* - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
|
||||
* - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
|
||||
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
|
||||
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt *
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
|
||||
*/
|
||||
void UART_EnableInt(UART_T *uart, uint32_t u32InterruptFlag)
|
||||
{
|
||||
/* Enable UART specified interrupt */
|
||||
UART_ENABLE_INT(uart, u32InterruptFlag);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Open and set UART function
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module.
|
||||
* @param[in] u32baudrate The baudrate of UART module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function use to enable UART function and set baud-rate.
|
||||
*/
|
||||
void UART_Open(UART_T *uart, uint32_t u32baudrate)
|
||||
{
|
||||
uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul;
|
||||
uint32_t u32ClkTbl[6ul] = {__HXT, 0ul, __LXT, __HIRC, 0ul, __LIRC};
|
||||
uint32_t u32Baud_Div = 0ul;
|
||||
|
||||
|
||||
if (uart == (UART_T *)UART0)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
|
||||
}
|
||||
else if (uart == (UART_T *)UART1)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
|
||||
}
|
||||
else if (uart == (UART_T *)UART2)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
|
||||
}
|
||||
else if (uart == (UART_T *)UART3)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
|
||||
}
|
||||
else if (uart == (UART_T *)UART4)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
|
||||
}
|
||||
else if (uart == (UART_T *)UART5)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
|
||||
}
|
||||
else if (uart == (UART_T *)UART6)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART6SEL_Msk) >> CLK_CLKSEL3_UART6SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART6DIV_Msk) >> CLK_CLKDIV4_UART6DIV_Pos;
|
||||
}
|
||||
else if (uart == (UART_T *)UART7)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART7SEL_Msk) >> CLK_CLKSEL3_UART7SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART7DIV_Msk) >> CLK_CLKDIV4_UART7DIV_Pos;
|
||||
}
|
||||
|
||||
/* Select UART function */
|
||||
uart->FUNCSEL = UART_FUNCSEL_UART;
|
||||
|
||||
/* Set UART line configuration */
|
||||
uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
|
||||
|
||||
/* Set UART Rx and RTS trigger level */
|
||||
uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
|
||||
|
||||
/* Get PLL clock frequency if UART clock source selection is PLL */
|
||||
if (u32UartClkSrcSel == 1ul)
|
||||
{
|
||||
u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
|
||||
}
|
||||
|
||||
/* Get PCLK clock frequency if UART clock source selection is PCLK */
|
||||
if (u32UartClkSrcSel == 4ul)
|
||||
{
|
||||
/* UART Port as UART0 ,UART2, UART4 or UART6 */
|
||||
if ((uart == (UART_T *)UART0) || (uart == (UART_T *)UART2) || (uart == (UART_T *)UART4) || (uart == (UART_T *)UART6))
|
||||
{
|
||||
u32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK0Freq();
|
||||
}
|
||||
else /* UART Port as UART1, UART3, UART5 or UART7*/
|
||||
{
|
||||
u32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK1Freq();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Set UART baud rate */
|
||||
if (u32baudrate != 0ul)
|
||||
{
|
||||
u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
|
||||
|
||||
if (u32Baud_Div > 0xFFFFul)
|
||||
{
|
||||
uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
|
||||
}
|
||||
else
|
||||
{
|
||||
uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Read UART data
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module.
|
||||
* @param[in] pu8RxBuf The buffer to receive the data of receive FIFO.
|
||||
* @param[in] u32ReadBytes The the read bytes number of data.
|
||||
*
|
||||
* @return u32Count Receive byte count
|
||||
*
|
||||
* @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
|
||||
*/
|
||||
uint32_t UART_Read(UART_T *uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
|
||||
{
|
||||
uint32_t u32Count, u32delayno;
|
||||
uint32_t u32Exit = 0ul;
|
||||
|
||||
for (u32Count = 0ul; u32Count < u32ReadBytes; u32Count++)
|
||||
{
|
||||
u32delayno = 0ul;
|
||||
|
||||
while (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */
|
||||
{
|
||||
u32delayno++;
|
||||
|
||||
if (u32delayno >= 0x40000000ul)
|
||||
{
|
||||
u32Exit = 1ul;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (u32Exit == 1ul)
|
||||
{
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */
|
||||
}
|
||||
}
|
||||
|
||||
return u32Count;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set UART line configuration
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module.
|
||||
* @param[in] u32baudrate The register value of baudrate of UART module.
|
||||
* If u32baudrate = 0, UART baudrate will not change.
|
||||
* @param[in] u32data_width The data length of UART module.
|
||||
* - \ref UART_WORD_LEN_5
|
||||
* - \ref UART_WORD_LEN_6
|
||||
* - \ref UART_WORD_LEN_7
|
||||
* - \ref UART_WORD_LEN_8
|
||||
* @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module.
|
||||
* - \ref UART_PARITY_NONE
|
||||
* - \ref UART_PARITY_ODD
|
||||
* - \ref UART_PARITY_EVEN
|
||||
* - \ref UART_PARITY_MARK
|
||||
* - \ref UART_PARITY_SPACE
|
||||
* @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module.
|
||||
* - \ref UART_STOP_BIT_1
|
||||
* - \ref UART_STOP_BIT_1_5
|
||||
* - \ref UART_STOP_BIT_2
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function use to config UART line setting.
|
||||
*/
|
||||
void UART_SetLine_Config(UART_T *uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
|
||||
{
|
||||
uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul;
|
||||
uint32_t u32ClkTbl[6ul] = {__HXT, 0ul, __LXT, __HIRC, 0, __LIRC};
|
||||
uint32_t u32Baud_Div = 0ul;
|
||||
|
||||
|
||||
if (uart == (UART_T *)UART0)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
|
||||
}
|
||||
else if (uart == (UART_T *)UART1)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
|
||||
}
|
||||
else if (uart == (UART_T *)UART2)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
|
||||
}
|
||||
else if (uart == (UART_T *)UART3)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
|
||||
}
|
||||
else if (uart == (UART_T *)UART4)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
|
||||
}
|
||||
else if (uart == (UART_T *)UART5)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
|
||||
}
|
||||
else if (uart == (UART_T *)UART6)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART6SEL_Msk) >> CLK_CLKSEL3_UART6SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART6DIV_Msk) >> CLK_CLKDIV4_UART6DIV_Pos;
|
||||
}
|
||||
else if (uart == (UART_T *)UART7)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART7SEL_Msk) >> CLK_CLKSEL3_UART7SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART7DIV_Msk) >> CLK_CLKDIV4_UART7DIV_Pos;
|
||||
}
|
||||
|
||||
/* Get PLL clock frequency if UART clock source selection is PLL */
|
||||
if (u32UartClkSrcSel == 1ul)
|
||||
{
|
||||
u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
|
||||
}
|
||||
|
||||
/* Get PCLK clock frequency if UART clock source selection is PCLK */
|
||||
if (u32UartClkSrcSel == 4ul)
|
||||
{
|
||||
if ((uart == (UART_T *)UART0) || (uart == (UART_T *)UART2) || (uart == (UART_T *)UART4) || (uart == (UART_T *)UART6))
|
||||
{
|
||||
u32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK0Freq();
|
||||
}
|
||||
else /* UART Port as UART1, UART3, UART5, UART7*/
|
||||
{
|
||||
u32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK1Freq();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Set UART baud rate */
|
||||
if (u32baudrate != 0ul)
|
||||
{
|
||||
u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
|
||||
|
||||
if (u32Baud_Div > 0xFFFFul)
|
||||
{
|
||||
uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
|
||||
}
|
||||
else
|
||||
{
|
||||
uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set UART line configuration */
|
||||
uart->LINE = u32data_width | u32parity | u32stop_bits;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set Rx timeout count
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module.
|
||||
* @param[in] u32TOC Rx timeout counter.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function use to set Rx timeout count.
|
||||
*/
|
||||
void UART_SetTimeoutCnt(UART_T *uart, uint32_t u32TOC)
|
||||
{
|
||||
/* Set time-out interrupt comparator */
|
||||
uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);
|
||||
|
||||
/* Set time-out counter enable */
|
||||
uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Select and configure IrDA function
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module.
|
||||
* @param[in] u32Buadrate The baudrate of UART module.
|
||||
* @param[in] u32Direction The direction of UART module in IrDA mode:
|
||||
* - \ref UART_IRDA_TXEN
|
||||
* - \ref UART_IRDA_RXEN
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
|
||||
*/
|
||||
void UART_SelectIrDAMode(UART_T *uart, uint32_t u32Buadrate, uint32_t u32Direction)
|
||||
{
|
||||
uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul;
|
||||
uint32_t u32ClkTbl[6ul] = {__HXT, 0ul, __LXT, __HIRC, 0ul, __LIRC};
|
||||
uint32_t u32Baud_Div;
|
||||
|
||||
/* Select IrDA function mode */
|
||||
uart->FUNCSEL = UART_FUNCSEL_IrDA;
|
||||
|
||||
|
||||
if (uart == UART0)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
|
||||
}
|
||||
else if (uart == UART1)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
|
||||
}
|
||||
else if (uart == UART2)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
|
||||
}
|
||||
else if (uart == UART3)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
|
||||
}
|
||||
else if (uart == UART4)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
|
||||
}
|
||||
else if (uart == UART5)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
|
||||
}
|
||||
else if (uart == UART6)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART6SEL_Msk) >> CLK_CLKSEL3_UART6SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART6DIV_Msk) >> CLK_CLKDIV4_UART6DIV_Pos;
|
||||
}
|
||||
else if (uart == UART7)
|
||||
{
|
||||
/* Get UART clock source selection */
|
||||
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART7SEL_Msk) >> CLK_CLKSEL3_UART7SEL_Pos;
|
||||
/* Get UART clock divider number */
|
||||
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART7DIV_Msk) >> CLK_CLKDIV4_UART7DIV_Pos;
|
||||
}
|
||||
|
||||
/* Get PLL clock frequency if UART clock source selection is PLL */
|
||||
if (u32UartClkSrcSel == 1ul)
|
||||
{
|
||||
u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
|
||||
}
|
||||
|
||||
/* Get PCLK clock frequency if UART clock source selection is PCLK */
|
||||
if (u32UartClkSrcSel == 4ul)
|
||||
{
|
||||
if ((uart == (UART_T *)UART0) || (uart == (UART_T *)UART2) || (uart == (UART_T *)UART4) || (uart == (UART_T *)UART6))
|
||||
{
|
||||
u32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK0Freq();
|
||||
}
|
||||
else /* UART Port as UART1, UART3, UART5, UART7*/
|
||||
{
|
||||
u32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK1Freq();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Set UART IrDA baud rate in mode 0 */
|
||||
if (u32Buadrate != 0ul)
|
||||
{
|
||||
u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate);
|
||||
|
||||
if (u32Baud_Div < 0xFFFFul)
|
||||
{
|
||||
uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure IrDA relative settings */
|
||||
if (u32Direction == UART_IRDA_RXEN)
|
||||
{
|
||||
uart->IRDA |= UART_IRDA_RXINV_Msk; /*Rx signal is inverse*/
|
||||
uart->IRDA &= ~UART_IRDA_TXEN_Msk;
|
||||
}
|
||||
else
|
||||
{
|
||||
uart->IRDA &= ~UART_IRDA_TXINV_Msk; /*Tx signal is not inverse*/
|
||||
uart->IRDA |= UART_IRDA_TXEN_Msk;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Select and configure RS485 function
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module.
|
||||
* @param[in] u32Mode The operation mode(NMM/AUD/AAD).
|
||||
* - \ref UART_ALTCTL_RS485NMM_Msk
|
||||
* - \ref UART_ALTCTL_RS485AUD_Msk
|
||||
* - \ref UART_ALTCTL_RS485AAD_Msk
|
||||
* @param[in] u32Addr The RS485 address.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function is used to set RS485 relative setting.
|
||||
*/
|
||||
void UART_SelectRS485Mode(UART_T *uart, uint32_t u32Mode, uint32_t u32Addr)
|
||||
{
|
||||
/* Select UART RS485 function mode */
|
||||
uart->FUNCSEL = UART_FUNCSEL_RS485;
|
||||
|
||||
/* Set RS485 configuration */
|
||||
uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk);
|
||||
uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write UART data
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module.
|
||||
* @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO.
|
||||
* @param[out] u32WriteBytes The byte number of data.
|
||||
*
|
||||
* @return u32Count transfer byte count
|
||||
*
|
||||
* @details The function is to write data into TX buffer to transmit data by UART.
|
||||
*/
|
||||
uint32_t UART_Write(UART_T *uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
|
||||
{
|
||||
uint32_t u32Count, u32delayno;
|
||||
uint32_t u32Exit = 0ul;
|
||||
|
||||
for (u32Count = 0ul; u32Count != u32WriteBytes; u32Count++)
|
||||
{
|
||||
u32delayno = 0ul;
|
||||
|
||||
while (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) /* Check Tx Full */
|
||||
{
|
||||
u32delayno++;
|
||||
|
||||
if (u32delayno >= 0x40000000ul)
|
||||
{
|
||||
u32Exit = 1ul;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (u32Exit == 1ul)
|
||||
{
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */
|
||||
}
|
||||
}
|
||||
|
||||
return u32Count;
|
||||
|
||||
}
|
||||
/**
|
||||
* @brief Select Single Wire mode function
|
||||
*
|
||||
* @param[in] uart The pointer of the specified UART module.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function is used to select Single Wire mode.
|
||||
*/
|
||||
void UART_SelectSingleWireMode(UART_T *uart)
|
||||
{
|
||||
|
||||
/* Select UART SingleWire function mode */
|
||||
uart->FUNCSEL = ((uart->FUNCSEL & (~UART_FUNCSEL_FUNCSEL_Msk)) | UART_FUNCSEL_SINGLE_WIRE);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group UART_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,705 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file usbd.c
|
||||
* @version V1.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 18/06/12 9:23a $
|
||||
* @brief M031 series USBD driver source file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
|
||||
#include <string.h>
|
||||
#include "NuMicro.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup USBD_Driver USBD Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Global variables for Control Pipe */
|
||||
uint8_t g_usbd_SetupPacket[8] = {0ul}; /*!< Setup packet buffer */
|
||||
volatile uint8_t g_usbd_RemoteWakeupEn = 0ul; /*!< Remote wake up function enable flag */
|
||||
|
||||
/**
|
||||
* @cond HIDDEN_SYMBOLS
|
||||
*/
|
||||
static uint8_t *g_usbd_CtrlInPointer = 0;
|
||||
static uint8_t *g_usbd_CtrlOutPointer = 0;
|
||||
static volatile uint32_t g_usbd_CtrlInSize = 0ul;
|
||||
static volatile uint32_t g_usbd_CtrlOutSize = 0ul;
|
||||
static volatile uint32_t g_usbd_CtrlOutSizeLimit = 0ul;
|
||||
static volatile uint32_t g_usbd_UsbAddr = 0ul;
|
||||
static volatile uint32_t g_usbd_UsbConfig = 0ul;
|
||||
static volatile uint32_t g_usbd_CtrlMaxPktSize = 8ul;
|
||||
static volatile uint32_t g_usbd_UsbAltInterface = 0ul;
|
||||
static volatile uint8_t g_usbd_CtrlInZeroFlag = 0ul;
|
||||
/**
|
||||
* @endcond
|
||||
*/
|
||||
|
||||
const S_USBD_INFO_T *g_usbd_sInfo; /*!< A pointer for USB information structure */
|
||||
|
||||
VENDOR_REQ g_usbd_pfnVendorRequest = NULL; /*!< USB Vendor Request Functional Pointer */
|
||||
CLASS_REQ g_usbd_pfnClassRequest = NULL; /*!< USB Class Request Functional Pointer */
|
||||
SET_INTERFACE_REQ g_usbd_pfnSetInterface = NULL; /*!< USB Set Interface Functional Pointer */
|
||||
SET_CONFIG_CB g_usbd_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */
|
||||
uint32_t g_u32EpStallLock = 0ul; /*!< Bit map flag to lock specified EP when SET_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief This function makes USBD module to be ready to use
|
||||
*
|
||||
* @param[in] param The structure of USBD information.
|
||||
* @param[in] pfnClassReq USB Class request callback function.
|
||||
* @param[in] pfnSetInterface USB Set Interface request callback function.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus.
|
||||
*/
|
||||
void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface)
|
||||
{
|
||||
g_usbd_sInfo = param;
|
||||
g_usbd_pfnClassRequest = pfnClassReq;
|
||||
g_usbd_pfnSetInterface = pfnSetInterface;
|
||||
|
||||
/* get EP0 maximum packet size */
|
||||
g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7];
|
||||
|
||||
/* Initial USB engine */
|
||||
USBD->ATTR = 0x6D0ul;
|
||||
/* Force SE0 */
|
||||
USBD_SET_SE0();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function makes USB host to recognize the device
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer.
|
||||
*/
|
||||
void USBD_Start(void)
|
||||
{
|
||||
/* Disable software-disconnect function */
|
||||
USBD_CLR_SE0();
|
||||
USBD->ATTR = 0x7D0ul;
|
||||
|
||||
/* Clear USB-related interrupts before enable interrupt */
|
||||
USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
|
||||
|
||||
/* Enable USB-related interrupts. */
|
||||
USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the received SETUP packet
|
||||
*
|
||||
* @param[in] buf A buffer pointer used to store 8-byte SETUP packet.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Store SETUP packet to a user-specified buffer.
|
||||
*
|
||||
*/
|
||||
void USBD_GetSetupPacket(uint8_t *buf)
|
||||
{
|
||||
USBD_MemCopy(buf, g_usbd_SetupPacket, 8ul);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Process SETUP packet
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Parse SETUP packet and perform the corresponding action.
|
||||
*
|
||||
*/
|
||||
void USBD_ProcessSetupPacket(void)
|
||||
{
|
||||
/* Get SETUP packet from USB buffer */
|
||||
USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8ul);
|
||||
|
||||
/* Check the request type */
|
||||
switch(g_usbd_SetupPacket[0] & 0x60ul)
|
||||
{
|
||||
case REQ_STANDARD:
|
||||
{
|
||||
USBD_StandardRequest();
|
||||
break;
|
||||
}
|
||||
case REQ_CLASS:
|
||||
{
|
||||
if(g_usbd_pfnClassRequest != NULL)
|
||||
{
|
||||
g_usbd_pfnClassRequest();
|
||||
}
|
||||
break;
|
||||
}
|
||||
case REQ_VENDOR:
|
||||
{
|
||||
if(g_usbd_pfnVendorRequest != NULL)
|
||||
{
|
||||
g_usbd_pfnVendorRequest();
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
/* Setup error, stall the device */
|
||||
USBD_SET_EP_STALL(EP0);
|
||||
USBD_SET_EP_STALL(EP1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Process GetDescriptor request
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Parse GetDescriptor request and perform the corresponding action.
|
||||
*
|
||||
*/
|
||||
void USBD_GetDescriptor(void)
|
||||
{
|
||||
uint32_t u32Len;
|
||||
|
||||
u32Len = 0ul;
|
||||
u32Len = g_usbd_SetupPacket[7];
|
||||
u32Len <<= 8ul;
|
||||
u32Len += g_usbd_SetupPacket[6];
|
||||
|
||||
switch(g_usbd_SetupPacket[3])
|
||||
{
|
||||
/* Get Device Descriptor */
|
||||
case DESC_DEVICE:
|
||||
{
|
||||
u32Len = USBD_Minimum(u32Len, (uint32_t)LEN_DEVICE);
|
||||
USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len);
|
||||
break;
|
||||
}
|
||||
/* Get Configuration Descriptor */
|
||||
case DESC_CONFIG:
|
||||
{
|
||||
uint32_t u32TotalLen;
|
||||
u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3];
|
||||
u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8);
|
||||
u32Len = USBD_Minimum(u32Len, u32TotalLen);
|
||||
USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Get BOS Descriptor */
|
||||
case DESC_BOS:
|
||||
{
|
||||
if(g_usbd_sInfo->gu8BosDesc)
|
||||
{
|
||||
u32Len = USBD_Minimum(u32Len, LEN_BOS+LEN_BOSCAP);
|
||||
USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8BosDesc, u32Len);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Not support. Reply STALL. */
|
||||
USBD_SET_EP_STALL(EP0);
|
||||
USBD_SET_EP_STALL(EP1);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
/* Get HID Descriptor */
|
||||
case DESC_HID:
|
||||
{
|
||||
/* CV3.0 HID Class Descriptor Test,
|
||||
Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */
|
||||
uint32_t u32ConfigDescOffset; /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */
|
||||
u32Len = USBD_Minimum(u32Len, LEN_HID);
|
||||
u32ConfigDescOffset = g_usbd_sInfo->gu32ConfigHidDescIdx[g_usbd_SetupPacket[4]];
|
||||
USBD_PrepareCtrlIn((uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len);
|
||||
break;
|
||||
}
|
||||
/* Get Report Descriptor */
|
||||
case DESC_HID_RPT:
|
||||
{
|
||||
u32Len = USBD_Minimum(u32Len, g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]);
|
||||
USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[g_usbd_SetupPacket[4]], u32Len);
|
||||
break;
|
||||
}
|
||||
/* Get String Descriptor */
|
||||
case DESC_STRING:
|
||||
{
|
||||
/* Get String Descriptor */
|
||||
if(g_usbd_SetupPacket[2] < 4ul)
|
||||
{
|
||||
u32Len = USBD_Minimum(u32Len, g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]);
|
||||
USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]], u32Len);
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Not support. Reply STALL. */
|
||||
USBD_SET_EP_STALL(EP0);
|
||||
USBD_SET_EP_STALL(EP1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
default:
|
||||
/* Not support. Reply STALL.*/
|
||||
USBD_SET_EP_STALL(EP0);
|
||||
USBD_SET_EP_STALL(EP1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Process standard request
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Parse standard request and perform the corresponding action.
|
||||
*
|
||||
*/
|
||||
void USBD_StandardRequest(void)
|
||||
{
|
||||
uint32_t addr;
|
||||
/* clear global variables for new request */
|
||||
g_usbd_CtrlInPointer = 0;
|
||||
g_usbd_CtrlInSize = 0ul;
|
||||
|
||||
if((g_usbd_SetupPacket[0] & 0x80ul) == 0x80ul) /* request data transfer direction */
|
||||
{
|
||||
/* Device to host */
|
||||
switch(g_usbd_SetupPacket[1])
|
||||
{
|
||||
case GET_CONFIGURATION:
|
||||
{
|
||||
/* Return current configuration setting */
|
||||
/* Data stage */
|
||||
addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
|
||||
M8(addr) = (uint8_t)g_usbd_UsbConfig;
|
||||
USBD_SET_DATA1(EP0);
|
||||
USBD_SET_PAYLOAD_LEN(EP0, 1ul);
|
||||
/* Status stage */
|
||||
USBD_PrepareCtrlOut(0, 0ul);
|
||||
break;
|
||||
}
|
||||
case GET_DESCRIPTOR:
|
||||
{
|
||||
USBD_GetDescriptor();
|
||||
USBD_PrepareCtrlOut(0, 0ul); /* For status stage */
|
||||
break;
|
||||
}
|
||||
case GET_INTERFACE:
|
||||
{
|
||||
/* Return current interface setting */
|
||||
/* Data stage */
|
||||
addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
|
||||
M8(addr) = (uint8_t)g_usbd_UsbAltInterface;
|
||||
USBD_SET_DATA1(EP0);
|
||||
USBD_SET_PAYLOAD_LEN(EP0, 1ul);
|
||||
/* Status stage */
|
||||
USBD_PrepareCtrlOut(0, 0ul);
|
||||
break;
|
||||
}
|
||||
case GET_STATUS:
|
||||
{
|
||||
/* Device */
|
||||
if(g_usbd_SetupPacket[0] == 0x80ul)
|
||||
{
|
||||
uint8_t u8Tmp;
|
||||
|
||||
u8Tmp = (uint8_t)0ul;
|
||||
if ((g_usbd_sInfo->gu8ConfigDesc[7] & 0x40ul) == 0x40ul)
|
||||
{
|
||||
u8Tmp |= (uint8_t)1ul; /* Self-Powered/Bus-Powered.*/
|
||||
}
|
||||
if ((g_usbd_sInfo->gu8ConfigDesc[7] & 0x20ul) == 0x20ul)
|
||||
{
|
||||
u8Tmp |= (uint8_t)(g_usbd_RemoteWakeupEn << 1ul); /* Remote wake up */
|
||||
}
|
||||
|
||||
addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
|
||||
M8(addr) = u8Tmp;
|
||||
}
|
||||
/* Interface */
|
||||
else if(g_usbd_SetupPacket[0] == 0x81ul)
|
||||
{
|
||||
addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
|
||||
M8(addr) = (uint8_t)0ul;
|
||||
}
|
||||
/* Endpoint */
|
||||
else if(g_usbd_SetupPacket[0] == 0x82ul)
|
||||
{
|
||||
uint8_t ep = (uint8_t)(g_usbd_SetupPacket[4] & 0xFul);
|
||||
addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
|
||||
M8(addr) = (uint8_t)(USBD_GetStall(ep) ? 1ul : 0ul);
|
||||
}
|
||||
|
||||
addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1ul;
|
||||
M8(addr) = (uint8_t)0ul;
|
||||
/* Data stage */
|
||||
USBD_SET_DATA1(EP0);
|
||||
USBD_SET_PAYLOAD_LEN(EP0, 2ul);
|
||||
/* Status stage */
|
||||
USBD_PrepareCtrlOut(0, 0ul);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
/* Setup error, stall the device */
|
||||
USBD_SET_EP_STALL(EP0);
|
||||
USBD_SET_EP_STALL(EP1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Host to device */
|
||||
switch(g_usbd_SetupPacket[1])
|
||||
{
|
||||
case CLEAR_FEATURE:
|
||||
{
|
||||
if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT)
|
||||
{
|
||||
uint32_t epNum, i;
|
||||
/* EP number stall is not allow to be clear in MSC class "Error Recovery Test".
|
||||
a flag: g_u32EpStallLock is added to support it */
|
||||
epNum = (uint8_t)(g_usbd_SetupPacket[4] & 0xFul);
|
||||
for(i = 0ul; i < USBD_MAX_EP; i++)
|
||||
{
|
||||
if(((USBD->EP[i].CFG & 0xFul) == epNum) && ((g_u32EpStallLock & (1ul << i)) == 0ul))
|
||||
{
|
||||
USBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
|
||||
{
|
||||
g_usbd_RemoteWakeupEn = (uint8_t)0;
|
||||
}
|
||||
/* Status stage */
|
||||
USBD_SET_DATA1(EP0);
|
||||
USBD_SET_PAYLOAD_LEN(EP0, 0ul);
|
||||
break;
|
||||
}
|
||||
case SET_ADDRESS:
|
||||
{
|
||||
g_usbd_UsbAddr = g_usbd_SetupPacket[2];
|
||||
/* Status Stage */
|
||||
USBD_SET_DATA1(EP0);
|
||||
USBD_SET_PAYLOAD_LEN(EP0, 0ul);
|
||||
|
||||
break;
|
||||
}
|
||||
case SET_CONFIGURATION:
|
||||
{
|
||||
g_usbd_UsbConfig = g_usbd_SetupPacket[2];
|
||||
|
||||
if(g_usbd_pfnSetConfigCallback)
|
||||
{
|
||||
g_usbd_pfnSetConfigCallback();
|
||||
}
|
||||
|
||||
/* Status stage */
|
||||
USBD_SET_DATA1(EP0);
|
||||
USBD_SET_PAYLOAD_LEN(EP0, 0ul);
|
||||
break;
|
||||
}
|
||||
case SET_FEATURE:
|
||||
{
|
||||
if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT)
|
||||
{
|
||||
USBD_SetStall((uint8_t)(g_usbd_SetupPacket[4] & 0xFul));
|
||||
}
|
||||
else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
|
||||
{
|
||||
g_usbd_RemoteWakeupEn = (uint8_t)1ul;
|
||||
}
|
||||
|
||||
/* Status stage */
|
||||
USBD_SET_DATA1(EP0);
|
||||
USBD_SET_PAYLOAD_LEN(EP0, 0ul);
|
||||
|
||||
break;
|
||||
}
|
||||
case SET_INTERFACE:
|
||||
{
|
||||
g_usbd_UsbAltInterface = g_usbd_SetupPacket[2];
|
||||
if(g_usbd_pfnSetInterface != NULL)
|
||||
{
|
||||
g_usbd_pfnSetInterface(g_usbd_UsbAltInterface);
|
||||
}
|
||||
/* Status stage */
|
||||
USBD_SET_DATA1(EP0);
|
||||
USBD_SET_PAYLOAD_LEN(EP0, 0ul);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
/* Setup error, stall the device */
|
||||
USBD_SET_EP_STALL(EP0);
|
||||
USBD_SET_EP_STALL(EP1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Prepare the first Control IN pipe
|
||||
*
|
||||
* @param[in] pu8Buf The pointer of data sent to USB host.
|
||||
* @param[in] u32Size The IN transfer size.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Prepare data for Control IN transfer.
|
||||
*
|
||||
*/
|
||||
void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size)
|
||||
{
|
||||
uint32_t addr;
|
||||
if(u32Size > g_usbd_CtrlMaxPktSize)
|
||||
{
|
||||
/* Data size > MXPLD */
|
||||
g_usbd_CtrlInPointer = pu8Buf + g_usbd_CtrlMaxPktSize;
|
||||
g_usbd_CtrlInSize = u32Size - g_usbd_CtrlMaxPktSize;
|
||||
USBD_SET_DATA1(EP0);
|
||||
addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
|
||||
USBD_MemCopy((uint8_t *)addr, pu8Buf, g_usbd_CtrlMaxPktSize);
|
||||
USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Data size <= MXPLD */
|
||||
g_usbd_CtrlInPointer = 0;
|
||||
g_usbd_CtrlInSize = 0ul;
|
||||
if (u32Size == g_usbd_CtrlMaxPktSize)
|
||||
g_usbd_CtrlInZeroFlag = 1ul;
|
||||
USBD_SET_DATA1(EP0);
|
||||
addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
|
||||
USBD_MemCopy((uint8_t *)addr, pu8Buf, u32Size);
|
||||
USBD_SET_PAYLOAD_LEN(EP0, u32Size);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Repeat Control IN pipe
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function processes the remained data of Control IN transfer.
|
||||
*
|
||||
*/
|
||||
void USBD_CtrlIn(void)
|
||||
{
|
||||
uint32_t addr;
|
||||
|
||||
if(g_usbd_CtrlInSize)
|
||||
{
|
||||
/* Process remained data */
|
||||
if(g_usbd_CtrlInSize > g_usbd_CtrlMaxPktSize)
|
||||
{
|
||||
/* Data size > MXPLD */
|
||||
addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
|
||||
USBD_MemCopy((uint8_t *)addr, (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlMaxPktSize);
|
||||
USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize);
|
||||
g_usbd_CtrlInPointer += g_usbd_CtrlMaxPktSize;
|
||||
g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Data size <= MXPLD */
|
||||
addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
|
||||
USBD_MemCopy((uint8_t *)addr, (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlInSize);
|
||||
USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlInSize);
|
||||
if(g_usbd_CtrlInSize == g_usbd_CtrlMaxPktSize)
|
||||
g_usbd_CtrlInZeroFlag = 1ul;
|
||||
g_usbd_CtrlInPointer = 0ul;
|
||||
g_usbd_CtrlInSize = 0ul;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* In ACK for Set address */
|
||||
if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS))
|
||||
{
|
||||
addr = USBD_GET_ADDR();
|
||||
if((addr != g_usbd_UsbAddr) && (addr == 0ul))
|
||||
USBD_SET_ADDR(g_usbd_UsbAddr);
|
||||
}
|
||||
|
||||
/* For the case of data size is integral times maximum packet size */
|
||||
if (g_usbd_CtrlInZeroFlag)
|
||||
{
|
||||
USBD_SET_PAYLOAD_LEN(EP0, 0ul);
|
||||
g_usbd_CtrlInZeroFlag = 0ul;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Prepare the first Control OUT pipe
|
||||
*
|
||||
* @param[in] pu8Buf The pointer of data received from USB host.
|
||||
* @param[in] u32Size The OUT transfer size.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to prepare the first Control OUT transfer.
|
||||
*
|
||||
*/
|
||||
void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size)
|
||||
{
|
||||
g_usbd_CtrlOutPointer = pu8Buf;
|
||||
g_usbd_CtrlOutSize = 0ul;
|
||||
g_usbd_CtrlOutSizeLimit = u32Size;
|
||||
USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Repeat Control OUT pipe
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function processes the successive Control OUT transfer.
|
||||
*
|
||||
*/
|
||||
void USBD_CtrlOut(void)
|
||||
{
|
||||
uint32_t u32Size;
|
||||
uint32_t addr;
|
||||
|
||||
if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit)
|
||||
{
|
||||
u32Size = USBD_GET_PAYLOAD_LEN(EP1);
|
||||
addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1);
|
||||
USBD_MemCopy((uint8_t *)g_usbd_CtrlOutPointer, (uint8_t *)addr, u32Size);
|
||||
g_usbd_CtrlOutPointer += u32Size;
|
||||
g_usbd_CtrlOutSize += u32Size;
|
||||
|
||||
if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit)
|
||||
{
|
||||
USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset software flags
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function resets all variables for protocol and resets USB device address to 0.
|
||||
*
|
||||
*/
|
||||
void USBD_SwReset(void)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
/* Reset all variables for protocol */
|
||||
g_usbd_CtrlInPointer = 0;
|
||||
g_usbd_CtrlInSize = 0ul;
|
||||
g_usbd_CtrlOutPointer = 0;
|
||||
g_usbd_CtrlOutSize = 0ul;
|
||||
g_usbd_CtrlOutSizeLimit = 0ul;
|
||||
g_u32EpStallLock = 0ul;
|
||||
memset(g_usbd_SetupPacket, 0, 8ul);
|
||||
|
||||
/* Reset PID DATA0 */
|
||||
for(i=0ul; i<USBD_MAX_EP; i++)
|
||||
{
|
||||
USBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk;
|
||||
}
|
||||
|
||||
/* Reset USB device address */
|
||||
USBD_SET_ADDR(0ul);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD Set Vendor Request
|
||||
*
|
||||
* @param[in] pfnVendorReq Vendor Request Callback Function
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to set USBD vendor request callback function
|
||||
*/
|
||||
void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq)
|
||||
{
|
||||
g_usbd_pfnVendorRequest = pfnVendorReq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief The callback function which called when get SET CONFIGURATION request
|
||||
*
|
||||
* @param[in] pfnSetConfigCallback Callback function pointer for SET CONFIGURATION request
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to set the callback function which will be called at SET CONFIGURATION request.
|
||||
*/
|
||||
void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback)
|
||||
{
|
||||
g_usbd_pfnSetConfigCallback = pfnSetConfigCallback;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief EP stall lock function to avoid stall clear by USB SET FEATURE request.
|
||||
*
|
||||
* @param[in] u32EpBitmap Use bitmap to select which endpoints will be locked
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to lock relative endpoint to avoid stall clear by SET FEATURE request.
|
||||
* If ep stall locked, user needs to reset USB device or re-configure device to clear it.
|
||||
*/
|
||||
void USBD_LockEpStall(uint32_t u32EpBitmap)
|
||||
{
|
||||
g_u32EpStallLock = u32EpBitmap;
|
||||
}
|
||||
|
||||
|
||||
/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group USBD_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,635 +0,0 @@
|
|||
/****************************************************************************//**
|
||||
* @file usci_spi.c
|
||||
* @version V1.00
|
||||
* @brief M031 series USCI_SPI driver source file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "M031Series.h"
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup USCI_SPI_Driver USCI_SPI Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function make USCI_SPI module be ready to transfer.
|
||||
* By default, the USCI_SPI transfer sequence is MSB first, the slave selection
|
||||
* signal is active low and the automatic slave select function is disabled. In
|
||||
* Slave mode, the u32BusClock must be NULL and the USCI_SPI clock
|
||||
* divider setting will be 0.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32MasterSlave Decide the USCI_SPI module is operating in master mode or in slave mode. Valid values are:
|
||||
* - \ref USPI_SLAVE
|
||||
* - \ref USPI_MASTER
|
||||
* @param[in] u32SPIMode Decide the transfer timing. Valid values are:
|
||||
* - \ref USPI_MODE_0
|
||||
* - \ref USPI_MODE_1
|
||||
* - \ref USPI_MODE_2
|
||||
* - \ref USPI_MODE_3
|
||||
* @param[in] u32DataWidth The data width of a USCI_SPI transaction.
|
||||
* @param[in] u32BusClock The expected frequency of USCI_SPI bus clock in Hz.
|
||||
* @return Actual frequency of USCI_SPI peripheral clock.
|
||||
*/
|
||||
uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
|
||||
{
|
||||
uint32_t u32ClkDiv = 0UL;
|
||||
uint32_t u32Pclk;
|
||||
uint32_t u32RetValue = 0UL;
|
||||
|
||||
if (uspi == USPI0)
|
||||
{
|
||||
u32Pclk = CLK_GetPCLK0Freq();
|
||||
}
|
||||
else
|
||||
{
|
||||
u32Pclk = CLK_GetPCLK1Freq();
|
||||
}
|
||||
|
||||
if(u32BusClock != 0UL)
|
||||
{
|
||||
u32ClkDiv = (uint32_t)((((((u32Pclk / 2UL) * 10UL) / (u32BusClock)) + 5UL) / 10UL) - 1UL); /* Compute proper divider for USCI_SPI clock */
|
||||
}
|
||||
|
||||
/* Enable USCI_SPI protocol */
|
||||
uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;
|
||||
uspi->CTL = 1UL << USPI_CTL_FUNMODE_Pos;
|
||||
|
||||
/* Data format configuration */
|
||||
if(u32DataWidth == 16UL)
|
||||
{
|
||||
u32DataWidth = 0UL;
|
||||
}
|
||||
uspi->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk;
|
||||
uspi->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos);
|
||||
|
||||
/* MSB data format */
|
||||
uspi->LINECTL &= ~USPI_LINECTL_LSB_Msk;
|
||||
|
||||
/* Set slave selection signal active low */
|
||||
if(u32MasterSlave == USPI_MASTER)
|
||||
{
|
||||
uspi->LINECTL |= USPI_LINECTL_CTLOINV_Msk;
|
||||
}
|
||||
else
|
||||
{
|
||||
uspi->CTLIN0 |= USPI_CTLIN0_ININV_Msk;
|
||||
}
|
||||
|
||||
/* Set operating mode and transfer timing */
|
||||
uspi->PROTCTL &= ~(USPI_PROTCTL_SCLKMODE_Msk | USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SLAVE_Msk);
|
||||
uspi->PROTCTL |= (u32MasterSlave | u32SPIMode);
|
||||
|
||||
/* Set USCI_SPI bus clock */
|
||||
uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;
|
||||
uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);
|
||||
uspi->PROTCTL |= USPI_PROTCTL_PROTEN_Msk;
|
||||
|
||||
if(u32BusClock != 0UL)
|
||||
{
|
||||
u32RetValue = (u32Pclk / ((u32ClkDiv + 1UL) << 1UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
u32RetValue = 0UL;
|
||||
}
|
||||
|
||||
return u32RetValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable USCI_SPI function mode.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None
|
||||
*/
|
||||
void USPI_Close(USPI_T *uspi)
|
||||
{
|
||||
uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Rx buffer.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None
|
||||
*/
|
||||
void USPI_ClearRxBuf(USPI_T *uspi)
|
||||
{
|
||||
uspi->BUFCTL |= USPI_BUFCTL_RXCLR_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Tx buffer.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None
|
||||
*/
|
||||
void USPI_ClearTxBuf(USPI_T *uspi)
|
||||
{
|
||||
uspi->BUFCTL |= USPI_BUFCTL_TXCLR_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the automatic slave select function.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None
|
||||
*/
|
||||
void USPI_DisableAutoSS(USPI_T *uspi)
|
||||
{
|
||||
uspi->PROTCTL &= ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the automatic slave select function. Only available in Master mode.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32SSPinMask This parameter is not used.
|
||||
* @param[in] u32ActiveLevel The active level of slave select signal. Valid values are:
|
||||
* - \ref USPI_SS_ACTIVE_HIGH
|
||||
* - \ref USPI_SS_ACTIVE_LOW
|
||||
* @return None
|
||||
*/
|
||||
void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
|
||||
{
|
||||
uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel;
|
||||
uspi->PROTCTL |= USPI_PROTCTL_AUTOSS_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the USCI_SPI bus clock. Only available in Master mode.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32BusClock The expected frequency of USCI_SPI bus clock.
|
||||
* @return Actual frequency of USCI_SPI peripheral clock.
|
||||
*/
|
||||
uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock)
|
||||
{
|
||||
uint32_t u32ClkDiv;
|
||||
uint32_t u32Pclk;
|
||||
|
||||
if (uspi == USPI0)
|
||||
{
|
||||
u32Pclk = CLK_GetPCLK0Freq();
|
||||
}
|
||||
else
|
||||
{
|
||||
u32Pclk = CLK_GetPCLK1Freq();
|
||||
}
|
||||
|
||||
u32ClkDiv = (uint32_t)((((((u32Pclk / 2UL) * 10UL) / (u32BusClock)) + 5UL) / 10UL) - 1UL); /* Compute proper divider for USCI_SPI clock */
|
||||
|
||||
/* Set USCI_SPI bus clock */
|
||||
uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;
|
||||
uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);
|
||||
|
||||
return (u32Pclk / ((u32ClkDiv + 1UL) << 1UL));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the actual frequency of USCI_SPI bus clock. Only available in Master mode.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return Actual USCI_SPI bus clock frequency.
|
||||
*/
|
||||
uint32_t USPI_GetBusClock(USPI_T *uspi)
|
||||
{
|
||||
uint32_t u32ClkDiv, u32BusClk;
|
||||
|
||||
u32ClkDiv = (uspi->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos;
|
||||
|
||||
if (uspi == USPI0)
|
||||
{
|
||||
u32BusClk = (CLK_GetPCLK0Freq() / ((u32ClkDiv + 1UL) << 1UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
u32BusClk = (CLK_GetPCLK1Freq() / ((u32ClkDiv + 1UL) << 1UL));
|
||||
}
|
||||
|
||||
return u32BusClk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable related interrupts specified by u32Mask parameter.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32Mask The combination of all related interrupt enable bits.
|
||||
* Each bit corresponds to a interrupt bit.
|
||||
* This parameter decides which interrupts will be enabled. Valid values are:
|
||||
* - \ref USPI_SSINACT_INT_MASK
|
||||
* - \ref USPI_SSACT_INT_MASK
|
||||
* - \ref USPI_SLVTO_INT_MASK
|
||||
* - \ref USPI_SLVBE_INT_MASK
|
||||
* - \ref USPI_TXUDR_INT_MASK
|
||||
* - \ref USPI_RXOV_INT_MASK
|
||||
* - \ref USPI_TXST_INT_MASK
|
||||
* - \ref USPI_TXEND_INT_MASK
|
||||
* - \ref USPI_RXST_INT_MASK
|
||||
* - \ref USPI_RXEND_INT_MASK
|
||||
* @return None
|
||||
*/
|
||||
void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask)
|
||||
{
|
||||
/* Enable slave selection signal inactive interrupt flag */
|
||||
if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK)
|
||||
{
|
||||
uspi->PROTIEN |= USPI_PROTIEN_SSINAIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable slave selection signal active interrupt flag */
|
||||
if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK)
|
||||
{
|
||||
uspi->PROTIEN |= USPI_PROTIEN_SSACTIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable slave time-out interrupt flag */
|
||||
if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK)
|
||||
{
|
||||
uspi->PROTIEN |= USPI_PROTIEN_SLVTOIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable slave bit count error interrupt flag */
|
||||
if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK)
|
||||
{
|
||||
uspi->PROTIEN |= USPI_PROTIEN_SLVBEIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable TX under run interrupt flag */
|
||||
if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK)
|
||||
{
|
||||
uspi->BUFCTL |= USPI_BUFCTL_TXUDRIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable RX overrun interrupt flag */
|
||||
if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK)
|
||||
{
|
||||
uspi->BUFCTL |= USPI_BUFCTL_RXOVIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable TX start interrupt flag */
|
||||
if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK)
|
||||
{
|
||||
uspi->INTEN |= USPI_INTEN_TXSTIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable TX end interrupt flag */
|
||||
if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK)
|
||||
{
|
||||
uspi->INTEN |= USPI_INTEN_TXENDIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable RX start interrupt flag */
|
||||
if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK)
|
||||
{
|
||||
uspi->INTEN |= USPI_INTEN_RXSTIEN_Msk;
|
||||
}
|
||||
|
||||
/* Enable RX end interrupt flag */
|
||||
if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK)
|
||||
{
|
||||
uspi->INTEN |= USPI_INTEN_RXENDIEN_Msk;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable related interrupts specified by u32Mask parameter.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32Mask The combination of all related interrupt enable bits.
|
||||
* Each bit corresponds to a interrupt bit.
|
||||
* This parameter decides which interrupts will be disabled. Valid values are:
|
||||
* - \ref USPI_SSINACT_INT_MASK
|
||||
* - \ref USPI_SSACT_INT_MASK
|
||||
* - \ref USPI_SLVTO_INT_MASK
|
||||
* - \ref USPI_SLVBE_INT_MASK
|
||||
* - \ref USPI_TXUDR_INT_MASK
|
||||
* - \ref USPI_RXOV_INT_MASK
|
||||
* - \ref USPI_TXST_INT_MASK
|
||||
* - \ref USPI_TXEND_INT_MASK
|
||||
* - \ref USPI_RXST_INT_MASK
|
||||
* - \ref USPI_RXEND_INT_MASK
|
||||
* @return None
|
||||
*/
|
||||
void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask)
|
||||
{
|
||||
/* Disable slave selection signal inactive interrupt flag */
|
||||
if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK)
|
||||
{
|
||||
uspi->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable slave selection signal active interrupt flag */
|
||||
if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK)
|
||||
{
|
||||
uspi->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable slave time-out interrupt flag */
|
||||
if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK)
|
||||
{
|
||||
uspi->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable slave bit count error interrupt flag */
|
||||
if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK)
|
||||
{
|
||||
uspi->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable TX under run interrupt flag */
|
||||
if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK)
|
||||
{
|
||||
uspi->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable RX overrun interrupt flag */
|
||||
if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK)
|
||||
{
|
||||
uspi->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable TX start interrupt flag */
|
||||
if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK)
|
||||
{
|
||||
uspi->INTEN &= ~USPI_INTEN_TXSTIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable TX end interrupt flag */
|
||||
if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK)
|
||||
{
|
||||
uspi->INTEN &= ~USPI_INTEN_TXENDIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable RX start interrupt flag */
|
||||
if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK)
|
||||
{
|
||||
uspi->INTEN &= ~USPI_INTEN_RXSTIEN_Msk;
|
||||
}
|
||||
|
||||
/* Disable RX end interrupt flag */
|
||||
if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK)
|
||||
{
|
||||
uspi->INTEN &= ~USPI_INTEN_RXENDIEN_Msk;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt flag.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32Mask The combination of all related interrupt sources.
|
||||
* Each bit corresponds to a interrupt source.
|
||||
* This parameter decides which interrupt flags will be read. It is combination of:
|
||||
* - \ref USPI_SSINACT_INT_MASK
|
||||
* - \ref USPI_SSACT_INT_MASK
|
||||
* - \ref USPI_SLVTO_INT_MASK
|
||||
* - \ref USPI_SLVBE_INT_MASK
|
||||
* - \ref USPI_TXUDR_INT_MASK
|
||||
* - \ref USPI_RXOV_INT_MASK
|
||||
* - \ref USPI_TXST_INT_MASK
|
||||
* - \ref USPI_TXEND_INT_MASK
|
||||
* - \ref USPI_RXST_INT_MASK
|
||||
* - \ref USPI_RXEND_INT_MASK
|
||||
* @return Interrupt flags of selected sources.
|
||||
*/
|
||||
uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask)
|
||||
{
|
||||
uint32_t u32ProtStatus, u32BufStatus;
|
||||
uint32_t u32IntFlag = 0UL;
|
||||
|
||||
u32ProtStatus = uspi->PROTSTS;
|
||||
u32BufStatus = uspi->BUFSTS;
|
||||
|
||||
/* Check slave selection signal inactive interrupt flag */
|
||||
if((u32Mask & USPI_SSINACT_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SSINAIF_Msk))
|
||||
{
|
||||
u32IntFlag |= USPI_SSINACT_INT_MASK;
|
||||
}
|
||||
|
||||
/* Check slave selection signal active interrupt flag */
|
||||
if((u32Mask & USPI_SSACT_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SSACTIF_Msk))
|
||||
{
|
||||
u32IntFlag |= USPI_SSACT_INT_MASK;
|
||||
}
|
||||
|
||||
/* Check slave time-out interrupt flag */
|
||||
if((u32Mask & USPI_SLVTO_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SLVTOIF_Msk))
|
||||
{
|
||||
u32IntFlag |= USPI_SLVTO_INT_MASK;
|
||||
}
|
||||
|
||||
/* Check slave bit count error interrupt flag */
|
||||
if((u32Mask & USPI_SLVBE_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SLVBEIF_Msk))
|
||||
{
|
||||
u32IntFlag |= USPI_SLVBE_INT_MASK;
|
||||
}
|
||||
|
||||
/* Check TX under run interrupt flag */
|
||||
if((u32Mask & USPI_TXUDR_INT_MASK) && (u32BufStatus & USPI_BUFSTS_TXUDRIF_Msk))
|
||||
{
|
||||
u32IntFlag |= USPI_TXUDR_INT_MASK;
|
||||
}
|
||||
|
||||
/* Check RX overrun interrupt flag */
|
||||
if((u32Mask & USPI_RXOV_INT_MASK) && (u32BufStatus & USPI_BUFSTS_RXOVIF_Msk))
|
||||
{
|
||||
u32IntFlag |= USPI_RXOV_INT_MASK;
|
||||
}
|
||||
|
||||
/* Check TX start interrupt flag */
|
||||
if((u32Mask & USPI_TXST_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_TXSTIF_Msk))
|
||||
{
|
||||
u32IntFlag |= USPI_TXST_INT_MASK;
|
||||
}
|
||||
|
||||
/* Check TX end interrupt flag */
|
||||
if((u32Mask & USPI_TXEND_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_TXENDIF_Msk))
|
||||
{
|
||||
u32IntFlag |= USPI_TXEND_INT_MASK;
|
||||
}
|
||||
|
||||
/* Check RX start interrupt flag */
|
||||
if((u32Mask & USPI_RXST_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_RXSTIF_Msk))
|
||||
{
|
||||
u32IntFlag |= USPI_RXST_INT_MASK;
|
||||
}
|
||||
|
||||
/* Check RX end interrupt flag */
|
||||
if((u32Mask & USPI_RXEND_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_RXENDIF_Msk))
|
||||
{
|
||||
u32IntFlag |= USPI_RXEND_INT_MASK;
|
||||
}
|
||||
|
||||
return u32IntFlag;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt flag.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32Mask The combination of all related interrupt sources.
|
||||
* Each bit corresponds to a interrupt source.
|
||||
* This parameter decides which interrupt flags will be cleared. It could be the combination of:
|
||||
* - \ref USPI_SSINACT_INT_MASK
|
||||
* - \ref USPI_SSACT_INT_MASK
|
||||
* - \ref USPI_SLVTO_INT_MASK
|
||||
* - \ref USPI_SLVBE_INT_MASK
|
||||
* - \ref USPI_TXUDR_INT_MASK
|
||||
* - \ref USPI_RXOV_INT_MASK
|
||||
* - \ref USPI_TXST_INT_MASK
|
||||
* - \ref USPI_TXEND_INT_MASK
|
||||
* - \ref USPI_RXST_INT_MASK
|
||||
* - \ref USPI_RXEND_INT_MASK
|
||||
* @return None
|
||||
*/
|
||||
void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask)
|
||||
{
|
||||
/* Clear slave selection signal inactive interrupt flag */
|
||||
if(u32Mask & USPI_SSINACT_INT_MASK)
|
||||
{
|
||||
uspi->PROTSTS = USPI_PROTSTS_SSINAIF_Msk;
|
||||
}
|
||||
|
||||
/* Clear slave selection signal active interrupt flag */
|
||||
if(u32Mask & USPI_SSACT_INT_MASK)
|
||||
{
|
||||
uspi->PROTSTS = USPI_PROTSTS_SSACTIF_Msk;
|
||||
}
|
||||
|
||||
/* Clear slave time-out interrupt flag */
|
||||
if(u32Mask & USPI_SLVTO_INT_MASK)
|
||||
{
|
||||
uspi->PROTSTS = USPI_PROTSTS_SLVTOIF_Msk;
|
||||
}
|
||||
|
||||
/* Clear slave bit count error interrupt flag */
|
||||
if(u32Mask & USPI_SLVBE_INT_MASK)
|
||||
{
|
||||
uspi->PROTSTS = USPI_PROTSTS_SLVBEIF_Msk;
|
||||
}
|
||||
|
||||
/* Clear TX under run interrupt flag */
|
||||
if(u32Mask & USPI_TXUDR_INT_MASK)
|
||||
{
|
||||
uspi->BUFSTS = USPI_BUFSTS_TXUDRIF_Msk;
|
||||
}
|
||||
|
||||
/* Clear RX overrun interrupt flag */
|
||||
if(u32Mask & USPI_RXOV_INT_MASK)
|
||||
{
|
||||
uspi->BUFSTS = USPI_BUFSTS_RXOVIF_Msk;
|
||||
}
|
||||
|
||||
/* Clear TX start interrupt flag */
|
||||
if(u32Mask & USPI_TXST_INT_MASK)
|
||||
{
|
||||
uspi->PROTSTS = USPI_PROTSTS_TXSTIF_Msk;
|
||||
}
|
||||
|
||||
/* Clear TX end interrupt flag */
|
||||
if(u32Mask & USPI_TXEND_INT_MASK)
|
||||
{
|
||||
uspi->PROTSTS = USPI_PROTSTS_TXENDIF_Msk;
|
||||
}
|
||||
|
||||
/* Clear RX start interrupt flag */
|
||||
if(u32Mask & USPI_RXST_INT_MASK)
|
||||
{
|
||||
uspi->PROTSTS = USPI_PROTSTS_RXSTIF_Msk;
|
||||
}
|
||||
|
||||
/* Clear RX end interrupt flag */
|
||||
if(u32Mask & USPI_RXEND_INT_MASK)
|
||||
{
|
||||
uspi->PROTSTS = USPI_PROTSTS_RXENDIF_Msk;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get USCI_SPI status.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @param[in] u32Mask The combination of all related sources.
|
||||
* Each bit corresponds to a source.
|
||||
* This parameter decides which flags will be read. It is combination of:
|
||||
* - \ref USPI_BUSY_MASK
|
||||
* - \ref USPI_RX_EMPTY_MASK
|
||||
* - \ref USPI_RX_FULL_MASK
|
||||
* - \ref USPI_TX_EMPTY_MASK
|
||||
* - \ref USPI_TX_FULL_MASK
|
||||
* - \ref USPI_SSLINE_STS_MASK
|
||||
* @return Flags of selected sources.
|
||||
*/
|
||||
uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask)
|
||||
{
|
||||
uint32_t u32ProtStatus, u32BufStatus;
|
||||
uint32_t u32Flag = 0UL;
|
||||
|
||||
u32ProtStatus = uspi->PROTSTS;
|
||||
u32BufStatus = uspi->BUFSTS;
|
||||
|
||||
/* Check busy status */
|
||||
if((u32Mask & USPI_BUSY_MASK) && (u32ProtStatus & USPI_PROTSTS_BUSY_Msk))
|
||||
{
|
||||
u32Flag |= USPI_BUSY_MASK;
|
||||
}
|
||||
|
||||
/* Check RX empty flag */
|
||||
if((u32Mask & USPI_RX_EMPTY_MASK) && (u32BufStatus & USPI_BUFSTS_RXEMPTY_Msk))
|
||||
{
|
||||
u32Flag |= USPI_RX_EMPTY_MASK;
|
||||
}
|
||||
|
||||
/* Check RX full flag */
|
||||
if((u32Mask & USPI_RX_FULL_MASK) && (u32BufStatus & USPI_BUFSTS_RXFULL_Msk))
|
||||
{
|
||||
u32Flag |= USPI_RX_FULL_MASK;
|
||||
}
|
||||
|
||||
/* Check TX empty flag */
|
||||
if((u32Mask & USPI_TX_EMPTY_MASK) && (u32BufStatus & USPI_BUFSTS_TXEMPTY_Msk))
|
||||
{
|
||||
u32Flag |= USPI_TX_EMPTY_MASK;
|
||||
}
|
||||
|
||||
/* Check TX full flag */
|
||||
if((u32Mask & USPI_TX_FULL_MASK) && (u32BufStatus & USPI_BUFSTS_TXFULL_Msk))
|
||||
{
|
||||
u32Flag |= USPI_TX_FULL_MASK;
|
||||
}
|
||||
|
||||
/* Check USCI_SPI_SS line status */
|
||||
if((u32Mask & USPI_SSLINE_STS_MASK) && (u32ProtStatus & USPI_PROTSTS_SSLINE_Msk))
|
||||
{
|
||||
u32Flag |= USPI_SSLINE_STS_MASK;
|
||||
}
|
||||
|
||||
return u32Flag;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable USCI_SPI Wake-up Function.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None
|
||||
*/
|
||||
void USPI_EnableWakeup(USPI_T *uspi)
|
||||
{
|
||||
uspi->WKCTL |= USPI_WKCTL_WKEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable USCI_SPI Wake-up Function.
|
||||
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||
* @return None
|
||||
*/
|
||||
void USPI_DisableWakeup(USPI_T *uspi)
|
||||
{
|
||||
uspi->WKCTL &= ~USPI_WKCTL_WKEN_Msk;
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group USCI_SPI_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue