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add hc32f4a0

This commit is contained in:
chengy4 2020-12-25 14:33:03 +08:00
parent c924330469
commit c5461139f1
178 changed files with 353983 additions and 0 deletions
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533
bsp/hc32f4a0/.config Normal file
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#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Project Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40003
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M4=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
# CONFIG_RT_USING_MODULE is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_PPOOL is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# games: games run on RT-Thread console
#
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
#
# Hardware Drivers Config
#
CONFIG_MCU_HC32F4A0=y
#
# Onboard Peripheral Drivers
#
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
CONFIG_BSP_UART1_RX_USING_DMA=y
CONFIG_BSP_UART1_TX_USING_DMA=y
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
# CONFIG_BSP_USING_UART6 is not set
# CONFIG_BSP_USING_UART7 is not set
# CONFIG_BSP_USING_UART8 is not set
# CONFIG_BSP_USING_UART9 is not set
# CONFIG_BSP_USING_UART10 is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_RTC is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_TIMER is not set
# CONFIG_BSP_USING_PULSE_ENCODER is not set
#
# Board extended module Drivers
#

42
bsp/hc32f4a0/.gitignore vendored Normal file
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@ -0,0 +1,42 @@
*.pyc
*.map
*.dblite
*.elf
*.bin
*.hex
*.axf
*.exe
*.pdb
*.idb
*.ilk
*.old
build
Debug
documentation/html
packages/
*~
*.o
*.obj
*.out
*.bak
*.dep
*.lib
*.i
*.d
.DS_Stor*
.config 3
.config 4
.config 5
Midea-X1
*.uimg
GPATH
GRTAGS
GTAGS
.vscode
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h

23
bsp/hc32f4a0/Kconfig Normal file
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mainmenu "RT-Thread Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "board/Kconfig"

214
bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/ddl_config.h Normal file
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/**
*******************************************************************************
* @file adc/adc_01_base/source/ddl_config.h
* @brief This file contains HC32 Series Device Driver Library usage management.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __DDL_CONFIG_H__
#define __DDL_CONFIG_H__
/*******************************************************************************
* Include files
******************************************************************************/
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/* Chip module on-off define */
#define DDL_ON (1U)
#define DDL_OFF (0U)
/**
* @brief This is the list of modules to be used in the Device Driver Library.
* Select the modules you need to use to DDL_ON.
* @note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
* properly.
* @note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
* Library.
* @note DDL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
*/
#define DDL_ICG_ENABLE (DDL_ON)
#define DDL_UTILITY_ENABLE (DDL_ON)
#define DDL_PRINT_ENABLE (DDL_ON)
#define DDL_ADC_ENABLE (DDL_ON)
#define DDL_AES_ENABLE (DDL_ON)
#define DDL_CAN_ENABLE (DDL_ON)
#define DDL_CLK_ENABLE (DDL_ON)
#define DDL_CMP_ENABLE (DDL_ON)
#define DDL_CRC_ENABLE (DDL_ON)
#define DDL_CTC_ENABLE (DDL_ON)
#define DDL_DAC_ENABLE (DDL_ON)
#define DDL_DCU_ENABLE (DDL_ON)
#define DDL_DMA_ENABLE (DDL_ON)
#define DDL_DMC_ENABLE (DDL_ON)
#define DDL_DVP_ENABLE (DDL_ON)
#define DDL_EFM_ENABLE (DDL_ON)
#define DDL_EMB_ENABLE (DDL_ON)
#define DDL_ETH_ENABLE (DDL_ON)
#define DDL_EVENT_PORT_ENABLE (DDL_OFF)
#define DDL_FCM_ENABLE (DDL_ON)
#define DDL_FMAC_ENABLE (DDL_ON)
#define DDL_GPIO_ENABLE (DDL_ON)
#define DDL_HASH_ENABLE (DDL_ON)
#define DDL_HRPWM_ENABLE (DDL_ON)
#define DDL_I2C_ENABLE (DDL_ON)
#define DDL_I2S_ENABLE (DDL_ON)
#define DDL_INTERRUPTS_ENABLE (DDL_ON)
#define DDL_KEYSCAN_ENABLE (DDL_ON)
#define DDL_MAU_ENABLE (DDL_ON)
#define DDL_MPU_ENABLE (DDL_ON)
#define DDL_NFC_ENABLE (DDL_ON)
#define DDL_OTS_ENABLE (DDL_ON)
#define DDL_PWC_ENABLE (DDL_ON)
#define DDL_QSPI_ENABLE (DDL_ON)
#define DDL_RMU_ENABLE (DDL_ON)
#define DDL_RTC_ENABLE (DDL_ON)
#define DDL_SDIOC_ENABLE (DDL_ON)
#define DDL_SMC_ENABLE (DDL_ON)
#define DDL_SPI_ENABLE (DDL_ON)
#define DDL_SRAM_ENABLE (DDL_ON)
#define DDL_SWDT_ENABLE (DDL_ON)
#define DDL_TMR0_ENABLE (DDL_ON)
#define DDL_TMR2_ENABLE (DDL_ON)
#define DDL_TMR4_ENABLE (DDL_ON)
#define DDL_TMR6_ENABLE (DDL_ON)
#define DDL_TMRA_ENABLE (DDL_ON)
#define DDL_TRNG_ENABLE (DDL_ON)
#define DDL_USART_ENABLE (DDL_ON)
#define DDL_USBFS_ENABLE (DDL_OFF)
#define DDL_USBHS_ENABLE (DDL_OFF)
#define DDL_WDT_ENABLE (DDL_ON)
/* BSP on-off define */
#define BSP_ON (1U)
#define BSP_OFF (0U)
/**
* @brief The following is a list of currently supported BSP boards.
*/
#define BSP_EV_HC32F4A0_LQFP176 (1U)
#define BSP_MS_HC32F4A0_LQFP176_050_MEM (2U)
/**
* @brief The macro BSP_EV_HC32F4A0 is used to specify the BSP board currently
* in use.
* The value should be set to one of the list of currently supported BSP boards.
* @note If there is no supported BSP board or the BSP function is not used,
* the value needs to be set to BSP_EV_HC32F4A0.
*/
#define BSP_EV_HC32F4A0 (BSP_EV_HC32F4A0)
/**
* @brief This is the list of BSP components to be used.
* Select the components you need to use to BSP_ON.
*/
#define BSP_CY62167EV30LL_ENABLE (BSP_OFF)
#define BSP_IS42S16400J7TLI_ENABLE (BSP_OFF)
#define BSP_IS62WV51216_ENABLE (BSP_OFF)
#define BSP_MT29F2G08AB_ENABLE (BSP_OFF)
#define BSP_NT35510_ENABLE (BSP_OFF)
#define BSP_OV5640_ENABLE (BSP_OFF)
#define BSP_S29GL064N90TFI03_ENABLE (BSP_OFF)
#define BSP_TCA9539_ENABLE (BSP_OFF)
#define BSP_W25QXX_ENABLE (BSP_OFF)
#define BSP_WM8731_ENABLE (BSP_OFF)
/**
* @brief Ethernet and PHY Configuration.
* @note PHY delay these values are based on a 1 ms Systick interrupt.
*/
/* MAC ADDRESS */
#define ETH_MAC_ADDR0 (2U)
#define ETH_MAC_ADDR1 (0U)
#define ETH_MAC_ADDR2 (0U)
#define ETH_MAC_ADDR3 (0U)
#define ETH_MAC_ADDR4 (0U)
#define ETH_MAC_ADDR5 (0U)
/* Ethernet driver buffers size and count */
#define ETH_TXBUF_SIZE (ETH_PACKET_MAX_SIZE) /* Buffer size for receive */
#define ETH_RXBUF_SIZE (ETH_PACKET_MAX_SIZE) /* Buffer size for transmit */
#define ETH_TXBUF_NUMBER (4UL) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_RXBUF_NUMBER (4UL) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* PHY Address*/
#define PHY_ADDRESS (0x00U) /* RTL8201F */
/* PHY Configuration delay */
#define PHY_HW_RESET_DELAY (0x0000003FUL)
#define PHY_RESET_DELAY (0x0000007FUL)
#define PHY_CONFIG_DELAY (0x0000003FUL)
#define PHY_READ_TIMEOUT (0x00000005UL)
#define PHY_WRITE_TIMEOUT (0x00000005UL)
/* Common PHY Registers */
#define PHY_BCR (0x00U) /*!< Basic Control Register */
#define PHY_BSR (0x01U) /*!< Basic Status Register */
#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */
#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M (0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M (0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M (0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M (0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */
#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */
#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */
#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */
#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */
#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */
#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */
#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */
/**
* @brief External clock source for I2S peripheral
*/
#ifndef I2S_EXT_CLK_FREQ
#define I2S_EXT_CLK_FREQ (12288000UL) /*!< Value of the external oscillator */
#endif /* I2S_EXT_CLK_FREQ */
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __DDL_CONFIG_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_common.h
* @brief This file contains the common part of the HC32 series.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
2020-09-07 Yangjp Add the precompiled configuration of ARM compiler V6
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_COMMON_H__
#define __HC32_COMMON_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include <stddef.h>
#include <string.h>
/**
* @addtogroup CMSIS
* @{
*/
/**
* @addtogroup HC32_Common_Part
* @{
*/
/**
* @brief HC32 Common Device Include
*/
#if defined(HC32F120)
#include "hc32f120.h"
#include "system_hc32f120.h"
#elif defined(HC32F4A0)
#include "hc32f4a0.h"
#include "system_hc32f4a0.h"
#elif defined(HC32M120)
#include "hc32m120.h"
#include "system_hc32m120.h"
#elif defined(HC32M423)
#include "hc32m423.h"
#include "system_hc32m423.h"
#else
#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)"
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup HC32_Common_Global_Types HC32 Common Global Types
* @{
*/
/**
* @brief Single precision floating point number (4 byte)
*/
typedef float float32_t;
/**
* @brief Double precision floating point number (8 byte)
*/
typedef double float64_t;
/**
* @brief Function pointer type to void/void function
*/
typedef void (*func_ptr_t)(void);
/**
* @brief Function pointer type to void/uint8_t function
*/
typedef void (*func_ptr_arg1_t)(uint8_t);
/**
* @brief Functional state
*/
typedef enum
{
Disable = 0U,
Enable = 1U,
} en_functional_state_t;
/* Check if it is a functional state */
#define IS_FUNCTIONAL_STATE(state) (((state) == Disable) || ((state) == Enable))
/**
* @brief Flag status
*/
typedef enum
{
Reset = 0U,
Set = 1U,
} en_flag_status_t, en_int_status_t;
/**
* @brief Generic error codes
*/
typedef enum
{
Ok = 0U, /*!< No error */
Error = 1U, /*!< Non-specific error code */
ErrorAddressAlignment = 2U, /*!< Address alignment does not match */
ErrorAccessRights = 3U, /*!< Wrong mode (e.g. user/system) mode is set */
ErrorInvalidParameter = 4U, /*!< Provided parameter is not valid */
ErrorOperationInProgress = 5U, /*!< A conflicting or requested operation is still in progress */
ErrorInvalidMode = 6U, /*!< Operation not allowed in current mode */
ErrorUninitialized = 7U, /*!< Module (or part of it) was not initialized properly */
ErrorBufferEmpty = 8U, /*!< Circular buffer can not be read because the buffer is empty */
ErrorBufferFull = 9U, /*!< Circular buffer can not be written because the buffer is full */
ErrorTimeout = 10U, /*!< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) */
ErrorNotReady = 11U, /*!< A requested final state is not reached */
OperationInProgress = 12U, /*!< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.) */
} en_result_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup HC32_Common_Global_Macros HC32 Common Global Macros
* @{
*/
/**
* @brief Compiler Macro Definitions
*/
#ifndef __UNUSED
#define __UNUSED __attribute__((unused))
#endif /* __UNUSED */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#ifndef __WEAKDEF
#define __WEAKDEF __attribute__((weak))
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN __attribute__((aligned(4)))
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE __attribute__((noinline))
#endif /* __NOINLINE */
#ifndef __RAM_FUNC
#define __RAM_FUNC __attribute__((long_call, section(".ramfunc")))
/* Usage: void __RAM_FUNC foo(void) */
#endif /* __RAM_FUNC */
#ifndef __NO_INIT
#define __NO_INIT
#endif /* __NO_INIT */
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */
#ifndef __WEAKDEF
#define __WEAKDEF __attribute__((weak))
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN __attribute__((aligned (4)))
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE __attribute__((noinline))
#endif /* __NOINLINE */
#ifndef __RAM_FUNC
#define __RAM_FUNC __attribute__((long_call, section(".ramfunc")))
/* Usage: void __RAM_FUNC foo(void) */
#endif /* __RAM_FUNC */
#ifndef __NO_INIT
#define __NO_INIT __attribute__((section(".noinit")))
#endif /* __NO_INIT */
#elif defined (__ICCARM__) /*!< IAR Compiler */
#ifndef __WEAKDEF
#define __WEAKDEF __weak
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN _Pragma("data_alignment=4")
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE _Pragma("optimize = no_inline")
#endif /* __NOINLINE */
#ifndef __RAM_FUNC
#define __RAM_FUNC __ramfunc
#endif /* __RAM_FUNC */
#ifndef __NO_INIT
#define __NO_INIT __no_init
#endif /* __NO_INIT */
#elif defined (__CC_ARM) /*!< ARM Compiler */
#ifndef __WEAKDEF
#define __WEAKDEF __attribute__((weak))
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN __align(4)
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE __attribute__((noinline))
#endif /* __NOINLINE */
#ifndef __NO_INIT
#define __NO_INIT
#endif /* __NO_INIT */
/* RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM. */
#define __RAM_FUNC
#else
#error "unsupported compiler!!"
#endif
/**
* @defgroup Extend_Macro_Definitions Extend Macro Definitions
* @{
*/
/* Decimal to BCD */
#define DEC2BCD(x) ((((x) / 10U) << 4U) + ((x) % 10U))
/* BCD to decimal */
#define BCD2DEC(x) ((((x) >> 4U) * 10U) + ((x) & 0x0FU))
/* Returns the dimension of an array */
#define ARRAY_SZ(x) ((sizeof(x)) / (sizeof((x)[0])))
/**
* @}
*/
/**
* @defgroup Address_Align Address Align
* @{
*/
#define IS_ADDRESS_ALIGN(addr, align) (0UL == (((uint32_t)(addr)) & (((uint32_t)(align)) - 1UL)))
#define IS_ADDRESS_ALIGN_HALFWORD(addr) (0UL == (((uint32_t)(addr)) & 0x1UL))
#define IS_ADDRESS_ALIGN_WORD(addr) (0UL == (((uint32_t)(addr)) & 0x3UL))
/**
* @}
*/
/**
* @defgroup Register_Macro_Definitions Register Macro Definitions
* @{
*/
#define RW_MEM8(addr) (*(volatile uint8_t *)(addr))
#define RW_MEM16(addr) (*(volatile uint16_t *)(addr))
#define RW_MEM32(addr) (*(volatile uint32_t *)(addr))
#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT)))
#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT)))
#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT)))
#define CLEAR_REG8_BIT(REG, BIT) ((REG) &= ((uint8_t)(~((uint8_t)(BIT)))))
#define CLEAR_REG16_BIT(REG, BIT) ((REG) &= ((uint16_t)(~((uint16_t)(BIT)))))
#define CLEAR_REG32_BIT(REG, BIT) ((REG) &= ((uint32_t)(~((uint32_t)(BIT)))))
#define READ_REG8_BIT(REG, BIT) ((REG) & ((uint8_t)(BIT)))
#define READ_REG16_BIT(REG, BIT) ((REG) & ((uint16_t)(BIT)))
#define READ_REG32_BIT(REG, BIT) ((REG) & ((uint32_t)(BIT)))
#define CLEAR_REG8(REG) ((REG) = ((uint8_t)(0U)))
#define CLEAR_REG16(REG) ((REG) = ((uint16_t)(0U)))
#define CLEAR_REG32(REG) ((REG) = ((uint32_t)(0UL)))
#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL)))
#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL)))
#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL)))
#define READ_REG8(REG) (REG)
#define READ_REG16(REG) (REG)
#define READ_REG32(REG) (REG)
#define MODIFY_REG8(REGS, CLEARMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLEARMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLEARMASK)))))
#define MODIFY_REG16(REGS, CLEARMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLEARMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLEARMASK)))))
#define MODIFY_REG32(REGS, CLEARMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLEARMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLEARMASK)))))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_COMMON_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ddl.h
* @brief This file contains HC32 Series Device Driver Library file call
* management.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_DDL_H__
#define __HC32_DDL_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/* Defined use Device Driver Library */
#if !defined (USE_DDL_DRIVER)
/**
* @brief Comment the line below if you will not use the Device Driver Library.
* In this case, the application code will be based on direct access to
* peripherals registers.
*/
/* #define USE_DDL_DRIVER */
#endif /* USE_DDL_DRIVER */
/**
* @brief HC32 Series Device Driver Library version number
*/
#define HC32_DDL_VERSION_MAIN 0x01U /*!< [31:24] main version */
#define HC32_DDL_VERSION_SUB1 0x00U /*!< [23:16] sub1 version */
#define HC32_DDL_VERSION_SUB2 0x04U /*!< [15:8] sub2 version */
#define HC32_DDL_VERSION_RC 0x00U /*!< [7:0] release candidate */
#define HC32_DDL_VERSION ((HC32_DDL_VERSION_MAIN << 24) | \
(HC32_DDL_VERSION_SUB1 << 16) | \
(HC32_DDL_VERSION_SUB2 << 8 ) | \
(HC32_DDL_VERSION_RC))
/* Use Device Driver Library */
#if defined (USE_DDL_DRIVER)
/**
* @brief Include peripheral module's header file
*/
#if (DDL_ADC_ENABLE == DDL_ON)
#include "hc32f4a0_adc.h"
#endif /* DDL_ADC_ENABLE */
#if (DDL_AES_ENABLE == DDL_ON)
#include "hc32f4a0_aes.h"
#endif /* DDL_AES_ENABLE */
#if (DDL_CAN_ENABLE == DDL_ON)
#include "hc32f4a0_can.h"
#endif /* DDL_CAN_ENABLE */
#if (DDL_CLK_ENABLE == DDL_ON)
#include "hc32f4a0_clk.h"
#endif /* DDL_CLK_ENABLE */
#if (DDL_CMP_ENABLE == DDL_ON)
#include "hc32f4a0_cmp.h"
#endif /* DDL_CMP_ENABLE */
#if (DDL_CRC_ENABLE == DDL_ON)
#include "hc32f4a0_crc.h"
#endif /* DDL_CRC_ENABLE */
#if (DDL_CTC_ENABLE == DDL_ON)
#include "hc32f4a0_ctc.h"
#endif /* DDL_CTC_ENABLE */
#if (DDL_DAC_ENABLE == DDL_ON)
#include "hc32f4a0_dac.h"
#endif /* DDL_DAC_ENABLE */
#if (DDL_DCU_ENABLE == DDL_ON)
#include "hc32f4a0_dcu.h"
#endif /* DDL_DCU_ENABLE */
#if (DDL_DMA_ENABLE == DDL_ON)
#include "hc32f4a0_dma.h"
#endif /* DDL_DMA_ENABLE */
#if (DDL_DMC_ENABLE == DDL_ON)
#include "hc32f4a0_dmc.h"
#endif /* DDL_DMC_ENABLE */
#if (DDL_DVP_ENABLE == DDL_ON)
#include "hc32f4a0_dvp.h"
#endif /* DDL_DVP_ENABLE */
#if (DDL_EFM_ENABLE == DDL_ON)
#include "hc32f4a0_efm.h"
#endif /* DDL_EFM_ENABLE */
#if (DDL_EMB_ENABLE == DDL_ON)
#include "hc32f4a0_emb.h"
#endif /* DDL_EMB_ENABLE */
#if (DDL_ETH_ENABLE == DDL_ON)
#include "hc32f4a0_eth.h"
#endif /* DDL_ETH_ENABLE */
#if (DDL_EVENT_PORT_ENABLE == DDL_ON)
#include "hc32f4a0_event_port.h"
#endif /* DDL_EVENT_PORT_ENABLE */
#if (DDL_FCM_ENABLE == DDL_ON)
#include "hc32f4a0_fcm.h"
#endif /* DDL_FCM_ENABLE */
#if (DDL_FMAC_ENABLE == DDL_ON)
#include "hc32f4a0_fmac.h"
#endif /* DDL_FMAC_ENABLE */
#if (DDL_GPIO_ENABLE == DDL_ON)
#include "hc32f4a0_gpio.h"
#endif /* DDL_GPIO_ENABLE */
#if (DDL_HASH_ENABLE == DDL_ON)
#include "hc32f4a0_hash.h"
#endif /* DDL_HASH_ENABLE */
#if (DDL_I2C_ENABLE == DDL_ON)
#include "hc32f4a0_i2c.h"
#endif /* DDL_I2C_ENABLE */
#if (DDL_I2S_ENABLE == DDL_ON)
#include "hc32f4a0_i2s.h"
#endif /* DDL_I2S_ENABLE */
#if (DDL_ICG_ENABLE == DDL_ON)
#include "hc32f4a0_icg.h"
#endif /* DDL_ICG_ENABLE */
#if (DDL_INTERRUPTS_ENABLE == DDL_ON)
#include "hc32f4a0_interrupts.h"
#endif /* DDL_INTERRUPTS_ENABLE */
#if (DDL_KEYSCAN_ENABLE == DDL_ON)
#include "hc32f4a0_keyscan.h"
#endif /* DDL_KEYSCAN_ENABLE */
#if (DDL_MAU_ENABLE == DDL_ON)
#include "hc32f4a0_mau.h"
#endif /* DDL_MAU_ENABLE */
#if (DDL_MPU_ENABLE == DDL_ON)
#include "hc32f4a0_mpu.h"
#endif /* DDL_MPU_ENABLE */
#if (DDL_NFC_ENABLE == DDL_ON)
#include "hc32f4a0_nfc.h"
#endif /* DDL_NFC_ENABLE */
#if (DDL_OTS_ENABLE == DDL_ON)
#include "hc32f4a0_ots.h"
#endif /* DDL_OTS_ENABLE */
#if (DDL_PWC_ENABLE == DDL_ON)
#include "hc32f4a0_pwc.h"
#endif /* DDL_PWC_ENABLE */
#if (DDL_QSPI_ENABLE == DDL_ON)
#include "hc32f4a0_qspi.h"
#endif /* DDL_QSPI_ENABLE */
#if (DDL_RMU_ENABLE == DDL_ON)
#include "hc32f4a0_rmu.h"
#endif /* DDL_RMU_ENABLE */
#if (DDL_RTC_ENABLE == DDL_ON)
#include "hc32f4a0_rtc.h"
#endif /* DDL_RTC_ENABLE */
#if (DDL_SDIOC_ENABLE == DDL_ON)
#include "hc32f4a0_sdioc.h"
#endif /* DDL_SDIOC_ENABLE */
#if (DDL_SMC_ENABLE == DDL_ON)
#include "hc32f4a0_smc.h"
#endif /* DDL_SMC_ENABLE */
#if (DDL_SPI_ENABLE == DDL_ON)
#include "hc32f4a0_spi.h"
#endif /* DDL_SPI_ENABLE */
#if (DDL_SRAM_ENABLE == DDL_ON)
#include "hc32f4a0_sram.h"
#endif /* DDL_SRAM_ENABLE */
#if (DDL_SWDT_ENABLE == DDL_ON)
#include "hc32f4a0_swdt.h"
#endif /* DDL_SWDT_ENABLE */
#if (DDL_TMR0_ENABLE == DDL_ON)
#include "hc32f4a0_tmr0.h"
#endif /* DDL_TMR0_ENABLE */
#if (DDL_TMR2_ENABLE == DDL_ON)
#include "hc32f4a0_tmr2.h"
#endif /* DDL_TMR2_ENABLE */
#if (DDL_TMR4_ENABLE == DDL_ON)
#include "hc32f4a0_tmr4.h"
#endif /* DDL_TMR4_ENABLE */
#if (DDL_TMR6_ENABLE == DDL_ON)
#include "hc32f4a0_tmr6.h"
#endif /* DDL_TMR6_ENABLE */
#if (DDL_TMRA_ENABLE == DDL_ON)
#include "hc32f4a0_tmra.h"
#endif /* DDL_TMRA_ENABLE */
#if (DDL_TRNG_ENABLE == DDL_ON)
#include "hc32f4a0_trng.h"
#endif /* DDL_TRNG_ENABLE */
#if (DDL_USART_ENABLE == DDL_ON)
#include "hc32f4a0_usart.h"
#endif /* DDL_USART_ENABLE */
#if (DDL_USBFS_ENABLE == DDL_ON)
#include "hc32f4a0_usbfs.h"
#endif /* DDL_USBFS_ENABLE */
#if (DDL_USBHS_ENABLE == DDL_ON)
#include "hc32f4a0_usbhs.h"
#endif /* DDL_USBHS_ENABLE */
#if (DDL_UTILITY_ENABLE == DDL_ON)
#include "hc32f4a0_utility.h"
#endif /* DDL_UTILITY_ENABLE */
#if (DDL_WDT_ENABLE == DDL_ON)
#include "hc32f4a0_wdt.h"
#endif /* DDL_WDT_ENABLE */
#if (DDL_HRPWM_ENABLE == DDL_ON)
#include "hc32f4a0_hrpwm.h"
#endif /* DDL_HRPWM_ENABLE */
/**
* @brief Include BSP board's header file
*/
#if (BSP_EV_HC32F4A0_LQFP176 == BSP_EV_HC32F4A0)
#include "ev_hc32f4a0_lqfp176.h"
#endif /* BSP_EV_HC32F4A0_LQFP176 */
#if (BSP_MS_HC32F4A0_LQFP176_050_MEM == BSP_EV_HC32F4A0)
#include "ms_hc32f4a0_lqfp176_050_mem.h"
#endif /* BSP_MS_HC32F4A0_LQFP176_050_MEM */
/**
* @brief Include BSP device component's header file
*/
#if (BSP_CY62167EV30LL_ENABLE == BSP_ON)
#include "cy62167ev30ll.h"
#endif /* BSP_CY62167EV30LL_ENABLE */
#if (BSP_IS42S16400J7TLI_ENABLE == BSP_ON)
#include "is42s16400j7tli.h"
#endif /* BSP_IS42S16400J7TLI_ENABLE */
#if (BSP_IS62WV51216_ENABLE == BSP_ON)
#include "is62wv51216.h"
#endif /* BSP_IS62WV51216_ENABLE */
#if (BSP_MT29F2G08AB_ENABLE == BSP_ON)
#include "mt29f2g08ab.h"
#endif /* BSP_MT29F2G08AB_ENABLE */
#if (BSP_NT35510_ENABLE == BSP_ON)
#include "nt35510.h"
#endif /* BSP_NT35510_ENABLE */
#if (BSP_OV5640_ENABLE == BSP_ON)
#include "ov5640.h"
#endif /* BSP_OV5640_ENABLE */
#if (BSP_S29GL064N90TFI03_ENABLE == BSP_ON)
#include "s29gl064n90tfi03.h"
#endif /* BSP_S29GL064N90TFI03_ENABLE */
#if (BSP_TCA9539_ENABLE == BSP_ON)
#include "ev_hc32f4a0_lqfp176_tca9539.h"
#include "tca9539.h"
#endif /* BSP_TCA9539_ENABLE */
#if (BSP_W25QXX_ENABLE == BSP_ON)
#include "w25qxx.h"
#endif /* BSP_W25QXX_ENABLE */
#if (BSP_WM8731_ENABLE == BSP_ON)
#include "wm8731.h"
#endif /* BSP_WM8731_ENABLE */
#endif /* USE_DDL_DRIVER */
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_DDL_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file system_hc32f4a0.h
* @brief This file contains all the functions prototypes of the HC32 System.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Zhangxl First version
2020-07-03 Zhangxl Modify for 16MHz & 20MHz HRC
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __SYSTEM_HC32F4A0_H__
#define __SYSTEM_HC32F4A0_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include <stdint.h>
/**
* @addtogroup CMSIS
* @{
*/
/**
* @addtogroup HC32F4A0_System
* @{
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('define')
******************************************************************************/
/**
* @addtogroup HC32F4A0_System_Global_Macros
* @{
*/
/**
* @brief Clock setup macro definition
*/
#define CLOCK_SETTING_NONE 0U /*!< User provides own clock setting in application */
#define CLOCK_SETTING_CMSIS 1U
#define HRC_FREQ_MON() (*((volatile unsigned int*)(0x40010684UL)))
/**
* @addtogroup HC32F4A0_System_Clock_Source
* @{
*/
#if !defined (HRC_16MHz_VALUE)
#define HRC_16MHz_VALUE ((uint32_t)16000000UL) /*!< Internal high speed RC freq.(16MHz) */
#endif
#if !defined (HRC_20MHz_VALUE)
#define HRC_20MHz_VALUE ((uint32_t)20000000UL) /*!< Internal high speed RC freq.(20MHz) */
#endif
#if !defined (MRC_VALUE)
#define MRC_VALUE ((uint32_t)8000000UL) /*!< Internal middle speed RC freq.(8MHz) */
#endif
#if !defined (LRC_VALUE)
#define LRC_VALUE ((uint32_t)32768UL) /*!< Internal low speed RC freq.(32.768KHz) */
#endif
#if !defined (RTCLRC_VALUE)
#define RTCLRC_VALUE ((uint32_t)32768UL) /*!< Internal RTC low speed RC freq.(32.768KHz) */
#endif
#if !defined (SWDTLRC_VALUE)
#define SWDTLRC_VALUE ((uint32_t)10000UL) /*!< External low speed OSC freq.(10KHz) */
#endif
#if !defined (XTAL_VALUE)
#define XTAL_VALUE ((uint32_t)8000000UL) /*!< External high speed OSC freq.(8MHz) */
#endif
#if !defined (XTAL32_VALUE)
#define XTAL32_VALUE ((uint32_t)32768UL) /*!< External low speed OSC freq.(32.768KHz) */
#endif
#if !defined (HCLK_VALUE)
#define HCLK_VALUE (SystemCoreClock >> ((M4_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS))
#endif
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/**
* @addtogroup HC32F4A0_System_Exported_Variable
* @{
*/
extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */
extern uint32_t HRC_VALUE; /*!< HRC frequency */
/**
* @}
*/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup HC32F4A0_System_Global_Functions
* @{
*/
extern void SystemInit(void); /*!< Initialize the system */
extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_HC32F4A0_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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;/******************************************************************************
;* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved.
;*
;* This software is owned and published by:
;* Huada Semiconductor Co.,Ltd ("HDSC").
;*
;* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
;* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
;*
;* This software contains source code for use with HDSC
;* components. This software is licensed by HDSC to be adapted only
;* for use in systems utilizing HDSC components. HDSC shall not be
;* responsible for misuse or illegal use of this software for devices not
;* supported herein. HDSC is providing this software "AS IS" and will
;* not be responsible for issues arising from incorrect user implementation
;* of the software.
;*
;* Disclaimer:
;* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
;* REGARDING THE SOFTWARE (INCLUDING ANY ACCOMPANYING WRITTEN MATERIALS),
;* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
;* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
;* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
;* WARRANTY OF NONINFRINGEMENT.
;* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
;* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
;* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
;* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
;* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
;* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
;* SAVINGS OR PROFITS,
;* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
;* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
;* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
;* FROM, THE SOFTWARE.
;*
;* This software may be replicated in part or whole for the licensed use,
;* with the restriction that this Disclaimer and Copyright notice must be
;* included with each copy of this software, whether used in part or whole,
;* at all times.
;*/
;/*****************************************************************************/
;/*****************************************************************************/
;/* Startup for ARM */
;/* Version V1.0 */
;/* Date 2020-06-12 */
;/* Target-mcu HC32F4A0 */
;/*****************************************************************************/
; Stack Configuration
; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
Stack_Size EQU 0x00002000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; Heap Configuration
; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
Heap_Size EQU 0x00002000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD IRQ000_Handler
DCD IRQ001_Handler
DCD IRQ002_Handler
DCD IRQ003_Handler
DCD IRQ004_Handler
DCD IRQ005_Handler
DCD IRQ006_Handler
DCD IRQ007_Handler
DCD IRQ008_Handler
DCD IRQ009_Handler
DCD IRQ010_Handler
DCD IRQ011_Handler
DCD IRQ012_Handler
DCD IRQ013_Handler
DCD IRQ014_Handler
DCD IRQ015_Handler
DCD IRQ016_Handler
DCD IRQ017_Handler
DCD IRQ018_Handler
DCD IRQ019_Handler
DCD IRQ020_Handler
DCD IRQ021_Handler
DCD IRQ022_Handler
DCD IRQ023_Handler
DCD IRQ024_Handler
DCD IRQ025_Handler
DCD IRQ026_Handler
DCD IRQ027_Handler
DCD IRQ028_Handler
DCD IRQ029_Handler
DCD IRQ030_Handler
DCD IRQ031_Handler
DCD IRQ032_Handler
DCD IRQ033_Handler
DCD IRQ034_Handler
DCD IRQ035_Handler
DCD IRQ036_Handler
DCD IRQ037_Handler
DCD IRQ038_Handler
DCD IRQ039_Handler
DCD IRQ040_Handler
DCD IRQ041_Handler
DCD IRQ042_Handler
DCD IRQ043_Handler
DCD IRQ044_Handler
DCD IRQ045_Handler
DCD IRQ046_Handler
DCD IRQ047_Handler
DCD IRQ048_Handler
DCD IRQ049_Handler
DCD IRQ050_Handler
DCD IRQ051_Handler
DCD IRQ052_Handler
DCD IRQ053_Handler
DCD IRQ054_Handler
DCD IRQ055_Handler
DCD IRQ056_Handler
DCD IRQ057_Handler
DCD IRQ058_Handler
DCD IRQ059_Handler
DCD IRQ060_Handler
DCD IRQ061_Handler
DCD IRQ062_Handler
DCD IRQ063_Handler
DCD IRQ064_Handler
DCD IRQ065_Handler
DCD IRQ066_Handler
DCD IRQ067_Handler
DCD IRQ068_Handler
DCD IRQ069_Handler
DCD IRQ070_Handler
DCD IRQ071_Handler
DCD IRQ072_Handler
DCD IRQ073_Handler
DCD IRQ074_Handler
DCD IRQ075_Handler
DCD IRQ076_Handler
DCD IRQ077_Handler
DCD IRQ078_Handler
DCD IRQ079_Handler
DCD IRQ080_Handler
DCD IRQ081_Handler
DCD IRQ082_Handler
DCD IRQ083_Handler
DCD IRQ084_Handler
DCD IRQ085_Handler
DCD IRQ086_Handler
DCD IRQ087_Handler
DCD IRQ088_Handler
DCD IRQ089_Handler
DCD IRQ090_Handler
DCD IRQ091_Handler
DCD IRQ092_Handler
DCD IRQ093_Handler
DCD IRQ094_Handler
DCD IRQ095_Handler
DCD IRQ096_Handler
DCD IRQ097_Handler
DCD IRQ098_Handler
DCD IRQ099_Handler
DCD IRQ100_Handler
DCD IRQ101_Handler
DCD IRQ102_Handler
DCD IRQ103_Handler
DCD IRQ104_Handler
DCD IRQ105_Handler
DCD IRQ106_Handler
DCD IRQ107_Handler
DCD IRQ108_Handler
DCD IRQ109_Handler
DCD IRQ110_Handler
DCD IRQ111_Handler
DCD IRQ112_Handler
DCD IRQ113_Handler
DCD IRQ114_Handler
DCD IRQ115_Handler
DCD IRQ116_Handler
DCD IRQ117_Handler
DCD IRQ118_Handler
DCD IRQ119_Handler
DCD IRQ120_Handler
DCD IRQ121_Handler
DCD IRQ122_Handler
DCD IRQ123_Handler
DCD IRQ124_Handler
DCD IRQ125_Handler
DCD IRQ126_Handler
DCD IRQ127_Handler
DCD IRQ128_Handler
DCD IRQ129_Handler
DCD IRQ130_Handler
DCD IRQ131_Handler
DCD IRQ132_Handler
DCD IRQ133_Handler
DCD IRQ134_Handler
DCD IRQ135_Handler
DCD IRQ136_Handler
DCD IRQ137_Handler
DCD IRQ138_Handler
DCD IRQ139_Handler
DCD IRQ140_Handler
DCD IRQ141_Handler
DCD IRQ142_Handler
DCD IRQ143_Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT IRQ000_Handler [WEAK]
EXPORT IRQ001_Handler [WEAK]
EXPORT IRQ002_Handler [WEAK]
EXPORT IRQ003_Handler [WEAK]
EXPORT IRQ004_Handler [WEAK]
EXPORT IRQ005_Handler [WEAK]
EXPORT IRQ006_Handler [WEAK]
EXPORT IRQ007_Handler [WEAK]
EXPORT IRQ008_Handler [WEAK]
EXPORT IRQ009_Handler [WEAK]
EXPORT IRQ010_Handler [WEAK]
EXPORT IRQ011_Handler [WEAK]
EXPORT IRQ012_Handler [WEAK]
EXPORT IRQ013_Handler [WEAK]
EXPORT IRQ014_Handler [WEAK]
EXPORT IRQ015_Handler [WEAK]
EXPORT IRQ016_Handler [WEAK]
EXPORT IRQ017_Handler [WEAK]
EXPORT IRQ018_Handler [WEAK]
EXPORT IRQ019_Handler [WEAK]
EXPORT IRQ020_Handler [WEAK]
EXPORT IRQ021_Handler [WEAK]
EXPORT IRQ022_Handler [WEAK]
EXPORT IRQ023_Handler [WEAK]
EXPORT IRQ024_Handler [WEAK]
EXPORT IRQ025_Handler [WEAK]
EXPORT IRQ026_Handler [WEAK]
EXPORT IRQ027_Handler [WEAK]
EXPORT IRQ028_Handler [WEAK]
EXPORT IRQ029_Handler [WEAK]
EXPORT IRQ030_Handler [WEAK]
EXPORT IRQ031_Handler [WEAK]
EXPORT IRQ032_Handler [WEAK]
EXPORT IRQ033_Handler [WEAK]
EXPORT IRQ034_Handler [WEAK]
EXPORT IRQ035_Handler [WEAK]
EXPORT IRQ036_Handler [WEAK]
EXPORT IRQ037_Handler [WEAK]
EXPORT IRQ038_Handler [WEAK]
EXPORT IRQ039_Handler [WEAK]
EXPORT IRQ040_Handler [WEAK]
EXPORT IRQ041_Handler [WEAK]
EXPORT IRQ042_Handler [WEAK]
EXPORT IRQ043_Handler [WEAK]
EXPORT IRQ044_Handler [WEAK]
EXPORT IRQ045_Handler [WEAK]
EXPORT IRQ046_Handler [WEAK]
EXPORT IRQ047_Handler [WEAK]
EXPORT IRQ048_Handler [WEAK]
EXPORT IRQ049_Handler [WEAK]
EXPORT IRQ050_Handler [WEAK]
EXPORT IRQ051_Handler [WEAK]
EXPORT IRQ052_Handler [WEAK]
EXPORT IRQ053_Handler [WEAK]
EXPORT IRQ054_Handler [WEAK]
EXPORT IRQ055_Handler [WEAK]
EXPORT IRQ056_Handler [WEAK]
EXPORT IRQ057_Handler [WEAK]
EXPORT IRQ058_Handler [WEAK]
EXPORT IRQ059_Handler [WEAK]
EXPORT IRQ060_Handler [WEAK]
EXPORT IRQ061_Handler [WEAK]
EXPORT IRQ062_Handler [WEAK]
EXPORT IRQ063_Handler [WEAK]
EXPORT IRQ064_Handler [WEAK]
EXPORT IRQ065_Handler [WEAK]
EXPORT IRQ066_Handler [WEAK]
EXPORT IRQ067_Handler [WEAK]
EXPORT IRQ068_Handler [WEAK]
EXPORT IRQ069_Handler [WEAK]
EXPORT IRQ070_Handler [WEAK]
EXPORT IRQ071_Handler [WEAK]
EXPORT IRQ072_Handler [WEAK]
EXPORT IRQ073_Handler [WEAK]
EXPORT IRQ074_Handler [WEAK]
EXPORT IRQ075_Handler [WEAK]
EXPORT IRQ076_Handler [WEAK]
EXPORT IRQ077_Handler [WEAK]
EXPORT IRQ078_Handler [WEAK]
EXPORT IRQ079_Handler [WEAK]
EXPORT IRQ080_Handler [WEAK]
EXPORT IRQ081_Handler [WEAK]
EXPORT IRQ082_Handler [WEAK]
EXPORT IRQ083_Handler [WEAK]
EXPORT IRQ084_Handler [WEAK]
EXPORT IRQ085_Handler [WEAK]
EXPORT IRQ086_Handler [WEAK]
EXPORT IRQ087_Handler [WEAK]
EXPORT IRQ088_Handler [WEAK]
EXPORT IRQ089_Handler [WEAK]
EXPORT IRQ090_Handler [WEAK]
EXPORT IRQ091_Handler [WEAK]
EXPORT IRQ092_Handler [WEAK]
EXPORT IRQ093_Handler [WEAK]
EXPORT IRQ094_Handler [WEAK]
EXPORT IRQ095_Handler [WEAK]
EXPORT IRQ096_Handler [WEAK]
EXPORT IRQ097_Handler [WEAK]
EXPORT IRQ098_Handler [WEAK]
EXPORT IRQ099_Handler [WEAK]
EXPORT IRQ100_Handler [WEAK]
EXPORT IRQ101_Handler [WEAK]
EXPORT IRQ102_Handler [WEAK]
EXPORT IRQ103_Handler [WEAK]
EXPORT IRQ104_Handler [WEAK]
EXPORT IRQ105_Handler [WEAK]
EXPORT IRQ106_Handler [WEAK]
EXPORT IRQ107_Handler [WEAK]
EXPORT IRQ108_Handler [WEAK]
EXPORT IRQ109_Handler [WEAK]
EXPORT IRQ110_Handler [WEAK]
EXPORT IRQ111_Handler [WEAK]
EXPORT IRQ112_Handler [WEAK]
EXPORT IRQ113_Handler [WEAK]
EXPORT IRQ114_Handler [WEAK]
EXPORT IRQ115_Handler [WEAK]
EXPORT IRQ116_Handler [WEAK]
EXPORT IRQ117_Handler [WEAK]
EXPORT IRQ118_Handler [WEAK]
EXPORT IRQ119_Handler [WEAK]
EXPORT IRQ120_Handler [WEAK]
EXPORT IRQ121_Handler [WEAK]
EXPORT IRQ122_Handler [WEAK]
EXPORT IRQ123_Handler [WEAK]
EXPORT IRQ124_Handler [WEAK]
EXPORT IRQ125_Handler [WEAK]
EXPORT IRQ126_Handler [WEAK]
EXPORT IRQ127_Handler [WEAK]
EXPORT IRQ128_Handler [WEAK]
EXPORT IRQ129_Handler [WEAK]
EXPORT IRQ130_Handler [WEAK]
EXPORT IRQ131_Handler [WEAK]
EXPORT IRQ132_Handler [WEAK]
EXPORT IRQ133_Handler [WEAK]
EXPORT IRQ134_Handler [WEAK]
EXPORT IRQ135_Handler [WEAK]
EXPORT IRQ136_Handler [WEAK]
EXPORT IRQ137_Handler [WEAK]
EXPORT IRQ138_Handler [WEAK]
EXPORT IRQ139_Handler [WEAK]
EXPORT IRQ140_Handler [WEAK]
EXPORT IRQ141_Handler [WEAK]
EXPORT IRQ142_Handler [WEAK]
EXPORT IRQ143_Handler [WEAK]
IRQ000_Handler
IRQ001_Handler
IRQ002_Handler
IRQ003_Handler
IRQ004_Handler
IRQ005_Handler
IRQ006_Handler
IRQ007_Handler
IRQ008_Handler
IRQ009_Handler
IRQ010_Handler
IRQ011_Handler
IRQ012_Handler
IRQ013_Handler
IRQ014_Handler
IRQ015_Handler
IRQ016_Handler
IRQ017_Handler
IRQ018_Handler
IRQ019_Handler
IRQ020_Handler
IRQ021_Handler
IRQ022_Handler
IRQ023_Handler
IRQ024_Handler
IRQ025_Handler
IRQ026_Handler
IRQ027_Handler
IRQ028_Handler
IRQ029_Handler
IRQ030_Handler
IRQ031_Handler
IRQ032_Handler
IRQ033_Handler
IRQ034_Handler
IRQ035_Handler
IRQ036_Handler
IRQ037_Handler
IRQ038_Handler
IRQ039_Handler
IRQ040_Handler
IRQ041_Handler
IRQ042_Handler
IRQ043_Handler
IRQ044_Handler
IRQ045_Handler
IRQ046_Handler
IRQ047_Handler
IRQ048_Handler
IRQ049_Handler
IRQ050_Handler
IRQ051_Handler
IRQ052_Handler
IRQ053_Handler
IRQ054_Handler
IRQ055_Handler
IRQ056_Handler
IRQ057_Handler
IRQ058_Handler
IRQ059_Handler
IRQ060_Handler
IRQ061_Handler
IRQ062_Handler
IRQ063_Handler
IRQ064_Handler
IRQ065_Handler
IRQ066_Handler
IRQ067_Handler
IRQ068_Handler
IRQ069_Handler
IRQ070_Handler
IRQ071_Handler
IRQ072_Handler
IRQ073_Handler
IRQ074_Handler
IRQ075_Handler
IRQ076_Handler
IRQ077_Handler
IRQ078_Handler
IRQ079_Handler
IRQ080_Handler
IRQ081_Handler
IRQ082_Handler
IRQ083_Handler
IRQ084_Handler
IRQ085_Handler
IRQ086_Handler
IRQ087_Handler
IRQ088_Handler
IRQ089_Handler
IRQ090_Handler
IRQ091_Handler
IRQ092_Handler
IRQ093_Handler
IRQ094_Handler
IRQ095_Handler
IRQ096_Handler
IRQ097_Handler
IRQ098_Handler
IRQ099_Handler
IRQ100_Handler
IRQ101_Handler
IRQ102_Handler
IRQ103_Handler
IRQ104_Handler
IRQ105_Handler
IRQ106_Handler
IRQ107_Handler
IRQ108_Handler
IRQ109_Handler
IRQ110_Handler
IRQ111_Handler
IRQ112_Handler
IRQ113_Handler
IRQ114_Handler
IRQ115_Handler
IRQ116_Handler
IRQ117_Handler
IRQ118_Handler
IRQ119_Handler
IRQ120_Handler
IRQ121_Handler
IRQ122_Handler
IRQ123_Handler
IRQ124_Handler
IRQ125_Handler
IRQ126_Handler
IRQ127_Handler
IRQ128_Handler
IRQ129_Handler
IRQ130_Handler
IRQ131_Handler
IRQ132_Handler
IRQ133_Handler
IRQ134_Handler
IRQ135_Handler
IRQ136_Handler
IRQ137_Handler
IRQ138_Handler
IRQ139_Handler
IRQ140_Handler
IRQ141_Handler
IRQ142_Handler
IRQ143_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

565
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/*
;*******************************************************************************
; Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved.
;
; This software is owned and published by:
; Huada Semiconductor Co.,Ltd ("HDSC").
;
; BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
; BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
;
; This software contains source code for use with HDSC
; components. This software is licensed by HDSC to be adapted only
; for use in systems utilizing HDSC components. HDSC shall not be
; responsible for misuse or illegal use of this software for devices not
; supported herein. HDSC is providing this software "AS IS" and will
; not be responsible for issues arising from incorrect user implementation
; of the software.
;
; Disclaimer:
; HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
; REGARDING THE SOFTWARE (INCLUDING ANY ACCOMPANYING WRITTEN MATERIALS),
; ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
; WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
; WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
; WARRANTY OF NONINFRINGEMENT.
; HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
; NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
; LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
; LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
; INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
; INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
; SAVINGS OR PROFITS,
; EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
; YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
; INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
; FROM, THE SOFTWARE.
;
; This software may be replicated in part or whole for the licensed use,
; with the restriction that this Disclaimer and Copyright notice must be
; included with each copy of this software, whether used in part or whole,
; at all times.
;/
*/
/*****************************************************************************/
/* Startup for GCC */
/* Version V1.0 */
/* Date 2020-06-12 */
/* Target-mcu HC32F4A0 */
/*****************************************************************************/
/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
.syntax unified
.arch armv7e-m
.cpu cortex-m4
.fpu softvfp
.thumb
/*
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Stack_Size, 0x00002000
.section .stack
.align 3
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
/*
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Heap_Size, 0x00002000
.if Heap_Size != 0 /* Heap is provided */
.section .heap
.align 3
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space Heap_Size
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.endif
/*
;<h> Interrupt vector table start.
*/
.section .vectors, "a", %progbits
.align 2
.type __Vectors, %object
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* -14 NMI Handler */
.long HardFault_Handler /* -13 Hard Fault Handler */
.long MemManage_Handler /* -12 MPU Fault Handler */
.long BusFault_Handler /* -11 Bus Fault Handler */
.long UsageFault_Handler /* -10 Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* -5 SVCall Handler */
.long DebugMon_Handler /* -4 Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* -2 PendSV Handler */
.long SysTick_Handler /* -1 SysTick Handler */
/* Interrupts */
.long IRQ000_Handler
.long IRQ001_Handler
.long IRQ002_Handler
.long IRQ003_Handler
.long IRQ004_Handler
.long IRQ005_Handler
.long IRQ006_Handler
.long IRQ007_Handler
.long IRQ008_Handler
.long IRQ009_Handler
.long IRQ010_Handler
.long IRQ011_Handler
.long IRQ012_Handler
.long IRQ013_Handler
.long IRQ014_Handler
.long IRQ015_Handler
.long IRQ016_Handler
.long IRQ017_Handler
.long IRQ018_Handler
.long IRQ019_Handler
.long IRQ020_Handler
.long IRQ021_Handler
.long IRQ022_Handler
.long IRQ023_Handler
.long IRQ024_Handler
.long IRQ025_Handler
.long IRQ026_Handler
.long IRQ027_Handler
.long IRQ028_Handler
.long IRQ029_Handler
.long IRQ030_Handler
.long IRQ031_Handler
.long IRQ032_Handler
.long IRQ033_Handler
.long IRQ034_Handler
.long IRQ035_Handler
.long IRQ036_Handler
.long IRQ037_Handler
.long IRQ038_Handler
.long IRQ039_Handler
.long IRQ040_Handler
.long IRQ041_Handler
.long IRQ042_Handler
.long IRQ043_Handler
.long IRQ044_Handler
.long IRQ045_Handler
.long IRQ046_Handler
.long IRQ047_Handler
.long IRQ048_Handler
.long IRQ049_Handler
.long IRQ050_Handler
.long IRQ051_Handler
.long IRQ052_Handler
.long IRQ053_Handler
.long IRQ054_Handler
.long IRQ055_Handler
.long IRQ056_Handler
.long IRQ057_Handler
.long IRQ058_Handler
.long IRQ059_Handler
.long IRQ060_Handler
.long IRQ061_Handler
.long IRQ062_Handler
.long IRQ063_Handler
.long IRQ064_Handler
.long IRQ065_Handler
.long IRQ066_Handler
.long IRQ067_Handler
.long IRQ068_Handler
.long IRQ069_Handler
.long IRQ070_Handler
.long IRQ071_Handler
.long IRQ072_Handler
.long IRQ073_Handler
.long IRQ074_Handler
.long IRQ075_Handler
.long IRQ076_Handler
.long IRQ077_Handler
.long IRQ078_Handler
.long IRQ079_Handler
.long IRQ080_Handler
.long IRQ081_Handler
.long IRQ082_Handler
.long IRQ083_Handler
.long IRQ084_Handler
.long IRQ085_Handler
.long IRQ086_Handler
.long IRQ087_Handler
.long IRQ088_Handler
.long IRQ089_Handler
.long IRQ090_Handler
.long IRQ091_Handler
.long IRQ092_Handler
.long IRQ093_Handler
.long IRQ094_Handler
.long IRQ095_Handler
.long IRQ096_Handler
.long IRQ097_Handler
.long IRQ098_Handler
.long IRQ099_Handler
.long IRQ100_Handler
.long IRQ101_Handler
.long IRQ102_Handler
.long IRQ103_Handler
.long IRQ104_Handler
.long IRQ105_Handler
.long IRQ106_Handler
.long IRQ107_Handler
.long IRQ108_Handler
.long IRQ109_Handler
.long IRQ110_Handler
.long IRQ111_Handler
.long IRQ112_Handler
.long IRQ113_Handler
.long IRQ114_Handler
.long IRQ115_Handler
.long IRQ116_Handler
.long IRQ117_Handler
.long IRQ118_Handler
.long IRQ119_Handler
.long IRQ120_Handler
.long IRQ121_Handler
.long IRQ122_Handler
.long IRQ123_Handler
.long IRQ124_Handler
.long IRQ125_Handler
.long IRQ126_Handler
.long IRQ127_Handler
.long IRQ128_Handler
.long IRQ129_Handler
.long IRQ130_Handler
.long IRQ131_Handler
.long IRQ132_Handler
.long IRQ133_Handler
.long IRQ134_Handler
.long IRQ135_Handler
.long IRQ136_Handler
.long IRQ137_Handler
.long IRQ138_Handler
.long IRQ139_Handler
.long IRQ140_Handler
.long IRQ141_Handler
.long IRQ142_Handler
.long IRQ143_Handler
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.size __Vectors, . - __Vectors
/*
;<h> Interrupt vector table end.
*/
/*
;<h> Reset handler start.
*/
.section .text.Reset_Handler
.align 2
.weak Reset_Handler
.type Reset_Handler, %function
.globl Reset_Handler
Reset_Handler:
/* Set stack top pointer. */
ldr sp, =__StackTop
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
StackInit:
ldr r1, =__StackLimit
ldr r2, =__StackTop
movs r0, 0
StackInitLoop:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt StackInitLoop
ClrSramSR:
ldr r0, =0x40050810
ldr r1, =0x1FF
str r1, [r0]
/* Copy data from read only memory to RAM. */
CopyData:
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
CopyLoop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt CopyLoop
CopyData1:
ldr r1, =__etext_ramb
ldr r2, =__data_start_ramb__
ldr r3, =__data_end_ramb__
CopyLoop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt CopyLoop1
/* This part of work usually is done in C library startup code.
* Otherwise, define this macro to enable it in this startup.
*
* There are two schemes too.
* One can clear multiple BSS sections. Another can only clear one section.
* The former is more size expensive than the latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
/* Clear BSS section. */
ClearBss:
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
ClearLoop:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt ClearLoop
ClearBss1:
ldr r1, =__bss_start_ramb__
ldr r2, =__bss_end_ramb__
movs r0, 0
ClearLoop1:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt ClearLoop1
/* Call the clock system initialization function. */
bl SystemInit
/* Call the application's entry point. */
bl main
bx lr
.size Reset_Handler, . - Reset_Handler
/*
;<h> Reset handler end.
*/
/*
;<h> Default handler start.
*/
.section .text.Default_Handler, "ax", %progbits
.align 2
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/*
;<h> Default handler end.
*/
/* Macro to define default exception/interrupt handlers.
* Default handler are weak symbols with an endless loop.
* They can be overwritten by real handlers.
*/
.macro Set_Default_Handler Handler_Name
.weak \Handler_Name
.set \Handler_Name, Default_Handler
.endm
/* Default exception/interrupt handler */
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler IRQ000_Handler
Set_Default_Handler IRQ001_Handler
Set_Default_Handler IRQ002_Handler
Set_Default_Handler IRQ003_Handler
Set_Default_Handler IRQ004_Handler
Set_Default_Handler IRQ005_Handler
Set_Default_Handler IRQ006_Handler
Set_Default_Handler IRQ007_Handler
Set_Default_Handler IRQ008_Handler
Set_Default_Handler IRQ009_Handler
Set_Default_Handler IRQ010_Handler
Set_Default_Handler IRQ011_Handler
Set_Default_Handler IRQ012_Handler
Set_Default_Handler IRQ013_Handler
Set_Default_Handler IRQ014_Handler
Set_Default_Handler IRQ015_Handler
Set_Default_Handler IRQ016_Handler
Set_Default_Handler IRQ017_Handler
Set_Default_Handler IRQ018_Handler
Set_Default_Handler IRQ019_Handler
Set_Default_Handler IRQ020_Handler
Set_Default_Handler IRQ021_Handler
Set_Default_Handler IRQ022_Handler
Set_Default_Handler IRQ023_Handler
Set_Default_Handler IRQ024_Handler
Set_Default_Handler IRQ025_Handler
Set_Default_Handler IRQ026_Handler
Set_Default_Handler IRQ027_Handler
Set_Default_Handler IRQ028_Handler
Set_Default_Handler IRQ029_Handler
Set_Default_Handler IRQ030_Handler
Set_Default_Handler IRQ031_Handler
Set_Default_Handler IRQ032_Handler
Set_Default_Handler IRQ033_Handler
Set_Default_Handler IRQ034_Handler
Set_Default_Handler IRQ035_Handler
Set_Default_Handler IRQ036_Handler
Set_Default_Handler IRQ037_Handler
Set_Default_Handler IRQ038_Handler
Set_Default_Handler IRQ039_Handler
Set_Default_Handler IRQ040_Handler
Set_Default_Handler IRQ041_Handler
Set_Default_Handler IRQ042_Handler
Set_Default_Handler IRQ043_Handler
Set_Default_Handler IRQ044_Handler
Set_Default_Handler IRQ045_Handler
Set_Default_Handler IRQ046_Handler
Set_Default_Handler IRQ047_Handler
Set_Default_Handler IRQ048_Handler
Set_Default_Handler IRQ049_Handler
Set_Default_Handler IRQ050_Handler
Set_Default_Handler IRQ051_Handler
Set_Default_Handler IRQ052_Handler
Set_Default_Handler IRQ053_Handler
Set_Default_Handler IRQ054_Handler
Set_Default_Handler IRQ055_Handler
Set_Default_Handler IRQ056_Handler
Set_Default_Handler IRQ057_Handler
Set_Default_Handler IRQ058_Handler
Set_Default_Handler IRQ059_Handler
Set_Default_Handler IRQ060_Handler
Set_Default_Handler IRQ061_Handler
Set_Default_Handler IRQ062_Handler
Set_Default_Handler IRQ063_Handler
Set_Default_Handler IRQ064_Handler
Set_Default_Handler IRQ065_Handler
Set_Default_Handler IRQ066_Handler
Set_Default_Handler IRQ067_Handler
Set_Default_Handler IRQ068_Handler
Set_Default_Handler IRQ069_Handler
Set_Default_Handler IRQ070_Handler
Set_Default_Handler IRQ071_Handler
Set_Default_Handler IRQ072_Handler
Set_Default_Handler IRQ073_Handler
Set_Default_Handler IRQ074_Handler
Set_Default_Handler IRQ075_Handler
Set_Default_Handler IRQ076_Handler
Set_Default_Handler IRQ077_Handler
Set_Default_Handler IRQ078_Handler
Set_Default_Handler IRQ079_Handler
Set_Default_Handler IRQ080_Handler
Set_Default_Handler IRQ081_Handler
Set_Default_Handler IRQ082_Handler
Set_Default_Handler IRQ083_Handler
Set_Default_Handler IRQ084_Handler
Set_Default_Handler IRQ085_Handler
Set_Default_Handler IRQ086_Handler
Set_Default_Handler IRQ087_Handler
Set_Default_Handler IRQ088_Handler
Set_Default_Handler IRQ089_Handler
Set_Default_Handler IRQ090_Handler
Set_Default_Handler IRQ091_Handler
Set_Default_Handler IRQ092_Handler
Set_Default_Handler IRQ093_Handler
Set_Default_Handler IRQ094_Handler
Set_Default_Handler IRQ095_Handler
Set_Default_Handler IRQ096_Handler
Set_Default_Handler IRQ097_Handler
Set_Default_Handler IRQ098_Handler
Set_Default_Handler IRQ099_Handler
Set_Default_Handler IRQ100_Handler
Set_Default_Handler IRQ101_Handler
Set_Default_Handler IRQ102_Handler
Set_Default_Handler IRQ103_Handler
Set_Default_Handler IRQ104_Handler
Set_Default_Handler IRQ105_Handler
Set_Default_Handler IRQ106_Handler
Set_Default_Handler IRQ107_Handler
Set_Default_Handler IRQ108_Handler
Set_Default_Handler IRQ109_Handler
Set_Default_Handler IRQ110_Handler
Set_Default_Handler IRQ111_Handler
Set_Default_Handler IRQ112_Handler
Set_Default_Handler IRQ113_Handler
Set_Default_Handler IRQ114_Handler
Set_Default_Handler IRQ115_Handler
Set_Default_Handler IRQ116_Handler
Set_Default_Handler IRQ117_Handler
Set_Default_Handler IRQ118_Handler
Set_Default_Handler IRQ119_Handler
Set_Default_Handler IRQ120_Handler
Set_Default_Handler IRQ121_Handler
Set_Default_Handler IRQ122_Handler
Set_Default_Handler IRQ123_Handler
Set_Default_Handler IRQ124_Handler
Set_Default_Handler IRQ125_Handler
Set_Default_Handler IRQ126_Handler
Set_Default_Handler IRQ127_Handler
Set_Default_Handler IRQ128_Handler
Set_Default_Handler IRQ129_Handler
Set_Default_Handler IRQ130_Handler
Set_Default_Handler IRQ131_Handler
Set_Default_Handler IRQ132_Handler
Set_Default_Handler IRQ133_Handler
Set_Default_Handler IRQ134_Handler
Set_Default_Handler IRQ135_Handler
Set_Default_Handler IRQ136_Handler
Set_Default_Handler IRQ137_Handler
Set_Default_Handler IRQ138_Handler
Set_Default_Handler IRQ139_Handler
Set_Default_Handler IRQ140_Handler
Set_Default_Handler IRQ141_Handler
Set_Default_Handler IRQ142_Handler
Set_Default_Handler IRQ143_Handler
.end

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/**
*******************************************************************************
* @file system_hc32f4a0.c
* @brief This file provides two functions and one global variable to be called
* from user application
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Zhangxl First version
2020-07-03 Zhangxl Modify for 16MHz & 20MHz HRC
2020-09-10 Zhangxl Simplify the declare
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
/**
* @addtogroup CMSIS
* @{
*/
/**
* @addtogroup HC32F4A0_System
* @{
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/**
* @addtogroup HC32F4A0_System_Global_Variable
* @{
*/
/*!< System clock frequency (Core clock) */
__NO_INIT uint32_t SystemCoreClock;
/*!< High speed RC frequency (HCR clock) */
__NO_INIT uint32_t HRC_VALUE;
/**
* @}
*/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @addtogroup HC32F4A0_System_Global_Functions
* @{
*/
/**
* @brief Setup the microcontroller system. Initialize the System and update
* the SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
(*((volatile unsigned short*)(0x400543FEUL)))=0xA50BU;
(*((volatile unsigned int*)(0x4004CCE8UL)))=0x00040000UL;
(*((volatile unsigned short*)(0x400543FEUL)))=0xA500U;
/* FPU settings */
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
SystemCoreClockUpdate();
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint8_t tmp;
uint32_t plln;
uint32_t pllp;
uint32_t pllm;
/* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */
/* ICG1.HRCFREQSEL = '0' represent HRC_VALUE = 20000000UL */
/* ICG1.HRCFREQSEL = '1' represent HRC_VALUE = 16000000UL */
if (1UL == (HRC_FREQ_MON() & 1UL))
{
HRC_VALUE = HRC_16MHz_VALUE;
}
else
{
HRC_VALUE = HRC_20MHz_VALUE;
}
tmp = M4_CMU->CKSWR & CMU_CKSWR_CKSW;
switch(tmp)
{
case 0x00U: /* use internal high speed RC */
SystemCoreClock = HRC_VALUE;
break;
case 0x01U: /* use internal middle speed RC */
SystemCoreClock = MRC_VALUE;
break;
case 0x02U: /* use internal low speed RC */
SystemCoreClock = LRC_VALUE;
break;
case 0x03U: /* use external high speed OSC */
SystemCoreClock = XTAL_VALUE;
break;
case 0x04U: /* use external low speed OSC */
SystemCoreClock = XTAL32_VALUE;
break;
case 0x05U: /* use PLLH */
/* PLLCLK = ((pllsrc / pllm) * plln) / pllp */
pllp = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHP_POS) & 0x0FUL);
plln = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL);
pllm = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL);
/* use external high speed OSC as PLL source */
if (0UL == bM4_CMU->PLLHCFGR_b.PLLSRC)
{
SystemCoreClock = (XTAL_VALUE) / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
}
/* use internal high RC as PLL source */
else
{
SystemCoreClock = (HRC_VALUE) / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
}
break;
default:
break;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2019 IAR Systems
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.3
* @date 24. June 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 13. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t vectors = 0x0U;
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = 0x0U;
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.1
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

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/**
*******************************************************************************
* @file hc32f4a0_adc.h
* @brief This file contains all the functions prototypes of the ADC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Wuze First version
2020-12-15 Wuze ADC_ComTriggerCmd() refine.
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_ADC_H__
#define __HC32F4A0_ADC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_ADC
* @{
*/
#if (DDL_ADC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup ADC_Global_Types ADC Global Types
* @{
*/
/**
* @brief Structure definition of ADC initialization.
*/
typedef struct
{
uint16_t u16ScanMode; /*!< Configures the scan convert mode of ADC.
This parameter can be a value of @ref ADC_Scan_Convert_Mode */
uint16_t u16Resolution; /*!< Configures the ADC resolution.
This parameter can be a value of @ref ADC_Resolution */
uint16_t u16AutoClrCmd; /*!< Configures whether the ADC data register is
automatically cleared after the data is read.
This parameter can be a value of @ref ADC_Data_Auto_Clear_Cmd */
uint16_t u16DataAlign; /*!< Specifies ADC data alignment to right or to left.
This parameter can be a value of @ref ADC_Data_Alignment */
uint16_t u16SAResumePos; /*!< Specifies the resume channel position of sequence A.
Sequence A can be interrupted by sequence B. After the
the ending of sequence B, sequence A resumes from the
specified channel position.
This parameter can be a value of @ref ADC_Sequence_A_Resume_Channel_Position */
} stc_adc_init_t;
/**
* @brief Structure definition of ADC trigger source configuration.
*/
typedef struct
{
uint16_t u16TrigSrc; /*!< Specifies the trigger source type for the specified sequence.
This parameter can be a value of @ref ADC_Trigger_Source_Type */
en_event_src_t enEvent0; /*!< An @ref en_event_src_t enumeration value. */
en_event_src_t enEvent1; /*!< An @ref en_event_src_t enumeration value. */
} stc_adc_trig_cfg_t;
/**
* @brief Structure definition of AWD(analog watchdog) configuration.
*/
typedef struct
{
uint8_t u8ChNum; /*!< The number of the ADC channel which to be configured as an AWD channel.
This parameter can be a value of range [ADC_CH_NUM_0, ADC_CH_NUM_15] of @ref ADC_Channel_Number */
uint16_t u16CmpMode; /*!< The comparison mode of AWD.
This parameter can be a value of @ref ADC_AWD_Comparison_Mode */
uint16_t u16LowerLimit; /*!< Threshold lower limit value(to register ADC_AWDxDR0). */
uint16_t u16UpperLimit; /*!< Threshold upper limit value(to register ADC_AWDxDR1). */
} stc_adc_awd_cfg_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup ADC_Global_Macros ADC Global Macros
* @{
*/
/**
* @defgroup ADC_Sequence ADC Sequence
* @{
*/
#define ADC_SEQ_A (0U)
#define ADC_SEQ_B (1U)
/**
* @}
*/
/**
* @defgroup ADC_AWD_Unit ADC Analog Watchdog Unit
* @{
*/
#define ADC_AWD_0 (0U)
#define ADC_AWD_1 (1U)
/**
* @}
*/
/**
* @defgroup ADC_Scan_Convert_Mode ADC Scan Convert Mode
* @{
*/
#define ADC_MODE_SA_SSHOT (0x0U) /*!< Sequence A single shot. */
#define ADC_MODE_SA_CONT (ADC_CR0_MS_0) /*!< Sequence A continuous. */
#define ADC_MODE_SA_SB_SSHOT (ADC_CR0_MS_1) /*!< Sequence A and B both single shot. */
#define ADC_MODE_SA_CONT_SB_SSHOT (ADC_CR0_MS_1 | \
ADC_CR0_MS_0) /*!< Sequence A continuous and sequence B single shot. */
/**
* @}
*/
/**
* @defgroup ADC_Resolution ADC Resolution
* @{
*/
#define ADC_RESOLUTION_12BIT (0x0U) /*!< Resolution is 12 bit. */
#define ADC_RESOLUTION_10BIT (ADC_CR0_ACCSEL_0) /*!< Resolution is 10 bit. */
#define ADC_RESOLUTION_8BIT (ADC_CR0_ACCSEL_1) /*!< Resolution is 8 bit. */
/**
* @}
*/
/**
* @defgroup ADC_Data_Auto_Clear_Cmd ADC Data Auto Clear Cmd
* @{
*/
#define ADC_AUTO_CLR_DISABLE (0x0U)
#define ADC_AUTO_CLR_ENABLE (ADC_CR0_CLREN) /*!< ADC data register is automatically cleared after the data is read. */
/**
* @}
*/
/**
* @defgroup ADC_Data_Alignment ADC Data Alignment
* @{
*/
#define ADC_DATA_ALIGN_RIGHT (0x0U)
#define ADC_DATA_ALIGN_LEFT (ADC_CR0_DFMT)
/**
* @}
*/
/**
* @defgroup ADC_Average_Count ADC Average Count
* @{
*/
#define ADC_AVG_CNT_2 (0x0U)
#define ADC_AVG_CNT_4 (ADC_CR0_AVCNT_0)
#define ADC_AVG_CNT_8 (ADC_CR0_AVCNT_1)
#define ADC_AVG_CNT_16 (ADC_CR0_AVCNT_1 | ADC_CR0_AVCNT_0)
#define ADC_AVG_CNT_32 (ADC_CR0_AVCNT_2)
#define ADC_AVG_CNT_64 (ADC_CR0_AVCNT_2 | ADC_CR0_AVCNT_0)
#define ADC_AVG_CNT_128 (ADC_CR0_AVCNT_2 | ADC_CR0_AVCNT_1)
#define ADC_AVG_CNT_256 (ADC_CR0_AVCNT_2 | ADC_CR0_AVCNT_1 | ADC_CR0_AVCNT_0)
/**
* @}
*/
/**
* @defgroup ADC_Sequence_A_Resume_Channel_Position ADC Sequence A Resume Channel Position
* @{
*/
#define ADC_SA_RESUME_POS_INT_CH (0x0U) /*!< Resumes from the interrupt channel of the sequence. */
#define ADC_SA_RESUME_POS_FIRST_CH (ADC_CR1_RSCHSEL) /*!< Resumes from the first channel of the sequence. */
/**
* @}
*/
/**
* @defgroup ADC_Trigger_Source_Type ADC Trigger Source Type
* @{
*/
#define ADC_TRIG_SRC_ADTRG (0x0U) /*!< The trigger source is the falling edge(the low level of the should \
hold at least 1.5*PCLK cycle) of external pin ADTRGx(x=1, 2, 3). */
#define ADC_TRIG_SRC_EVENT0 (ADC_TRGSR_TRGSELA_0) /*!< The trigger source is a internal event from other peripheral. \
Only one event can be configured to trigger ADC. */
#define ADC_TRIG_SRC_EVENT1 (ADC_TRGSR_TRGSELA_1) /*!< The trigger source is a internal event from other peripheral. \
Only one event can be configured to trigger ADC. */
#define ADC_TRIG_SRC_EVENT0_EVENT1 (ADC_TRGSR_TRGSELA_0 | \
ADC_TRGSR_TRGSELA_1) /*!< The trigger source are two internal events from other peripheral(s). \
Two events can be configured to trigger ADC and one of which can trigger the ADC. */
/**
* @}
*/
/**
* @defgroup ADC_Channel_Number ADC Channel Number
* @{
*/
#define ADC_CH_NUM_0 (0U)
#define ADC_CH_NUM_1 (1U)
#define ADC_CH_NUM_2 (2U)
#define ADC_CH_NUM_3 (3U)
#define ADC_CH_NUM_4 (4U)
#define ADC_CH_NUM_5 (5U)
#define ADC_CH_NUM_6 (6U)
#define ADC_CH_NUM_7 (7U)
#define ADC_CH_NUM_8 (8U)
#define ADC_CH_NUM_9 (9U)
#define ADC_CH_NUM_10 (10U)
#define ADC_CH_NUM_11 (11U)
#define ADC_CH_NUM_12 (12U)
#define ADC_CH_NUM_13 (13U)
#define ADC_CH_NUM_14 (14U)
#define ADC_CH_NUM_15 (15U)
#define ADC_CH_NUM_16 (16U)
#define ADC_CH_NUM_17 (17U)
#define ADC_CH_NUM_18 (18U)
#define ADC_CH_NUM_19 (19U)
/**
* @}
*/
/**
* @defgroup ADC_Channel ADC Channel
* @{
*/
#define ADC_CH0 (0x1UL << ADC_CH_NUM_0)
#define ADC_CH1 (0x1UL << ADC_CH_NUM_1)
#define ADC_CH2 (0x1UL << ADC_CH_NUM_2)
#define ADC_CH3 (0x1UL << ADC_CH_NUM_3)
#define ADC_CH4 (0x1UL << ADC_CH_NUM_4)
#define ADC_CH5 (0x1UL << ADC_CH_NUM_5)
#define ADC_CH6 (0x1UL << ADC_CH_NUM_6)
#define ADC_CH7 (0x1UL << ADC_CH_NUM_7)
#define ADC_CH8 (0x1UL << ADC_CH_NUM_8)
#define ADC_CH9 (0x1UL << ADC_CH_NUM_9)
#define ADC_CH10 (0x1UL << ADC_CH_NUM_10)
#define ADC_CH11 (0x1UL << ADC_CH_NUM_11)
#define ADC_CH12 (0x1UL << ADC_CH_NUM_12)
#define ADC_CH13 (0x1UL << ADC_CH_NUM_13)
#define ADC_CH14 (0x1UL << ADC_CH_NUM_14)
#define ADC_CH15 (0x1UL << ADC_CH_NUM_15)
#define ADC_CH16 (0x1UL << ADC_CH_NUM_16)
#define ADC_CH17 (0x1UL << ADC_CH_NUM_17)
#define ADC_CH18 (0x1UL << ADC_CH_NUM_18)
#define ADC_CH19 (0x1UL << ADC_CH_NUM_19)
#define ADC_EXT_CH (ADC_CH15)
/**
* @}
*/
/**
* @defgroup ADC_Pin_Number ADC Pin Number
* @{
*/
#define ADC123_IN0 (0U) /*!< PA0 */
#define ADC123_IN1 (1U) /*!< PA1 */
#define ADC123_IN2 (2U) /*!< PA2 */
#define ADC123_IN3 (3U) /*!< PA3 */
#define ADC12_IN4 (4U) /*!< PA4 */
#define ADC12_IN5 (5U) /*!< PA5 */
#define ADC12_IN6 (6U) /*!< PA6 */
#define ADC12_IN7 (7U) /*!< PA7 */
#define ADC12_IN8 (8U) /*!< PB0 */
#define ADC12_IN9 (9U) /*!< PB1 */
#define ADC123_IN10 (10U) /*!< PC0 */
#define ADC123_IN11 (11U) /*!< PC1 */
#define ADC123_IN12 (12U) /*!< PC2 */
#define ADC123_IN13 (13U) /*!< PC3 */
#define ADC12_IN14 (14U) /*!< PC4 */
#define ADC12_IN15 (15U) /*!< PC5 */
#define ADC3_IN4 (4U) /*!< PF6 */
#define ADC3_IN5 (5U) /*!< PF7 */
#define ADC3_IN6 (6U) /*!< PF8 */
#define ADC3_IN7 (7U) /*!< PF9 */
#define ADC3_IN8 (8U) /*!< PF10 */
#define ADC3_IN9 (9U) /*!< PF3 */
#define ADC3_IN14 (14U) /*!< PF4 */
#define ADC3_IN15 (15U) /*!< PF5 */
#define ADC3_IN16 (16U) /*!< PH2 */
#define ADC3_IN17 (17U) /*!< PH3 */
#define ADC3_IN18 (18U) /*!< PH4 */
#define ADC3_IN19 (19U) /*!< PH5 */
/**
* @}
*/
/**
* @defgroup ADC_All_Channels_Mask ADC All Channels Mask
* @{
*/
#define ADC1_CH_ALL (0xFFFFUL)
#define ADC2_CH_ALL (0xFFFFUL)
#define ADC3_CH_ALL (0xFFFFFUL)
#define ADC_CH_REMAP_ALL (0xFFFFUL)
/**
* @}
*/
/**
* @defgroup ADC_Channel_Count ADC Channel Count
* @{
*/
#define ADC1_CH_COUNT (16U)
#define ADC2_CH_COUNT (16U)
#define ADC3_CH_COUNT (20U)
/**
* @}
*/
/**
* @defgroup ADC_Invalid_Value ADC Invalid Value
* @{
*/
#define ADC_INVALID_VAL (0xFFFFU)
/**
* @}
*/
/**
* @defgroup ADC_Extend_Channel_Source ADC Extend Channel Source
* @{
*/
#define ADC_EXCH_SRC_ADC_PIN (0x0U) /*!< The input source of the extended channel is analog input pin. */
#define ADC_EXCH_SRC_INTERNAL (ADC_EXCHSELR_EXCHSEL) /*!< The input source of the extended channel is internal analog signal. */
/**
* @}
*/
/**
* @defgroup ADC_Sequence_Status_Flag ADC Sequence Status Flag
* @{
*/
#define ADC_SEQ_FLAG_EOCA (ADC_ISR_EOCAF) /*!< Status flag of the end of conversion of sequence A. */
#define ADC_SEQ_FLAG_EOCB (ADC_ISR_EOCBF) /*!< Status flag of the end of conversion of sequence B. */
#define ADC_SEQ_FLAG_NESTED (ADC_ISR_SASTPDF) /*!< Status flag of sequence A was interrupted by sequence B. */
#define ADC_SEQ_FLAG_ALL (ADC_SEQ_FLAG_EOCA | \
ADC_SEQ_FLAG_EOCB | \
ADC_SEQ_FLAG_NESTED)
/**
* @}
*/
/**
* @defgroup ADC_Synchronous_Unit ADC Synchronous Unit
* @{
*/
#define ADC_SYNC_ADC1_ADC2 (0U) /*!< ADC1 and ADC2 work synchronously. */
#define ADC_SYNC_ADC1_ADC2_ADC3 (ADC_SYNCCR_SYNCMD_0) /*!< ADC1, ADC2 and ADC3 work synchronously. */
/**
* @}
*/
/**
* @defgroup ADC_Synchronous_Mode ADC Synchronous Mode
* @{
*/
#define ADC_SYNC_SSHOT_SEQUENTIAL (0U) /*!< Single shot trigger, sequentially trigger. \
When the trigger condition occurs, ADC1 starts before ADC2, \
and ADC1 and ADC2 only perform one sample conversion. */
#define ADC_SYNC_SSHOT_SIMULTANEOUS (ADC_SYNCCR_SYNCMD_1) /*!< Single shot trigger, simultaneously trigger. \
When the trigger condition occurs, ADC1 and ADC2 start at the same time, \
and ADC1 and ADC2 only perform one sample conversion. */
#define ADC_SYNC_CONT_SEQUENTIAL (ADC_SYNCCR_SYNCMD_2) /*!< Continuously trigger, sequentially trigger. \
When the trigger condition occurs, ADC1 starts before ADC2, \
and ADC1 and ADC2 will continue to sample conversion until stoped by software. */
#define ADC_SYNC_CONT_SIMULTANEOUS (ADC_SYNCCR_SYNCMD_2 | \
ADC_SYNCCR_SYNCMD_1) /*!< Continuously trigger, simultaneously trigger. \
When the trigger condition occurs, ADC1 and ADC2 start at the same time, \
and ADC1 and ADC2 will continue to sample conversion until stoped by software. */
/**
* @}
*/
/**
* @defgroup ADC_AWD_Comparison_Mode ADC AWD(Analog Watchdog) Comparison Mode
* @{
*/
#define ADC_AWD_CMP_OUT_RANGE (0x0U) /*!< ADCVal > UpperLimit or ADCVal < LowerLimit */
#define ADC_AWD_CMP_IN_RANGE (0x1U) /*!< LowerLimit < ADCVal < UpperLimit */
/**
* @}
*/
/**
* @defgroup ADC_AWD_Combination_Mode ADC AWD(Analog Watchdog) Combination Mode
* @note If combination mode is valid(ADC_AWD_COMB_OR/ADC_AWD_COMB_AND/ADC_AWD_COMB_XOR) and
the Channels selected by the AWD0 and AWD1 are deferent, make sure that the channel
of AWD1 is converted after the channel conversion of AWD0 ends.
* @{
*/
#define ADC_AWD_COMB_OR (ADC_AWDCR_AWDCM_0) /*!< The status of AWD0 is set or the status of AWD1 is set, the status of combination mode is set. */
#define ADC_AWD_COMB_AND (ADC_AWDCR_AWDCM_1) /*!< The status of AWD0 is set and the status of AWD1 is set, the status of combination mode is set. */
#define ADC_AWD_COMB_XOR (ADC_AWDCR_AWDCM_1 | \
ADC_AWDCR_AWDCM_0) /*!< Only one of the status of AWD0 and AWD1 is set, the status of combination mode is set. */
/**
* @}
*/
/**
* @defgroup ADC_AWD_Status_Flag ADC AWD Status Flag
* @{
*/
#define ADC_AWD_FLAG_AWD0 (ADC_AWDSR_AWD0F) /*!< Flag of AWD0. */
#define ADC_AWD_FLAG_AWD1 (ADC_AWDSR_AWD1F) /*!< Flag of AWD1. */
#define ADC_AWD_FLAG_COMB (ADC_AWDSR_AWDCMF) /*!< Flag of combination of mode. */
#define ADC_AWD_FLAG_ALL (ADC_AWD_FLAG_AWD0 | \
ADC_AWD_FLAG_AWD1 | \
ADC_AWD_FLAG_COMB)
/**
* @}
*/
/**
* @defgroup ADC_PGA_Gain_Factor ADC PGA Gain Factor
* @{
*/
#define ADC_PGA_GAIN_2 (0U) /*!< PGA gain factor is 2. */
#define ADC_PGA_GAIN_2P133 (ADC_PGACR3_PGAGAIN_0) /*!< PGA gain factor is 2.133. */
#define ADC_PGA_GAIN_2P286 (ADC_PGACR3_PGAGAIN_1) /*!< PGA gain factor is 2.286. */
#define ADC_PGA_GAIN_2P667 (ADC_PGACR3_PGAGAIN_1 | \
ADC_PGACR3_PGAGAIN_0) /*!< PGA gain factor is 2.667. */
#define ADC_PGA_GAIN_2P909 (ADC_PGACR3_PGAGAIN_2) /*!< PGA gain factor is 2.909. */
#define ADC_PGA_GAIN_3P2 (ADC_PGACR3_PGAGAIN_2 | \
ADC_PGACR3_PGAGAIN_0) /*!< PGA gain factor is 3.2. */
#define ADC_PGA_GAIN_3P556 (ADC_PGACR3_PGAGAIN_2 | \
ADC_PGACR3_PGAGAIN_1) /*!< PGA gain factor is 2.556. */
#define ADC_PGA_GAIN_4 (ADC_PGACR3_PGAGAIN_2 | \
ADC_PGACR3_PGAGAIN_1 | \
ADC_PGACR3_PGAGAIN_0) /*!< PGA gain factor is 4. */
#define ADC_PGA_GAIN_4P571 (ADC_PGACR3_PGAGAIN_3) /*!< PGA gain factor is 4.571. */
#define ADC_PGA_GAIN_5P333 (ADC_PGACR3_PGAGAIN_3 | \
ADC_PGACR3_PGAGAIN_0) /*!< PGA gain factor is 5.333. */
#define ADC_PGA_GAIN_6P4 (ADC_PGACR3_PGAGAIN_3 | \
ADC_PGACR3_PGAGAIN_1) /*!< PGA gain factor is 6.4. */
#define ADC_PGA_GAIN_8 (ADC_PGACR3_PGAGAIN_3 | \
ADC_PGACR3_PGAGAIN_1 | \
ADC_PGACR3_PGAGAIN_0) /*!< PGA gain factor is 8. */
#define ADC_PGA_GAIN_10P667 (ADC_PGACR3_PGAGAIN_3 | \
ADC_PGACR3_PGAGAIN_2) /*!< PGA gain factor is 10.667. */
#define ADC_PGA_GAIN_16 (ADC_PGACR3_PGAGAIN_3 | \
ADC_PGACR3_PGAGAIN_2 | \
ADC_PGACR3_PGAGAIN_0) /*!< PGA gain factor is 16. */
#define ADC_PGA_GAIN_32 (ADC_PGACR3_PGAGAIN_3 | \
ADC_PGACR3_PGAGAIN_2 | \
ADC_PGACR3_PGAGAIN_1) /*!< PGA gain factor is 32. */
/**
* @}
*/
/**
* @defgroup ADC_PGA_VSS ADC PGA VSS
* @{
*/
#define ADC_PGA_VSS_PGAVSS (0U) /*!< Use pin PGAx_VSS as the reference GND of PGAx */
#define ADC_PGA_VSS_AVSS (1U) /*!< Use AVSS as the reference GND of PGAx. */
/**
* @}
*/
/**
* @defgroup ADC_PGA_Unit ADC PGA Unit
* @{
*/
#define ADC_PGA_1 (0U) /*!< PGA1, belongs to ADC1. Input pin is ADC123_IN0. */
#define ADC_PGA_2 (1U) /*!< PGA2, belongs to ADC1. Input pin is ADC123_IN1. */
#define ADC_PGA_3 (2U) /*!< PGA3, belongs to ADC1. Input pin is ADC123_IN2. */
#define ADC_PGA_4 (3U) /*!< PGA4, belongs to ADC2. Input pin is ADC12_IN6. */
/**
* @}
*/
/**
* @defgroup ADC_Common_Trigger_Sel ADC Common Trigger Source Select
* @{
*/
#define ADC_COM_TRIG1 (AOS_ADC_1_ITRGSELR_COMTRG_EN_0)
#define ADC_COM_TRIG2 (AOS_ADC_1_ITRGSELR_COMTRG_EN_1)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup ADC_Global_Functions
* @{
*/
en_result_t ADC_Init(M4_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcInit);
void ADC_DeInit(M4_ADC_TypeDef *ADCx);
en_result_t ADC_StructInit(stc_adc_init_t *pstcInit);
void ADC_SetScanMode(M4_ADC_TypeDef *ADCx, uint16_t u16Mode);
en_result_t ADC_ChannelCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, \
uint32_t u32AdcCh, const uint8_t pu8SplTime[], \
en_functional_state_t enNewState);
void ADC_AvgChannelConfig(M4_ADC_TypeDef *ADCx, uint16_t u16AvgCnt);
void ADC_AvgChannelCmd(M4_ADC_TypeDef *ADCx, uint32_t u32AdcCh, en_functional_state_t enNewState);
void ADC_SetExChannelSrc(M4_ADC_TypeDef *ADCx, uint8_t u8ExChSrc);
en_result_t ADC_TrigSrcStructInit(stc_adc_trig_cfg_t *pstcCfg);
en_result_t ADC_TrigSrcConfig(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, const stc_adc_trig_cfg_t *pstcCfg);
void ADC_TrigSrcCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState);
void ADC_ComTriggerCmd(M4_ADC_TypeDef *ADCx, uint16_t u16TrigSrc, \
uint32_t u32ComTrig, en_functional_state_t enNewState);
void ADC_SeqIntCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState);
en_flag_status_t ADC_SeqGetStatus(const M4_ADC_TypeDef *ADCx, uint8_t u8Flag);
void ADC_SeqClrStatus(M4_ADC_TypeDef *ADCx, uint8_t u8Flag);
en_result_t ADC_AWD_Config(M4_ADC_TypeDef *ADCx, uint8_t u8AWDx, const stc_adc_awd_cfg_t *pstcCfg);
void ADC_AWD_CombModeCmd(M4_ADC_TypeDef *ADCx, uint16_t u16CombMode, en_functional_state_t enNewState);
void ADC_AWD_Cmd(M4_ADC_TypeDef *ADCx, uint8_t u8AWDx, en_functional_state_t enNewState);
void ADC_AWD_IntCmd(M4_ADC_TypeDef *ADCx, uint8_t u8AWDx, en_functional_state_t enNewState);
en_flag_status_t ADC_AWD_GetStatus(const M4_ADC_TypeDef *ADCx, uint8_t u8Flag);
void ADC_AWD_ClrStatus(M4_ADC_TypeDef *ADCx, uint8_t u8Flag);
void ADC_PGA_Config(uint8_t u8PGAx, uint8_t u8GainFactor, uint8_t u8PgaVss);
void ADC_PGA_Cmd(uint8_t u8PGAx, en_functional_state_t enNewState);
void ADC_SYNC_Config(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TrigDelay);
void ADC_SYNC_Cmd(en_functional_state_t enNewState);
void ADC_SH_Config(uint8_t u8SplTime);
void ADC_SH_ChannelCmd(uint32_t u32AdcCh, en_functional_state_t enNewState);
void ADC_ChannelRemap(M4_ADC_TypeDef *ADCx, uint32_t u32AdcCh, uint8_t u8AdcPinNum);
uint8_t ADC_GetChannelPinNum(const M4_ADC_TypeDef *ADCx, uint32_t u32AdcCh);
en_result_t ADC_PollingSA(M4_ADC_TypeDef *ADCx, uint16_t pu16AdcVal[], uint8_t u8Length, uint32_t u32Timeout);
void ADC_Start(M4_ADC_TypeDef *ADCx);
void ADC_Stop(M4_ADC_TypeDef *ADCx);
en_result_t ADC_GetAllData(const M4_ADC_TypeDef *ADCx, uint16_t pu16AdcVal[], uint8_t u8Length);
en_result_t ADC_GetChannelData(const M4_ADC_TypeDef *ADCx, uint32_t u32TargetCh, \
uint16_t pu16AdcVal[], uint8_t u8Length);
uint16_t ADC_GetValue(const M4_ADC_TypeDef *ADCx, uint8_t u8ChNum);
/**
* @}
*/
#endif /* DDL_ADC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_ADC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_aes.h
* @brief This file contains all the functions prototypes of the AES driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Heqb First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_AES_H__
#define __HC32F4A0_AES_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_AES
* @{
*/
#if (DDL_AES_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup AES_Global_Macros AES Global Macros
* @{
*/
/* AES key length in bytes is 16. */
#define AES_BLOCK_LEN (16U)
/**
* @defgroup AES_STATUS AES Start or Stop
* @{
*/
#define AES_START (AES_CR_START)
#define AES_STOP (0x0UL)
/**
* @}
*/
/**
* @defgroup AES_KEY_SIZE AES Key Size
* @{
*/
#define AES_KEY_SIZE_128BIT (0UL << AES_CR_KEYSIZE_POS)
#define AES_KEY_SIZE_192BIT (1UL << AES_CR_KEYSIZE_POS)
#define AES_KEY_SIZE_256BIT (2UL << AES_CR_KEYSIZE_POS)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup AES_Global_Functions
* @{
*/
en_result_t AES_Encrypt(uint8_t au8Plaintext[],
uint32_t u32PlaintextSize,
const uint8_t *pu8Key,
uint8_t u8KeyLength,
uint8_t au8Ciphertext[]);
en_result_t AES_Decrypt(uint8_t au8Ciphertext[],
uint32_t u32CiphertextSize,
const uint8_t *pu8Key,
uint8_t u8KeyLength,
uint8_t au8Plaintext[]);
/**
* @}
*/
#endif /* DDL_AES_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_AES_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_can.h
* @brief This file contains all the functions prototypes of the CAN driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Wuze First version
2020-12-14 Wuze Modified comment of structure stc_can_bt_cfg_t
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_CAN_H__
#define __HC32F4A0_CAN_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_CAN
* @{
*/
#if (DDL_CAN_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup CAN_Global_Types CAN Global Types
* @{
*/
/**
* @brief CAN bit timing configuration structure. See 11898-1 for details.
* @note 1. Restrictions: u32SEG1 >= u32SEG2 + 1, u32SEG2 >= u32SJW.
* @note 2. TQ = u32Prescaler / CANClock.
* @note 3. Bit time = (u32SEG2 + u32SEG2) x TQ.
* @note 4. Baudrate = CANClock/(u32Prescaler*(u32SEG1 + u32SEG2))
*/
typedef struct
{
uint32_t u32SEG1; /*!< TQs of segment 1. Contains synchronization segment, \
propagation time segment and phase buffer segment 1. */
uint32_t u32SEG2; /*!< TQs of segment 2. Phase buffer segment 2. */
uint32_t u32SJW; /*!< TQs of synchronization jump width. */
uint32_t u32Prescaler; /*!< Range [1, 256]. */
} stc_can_bt_cfg_t;
/**
* @brief CAN acceptance filter structure.
*/
typedef struct
{
uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */
uint32_t u32IDMsk; /*!< ID mask. The mask bits of ID will be ignored by the acceptance filter. */
uint32_t u32MskType; /*!< Acceptance filter mask type. This parameter can be a value of @ref CAN_AF_Mask_Type */
} stc_can_af_cfg_t;
/**
* @brief CAN FD configuration structure.
*/
typedef struct
{
uint8_t u8CANFDMode; /*!< CAN-FD mode, Bosch CAN-FD or 11898-1:2015 CAN-FD.
This parameter can be a value of @ref CAN_FD_Mode */
stc_can_bt_cfg_t stcFBT; /*!< Bit timing configuration of fast bit timing. */
uint8_t u8TDCCmd; /*!< Transmiter delay compensation function control.
This parameter can be a value of @ref CAN_FD_TDC_Command */
uint8_t u8TDCSSP; /*!< Specify secondary sample point(SSP) of transmitter delay compensatin(TDC). Number of TQ. */
} stc_can_fd_cfg_t;
/**
* @brief CAN time-triggered communication configuration structure.
*/
typedef struct
{
uint8_t u8TransBufMode; /*!< TTCAN Transmit Buffer Mode.
This parameter can be a value of @ref CAN_TTC_Transmit_Buffer_Mode */
uint8_t u8NTUPrescaler; /*!< Prescaler of NTU(network time unit). The source is the bit time which is defined by SBT.
This parameter can be a value of @ref CAN_TTC_NTU_Prescaler */
uint32_t u32RefMsgIDE; /*!< Reference message identifier extension bit.
'1' to set the ID which is specified by parameter 'u32RefMsgID' as an extended ID while \
'0' to set it as a standard ID. */
uint32_t u32RefMsgID; /*!< Reference message identifier. */
uint16_t u16TrigType; /*!< Trigger type of TTC.
This parameter can be a value of @ref CAN_TTC_Trigger_Type */
uint16_t u16TxEnWindow; /*!< Tx_Enable window. Time period within which the transmission of a message may be started. Range is [1, 16U] */
uint16_t u16TxTrigTime; /*!< Specifies for the referred message the time window of the matrix cycle at which it is to be transmitted. */
uint16_t u16WatchTrigTime; /*!< Time mark used to check whether the time since the last valid reference message has been too long. */
} stc_can_ttc_cfg_t;
/**
* @brief CAN initialization structure.
*/
typedef struct
{
uint8_t u8WorkMode; /*!< Specify the work mode of CAN.
This parameter can be a value of @ref CAN_Work_Mode */
stc_can_bt_cfg_t stcSBT; /*!< Bit timing configuration of slow bit timing. */
en_functional_state_t enCANFDCmd; /*!< Enable or Disable CAN-FD. If Disable, the following configuration valuse will not \
be written to the registers. */
stc_can_fd_cfg_t stcFDCfg; /*!< CAN-FD configuration structure. */
uint8_t u8TransMode; /*!< Transmission mode of PTB and STB.
This parameter can be a value of @ref CAN_Trans_Mode */
uint8_t u8STBPrioMode; /*!< Priority mode of STB. First in first transmit. OR the priority is determined by ID. Smaller ID higher priority.
Whatever the priority mode of STB is, PTB always has the highest priority.
This parameter can be a value of @ref CAN_STB_Priority_Mode */
uint8_t u8RBSWarnLimit; /*!< Specify receive buffer almost full warning limit. Rang is [1, 8]. \
Each CAN unit has 8 receive buffer slots. When the number of received frames reaches \
the set value of u8RBSWarnLimit, register bit RTIF.RAFIF is set and the interrupt occurred \
if it was enabled. */
uint8_t u8ErrWarnLimit; /*!< Specify programmable error warning limit. Range is [0, 15]. \
Error warning limit = (u8ErrWarnLimit + 1) * 8. */
stc_can_af_cfg_t *pstcAFCfg; /*!< Points to a stc_can_af_cfg_t structure type pointer value that
contains the configuration informations for the acceptance filters. */
uint16_t u16AFSel; /*!< Specify acceptance filter for receive buffer.
This parameter can be values of @ref CAN_AF */
uint8_t u8RBStoreSel; /*!< Receive buffer stores all data frames, includes error data.
This parameter can be a value of @ref CAN_RB_Store_Selection */
uint8_t u8RBOvfOp; /*!< Operation when receive buffer overflow.
This parameter can be a value of @ref CAN_RB_Overflow_Operation */
uint8_t u8SelfACKCmd; /*!< Self ACK. Only for external loopback mode.
This parameter can be a value of @ref CAN_Self_ACK_Command */
} stc_can_init_t;
/**
* @brief CAN transmit data structure.
*/
typedef struct
{
uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */
union
{
uint32_t u32Ctrl;
struct
{
uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame. \
It should be zero while the frame is remote frame. \
This parameter can be a value of @ref CAN_DLC */
uint32_t BRS: 1; /*!< Bit rate switch. */
uint32_t FDF: 1; /*!< CAN FD frame. */
uint32_t RTR: 1; /*!< Remote transmission request bit.
It is used to distinguish between data frames and remote frames. */
uint32_t IDE: 1; /*!< Identifier extension flag.
It is used to distinguish between standard format and extended format.
This parameter can be a 1 or 0. */
uint32_t RSVD: 24; /*!< Reserved bits. */
};
};
uint8_t *pu8Data; /*!< Pointer to data filed of data frame. */
} stc_can_tx_t;
/**
* @brief CAN receive data structure.
*/
typedef struct
{
uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */
union
{
uint32_t u32Ctrl;
struct
{
uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame. \
It should be zero while the frame is remote frame. \
This parameter can be a value of @ref CAN_DLC */
uint32_t BRS: 1; /*!< Bit rate switch. */
uint32_t FDF: 1; /*!< CAN FD frame. */
uint32_t RTR: 1; /*!< Remote transmission request bit.
It is used to distinguish between data frames and remote frames. */
uint32_t IDE: 1; /*!< Identifier extension flag.
It is used to distinguish between standard format and extended format.
This parameter can be 1 or 0. */
uint32_t RSVD: 4; /*!< Reserved bits. */
uint32_t TX: 1; /*!< This bit is set to 1 when receiving self-transmitted data in loopback mode. */
uint32_t ERRT: 3; /*!< Error type. */
uint32_t CYCLE_TIME: 16; /*!< Cycle time of time-triggered communication(TTC). */
};
};
uint8_t *pu8Data; /*!< Pointer to data filed of data frame. */
} stc_can_rx_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup CAN_Global_Macros CAN Global Macros
* @{
*/
/**
* @defgroup CAN_Work_Mode CAN Work Mode
* @{
*/
#define CAN_MODE_NORMAL (0U) /*!< Normal work mode. */
#define CAN_MODE_SILENT (1U) /*!< Silent work mode. Prohibit data transmission. */
#define CAN_MODE_ILB (2U) /*!< Internal loopback mode, just for self-test while developing. */
#define CAN_MODE_ELB (3U) /*!< External loopback mode, just for self-test while developing. */
#define CAN_MODE_ELB_SILENT (4U) /*!< External loppback silent mode, just for self-test while developing. \
It is forbidden to respond to received frames and error frames, but data can be transmitted. */
/**
* @}
*/
/**
* @defgroup CAN_Transmit_Buffer_Type CAN Transmit Buffer Type
* @{
*/
#define CAN_BUF_PTB (0U) /*!< Primary transmit buffer. */
#define CAN_BUF_STB (1U) /*!< Secondary transmit buffer. */
/**
* @}
*/
/**
* @defgroup CAN_DLC CAN Data_Length_Code
* @{
*/
#define CAN_DLC_0 (0x0U) /*!< CAN2.0 and CAN FD: payload is 0 in bytes. */
#define CAN_DLC_1 (0x1U) /*!< CAN2.0 and CAN FD: payload is 1 in bytes. */
#define CAN_DLC_2 (0x2U) /*!< CAN2.0 and CAN FD: payload is 2 in bytes. */
#define CAN_DLC_3 (0x3U) /*!< CAN2.0 and CAN FD: payload is 3 in bytes. */
#define CAN_DLC_4 (0x4U) /*!< CAN2.0 and CAN FD: payload is 4 in bytes. */
#define CAN_DLC_5 (0x5U) /*!< CAN2.0 and CAN FD: payload is 5 in bytes. */
#define CAN_DLC_6 (0x6U) /*!< CAN2.0 and CAN FD: payload is 6 in bytes. */
#define CAN_DLC_7 (0x7U) /*!< CAN2.0 and CAN FD: payload is 7 in bytes. */
#define CAN_DLC_8 (0x8U) /*!< CAN2.0 and CAN FD: payload is 8 in bytes. */
#define CAN_DLC_12 (0x9U) /*!< CAN FD: payload is 12 in bytes. CAN2.0: payload is 8 in bytes. */
#define CAN_DLC_16 (0xAU) /*!< CAN FD: payload is 16 in bytes. CAN2.0: payload is 8 in bytes. */
#define CAN_DLC_20 (0xBU) /*!< CAN FD: payload is 20 in bytes. CAN2.0: payload is 8 in bytes. */
#define CAN_DLC_24 (0xCU) /*!< CAN FD: payload is 24 in bytes. CAN2.0: payload is 8 in bytes. */
#define CAN_DLC_32 (0xDU) /*!< CAN FD: payload is 32 in bytes. CAN2.0: payload is 8 in bytes. */
#define CAN_DLC_48 (0xEU) /*!< CAN FD: payload is 48 in bytes. CAN2.0: payload is 8 in bytes. */
#define CAN_DLC_64 (0xFU) /*!< CAN FD: payload is 64 in bytes. CAN2.0: payload is 8 in bytes. */
/**
* @}
*/
/**
* @defgroup CAN_Trans_Mode CAN Transmission Mode
* @{
*/
#define CAN_TRANS_PTB_STB_AUTO_RETX (0x0U) /*!< Both PTB and STB automatically retransmit. */
#define CAN_TRANS_PTB_SSHOT (CAN_CFG_STAT_TPSS) /*!< PTB single shot transmission mode. */
#define CAN_TRANS_STB_SSHOT (CAN_CFG_STAT_TSSS) /*!< STB single shot transmission mode. */
#define CAN_TRANS_PTB_STB_SSHOT (CAN_CFG_STAT_TPSS | \
CAN_CFG_STAT_TSSS) /*!< STB single shot, PTB single shot. */
/**
* @}
*/
/**
* @defgroup CAN_STB_Trans_Control CAN STB Transmission Control
* @{
*/
#define CAN_STB_TRANS_ALL (0U) /*!< Transmit all of STB slots. */
#define CAN_STB_TRANS_ONE (1U) /*!< Transmit one STB slot. */
/**
* @}
*/
/**
* @defgroup CAN_STB_Priority_Mode CAN STB Priority Mode
* @{
*/
#define CAN_STB_PRIO_FIFO (0x0U) /*!< Data first in and first be transmitted. */
#define CAN_STB_PRIO_ID (CAN_TCTRL_TSMODE) /*!< Data with smallest ID first be transmitted. */
/**
* @}
*/
/**
* @defgroup CAN_TB_Status CAN Transmit Buffer Status
* @{
*/
#define CAN_TB_STAT_EMPTY (0x0U) /*!< TTCAN is disabled(TTEN == 0): STB is empty. \
TTCAN is disabled(TTEN == 1) and transmit buffer is specified by TBPTR and TTPTR(TTTBM == 1): \
PTB and STB are both empty. */
#define CAN_TB_STAT_LESS_HALF (0x1U) /*!< TTEN == 0: STB is not less than half full; \
TTEN == 1 && TTTBM == 1: PTB and STB are neither empty. */
#define CAN_TB_STAT_MORE_HALF (0x2U) /*!< TTEN == 0: STB is more than half full; \
TTEN == 1 && TTTBM == 1: reserved value. */
#define CAN_TB_STAT_FULL (0x3U) /*!< TTEN == 0: STB is full; \
TTEN == 1 && TTTBM == 1: PTB and STB are both full. */
/**
* @}
*/
/**
* @defgroup CAN_RB_Status CAN Receive Buffer Status
* @{
*/
#define CAN_RB_STAT_EMPTY (0x0U) /*!< Receive buffer(RB) is empty. */
#define CAN_RB_STAT_LESS_WARN_LIMIT (0x1U) /*!< RB is not empty, but is less than almost full warning limit. */
#define CAN_RB_STAT_MORE_WARN_LIMIT (0x2U) /*!< RB is not full, but is more than or equal to almost full warning limit. */
#define CAN_RB_STAT_FULL (0x3U) /*!< RB is full. */
/**
* @}
*/
/**
* @defgroup CAN_FD_Mode CAN FD Mode
* @{
*/
#define CAN_FD_MODE_BOSCH (0x0U)
#define CAN_FD_MODE_ISO_11898 (CAN_TCTRL_FD_ISO)
/**
* @}
*/
/**
* @defgroup CAN_RB_Store_Selection CAN Receive Buffer Store Selection
* @{
*/
#define CAN_RB_STORE_CORRECT_DATA (0x0U) /*!< Receive buffer stores correct data frames only. */
#define CAN_RB_STORE_ALL_DATA (CAN_RCTRL_RBALL) /*!< Receive buffer stores all data frames, includes error data. */
/**
* @}
*/
/**
* @defgroup CAN_RB_Overflow_Operation CAN Receive Buffer Overflow Operation
* @{
*/
#define CAN_RB_OVF_SAVE_NEW (0x0U) /*!< Saves the newly received data and the first received data will be overwritten. */
#define CAN_RB_OVF_DISCARD_NEW (CAN_RCTRL_ROM) /*!< Discard the newly received data. */
/**
* @}
*/
/**
* @defgroup CAN_Self_ACK_Command CAN Self ACK Command
* @{
*/
#define CAN_SELF_ACK_DISABLE (0x0U)
#define CAN_SELF_ACK_ENABLE (CAN_RCTRL_SACK)
/**
* @}
*/
/**
* @defgroup CAN_FD_TDC_Command CAN-FD Transmiter Delay Compensation Command
* @{
*/
#define CAN_FD_TDC_DISABLE (0x0U)
#define CAN_FD_TDC_ENABLE (CAN_TDC_TDCEN)
/**
* @}
*/
/**
* @defgroup CAN_Interrupt_Type CAN Interrupt Type
* @{
*/
#define CAN_INT_ERR_INT (1UL << 1U) /*!< Register bit RTIE.EIE. Error interrupt. */
#define CAN_INT_STB_TRANS_OK (1UL << 2U) /*!< Register bit RTIE.TSIE. Secondary transmit buffer was transmitted successfully. */
#define CAN_INT_PTB_TRANS_OK (1UL << 3U) /*!< Register bit RTIE.TPIE. Primary transmit buffer was transmitted successfully. */
#define CAN_INT_RB_ALMOST_FULL (1UL << 4U) /*!< Register bit RTIE.RAFIE. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */
#define CAN_INT_RB_FIFO_FULL (1UL << 5U) /*!< Register bit RTIE.RFIE. The FIFO of receive buffer is full. */
#define CAN_INT_RX_OVERRUN (1UL << 6U) /*!< Register bit RTIE.ROIE. Receive buffers are full and there is a further message to be stored. */
#define CAN_INT_RX (1UL << 7U) /*!< Register bit RTIE.RIE. Received a valid data frame or remote frame. */
#define CAN_INT_BUS_ERR (1UL << 9U) /*!< Register bit ERRINT.BEIE. Arbitration lost caused bus error */
#define CAN_INT_ARB_LOST (1UL << 11U) /*!< Register bit ERRINT.ALIE. Arbitration lost. */
#define CAN_INT_ERR_PASSIVE (1UL << 13U) /*!< Register bit ERRINT.EPIE. A change from error-passive to error-active or error-active to error-passive has occurred. */
#define CAN_INT_ALL (CAN_INT_ERR_INT | \
CAN_INT_STB_TRANS_OK | \
CAN_INT_PTB_TRANS_OK | \
CAN_INT_RB_ALMOST_FULL | \
CAN_INT_RB_FIFO_FULL | \
CAN_INT_RX_OVERRUN | \
CAN_INT_RX | \
CAN_INT_BUS_ERR | \
CAN_INT_ARB_LOST | \
CAN_INT_ERR_PASSIVE)
/**
* @}
*/
/**
* @defgroup CAN_Common_Status_Flag CAN Common Status Flag
* @{
*/
#define CAN_FLAG_BUS_OFF (1UL << 0U) /*!< Register bit CFG_STAT.BUSOFF. CAN bus off. */
#define CAN_FLAG_BUS_TX (1UL << 1U) /*!< Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. */
#define CAN_FLAG_BUS_RX (1UL << 2U) /*!< Register bit CFG_STAT.RACTIVE. CAN bus is receiving. */
#define CAN_FLAG_RB_OVF (1UL << 5U) /*!< Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost. */
#define CAN_FLAG_TB_FULL (1UL << 8U) /*!< Register bit RTIE.TSFF. Transmit buffers are all full. \
TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled. \
TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled.*/
#define CAN_FLAG_TRANS_ABORTED (1UL << 16U) /*!< Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. */
#define CAN_FLAG_ERR_INT (1UL << 17U) /*!< Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter and the \
set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than \
the set value to greater than the set value, or from greater than the set value to less than the set value. */
#define CAN_FLAG_STB_TRANS_OK (1UL << 18U) /*!< Register bit RTIF.TSIF. STB was transmitted successfully. */
#define CAN_FLAG_PTB_TRANS_OK (1UL << 19U) /*!< Register bit RTIF.TPIF. PTB was transmitted successfully. */
#define CAN_FLAG_RB_ALMOST_FULL (1UL << 20U) /*!< Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */
#define CAN_FLAG_RB_FIFO_FULL (1UL << 21U) /*!< Register bit RTIF.RFIF. The FIFO of receive buffer is full. */
#define CAN_FLAG_RX_OVERRUN (1UL << 22U) /*!< Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. */
#define CAN_FLAG_RX_OK (1UL << 23U) /*!< Register bit RTIF.RIF. Received a valid data frame or remote frame. */
#define CAN_FLAG_BUS_ERR (1UL << 24U) /*!< Register bit ERRINT.BEIF. Arbitration lost caused bus error. */
#define CAN_FLAG_ARB_LOST (1UL << 26U) /*!< Register bit ERRINT.ALIF. Arbitration lost. */
#define CAN_FLAG_ERR_PASSIVE (1UL << 28U) /*!< Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. */
#define CAN_FLAG_ERR_PASSIVE_NODE (1UL << 30U) /*!< Register bit ERRINT.EPASS. The node is an error-passive node. */
#define CAN_FLAG_REACH_WARN_LIMIT (1UL << 31U) /*!< Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. */
#define CAN_FLAG_ALL (CAN_FLAG_BUS_OFF | \
CAN_FLAG_BUS_TX | \
CAN_FLAG_BUS_RX | \
CAN_FLAG_RB_OVF | \
CAN_FLAG_TB_FULL | \
CAN_FLAG_TRANS_ABORTED | \
CAN_FLAG_ERR_INT | \
CAN_FLAG_STB_TRANS_OK | \
CAN_FLAG_PTB_TRANS_OK | \
CAN_FLAG_RB_ALMOST_FULL | \
CAN_FLAG_RB_FIFO_FULL | \
CAN_FLAG_RX_OVERRUN | \
CAN_FLAG_RX_OK | \
CAN_FLAG_BUS_ERR | \
CAN_FLAG_ARB_LOST | \
CAN_FLAG_ERR_PASSIVE | \
CAN_FLAG_ERR_PASSIVE_NODE | \
CAN_FLAG_REACH_WARN_LIMIT)
#define CAN_FLAG_CLR_MSK (CAN_FLAG_RB_OVF | \
CAN_FLAG_TRANS_ABORTED | \
CAN_FLAG_ERR_INT | \
CAN_FLAG_STB_TRANS_OK | \
CAN_FLAG_PTB_TRANS_OK | \
CAN_FLAG_RB_ALMOST_FULL | \
CAN_FLAG_RB_FIFO_FULL | \
CAN_FLAG_RX_OVERRUN | \
CAN_FLAG_RX_OK | \
CAN_FLAG_BUS_ERR | \
CAN_FLAG_ARB_LOST | \
CAN_FLAG_ERR_PASSIVE | \
CAN_FLAG_ERR_PASSIVE_NODE | \
CAN_FLAG_REACH_WARN_LIMIT)
#define CAN_FLAG_TX_ERR_MSK (CAN_FLAG_BUS_OFF | \
CAN_FLAG_TB_FULL | \
CAN_FLAG_ERR_INT | \
CAN_FLAG_BUS_ERR | \
CAN_FLAG_ARB_LOST | \
CAN_FLAG_ERR_PASSIVE | \
CAN_FLAG_ERR_PASSIVE_NODE | \
CAN_FLAG_REACH_WARN_LIMIT)
/**
* @}
*/
/**
* @defgroup CAN_AF_Mask_Type CAN AF Mask Type
* @{
*/
#define CAN_AF_MSK_STD_EXT (0x0U) /*!< Acceptance filter accept standard ID mask and extended ID mask. */
#define CAN_AF_MSK_STD (CAN_ACF_AIDEE) /*!< Acceptance filter accept standard ID mask. */
#define CAN_AF_MSK_EXT (CAN_ACF_AIDEE | \
CAN_ACF_AIDE) /*!< Acceptance filter accept extended ID mask. */
/**
* @}
*/
/**
* @defgroup CAN_Error_Type CAN Error Type
* @{
*/
#define CAN_ERR_NO (0U) /*!< No error. */
#define CAN_ERR_BIT (CAN_EALCAP_KOER_0) /*!< Error is bit error. */
#define CAN_ERR_FORM (CAN_EALCAP_KOER_1) /*!< Error is form error. */
#define CAN_ERR_STUFF (CAN_EALCAP_KOER_1 | \
CAN_EALCAP_KOER_0) /*!< Error is stuff error. */
#define CAN_ERR_ACK (CAN_EALCAP_KOER_2) /*!< Error is ACK error. */
#define CAN_ERR_CRC (CAN_EALCAP_KOER_2 | \
CAN_EALCAP_KOER_0) /*!< Error is CRC error. */
#define CAN_ERR_OTHER (CAN_EALCAP_KOER_2 | \
CAN_EALCAP_KOER_1) /*!< Error is other error. */
/**
* @}
*/
/**
* @defgroup CAN_AF CAN Acceptance Filter
* @{
*/
#define CAN_AF1 (CAN_ACFEN_AE_1) /*!< Acceptance filter 1 select bit. */
#define CAN_AF2 (CAN_ACFEN_AE_2) /*!< Acceptance filter 2 select bit. */
#define CAN_AF3 (CAN_ACFEN_AE_3) /*!< Acceptance filter 3 select bit. */
#define CAN_AF4 (CAN_ACFEN_AE_4) /*!< Acceptance filter 4 select bit. */
#define CAN_AF5 (CAN_ACFEN_AE_5) /*!< Acceptance filter 5 select bit. */
#define CAN_AF6 (CAN_ACFEN_AE_6) /*!< Acceptance filter 6 select bit. */
#define CAN_AF7 (CAN_ACFEN_AE_7) /*!< Acceptance filter 7 select bit. */
#define CAN_AF8 (CAN_ACFEN_AE_8) /*!< Acceptance filter 8 select bit. */
#define CAN_AF9 (CAN_ACFEN_AE_9) /*!< Acceptance filter 9 select bit. */
#define CAN_AF10 (CAN_ACFEN_AE_10) /*!< Acceptance filter 10 select bit. */
#define CAN_AF11 (CAN_ACFEN_AE_11) /*!< Acceptance filter 11 select bit. */
#define CAN_AF12 (CAN_ACFEN_AE_12) /*!< Acceptance filter 12 select bit. */
#define CAN_AF13 (CAN_ACFEN_AE_13) /*!< Acceptance filter 13 select bit. */
#define CAN_AF14 (CAN_ACFEN_AE_14) /*!< Acceptance filter 14 select bit. */
#define CAN_AF15 (CAN_ACFEN_AE_15) /*!< Acceptance filter 15 select bit. */
#define CAN_AF16 (CAN_ACFEN_AE_16) /*!< Acceptance filter 16 select bit. */
#define CAN_AF_ALL (0xFFFFU)
/**
* @}
*/
/**
* @defgroup CAN_TTC_Transmit_Buffer_Mode CAN Time-triggered Communication Transmit Buffer Mode
* @{
*/
#define CAN_TTC_TB_MODE_NORMAL (0x0U) /*!< TTC transmit buffer depends on the priority of STB which is defined by @ref CAN_STB_Priority_Mode */
#define CAN_TTC_TB_MODE_PTR (CAN_TCTRL_TTTBM) /*!< TTC transmit buffer is pointed by TBSLOT.TBPTR(for data filling) and \
TRG_CFG.TTPTR(for data transmission). */
/**
* @}
*/
/**
* @defgroup CAN_TTC_TBS_Pointer CAN Time-triggered Communication Transmit Buffer Slot Pointer
* @{
*/
#define CAN_TTC_TBS_PTB (0x0U) /*!< Point to PTB. */
#define CAN_TTC_TBS_STB1 (0x1U) /*!< Point to STB slot 1. */
#define CAN_TTC_TBS_STB2 (0x2U) /*!< Point to STB slot 2. */
#define CAN_TTC_TBS_STB3 (0x3U) /*!< Point to STB slot 3. */
/**
* @}
*/
/**
* @defgroup CAN_TTC_Status_Flag CAN Time-triggered Communication Status Flag
* @{
*/
#define CAN_TTC_FLAG_TTI (CAN_TTCFG_TTIF) /*!< Time trigger interrupt flag. */
#define CAN_TTC_FLAG_TEI (CAN_TTCFG_TEIF) /*!< Trigger error interrupt flag. */
#define CAN_TTC_FLAG_WTI (CAN_TTCFG_WTIF) /*!< Watch trigger interrupt flag. */
#define CAN_TTC_FLAG_ALL (CAN_TTC_FLAG_TTI | \
CAN_TTC_FLAG_TEI | \
CAN_TTC_FLAG_WTI)
/**
* @}
*/
/**
* @defgroup CAN_TTC_Interrupt_Type CAN Time-triggered Communication Interrupt Type
* @{
*/
#define CAN_TTC_INT_TTI (CAN_TTCFG_TTIE) /*!< Time trigger interrupt. */
#define CAN_TTC_INT_WTI (CAN_TTCFG_WTIE) /*!< Watch trigger interrupt. */
#define CAN_TTC_INT_ALL (CAN_TTC_INT_TTI | CAN_TTC_INT_WTI)
/**
* @}
*/
/**
* @defgroup CAN_TTC_NTU_Prescaler CAN Time-triggered Communication Network Time Unit Prescaler
* @{
*/
#define CAN_TTC_NTU_PRESC_1 (0x0U) /*!< NTU is SBT bit time * 1. */
#define CAN_TTC_NTU_PRESC_2 (CAN_TTCFG_T_PRESC_0) /*!< NTU is SBT bit time * 2. */
#define CAN_TTC_NTU_PRESC_4 (CAN_TTCFG_T_PRESC_1) /*!< NTU is SBT bit time * 4. */
#define CAN_TTC_NTU_PRESC_8 (CAN_TTCFG_T_PRESC_1 | \
CAN_TTCFG_T_PRESC_0) /*!< NTU is SBT bit time * 8. */
/**
* @}
*/
/**
* @defgroup CAN_TTC_Trigger_Type CAN Time-triggered Communication Trigger Type
* @{
*/
#define CAN_TTC_TRIG_IMMED_TRIG (0x0U) /*!< Immediate trigger for immediate transmission. */
#define CAN_TTC_TRIG_TIME_TRIG (CAN_TRG_CFG_TTYPE_0) /*!< Time trigger for receive triggers. */
#define CAN_TTC_TRIG_SSHOT_TRANS_TRIG (CAN_TRG_CFG_TTYPE_1) /*!< Single shot transmit trigger for exclusive time windows. */
#define CAN_TTC_TRIG_TRANS_START_TRIG (CAN_TRG_CFG_TTYPE_1 | \
CAN_TRG_CFG_TTYPE_0) /*!< Transmit start trigger for merged arbitrating time windows. */
#define CAN_TTC_TRIG_TRANS_STOP_TRIG (CAN_TRG_CFG_TTYPE_2) /*!< Transmit stop trigger for merged arbitrating time windows. */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup CAN_Global_Functions
* @{
*/
en_result_t CAN_Init(M4_CAN_TypeDef *CANx, const stc_can_init_t *pstcInit);
en_result_t CAN_StructInit(stc_can_init_t *pstcInit);
void CAN_DeInit(M4_CAN_TypeDef *CANx);
void CAN_SWReset(M4_CAN_TypeDef *CANx);
void CAN_EnterNormalComm(M4_CAN_TypeDef *CANx);
void CAN_SetWorkMode(M4_CAN_TypeDef *CANx, uint8_t u8WorkMode);
void CAN_SetTransMode(M4_CAN_TypeDef *CANx, uint8_t u8TransMode);
void CAN_SetSTBPrioMode(M4_CAN_TypeDef *CANx, uint8_t u8STBPrioMode);
void CAN_SetRBStoreSel(M4_CAN_TypeDef *CANx, uint8_t u8RBStoreSel);
void CAN_SetRBOvfOp(M4_CAN_TypeDef *CANx, uint8_t u8RBOvfOperation);
void CAN_IntCmd(M4_CAN_TypeDef *CANx, uint32_t u32IntType, en_functional_state_t enNewState);
en_result_t CAN_SBTConfig(M4_CAN_TypeDef *CANx, const stc_can_bt_cfg_t *pstcCfg);
uint8_t CAN_GetArbLostPos(const M4_CAN_TypeDef *CANx);
uint8_t CAN_GetErrType(const M4_CAN_TypeDef *CANx);
void CAN_SetRBSWarnLimit(M4_CAN_TypeDef *CANx, uint8_t u8RBSWarnLimit);
void CAN_SetErrWarnLimit(M4_CAN_TypeDef *CANx, uint8_t u8ErrWarnLimit);
uint8_t CAN_GetREC(const M4_CAN_TypeDef *CANx);
uint8_t CAN_GetTEC(const M4_CAN_TypeDef *CANx);
void CAN_ClrErrCount(M4_CAN_TypeDef *CANx);
en_result_t CAN_AFConfig(M4_CAN_TypeDef *CANx, uint16_t u16AFSel, const stc_can_af_cfg_t pstcAFCfg[]);
void CAN_AFCmd(M4_CAN_TypeDef *CANx, uint16_t u16AFSel, en_functional_state_t enNewState);
uint8_t CAN_GetTBType(const M4_CAN_TypeDef *CANx);
void CAN_AbortTrans(M4_CAN_TypeDef *CANx, uint8_t u8TBType);
en_flag_status_t CAN_GetStatus(const M4_CAN_TypeDef *CANx, uint32_t u32Flag);
void CAN_ClrStatus(M4_CAN_TypeDef *CANx, uint32_t u32Flag);
uint32_t CAN_GetStatusVal(const M4_CAN_TypeDef *CANx);
uint8_t CAN_GetTBFullStatus(const M4_CAN_TypeDef *CANx);
uint8_t CAN_GetRBFullStatus(const M4_CAN_TypeDef *CANx);
en_result_t CAN_FD_Config(M4_CAN_TypeDef *CANx, const stc_can_fd_cfg_t *pstcCfg);
en_result_t CAN_FD_StructInit(stc_can_fd_cfg_t *pstcCfg);
void CAN_FD_Cmd(const M4_CAN_TypeDef *CANx, en_functional_state_t enNewState);
en_result_t CAN_TTC_StructInit(stc_can_ttc_cfg_t *pstcCfg);
en_result_t CAN_TTC_Config(M4_CAN_TypeDef *CANx, const stc_can_ttc_cfg_t *pstcCfg);
void CAN_TTC_Cmd(M4_CAN_TypeDef *CANx, en_functional_state_t enNewState);
void CAN_TTC_SetTBSToBeFilled(M4_CAN_TypeDef *CANx, uint8_t u8SlotPtr);
void CAN_TTC_SetTBSFilled(M4_CAN_TypeDef *CANx);
void CAN_TTC_SetNTUPrescaler(M4_CAN_TypeDef *CANx, uint8_t u8NTUPrescaler);
void CAN_TTC_IntCmd(M4_CAN_TypeDef *CANx, uint8_t u8IntType, en_functional_state_t enNewState);
en_flag_status_t CAN_TTC_GetStatus(const M4_CAN_TypeDef *CANx, uint8_t u8Flag);
void CAN_TTC_ClrStatus(M4_CAN_TypeDef *CANx, uint8_t u8Flag);
uint8_t CAN_TTC_GetStatusVal(const M4_CAN_TypeDef *CANx);
void CAN_TTC_SetRefMsgID(M4_CAN_TypeDef *CANx, uint32_t u32ID);
void CAN_TTC_SetRefMsgIDE(M4_CAN_TypeDef *CANx, uint32_t u32IDE);
uint32_t CAN_TTC_GetRefMsgID(const M4_CAN_TypeDef *CANx);
uint32_t CAN_TTC_GetRefMsgIDE(const M4_CAN_TypeDef *CANx);
void CAN_TTC_SetTxTrigTBS(M4_CAN_TypeDef *CANx, uint8_t u8TBSlotPtr);
uint8_t CAN_TTC_GetTxTrigTBS(const M4_CAN_TypeDef *CANx);
void CAN_TTC_SetTrigType(M4_CAN_TypeDef *CANx, uint16_t u16TrigType);
uint16_t CAN_TTC_GetTrigType(const M4_CAN_TypeDef *CANx);
void CAN_TTC_SetTxEnableWindow(M4_CAN_TypeDef *CANx, uint16_t u16TxEnableWindow);
uint16_t CAN_TTC_GetTxEnableWindow(const M4_CAN_TypeDef *CANx);
void CAN_TTC_SetTxTrigTime(M4_CAN_TypeDef *CANx, uint16_t u16TxTrigTime);
uint16_t CAN_TTC_GetTxTrigTime(const M4_CAN_TypeDef *CANx);
void CAN_TTC_SetWatchTrigTime(M4_CAN_TypeDef *CANx, uint16_t u16WatchTrigTime);
uint16_t CAN_TTC_GetWatchTrigTime(const M4_CAN_TypeDef *CANx);
en_result_t CAN_TransData(M4_CAN_TypeDef *CANx, const stc_can_tx_t *pstcTx,
uint8_t u8TxBufType, uint8_t u8STBTxCtrl, uint32_t u32Timeout);
en_result_t CAN_TTC_TransData(M4_CAN_TypeDef *CANx, const stc_can_tx_t *pstcTx, uint8_t u8TBSlot);
en_result_t CAN_ReceiveData(M4_CAN_TypeDef *CANx, stc_can_rx_t *pstcRx, uint8_t *pu8RxFrameCnt, uint8_t u8RxFrameBufLength);
/**
* @}
*/
#endif /* DDL_CAN_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_CAN_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_cmp.h
* @brief Head file for CMP module.
*
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Heqb First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_CMP_H__
#define __HC32F4A0_CMP_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_CMP
* @{
*/
#if (DDL_CMP_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup CMP_Global_Types CMP Global Types
* @{
*/
/**
* @brief CMP configuration structure
*/
typedef struct
{
uint8_t u8CmpCh; /*!< Select the compare voltage channel for normal mode
@ref CMP_CVSL_Channal */
uint16_t u16CmpVol; /*!< Select the compare voltage source for normal mode
(Config the parameter when use CMP1 or CMP3)@ref CMP1_3_CVSL_Source */
uint8_t u8RefVol; /*!< Reference voltage for normal mode, @ref CMP_RVSL_Source*/
uint8_t u8OutPolarity; /*!< Output polarity select, @ref CMP_Out_Polarity_Select */
uint8_t u8OutDetectEdges; /*!< Output detecte edge, @ref CMP_Out_Detect_Edge */
uint8_t u8OutFilter; /*!< Output Filter, @ref CMP_Out_Filter */
}stc_cmp_init_t;
/**
* @brief CMP reference voltage for window mode configuration structure
*/
typedef struct
{
uint8_t u8CmpCh1; /*!< Select the compare voltage channel for window mode
@ref CMP_CVSL_Channal */
uint16_t u16CmpVol; /*!< Select the compare voltage source for window mode
(Config the parameter when use CMP1 or CMP3)@ref CMP1_3_CVSL_Source */
uint8_t u8CmpCh2; /*!< Select the compare voltage channel for window mode
@ref CMP_CVSL_Channal */
uint8_t u8WinVolLow; /*!< CMP reference low voltage for window mode
@ref CMP_RVSL_Source */
uint8_t u8WinVolHigh; /*!< CMP reference high voltage for window mode
@ref CMP_RVSL_Source */
}stc_cmp_win_ref_t;
/**
* @brief CMP timer windows function configuration structure
*/
typedef struct
{
uint16_t u16TWSelect; /*!< Timer window source select
@ref CMP_TimerWin_Select */
uint8_t u8TWOutLevel; /*!< Timer window mode output level
@ref CMP_TimerWin_output_Level*/
uint8_t u8TWInvalidLevel; /*!< Output level when timer window invalid
@ref CMP_TimerWin_Invalid_Level */
}stc_cmp_timerwindow_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup CMP_Global_Macros CMP Global Macros
* @{
*/
/** @defgroup CMP_Mode CMP compare mode
* @{
*/
#define CMP_MODE_NORMAL (0x00U) /*!< Normal mode */
#define CMP_MODE_WINDOW (CMP_MDR_CWDE) /*!< Window mode */
/**
* @}
*/
/** @defgroup CMP_CVSL_Channal CMP compare voltage channel selection
* @{
*/
#define CMP_CVSL_NONE (0x0U) /*!< No input compare voltage */
#define CMP_CVSL_INP1 (CMP_PMSR_CVSL_0) /*!< Select INP1 as compare voltage */
#define CMP_CVSL_INP2 (CMP_PMSR_CVSL_1) /*!< Select INP2 as compare voltage */
#define CMP_CVSL_INP3 (CMP_PMSR_CVSL_2) /*!< Select INP3 as compare voltage */
#define CMP_CVSL_INP4 (CMP_PMSR_CVSL_3) /*!< Select INP4 as compare voltage */
/**
* @}
*/
/** @defgroup CMP_RVSL_Source CMP reference voltage selection
* @{
*/
#define CMP_RVSL_NONE (0x0U) /*!< No input reference voltage */
#define CMP_RVSL_INM1 (CMP_PMSR_RVSL_0) /*!< Select INM1 as reference voltage */
#define CMP_RVSL_INM2 (CMP_PMSR_RVSL_1) /*!< Select INM2 as reference voltage */
#define CMP_RVSL_INM3 (CMP_PMSR_RVSL_2) /*!< Select INM3 as reference voltage */
#define CMP_RVSL_INM4 (CMP_PMSR_RVSL_3) /*!< Select INM4 as reference voltage */
/**
* @}
*/
/** @defgroup CMP1_3_CVSL_Source CMP1 CMP3 compare voltage selection
* @{
*/
#define CMP1_INP3_NONE (0x0U) /*!< No input voltage to CMP1 INP3 */
#define CMP1_INP3_CMP1_INP3 (CMP_VISR_P3SL_0) /*!< Select CMP1_INP3 as CMP1 INP3 input */
#define CMP1_INP3_CMP2_INP3 (CMP_VISR_P3SL_1) /*!< Select CMP2_INP3 as CMP1 INP3 input */
#define CMP1_INP2_NONE (0x0U) /*!< No input voltage to CMP1 INP2 */
#define CMP1_INP2_PGA1 (CMP_VISR_P2SL_0) /*!< Select PGA1 as CMP1 INP2 input */
#define CMP1_INP2_PGA2 (CMP_VISR_P2SL_1) /*!< Select PGA2 as CMP1 INP2 input */
#define CMP1_INP2_CMP1_INP2 (CMP_VISR_P2SL_2) /*!< Select CMP1_INP2 as CMP1 INP2 input */
#define CMP3_INP3_NONE (0x0U) /*!< No input voltage to CMP3 INP3 */
#define CMP3_INP3_CMP3_INP3 (CMP_VISR_P3SL_0) /*!< Select CMP3_INP3 as CMP3 INP3 input */
#define CMP3_INP3_CMP4_INP3 (CMP_VISR_P3SL_1) /*!< Select CMP4_INP3 as CMP3 INP3 input */
#define CMP3_INP2_NONE (0x0U) /*!< No input voltage to CMP3 INP2 */
#define CMP3_INP2_PGA3 (CMP_VISR_P2SL_0) /*!< Select PGA3 as CMP3 INP2 input */
#define CMP3_INP2_PGA4 (CMP_VISR_P2SL_1) /*!< Select PGA4 as CMP3 INP2 input */
#define CMP3_INP2_CMP3_INP2 (CMP_VISR_P2SL_2) /*!< Select CMP3_INP2 as CMp3 INP2 input */
/**
* @}
*/
/** @defgroup CMP_Out_Polarity_Select CMP output polarity selection
* @{
*/
#define CMP_OUT_REVERSE_OFF (0x0U) /*!< CMP output don't reverse */
#define CMP_OUT_REVERSE_ON (CMP_OCR_COPS) /*!< CMP output level reverse */
/**
* @}
*/
/** @defgroup CMP_Out_Detect_Edge CMP output detect edge selection
* @{
*/
#define CMP_DETECT_EDGS_NONE (0U) /*!< Do not detect edge */
#define CMP_DETECT_EDGS_RISING (1U << CMP_FIR_EDGS_POS) /*!< Detect rising edge */
#define CMP_DETECT_EDGS_FALLING (2U << CMP_FIR_EDGS_POS) /*!< Detect falling edge */
#define CMP_DETECT_EDGS_BOTH (3U << CMP_FIR_EDGS_POS) /*!< Detect rising and falling edges */
/**
* @}
*/
/** @defgroup CMP_Out_Filter CMP output filter configuration
* @{
*/
#define CMP_OUT_FILTER_NONE (0U) /*!< Do not filter */
#define CMP_OUT_FILTER_PCLK3 (1U) /*!< Use pclk3 */
#define CMP_OUT_FILTER_PCLK3_DIV8 (2U) /*!< Use pclk3/8 */
#define CMP_OUT_FILTER_PCLK3_DIV32 (3U) /*!< Use pclk3/32 */
/**
* @}
*/
/** @defgroup CMP_TimerWin_func CMP timer window function configuration
* @{
*/
#define CMP_TIMERWIN_OFF (0x0U) /*!< Disable Timer Window function */
#define CMP_TIMERWIN_ON (CMP_OCR_TWOE) /*!< Enable Timer Window function */
/**
* @}
*/
/** @defgroup CMP_TimerWin_Select CMP output timer window function control signal definition for CMP
* @{
*/
#define CMP_1_TIMERWIN_TIMA_1_PWM1 (CMP_TWSR_CTWS0) /*!< Selection TIMA_1_PWM1 as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIMA_3_PWM1 (CMP_TWSR_CTWS0) /*!< Selection TIMA_3_PWM1 as timer window signal for CMP2*/
#define CMP_3_TIMERWIN_TIMA_1_PWM1 (CMP_TWSR_CTWS0) /*!< Selection TIMA_1_PWM1 as timer window signal for CMP3*/
#define CMP_4_TIMERWIN_TIMA_2_PWM1 (CMP_TWSR_CTWS0) /*!< Selection TIMA_2_PWM1 as timer window signal for CMP4*/
#define CMP_1_TIMERWIN_TIMA_1_PWM2 (CMP_TWSR_CTWS1) /*!< Selection TIMA_1_PWM2 as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIMA_3_PWM2 (CMP_TWSR_CTWS1) /*!< Selection TIMA_3_PWM2 as timer window signal for CMP2*/
#define CMP_3_TIMERWIN_TIMA_1_PWM2 (CMP_TWSR_CTWS1) /*!< Selection TIMA_1_PWM2 as timer window signal for CMP3*/
#define CMP_4_TIMERWIN_TIMA_2_PWM2 (CMP_TWSR_CTWS1) /*!< Selection TIMA_2_PWM2 as timer window signal for CMP4*/
#define CMP_1_TIMERWIN_TIMA_1_PWM3 (CMP_TWSR_CTWS2) /*!< Selection TIMA_1_PWM3 as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIMA_3_PWM3 (CMP_TWSR_CTWS2) /*!< Selection TIMA_3_PWM3 as timer window signal for CMP2*/
#define CMP_3_TIMERWIN_TIMA_1_PWM3 (CMP_TWSR_CTWS2) /*!< Selection TIMA_1_PWM3 as timer window signal for CMP3*/
#define CMP_4_TIMERWIN_TIMA_2_PWM3 (CMP_TWSR_CTWS2) /*!< Selection TIMA_2_PWM3 as timer window signal for CMP3*/
#define CMP_1_TIMERWIN_TIMA_2_PWM1 (CMP_TWSR_CTWS3) /*!< Selection TIMA_2_PWM1 as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIMA_4_PWM1 (CMP_TWSR_CTWS3) /*!< Selection TIMA_4_PWM1 as timer window signal for CMP2 */
#define CMP_3_TIMERWIN_TIMA_3_PWM1 (CMP_TWSR_CTWS3) /*!< Selection TIMA_3_PWM1 as timer window signal for CMP3 */
#define CMP_4_TIMERWIN_TIMA_4_PWM1 (CMP_TWSR_CTWS3) /*!< Selection TIMA_4_PWM1 as timer window signal for CMP4 */
#define CMP_1_TIMERWIN_TIMA_2_PWM2 (CMP_TWSR_CTWS4) /*!< Selection TIMA_2_PWM2 as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIMA_4_PWM2 (CMP_TWSR_CTWS4) /*!< Selection TIMA_4_PWM2 as timer window signal for CMP2 */
#define CMP_3_TIMERWIN_TIMA_3_PWM2 (CMP_TWSR_CTWS4) /*!< Selection TIMA_3_PWM2 as timer window signal for CMP3 */
#define CMP_4_TIMERWIN_TIMA_4_PWM2 (CMP_TWSR_CTWS4) /*!< Selection TIMA_4_PWM2 as timer window signal for CMP4 */
#define CMP_1_TIMERWIN_TIMA_2_PWM3 (CMP_TWSR_CTWS5) /*!< Selection TIMA_2_PWM3 as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIMA_4_PWM3 (CMP_TWSR_CTWS5) /*!< Selection TIMA_4_PWM3 as timer window signal for CMP2 */
#define CMP_3_TIMERWIN_TIMA_3_PWM3 (CMP_TWSR_CTWS5) /*!< Selection TIMA_3_PWM3 as timer window signal for CMP3 */
#define CMP_4_TIMERWIN_TIMA_4_PWM3 (CMP_TWSR_CTWS5) /*!< Selection TIMA_4_PWM3 as timer window signal for CMP4 */
#define CMP_1_TIMERWIN_TIM6_1_PWMA (CMP_TWSR_CTWS6) /*!< Selection TIM6_1_PWMA as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIM6_5_PWMA (CMP_TWSR_CTWS6) /*!< Selection TIM6_5_PWMA as timer window signal for CMP2 */
#define CMP_3_TIMERWIN_TIM6_1_PWMB (CMP_TWSR_CTWS6) /*!< Selection TIM6_1_PWMB as timer window signal for CMP3 */
#define CMP_4_TIMERWIN_TIM6_5_PWMB (CMP_TWSR_CTWS6) /*!< Selection TIM6_5_PWMB as timer window signal for CMP4 */
#define CMP_1_TIMERWIN_TIM6_2_PWMA (CMP_TWSR_CTWS7) /*!< Selection TIM6_2_PWMA as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIM6_6_PWMA (CMP_TWSR_CTWS7) /*!< Selection TIM6_6_PWMA as timer window signal for CMP2 */
#define CMP_3_TIMERWIN_TIM6_2_PWMB (CMP_TWSR_CTWS7) /*!< Selection TIM6_2_PWMB as timer window signal for CMP3 */
#define CMP_4_TIMERWIN_TIM6_6_PWMB (CMP_TWSR_CTWS7) /*!< Selection TIM6_6_PWMB as timer window signal for CMP4 */
#define CMP_1_TIMERWIN_TIM6_3_PWMA (CMP_TWSR_CTWS8) /*!< Selection TIM6_3_PWMA as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIM6_7_PWMA (CMP_TWSR_CTWS8) /*!< Selection TIM6_7_PWMA as timer window signal for CMP2 */
#define CMP_3_TIMERWIN_TIM6_3_PWMB (CMP_TWSR_CTWS8) /*!< Selection TIM6_3_PWMB as timer window signal for CMP3 */
#define CMP_4_TIMERWIN_TIM6_7_PWMB (CMP_TWSR_CTWS8) /*!< Selection TIM6_7_PWMB as timer window signal for CMP4 */
#define CMP_1_TIMERWIN_TIM6_4_PWMA (CMP_TWSR_CTWS9) /*!< Selection TIM6_4_PWMA as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIM6_8_PWMA (CMP_TWSR_CTWS9) /*!< Selection TIM6_8_PWMA as timer window signal for CMP2 */
#define CMP_3_TIMERWIN_TIM6_4_PWMB (CMP_TWSR_CTWS9) /*!< Selection TIM6_4_PWMB as timer window signal for CMP3 */
#define CMP_4_TIMERWIN_TIM6_8_PWMB (CMP_TWSR_CTWS9) /*!< Selection TIM6_8_PWMB as timer window signal for CMP4 */
#define CMP_1_TIMERWIN_TIM4_1_OUH (CMP_TWSR_CTWS10) /*!< Selection TIM4_1_OUH as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIM4_2_OUH (CMP_TWSR_CTWS10) /*!< Selection TIM4_2_OUH as timer window signal for CMP2 */
#define CMP_3_TIMERWIN_TIM4_3_OUH (CMP_TWSR_CTWS10) /*!< Selection TIM4_3_OUH as timer window signal for CMP3 */
#define CMP_4_TIMERWIN_TIM4_3_OUH (CMP_TWSR_CTWS10) /*!< Selection TIM4_4_OUH as timer window signal for CMP4 */
#define CMP_1_TIMERWIN_TIM4_1_OUL (CMP_TWSR_CTWS11) /*!< Selection TIM4_1_OUL as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIM4_2_OUL (CMP_TWSR_CTWS11) /*!< Selection TIM4_2_OUL as timer window signal for CMP2 */
#define CMP_3_TIMERWIN_TIM4_3_OUL (CMP_TWSR_CTWS11) /*!< Selection TIM4_3_OUL as timer window signal for CMP3 */
#define CMP_4_TIMERWIN_TIM4_3_OUL (CMP_TWSR_CTWS11) /*!< Selection TIM4_4_OUL as timer window signal for CMP4 */
#define CMP_1_TIMERWIN_TIM4_1_OVH (CMP_TWSR_CTWS12) /*!< Selection TIM4_1_OVH as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIM4_2_OVH (CMP_TWSR_CTWS12) /*!< Selection TIM4_2_OVH as timer window signal for CMP2 */
#define CMP_3_TIMERWIN_TIM4_3_OVH (CMP_TWSR_CTWS12) /*!< Selection TIM4_3_OVH as timer window signal for CMP3 */
#define CMP_4_TIMERWIN_TIM4_3_OVH (CMP_TWSR_CTWS12) /*!< Selection TIM4_4_OVH as timer window signal for CMP4 */
#define CMP_1_TIMERWIN_TIM4_1_OVL (CMP_TWSR_CTWS13) /*!< Selection TIM4_1_OVL as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIM4_2_OVL (CMP_TWSR_CTWS13) /*!< Selection TIM4_2_OVL as timer window signal for CMP2 */
#define CMP_3_TIMERWIN_TIM4_3_OVL (CMP_TWSR_CTWS13) /*!< Selection TIM4_3_OVL as timer window signal for CMP3 */
#define CMP_4_TIMERWIN_TIM4_3_OVL (CMP_TWSR_CTWS13) /*!< Selection TIM4_4_OVL as timer window signal for CMP4 */
#define CMP_1_TIMERWIN_TIM4_1_OWH (CMP_TWSR_CTWS14) /*!< Selection TIM4_1_OWH as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIM4_2_OWH (CMP_TWSR_CTWS14) /*!< Selection TIM4_2_OWH as timer window signal for CMP2 */
#define CMP_3_TIMERWIN_TIM4_3_OWH (CMP_TWSR_CTWS14) /*!< Selection TIM4_3_OWH as timer window signal for CMP3 */
#define CMP_4_TIMERWIN_TIM4_3_OWH (CMP_TWSR_CTWS14) /*!< Selection TIM4_4_OWH as timer window signal for CMP4 */
#define CMP_1_TIMERWIN_TIM4_1_OWL (CMP_TWSR_CTWS15) /*!< Selection TIM4_1_OWL as timer window signal for CMP1 */
#define CMP_2_TIMERWIN_TIM4_2_OWL (CMP_TWSR_CTWS15) /*!< Selection TIM4_2_OWL as timer window signal for CMP2 */
#define CMP_3_TIMERWIN_TIM4_3_OWL (CMP_TWSR_CTWS15) /*!< Selection TIM4_3_OWL as timer window signal for CMP3 */
#define CMP_4_TIMERWIN_TIM4_3_OWL (CMP_TWSR_CTWS15) /*!< Selection TIM4_4_OWL as timer window signal for CMP4 */
/**
* @}
*/
/** @defgroup CMP_TimerWin_Invalid_Level CMP output level when timer window invalid
* @{
*/
#define CMP_TIMERWIN_INVALID_LEVEL_LOW (0x0U) /*!< Output Low when timer window invalid */
#define CMP_TIMERWIN_INVALID_LEVEL_HIGH (CMP_OCR_TWOL) /*!< Output High when timer window invalid */
/**
* @}
*/
/** @defgroup CMP_TimerWin_output_Level CMP output level in timer windows mode
* @{
*/
#define CMP_TIMERWIN_OUT_LEVEL_LOW (0U) /*!< Output Low in timer windows mode */
#define CMP_TIMERWIN_OUT_LEVEL_HIGH (1U) /*!< Output High in timer windows mode */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup CMP_Global_Functions
* @{
*/
en_result_t CMP_StructInit(stc_cmp_init_t *pstcCMP_InitStruct);
en_result_t CMP_NormalModeInit(M4_CMP_TypeDef *CMPx,
const stc_cmp_init_t *pstcCmpInit);
en_result_t CMP_WindowModeInit(const M4_CMP_TypeDef *CMPx,
const stc_cmp_init_t *pstcCmpInit,
const stc_cmp_win_ref_t *pstcCmpWinRef);
en_result_t CMP_TimerWindowConfig(M4_CMP_TypeDef *CMPx,
const stc_cmp_timerwindow_t *pstcCMP_TimerWinStruct);
void CMP_FuncCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus);
void CMP_IntCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus);
void CMP_OutputCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus);
void CMP_VCOUTCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus);
void CMP_SetOutDetectEdges(M4_CMP_TypeDef *CMPx, uint8_t u8CmpEdges);
void CMP_SetOutputFilter(M4_CMP_TypeDef *CMPx, uint8_t u8CmpFilter);
void CMP_SetOutputPolarity(M4_CMP_TypeDef *CMPx, uint8_t u8CmpPolarity);
void CMP_SetCompareVol(M4_CMP_TypeDef *CMPx, uint8_t u8CmpCh, uint8_t u8CmpVol);
void CMP_SetRefVol(M4_CMP_TypeDef *CMPx, uint8_t u8RefVol);
void CMP_DeInit(M4_CMP_TypeDef *CMPx);
void CMP_SetTimerWinSignal(M4_CMP_TypeDef *CMPx, \
uint16_t u16TWSignal, en_functional_state_t enNewStatus);
en_flag_status_t CMP_GetResult(const M4_CMP_TypeDef *CMPx);
/**
* @}
*/
#endif /* DDL_CMP_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_CMP_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_crc.h
* @brief This file contains all the functions prototypes of the CRC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Heqb First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_CRC_H__
#define __HC32F4A0_CRC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_CRC
* @{
*/
#if (DDL_CRC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/* Bits definitions of CRC control register(CRC_CR). */
/**
* @defgroup CRC_Global_Macros CRC Global Macros
* @{
*/
/**
* @defgroup CRC_Protocol_Control_Bit CRC Protocol Control Bit
* @note: - CRC16 polynomial is X16 + X12 + X5 + 1
* - CRC32 polynomial is X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + \
* X8 + X7 + X5 + X4 + X2 + X + 1
* @{
*/
#define CRC_CRC16 (0x0UL)
#define CRC_CRC32 (CRC_CR_CR)
/**
* @}
*/
/**
* @defgroup CRC_Flag_Bit_Mask CRC Flag Bit Mask
* @{
*/
#define CRC_FLAG_MASK (CRC_CR_FLAG)
/**
* @}
*/
/**
* @defgroup CRC_Bit_Width CRC Bit Width
* @{
*/
#define CRC_BW_8 (8U)
#define CRC_BW_16 (16U)
#define CRC_BW_32 (32U)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup CRC_Global_Functions
* @{
*/
uint32_t CRC_Calculate(uint32_t u32CrcProtocol,
const void *pvData,
uint32_t u32InitVal,
uint32_t u32Length,
uint8_t u8BitWidth);
en_flag_status_t CRC_Check(uint32_t u32CrcProtocol,
uint32_t u32CheckSum,
const void *pvData,
uint32_t u32InitVal,
uint32_t u32Length,
uint8_t u8BitWidth);
/**
* @}
*/
#endif /* DDL_CRC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_CRC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_ctc.h
* @brief This file contains all the functions prototypes of the Clock Trimming
* Controller(CTC) driver library.
@verbatim
Change Logs:
Date Author Notes
2020-09-01 Hongjh First version
2020-10-30 Hongjh Refine CTC initialization structure
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_CTC_H__
#define __HC32F4A0_CTC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_CTC
* @{
*/
#if (DDL_CTC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup CTC_Global_Types CTC Global Types
* @{
*/
/**
* @brief CTC initialization structure definition
*/
typedef struct
{
uint32_t u32RefClockFreq; /*!< Reference clock frequency
This parameter should refer user manual recommended values */
uint32_t u32RefClockSrc; /*!< Reference clock source selection
This parameter can be a value of @ref CTC_Reference_Clock_Source */
uint32_t u32RefClockDiv; /*!< Reference clock division
This parameter can be a value of @ref CTC_Reference_Clock_Division */
float32_t f32ToleranceDeviation; /*!< CTC Tolerance bias.
This parameter can be a value between Min_Data=0.0 and Max_Data=1.0(100%) */
uint32_t u32TrimValue; /*!< CTC TRMVAL value
This parameter can be a value between Min_Data=0 and Max_Data=0x3F */
} stc_ctc_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup CTC_Global_Macros CTC Global Macros
* @{
*/
/**
* @defgroup CTC_Reference_Clock_Source CTC Reference Clock Source
* @{
*/
#define CTC_REF_CLK_CTCREF (0UL) /*!< Clock source: CTCREF */
#define CTC_REF_CLK_XTAL32 (CTC_CR1_REFCKS_1) /*!< Clock source: XTAL32 */
#define CTC_REF_CLK_XTAL (CTC_CR1_REFCKS) /*!< Clock source: XTAL */
/**
* @}
*/
/**
* @defgroup CTC_Tolerance_Deviation_Max CTC Tolerance Deviation Max
* @{
*/
#define CTC_TOLERANCE_DEVIATION_MAX (1.0F)
/**
* @}
*/
/**
* @defgroup CTC_Flag CTC Flag
* @{
*/
#define CTC_FLAG_TRIM_OK (CTC_STR_TRIMOK) /*!< Trimming OK flag */
#define CTC_FLAG_TRIM_OVF (CTC_STR_TRMOVF) /*!< Trimming overflow flag */
#define CTC_FLAG_TRIM_UDF (CTC_STR_TRMUDF) /*!< Trimming underflow flag */
#define CTC_FLAG_BUSY (CTC_STR_CTCBSY) /*!< CTC busy flag */
#define CTC_FLAG_ALL (CTC_FLAG_TRIM_OK | \
CTC_FLAG_TRIM_OVF | \
CTC_FLAG_TRIM_UDF | \
CTC_FLAG_BUSY)
/**
* @}
*/
/**
* @defgroup CTC_Reference_Clock_Division CTC Reference Clock Division
* @{
*/
#define CTC_REF_CLK_DIV8 (0UL) /*!< REFCLK/8 */
#define CTC_REF_CLK_DIV32 (1UL) /*!< REFCLK/32 */
#define CTC_REF_CLK_DIV128 (2UL) /*!< REFCLK/128 */
#define CTC_REF_CLK_DIV256 (3UL) /*!< REFCLK/256 */
#define CTC_REF_CLK_DIV512 (4UL) /*!< REFCLK/512 */
#define CTC_REF_CLK_DIV1024 (5UL) /*!< REFCLK/1024 */
#define CTC_REF_CLK_DIV2048 (6UL) /*!< REFCLK/2048 */
#define CTC_REF_CLK_DIV4096 (7UL) /*!< REFCLK/4096 */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup CTC_Global_Functions
* @{
*/
/**
* @brief Start CTC trimming.
* @param None
* @retval None
*/
__STATIC_INLINE void CTC_Start(void)
{
WRITE_REG32(bM4_CTC->CR1_b.CTCEN, 1UL);
}
/**
* @brief Stop CTC trimming.
* @param None
* @retval None
*/
__STATIC_INLINE void CTC_Stop(void)
{
WRITE_REG32(bM4_CTC->CR1_b.CTCEN, 0UL);
}
en_result_t CTC_Init(const stc_ctc_init_t *pstcCtcInit);
en_result_t CTC_StructInit(stc_ctc_init_t *pstcCtcInit);
en_result_t CTC_DeInit(void);
void CTC_SetRefClockDiv(uint32_t u32Div);
void CTC_SetRefClockSrc(uint32_t u32ClockSrc);
void CTC_IntCmd(en_functional_state_t enNewState);
en_flag_status_t CTC_GetStatus(uint32_t u32Flag);
void CTC_SetTrimValue(uint32_t u32TrimValue);
uint32_t CTC_GetTrimValue(void);
void CTC_SetReloadValue(uint32_t u32ReloadValue);
uint16_t CTC_GetReloadValue(void);
void CTC_SetOffsetValue(uint32_t u32OffsetValue);
uint32_t CTC_GetOffsetValue(void);
/**
* @}
*/
#endif /* DDL_CTC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_CTC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_dac.h
* @brief This file contains all the functions prototypes of the DAC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hexiao First version
2020-07-15 Hexiao 1. Modify DAC_ChannelCmd to DAC_Start and DAC_Stop
2. Modify DAC_DualChannelCmd to DAC_DualChannelStart
and DAC_DualChannelStop
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_DAC_H__
#define __HC32F4A0_DAC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
#include "hc32f4a0_utility.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_DAC
* @{
*/
#if (DDL_DAC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup DAC_Global_Types DAC Global Types
* @{
*/
/**
* @brief Structure definition of DAC initialization.
*/
typedef struct
{
uint16_t u16Src; /*!< Data source to be converted
This parameter can be a value of @ref DAC_DATA_SRC */
en_functional_state_t enOutput; /*!< Enable or disable analog output
This parameter can be a value of @ref en_functional_state_t */
} stc_dac_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup DAC_Global_Macros DAC Global Macros
* @{
*/
/**
* @defgroup DAC_CH DAC channel
* @{
*/
#define DAC_CH_1 (0U)
#define DAC_CH_2 (1U)
/**
* @}
*/
/**
* @defgroup DAC_DATA_SRC DAC data source
* @{
*/
#define DAC_DATA_SRC_DATAREG (0U)
#define DAC_DATA_SRC_DCU (1U)
/**
* @}
*/
/**
* @defgroup DAC_DATAREG_ALIGN_PATTERN DAC data register alignment pattern
* @{
*/
#define DAC_DATA_ALIGN_L (DAC_DACR_DPSEL)
#define DAC_DATA_ALIGN_R (0U)
/**
* @}
*/
#define DAC_DATAREG_VALUE_MAX (4096UL)
/**
* @defgroup DAC_ADP_SELECT DAC ADCx priority select
* @{
*/
#define DAC_ADP_SELECT_ADC1 (DAC_DAADPCR_ADPSL1)
#define DAC_ADP_SELECT_ADC2 (DAC_DAADPCR_ADPSL2)
#define DAC_ADP_SELECT_ADC3 (DAC_DAADPCR_ADPSL3)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup DAC_Global_Functions
* @{
*/
en_result_t DAC_StructInit(stc_dac_init_t * pstcInit);
en_result_t DAC_Init(M4_DAC_TypeDef *DACx, uint16_t u16Ch, const stc_dac_init_t *pstcInit);
void DAC_DeInit(M4_DAC_TypeDef *DACx);
void DAC_SetDataSource(M4_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Src);
void DAC_DataRegAlignConfig(M4_DAC_TypeDef *DACx, uint16_t u16Align);
void DAC_OutputCmd(M4_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState);
en_result_t DAC_AMPCmd(M4_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState);
void DAC_ADCPrioCmd(M4_DAC_TypeDef *DACx, en_functional_state_t enNewState);
void DAC_ADCPrioConfig(M4_DAC_TypeDef *DACx, uint16_t u16ADCxPrio, en_functional_state_t enNewState);
en_result_t DAC_Start(M4_DAC_TypeDef *DACx, uint16_t u16Ch);
en_result_t DAC_Stop(M4_DAC_TypeDef *DACx, uint16_t u16Ch);
void DAC_DualChannelStart(M4_DAC_TypeDef *DACx);
void DAC_DualChannelStop(M4_DAC_TypeDef *DACx);
void DAC_SetChannel1Data(M4_DAC_TypeDef *DACx, uint16_t data);
void DAC_SetChannel2Data(M4_DAC_TypeDef *DACx, uint16_t data);
void DAC_SetDualChannelData(M4_DAC_TypeDef *DACx, uint16_t data2, uint16_t data1);
en_result_t DAC_GetChannel1ConvState(const M4_DAC_TypeDef *DACx);
en_result_t DAC_GetChannel2ConvState(const M4_DAC_TypeDef *DACx);
/**
* @}
*/
#endif /* DDL_DAC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_DAC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_dcu.h
* @brief This file contains all the functions prototypes of the DCU(Data
* Computing Unit) driver library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hongjh First version
2020-07-23 Hongjh 1. Correct the macro define: DCU_CMP_TRIG_DATA01;
2. Refine the macro define for interrupt, flag and mode;
3. Modify API: from DCU_IntFuncCmd to DCU_GlobalIntCmd;
4. Delete API: DCU_SetCmpIntMode;
5. Modify DCU DATA read/write API.
2020-09-07 Hongjh Refine API: DCU_SetTriggerSrc
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_DCU_H__
#define __HC32F4A0_DCU_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_DCU
* @{
*/
#if (DDL_DCU_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup DCU_Global_Types DCU Global Types
* @{
*/
/**
* @brief DCU initialization structure definition
*/
typedef struct
{
uint32_t u32IntEn; /*!< Select DCU interrupt function.
This parameter can be a value of @ref DCU_Interrupt_Configure */
uint32_t u32DataSize; /*!< Specifies DCU data size.
This parameter can be a value of @ref DCU_Data_Size */
uint32_t u32Mode; /*!< Specifies DCU operation.
This parameter can be a value of @ref DCU_Mode */
uint32_t u32CmpTriggerMode; /*!< Specifies DCU compare operation trigger mode size.
This parameter can be a value of @ref DCU_Compare_Trigger_Mode */
} stc_dcu_init_t;
/**
* @brief DCU wave output configure structure definition
*/
typedef struct
{
uint32_t u32LowerLimit; /*!< Defines the wave lower limit of the wave amplitude.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */
uint32_t u32UpperLimit; /*!< Defines the upper limit of the wave amplitude.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */
uint32_t u32Step; /*!< Defines the increasing/decreasing step.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */
} stc_dcu_wave_cfg_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup DCU_Global_Macros DCU Global Macros
* @{
*/
/**
* @defgroup DCU_Data_Size DCU Data Size
* @{
*/
#define DCU_DATA_SIZE_8BIT (0UL) /*!< DCU data size: 8 bit */
#define DCU_DATA_SIZE_16BIT (DCU_CTL_DATASIZE_0) /*!< DCU data size: 16 bit */
#define DCU_DATA_SIZE_32BIT (DCU_CTL_DATASIZE_1) /*!< DCU data size: 32 bit */
/**
* @}
*/
/**
* @defgroup DCU_Compare_Trigger_Mode DCU Compare Trigger Mode
* @{
*/
#define DCU_CMP_TRIG_DATA0 (0UL) /*!< DCU compare triggered by DATA0 */
#define DCU_CMP_TRIG_DATA012 (DCU_CTL_COMP_TRG) /*!< DCU compare triggered by DATA0 or DATA1 or DATA2 */
/**
* @}
*/
/**
* @defgroup DCU_Mode DCU Mode
* @{
*/
#define DCU_INVALID (0UL) /*!< DCU invalid */
#define DCU_ADD (DCU_CTL_MODE_0) /*!< DCU add operation */
#define DCU_SUB (DCU_CTL_MODE_1) /*!< DCU sub operation */
#define DCU_HW_ADD (DCU_CTL_MODE_1 | \
DCU_CTL_MODE_0) /*!< Hardware trigger DCU add */
#define DCU_HW_SUB (DCU_CTL_MODE_2) /*!< Hardware trigger DCU sub */
#define DCU_CMP (DCU_CTL_MODE_2 | \
DCU_CTL_MODE_0) /*!< DCU compare */
#define DCU_TRIANGLE_WAVE (DCU_CTL_MODE_3) /*!< DCU triangle wave output mode */
#define DCU_SAWTOOTH_WAVE_INC (DCU_CTL_MODE_3 | \
DCU_CTL_MODE_0) /*!< DCU increasing sawtooth wave output mode */
#define DCU_SAWTOOTH_WAVE_DEC (DCU_CTL_MODE_3 | \
DCU_CTL_MODE_1) /*!< DCU decreasing sawtooth wave output mode */
/**
* @}
*/
/**
* @defgroup DCU_Interrupt_Configure DCU Interrupt Configure
* @{
*/
#define DCU_INT_DISABLE (0UL) /*!< Disable DCU interrupt */
#define DCU_INT_ENABLE (DCU_CTL_INTEN) /*!< Enable DCU interrupt */
/**
* @}
*/
/**
* @defgroup DCU_Flag DCU Flag
* @{
*/
#define DCU_FLAG_OPERATION (DCU_FLAG_FLAG_OP) /*!< DCU addition overflow or subtraction underflow flag */
#define DCU_FLAG_DATA0_LS_DATA2 (DCU_FLAG_FLAG_LS2) /*!< DCU DATA0 < DATA2 flag */
#define DCU_FLAG_DATA0_EQ_DATA2 (DCU_FLAG_FLAG_EQ2) /*!< DCU DATA0 = DATA2 flag */
#define DCU_FLAG_DATA0_GT_DATA2 (DCU_FLAG_FLAG_GT2) /*!< DCU DATA0 > DATA2 flag */
#define DCU_FLAG_DATA0_LS_DATA1 (DCU_FLAG_FLAG_LS1) /*!< DCU DATA0 < DATA1 flag */
#define DCU_FLAG_DATA0_EQ_DATA1 (DCU_FLAG_FLAG_EQ1) /*!< DCU DATA0 = DATA1 flag */
#define DCU_FLAG_DATA0_GT_DATA1 (DCU_FLAG_FLAG_GT1) /*!< DCU DATA0 > DATA1 flag */
#define DCU_FLAG_WAVE_SAWTOOTH_RELOAD (DCU_FLAG_FLAG_RLD) /*!< DCU sawtooth wave mode reload interrupt */
#define DCU_FLAG_WAVE_TRIANGLE_BOTTOM (DCU_FLAG_FLAG_BTM) /*!< DCU triangle wave mode bottom interrupt */
#define DCU_FLAG_WAVE_TRIANGLE_TOP (DCU_FLAG_FLAG_TOP) /*!< DCU triangle wave mode top interrupt */
/**
* @}
*/
/**
* @defgroup DCU_Interrupt_Category DCU Interrupt Category
* @{
*/
#define DCU_INT_OP (0UL) /*!< DCU operation result(overflow/underflow) interrupt */
#define DCU_INT_WAVE_MD (1UL) /*!< DCU wave mode(sawtooth/triangle wave mode) interrupt */
#define DCU_INT_CMP_WIN (2UL) /*!< DCU comparison(window) interrupt */
#define DCU_INT_CMP_NON_WIN (3UL) /*!< DCU comparison(non-window) interrupt */
/**
* @}
*/
/**
* @defgroup DCU_Interrupt_Type DCU Interrupt Type
* @{
*/
/**
* @defgroup DCU_Compare_Interrupt DCU Compare(Non-window) Interrupt
* @{
* @note Compare interrupt selection is valid only when select DCU comparison(non-window) interrupt(DCU_INTSEL.INT_WIN=0) under DCU compare mode
*/
#define DCU_INT_CMP_DATA0_LS_DATA2 (DCU_INTEVTSEL_SEL_LS2) /*!< DCU DATA0 < DATA2 interrupt */
#define DCU_INT_CMP_DATA0_EQ_DATA2 (DCU_INTEVTSEL_SEL_EQ2) /*!< DCU DATA0 = DATA2 interrupt */
#define DCU_INT_CMP_DATA0_GT_DATA2 (DCU_INTEVTSEL_SEL_GT2) /*!< DCU DATA0 > DATA2 interrupt */
#define DCU_INT_CMP_DATA0_LS_DATA1 (DCU_INTEVTSEL_SEL_LS1) /*!< DCU DATA0 < DATA1 interrupt */
#define DCU_INT_CMP_DATA0_EQ_DATA1 (DCU_INTEVTSEL_SEL_EQ1) /*!< DCU DATA0 = DATA1 interrupt */
#define DCU_INT_CMP_DATA0_GT_DATA1 (DCU_INTEVTSEL_SEL_GT1) /*!< DCU DATA0 > DATA1 interrupt */
#define DCU_INT_CMP_NON_WIN_ALL (DCU_INT_CMP_DATA0_LS_DATA2 | \
DCU_INT_CMP_DATA0_EQ_DATA2 | \
DCU_INT_CMP_DATA0_GT_DATA2 | \
DCU_INT_CMP_DATA0_LS_DATA1 | \
DCU_INT_CMP_DATA0_EQ_DATA1 | \
DCU_INT_CMP_DATA0_GT_DATA1)
/**
* @}
*/
/**
* @defgroup DCU_Window_Compare_Interrupt DCU Window Compare Interrupt
* @{
*/
#define DCU_INT_CMP_WIN_INSIDE (DCU_INTEVTSEL_SEL_WIN_0) /*!< DCU comparison(DATA2 <= DATA0 <= DATA1) interrupt */
#define DCU_INT_CMP_WIN_OUTSIDE (DCU_INTEVTSEL_SEL_WIN_1) /*!< DCU comparison(DATA0 < DATA2 & DATA0 > DATA1 ) interrupt */
#define DCU_INT_CMP_WIN_ALL (DCU_INT_CMP_WIN_INSIDE | \
DCU_INT_CMP_WIN_OUTSIDE)
/**
* @}
*/
/**
* @defgroup DCU_Wave_Mode_Interrupt DCU Wave Mode Interrupt
* @{
*/
#define DCU_INT_WAVE_SAWTOOTH_RELOAD (DCU_INTEVTSEL_SEL_RLD) /*!< DCU sawtooth wave mode reload interrupt */
#define DCU_INT_WAVE_TRIANGLE_BOTTOM (DCU_INTEVTSEL_SEL_BTM) /*!< DCU triangle wave mode bottom interrupt */
#define DCU_INT_WAVE_TRIANGLE_TOP (DCU_INTEVTSEL_SEL_TOP) /*!< DCU triangle wave mode top interrupt */
#define DCU_INT_WAVE_MD_ALL (DCU_INT_WAVE_TRIANGLE_TOP |\
DCU_INT_WAVE_TRIANGLE_BOTTOM |\
DCU_INT_WAVE_SAWTOOTH_RELOAD)
/**
* @}
*/
/**
* @defgroup DCU_Operation_Interrupt DCU Operation Interrupt
* @{
*/
#define DCU_INT_OP_UDF_OVF (DCU_INTEVTSEL_SEL_OP) /*!< DCU addition overflow or subtraction underflow interrupt */
/**
* @}
*/
/**
* @}
*/
/**
* @defgroup DCU_Data_Register_Index DCU Data Register Index
* @{
*/
#define DCU_DATA0_IDX (0UL) /*!< DCU DATA0 */
#define DCU_DATA1_IDX (1UL) /*!< DCU DATA1 */
#define DCU_DATA2_IDX (2UL) /*!< DCU DATA2 */
/**
* @}
*/
/**
* @defgroup DCU_Common_Trigger_Source_Configure DCU common Trigger Source Configure
* @{
*/
#define DCU_COM_TRIG1 (AOS_DCU_1_TRGSEL_COMTRG_EN_0)
#define DCU_COM_TRIG2 (AOS_DCU_1_TRGSEL_COMTRG_EN_1)
#define DCU_COM_TRIG_MASK (AOS_DCU_1_TRGSEL_COMTRG_EN)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup DCU_Global_Functions
* @{
*/
/* Initialization and configuration DCU functions */
en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInit);
en_result_t DCU_StructInit(stc_dcu_init_t *pstcInit);
void DCU_DeInit(M4_DCU_TypeDef *DCUx);
en_result_t DCU_WaveCfg(M4_DCU_TypeDef *DCUx, const stc_dcu_wave_cfg_t *pstcCfg);
void DCU_SetMode(M4_DCU_TypeDef *DCUx, uint32_t u32Mode);
uint32_t DCU_GetMode(const M4_DCU_TypeDef *DCUx);
void DCU_SetDataSize(M4_DCU_TypeDef *DCUx, uint32_t u32DataSize);
uint32_t DCU_GetDataSize(const M4_DCU_TypeDef *DCUx);
en_flag_status_t DCU_GetStatus(const M4_DCU_TypeDef *DCUx, uint32_t u32Flag);
void DCU_ClearStatus(M4_DCU_TypeDef *DCUx, uint32_t u32Flag);
void DCU_IntCmd(M4_DCU_TypeDef *DCUx,
uint32_t u32IntCategory,
uint32_t u32IntType,
en_functional_state_t enNewState);
void DCU_GlobalIntCmd(M4_DCU_TypeDef *DCUx, en_functional_state_t enNewState);
void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx,
uint32_t u32ComTrig,
en_functional_state_t enNewState);
void DCU_SetTriggerSrc(const M4_DCU_TypeDef *DCUx, en_event_src_t enEventSrc);
uint8_t DCU_ReadData8(const M4_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
void DCU_WriteData8(M4_DCU_TypeDef *DCUx,
uint32_t u32DataIndex,
uint8_t u8Data);
uint16_t DCU_ReadData16(const M4_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
void DCU_WriteData16(M4_DCU_TypeDef *DCUx,
uint32_t u32DataIndex,
uint16_t u16Data);
uint32_t DCU_ReadData32(const M4_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
void DCU_WriteData32(M4_DCU_TypeDef *DCUx,
uint32_t u32DataIndex,
uint32_t u32Data);
/**
* @}
*/
#endif /* DDL_DCU_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_DCU_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_dma.h
* @brief This file contains all the functions prototypes of the DMA driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Zhangxl First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_DMA_H__
#define __HC32F4A0_DMA_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_DMA
* @{
*/
#if (DDL_DMA_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup DMA_Global_Types DMA Global Types
* @{
*/
/**
* @brief DMA basic configuration
*/
typedef struct
{
uint32_t u32IntEn; /*!< Specifies the DMA interrupt function.
This parameter can be a value of @ref DMA_Int_Config */
uint32_t u32SrcAddr; /*!< Specifies the DMA source address. */
uint32_t u32DestAddr; /*!< Specifies the DMA destination address. */
uint32_t u32DataWidth; /*!< Specifies the DMA transfer data width.
This parameter can be a value of @ref DMA_DataWidth_Sel */
uint32_t u32BlockSize; /*!< Specifies the DMA block size. */
uint32_t u32TransCnt; /*!< Specifies the DMA transfer count. */
uint32_t u32SrcInc; /*!< Specifies the source address increment mode.
This parameter can be a value of @ref DMA_SrcAddr_Incremented_Mode */
uint32_t u32DestInc; /*!< Specifies the destination address increment mode.
This parameter can be a value of @ref DMA_DesAddr_Incremented_Mode */
} stc_dma_init_t;
/**
* @brief DMA repeat mode configuration
*/
typedef struct
{
uint32_t u32SrcRptEn; /*!< Specifies the DMA source repeat function.
This parameter can be a value of @ref DMA_Repeat_Config */
uint32_t u32SrcRptSize; /*!< Specifies the DMA source repeat size. */
uint32_t u32DestRptEn; /*!< Specifies the DMA destination repeat function.
This parameter can be a value of @ref DMA_Repeat_Config */
uint32_t u32DestRptSize; /*!< Specifies the DMA destination repeat size. */
} stc_dma_rpt_init_t;
/**
* @brief DMA non-sequence mode configuration
*/
typedef struct
{
uint32_t u32SrcNonSeqEn; /*!< Specifies the DMA source non-sequence function.
This parameter can be a value of @ref DMA_NonSeq_Config */
uint32_t u32SrcNonSeqCnt; /*!< Specifies the DMA source non-sequence function count. */
uint32_t u32SrcNonSeqOfs; /*!< Specifies the DMA source non-sequence function offset. */
uint32_t u32DestNonSeqEn; /*!< Specifies the DMA destination non-sequence function.
This parameter can be a value of @ref DMA_NonSeq_Config */
uint32_t u32DestNonSeqCnt; /*!< Specifies the DMA destination non-sequence function count. */
uint32_t u32DestNonSeqOfs; /*!< Specifies the DMA destination non-sequence function offset. */
} stc_dma_nonseq_init_t;
/**
* @brief DMA Link List Pointer (LLP) mode configuration
*/
typedef struct
{
uint32_t u32LlpEn; /*!< Specifies the DMA LLP function.
This parameter can be a value of @ref DMA_Llp_En */
uint32_t u32LlpRun; /*!< Specifies the DMA LLP auto or wait REQ.
This parameter can be a value of @ref DMA_Llp_Mode */
uint32_t u32LlpAddr; /*!< Specifies the DMA list pointer address for LLP function. */
} stc_dma_llp_init_t;
/**
* @brief DMA re-config function configuration
*/
typedef struct
{
uint32_t u32CntMode; /*!< Specifies the DMA reconfig function count mode.
This parameter can be a value of @ref DMA_ReConfig_Cnt_Sel */
uint32_t u32DestAddrMode; /*!< Specifies the DMA reconfig function destination address mode.
This parameter can be a value of @ref DMA_ReConfig_DestAddr_Sel */
uint32_t u32SrcAddrMode; /*!< Specifies the DMA reconfig function source address mode.
This parameter can be a value of @ref DMA_ReConfig_SrcAddr_Sel */
} stc_dma_reconfig_init_t;
/**
* @brief Dma LLP(linked list pointer) descriptor structure definition
*/
typedef struct
{
uint32_t SARx; /*!< LLP source address */
uint32_t DARx; /*!< LLP destination address */
uint32_t DTCTLx; /*!< LLP transfer count and block size */
uint32_t RPTx; /*!< LLP source & destination repeat size */
uint32_t SNSEQCTLx; /*!< LLP source non-seq count and offset */
uint32_t DNSEQCTLx; /*!< LLP destination non-seq count and offset */
uint32_t LLPx; /*!< LLP next list pointer */
uint32_t CHCTLx; /*!< LLP channel control */
} stc_dma_llp_descriptor_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup DMA_Global_Macros DMA Global Macros
* @{
*/
/**
* @defgroup DMA_Channel_selection DMA Channel Position selection
* @{
*/
#define DMA_CH0 (0x00U) /*!< DMA Channel 0 */
#define DMA_CH1 (0x01U) /*!< DMA Channel 1 */
#define DMA_CH2 (0x02U) /*!< DMA Channel 2 */
#define DMA_CH3 (0x03U) /*!< DMA Channel 3 */
#define DMA_CH4 (0x04U) /*!< DMA Channel 4 */
#define DMA_CH5 (0x05U) /*!< DMA Channel 5 */
#define DMA_CH6 (0x06U) /*!< DMA Channel 6 */
#define DMA_CH7 (0x07U) /*!< DMA Channel 7 */
/**
* @}
*/
/**
* @defgroup DMA_Mx_Channel_selection DMA Multiplex Channel selection
* @{
*/
#define DMA_MX_CH0 (0x01UL) /*!< DMA Channel 0 position */
#define DMA_MX_CH1 (0x02UL) /*!< DMA Channel 1 position */
#define DMA_MX_CH2 (0x04UL) /*!< DMA Channel 2 position */
#define DMA_MX_CH3 (0x08UL) /*!< DMA Channel 3 position */
#define DMA_MX_CH4 (0x10UL) /*!< DMA Channel 4 position */
#define DMA_MX_CH5 (0x20UL) /*!< DMA Channel 5 position */
#define DMA_MX_CH6 (0x40UL) /*!< DMA Channel 6 position */
#define DMA_MX_CH7 (0x80UL) /*!< DMA Channel 7 position */
#define DMA_MX_CH_ALL (0xFFUL) /*!< DMA Channel mask position */
/**
* @}
*/
/**
* @defgroup DMA_ReqErrIrq_Sel DMA request error interrupt selection
* @{
*/
#define DMA_REQ_ERR_CH0 (DMA_INTSTAT0_REQERR_0) /*!< DMA request error interrupt CH.0 */
#define DMA_REQ_ERR_CH1 (DMA_INTSTAT0_REQERR_1) /*!< DMA request error interrupt CH.1 */
#define DMA_REQ_ERR_CH2 (DMA_INTSTAT0_REQERR_2) /*!< DMA request error interrupt CH.2 */
#define DMA_REQ_ERR_CH3 (DMA_INTSTAT0_REQERR_3) /*!< DMA request error interrupt CH.3 */
#define DMA_REQ_ERR_CH4 (DMA_INTSTAT0_REQERR_4) /*!< DMA request error interrupt CH.4 */
#define DMA_REQ_ERR_CH5 (DMA_INTSTAT0_REQERR_5) /*!< DMA request error interrupt CH.5 */
#define DMA_REQ_ERR_CH6 (DMA_INTSTAT0_REQERR_6) /*!< DMA request error interrupt CH.6 */
#define DMA_REQ_ERR_CH7 (DMA_INTSTAT0_REQERR_7) /*!< DMA request error interrupt CH.7 */
/**
* @}
*/
/**
* @defgroup DMA_TransErrIrq_Sel DMA transfer error interrupt selection
* @{
*/
#define DMA_TRANS_ERR_CH0 (DMA_INTSTAT0_TRNERR_0) /*!< DMA transfer error interrupt CH.0 */
#define DMA_TRANS_ERR_CH1 (DMA_INTSTAT0_TRNERR_1) /*!< DMA transfer error interrupt CH.1 */
#define DMA_TRANS_ERR_CH2 (DMA_INTSTAT0_TRNERR_2) /*!< DMA transfer error interrupt CH.2 */
#define DMA_TRANS_ERR_CH3 (DMA_INTSTAT0_TRNERR_3) /*!< DMA transfer error interrupt CH.3 */
#define DMA_TRANS_ERR_CH4 (DMA_INTSTAT0_TRNERR_4) /*!< DMA transfer error interrupt CH.4 */
#define DMA_TRANS_ERR_CH5 (DMA_INTSTAT0_TRNERR_5) /*!< DMA transfer error interrupt CH.5 */
#define DMA_TRANS_ERR_CH6 (DMA_INTSTAT0_TRNERR_6) /*!< DMA transfer error interrupt CH.6 */
#define DMA_TRANS_ERR_CH7 (DMA_INTSTAT0_TRNERR_7) /*!< DMA transfer error interrupt CH.7 */
/**
* @}
*/
/**
* @defgroup DMA_BtcIrq_Sel DMA block transfer completed interrupt selection
* @{
*/
#define DMA_BTC_INT_CH0 (DMA_INTSTAT1_BTC_0) /*!< DMA block transfer completed interrupt CH.0 */
#define DMA_BTC_INT_CH1 (DMA_INTSTAT1_BTC_1) /*!< DMA block transfer completed interrupt CH.1 */
#define DMA_BTC_INT_CH2 (DMA_INTSTAT1_BTC_2) /*!< DMA block transfer completed interrupt CH.2 */
#define DMA_BTC_INT_CH3 (DMA_INTSTAT1_BTC_3) /*!< DMA block transfer completed interrupt CH.3 */
#define DMA_BTC_INT_CH4 (DMA_INTSTAT1_BTC_4) /*!< DMA block transfer completed interrupt CH.4 */
#define DMA_BTC_INT_CH5 (DMA_INTSTAT1_BTC_5) /*!< DMA block transfer completed interrupt CH.5 */
#define DMA_BTC_INT_CH6 (DMA_INTSTAT1_BTC_6) /*!< DMA block transfer completed interrupt CH.6 */
#define DMA_BTC_INT_CH7 (DMA_INTSTAT1_BTC_7) /*!< DMA block transfer completed interrupt CH.7 */
/**
* @}
*/
/**
* @defgroup DMA_TcIrq_Sel DMA transfer completed interrupt selection
* @{
*/
#define DMA_TC_INT_CH0 (DMA_INTSTAT1_TC_0) /*!< DMA transfer completed interrupt CH.0 */
#define DMA_TC_INT_CH1 (DMA_INTSTAT1_TC_1) /*!< DMA transfer completed interrupt CH.1 */
#define DMA_TC_INT_CH2 (DMA_INTSTAT1_TC_2) /*!< DMA transfer completed interrupt CH.2 */
#define DMA_TC_INT_CH3 (DMA_INTSTAT1_TC_3) /*!< DMA transfer completed interrupt CH.3 */
#define DMA_TC_INT_CH4 (DMA_INTSTAT1_TC_4) /*!< DMA transfer completed interrupt CH.4 */
#define DMA_TC_INT_CH5 (DMA_INTSTAT1_TC_5) /*!< DMA transfer completed interrupt CH.5 */
#define DMA_TC_INT_CH6 (DMA_INTSTAT1_TC_6) /*!< DMA transfer completed interrupt CH.6 */
#define DMA_TC_INT_CH7 (DMA_INTSTAT1_TC_7) /*!< DMA transfer completed interrupt CH.7 */
/**
* @}
*/
/**
* @defgroup DMA_IntMsk_Sel DMA interrupt mask selection
* @{
*/
#define DMA_ERR_INT_MASK (0x00FF00FFUL) /*!< DMA error interrupt mask */
#define DMA_TRANS_INT_MASK (0x00FF00FFUL) /*!< DMA transfer interrupt mask */
/**
* @}
*/
/**
* @defgroup DMA_Req_Status_Sel DMA request status
* @{
*/
#define DMA_REQ_CH0 (DMA_REQSTAT_CHREQ_0) /*!< DMA request from CH.0 */
#define DMA_REQ_CH1 (DMA_REQSTAT_CHREQ_1) /*!< DMA request from CH.1 */
#define DMA_REQ_CH2 (DMA_REQSTAT_CHREQ_2) /*!< DMA request from CH.2 */
#define DMA_REQ_CH3 (DMA_REQSTAT_CHREQ_3) /*!< DMA request from CH.3 */
#define DMA_REQ_CH4 (DMA_REQSTAT_CHREQ_4) /*!< DMA request from CH.4 */
#define DMA_REQ_CH5 (DMA_REQSTAT_CHREQ_5) /*!< DMA request from CH.5 */
#define DMA_REQ_CH6 (DMA_REQSTAT_CHREQ_6) /*!< DMA request from CH.6 */
#define DMA_REQ_CH7 (DMA_REQSTAT_CHREQ_7) /*!< DMA request from CH.7 */
#define DMA_REQ_RECONFIG (DMA_REQSTAT_RCFGREQ) /*!< DMA request from reconfig */
#define DMA_REQ_STAT_MASK (0x000080FFUL) /*!< DMA request mask */
/**
* @}
*/
/**
* @defgroup DMA_Trans_Status_Sel DMA transfer status
* @{
*/
#define DMA_TRANS_CH0 (DMA_CHSTAT_CHACT_0) /*!< DMA transfer status of CH.0 */
#define DMA_TRANS_CH1 (DMA_CHSTAT_CHACT_1) /*!< DMA transfer status of CH.1 */
#define DMA_TRANS_CH2 (DMA_CHSTAT_CHACT_2) /*!< DMA transfer status of CH.2 */
#define DMA_TRANS_CH3 (DMA_CHSTAT_CHACT_3) /*!< DMA transfer status of CH.3 */
#define DMA_TRANS_CH4 (DMA_CHSTAT_CHACT_4) /*!< DMA transfer status of CH.4 */
#define DMA_TRANS_CH5 (DMA_CHSTAT_CHACT_5) /*!< DMA transfer status of CH.5 */
#define DMA_TRANS_CH6 (DMA_CHSTAT_CHACT_6) /*!< DMA transfer status of CH.6 */
#define DMA_TRANS_CH7 (DMA_CHSTAT_CHACT_7) /*!< DMA transfer status of CH.7 */
#define DMA_TRANS_RECONFIG (DMA_CHSTAT_RCFGACT) /*!< DMA reconfig status */
#define DMA_TRANS_DMA (DMA_CHSTAT_DMAACT) /*!< DMA transfer status of the DMA */
#define DMA_TRANS_STAT_MASK (0x0000FF03UL) /*!< DMA request mask */
/**
* @}
*/
/**
* @defgroup DMA_DataWidth_Sel DMA transfer data width
* @{
*/
#define DMA_DATAWIDTH_8BIT (0x00000000UL) /*!< DMA transfer data width 8bit */
#define DMA_DATAWIDTH_16BIT (DMA_CHCTL_HSIZE_0) /*!< DMA transfer data width 16bit */
#define DMA_DATAWIDTH_32BIT (DMA_CHCTL_HSIZE_1) /*!< DMA transfer data width 32bit */
/**
* @}
*/
/**
* @defgroup DMA_Llp_En DMA LLP(linked list pinter) enable or disable
* @{
*/
#define DMA_LLP_ENABLE (DMA_CHCTL_LLPEN) /*!< DMA LLP(linked list pinter) enable */
#define DMA_LLP_DISABLE (0x00000000UL) /*!< DMA LLP(linked list pinter) disable */
/**
* @}
*/
/**
* @defgroup DMA_Llp_Mode DMA linked list pinter mode while transferring complete
* @{
*/
#define DMA_LLP_RUN (DMA_CHCTL_LLPRUN) /*!< DMA Llp run right now while transfering complete */
#define DMA_LLP_WAIT (0x00000000UL) /*!< DMA Llp wait next request while transfering complete */
/**
* @}
*/
/**
* @defgroup DMA_SrcAddr_Incremented_Mode DMA source address increment mode
* @{
*/
#define DMA_SRC_ADDR_FIX (0x00000000UL) /*!< DMA source address fix */
#define DMA_SRC_ADDR_INC (DMA_CHCTL_SINC_0) /*!< DMA source address increment */
#define DMA_SRC_ADDR_DEC (DMA_CHCTL_SINC_1) /*!< DMA source address decrement */
/**
* @}
*/
/**
* @defgroup DMA_DesAddr_Incremented_Mode DMA destination address increment mode
* @{
*/
#define DMA_DEST_ADDR_FIX (0x00000000UL) /*!< DMA destination address fix */
#define DMA_DEST_ADDR_INC (DMA_CHCTL_DINC_0) /*!< DMA destination address increment */
#define DMA_DEST_ADDR_DEC (DMA_CHCTL_DINC_1) /*!< DMA destination address decrement */
/**
* @}
*/
/**
* @defgroup DMA_Int_Config DMA interrupt function config
* @{
*/
#define DMA_INT_ENABLE (DMA_CHCTL_IE) /*!< DMA interrupt enable */
#define DMA_INT_DISABLE (0x00000000UL) /*!< DMA interrupt disable */
/**
* @}
*/
/**
* @defgroup DMA_Repeat_Config DMA repeat mode function config
* @{
*/
#define DMA_SRC_RPT_ENABLE (DMA_CHCTL_SRTPEN) /*!< DMA source repeat enable */
#define DMA_SRC_RPT_DISABLE (0x00000000UL) /*!< DMA source repeat disable */
#define DMA_DEST_RPT_ENABLE (DMA_CHCTL_DRPTEN) /*!< DMA destination repeat enable */
#define DMA_DEST_RPT_DISABLE (0x00000000UL) /*!< DMA destination repeat disable */
/**
* @}
*/
/**
* @defgroup DMA_NonSeq_Config DMA non-sequence mode function config
* @{
*/
#define DMA_SRC_NS_ENABLE (DMA_CHCTL_SNSEQEN) /*!< DMA source non-sequence enable */
#define DMA_SRC_NS_DISABLE (0x00000000UL) /*!< DMA source non-sequence disable */
#define DMA_DEST_NS_ENABLE (DMA_CHCTL_DNSEQEN) /*!< DMA destination non-sequence enable */
#define DMA_DEST_NS_DISABLE (0x00000000UL) /*!< DMA destination non-sequence disable */
/**
* @}
*/
/**
* @defgroup DMA_ReConfig_Cnt_Sel DMA reconfig count mode selection
* @{
*/
#define DMA_RC_CNT_FIX (0x00UL) /*!< Keep the original counting method */
#define DMA_RC_CNT_SRC (DMA_RCFGCTL_CNTMD_0) /*!< Use source address counting method */
#define DMA_RC_CNT_DEST (DMA_RCFGCTL_CNTMD_1) /*!< Use destination address counting method */
/**
* @}
*/
/**
* @defgroup DMA_ReConfig_DestAddr_Sel DMA reconfig destination address mode selection
* @{
*/
#define DMA_RC_DA_FIX (0x00000000UL) /*!< Destination address fixed */
#define DMA_RC_DA_NS (DMA_RCFGCTL_DARMD_0) /*!< Destination address non-sequence */
#define DMA_RC_DA_RPT (DMA_RCFGCTL_DARMD_1) /*!< Destination address repeat */
/**
* @}
*/
/**
* @defgroup DMA_ReConfig_SrcAddr_Sel DMA reconfig source address mode selection
* @{
*/
#define DMA_RC_SA_FIX (0x00000000UL) /*!< Source address fixed */
#define DMA_RC_SA_NS (DMA_RCFGCTL_SARMD_0) /*!< Source address non-sequence */
#define DMA_RC_SA_RPT (DMA_RCFGCTL_SARMD_1) /*!< Source address repeat */
/**
* @}
*/
/**
* @defgroup DMA_Common_Trigger_Source_Config DMA common Trigger Source Config
* @{
*/
#define DMA_COM_TRIG1 (AOS_DMA_1_TRGSEL_COMTRG_EN_0)
#define DMA_COM_TRIG2 (AOS_DMA_1_TRGSEL_COMTRG_EN_1)
#define DMA_COM_TRIG_MASK (AOS_DMA_1_TRGSEL_COMTRG_EN)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup DMA_Global_Functions
* @{
*/
void DMA_Cmd(M4_DMA_TypeDef *DMAx, en_functional_state_t enNewState);
void DMA_ErrIntCmd(M4_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState);
en_flag_status_t DMA_GetErrIntStatus(const M4_DMA_TypeDef *DMAx, uint32_t u32ErrInt);
void DMA_ClearErrIntStatus(M4_DMA_TypeDef *DMAx, uint32_t u32ErrInt);
void DMA_TransIntCmd(M4_DMA_TypeDef *DMAx, uint32_t u32TransInt, en_functional_state_t enNewState);
en_flag_status_t DMA_GetTransIntStatus(const M4_DMA_TypeDef *DMAx, uint32_t u32TransInt);
void DMA_ClearTransIntStatus(M4_DMA_TypeDef *DMAx, uint32_t u32TransInt);
void DMA_MxChannelCmd(M4_DMA_TypeDef *DMAx, uint8_t u8MxCh, en_functional_state_t enNewState);
void DMA_ChannelCmd(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState);
void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc);
void DMA_RCComTriggerCmd(uint32_t u32ComTrig, en_functional_state_t enNewState);
void DMA_SetTriggerSrc(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch, en_event_src_t enSrc);
void DMA_ComTriggerCmd(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32ComTrig, en_functional_state_t enNewState);
en_flag_status_t DMA_GetReqStatus(const M4_DMA_TypeDef *DMAx, uint32_t u32Status);
en_flag_status_t DMA_GetTransStatus(const M4_DMA_TypeDef *DMAx, uint32_t u32Status);
void DMA_SetSrcAddr(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr);
void DMA_SetDestAddr(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr);
void DMA_SetTransCnt(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Cnt);
void DMA_SetBlockSize(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size);
void DMA_SetSrcRptSize(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size);
void DMA_SetDestRptSize(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size);
void DMA_SetNonSeqSrcCnt(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Cnt);
void DMA_SetNonSeqDestCnt(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Cnt);
void DMA_SetNonSeqSrcOffset(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Ofs);
void DMA_SetNonSeqDestOffset(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Ofs);
void DMA_SetLlpAddr(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32LlpAddr);
en_result_t DMA_Init(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit);
en_result_t DMA_RepeatInit(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_rpt_init_t *pstcDmaRptInit);
en_result_t DMA_NonSeqInit(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit);
en_result_t DMA_LlpInit(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit);
en_result_t DMA_ReConfigInit(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit);
en_result_t DMA_StructInit(stc_dma_init_t *pstcDmaInit);
en_result_t DMA_RepeatStructInit(stc_dma_rpt_init_t *pstcDmaRptInit);
en_result_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit);
en_result_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit);
en_result_t DMA_ReConfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit);
void DMA_LlpCmd(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState);
void DMA_ReConfigCmd(M4_DMA_TypeDef *DMAx, en_functional_state_t enNewState);
void DMA_ReConfigLlpCmd(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState);
uint32_t DMA_GetSrcAddr(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetDestAddr(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetTransCnt(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetBlockSize(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetSrcRptSize(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetDestRptSize(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetNonSeqSrcCnt(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetNonSeqDestCnt(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetNonSeqSrcOffset(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch);
uint32_t DMA_GetNonSeqDestOffset(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch);
/**
* @}
*/
#endif /* DDL_DMA_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_DMA_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_dmc.h
* @brief This file contains all the functions prototypes of the EXMC DMC
* (External Memory Controller: Dynamic Memory Controller) driver library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hongjh First version
2020-07-14 Hongjh Merge API from EXMC_DMC_Enable/Disable to EXMC_DMC_Cmd
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_DMC_H__
#define __HC32F4A0_DMC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_EXMC_DMC
* @{
*/
#if (DDL_DMC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup EXMC_DMC_Global_Types Dynamic Memory Controller Global Types
* @{
*/
/**
* @brief EXMC DMC CS Configuration Structure definition
*/
typedef struct
{
uint32_t u32AddrMask; /*!< Defines the address mask.
This parameter can be a value of @ref EXMC_DMC_Mask_Address. */
uint32_t u32AddrMatch; /*!< Defines the address match.
This parameter can be a value of @ref EXMC_DMC_Match_Address. */
uint32_t u32AddrDecodeMode; /*!< Defines the address decode mode.
This parameter can be a value of @ref EXMC_DMC_CS_Decode_Mode. */
} stc_exmc_dmc_cs_cfg_t;
/**
* @brief EXMC DMC Chip Configuration Structure definition
*/
typedef struct
{
uint32_t u32ColumnBitsNumber; /*!< Defines the number of bits of column address.
This parameter can be a value of @ref EXMC_DMC_Column_Bits_Number. */
uint32_t u32RowBitsNumber; /*!< Defines the number of bits of row address.
This parameter can be a value of @ref EXMC_DMC_Row_Bits_Number. */
uint32_t u32AutoPrechargePin; /*!< Defines the auto-precharge pin.
This parameter can be a value of @ref EXMC_DMC_Auto_Precharge_Pin. */
uint32_t u32MemClkSel; /*!< Defines the memory clock selection.
This parameter can be a value of @ref EXMC_DMC_MemClock_Selection */
uint32_t u32CkeOutputSel; /*!< Defines the CKE output selection.
This parameter can be a value of @ref EXMC_DMC_CKE_Output_Selection */
uint32_t u32CkeDisablePeriod; /*!< Defines the CKE disable period.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x3F */
uint32_t u32MemBurst; /*!< Defines the number of data accesses.
This parameter can be a value of @ref EXMC_DMC_Memory_Burst. */
uint32_t u32AutoRefreshChips; /*!< Defines the refresh command generation for the number of memory chips.
This parameter can be a value of @ref EXMC_DMC_Auto_Refresh_Chips. */
}stc_exmc_dmc_chip_cfg_t;
/**
* @brief EXMC DMC Timing Configuration Structure definition
*/
typedef struct
{
uint32_t u32CASL; /*!< Defines the CAS latency in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint32_t u32DQSS; /*!< Defines the DQSS in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 3 */
uint32_t u32MRD; /*!< Defines the the mode register command time in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x7F */
uint32_t u32RAS; /*!< Defines the RAS in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
uint32_t u32RC; /*!< Defines the RC in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
uint32_t u32RCD; /*!< Defines the RCD in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint32_t u32RFC; /*!< Defines the RFC in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x1F */
uint32_t u32RP; /*!< Defines the RP in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint32_t u32RRD; /*!< Defines the RRD in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
uint32_t u32WR; /*!< Defines the WR in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint32_t u32WTR; /*!< Defines the WTR in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint32_t u32XP; /*!< Defines the XP in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32XSR; /*!< Defines the XSR in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32ESR; /*!< Defines the ESR in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
} stc_exmc_dmc_timing_cfg_t;
/**
* @brief EXMC DMC Initialization Structure definition
*/
typedef struct
{
uint32_t u32DmcMemWidth; /*!< DMC memory width.
This parameter can be a value of @ref EXMC_DMC_Memory_Width. */
uint32_t u32RefreshPeriod; /*!< DMC memory refresh period.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x7FFF */
stc_exmc_dmc_chip_cfg_t stcChipCfg; /*!< DMC memory chip configure.
This structure details refer @ref stc_exmc_dmc_chip_cfg_t. */
stc_exmc_dmc_timing_cfg_t stcTimingCfg; /*!< DMC memory timing configure.
This structure details refer @ref stc_exmc_dmc_timing_cfg_t. */
} stc_exmc_dmc_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup EXMC_DMC_Global_Macros Dynamic Memory Controller Global Macros
* @{
*/
/**
* @defgroup EXMC_DMC_Memory_Width EXMC DMC Memory Width
* @{
*/
#define EXMC_DMC_MEMORY_WIDTH_16BIT (0UL)
#define EXMC_DMC_MEMORY_WIDTH_32BIT (DMC_BACR_DMCMW_0)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Chip EXMC DMC Chip
* @{
*/
#define EXMC_DMC_CHIP_0 (0UL) /*!< Chip 0 */
#define EXMC_DMC_CHIP_1 (1UL) /*!< Chip 1 */
#define EXMC_DMC_CHIP_2 (2UL) /*!< Chip 2 */
#define EXMC_DMC_CHIP_3 (3UL) /*!< Chip 3 */
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Bank EXMC DMC Bank
* @{
*/
#define EXMC_DMC_BANK_0 (0UL) /*!< Bank 0 */
#define EXMC_DMC_BANK_1 (1UL) /*!< Bank 1 */
#define EXMC_DMC_BANK_2 (2UL) /*!< Bank 2 */
#define EXMC_DMC_BANK_3 (3UL) /*!< Bank 3 */
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Current_Status EXMC DMC Current Status
* @{
*/
#define EXMC_DMC_CURR_STATUS_CONFIGURE (0UL)
#define EXMC_DMC_CURR_STATUS_READY (DMC_STSR_STATUS_0)
#define EXMC_DMC_CURR_STATUS_PAUSED (DMC_STSR_STATUS_1)
#define EXMC_DMC_CURR_STATUS_LOWPOWER (DMC_STSR_STATUS)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Control_State EXMC DMC Control State
* @{
*/
#define EXMC_DMC_CTL_STATE_GO (0UL)
#define EXMC_DMC_CTL_STATE_SLEEP (1UL)
#define EXMC_DMC_CTL_STATE_WAKEUP (2UL)
#define EXMC_DMC_CTL_STATE_PAUSE (3UL)
#define EXMC_DMC_CTL_STATE_CONFIGURE (4UL)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Command EXMC DMC Command
* @{
*/
#define EXMC_DMC_CMD_PRECHARGEALL (0UL) /*!< Precharge all */
#define EXMC_DMC_CMD_AUTOREFRESH (DMC_CMDR_CMD_0) /*!< Auto refresh */
#define EXMC_DMC_CMD_MDREGCONFIG (DMC_CMDR_CMD_1) /*!< Set memory device mode register */
#define EXMC_DMC_CMD_NOP (DMC_CMDR_CMD) /*!< NOP */
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Refresh_Period_Max EXMC DMC Refresh Period Max
* @{
*/
#define EXMC_DMC_REFRESH_PERIOD_MAX (0x00007FFFUL)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_CS_Decode_Mode EXMC DMC CS Decode Mode
* @{
*/
#define EXMC_DMC_CS_DECODE_ROWBANKCOL (0UL) /*!< Row -> Bank -> Column */
#define EXMC_DMC_CS_DECODE_BANKROWCOL (DMC_CSCR_BRC) /*!< Bank -> Row -> Column */
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Column_Bits_Number EXMC DMC Column Bits Number
* @{
*/
#define EXMC_DMC_COLUMN_BITS_NUM_8 (0UL)
#define EXMC_DMC_COLUMN_BITS_NUM_9 (DMC_CPCR_COLBS_0)
#define EXMC_DMC_COLUMN_BITS_NUM_10 (DMC_CPCR_COLBS_1)
#define EXMC_DMC_COLUMN_BITS_NUM_11 (DMC_CPCR_COLBS_1 | \
DMC_CPCR_COLBS_0)
#define EXMC_DMC_COLUMN_BITS_NUM_12 (DMC_CPCR_COLBS_2)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Row_Bits_Number EXMC DMC Row Bits Number
* @{
*/
#define EXMC_DMC_ROW_BITS_NUM_11 (0UL)
#define EXMC_DMC_ROW_BITS_NUM_12 (DMC_CPCR_ROWBS_0)
#define EXMC_DMC_ROW_BITS_NUM_13 (DMC_CPCR_ROWBS_1)
#define EXMC_DMC_ROW_BITS_NUM_14 (DMC_CPCR_ROWBS_1 | \
DMC_CPCR_ROWBS_0)
#define EXMC_DMC_ROW_BITS_NUM_15 (DMC_CPCR_ROWBS_2)
#define EXMC_DMC_ROW_BITS_NUM_16 (DMC_CPCR_ROWBS_2 | \
DMC_CPCR_ROWBS_0)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Auto_Precharge_Pin EXMC DMC Auto Pre-charge Pin
* @{
*/
#define EXMC_DMC_AUTO_PRECHARGE_A8 (DMC_CPCR_APBS)
#define EXMC_DMC_AUTO_PRECHARGE_A10 (0UL)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_CKE_Output_Selection EXMC DMC CKE Output Selection
* @{
*/
#define EXMC_DMC_CKE_OUTPUT_ENABLE (0UL)
#define EXMC_DMC_CKE_OUTPUT_DISABLE (DMC_CPCR_CKEDIS)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_MemClock_Selection EXMC DMC MemClock Selection
* @{
*/
#define EXMC_DMC_MEMCLK_NORMAL_OUTPUT (0UL)
#define EXMC_DMC_MEMCLK_NOP_STOP_OUTPUT (DMC_CPCR_CKSTOP)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Memory_Burst EXMC DMC Memory Burst
* @{
*/
#define EXMC_DMC_MEM_BURST_1 (0UL)
#define EXMC_DMC_MEM_BURST_2 (DMC_CPCR_BURST_0)
#define EXMC_DMC_MEM_BURST_4 (DMC_CPCR_BURST_1)
#define EXMC_DMC_MEM_BURST_8 (DMC_CPCR_BURST_1 | \
DMC_CPCR_BURST_0)
#define EXMC_DMC_MEM_BURST_16 (DMC_CPCR_BURST_2)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Auto_Refresh_Chips EXMC DMC Auto Refresh
* @{
*/
#define EXMC_DMC_AUTO_REFRESH_CHIP_0 (0UL)
#define EXMC_DMC_AUTO_REFRESH_CHIPS_01 (DMC_CPCR_ACTCP_0)
#define EXMC_DMC_AUTO_REFRESH_CHIPS_012 (DMC_CPCR_ACTCP_1)
#define EXMC_DMC_AUTO_REFRESH_CHIPS_0123 (DMC_CPCR_ACTCP)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Match_Address EXMC DMC Match Address
* @{
*/
#define EXMC_DMC_ADDR_MATCH_0X80000000 (0x80UL << DMC_CSCR_ADDMAT_POS)
#define EXMC_DMC_ADDR_MATCH_0X81000000 (0x81UL << DMC_CSCR_ADDMAT_POS)
#define EXMC_DMC_ADDR_MATCH_0X82000000 (0x82UL << DMC_CSCR_ADDMAT_POS)
#define EXMC_DMC_ADDR_MATCH_0X83000000 (0x83UL << DMC_CSCR_ADDMAT_POS)
#define EXMC_DMC_ADDR_MATCH_0X84000000 (0x84UL << DMC_CSCR_ADDMAT_POS)
#define EXMC_DMC_ADDR_MATCH_0X85000000 (0x85UL << DMC_CSCR_ADDMAT_POS)
#define EXMC_DMC_ADDR_MATCH_0X86000000 (0x86UL << DMC_CSCR_ADDMAT_POS)
#define EXMC_DMC_ADDR_MATCH_0X87000000 (0x87UL << DMC_CSCR_ADDMAT_POS)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Mask_Address EXMC DMC Mask Address
* @{
*/
#define EXMC_DMC_ADDR_MASK_16MB (0xFFUL)
#define EXMC_DMC_ADDR_MASK_32MB (0xFEUL)
#define EXMC_DMC_ADDR_MASK_64MB (0xFCUL)
#define EXMC_DMC_ADDR_MASK_128MB (0xF8UL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup EXMC_DMC_Global_Functions
* @{
*/
/**
* @brief Get DMC status.
* @param None
* @retval Returned value can be one of the following values:
* @arg EXMC_DMC_CURR_STATUS_CONFIGURE: Configure status
* @arg EXMC_DMC_CURR_STATUS_READY: Ready status
* @arg EXMC_DMC_CURR_STATUS_PAUSED: Pause status
* @arg EXMC_DMC_CURR_STATUS_LOWPOWER: Sleep for low power status
*/
__STATIC_INLINE uint32_t EXMC_DMC_GetStatus(void)
{
return READ_REG32_BIT(M4_DMC->STSR, DMC_STSR_STATUS);
}
/* Initialization and configuration EXMC DMC functions */
en_result_t EXMC_DMC_Init(const stc_exmc_dmc_init_t *pstcInit);
void EXMC_DMC_DeInit(void);
en_result_t EXMC_DMC_StructInit(stc_exmc_dmc_init_t *pstcInit);
void EXMC_DMC_Cmd(en_functional_state_t enNewState);
en_result_t EXMC_DMC_CsConfig(uint32_t u32Chip,
const stc_exmc_dmc_cs_cfg_t *pstcCfg);
uint32_t EXMC_DMC_ChipStartAddress(uint32_t u32Chip);
uint32_t EXMC_DMC_ChipEndAddress(uint32_t u32Chip);
en_result_t EXMC_DMC_SetCommand(uint32_t u32Chip,
uint32_t u32Bank,
uint32_t u32Cmd,
uint32_t u32Address);
void EXMC_DMC_SetState(uint32_t u32State);
/**
* @}
*/
#endif /* DDL_DMC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_DMC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_dvp.h
* @brief This file contains all the functions prototypes of the DVP(Digital
* Video Processor) driver library.
@verbatim
Change Logs:
Date Author Notes
2020-08-20 Hongjh First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_DVP_H__
#define __HC32F4A0_DVP_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_DVP
* @{
*/
#if (DDL_DVP_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup DVP_Global_Types DVP Global Types
* @{
*/
/**
* @brief DVP Initialization Structure definition
*/
typedef struct
{
uint32_t u32SyncMode; /*!< The DVP sync mode.
This parameter can be a value of @ref DVP_Sync_Mode. */
uint32_t u32DataWidth; /*!< The DVP data interface width.
This parameter can be a value of @ref DVP_Data_Width. */
uint32_t u32CaptureMode; /*!< The DVP capture mode.
This parameter can be a value of @ref DVP_Capture_Mode. */
uint32_t u32CaptureFreq; /*!< The DVP capture frequence.
This parameter can be a value of @ref DVP_Capture_Frequence. */
uint32_t u32PIXCLKPolarity; /*!< The DVP_PIXCLK Polarity.
This parameter can be a value of @ref DVP_PIXCLK_Polarity. */
uint32_t u32HSYNCPolarity; /*!< The DVP_HSYNC Polarity.
This parameter can be a value of @ref DVP_HSYNC_Polarity. */
uint32_t u32VSYNCPolarity; /*!< The DVP_VSYNC Polarity.
This parameter can be a value of @ref DVP_VSYNC_Polarity. */
} stc_dvp_init_t;
/**
* @brief DVP Crop Window Configure definition
*/
typedef struct
{
uint32_t u32X; /*!< The DVP window X offset
This parameter can be a value between 0x00 and 0x3FFF */
uint32_t u32Y; /*!< The DVP window Y offset
This parameter can be a value between 0x00 and 0x3FFF */
uint32_t u32XSize; /*!< The DVP window pixel per line
This parameter can be a value between 0x00 and 0x3FFF */
uint32_t u32YSize; /*!< The DVP window line number.
This parameter can be a value between 0x00 and 0x3FFF */
} stc_dvp_crop_window_config_t;
/**
* @brief DVP Software Sync Code definition
*/
typedef struct
{
uint32_t u32FrameStartSyncCode; /*!< The sync code of the frame start delimiter.
This parameter can be a value between 0x00 and 0xFF */
uint32_t u32LineStartSyncCode; /*!< The sync code of the line start delimiter.
This parameter can be a value between 0x00 and 0xFF */
uint32_t u32LineEndSyncCode; /*!< The sync code of the line end delimiter.
This parameter can be a value between 0x00 and 0xFF */
uint32_t u32FrameEndSyncCode; /*!< The sync code of the frame end delimiter.
This parameter can be a value between 0x00 and 0xFF */
} stc_dvp_sw_sync_code_t;
/**
* @brief DVP Software Mask Code definition
*/
typedef struct
{
uint32_t u32FrameStartMaskCode; /*!< The mask code of the frame start delimiter.
This parameter can be a value between between 0x00 and 0xFF */
uint32_t u32LineStartMaskCode; /*!< The mask code of the line start delimiter.
This parameter can be a value between between 0x00 and 0xFF */
uint32_t u32LineEndMaskCode; /*!< The mask code of the line end delimiter.
This parameter can be a value between between 0x00 and 0xFF */
uint32_t u32FrameEndMaskCode; /*!< The mask code of the frame end delimiter.
This parameter can be a value between between 0x00 and 0xFF */
} stc_dvp_sw_mask_code_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup DVP_Global_Macros DVP Global Macros
* @{
*/
/** @defgroup DVP_Capture_Mode DVP Capture Mode
* @{
*/
#define DVP_CAPT_MD_CONTINUOS_FRAME (0UL)
#define DVP_CAPT_MD_SINGLE_FRAME (DVP_CTR_CAPMD)
/**
* @}
*/
/** @defgroup DVP_Sync_Mode DVP Sync Mode
* @{
*/
#define DVP_SYNC_MD_HW (0UL) /*!< Hardware sync */
#define DVP_SYNC_MD_SW (DVP_CTR_SWSYNC) /*!< Software sync */
/**
* @}
*/
/** @defgroup DVP_PIXCLK_Polarity DVP PIXCLK Polarity
* @{
*/
#define DVP_PIXCLK_FALLING (0UL) /*!< DVP_PIXCLK active on Falling edge */
#define DVP_PIXCLK_RISING (DVP_CTR_PIXCKSEL) /*!< DVP_PIXCLK active on Rising edge */
/**
* @}
*/
/** @defgroup DVP_HSYNC_Polarity DVP HSYNC Polarity
* @{
*/
#define DVP_HSYNC_LOW (0UL) /*!< DVP_HSYNC active Low */
#define DVP_HSYNC_HIGH (DVP_CTR_HSYNCSEL) /*!< DVP_HSYNC active High */
/**
* @}
*/
/** @defgroup DVP_VSYNC_Polarity DVP VSYNC Polarity
* @{
*/
#define DVP_VSYNC_LOW (0UL) /*!< DVP_VSYNC active Low */
#define DVP_VSYNC_HIGH (DVP_CTR_VSYNCSEL) /*!< DVP_VSYNC active High */
/**
* @}
*/
/**
* @defgroup DVP_Capture_Frequence DVP Capture Frequence
* @{
*/
#define DVP_CAPT_FREQ_ALL_FRAME (0UL) /*!< All frames are captured */
#define DVP_CAPT_FREQ_ONT_TIME_2FRAME (DVP_CTR_CAPFRC_0) /*!< One frame per 2 frames captured */
#define DVP_CAPT_FREQ_ONT_TIME_4FRAME (DVP_CTR_CAPFRC_1) /*!< One frame per 4 frames captured */
/**
* @}
*/
/**
* @defgroup DVP_Data_Width DVP Data Width
* @{
*/
#define DVP_DATA_WIDTH_8BIT (0UL) /*!< DVP captures 8-bit data on every DVP_PIXCLK clock */
#define DVP_DATA_WIDTH_10BIT (DVP_CTR_BITSEL_0) /*!< DVP captures 10-bit data on every DVP_PIXCLK clock */
#define DVP_DATA_WIDTH_12BIT (DVP_CTR_BITSEL_1) /*!< DVP captures 12-bit data on every DVP_PIXCLK clock */
#define DVP_DATA_WIDTH_14BIT (DVP_CTR_BITSEL) /*!< DVP captures 14-bit data on every DVP_PIXCLK clock */
/**
* @}
*/
/**
* @defgroup DVP_Flag DVP Flag
* @{
*/
#define DVP_FLAG_FRAME_START (DVP_STR_FSF) /*!< Frame start flag */
#define DVP_FLAG_LINE_START (DVP_STR_LSF) /*!< Line start flag */
#define DVP_FLAG_LINE_END (DVP_STR_LEF) /*!< Line end flag */
#define DVP_FLAG_FRAME_END (DVP_STR_FEF) /*!< Frame end flag */
#define DVP_FLAG_FIFO_OVF (DVP_STR_FIFOERF) /*!< FIFO overflow error flag */
#define DVP_FLAG_SYNC_ERR (DVP_STR_SQUERF) /*!< Sync error flag */
#define DVP_FLAG_ALL (DVP_FLAG_SYNC_ERR | \
DVP_FLAG_FIFO_OVF | \
DVP_FLAG_LINE_END | \
DVP_FLAG_LINE_START | \
DVP_FLAG_FRAME_END | \
DVP_FLAG_FRAME_START)
/**
* @}
*/
/**
* @defgroup DVP_Interrupt DVP Interrupt
* @{
*/
#define DVP_INT_FRAME_START (DVP_IER_FSIEN) /*!< Frame start interrupt */
#define DVP_INT_LINE_START (DVP_IER_LSIEN) /*!< Line start interrupt */
#define DVP_INT_LINE_END (DVP_IER_LEIEN) /*!< Line end interrupt */
#define DVP_INT_FRAME_END (DVP_IER_FEIEN) /*!< Frame end interrupt */
#define DVP_INT_FIFO_OVF (DVP_IER_FIFOERIEN) /*!< FIFO overflow error interrupt */
#define DVP_INT_SYNC_ERR (DVP_IER_SQUERIEN) /*!< Sync error interrupt */
#define DVP_INT_ALL (DVP_INT_SYNC_ERR | \
DVP_INT_FIFO_OVF | \
DVP_INT_LINE_END | \
DVP_INT_LINE_START | \
DVP_INT_FRAME_END | \
DVP_INT_FRAME_START)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup DVP_Global_Functions
* @{
*/
en_result_t DVP_Init(const stc_dvp_init_t *pstcDvpInit);
void DVP_DeInit(void);
en_result_t DVP_StructInit(stc_dvp_init_t *pstcDvpInit);
void DVP_Cmd(en_functional_state_t enNewState);
void DVP_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState);
void DVP_CropCmd(en_functional_state_t enNewState);
void DVP_JPEGCmd(en_functional_state_t enNewState);
void DVP_CaptrueCmd(en_functional_state_t enNewState);
en_functional_state_t DVP_GetCaptrueCmdState(void);
en_flag_status_t DVP_GetStatus(uint32_t u32Flag);
void DVP_ClearStatus(uint32_t u32Flag);
en_result_t DVP_SetSWSyncCode(const stc_dvp_sw_sync_code_t *pstcSyncCode);
en_result_t DVP_SetSWMaskCode(const stc_dvp_sw_mask_code_t *pstcMaskCode);
en_result_t DVP_CropWindowConfig(const stc_dvp_crop_window_config_t *pstcConfig);
/**
* @}
*/
#endif /* DDL_DVP_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_DVP_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_emb.h
* @brief This file contains all the functions prototypes of the EMB
* (Emergency Brake) driver library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hongjh First version
2020-07-07 Hongjh 1. Modify structure member comments for
stc_emb_monitor_port_t/stc_emb_monitor_tmr_pwm_t
2. Replace the word Timer with TMR abbreviation
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_EMB_H__
#define __HC32F4A0_EMB_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_EMB
* @{
*/
#if (DDL_EMB_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup EMB_Global_Types EMB Global Types
* @{
*/
/**
* @brief EMB monitor EMB port configuration
*/
typedef struct
{
uint32_t u32PortSel; /*!< Enable or disable EMB detect port in control function
This parameter can be a value of EMB_Portx_Selection(x=1~4) */
uint32_t u32PortLevel; /*!< EMB detect port level
This parameter can be a value of EMB_Detect_Portx_Level(x=1~4) */
uint32_t u32PortFilterDiv; /*!< EMB port filter division
This parameter can be a value of EMB_Portx_Filter_Clock_Division(x=1~4) */
} stc_emb_monitor_port_t;
/**
* @brief EMB monitor TMR4 or TMR6 PWM configuration
*/
typedef struct
{
uint32_t u32PwmSel; /*!< Enable or disable EMB detect TMR4/6 PWM x channel same phase function
This parameter can be a value of EMB_TMR4_PWM_x_Selection(x=U/V/W) or
EMB_TMR6_x_PWM_Selection(x=1~8) */
uint32_t u32PwmLevel; /*!< Detect TMR4/6 PWM x channel polarity level
This parameter can be a value of EMB_Detect_TMR4_PWM_x_Level(x=U/V/W) or
EMB_Detect_TMR6_x_PWM_Level(x=1~8) */
} stc_emb_monitor_tmr_pwm_t;
/**
* @brief EMB control TMR4 initialization configuration
*/
typedef struct
{
uint32_t u32Cmp1; /*!< Enable or disable EMB detect CMP1 result function
This parameter can be a value of @ref EMB_CMP1_Selection */
uint32_t u32Cmp2; /*!< Enable or disable EMB detect CMP2 result function
This parameter can be a value of @ref EMB_CMP2_Selection */
uint32_t u32Cmp3; /*!< Enable or disable EMB detect CMP3 result function
This parameter can be a value of @ref EMB_CMP3_Selection */
uint32_t u32Cmp4; /*!< Enable or disable EMB detect CMP4 result function
This parameter can be a value of @ref EMB_CMP4_Selection */
uint32_t u32Osc; /*!< EMB detect OSC failure function
This parameter can be a value of @ref EMB_OSC_Stop_Selection */
stc_emb_monitor_port_t stcPort1; /*!< EMB detect port EMBIN1 function
This parameter details refer @ref stc_emb_monitor_port_t structure */
stc_emb_monitor_port_t stcPort2; /*!< EMB detect port EMBIN1 function
This parameter details refer @ref stc_emb_monitor_port_t structure */
stc_emb_monitor_port_t stcPort3; /*!< EMB detect port EMBIN1 function
This parameter details refer @ref stc_emb_monitor_port_t structure */
stc_emb_monitor_port_t stcPort4; /*!< EMB detect port EMBIN1 function
This parameter details refer @ref stc_emb_monitor_port_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr4PwmU; /*!< EMB detect TMR4 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr4PwmV; /*!< EMB detect TMR4 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr4PwmW; /*!< EMB detect TMR4 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
} stc_emb_tmr4_init_t;
/**
* @brief EMB control TMR6 initialization configuration
*/
typedef struct
{
uint32_t u32Cmp1; /*!< Enable or disable EMB detect CMP1 result function
This parameter can be a value of @ref EMB_CMP1_Selection */
uint32_t u32Cmp2; /*!< Enable or disable EMB detect CMP2 result function
This parameter can be a value of @ref EMB_CMP2_Selection */
uint32_t u32Cmp3; /*!< Enable or disable EMB detect CMP3 result function
This parameter can be a value of @ref EMB_CMP3_Selection */
uint32_t u32Cmp4; /*!< Enable or disable EMB detect CMP4 result function
This parameter can be a value of @ref EMB_CMP4_Selection */
uint32_t u32Osc; /*!< EMB detect OSC failure function
This parameter can be a value of @ref EMB_OSC_Stop_Selection */
stc_emb_monitor_port_t stcPort1; /*!< EMB detect port EMBIN1 function
This parameter details refer @ref stc_emb_monitor_port_t structure */
stc_emb_monitor_port_t stcPort2; /*!< EMB detect port EMBIN1 function
This parameter details refer @ref stc_emb_monitor_port_t structure */
stc_emb_monitor_port_t stcPort3; /*!< EMB detect port EMBIN1 function
This parameter details refer @ref stc_emb_monitor_port_t structure */
stc_emb_monitor_port_t stcPort4; /*!< EMB detect port EMBIN1 function
This parameter details refer @ref stc_emb_monitor_port_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_1; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_2; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_3; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_4; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_5; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_6; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_7; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
stc_emb_monitor_tmr_pwm_t stcTmr6_8; /*!< EMB detect TMR6 function
This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
} stc_emb_tmr6_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup EMB_Global_Macros EMB Global Macros
* @{
*/
/**
* @defgroup EMB_CMP1_Selection EMB CMP1 Selection
* @{
*/
#define EMB_CMP1_DISABLE (0UL)
#define EMB_CMP1_ENABLE (EMB_CTL1_CMPEN_0)
/**
* @}
*/
/**
* @defgroup EMB_CMP2_Selection EMB CMP2 Selection
* @{
*/
#define EMB_CMP2_DISABLE (0UL)
#define EMB_CMP2_ENABLE (EMB_CTL1_CMPEN_1)
/**
* @}
*/
/**
* @defgroup EMB_CMP3_Selection EMB CMP3 Selection
* @{
*/
#define EMB_CMP3_DISABLE (0UL)
#define EMB_CMP3_ENABLE (EMB_CTL1_CMPEN_2)
/**
* @}
*/
/**
* @defgroup EMB_CMP4_Selection EMB CMP4 Selection
* @{
*/
#define EMB_CMP4_DISABLE (0UL)
#define EMB_CMP4_ENABLE (EMB_CTL1_CMPEN_3)
/**
* @}
*/
/**
* @defgroup EMB_OSC_Stop_Selection EMB OSC Stop Selection
* @{
*/
#define EMB_OSC_DISABLE (0UL)
#define EMB_OSC_ENABLE (EMB_CTL1_OSCSTPEN)
/**
* @}
*/
/**
* @defgroup EMB_TMR4_PWM_W_Selection EMB TMR4 PWM W Selection
* @{
*/
#define EMB_TMR4_PWM_W_DISABLE (0UL)
#define EMB_TMR4_PWM_W_ENABLE (EMB_CTL1_PWMSEN_0)
/**
* @}
*/
/**
* @defgroup EMB_TMR4_PWM_V_Selection EMB TMR4 PWM V Selection
* @{
*/
#define EMB_TMR4_PWM_V_DISABLE (0UL)
#define EMB_TMR4_PWM_V_ENABLE (EMB_CTL1_PWMSEN_1)
/**
* @}
*/
/**
* @defgroup EMB_TMR4_PWM_U_Selection EMB TMR4 PWM U Selection
* @{
*/
#define EMB_TMR4_PWM_U_DISABLE (0UL)
#define EMB_TMR4_PWM_U_ENABLE (EMB_CTL1_PWMSEN_2)
/**
* @}
*/
/**
* @defgroup EMB_TMR6_1_PWM_Selection EMB TMR6_1 PWM Selection
* @{
*/
#define EMB_TMR6_1_PWM_DISABLE (0UL)
#define EMB_TMR6_1_PWM_ENABLE (EMB_CTL1_PWMSEN_0)
/**
* @}
*/
/**
* @defgroup EMB_TMR6_2_PWM_Selection EMB TMR6_2 PWM Selection
* @{
*/
#define EMB_TMR6_2_PWM_DISABLE (0UL)
#define EMB_TMR6_2_PWM_ENABLE (EMB_CTL1_PWMSEN_1)
/**
* @}
*/
/**
* @defgroup EMB_TMR6_3_PWM_Selection EMB TMR6_3 PWM Selection
* @{
*/
#define EMB_TMR6_3_PWM_DISABLE (0UL)
#define EMB_TMR6_3_PWM_ENABLE (EMB_CTL1_PWMSEN_2)
/**
* @}
*/
/**
* @defgroup EMB_TMR6_4_PWM_Selection EMB TMR6_4 PWM Selection
* @{
*/
#define EMB_TMR6_4_PWM_DISABLE (0UL)
#define EMB_TMR6_4_PWM_ENABLE (EMB_CTL1_PWMSEN_3)
/**
* @}
*/
/**
* @defgroup EMB_TMR6_5_PWM_Selection EMB TMR6_5 PWM Selection
* @{
*/
#define EMB_TMR6_5_PWM_DISABLE (0UL)
#define EMB_TMR6_5_PWM_ENABLE (EMB_CTL1_PWMSEN_4)
/**
* @}
*/
/**
* @defgroup EMB_TMR6_6_PWM_Selection EMB TMR6_6 PWM Selection
* @{
*/
#define EMB_TMR6_6_PWM_DISABLE (0UL)
#define EMB_TMR6_6_PWM_ENABLE (EMB_CTL1_PWMSEN_5)
/**
* @}
*/
/**
* @defgroup EMB_TMR6_7_PWM_Selection EMB TMR6_7 PWM Selection
* @{
*/
#define EMB_TMR6_7_PWM_DISABLE (0UL)
#define EMB_TMR6_7_PWM_ENABLE (EMB_CTL1_PWMSEN_6)
/**
* @}
*/
/**
* @defgroup EMB_TMR6_8_PWM_Selection EMB TMR6_8 PWM Selection
* @{
*/
#define EMB_TMR6_8_PWM_DISABLE (0UL)
#define EMB_TMR6_8_PWM_ENABLE (EMB_CTL1_PWMSEN_7)
/**
* @}
*/
/**
* @defgroup EMB_Port1_Selection EMB Port1 Selection
* @{
*/
#define EMB_PORT1_ENABLE (EMB_CTL1_PORTINEN1)
#define EMB_PORT1_DISABLE (0UL)
/**
* @}
*/
/**
* @defgroup EMB_Port2_Selection EMB Port2 Selection
* @{
*/
#define EMB_PORT2_ENABLE (EMB_CTL1_PORTINEN2)
#define EMB_PORT2_DISABLE (0UL)
/**
* @}
*/
/**
* @defgroup EMB_Port3_Selection EMB Port3 Selection
* @{
*/
#define EMB_PORT3_ENABLE (EMB_CTL1_PORTINEN3)
#define EMB_PORT3_DISABLE (0UL)
/**
* @}
*/
/**
* @defgroup EMB_Port4_Selection EMB Port4 Selection
* @{
*/
#define EMB_PORT4_ENABLE (EMB_CTL1_PORTINEN2)
#define EMB_PORT4_DISABLE (0UL)
/**
* @}
*/
/**
* @defgroup EMB_Detect_Port1_Level EMB Detect Port1 Level
* @{
*/
#define EMB_DETECT_PORT1_LEVEL_HIGH (0UL)
#define EMB_DETECT_PORT1_LEVEL_LOW (EMB_CTL1_INVSEL1)
/**
* @}
*/
/**
* @defgroup EMB_Detect_Port2_Level EMB Detect Port2 Level
* @{
*/
#define EMB_DETECT_PORT2_LEVEL_HIGH (0UL)
#define EMB_DETECT_PORT2_LEVEL_LOW (EMB_CTL1_INVSEL2)
/**
* @}
*/
/**
* @defgroup EMB_Detect_Port3_Level EMB Detect Port3 Level
* @{
*/
#define EMB_DETECT_PORT3_LEVEL_HIGH (0UL)
#define EMB_DETECT_PORT3_LEVEL_LOW (EMB_CTL1_INVSEL3)
/**
* @}
*/
/**
* @defgroup EMB_Detect_Port4_Level EMB Detect Port4 Level
* @{
*/
#define EMB_DETECT_PORT4_LEVEL_HIGH (0UL)
#define EMB_DETECT_PORT4_LEVEL_LOW (EMB_CTL1_INVSEL4)
/**
* @}
*/
/**
* @defgroup EMB_Detect_TMR4_PWM_W_Level EMB Detect TMR4 PWM W Level
* @{
*/
#define EMB_DETECT_TMR4_PWM_W_BOTH_LOW (0UL)
#define EMB_DETECT_TMR4_PWM_W_BOTH_HIGH (EMB_CTL2_PWMLV_0)
/**
* @}
*/
/**
* @defgroup EMB_Detect_TMR4_PWM_V_Level EMB Detect TMR4 PWM V Level
* @{
*/
#define EMB_DETECT_TMR4_PWM_V_BOTH_LOW (0UL)
#define EMB_DETECT_TMR4_PWM_V_BOTH_HIGH (EMB_CTL2_PWMLV_1)
/**
* @}
*/
/**
* @defgroup EMB_Detect_TMR4_PWM_U_Level EMB Detect TMR4 PWM U Level
* @{
*/
#define EMB_DETECT_TMR4_PWM_U_BOTH_LOW (0UL)
#define EMB_DETECT_TMR4_PWM_U_BOTH_HIGH (EMB_CTL2_PWMLV_2)
/**
* @}
*/
/**
* @defgroup EMB_Detect_TMR6_1_PWM_Level EMB Detect TMR6_1 PWM Level
* @{
*/
#define EMB_DETECT_TMR6_1_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_1_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_0)
/**
* @}
*/
/**
* @defgroup EMB_Detect_TMR6_2_PWM_Level EMB Detect TMR6_2 PWM Level
* @{
*/
#define EMB_DETECT_TMR6_2_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_2_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_1)
/**
* @}
*/
/**
* @defgroup EMB_Detect_TMR6_3_PWM_Level EMB Detect TMR6_3 PWM Level
* @{
*/
#define EMB_DETECT_TMR6_3_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_3_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_2)
/**
* @}
*/
/**
* @defgroup EMB_Detect_TMR6_4_PWM_Level EMB Detect TMR6_4 PWM Level
* @{
*/
#define EMB_DETECT_TMR6_4_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_4_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_3)
/**
* @}
*/
/**
* @defgroup EMB_Detect_TMR6_5_PWM_Level EMB Detect TMR6_5 PWM Level
* @{
*/
#define EMB_DETECT_TMR6_5_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_5_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_4)
/**
* @}
*/
/**
* @defgroup EMB_Detect_TMR6_6_PWM_Level EMB Detect TMR6_6 PWM Level
* @{
*/
#define EMB_DETECT_TMR6_6_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_6_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_5)
/**
* @}
*/
/**
* @defgroup EMB_Detect_TMR6_7_PWM_Level EMB Detect TMR6_7 PWM Level
* @{
*/
#define EMB_DETECT_TMR6_7_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_7_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_6)
/**
* @}
*/
/**
* @defgroup EMB_Detect_TMR6_8_PWM_Level EMB Detect TMR6_8 PWM Level
* @{
*/
#define EMB_DETECT_TMR6_8_PWM_BOTH_LOW (0UL)
#define EMB_DETECT_TMR6_8_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_7)
/**
* @}
*/
/** @defgroup EMB_Port1_Filter_Clock_Division EMB Port1 Filter Clock Division
* @{
*/
#define EMB_PORT1_FILTER_NONE (0UL)
#define EMB_PORT1_FILTER_CLK_DIV1 (EMB_CTL2_NFEN1)
#define EMB_PORT1_FILTER_CLK_DIV8 (EMB_CTL2_NFEN1 | EMB_CTL2_NFSEL1_0)
#define EMB_PORT1_FILTER_CLK_DIV32 (EMB_CTL2_NFEN1 | EMB_CTL2_NFSEL1_1)
#define EMB_PORT1_FILTER_CLK_DIV128 (EMB_CTL2_NFEN1 | EMB_CTL2_NFSEL1)
/**
* @}
*/
/** @defgroup EMB_Port2_Filter_Clock_Division EMB Port2 Filter Clock Division
* @{
*/
#define EMB_PORT2_FILTER_NONE (0UL)
#define EMB_PORT2_FILTER_CLK_DIV1 (EMB_CTL2_NFEN2)
#define EMB_PORT2_FILTER_CLK_DIV8 (EMB_CTL2_NFEN2 | EMB_CTL2_NFSEL2_0)
#define EMB_PORT2_FILTER_CLK_DIV32 (EMB_CTL2_NFEN2 | EMB_CTL2_NFSEL2_1)
#define EMB_PORT2_FILTER_CLK_DIV128 (EMB_CTL2_NFEN2 | EMB_CTL2_NFSEL2)
/**
* @}
*/
/** @defgroup EMB_Port3_Filter_Clock_Division EMB Port3 Filter Clock Division
* @{
*/
#define EMB_PORT3_FILTER_NONE (0UL)
#define EMB_PORT3_FILTER_CLK_DIV1 (EMB_CTL2_NFEN3)
#define EMB_PORT3_FILTER_CLK_DIV8 (EMB_CTL2_NFEN3 | EMB_CTL2_NFSEL3_0)
#define EMB_PORT3_FILTER_CLK_DIV32 (EMB_CTL2_NFEN3 | EMB_CTL2_NFSEL3_1)
#define EMB_PORT3_FILTER_CLK_DIV128 (EMB_CTL2_NFEN3 | EMB_CTL2_NFSEL3)
/**
* @}
*/
/** @defgroup EMB_Port4_Filter_Clock_Division EMB Port4 Filter Clock Division
* @{
*/
#define EMB_PORT4_FILTER_NONE (0UL)
#define EMB_PORT4_FILTER_CLK_DIV1 (EMB_CTL2_NFEN4)
#define EMB_PORT4_FILTER_CLK_DIV8 (EMB_CTL2_NFEN4 | EMB_CTL2_NFSEL4_0)
#define EMB_PORT4_FILTER_CLK_DIV32 (EMB_CTL2_NFEN4 | EMB_CTL2_NFSEL4_1)
#define EMB_PORT4_FILTER_CLK_DIV128 (EMB_CTL2_NFEN4 | EMB_CTL2_NFSEL4)
/**
* @}
*/
/**
* @defgroup EMB_Flag EMB Flag
* @{
*/
#define EMB_FLAG_PWMS (EMB_STAT_PWMSF)
#define EMB_FLAG_CMP (EMB_STAT_CMPF)
#define EMB_FLAG_OSC (EMB_STAT_OSF)
#define EMB_FLAG_PORT1 (EMB_STAT_PORTINF1)
#define EMB_FLAG_PORT2 (EMB_STAT_PORTINF2)
#define EMB_FLAG_PORT3 (EMB_STAT_PORTINF3)
#define EMB_FLAG_PORT4 (EMB_STAT_PORTINF4)
/**
* @}
*/
/**
* @defgroup EMB_State EMB State
* @{
*/
#define EMB_STATE_PWMS (EMB_STAT_PWMST)
#define EMB_STATE_CMP (EMB_STAT_CMPST)
#define EMB_STATE_OSC (EMB_STAT_OSST)
#define EMB_STATE_PORT1 (EMB_STAT_PORTINST1)
#define EMB_STATE_PORT2 (EMB_STAT_PORTINST2)
#define EMB_STATE_PORT3 (EMB_STAT_PORTINST3)
#define EMB_STATE_PORT4 (EMB_STAT_PORTINST4)
/**
* @}
*/
/**
* @defgroup EMB_Interrupt EMB Interrupt
* @{
*/
#define EMB_INT_PWMS (EMB_INTEN_PWMSINTEN)
#define EMB_INT_CMP (EMB_INTEN_CMPINTEN)
#define EMB_INT_OSC (EMB_INTEN_OSINTEN)
#define EMB_INT_PORT1 (EMB_INTEN_PORTINTEN1)
#define EMB_INT_PORT2 (EMB_INTEN_PORTINTEN2)
#define EMB_INT_PORT3 (EMB_INTEN_PORTINTEN3)
#define EMB_INT_PORT4 (EMB_INTEN_PORTINTEN4)
/**
* @}
*/
/**
* @defgroup EMB_Release_TMR_PWM_Selection EMB Release TMR PWM Selection
* @{
*/
#define EMB_RELEASE_PWM_SEL_FLAG_ZERO (0UL)
#define EMB_RELEASE_PWM_SEL_STATE_ZERO (1UL)
/**
* @}
*/
/**
* @defgroup EMB_Monitor_Event EMB Monitor Event
* @{
*/
#define EMB_EVENT_PWMS (EMB_RLSSEL_PWMRSEL)
#define EMB_EVENT_CMP (EMB_RLSSEL_CMPRSEL)
#define EMB_EVENT_OSC (EMB_RLSSEL_OSRSEL)
#define EMB_EVENT_PORT1 (EMB_RLSSEL_PORTINRSEL1)
#define EMB_EVENT_PORT2 (EMB_RLSSEL_PORTINRSEL2)
#define EMB_EVENT_PORT3 (EMB_RLSSEL_PORTINRSEL3)
#define EMB_EVENT_PORT4 (EMB_RLSSEL_PORTINRSEL4)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup EMB_Global_Functions
* @{
*/
en_result_t EMB_Tmr4Init(M4_EMB_TypeDef *EMBx,
const stc_emb_tmr4_init_t *pstcInit);
en_result_t EMB_Tmr4StructInit(stc_emb_tmr4_init_t *pstcInit);
en_result_t EMB_Tmr6Init(M4_EMB_TypeDef *EMBx,
const stc_emb_tmr6_init_t *pstcInit);
en_result_t EMB_Tmr6StructInit(stc_emb_tmr6_init_t *pstcInit);
void EMB_DeInit(M4_EMB_TypeDef *EMBx);
void EMB_IntCmd(M4_EMB_TypeDef *EMBx,
uint32_t u32IntSource,
en_functional_state_t enNewState);
void EMB_SetReleasePwmMode(M4_EMB_TypeDef *EMBx,
uint32_t u32Event,
uint32_t u32Mode);
en_flag_status_t EMB_GetFlag(const M4_EMB_TypeDef *EMBx, uint32_t u32Flag);
void EMB_ClearFlag(M4_EMB_TypeDef *EMBx, uint32_t u32Flag);
en_flag_status_t EMB_GetStatus(const M4_EMB_TypeDef *EMBx,
uint32_t u32Status);
void EMB_SwBrake(M4_EMB_TypeDef *EMBx, en_functional_state_t enNewState);
/**
* @}
*/
#endif /* DDL_EMB_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_EMB_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_fcm.h
* @brief This file contains all the functions prototypes of the FCM driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Zhangxl First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_FCM_H__
#define __HC32F4A0_FCM_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_FCM
* @{
*/
#if (DDL_FCM_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup FCM_Global_Types FCM Global Types
* @{
*/
/**
* @brief FCM Init structure definition
*/
typedef struct
{
uint16_t u16LowerLimit; /*!< FCM lower limit value*/
uint16_t u16UpperLimit; /*!< FCM upper limit value*/
uint32_t u32TarClk; /*!< FCM target clock source selection, \
@ref FCM_Init_Config for details */
uint32_t u32TarClkDiv; /*!< FCM target clock source division selection,\
@ref FCM_Init_Config for details */
uint32_t u32ExRefClkEn; /*!< FCM external reference clock function config, \
@ref FCM_Init_Config for details */
uint32_t u32RefClkEdge; /*!< FCM reference clock trigger edge selection,\
@ref FCM_Init_Config for details */
uint32_t u32DigFilter; /*!< FCM digital filter function config, \
@ref FCM_Init_Config for details */
uint32_t u32RefClk; /*!< FCM reference clock source selection, \
@ref FCM_Init_Config for details */
uint32_t u32RefClkDiv; /*!< FCM reference clock source division selection, \
@ref FCM_Init_Config for details */
uint32_t u32RstEn; /*!< FCM abnormal reset function config, \
@ref FCM_Init_Config for details */
uint32_t u32IntRstSel; /*!< FCM abnormal detecting behavior selection, \
@ref FCM_Init_Config */
uint32_t u32IntType; /*!< FCM interrupt type selection, \
@ref FCM_Init_Config for details. */
} stc_fcm_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup FCM_Global_Macros FCM Global Macros
* @{
*/
/**
* @defgroup FCM_Registers_Reset_Value FCM Registers Reset Value
* @{
*/
#define FCM_REG_RESET_VALUE (0x00000000UL)
/**
* @}
*/
/**
* @defgroup FCM_Init_Config FCM init config
* @{
*/
/**
* @brief FCM target clock source selection
*/
#define FCM_TAR_CLK_XTAL (0x00UL << FCM_MCCR_MCKS_POS)
#define FCM_TAR_CLK_XTAL32 (0x01UL << FCM_MCCR_MCKS_POS)
#define FCM_TAR_CLK_HRC (0x02UL << FCM_MCCR_MCKS_POS)
#define FCM_TAR_CLK_LRC (0x03UL << FCM_MCCR_MCKS_POS)
#define FCM_TAR_CLK_SWDTLRC (0x04UL << FCM_MCCR_MCKS_POS)
#define FCM_TAR_CLK_PCLK1 (0x05UL << FCM_MCCR_MCKS_POS)
#define FCM_TAR_CLK_PLLAP (0x06UL << FCM_MCCR_MCKS_POS)
#define FCM_TAR_CLK_MRC (0x07UL << FCM_MCCR_MCKS_POS)
#define FCM_TAR_CLK_PLLHP (0x08UL << FCM_MCCR_MCKS_POS)
#define FCM_TAR_CLK_RTCLRC (0x09UL << FCM_MCCR_MCKS_POS)
/**
* @brief FCM target clock division
*/
#define FCM_TAR_CLK_DIV1 (0x00UL)
#define FCM_TAR_CLK_DIV4 (0x01UL)
#define FCM_TAR_CLK_DIV8 (0x02UL)
#define FCM_TAR_CLK_DIV32 (0x03UL)
/**
* @brief FCM external reference clock function config
*/
#define FCM_EX_REF_OFF (0x00UL)
#define FCM_EX_REF_ON (FCM_RCCR_EXREFE)
/**
* @brief FCM reference clock edge config
*/
#define FCM_REF_CLK_RISING (0x00UL)
#define FCM_REF_CLK_FALLING (FCM_RCCR_EDGES_0)
#define FCM_REF_CLK_BOTH (FCM_RCCR_EDGES_1)
/**
* @brief FCM digital filter function config
*/
#define FCM_DF_OFF (0x00UL)
#define FCM_DF_MCKS_DIV1 (FCM_RCCR_DNFS_0)
#define FCM_DF_MCKS_DIV4 (FCM_RCCR_DNFS_1)
#define FCM_DF_MCKS_DIV16 (FCM_RCCR_DNFS)
/**
* @brief FCM reference clock source selection
*/
#define FCM_REF_CLK_EXINPUT (0x00UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_XTAL (0x10UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_XTAL32 (0x11UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_HRC (0x12UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_LRC (0x13UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_SWDTLRC (0x14UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_PCLK1 (0x15UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_PCLKAP (0x16UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_MRC (0x17UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_PLLHP (0x18UL << FCM_RCCR_RCKS_POS)
#define FCM_REF_CLK_RTCLRC (0x19UL << FCM_RCCR_RCKS_POS)
/**
* @brief FCM reference clock division
*/
#define FCM_REF_CLK_DIV32 (0x00UL)
#define FCM_REF_CLK_DIV128 (0x01UL)
#define FCM_REF_CLK_DIV1024 (0x02UL)
#define FCM_REF_CLK_DIV8192 (0x03UL)
/**
* @brief FCM abnormal reset function config
*/
#define FCM_RST_OFF (0x00UL)
#define FCM_RST_ON (FCM_RIER_ERRE)
/**
* @brief FCM abnormal behavior selection
*/
#define FCM_ERR_INT (0x00UL)
#define FCM_ERR_RESET (FCM_RIER_ERRINTRS)
/**
* @brief FCM counter overflow interrupt config
*/
#define FCM_OVF_INT_OFF (0x00UL)
#define FCM_OVF_INT_ON (FCM_RIER_OVFIE)
/**
* @brief FCM measure completed interrupt config
*/
#define FCM_END_INT_OFF (0x00UL)
#define FCM_END_INT_ON (FCM_RIER_MENDIE)
/**
* @brief FCM error interrupt config
*/
#define FCM_ERR_INT_OFF (0x00UL)
#define FCM_ERR_INT_ON (FCM_RIER_ERRIE)
/**
* @brief FCM interrupt mask
*/
#define FCM_INT_MSK (FCM_OVF_INT_ON | FCM_END_INT_ON | FCM_ERR_INT_ON)
/**
* @}
*/
/**
* @defgroup FCM_Flag_Sel FCM status flag selection
* @{
*/
#define FCM_FLAG_ERR (FCM_SR_ERRF)
#define FCM_FLAG_END (FCM_SR_MENDF)
#define FCM_FLAG_OVF (FCM_SR_OVF)
#define FCM_FLAG_MSK (FCM_SR_ERRF | FCM_SR_MENDF | FCM_SR_OVF)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup FCM_Global_Functions
* @{
*/
/**
* @brief Set FCM upper limit value.
* @param [in] u16Lmt
* @retval None.
*/
__STATIC_INLINE void FCM_SetUpLimit(uint16_t u16Lmt)
{
WRITE_REG32(M4_FCM->UVR, u16Lmt);
}
/**
* @brief Set FCM lower limit value.
* @param u16Lmt
* @retval None
*/
__STATIC_INLINE void FCM_SetLowLimit(uint16_t u16Lmt)
{
WRITE_REG32(M4_FCM->LVR, u16Lmt);
}
en_result_t FCM_Init(const stc_fcm_init_t *pstcFcmInit);
en_result_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit);
void FCM_DeInit(void);
uint16_t FCM_GetCounter(void);
void FCM_SetUpLimit(uint16_t u16Lmt);
void FCM_SetLowLimit(uint16_t u16Lmt);
void FCM_SetTarClk(uint32_t u32Tar, uint32_t u32Div);
void FCM_SetRefClk(uint32_t u32Ref, uint32_t u32Div);
en_flag_status_t FCM_GetStatus(uint32_t u32Flag);
void FCM_ClearStatus(uint32_t u32Flag);
void FCM_Cmd(en_functional_state_t enNewState);
/**
* @}
*/
#endif /* DDL_FCM_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_FCM_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_fmac.h
* @brief This file contains all the functions prototypes of the FMAC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Heqb First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_FMAC_H__
#define __HC32F4A0_FMAC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_FMAC
* @{
*/
#if (DDL_FMAC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup FMAC_Global_Types FMAC Global Types
* @{
*/
/**
* @brief FMAC configuration structure
*/
typedef struct
{
uint32_t u32FiltStage; /*!< FMAC filter stage number config.
This parameter can be a value of @ref FMAC_Filter_stage.*/
uint32_t u32FiltShift; /*!< FMAC filter result right shift bits.
This parameter can be a value of @ref FMAC_Filter_shift.*/
int16_t i16FiltFactor; /*!< FMAC filter factor config.
This parameter can be set -32768~32767 */
uint32_t u32IntCmd; /*!< Enable or disable FMAC interrupt.
This parameter can be a value of @ref FMAC_Interrupt_Definition.*/
}stc_fmac_init_t;
/**
* @brief FMAC result definition
*/
typedef struct
{
uint32_t u32ResultHigh; /*!< The high value of the result. */
uint32_t u32ResultLow; /*!< The low value of the result. */
} stc_fmac_result_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup FMAC_Global_Macros FMAC Global Macros
* @{
*/
/**
* @defgroup FMAC_ENABLE FMAC Enable or Disable
* @{
*/
#define FMAC_FUNC_ENABLE (FMAC_ENR_FMACEN)
#define FMAC_FUNC_DISABLE (0x0UL)
/**
* @}
*/
/**
* @defgroup FMAC_Interrupt_Definition FMAC interrupt definition
* @{
*/
#define FMAC_INT_ENABLE (FMAC_IER_INTEN)
#define FMAC_INT_DISABLE (0x0UL)
/**
* @}
*/
/** @defgroup FMAC_Filter_shift FMAC filter shift times
* @{
*/
#define FMAC_FILTER_SHIFT_0BIT (0U)
#define FMAC_FILTER_SHIFT_1BIT (1U)
#define FMAC_FILTER_SHIFT_2BIT (2U)
#define FMAC_FILTER_SHIFT_3BIT (3U)
#define FMAC_FILTER_SHIFT_4BIT (4U)
#define FMAC_FILTER_SHIFT_5BIT (5U)
#define FMAC_FILTER_SHIFT_6BIT (6U)
#define FMAC_FILTER_SHIFT_7BIT (7U)
#define FMAC_FILTER_SHIFT_8BIT (8U)
#define FMAC_FILTER_SHIFT_9BIT (9U)
#define FMAC_FILTER_SHIFT_10BIT (10U)
#define FMAC_FILTER_SHIFT_11BIT (11U)
#define FMAC_FILTER_SHIFT_12BIT (12U)
#define FMAC_FILTER_SHIFT_13BIT (13U)
#define FMAC_FILTER_SHIFT_14BIT (14U)
#define FMAC_FILTER_SHIFT_15BIT (15U)
#define FMAC_FILTER_SHIFT_16BIT (16U)
#define FMAC_FILTER_SHIFT_17BIT (17U)
#define FMAC_FILTER_SHIFT_18BIT (18U)
#define FMAC_FILTER_SHIFT_19BIT (19U)
#define FMAC_FILTER_SHIFT_20BIT (20U)
#define FMAC_FILTER_SHIFT_21BIT (21U)
/**
* @}
*/
/** @defgroup FMAC_Filter_stage FMAC filter stage number
* @{
*/
#define FMAC_FILTER_STAGE_0 (0U)
#define FMAC_FILTER_STAGE_1 (1U)
#define FMAC_FILTER_STAGE_2 (2U)
#define FMAC_FILTER_STAGE_3 (3U)
#define FMAC_FILTER_STAGE_4 (4U)
#define FMAC_FILTER_STAGE_5 (5U)
#define FMAC_FILTER_STAGE_6 (6U)
#define FMAC_FILTER_STAGE_7 (7U)
#define FMAC_FILTER_STAGE_8 (8U)
#define FMAC_FILTER_STAGE_9 (9U)
#define FMAC_FILTER_STAGE_10 (10U)
#define FMAC_FILTER_STAGE_11 (11U)
#define FMAC_FILTER_STAGE_12 (12U)
#define FMAC_FILTER_STAGE_13 (13U)
#define FMAC_FILTER_STAGE_14 (14U)
#define FMAC_FILTER_STAGE_15 (15U)
#define FMAC_FILTER_STAGE_16 (16U)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup FMAC_Global_Functions
* @{
*/
en_result_t FMAC_StructInit(stc_fmac_init_t* pstcInitStruct);
void FMAC_DeInit(M4_FMAC_TypeDef* FMACx);
en_result_t FMAC_Init(M4_FMAC_TypeDef* FMACx, const stc_fmac_init_t *pstcFmacInit);
void FMAC_Cmd(M4_FMAC_TypeDef* FMACx, en_functional_state_t enNewState);
void FMAC_SetResultShift(M4_FMAC_TypeDef* FMACx, uint32_t u32ShiftNum);
void FMAC_SetStageFactor(M4_FMAC_TypeDef* FMACx, uint32_t u32FilterStage, int16_t i16Factor);
void FMAC_IntCmd(M4_FMAC_TypeDef* FMACx, en_functional_state_t enNewState);
void FMAC_FIRInput(M4_FMAC_TypeDef* FMACx, int16_t i16Factor);
en_flag_status_t FMAC_GetStatus(const M4_FMAC_TypeDef* FMACx);
en_result_t FMAC_GetResult(const M4_FMAC_TypeDef* FMACx, stc_fmac_result_t *stcResult);
/**
* @}
*/
#endif /* DDL_FMAC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_FMAC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_hash.h
* @brief This file contains all the functions prototypes of the HASH driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Heqb First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_HASH_H__
#define __HC32F4A0_HASH_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_HASH
* @{
*/
#if (DDL_HASH_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup HASH_Global_Macros HASH Global Macros
* @{
*/
#define HASH_GROUP_LEN (64U)
#define LAST_GROUP_MAX_LEN (56U)
/** @defgroup HASH_Mode HASH Mode
* @{
*/
#define HASH_MODE_SHA_256 (0x00000000UL) /*!< SHA_256 Operating mode */
#define HASH_MODE_HMAC (0x00000010UL) /*!< HMAC Operating mode */
/**
* @}
*/
/**
* @defgroup HASH_Key_Len HASH Key Length
* @{
*/
#define HASH_KEY_LEN_LONG (HASH_CR_LKEY) /*!< Key length > 64 Bytes */
#define HASH_KEY_LEN_SHORT (0x0UL) /*!< Key length <= 64 Bytes */
/**
* @}
*/
/**
* @defgroup HASH_Interrupt_Definition HASH Interrupt Definition
* @{
*/
#define HASH_INT_GROUP (HASH_CR_HEIE) /*!< A set of data operations complete interrupt */
#define HASH_INT_ALL (HASH_CR_HCIE) /*!< All data operations complete interrupt */
/**
* @}
*/
/**
* @defgroup HASH_Msg_Group HASH Messages Group
* @{
*/
#define HASH_MSG_GRP_FIRST (HASH_CR_FST_GRP) /*!< The first group of messages or keys */
#define HASH_MSG_GRP_END (HASH_CR_KMSG_END) /*!< The last group of messages or keys */
#define HASH_MSG_GRP_ONLY_ONE (HASH_CR_FST_GRP | \
HASH_CR_KMSG_END) /*!< Only one set of message or key */
/**
* @}
*/
/**
* @defgroup HASH_Status HASH Status
* @{
*/
#define HASH_FLAG_START (HASH_CR_START) /*!< Operation in progress */
#define HASH_FLAG_BUSY (HASH_CR_BUSY) /*!< HASH in operation */
#define HASH_FLAG_CYC_END (HASH_CR_CYC_END) /*!< key or message operation completed */
#define HASH_FLAG_HMAC_END (HASH_CR_HMAC_END) /*!< HMAC operation completed */
/**
* @}
*/
/**
* @defgroup HASH_Common_Trigger_Sel HASH common trigger source select
* @{
*/
#define HASH_COM_TRIG1 (AOS_HASH_ITRGSELA_COMTRG_EN_0)
#define HASH_COM_TRIG2 (AOS_HASH_ITRGSELA_COMTRG_EN_1)
#define HASH_COM_TRIG_MASk (AOS_HASH_ITRGSELA_COMTRG_EN)
/**
* @}
*/
/**
* @defgroup HASH_Common_Trigger_Reg_Sel HASH common trigger cource select
* @{
*/
#define HASH_TRIG_REG_BLKCOM (0U) /*!< DMA block transfer complete register */
#define HASH_TRIG_REG_TRNCOM (1U) /*!< DMA transfer complete register*/
/**
* @}
*/
/**
* @defgroup HASH_Trigger_Source_Sel HASH Trigger Source Select
* @{
*/
#define HASH_TRG_SRC_DMA1_BTC0 (EVT_DMA1_BTC0) /*!< Select the DMA1 ch0 block transfer complete */
#define HASH_TRG_SRC_DMA1_BTC1 (EVT_DMA1_BTC1) /*!< Select the DMA1 ch1 block transfer complete */
#define HASH_TRG_SRC_DMA1_BTC2 (EVT_DMA1_BTC2) /*!< Select the DMA1 ch2 block transfer complete */
#define HASH_TRG_SRC_DMA1_BTC3 (EVT_DMA1_BTC3) /*!< Select the DMA1 ch3 block transfer complete */
#define HASH_TRG_SRC_DMA1_BTC4 (EVT_DMA1_BTC4) /*!< Select the DMA1 ch4 block transfer complete */
#define HASH_TRG_SRC_DMA1_BTC5 (EVT_DMA1_BTC5) /*!< Select the DMA1 ch5 block transfer complete */
#define HASH_TRG_SRC_DMA1_BTC6 (EVT_DMA1_BTC6) /*!< Select the DMA1 ch6 block transfer complete */
#define HASH_TRG_SRC_DMA1_BTC7 (EVT_DMA1_BTC7) /*!< Select the DMA1 ch7 block transfer complete */
#define HASH_TRG_SRC_DMA1_TC0 (EVT_DMA1_TC0) /*!< Select the DMA1 ch0 transfer complete*/
#define HASH_TRG_SRC_DMA1_TC1 (EVT_DMA1_TC1) /*!< Select the DMA1 ch1 transfer complete*/
#define HASH_TRG_SRC_DMA1_TC2 (EVT_DMA1_TC2) /*!< Select the DMA1 ch2 transfer complete*/
#define HASH_TRG_SRC_DMA1_TC3 (EVT_DMA1_TC3) /*!< Select the DMA1 ch3 transfer complete*/
#define HASH_TRG_SRC_DMA1_TC4 (EVT_DMA1_TC4) /*!< Select the DMA1 ch4 transfer complete*/
#define HASH_TRG_SRC_DMA1_TC5 (EVT_DMA1_TC5) /*!< Select the DMA1 ch5 transfer complete*/
#define HASH_TRG_SRC_DMA1_TC6 (EVT_DMA1_TC6) /*!< Select the DMA1 ch6 transfer complete*/
#define HASH_TRG_SRC_DMA1_TC7 (EVT_DMA1_TC7) /*!< Select the DMA1 ch7 transfer complete*/
#define HASH_TRG_SRC_DMA2_BTC0 (EVT_DMA2_BTC0) /*!< Select the DMA2 ch0 block transfer complete */
#define HASH_TRG_SRC_DMA2_BTC1 (EVT_DMA2_BTC1) /*!< Select the DMA2 ch1 block transfer complete */
#define HASH_TRG_SRC_DMA2_BTC2 (EVT_DMA2_BTC2) /*!< Select the DMA2 ch2 block transfer complete */
#define HASH_TRG_SRC_DMA2_BTC3 (EVT_DMA2_BTC3) /*!< Select the DMA2 ch3 block transfer complete */
#define HASH_TRG_SRC_DMA2_BTC4 (EVT_DMA2_BTC4) /*!< Select the DMA2 ch4 block transfer complete */
#define HASH_TRG_SRC_DMA2_BTC5 (EVT_DMA2_BTC5) /*!< Select the DMA2 ch5 block transfer complete */
#define HASH_TRG_SRC_DMA2_BTC6 (EVT_DMA2_BTC6) /*!< Select the DMA2 ch6 block transfer complete */
#define HASH_TRG_SRC_DMA2_BTC7 (EVT_DMA2_BTC7) /*!< Select the DMA2 ch7 block transfer complete */
#define HASH_TRG_SRC_DMA2_TC0 (EVT_DMA2_TC0) /*!< Select the DMA2 ch0 transfer complete*/
#define HASH_TRG_SRC_DMA2_TC1 (EVT_DMA2_TC1) /*!< Select the DMA2 ch1 transfer complete*/
#define HASH_TRG_SRC_DMA2_TC2 (EVT_DMA2_TC2) /*!< Select the DMA2 ch2 transfer complete*/
#define HASH_TRG_SRC_DMA2_TC3 (EVT_DMA2_TC3) /*!< Select the DMA2 ch3 transfer complete*/
#define HASH_TRG_SRC_DMA2_TC4 (EVT_DMA2_TC4) /*!< Select the DMA2 ch4 transfer complete*/
#define HASH_TRG_SRC_DMA2_TC5 (EVT_DMA2_TC5) /*!< Select the DMA2 ch5 transfer complete*/
#define HASH_TRG_SRC_DMA2_TC6 (EVT_DMA2_TC6) /*!< Select the DMA2 ch6 transfer complete*/
#define HASH_TRG_SRC_DMA2_TC7 (EVT_DMA2_TC7) /*!< Select the DMA2 ch7 transfer complete*/
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup HASH_Global_Functions
* @{
*/
en_result_t HASH_Calculate(const void *pvSrcData,
uint32_t u32SrcDataSize,
uint8_t au8MsgDigest[]);
en_result_t HMAC_Calculate(const void *pvSrcData,
uint32_t u32SrcDataSize,
const uint8_t au8Key[],
uint32_t u32KeyLength,
uint8_t au8MsgDigest[]);
en_result_t HASH_Start(void);
en_result_t HASH_IntCmd(uint32_t u32HashInt, en_functional_state_t enNewState);
en_result_t HASH_SetMode(uint32_t u32HashMode);
en_result_t HASH_SetKeyLength(uint32_t u32KeyLen);
en_result_t HASH_MsgGrpConfig(uint32_t u32MsgGroup);
en_result_t HASH_ClearStatus(uint32_t u32ClearFlag);
void HASH_SetTriggerSrc(en_event_src_t enSrc);
void HASH_ComTriggerCmd(uint8_t u8TrigReg, uint32_t u32ComTrig, \
en_functional_state_t enNewState);
en_flag_status_t HASH_GetStatus(uint32_t u32HashFlag);
void HASH_GetResult(uint8_t au8MsgDigest[]);
/**
* @}
*/
#endif /* DDL_HASH_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_HASH_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_hrpwm.h
* @brief Head file for HRPWM module.
*
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Wangmin First version
2020-09-07 Wangmin Modify channel delay configure function
parameter type.
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_HRPWM_H__
#define __HC32F4A0_HRPWM_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_HRPWM
* @{
*/
#if (DDL_HRPWM_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup HRPWM_Global_Macros HRPWM Global Macros
* @{
*/
#define HRPWM_CH_MIN (1UL)
#define HRPWM_CH_MAX (16UL)
#define HRPWM_CH_DELAY_NUM_MIN (1U)
#define HRPWM_CH_DELAY_NUM_MAX (256U)
/** @defgroup HRPWM_Calibrate_Unit_Define HRPWM Calibrate unit define
* @{
*/
#define HRPWM_CAL_UNIT0 (0x00UL)
#define HRPWM_CAL_UNIT1 (0x01UL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup HRPWM_Global_Functions
* @{
*/
/* HRPWM Judge the condition of calibration function */
en_functional_state_t HRPWM_ConditionConfirm(void);
/* Process for getting HRPWM Calibrate function code */
en_result_t HRPWM_CalibrateProcess(uint32_t u32Unit, uint8_t* pu8Code);
/* HRPWM Calibrate function enable or disable for specified unit */
void HRPWM_CalibrateCmd(uint32_t u32Unit, en_functional_state_t enNewState);
/* HRPWM Calibrate function status get for specified unit */
en_functional_state_t HRPWM_GetCalibrateStd(uint32_t u32Unit);
/* HRPWM Calibrate code get for specified unit */
uint8_t HRPWM_GetCalCode(uint32_t u32Unit);
/* HRPWM function enable or disable for specified channel */
void HRPWM_CHCmd(uint32_t u32Ch, en_functional_state_t enNewState);
/* HRPWM positive edge adjust enable or disable for specified channel */
void HRPWM_CHPositAdjCmd(uint32_t u32Ch, en_functional_state_t enNewState);
/* HRPWM negative edge adjust enable or disable for specified channel */
void HRPWM_CHNegatAdjCmd(uint32_t u32Ch, en_functional_state_t enNewState);
/* HRPWM positive edge adjust delay counts configration for specified channel */
void HRPWM_CHPositCfg(uint32_t u32Ch, uint8_t u8DelayNum);
/* HRPWM negative edge adjust delay counts configration for specified channel */
void HRPWM_CHNegatCfg(uint32_t u32Ch, uint8_t u8DelayNum);
/**
* @}
*/
#endif /* DDL_HRPWM_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_HRPWM_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_i2c.h
* @brief This file contains all the functions prototypes of the Inter-Integrated
* Circuit(I2C).
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hexiao First version
2020-07-15 Hexiao Modify I2C_SmBusCmd to I2C_SetMode
2020-08-31 Hexiao Remove invalid clock division value
2020-10-30 Hexiao Optimize data transfer api,etc.
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_I2C_H__
#define __HC32F4A0_I2C_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_I2C
* @{
*/
#if (DDL_I2C_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup I2C_Global_Types I2C Global Types
* @{
*/
/**
* @brief I2c configuration structure
*/
typedef struct
{
uint32_t u32ClkDiv; /*!< I2C clock division for pclk3*/
uint32_t u32Baudrate; /*!< I2C baudrate config*/
uint32_t u32SclTime; /*!< The SCL rising and falling time, count of T(pclk3)*/
}stc_i2c_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup I2C_Global_Macros I2C Global Macros
* @{
*/
/** @defgroup I2C_Buadrate_Max I2C baudrate max value
* @{
*/
#define I2C_BAUDRATE_MAX (400000UL)
/**
* @}
*/
/** @defgroup I2C_Mode Peripheral Mode
* @{
*/
#define I2C_MODE_I2C (0UL)
#define I2C_MODE_SMBUS (2UL)
/**
* @}
*/
/** @defgroup I2C_Transfer_Direction I2C transfer direction
* @{
*/
#define I2C_DIR_TX (0x0U)
#define I2C_DIR_RX (0x1U)
/**
* @}
*/
/** @defgroup I2C_Addr_Config I2C address configuration
* @{
*/
#define I2C_ADDR_MODE_7BIT (0x0U)
#define I2C_ADDR_MODE_10BIT (I2C_SLR0_ADDRMOD0)
/**
* @}
*/
/** @defgroup I2C_Clock_division I2C clock division
* @{
*/
#define I2C_CLK_DIV1 (0UL)
#define I2C_CLK_DIV2 (1UL)
#define I2C_CLK_DIV4 (2UL)
#define I2C_CLK_DIV8 (3UL)
#define I2C_CLK_DIV16 (4UL)
#define I2C_CLK_DIV32 (5UL)
#define I2C_CLK_DIV64 (6UL)
#define I2C_CLK_DIV128 (7UL)
/**
* @}
*/
/** @defgroup I2C_Address_Num I2C address number
* @{
*/
#define I2C_ADDR_0 (0UL)
#define I2C_ADDR_1 (1UL)
/**
* @}
*/
/** @defgroup I2C_Ack_Type I2C ack type
* @{
*/
#define I2C_ACK (0UL)
#define I2C_NACK (I2C_CR1_ACK)
/**
* @}
*/
/** @defgroup I2C_Smbus_Match_Cfg I2C smbus address match configuration
* @{
*/
#define I2C_SMBUS_MATCH_ALRT (I2C_CR1_SMBALRTEN)
#define I2C_SMBUS_MATCH_DEFAULT (I2C_CR1_SMBDEFAULTEN)
#define I2C_SMBUS_MATCH_HOST (I2C_CR1_SMBHOSTEN)
/**
* @}
*/
/** @defgroup I2C_Smbus_clear_mask I2C smbus clear mask
* @{
*/
#define I2C_SMBUS_CONFIG_CLEARMASK (I2C_CR1_SMBALRTEN|I2C_CR1_SMBDEFAULTEN|I2C_CR1_SMBHOSTEN)
/**
* @}
*/
/** @defgroup I2C_Digital_Filter_mode I2C digital filter mode
* @{
*/
#define I2C_DIG_FILTMODE_1CYCLE (0UL << I2C_FLTR_DNF_POS)
#define I2C_DIG_FILTMODE_2CYCLE (1UL << I2C_FLTR_DNF_POS)
#define I2C_DIG_FILTMODE_3CYCLE (2UL << I2C_FLTR_DNF_POS)
#define I2C_DIG_FILTMODE_4CYCLE (3UL << I2C_FLTR_DNF_POS)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup I2C_Global_Functions
* @{
*/
/* Initialization and Configuration **********************************/
void I2C_DeInit(M4_I2C_TypeDef* I2Cx);
en_result_t I2C_StructInit(stc_i2c_init_t* pstcI2C_InitStruct);
en_result_t I2C_Init(M4_I2C_TypeDef* I2Cx, const stc_i2c_init_t *pstcI2C_InitStruct, float32_t *pf32Err);
en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* I2Cx, const stc_i2c_init_t *pstcI2C_InitStruct, float32_t *pf32Err);
void I2C_SlaveAddrCmd(M4_I2C_TypeDef* I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState);
void I2C_SlaveAddrConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr);
void I2C_SetMode(M4_I2C_TypeDef* I2Cx, uint32_t u32Mode);
void I2C_Cmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_FastAckCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_BusWaitCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_SoftwareResetCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_IntCmd(M4_I2C_TypeDef* I2Cx, uint32_t u32IntEn, en_functional_state_t enNewState);
void I2C_ClkHighTimeoutConfig(M4_I2C_TypeDef* I2Cx, uint16_t u16TimeoutH);
void I2C_ClkLowTimeoutConfig(M4_I2C_TypeDef* I2Cx, uint16_t u16TimeoutL);
void I2C_ClkHighTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_ClkLowTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_ClkTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_SmbusConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState);
void I2C_DigitalFilterConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32DigFilterMode);
void I2C_DigitalFilterCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_AnalogFilterCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_GeneralCallCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
/* Start/Restart/Stop ************************************************/
void I2C_GenerateStart(M4_I2C_TypeDef* I2Cx);
void I2C_GenerateReStart(M4_I2C_TypeDef* I2Cx);
void I2C_GenerateStop(M4_I2C_TypeDef* I2Cx);
/* Status management *************************************************/
en_flag_status_t I2C_GetStatus(const M4_I2C_TypeDef *I2Cx, uint32_t u32StatusBit);
void I2C_ClearStatus(M4_I2C_TypeDef* I2Cx, uint32_t u32StatusBit);
/* Data transfer *****************************************************/
void I2C_WriteDataReg(M4_I2C_TypeDef* I2Cx, uint8_t u8Data);
uint8_t I2C_ReadDataReg(const M4_I2C_TypeDef *I2Cx);
void I2C_AckConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32AckConfig);
/* High level functions for reference ********************************/
en_result_t I2C_Start(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout);
en_result_t I2C_Restart(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout);
en_result_t I2C_TransAddr(M4_I2C_TypeDef* I2Cx, uint8_t u8Addr, uint8_t u8Dir, uint32_t u32Timeout);
en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout);
en_result_t I2C_TransData(M4_I2C_TypeDef* I2Cx, uint8_t const pau8TxData[], uint32_t u32Size, uint32_t u32Timeout);
en_result_t I2C_Receive(M4_I2C_TypeDef* I2Cx, uint8_t pau8RxData[], uint32_t u32Size, uint32_t u32Timeout);
en_result_t I2C_Stop(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout);
en_result_t I2C_MasterReceiveAndStop(M4_I2C_TypeDef* I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout);
/**
* @}
*/
#endif /* DDL_I2C_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_I2C_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_i2s.h
* @brief This file contains all the functions prototypes of the I2S driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_I2S_H__
#define __HC32F4A0_I2S_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_I2S
* @{
*/
#if (DDL_I2S_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup I2S_Global_Types I2S Global Types
* @{
*/
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint32_t u32ClockSrc; /*!< Specifies the clock source of I2S.
This parameter can be a value of @ref I2S_Clock_Source */
uint32_t u32Mode; /*!< Specifies the master/slave mode of I2S.
This parameter can be a value of @ref I2S_Mode */
uint32_t u32ComProtocol; /*!< Specifies the communication protocol of I2S.
This parameter can be a value of @ref I2S_Com_Protocol */
uint32_t u32TransMode; /*!< Specifies the transmission mode for the I2S communication.
This parameter can be a value of @ref I2S_Trans_Mode */
uint32_t u32AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint32_t u32ChLen; /*!< Specifies the channel length for the I2S communication.
This parameter can be a value of @ref I2S_Channel_Length */
uint32_t u32DataLen; /*!< Specifies the data length for the I2S communication.
This parameter can be a value of @ref I2S_Data_Length */
uint32_t u32MCKOutput; /*!< Specifies the validity of the MCK output for I2S.
This parameter can be a value of @ref I2S_MCK_Output */
uint32_t u32TransFIFOLevel; /*!< Specifies the level of transfer FIFO.
This parameter can be a value of @ref I2S_Trans_Level */
uint32_t u32ReceiveFIFOLevel; /*!< Specifies the level of receive FIFO.
This parameter can be a value of @ref I2S_Receive_Level */
} stc_i2s_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup I2S_Global_Macros I2S Global Macros
* @{
*/
/**
* @defgroup I2S_Clock_Source I2S Clock Source
* @{
*/
#define I2S_CLK_SRC_PLL (I2S_CTRL_I2SPLLSEL) /*!< Internal PLL Clock */
#define I2S_CLK_SRC_EXT (I2S_CTRL_CLKSEL) /*!< External Clock */
/**
* @}
*/
/**
* @defgroup I2S_Mode I2S Mode
* @{
*/
#define I2S_MD_MASTER (0UL) /*!< Master mode */
#define I2S_MD_SLAVE (I2S_CTRL_WMS) /*!< Slave mode */
/**
* @}
*/
/**
* @defgroup I2S_Com_Protocol I2S Communication Protocol
* @{
*/
#define I2S_COM_PROTOCOL_PHILLIPS (0UL) /*!< Phillips protocol */
#define I2S_COM_PROTOCOL_MSB (I2S_CFGR_I2SSTD_0) /*!< MSB justified protocol */
#define I2S_COM_PROTOCOL_LSB (I2S_CFGR_I2SSTD_1) /*!< LSB justified protocol */
#define I2S_COM_PROTOCOL_PCM_SHORT (I2S_CFGR_I2SSTD) /*!< PCM short-frame protocol */
#define I2S_COM_PROTOCOL_PCM_LONG (I2S_CFGR_I2SSTD | I2S_CFGR_PCMSYNC) /*!< PCM long-frame protocol */
/**
* @}
*/
/**
* @defgroup I2S_Trans_Mode I2S Transfer Mode
* @{
*/
#define I2S_TRANS_MD_HALF_DUPLEX_RX (0UL) /*!< Receive only and half duplex mode */
#define I2S_TRANS_MD_HALF_DUPLEX_TX (I2S_CTRL_SDOE) /*!< Send only and half duplex mode */
#define I2S_TRANS_MD_FULL_DUPLEX (I2S_CTRL_DUPLEX | I2S_CTRL_SDOE) /*!< Full duplex mode */
/**
* @}
*/
/**
* @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
#define I2S_AUDIO_FREQ_192K (192000UL) /*!< FS = 192000Hz */
#define I2S_AUDIO_FREQ_96K (96000UL) /*!< FS = 96000Hz */
#define I2S_AUDIO_FREQ_48K (48000UL) /*!< FS = 48000Hz */
#define I2S_AUDIO_FREQ_44K (44100UL) /*!< FS = 44100Hz */
#define I2S_AUDIO_FREQ_32K (32000UL) /*!< FS = 32000Hz */
#define I2S_AUDIO_FREQ_22K (22050UL) /*!< FS = 22050Hz */
#define I2S_AUDIO_FREQ_16K (16000UL) /*!< FS = 16000Hz */
#define I2S_AUDIO_FREQ_8K (8000UL) /*!< FS = 8000Hz */
#define I2S_AUDIO_FREQ_DEFAULT (2UL)
/**
* @}
*/
/**
* @defgroup I2S_Channel_Length I2S Channel Length
* @{
*/
#define I2S_CH_LEN_16BIT (0UL) /*!< Channel length is 16bits */
#define I2S_CH_LEN_32BIT (I2S_CFGR_CHLEN) /*!< Channel length is 32bits */
/**
* @}
*/
/**
* @defgroup I2S_Data_Length I2S Data Length
* @{
*/
#define I2S_DATA_LEN_16BIT (0UL) /*!< Transfer data length is 16bits */
#define I2S_DATA_LEN_24BIT (I2S_CFGR_DATLEN_0) /*!< Transfer data length is 24bits */
#define I2S_DATA_LEN_32BIT (I2S_CFGR_DATLEN_1) /*!< Transfer data length is 32bits */
/**
* @}
*/
/**
* @defgroup I2S_MCK_Output I2S MCK Output
* @{
*/
#define I2S_MCK_OUTPUT_DISABLE (0UL) /*!< Disable the drive clock(MCK) output */
#define I2S_MCK_OUTPUT_ENABLE (I2S_CTRL_MCKOE) /*!< Enable the drive clock(MCK) output */
/**
* @}
*/
/**
* @defgroup I2S_Trans_Level I2S Transfer Level
* @{
*/
#define I2S_TRANS_LVL0 (0x00UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 0 */
#define I2S_TRANS_LVL1 (0x01UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 1 */
#define I2S_TRANS_LVL2 (0x02UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 2 */
#define I2S_TRANS_LVL3 (0x03UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 3 */
#define I2S_TRANS_LVL4 (0x04UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 4 */
/**
* @}
*/
/**
* @defgroup I2S_Receive_Level I2S Receive Level
* @{
*/
#define I2S_RECEIVE_LVL0 (0x00UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 0 */
#define I2S_RECEIVE_LVL1 (0x01UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 1 */
#define I2S_RECEIVE_LVL2 (0x02UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 2 */
#define I2S_RECEIVE_LVL3 (0x03UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 3 */
#define I2S_RECEIVE_LVL4 (0x04UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 4 */
/**
* @}
*/
/**
* @defgroup I2S_Com_Func I2S Communication Function
* @{
*/
#define I2S_FUNC_TXE (I2S_CTRL_TXE) /*!< Transfer function */
#define I2S_FUNC_RXE (I2S_CTRL_RXE) /*!< Receive function */
#define I2S_FUNC_ALL (I2S_FUNC_TXE | I2S_FUNC_RXE)
/**
* @}
*/
/**
* @defgroup I2S_Reset_Type I2S Reset Type
* @{
*/
#define I2S_RST_TYPE_SW (I2S_CTRL_SRST) /*!< I2S software reset */
#define I2S_RST_TYPE_CODEC (I2S_CTRL_CODECRC) /*!< Reset codec of I2S */
#define I2S_RST_TYPE_FIFO (I2S_CTRL_FIFOR) /*!< Reset FIFO of I2S */
#define I2S_RST_TYPE_ALL (I2S_RST_TYPE_SW | I2S_RST_TYPE_CODEC | I2S_RST_TYPE_FIFO)
/**
* @}
*/
/**
* @defgroup I2S_Interrupt I2S Interrupt
* @{
*/
#define I2S_INT_TX (I2S_CTRL_TXIE) /*!< Transfer interrupt */
#define I2S_INT_RX (I2S_CTRL_RXIE) /*!< Receive interrupt */
#define I2S_INT_ERR (I2S_CTRL_EIE) /*!< Communication error interrupt */
#define I2S_INT_ALL (I2S_INT_TX | I2S_INT_RX | I2S_INT_ERR)
/**
* @}
*/
/**
* @defgroup I2S_Flag I2S Flag
* @{
*/
#define I2S_FLAG_TX_ALARM (I2S_SR_TXBA) /*!< Transfer buffer alarm flag */
#define I2S_FLAG_RX_ALARM (I2S_SR_RXBA) /*!< Receive buffer alarm flag */
#define I2S_FLAG_TX_EMPTY (I2S_SR_TXBE) /*!< Transfer buffer empty flag */
#define I2S_FLAG_TX_FULL (I2S_SR_TXBF) /*!< Transfer buffer full flag */
#define I2S_FLAG_RX_EMPTY (I2S_SR_RXBE) /*!< Receive buffer empty flag */
#define I2S_FLAG_RX_FULL (I2S_SR_RXBF) /*!< Receive buffer full flag */
#define I2S_FLAG_TX_ERR (I2S_ER_TXERR << 16U) /*!< Transfer overflow or underflow flag */
#define I2S_FLAG_RX_ERR (I2S_ER_RXERR << 16U) /*!< Receive overflow flag */
#define I2S_FLAG_ALL (I2S_FLAG_TX_ALARM | I2S_FLAG_RX_ALARM | I2S_FLAG_TX_EMPTY | \
I2S_FLAG_TX_FULL | I2S_FLAG_RX_EMPTY | I2S_FLAG_RX_FULL | \
I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR)
#define I2S_CLR_FLAG_ALL (I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup I2S_Global_Functions
* @{
*/
/* Initialization and configuration functions */
void I2S_DeInit(M4_I2S_TypeDef *I2Sx);
en_result_t I2S_Init(M4_I2S_TypeDef *I2Sx, const stc_i2s_init_t *pstcI2sInit);
en_result_t I2S_StructInit(stc_i2s_init_t *pstcI2sInit);
void I2S_SetSWReset(M4_I2S_TypeDef *I2Sx, uint32_t u32ResetType);
void I2S_SetTransMode(M4_I2S_TypeDef *I2Sx, uint32_t u32Mode);
void I2S_SetTransFIFOLevel(M4_I2S_TypeDef *I2Sx, uint32_t u32Level);
void I2S_SetReceiveFIFOLevel(M4_I2S_TypeDef *I2Sx, uint32_t u32Level);
void I2S_SetComProtocol(M4_I2S_TypeDef *I2Sx, uint32_t u32Protocol);
en_result_t I2S_SetAudioFreq(M4_I2S_TypeDef *I2Sx, uint32_t u32Freq);
void I2S_MCKOutputCmd(M4_I2S_TypeDef *I2Sx, en_functional_state_t enNewState);
void I2S_FuncCmd(M4_I2S_TypeDef* I2Sx, uint32_t u32Func, en_functional_state_t enNewState);
/* Transfer and receive data functions */
void I2S_WriteData(M4_I2S_TypeDef *I2Sx, uint32_t u32Data);
uint32_t I2S_ReadData(const M4_I2S_TypeDef *I2Sx);
en_result_t I2S_Trans(M4_I2S_TypeDef *I2Sx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout);
en_result_t I2S_Receive(const M4_I2S_TypeDef *I2Sx, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout);
en_result_t I2S_TransReceive(M4_I2S_TypeDef *I2Sx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout);
/* Interrupt and flag management functions */
void I2S_IntCmd(M4_I2S_TypeDef *I2Sx, uint32_t u32IntType, en_functional_state_t enNewState);
en_flag_status_t I2S_GetStatus(const M4_I2S_TypeDef *I2Sx, uint32_t u32Flag);
void I2S_ClearStatus(M4_I2S_TypeDef *I2Sx, uint32_t u32Flag);
/**
* @}
*/
#endif /* DDL_I2S_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_I2S_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_icg.h
* @brief This file contains all the Macro Definitions of the ICG driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_ICG_H__
#define __HC32F4A0_ICG_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_ICG
* @{
*/
#if (DDL_ICG_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup ICG_Global_Macros ICG Global Macros
* @{
*/
/**
* @defgroup ICG_SWDT_Reset_State ICG SWDT Reset State
* @{
*/
#define ICG_SWDT_RESET_AUTOSTART (0UL) /*!< SWDT Auto Start after reset */
#define ICG_SWDT_RESET_STOP (ICG_ICG0_SWDTAUTS) /*!< SWDT stop after reset */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_Trigger_Type ICG SWDT Trigger Type
* @{
*/
#define ICG_SWDT_TRIG_INT (0UL) /*!< SWDT trigger interrupt */
#define ICG_SWDT_TRIG_RESET (ICG_ICG0_SWDTITS) /*!< SWDT trigger reset */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_Counter_Cycle ICG SWDT Counter Cycle
* @{
*/
#define ICG_SWDT_COUNTER_CYCLE_256 (0UL) /*!< 256 clock cycle */
#define ICG_SWDT_COUNTER_CYCLE_4096 (ICG_ICG0_SWDTPERI_0) /*!< 4096 clock cycle */
#define ICG_SWDT_COUNTER_CYCLE_16384 (ICG_ICG0_SWDTPERI_1) /*!< 16384 clock cycle */
#define ICG_SWDT_COUNTER_CYCLE_65536 (ICG_ICG0_SWDTPERI) /*!< 65536 clock cycle */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_Clock_Division ICG SWDT Clock Division
* @{
*/
#define ICG_SWDT_CLOCK_DIV1 (0UL) /*!< SWDTCLK */
#define ICG_SWDT_CLOCK_DIV16 (ICG_ICG0_SWDTCKS_2) /*!< SWDTCLK/16 */
#define ICG_SWDT_CLOCK_DIV32 (ICG_ICG0_SWDTCKS_2 | ICG_ICG0_SWDTCKS_0) /*!< SWDTCLK/32 */
#define ICG_SWDT_CLOCK_DIV64 (ICG_ICG0_SWDTCKS_2 | ICG_ICG0_SWDTCKS_1) /*!< SWDTCLK/64 */
#define ICG_SWDT_CLOCK_DIV128 (ICG_ICG0_SWDTCKS_2 | ICG_ICG0_SWDTCKS_1 | ICG_ICG0_SWDTCKS_0) /*!< SWDTCLK/128 */
#define ICG_SWDT_CLOCK_DIV256 (ICG_ICG0_SWDTCKS_3) /*!< SWDTCLK/256 */
#define ICG_SWDT_CLOCK_DIV2048 (ICG_ICG0_SWDTCKS_3 | ICG_ICG0_SWDTCKS_1 | ICG_ICG0_SWDTCKS_0) /*!< SWDTCLK/2048 */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_Refresh_Range ICG SWDT Refresh Range
* @{
*/
#define ICG_SWDT_RANGE_0TO100PCT (0UL) /*!< 0%~100% */
#define ICG_SWDT_RANGE_0TO25PCT (ICG_ICG0_SWDTWDPT_0) /*!< 0%~25% */
#define ICG_SWDT_RANGE_25TO50PCT (ICG_ICG0_SWDTWDPT_1) /*!< 25%~50% */
#define ICG_SWDT_RANGE_0TO50PCT (ICG_ICG0_SWDTWDPT_1 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~50% */
#define ICG_SWDT_RANGE_50TO75PCT (ICG_ICG0_SWDTWDPT_2) /*!< 50%~75% */
#define ICG_SWDT_RANGE_0TO25PCT_50TO75PCT (ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~25% & 50%~75% */
#define ICG_SWDT_RANGE_25TO75PCT (ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_1)) /*!< 25%~75% */
#define ICG_SWDT_RANGE_0TO75PCT (ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_1 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~75% */
#define ICG_SWDT_RANGE_75TO100PCT (ICG_ICG0_SWDTWDPT_3) /*!< 75%~100% */
#define ICG_SWDT_RANGE_0TO25PCT_75TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~25% & 75%~100% */
#define ICG_SWDT_RANGE_25TO50PCT_75TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_1)) /*!< 25%~50% & 75%~100% */
#define ICG_SWDT_RANGE_0TO50PCT_75TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_1 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~50% & 75%~100% */
#define ICG_SWDT_RANGE_50TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_2)) /*!< 50%~100% */
#define ICG_SWDT_RANGE_0TO25PCT_50TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~25% & 50%~100% */
#define ICG_SWDT_RANGE_25TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_1)) /*!< 25%~100% */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_LPM_Count ICG SWDT Low Power Mode Count
* @brief SWDT count control in the sleep/stop mode
* @{
*/
#define ICG_SWDT_LPM_COUNT_CONTINUE (0UL) /*!< SWDT count continue in the sleep/stop mode */
#define ICG_SWDT_LPM_COUNT_STOP (ICG_ICG0_SWDTSLPOFF) /*!< SWDT count stop in the sleep/stop mode */
/**
* @}
*/
/**
* @defgroup ICG_WDT_Reset_State ICG WDT Reset State
* @{
*/
#define ICG_WDT_RESET_AUTOSTART (0UL) /*!< WDT Auto Start after reset */
#define ICG_WDT_RESET_STOP (ICG_ICG0_WDTAUTS) /*!< WDT stop after reset */
/**
* @}
*/
/**
* @defgroup ICG_WDT_Trigger_Type ICG WDT Trigger Type
* @{
*/
#define ICG_WDT_TRIG_INT (0UL) /*!< WDT trigger interrupt */
#define ICG_WDT_TRIG_RESET (ICG_ICG0_WDTITS) /*!< WDT trigger reset */
/**
* @}
*/
/**
* @defgroup ICG_WDT_Counter_Cycle ICG WDT Counter Cycle
* @{
*/
#define ICG_WDT_COUNTER_CYCLE_256 (0UL) /*!< 256 clock cycle */
#define ICG_WDT_COUNTER_CYCLE_4096 (ICG_ICG0_WDTPERI_0) /*!< 4096 clock cycle */
#define ICG_WDT_COUNTER_CYCLE_16384 (ICG_ICG0_WDTPERI_1) /*!< 16384 clock cycle */
#define ICG_WDT_COUNTER_CYCLE_65536 (ICG_ICG0_WDTPERI) /*!< 65536 clock cycle */
/**
* @}
*/
/**
* @defgroup ICG_WDT_Clock_Division ICG WDT Clock Division
* @{
*/
#define ICG_WDT_CLOCK_DIV4 (ICG_ICG0_WDTCKS_1) /*!< PCLK3/4 */
#define ICG_WDT_CLOCK_DIV64 (ICG_ICG0_WDTCKS_2 | ICG_ICG0_WDTCKS_1) /*!< PCLK3/64 */
#define ICG_WDT_CLOCK_DIV128 (ICG_ICG0_WDTCKS_2 | ICG_ICG0_WDTCKS_1 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/128 */
#define ICG_WDT_CLOCK_DIV256 (ICG_ICG0_WDTCKS_3) /*!< PCLK3/256 */
#define ICG_WDT_CLOCK_DIV512 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/512 */
#define ICG_WDT_CLOCK_DIV1024 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_1) /*!< PCLK3/1024 */
#define ICG_WDT_CLOCK_DIV2028 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_1 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/2048 */
#define ICG_WDT_CLOCK_DIV8192 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_2 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/8192 */
/**
* @}
*/
/**
* @defgroup ICG_WDT_Refresh_Range ICG WDT Refresh Range
* @{
*/
#define ICG_WDT_RANGE_0TO100PCT (0UL) /*!< 0%~100% */
#define ICG_WDT_RANGE_0TO25PCT (ICG_ICG0_WDTWDPT_0) /*!< 0%~25% */
#define ICG_WDT_RANGE_25TO50PCT (ICG_ICG0_WDTWDPT_1) /*!< 25%~50% */
#define ICG_WDT_RANGE_0TO50PCT (ICG_ICG0_WDTWDPT_1 | ICG_ICG0_WDTWDPT_0) /*!< 0%~50% */
#define ICG_WDT_RANGE_50TO75PCT (ICG_ICG0_WDTWDPT_2) /*!< 50%~75% */
#define ICG_WDT_RANGE_0TO25PCT_50TO75PCT (ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_0) /*!< 0%~25% & 50%~75% */
#define ICG_WDT_RANGE_25TO75PCT (ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_1) /*!< 25%~75% */
#define ICG_WDT_RANGE_0TO75PCT (ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_1 | ICG_ICG0_WDTWDPT_0) /*!< 0%~75% */
#define ICG_WDT_RANGE_75TO100PCT (ICG_ICG0_WDTWDPT_3) /*!< 75%~100% */
#define ICG_WDT_RANGE_0TO25PCT_75TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_0) /*!< 0%~25% & 75%~100% */
#define ICG_WDT_RANGE_25TO50PCT_75TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_1) /*!< 25%~50% & 75%~100% */
#define ICG_WDT_RANGE_0TO50PCT_75TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_1 | ICG_ICG0_WDTWDPT_0) /*!< 0%~50% & 75%~100% */
#define ICG_WDT_RANGE_50TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_2) /*!< 50%~100% */
#define ICG_WDT_RANGE_0TO25PCT_50TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_0) /*!< 0%~25% & 50%~100% */
#define ICG_WDT_RANGE_25TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_1) /*!< 25%~100% */
/**
* @}
*/
/**
* @defgroup ICG_WDT_LPM_Count ICG WDT Low Power Mode Count
* @brief WDT count control in the sleep mode
* @{
*/
#define ICG_WDT_LPM_COUNT_CONTINUE (0UL) /*!< WDT count continue in the sleep mode */
#define ICG_WDT_LPM_COUNT_STOP (ICG_ICG0_WDTSLPOFF) /*!< WDT count stop in the sleep mode */
/**
* @}
*/
/**
* @defgroup ICG_HRC_Frequency_Select ICG HRC Frequency Select
* @{
*/
#define ICG_HRC_FREQ_20MHZ (0UL) /*!< HRC frequency 20MHZ */
#define ICG_HRC_FREQ_16MHZ (ICG_ICG1_HRCFREQSEL) /*!< HRC frequency 16MHZ */
/**
* @}
*/
/**
* @defgroup ICG_HRC_Reset_State ICG HRC Reset State
* @{
*/
#define ICG_HRC_RESET_OSCILLATION (0UL) /*!< HRC Oscillation after reset */
#define ICG_HRC_RESET_STOP (ICG_ICG1_HRCSTOP) /*!< HRC stop after reset */
/**
* @}
*/
/**
* @defgroup ICG_BOR_Voltage_Threshold ICG BOR Voltage Threshold
* @{
*/
#define ICG_BOR_VOL_THRESHOLD_1P9 (0UL) /*!< BOR voltage threshold 1.9V */
#define ICG_BOR_VOL_THRESHOLD_2P0 (ICG_ICG1_BOR_LEV_0) /*!< BOR voltage threshold 2.0V */
#define ICG_BOR_VOL_THRESHOLD_2P1 (ICG_ICG1_BOR_LEV_1) /*!< BOR voltage threshold 2.1V */
#define ICG_BOR_VOL_THRESHOLD_2P3 (ICG_ICG1_BOR_LEV) /*!< BOR voltage threshold 2.3V */
/**
* @}
*/
/**
* @defgroup ICG_BOR_Reset_State ICG BOR Reset State
* @{
*/
#define ICG_BOR_RESET_ENABLE (0UL) /*!< Enable BOR voltage detection after reset */
#define ICG_BOR_RESET_DISABLE (ICG_ICG1_BORDIS) /*!< Disable BOR voltage detection after reset */
/**
* @}
*/
/**
* @defgroup ICG_FLASH_Bank_Reset_State ICG FLASH Bank Reset State
* @{
*/
#define ICG_FLASH_BANK_1 (0xFFFFFFFFUL) /*!< After reset, 1MBytes flash are provided by bank0 */
#define ICG_FLASH_BANK_12 (0x004B4B4BUL) /*!< After reset, 1MBytes flash are provided by bank0 and bank1 with 512Bytes each */
/**
* @}
*/
/**
* @defgroup ICG_FLASH_Protect_Reset_State ICG FLASH Protect Reset State
* @brief Enable or disable D-BUS read protection for addresses 0x00000000 - 0x0001FFFF
* @{
*/
#define ICG_FLASH_PROTECT_RESET_ENABLE (0x00004450UL) /*!< Enable D-BUS read protection after reset */
#define ICG_FLASH_PROTECT_RESET_DISABLE (0xFFFFFFFFUL) /*!< Disable D-BUS read protection after reset */
/**
* @}
*/
/**
* @}
*/
/**
* @defgroup ICG_Register_Configuration ICG Register Configuration
* @{
*/
/**
*******************************************************************************
* @defgroup ICG_SWDT_Preload_Configuration ICG SWDT Preload Configuration
* @{
*******************************************************************************
*/
/* SWDT register config */
#define ICG0_RB_SWDT_AUTS (ICG_SWDT_RESET_STOP)
#define ICG0_RB_SWDT_ITS (ICG_SWDT_TRIG_INT)
#define ICG0_RB_SWDT_PERI (ICG_SWDT_COUNTER_CYCLE_65536)
#define ICG0_RB_SWDT_CKS (ICG_SWDT_CLOCK_DIV2048)
#define ICG0_RB_SWDT_WDPT (ICG_SWDT_RANGE_0TO100PCT)
#define ICG0_RB_SWDT_SLTPOFF (ICG_SWDT_LPM_COUNT_CONTINUE)
/* SWDT register value */
#define ICG0_RB_SWDT_CONFIG (ICG0_RB_SWDT_AUTS | ICG0_RB_SWDT_ITS | \
ICG0_RB_SWDT_PERI | ICG0_RB_SWDT_CKS | \
ICG0_RB_SWDT_WDPT | ICG0_RB_SWDT_SLTPOFF)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_WDT_Preload_Configuration ICG WDT Preload Configuration
* @{
*******************************************************************************
*/
/* WDT register config */
#define ICG0_RB_WDT_AUTS (ICG_WDT_RESET_STOP)
#define ICG0_RB_WDT_ITS (ICG_WDT_TRIG_INT)
#define ICG0_RB_WDT_PERI (ICG_WDT_COUNTER_CYCLE_65536)
#define ICG0_RB_WDT_CKS (ICG_WDT_CLOCK_DIV8192)
#define ICG0_RB_WDT_WDPT (ICG_WDT_RANGE_0TO100PCT)
#define ICG0_RB_WDT_SLTPOFF (ICG_WDT_LPM_COUNT_CONTINUE)
/* WDT register value */
#define ICG0_RB_WDT_CONFIG (ICG0_RB_WDT_AUTS | ICG0_RB_WDT_ITS | \
ICG0_RB_WDT_PERI | ICG0_RB_WDT_CKS | \
ICG0_RB_WDT_WDPT | ICG0_RB_WDT_SLTPOFF)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_HRC_Preload_Configuration ICG HRC Preload Configuration
* @{
*******************************************************************************
*/
/* HRC register config */
#define ICG1_RB_HRC_FREQSEL (ICG_HRC_FREQ_16MHZ)
#define ICG1_RB_HRC_STOP (ICG_HRC_RESET_STOP)
/* HRC register value */
#define ICG1_RB_HRC_CONFIG (ICG1_RB_HRC_FREQSEL | ICG1_RB_HRC_STOP)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_BOR_Preload_Configuration ICG BOR Preload Configuration
* @{
*******************************************************************************
*/
/* BOR register config */
#define ICG1_RB_BOR_LEV (ICG_BOR_VOL_THRESHOLD_2P3)
#define ICG1_RB_BOR_DIS (ICG_BOR_RESET_DISABLE)
/* BOR register value */
#define ICG1_RB_BOR_CONFIG (ICG1_RB_BOR_LEV | ICG1_RB_BOR_DIS)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_FLASH_Bank_Preload_Configuration ICG FLASH Bank Preload Configuration
* @{
*******************************************************************************
*/
/* FLASH Bank register value */
#define ICG2_RB_FLASH_BANK_CONFIG (ICG_FLASH_BANK_1)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_FLASH_Protect_Preload_Configuration ICG FLASH Protect Preload Configuration
* @{
*******************************************************************************
*/
/* FLASH Read Protect register value */
#define ICG3_RB_FLASH_PROTECT_CONFIG (ICG_FLASH_PROTECT_RESET_DISABLE)
/**
* @}
*/
/**
* @}
*/
/**
* @defgroup ICG_Register_Value ICG Register Value
* @{
*/
/* ICG register value */
#define ICG_REG_CFG0_CONSTANT (ICG0_RB_WDT_CONFIG | ICG0_RB_SWDT_CONFIG | 0xE000E000UL)
#define ICG_REG_CFG1_CONSTANT (ICG1_RB_BOR_CONFIG | ICG1_RB_HRC_CONFIG | 0xFFF8FEFEUL)
#define ICG_REG_CFG2_CONSTANT (ICG2_RB_FLASH_BANK_CONFIG | 0xFF000000UL)
#define ICG_REG_CFG3_CONSTANT (ICG3_RB_FLASH_PROTECT_CONFIG | 0xFFFF0000UL)
/* ICG reserved value */
#define ICG_RESERVED_CONSTANT (0xFFFFFFFFUL)
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
#endif /* DDL_ICG_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_ICG_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_keyscan.h
* @brief This file contains all the functions prototypes of the KEYSCAN driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Zhangxl First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_KEYSCAN_H__
#define __HC32F4A0_KEYSCAN_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_KEYSCAN
* @{
*/
#if (DDL_KEYSCAN_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup KEYSCAN_Global_Types KEYSCAN Global Types
* @{
*/
/**
* @brief KEYSCAN configuration
*/
typedef struct
{
uint32_t u32HizCycle; /*!< Specifies the KEYSCAN Hiz cycles.
This parameter can be a value of @ref KEYSCAN_Hiz_Cycle_Sel */
uint32_t u32LowCycle; /*!< Specifies the KEYSCAN low cycles.
This parameter can be a value of @ref KEYSCAN_Low_Cycle_Sel */
uint32_t u32KeyClk; /*!< Specifies the KEYSCAN low cycles.
This parameter can be a value of @ref KEYSCAN_Clock_Sel */
uint32_t u32KeyOut; /*!< Specifies the KEYSCAN low cycles.
This parameter can be a value of @ref KEYSCAN_Keyout_Sel */
uint32_t u32KeyIn; /*!< Specifies the KEYSCAN low cycles.
This parameter can be a value of @ref KEYSCAN_Keyin_Sel */
} stc_keyscan_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup KEYSCAN_Global_Macros KEYSCAN Global Macros
* @{
*/
/**
* @defgroup KEYSCAN_Hiz_Cycle_Sel KEYSCAN Hiz cycles during low ouput selection
* @{
*/
#define KEYSCAN_HIZ_CLC_4 (0x00UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 4 cycles during low ouput */
#define KEYSCAN_HIZ_CLC_8 (0x01UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 8 cycles during low ouput */
#define KEYSCAN_HIZ_CLC_16 (0x02UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 16 cycles during low ouput */
#define KEYSCAN_HIZ_CLC_32 (0x03UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 32 cycles during low ouput */
#define KEYSCAN_HIZ_CLC_64 (0x04UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 64 cycles during low ouput */
#define KEYSCAN_HIZ_CLC_256 (0x05UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 256 cycles during low ouput */
#define KEYSCAN_HIZ_CLC_512 (0x06UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 512 cycles during low ouput */
#define KEYSCAN_HIZ_CLC_1024 (0x07UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 1024 cycles during low ouput */
/**
* @}
*/
/**
* @defgroup KEYSCAN_Low_Cycle_Sel KEYSCAN low level output cycles selection
* @{
*/
#define KEYSCAN_LOW_CLC_4 (0x02UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^2=4 cycles */
#define KEYSCAN_LOW_CLC_8 (0x03UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^3=8 cycles */
#define KEYSCAN_LOW_CLC_16 (0x04UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^4=16 cycles */
#define KEYSCAN_LOW_CLC_32 (0x05UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^5=32 cycles */
#define KEYSCAN_LOW_CLC_64 (0x06UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^6=64 cycles */
#define KEYSCAN_LOW_CLC_128 (0x07UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^7=128 cycles */
#define KEYSCAN_LOW_CLC_256 (0x08UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^8=256 cycles */
#define KEYSCAN_LOW_CLC_512 (0x09UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^9=512 cycles */
#define KEYSCAN_LOW_CLC_1K (0x0AUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^10=1K cycles */
#define KEYSCAN_LOW_CLC_2K (0x0BUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^11=2K cycles */
#define KEYSCAN_LOW_CLC_4K (0x0CUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^12=4K cycles */
#define KEYSCAN_LOW_CLC_8K (0x0DUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^13=8K cycles */
#define KEYSCAN_LOW_CLC_16K (0x0EUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^14=16K cycles */
#define KEYSCAN_LOW_CLC_32K (0x0FUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^15=32K cycles */
#define KEYSCAN_LOW_CLC_64K (0x10UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^16=64K cycles */
#define KEYSCAN_LOW_CLC_128K (0x11UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^17=128K cycles */
#define KEYSCAN_LOW_CLC_256K (0x12UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^18=256K cycles */
#define KEYSCAN_LOW_CLC_512K (0x13UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^19=512K cycles */
#define KEYSCAN_LOW_CLC_1M (0x14UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^20=1M cycles */
#define KEYSCAN_LOW_CLC_2M (0x15UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^21=2M cycles */
#define KEYSCAN_LOW_CLC_4M (0x16UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^22=4M cycles */
#define KEYSCAN_LOW_CLC_8M (0x17UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^23=8M cycles */
#define KEYSCAN_LOW_CLC_16M (0x18UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^24=16M cycles */
/**
* @}
*/
/**
* @defgroup KEYSCAN_Clock_Sel KEYSCAN scan clock selection
* @{
*/
#define KEYSCAN_CLK_HCLK (0x00UL) /*!< Use as HCLK KEYSCAN clock */
#define KEYSCAN_CLK_LRC (KEYSCAN_SCR_CKSEL_0) /*!< Use as LRC KEYSCAN clock */
#define KEYSCAN_CLK_XTAL32 (KEYSCAN_SCR_CKSEL_1) /*!< Use as XTAL32 KEYSCAN clock */
/**
* @}
*/
/**
* @defgroup KEYSCAN_Keyout_Sel KEYSCAN keyout pins selection
* @{
*/
#define KEYSCAN_OUT_0T1 (0x01UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 1 are selected */
#define KEYSCAN_OUT_0T2 (0x02UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 2 are selected */
#define KEYSCAN_OUT_0T3 (0x03UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 3 are selected */
#define KEYSCAN_OUT_0T4 (0x04UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 4 are selected */
#define KEYSCAN_OUT_0T5 (0x05UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 5 are selected */
#define KEYSCAN_OUT_0T6 (0x06UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 6 are selected */
#define KEYSCAN_OUT_0T7 (0x07UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 7 are selected */
/**
* @}
*/
/**
* @defgroup KEYSCAN_Keyin_Sel KEYSCAN keyin pins selection
* @{
*/
#define KEYSCAN_IN_0 (KEYSCAN_SCR_KEYINSEL_0) /*!< KEYIN(EIRQ) 0 is selected */
#define KEYSCAN_IN_1 (KEYSCAN_SCR_KEYINSEL_1) /*!< KEYIN(EIRQ) 1 is selected */
#define KEYSCAN_IN_2 (KEYSCAN_SCR_KEYINSEL_2) /*!< KEYIN(EIRQ) 2 is selected */
#define KEYSCAN_IN_3 (KEYSCAN_SCR_KEYINSEL_3) /*!< KEYIN(EIRQ) 3 is selected */
#define KEYSCAN_IN_4 (KEYSCAN_SCR_KEYINSEL_4) /*!< KEYIN(EIRQ) 4 is selected */
#define KEYSCAN_IN_5 (KEYSCAN_SCR_KEYINSEL_5) /*!< KEYIN(EIRQ) 5 is selected */
#define KEYSCAN_IN_6 (KEYSCAN_SCR_KEYINSEL_6) /*!< KEYIN(EIRQ) 6 is selected */
#define KEYSCAN_IN_7 (KEYSCAN_SCR_KEYINSEL_7) /*!< KEYIN(EIRQ) 7 is selected */
#define KEYSCAN_IN_8 (KEYSCAN_SCR_KEYINSEL_8) /*!< KEYIN(EIRQ) 8 is selected */
#define KEYSCAN_IN_9 (KEYSCAN_SCR_KEYINSEL_9) /*!< KEYIN(EIRQ) 9 is selected */
#define KEYSCAN_IN_10 (KEYSCAN_SCR_KEYINSEL_10) /*!< KEYIN(EIRQ) 10 is selected */
#define KEYSCAN_IN_11 (KEYSCAN_SCR_KEYINSEL_11) /*!< KEYIN(EIRQ) 11 is selected */
#define KEYSCAN_IN_12 (KEYSCAN_SCR_KEYINSEL_12) /*!< KEYIN(EIRQ) 12 is selected */
#define KEYSCAN_IN_13 (KEYSCAN_SCR_KEYINSEL_13) /*!< KEYIN(EIRQ) 13 is selected */
#define KEYSCAN_IN_14 (KEYSCAN_SCR_KEYINSEL_14) /*!< KEYIN(EIRQ) 14 is selected */
#define KEYSCAN_IN_15 (KEYSCAN_SCR_KEYINSEL_15) /*!< KEYIN(EIRQ) 15 is selected */
#define KEYSCAN_IN_MASK (KEYSCAN_SCR_KEYINSEL) /*!< KEYIN(EIRQ) mask */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup KEYSCAN_Global_Functions
* @{
*/
/**
* @brief Get KEYOUT index.
* @param None.
* @retval uint32_t: KEYOUT index 0~7.
*/
__STATIC_INLINE uint32_t KEYSCAN_GetKeyoutIdx(void)
{
return READ_REG32_BIT(M4_KEYSCAN->SSR, KEYSCAN_SSR_INDEX);
}
en_result_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit);
en_result_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit);
void KEYSCAN_Cmd(en_functional_state_t enNewState);
/**
* @}
*/
#endif /* DDL_KEYSCAN_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_KEYSCAN_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_mau.h
* @brief This file contains all the functions prototypes of the MAU driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hexiao First version
2020-07-15 Hexiao Modify MAU_SqrtStartCmd to MAU_SqrtStart
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_MAU_H__
#define __HC32F4A0_MAU_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
#include "hc32f4a0_utility.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_MAU
* @{
*/
#if (DDL_MAU_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup MAU_Global_Macros MAU Global Macros
* @{
*/
#define MAU_SQRT_TIMEOUT (HCLK_VALUE / 10000UL)/* About 1mS timeout */
#define MAU_SQRT_OUTPUT_LSHIFT_MAX (16U)
#define MAU_SIN_Q15_SCALAR (0x8000UL)
#define MAU_SIN_ANGIDX_TOTAL (0x1000UL)
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup MAU_Global_Functions
* @{
*/
void MAU_SqrtInit(M4_MAU_TypeDef *MAUx, uint8_t u8LShBitsNumber, en_functional_state_t enIntNewState);
void MAU_SqrtDeInit(M4_MAU_TypeDef *MAUx);
void MAU_SqrtResultLShiftCfg(M4_MAU_TypeDef *MAUx, uint8_t u8LShBitsNumber);
void MAU_SqrtIntCmd(M4_MAU_TypeDef *MAUx, en_functional_state_t enNewState);
void MAU_SqrtWriteDataReg(M4_MAU_TypeDef *MAUx, uint32_t u32Radicand);
en_flag_status_t MAU_SqrtGetStatus(const M4_MAU_TypeDef *MAUx);
uint32_t MAU_SqrtReadDataReg(const M4_MAU_TypeDef *MAUx);
void MAU_SqrtStart(M4_MAU_TypeDef* MAUx);
en_result_t MAU_Sqrt(M4_MAU_TypeDef *MAUx, uint32_t u32Radicand, uint32_t *pu32Result);
int16_t MAU_Sin(M4_MAU_TypeDef *MAUx, uint16_t u16AngleIdx);
/**
* @}
*/
#endif /* DDL_MAU_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_MAU_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_mpu.h
* @brief This file contains all the functions prototypes of the MPU driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_MPU_H__
#define __HC32F4A0_MPU_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_MPU
* @{
*/
#if (DDL_MPU_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup MPU_Global_Types MPU Global Types
* @{
*/
/**
* @brief MPU Unit configure structure definition
*/
typedef struct
{
uint32_t u32ExceptionType; /*!< Specifies the type of exception that occurs when the unit accesses a protected region.
This parameter can be a value of @ref MPU_Exception_Type */
uint32_t u32BackgroundWriteProtect; /*!< Specifies the unit's write protection for the background space.
This parameter can be a value of @ref MPU_Background_Write_Protect */
uint32_t u32BackgroundReadProtect; /*!< Specifies the unit's read protection for the background space
This parameter can be a value of @ref MPU_Background_Read_Protect */
} stc_mpu_unit_config_t;
/**
* @brief MPU Init structure definition
*/
typedef struct
{
stc_mpu_unit_config_t stcDma1; /*!< Configure storage protection unit of DMA1 */
stc_mpu_unit_config_t stcDma2; /*!< Configure storage protection unit of DMA2 */
stc_mpu_unit_config_t stcUsbFSDma; /*!< Configure storage protection unit of USBFS_DMA */
stc_mpu_unit_config_t stcUsbHSDma; /*!< Configure storage protection unit of USBHS_DMA */
stc_mpu_unit_config_t stcEthDma; /*!< Configure storage protection unit of ETH_DMA */
} stc_mpu_init_t;
/**
* @brief MPU Region Permission structure definition
*/
typedef struct
{
uint32_t u32WriteProtect; /*!< Specifies the unit's write protection for the region.
This parameter can be a value of @ref MPU_Region_Write_Protect */
uint32_t u32ReadProtect; /*!< Specifies the unit's read protection for the region.
This parameter can be a value of @ref MPU_Region_Read_Protect */
} stc_mpu_region_permission_t;
/**
* @brief MPU region initialization structure definition
* @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region,
* and the low 'u32Size+1' bits are fixed at 0.
*/
typedef struct
{
uint32_t u32BaseAddr; /*!< Specifies the base address of the region.
This parameter can be a number between 0UL and 0xFFFFFFE0UL */
uint32_t u32Size; /*!< Specifies the size of the region.
This parameter can be a value of @ref MPU_Region_Size */
stc_mpu_region_permission_t stcDma1; /*!< Specifies the DMA1 access permission for the region */
stc_mpu_region_permission_t stcDma2; /*!< Specifies the DMA2 access permission for the region */
stc_mpu_region_permission_t stcUsbFSDma; /*!< Specifies the USBFS_DMA access permission for the region */
stc_mpu_region_permission_t stcUsbHSDma; /*!< Specifies the USBHS_DMA access permission for the region */
stc_mpu_region_permission_t stcEthDma; /*!< Specifies the ETH_DMA access permission for the region */
} stc_mpu_region_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup MPU_Global_Macros MPU Global Macros
* @{
*/
/**
* @defgroup MPU_Unit_Type MPU Unit Type
* @{
*/
#define MPU_UNIT_DMA1 (0x01UL) /*!< System DMA_1 MPU */
#define MPU_UNIT_DMA2 (0x02UL) /*!< System DMA_2 MPU */
#define MPU_UNIT_USBFS_DMA (0x04UL) /*!< USBFS_DMA MPU */
#define MPU_UNIT_USBHS_DMA (0x08UL) /*!< USBHS_DMA MPU */
#define MPU_UNIT_ETH_DMA (0x10UL) /*!< ETH_DMA MPU */
#define MPU_UNIT_ALL (0x1FUL)
/**
* @}
*/
/**
* @defgroup MPU_Region_Number MPU Region Number
* @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'.
* @{
*/
#define MPU_REGION_NUM0 (0x00UL) /*!< MPU region number 0 */
#define MPU_REGION_NUM1 (0x01UL) /*!< MPU region number 1 */
#define MPU_REGION_NUM2 (0x02UL) /*!< MPU region number 2 */
#define MPU_REGION_NUM3 (0x03UL) /*!< MPU region number 3 */
#define MPU_REGION_NUM4 (0x04UL) /*!< MPU region number 4 */
#define MPU_REGION_NUM5 (0x05UL) /*!< MPU region number 5 */
#define MPU_REGION_NUM6 (0x06UL) /*!< MPU region number 6 */
#define MPU_REGION_NUM7 (0x07UL) /*!< MPU region number 7 */
#define MPU_REGION_NUM8 (0x08UL) /*!< MPU region number 8 */
#define MPU_REGION_NUM9 (0x09UL) /*!< MPU region number 9 */
#define MPU_REGION_NUM10 (0x0AUL) /*!< MPU region number 10 */
#define MPU_REGION_NUM11 (0x0BUL) /*!< MPU region number 11 */
#define MPU_REGION_NUM12 (0x0CUL) /*!< MPU region number 12 */
#define MPU_REGION_NUM13 (0x0DUL) /*!< MPU region number 13 */
#define MPU_REGION_NUM14 (0x0EUL) /*!< MPU region number 14 */
#define MPU_REGION_NUM15 (0x0FUL) /*!< MPU region number 15 */
/**
* @}
*/
/**
* @defgroup MPU_Background_Write_Protect MPU Background Write Protect
* @{
*/
#define MPU_BKGRD_WR_PROTECT_DISABLE (0UL) /*!< Disable write protection of background space */
#define MPU_BKGRD_WR_PROTECT_ENABLE (MPU_S1CR_SMPU1BWP) /*!< Enable write protection of background space */
/**
* @}
*/
/**
* @defgroup MPU_Background_Read_Protect MPU Background Read Protect
* @{
*/
#define MPU_BKGRD_RD_PROTECT_DISABLE (0UL) /*!< Disable read protection of background space */
#define MPU_BKGRD_RD_PROTECT_ENABLE (MPU_S1CR_SMPU1BRP) /*!< Enable read protection of background space */
/**
* @}
*/
/**
* @defgroup MPU_Exception_Type MPU Exception Type
* @{
*/
#define MPU_EXP_TYPE_NONE (0UL) /*!< The host unit access protection regions will be ignored */
#define MPU_EXP_TYPE_BUS_ERR (MPU_S1CR_SMPU1ACT_0) /*!< The host unit access protection regions will be ignored and a bus error will be triggered */
#define MPU_EXP_TYPE_NMI (MPU_S1CR_SMPU1ACT_1) /*!< The host unit access protection regions will be ignored and a NMI interrupt will be triggered */
#define MPU_EXP_TYPE_RST (MPU_S1CR_SMPU1ACT) /*!< The host unit access protection regions will trigger the reset */
/**
* @}
*/
/**
* @defgroup MPU_Region_Write_Protect MPU Region Write Protect
* @{
*/
#define MPU_REGION_WR_PROTECT_DISABLE (0UL) /*!< Disable write protection of the region */
#define MPU_REGION_WR_PROTECT_ENABLE (MPU_S1RGWP_S1RG0WP) /*!< Enable write protection of the region */
/**
* @}
*/
/**
* @defgroup MPU_Region_Read_Protect MPU Region Read Protect
* @{
*/
#define MPU_REGION_RD_PROTECT_DISABLE (0UL) /*!< Disable read protection of the region */
#define MPU_REGION_RD_PROTECT_ENABLE (MPU_S1RGRP_S1RG0RP) /*!< Enable read protection of the region */
/**
* @}
*/
/**
* @defgroup MPU_Region_Size MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32BYTE (0x04UL) /*!< 32 Byte */
#define MPU_REGION_SIZE_64BYTE (0x05UL) /*!< 64 Byte */
#define MPU_REGION_SIZE_128BYTE (0x06UL) /*!< 126 Byte */
#define MPU_REGION_SIZE_256BYTE (0x07UL) /*!< 256 Byte */
#define MPU_REGION_SIZE_512BYTE (0x08UL) /*!< 512 Byte */
#define MPU_REGION_SIZE_1KBYTE (0x09UL) /*!< 1K Byte */
#define MPU_REGION_SIZE_2KBYTE (0x0AUL) /*!< 2K Byte */
#define MPU_REGION_SIZE_4KBYTE (0x0BUL) /*!< 4K Byte */
#define MPU_REGION_SIZE_8KBYTE (0x0CUL) /*!< 8K Byte */
#define MPU_REGION_SIZE_16KBYTE (0x0DUL) /*!< 16K Byte */
#define MPU_REGION_SIZE_32KBYTE (0x0EUL) /*!< 32K Byte */
#define MPU_REGION_SIZE_64KBYTE (0x0FUL) /*!< 64K Byte */
#define MPU_REGION_SIZE_128KBYTE (0x10UL) /*!< 128K Byte */
#define MPU_REGION_SIZE_256KBYTE (0x11UL) /*!< 256K Byte */
#define MPU_REGION_SIZE_512KBYTE (0x12UL) /*!< 512K Byte */
#define MPU_REGION_SIZE_1MBYTE (0x13UL) /*!< 1M Byte */
#define MPU_REGION_SIZE_2MBYTE (0x14UL) /*!< 2M Byte */
#define MPU_REGION_SIZE_4MBYTE (0x15UL) /*!< 4M Byte */
#define MPU_REGION_SIZE_8MBYTE (0x16UL) /*!< 8M Byte */
#define MPU_REGION_SIZE_16MBYTE (0x17UL) /*!< 16M Byte */
#define MPU_REGION_SIZE_32MBYTE (0x18UL) /*!< 32M Byte */
#define MPU_REGION_SIZE_64MBYTE (0x19UL) /*!< 64M Byte */
#define MPU_REGION_SIZE_128MBYTE (0x1AUL) /*!< 128M Byte */
#define MPU_REGION_SIZE_256MBYTE (0x1BUL) /*!< 256M Byte */
#define MPU_REGION_SIZE_512MBYTE (0x1CUL) /*!< 512M Byte */
#define MPU_REGION_SIZE_1GBYTE (0x1DUL) /*!< 1G Byte */
#define MPU_REGION_SIZE_2GBYTE (0x1EUL) /*!< 2G Byte */
#define MPU_REGION_SIZE_4GBYTE (0x1FUL) /*!< 4G Byte */
/**
* @}
*/
/**
* @defgroup MPU_Flag MPU Flag
* @{
*/
#define MPU_FLAG_SMPU1EAF (MPU_SR_SMPU1EAF) /*!< System DMA_1 error flag */
#define MPU_FLAG_SMPU2EAF (MPU_SR_SMPU2EAF) /*!< System DMA_2 error flag */
#define MPU_FLAG_FMPUEAF (MPU_SR_FMPUEAF) /*!< USBFS_DMA error flag */
#define MPU_FLAG_HMPUEAF (MPU_SR_HMPUEAF) /*!< USBHS_DMA error flag */
#define MPU_FLAG_EMPUEAF (MPU_SR_EMPUEAF) /*!< ETH_DMA error flag */
#define MPU_FLAG_ALL (0x0000001FUL)
/**
* @}
*/
/**
* @defgroup MPU_IP_Type MPU IP Type
* @note IP access protection is not available in privileged mode.
* @{
*/
#define MPU_IP_AES (MPU_IPPR_AESRDP) /*!< AES module */
#define MPU_IP_HASH (MPU_IPPR_HASHRDP) /*!< HASH module */
#define MPU_IP_TRNG (MPU_IPPR_TRNGRDP) /*!< TRNG module */
#define MPU_IP_CRC (MPU_IPPR_CRCRDP) /*!< CRC module */
#define MPU_IP_FMC (MPU_IPPR_FMCRDP) /*!< FMC module */
#define MPU_IP_WDT (MPU_IPPR_WDTRDP) /*!< WDT module */
#define MPU_IP_SWDT (MPU_IPPR_SWDTRDP) /*!< SWDT module */
#define MPU_IP_BKSRAM (MPU_IPPR_BKSRAMRDP) /*!< BKSRAM module */
#define MPU_IP_RTC (MPU_IPPR_RTCRDP) /*!< RTC module */
#define MPU_IP_DMPU (MPU_IPPR_DMPURDP) /*!< DMPU module */
#define MPU_IP_SRAMC (MPU_IPPR_SRAMCRDP) /*!< SRAMC module */
#define MPU_IP_INTC (MPU_IPPR_INTCRDP) /*!< INTC module */
#define MPU_IP_SYSC (MPU_IPPR_SYSCRDP) /*!< SYSC module */
#define MPU_IP_MSTP (MPU_IPPR_MSTPRDP) /*!< MSTP module */
#define MPU_IP_ALL (0x15555155UL)
/**
* @}
*/
/**
* @defgroup MPU_IP_Exception_Type MPU IP Exception Type
* @{
*/
#define MPU_IP_EXP_TYPE_NONE (0UL) /*!< Access to the protected IP will be ignored */
#define MPU_IP_EXP_TYPE_BUS_ERR (MPU_IPPR_BUSERRE) /*!< Access to the protected IP will trigger a bus error */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup MPU_Global_Functions
* @{
*/
/**
* @brief MPU write protect unlock.
* @param None
* @retval None
*/
__STATIC_INLINE void MPU_Unlock(void)
{
WRITE_REG32(M4_MPU->WP, 0x96A5UL);
}
/**
* @brief MPU write protect lock.
* @param None
* @retval None
*/
__STATIC_INLINE void MPU_Lock(void)
{
WRITE_REG32(M4_MPU->WP, 0x96A4UL);
}
void MPU_Unlock(void);
void MPU_Lock(void);
void MPU_DeInit(void);
en_result_t MPU_Init(const stc_mpu_init_t *pstcMpuInit);
en_result_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit);
void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32ExceptionType);
void MPU_BackgroundWriteProtectCmd(uint32_t u32Unit, en_functional_state_t enNewState);
void MPU_BackgroundReadProtectCmd(uint32_t u32Unit, en_functional_state_t enNewState);
void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState);
en_flag_status_t MPU_GetStatus(uint32_t u32Flag);
void MPU_ClearStatus(uint32_t u32Flag);
en_result_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit);
en_result_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit);
void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr);
void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size);
void MPU_RegionWriteProtectCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState);
void MPU_RegionReadProtectCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState);
void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState);
void MPU_IP_SetExceptionType(uint32_t u32ExceptionType);
void MPU_IP_WriteProtectCmd(uint32_t u32Peripheral, en_functional_state_t enNewState);
void MPU_IP_ReadProtectCmd(uint32_t u32Peripheral, en_functional_state_t enNewState);
/**
* @}
*/
#endif /* DDL_MPU_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_MPU_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_nfc.h
* @brief This file contains all the functions prototypes of the EXMC NFC
* (External Memory Controller: NAND Flash Controller) driver library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hongjh First version
2020-07-14 Hongjh 1. Merge API from EXMC_NFC_Enable/Disable to EXMC_NFC_Cmd
2. Merge API from EXMC_NFC_Enable/DisableEcc
to EXMC_NFC_EccCmd
3. Merge API from EXMC_NFC_Enable/DisableWriteProtect
to EXMC_NFC_WriteProtectCmd
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_NFC_H__
#define __HC32F4A0_NFC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_EXMC_NFC
* @{
*/
#if (DDL_NFC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup EXMC_NFC_Global_Types NAND Flash Controller Global Types
* @{
*/
/**
* @brief EXMC SMC Chip Configuration Structure definition
*/
typedef struct
{
uint32_t u32CapacitySize; /*!< Defines the capacity size.
This parameter can be a value of @ref EXMC_NFC_BANK_Memory_Capacity. */
uint32_t u32MemWidth; /*!< Defines the memory width.
This parameter can be a value of @ref EXMC_NFC_Memory_Width. */
uint32_t u32BankNum; /*!< Defines the bank number.
This parameter can be a value of @ref EXMC_NFC_Bank_Number */
uint32_t u32PageSize; /*!< Defines the page size.
This parameter can be a value of @ref EXMC_NFC_Page_Size. */
uint32_t u32WrProtect; /*!< Defines the write protect.
This parameter can be a value of @ref EXMC_NFC_Write_Protect. */
uint32_t u32EccMode; /*!< Defines the ECC mode.
This parameter can be a value of @ref EXMC_NFC_ECC_Mode. */
uint32_t u32RowAddrCycle; /*!< Defines the row address cycle.
This parameter can be a value of @ref EXMC_NFC_Row_Address_Cycle. */
uint8_t u8SpareSizeForUserData; /*!< Defines the spare column size for user data.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
}stc_exmc_nfc_base_cfg_t;
/**
* @brief EXMC NFC Timing Register 0 Configuration Structure definition
*/
typedef struct
{
uint32_t u32TS; /*!< Defines the CLE/ALE/CE setup time in memory clock cycles(tALS/tCS/tCLS).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TWP; /*!< Defines the WE# pulse width time in memory clock cycles(tWP).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TRP; /*!< Defines the RE# pulse width time in memory clock cycles(tRP).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TH; /*!< Defines the CLE/ALE/CE hold time in memory clock cycles(tALH/tCH/tCLH).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
} stc_exmc_nfc_cfg_timing_reg0_t;
/**
* @brief EXMC NFC Timing Register 1 Configuration Structure definition
*/
typedef struct
{
uint32_t u32TWH; /*!< Defines the WE# pulse width HIGH time in memory clock cycles(tWH).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TRH; /*!< Defines the RE# HIGH hold time in memory clock cycles(tREH).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TRR; /*!< Defines the Ready to RE# LOW time in memory clock cycles(tRR).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TWB; /*!< Defines the WE# HIGH to busy time in memory clock cycles(tWB).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
} stc_exmc_nfc_cfg_timing_reg1_t;
/**
* @brief EXMC NFC Timing Register 2 Configuration Structure definition
*/
typedef struct
{
uint32_t u32TCCS; /*!< Defines the command(change read/write column) delay time in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TWTR; /*!< Defines the WE# HIGH to RE# LOW time in memory clock cycles(tWHR).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TRTW; /*!< Defines the RE# HIGH to WE# LOW time in memory clock cycles(tRHW).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32TADL; /*!< Defines the Address to Data Loading time in memory clock cycles(tADL).
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
} stc_exmc_nfc_cfg_timing_reg2_t;
/**
* @brief EXMC NFC Initialization Structure definition
*/
typedef struct
{
uint32_t u32OpenPage; /*!< NFC memory open-page selection.
This structure details refer @ref EXMC_NFC_Open_Page. */
stc_exmc_nfc_base_cfg_t stcBaseCfg; /*!< NFC memory base configure.
This structure details refer @ref stc_exmc_nfc_base_cfg_t. */
stc_exmc_nfc_cfg_timing_reg0_t stcTimingReg0; /*!< NFC memory timing configure 0.
This structure details refer @ref stc_exmc_nfc_cfg_timing_reg0_t. */
stc_exmc_nfc_cfg_timing_reg1_t stcTimingReg1; /*!< NFC memory timing configure 1.
This structure details refer @ref stc_exmc_nfc_cfg_timing_reg1_t. */
stc_exmc_nfc_cfg_timing_reg2_t stcTimingReg2; /*!< NFC memory timing configure 2.
This structure details refer @ref stc_exmc_nfc_cfg_timing_reg2_t. */
} stc_exmc_nfc_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup EXMC_NFC_Global_Macros NAND Flash Controller Global Macros
* @{
*/
/**
* @defgroup EXMC_NFC_Bank EXMC NFC Bank
* @{
*/
#define EXMC_NFC_BANK_0 (0UL) /*!< Bank 0 */
#define EXMC_NFC_BANK_1 (1UL) /*!< Bank 1 */
#define EXMC_NFC_BANK_2 (2UL) /*!< Bank 2 */
#define EXMC_NFC_BANK_3 (3UL) /*!< Bank 3 */
#define EXMC_NFC_BANK_4 (4UL) /*!< Bank 4 */
#define EXMC_NFC_BANK_5 (5UL) /*!< Bank 5 */
#define EXMC_NFC_BANK_6 (6UL) /*!< Bank 6 */
#define EXMC_NFC_BANK_7 (7UL) /*!< Bank 7 */
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Memory_Command EXMC NFC Memory Command
* @{
*/
#define EXMC_NFC_CMD_READ_1ST (0x00UL)
#define EXMC_NFC_CMD_READ_2ND (0xE0UL)
#define EXMC_NFC_CMD_COPYBACK_READ_1ST (0x00UL)
#define EXMC_NFC_CMD_COPYBACK_READ_2ND (0x35UL)
#define EXMC_NFC_CMD_CHANGE_RD_COL_1ST (0x05UL)
#define EXMC_NFC_CMD_CHANGE_RD_COL_2ND (0xE0UL)
#define EXMC_NFC_CMD_CHANGE_RD_COL_ENHANCED_1ST (0x06UL)
#define EXMC_NFC_CMD_CHANGE_RD_COL_ENHANCED_2ND (0xE0UL)
#define EXMC_NFC_CMD_READ_CACHE_RANDOM_1ST (0x00UL)
#define EXMC_NFC_CMD_READ_CACHE_RANDOM_2ND (0x31UL)
#define EXMC_NFC_CMD_CALCULATE_ECC (0x23UL)
#define EXMC_NFC_CMD_READ_CACHE_SEQ (0x31UL)
#define EXMC_NFC_CMD_READ_CACHE_END (0x3FUL)
#define EXMC_NFC_CMD_BLK_ERASE_1ST (0x60UL)
#define EXMC_NFC_CMD_BLK_ERASE_2ND (0xD0UL)
#define EXMC_NFC_CMD_BLK_ERASE_INTERLEAVED_1ST (0x60UL)
#define EXMC_NFC_CMD_BLK_ERASE_INTERLEAVED_2ND (0xD1UL)
#define EXMC_NFC_CMD_READ_STATUS (0x70UL)
#define EXMC_NFC_CMD_READ_STATUS_ENHANCED (0x78UL)
#define EXMC_NFC_CMD_PAGE_PROGRAM_1ST (0x80UL)
#define EXMC_NFC_CMD_PAGE_PROGRAM_2ND (0x10UL)
#define EXMC_NFC_CMD_PAGE_PROGRAM_INTERLEAVED_1ST (0x80UL)
#define EXMC_NFC_CMD_PAGE_PROGRAM_INTERLEAVED_2ND (0x11UL)
#define EXMC_NFC_CMD_PAGE_CACHE_PROGRAM_1ST (0x80UL)
#define EXMC_NFC_CMD_PAGE_CACHE_PROGRAM_2ND (0x15UL)
#define EXMC_NFC_CMD_COPYBACK_PROGRAM_1ST (0x85UL)
#define EXMC_NFC_CMD_COPYBACK_PROGRAM_2ND (0x10UL)
#define EXMC_NFC_CMD_COPYBACK_PROGRAM_INTERLEAVED_1ST (0x85UL)
#define EXMC_NFC_CMD_COPYBACK_PROGRAM_INTERLEAVED_2ND (0x11UL)
#define EXMC_NFC_CMD_CHANGE_WR_COL (0x85UL)
#define EXMC_NFC_CMD_CHANGE_ROW_ADDRESS (0x85UL)
#define EXMC_NFC_CMD_READ_ID (0x90UL)
#define EXMC_NFC_CMD_READ_PARAMETER_PAGE (0xECUL)
#define EXMC_NFC_CMD_READ_UNIQUE_ID (0xEDUL)
#define EXMC_NFC_CMD_GET_FEATURES (0xEEUL)
#define EXMC_NFC_CMD_SET_FEATURES (0xEFUL)
#define EXMC_NFC_CMD_RESET_LUN (0xFAUL)
#define EXMC_NFC_CMD_ASYNCHRONOUS_RESSET (0xFCUL)
#define EXMC_NFC_CMD_DESELECT_CHIP (0xFEUL)
#define EXMC_NFC_CMD_RESET (0xFFUL)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Page_Size EXMC NFC Page Size
* @{
*/
#define EXMC_NFC_PAGE_SIZE_2KBYTES (NFC_BACR_PAGE_0)
#define EXMC_NFC_PAGE_SIZE_4KBYTES (NFC_BACR_PAGE_1)
#define EXMC_NFC_PAGE_SIZE_8KBYTES (NFC_BACR_PAGE)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_BANK_Memory_Capacity EXMC NFC BANK Memory Capacity
* @{
*/
#define EXMC_NFC_BANK_CAPACITY_512MBIT (NFC_BACR_SIZE_1 | NFC_BACR_SIZE_0)
#define EXMC_NFC_BANK_CAPACITY_1GBIT (NFC_BACR_SIZE_2)
#define EXMC_NFC_BANK_CAPACITY_2GBIT (NFC_BACR_SIZE_2 | NFC_BACR_SIZE_0)
#define EXMC_NFC_BANK_CAPACITY_4GBIT (NFC_BACR_SIZE_2 | NFC_BACR_SIZE_1)
#define EXMC_NFC_BANK_CAPACITY_8GBIT (NFC_BACR_SIZE)
#define EXMC_NFC_BANK_CAPACITY_16GBIT (0UL)
#define EXMC_NFC_BANK_CAPACITY_32GBIT (NFC_BACR_SIZE_0)
#define EXMC_NFC_BANK_CAPACITY_64GBIT (NFC_BACR_SIZE_1)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Memory_Width EXMC NFC Memory Width
* @{
*/
#define EXMC_NFC_MEMORY_WIDTH_8BIT (0UL)
#define EXMC_NFC_MEMORY_WIDTH_16BIT (NFC_BACR_B16BIT)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Bank_Number EXMC NFC Bank Number
* @{
*/
#define EXMC_NFC_1_BANK (0UL)
#define EXMC_NFC_2_BANKS (NFC_BACR_BANK_0)
#define EXMC_NFC_4_BANKS (NFC_BACR_BANK_1)
#define EXMC_NFC_8_BANKS (NFC_BACR_BANK)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Open_Page EXMC NFC Open Page
* @{
*/
#define EXMC_NFC_OPEN_PAGE_DISABLE (0UL)
#define EXMC_NFC_OPEN_PAGE_ENABLE (PERIC_NFC_SYCTLREG_OPO)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Write_Protect EXMC NFC Write Protect
* @{
*/
#define EXMC_NFC_WR_PROTECT_ENABLE (0UL)
#define EXMC_NFC_WR_PROTECT_DISABLE (NFC_BACR_WP)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_ECC_Mode EXMC NFC ECC Mode
* @{
*/
#define EXMC_NFC_ECC_1BIT (0UL)
#define EXMC_NFC_ECC_4BITS (NFC_BACR_ECCM_0)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Row_Address_Cycle EXMC NFC Row Address Cycle
* @{
*/
#define EXMC_NFC_2_ROW_ADDRESS_CYCLES (0UL)
#define EXMC_NFC_3_ROW_ADDRESS_CYCLES (NFC_BACR_RAC)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Interrupt EXMC NFC Interrupt
* @{
*/
#define EXMC_NFC_INT_ECC_UNCORRECTABLE_ERROR (NFC_IENR_ECCEUEN)
#define EXMC_NFC_INT_ECC_CORRECTABLE_ERROR (NFC_IENR_ECCECEN)
#define EXMC_NFC_INT_ECC_CALC_COMPLETION (NFC_IENR_ECCCEN)
#define EXMC_NFC_INT_ECC_ERROR (NFC_IENR_ECCEEN)
#define EXMC_NFC_INT_RB_BANK0 (NFC_IENR_RBEN_0)
#define EXMC_NFC_INT_RB_BANK1 (NFC_IENR_RBEN_1)
#define EXMC_NFC_INT_RB_BANK2 (NFC_IENR_RBEN_2)
#define EXMC_NFC_INT_RB_BANK3 (NFC_IENR_RBEN_3)
#define EXMC_NFC_INT_RB_BANK4 (NFC_IENR_RBEN_4)
#define EXMC_NFC_INT_RB_BANK5 (NFC_IENR_RBEN_5)
#define EXMC_NFC_INT_RB_BANK6 (NFC_IENR_RBEN_6)
#define EXMC_NFC_INT_RB_BANK7 (NFC_IENR_RBEN_7)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Flag EXMC NFC Flag
* @{
*/
#define EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERROR (NFC_ISTR_ECCEUST)
#define EXMC_NFC_FLAG_ECC_CORRECTABLE_ERROR (NFC_ISTR_ECCECST)
#define EXMC_NFC_FLAG_ECC_CALC_COMPLETION (NFC_ISTR_ECCCST)
#define EXMC_NFC_FLAG_ECC_ERROR (NFC_ISTR_ECCEST)
#define EXMC_NFC_FLAG_RB_BANK0 (NFC_ISTR_RBST_0)
#define EXMC_NFC_FLAG_RB_BANK1 (NFC_ISTR_RBST_1)
#define EXMC_NFC_FLAG_RB_BANK2 (NFC_ISTR_RBST_2)
#define EXMC_NFC_FLAG_RB_BANK3 (NFC_ISTR_RBST_3)
#define EXMC_NFC_FLAG_RB_BANK4 (NFC_ISTR_RBST_4)
#define EXMC_NFC_FLAG_RB_BANK5 (NFC_ISTR_RBST_5)
#define EXMC_NFC_FLAG_RB_BANK6 (NFC_ISTR_RBST_6)
#define EXMC_NFC_FLAG_RB_BANK7 (NFC_ISTR_RBST_7)
#define EXMC_NFC_FLAG_ECC_CALCULATING (NFC_ISTR_RESV)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_ECC_Calculate_Bytes EXMC NFC ECC Calculate Bytes
* @{
*/
#define EXMC_NFC_ECC_CALCULATE_BLOCK_BYTES (512UL)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_ECC_Value_Bytes EXMC NFC ECC Value Bytes
* @{
*/
#define EXMC_NFC_1BIT_ECC_VALUE_BYTES (0x03UL)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_1Bit_ECC_Result EXMC NFC 1Bit ECC Result
* @{
*/
#define EXMC_NFC_1BIT_ECC_SINGLE_BIT_ERR (NFC_ECCR_SE)
#define EXMC_NFC_1BIT_ECC_MULTIPLE_BITS_ERR (NFC_ECCR_ME)
#define EXMC_NFC_1BIT_ECC_ERR_LOCATION (NFC_ECCR_ERRLOC)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_1Bit_ECC_Error_Location_Position EXMC NFC 1Bit ECC Error Location Position
* @{
*/
#define EXMC_NFC_1BIT_ECC_ERR_BIT_POS (NFC_ECCR_ERRLOC_POS)
#define EXMC_NFC_1BIT_ECC_ERR_BYTE_POS (NFC_ECCR_ERRLOC_POS + 3UL)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_ECC_Section EXMC NFC ECC Section
* @{
*/
#define EXMC_NFC_ECC_SECTION0 (0UL)
#define EXMC_NFC_ECC_SECTION1 (1UL)
#define EXMC_NFC_ECC_SECTION2 (2UL)
#define EXMC_NFC_ECC_SECTION3 (3UL)
#define EXMC_NFC_ECC_SECTION4 (4UL)
#define EXMC_NFC_ECC_SECTION5 (5UL)
#define EXMC_NFC_ECC_SECTION6 (6UL)
#define EXMC_NFC_ECC_SECTION7 (7UL)
#define EXMC_NFC_ECC_SECTION8 (8UL)
#define EXMC_NFC_ECC_SECTION9 (9UL)
#define EXMC_NFC_ECC_SECTION10 (10UL)
#define EXMC_NFC_ECC_SECTION11 (11UL)
#define EXMC_NFC_ECC_SECTION12 (12UL)
#define EXMC_NFC_ECC_SECTION13 (13UL)
#define EXMC_NFC_ECC_SECTION14 (14UL)
#define EXMC_NFC_ECC_SECTION15 (15UL)
/**
* @}
*/
/**
* @defgroup EXMC_NFC_Operation_Timeout EXMC NFC Operation Timeout
* @{
*/
#define EXMC_NFC_MAX_TIMEOUT (0xFFFFFFFFUL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup EXMC_NFC_Global_Functions
* @{
*/
/**
* @brief Set EXMC NFC command register value.
* @param [in] u32Val The combination value of command and arguments.
* @retval None
*/
__STATIC_INLINE void EXMC_NFC_WriteCmdReg(uint32_t u32Val)
{
WRITE_REG32(M4_NFC->CMDR, u32Val);
}
/**
* @brief Set EXMC NFC Index register value.
* @param [in] u32Val The value of NFC_IDXR0.
* This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void EXMC_NFC_WriteIDXR0(uint32_t u32Val)
{
WRITE_REG32(M4_NFC->IDXR0, u32Val);
}
/**
* @brief Set EXMC NFC Index register value.
* @param [in] u32Val The value of NFC_IDXR1.
* This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF
* @retval None
*/
__STATIC_INLINE void EXMC_NFC_WriteIDXR1(uint32_t u32Val)
{
WRITE_REG32(M4_NFC->IDXR1, u32Val);
}
/**
* @brief De-select NFC bank.
* @param None
* @retval None
*/
__STATIC_INLINE void EXMC_NFC_DeselectChip(void)
{
WRITE_REG32(M4_NFC->CMDR, EXMC_NFC_CMD_DESELECT_CHIP);
}
/**
* @brief Get the 4BIT ECC error section.
* @param None
* @retval The register value
*/
__STATIC_INLINE uint32_t EXMC_NFC_GetEcc4BitsErrSection(void)
{
return READ_REG32(M4_NFC->ECC_STAT);
}
/* Initialization and configuration EXMC NFC functions */
en_result_t EXMC_NFC_Init(const stc_exmc_nfc_init_t *pstcInit);
void EXMC_NFC_DeInit(void);
en_result_t EXMC_NFC_StructInit(stc_exmc_nfc_init_t *pstcInit);
void EXMC_NFC_Cmd(en_functional_state_t enNewState);
void EXMC_NFC_EccCmd(en_functional_state_t enNewState);
void EXMC_NFC_WriteProtectCmd(en_functional_state_t enNewState);
void EXMC_NFC_IntCmd(uint16_t u16IntSource, en_functional_state_t enNewState);
en_flag_status_t EXMC_NFC_GetStatus(uint32_t u32Flag);
void EXMC_NFC_ClearStatus(uint32_t u32Flag);
en_flag_status_t EXMC_NFC_GetIntResultStatus(uint32_t u32Flag);
uint32_t EXMC_NFC_GetEcc1BitResult(uint32_t u32Section);
en_result_t EXMC_NFC_GetSyndrome(uint32_t u32Section,
uint16_t au16Synd[],
uint8_t u8Length);
void EXMC_NFC_SetSpareAreaSize(uint8_t u8SpareSizeForUserData);
void EXMC_NFC_SetEccMode(uint32_t u32EccMode);
/* EXMC NFC command functions */
uint32_t EXMC_NFC_ReadStatus(uint32_t u32Bank);
uint32_t EXMC_NFC_ReadStatusEnhanced(uint32_t u32Bank,
uint32_t u32RowAddress);
en_result_t EXMC_NFC_Reset(uint32_t u32Bank, uint32_t u32Timeout);
en_result_t EXMC_NFC_AsyncReset(uint32_t u32Bank, uint32_t u32Timeout);
en_result_t EXMC_NFC_ResetLun(uint32_t u32Bank,
uint32_t u32RowAddress,
uint32_t u32Timeout);
en_result_t EXMC_NFC_ReadId(uint32_t u32Bank,
uint32_t u32IdAddr,
uint8_t au8DevId[],
uint32_t u32NumBytes,
uint32_t u32Timeout);
en_result_t EXMC_NFC_ReadUniqueId(uint32_t u32Bank,
uint32_t u32IdAddr,
uint32_t au32UniqueId[],
uint8_t u8NumWords,
uint32_t u32Timeout);
en_result_t EXMC_NFC_ReadParameterPage(uint32_t u32Bank,
uint32_t au32Data[],
uint16_t u16NumWords,
uint32_t u32Timeout);
en_result_t EXMC_NFC_SetFeature(uint32_t u32Bank,
uint8_t u8FeatrueAddr,
const uint32_t au32Data[],
uint8_t u8NumWords,
uint32_t u32Timeout);
en_result_t EXMC_NFC_GetFeature(uint32_t u32Bank,
uint8_t u8FeatrueAddr,
uint32_t au32Data[],
uint8_t u8NumWords,
uint32_t u32Timeout);
en_result_t EXMC_NFC_EraseBlock(uint32_t u32Bank,
uint32_t u32RowAddress,
uint32_t u32Timeout);
en_result_t EXMC_NFC_ReadPageMeta(uint32_t u32Bank,
uint32_t u32Page,
uint8_t *pu8Data,
uint32_t u32NumBytes,
uint32_t u32Timeout);
en_result_t EXMC_NFC_WritePageMeta(uint32_t u32Bank,
uint32_t u32Page,
const uint8_t *pu8Data,
uint32_t u32NumBytes,
uint32_t u32Timeout);
en_result_t EXMC_NFC_ReadPageHwEcc(uint32_t u32Bank,
uint32_t u32Page,
uint8_t *pu8Data,
uint32_t u32NumBytes,
uint32_t u32Timeout);
en_result_t EXMC_NFC_WritePageHwEcc(uint32_t u32Bank,
uint32_t u32Page,
const uint8_t *pu8Data,
uint32_t u32NumBytes,
uint32_t u32Timeout);
/**
* @}
*/
#endif /* DDL_NFC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_NFC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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@ -0,0 +1,212 @@
/**
*******************************************************************************
* @file hc32f4a0_ots.h
* @brief This file contains all the functions prototypes of the OTS driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Wuze First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_OTS_H__
#define __HC32F4A0_OTS_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_OTS
* @{
*/
#if (DDL_OTS_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup OTS_Global_Types OTS Global Types
* @{
*/
/**
* @brief Conditions for default parameters(slope K and offset M).
* @note 'u8T1' CANNOT equal 'u8T2'.
*/
typedef struct
{
uint16_t u16ClkFreq; /*!< Frequency(MHz) of clock sources that OTS is going to use. */
uint8_t u8T1; /*!< Temperature value T1 for the default parameter.
This parameter can be a value of @ref OTS_Temp_Condition */
uint8_t u8T2; /*!< Temperature value T2 for the default parameter.
This parameter can be a value of @ref OTS_Temp_Condition */
} stc_para_cond_t;
/**
* @brief OTS initialization structure.
*/
typedef struct
{
uint16_t u16ClkSrc; /*!< Specifies clock source for OTS.
This parameter can be a value of @ref OTS_Clock_Source */
float32_t f32SlopeK; /*!< K: Temperature slope (calculated by calibration experiment). \
When you want to use the default parameters(slope K and offset M), specify it as ZERO. */
float32_t f32OffsetM; /*!< M: Temperature offset (calculated by calibration experiment). \
When you want to use the default parameters(slope K and offset M), specify it as ZERO. */
uint16_t u16AutoOffEn; /*!< OTS automatic-off function control.
This parameter can be a value of @ref OTS_Automatic_Off_Ctrl */
stc_para_cond_t stcParaCond; /*!< Specify the conditions when you want to use the default parameters(slope K and offset M). */
} stc_ots_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup OTS_Global_Macros OTS Global Macros
* @{
*/
/**
* @defgroup OTS_Clock_Source OTS Clock Source
* @{
*/
#define OTS_CLK_XTAL (0x0U) /*!< Select XTAL as OTS clock. */
#define OTS_CLK_HRC (OTS_CTL_OTSCK) /*!< Select HRC as OTS clock */
/**
* @}
*/
/**
* @defgroup OTS_Automatic_Off_Ctrl OTS Automatic Off Control
* @{
*/
#define OTS_AUTO_OFF_DISABLE (0x0U)
#define OTS_AUTO_OFF_ENABLE (OTS_CTL_TSSTP)
/**
* @}
*/
/**
* @defgroup OTS_Temp_Condition OTS Temperature Condition For Default Parameters(slope K and offset M)
* @{
*/
#define OTS_COND_TN40 (0U) /*!< -40 degrees Celsius. */
#define OTS_COND_T25 (1U) /*!< 25 degrees Celsius. */
#define OTS_COND_T125 (2U) /*!< 125 degrees Celsius. */
/**
* @}
*/
/**
* @defgroup OTS_Common_Trigger_Sel OTS Common Trigger Source Select
* @{
*/
#define OTS_COM_TRIG1 (AOS_OTS_TRG_COMTRG_EN_0)
#define OTS_COM_TRIG2 (AOS_OTS_TRG_COMTRG_EN_1)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup OTS_Global_Functions
* @{
*/
/**
* @brief Start OTS.
* @param None
* @retval None
*/
__STATIC_INLINE void OTS_Start(void)
{
bM4_OTS->CTL_b.OTSST = (uint32_t)1U;
}
/**
* @brief Stop OTS.
* @param None
* @retval None
*/
__STATIC_INLINE void OTS_Stop(void)
{
bM4_OTS->CTL_b.OTSST = (uint32_t)0U;
}
en_result_t OTS_Init(const stc_ots_init_t *pstcInit);
en_result_t OTS_StructInit(stc_ots_init_t *pstcInit);
void OTS_DeInit(void);
en_result_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout);
void OTS_IntCmd(en_functional_state_t enNewState);
void OTS_SetTriggerSrc(en_event_src_t enEvent);
void OTS_ComTriggerCmd(uint32_t u32ComTrig, en_functional_state_t enNewState);
en_result_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, \
uint16_t *pu16Ecr, float32_t *pf32A, \
uint32_t u32Timeout);
float OTS_CalculateTemp(void);
/**
* @}
*/
#endif /* DDL_OTS_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_OTS_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_pwc.h
* @brief This file contains all the functions prototypes of the PWC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Zhangxl First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_PWC_H__
#define __HC32F4A0_PWC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_PWC
* @{
*/
#if (DDL_PWC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup PWC_Global_Types PWC Global Types
* @{
*/
typedef struct
{
uint32_t u32RamCtrl; /*!< Internal RAM power setting. */
uint32_t u32PRamCtrl; /*!< Peripheral RAM power setting. */
uint16_t u16RamMode; /*!< RAM setting for Operating mode, @ref PWC_RAM_Config for details */
} stc_pwc_ram_config_t;
typedef struct
{
uint8_t u8PvdEn; /*!< PVD function setting, @ref PWC_PVD_Config for details */
uint8_t u8Pvd2ExtInEn; /*!< PVD2 ext. pin input function setting, @ref PWC_PVD2_ExtIn_Config */
uint8_t u8PvdCmpOutEn; /*!< PVD compare output function setting, @ref PWC_PVD_CMP_Config for details */
uint8_t u8PvdIntRstSel; /*!< PVD interrupt or reset selection, @ref PWC_PVD_IntRst_Sel for details */
uint8_t u8PvdIntRstEn; /*!< PVD interrupt or reset function setting, @ref PWC_PVD_IR_Config for details */
uint8_t u8FilterEn; /*!< PVD digital filter function setting, @ref PWC_PVD_DF_Config for details */
uint8_t u8FilterClk; /*!< PVD digital filter clock setting, @ref PWC_PVD_DFS_Clk_Sel for details */
uint8_t u8PvdVoltage; /*!< PVD detect voltage setting, @ref PWC_PVD_detection_Vol for details */
uint8_t u8PvdNmiEn; /*!< PVD NMI function setting, @ref PWC_PVD_Int_Mode_Config for details */
uint8_t u8PvdTrigger; /*!< PVD trigger setting, @ref PWC_PVD_Trigger_Sel for details */
} stc_pwc_pvd_config_t;
typedef struct
{
uint8_t u8PDMode; /*!< Power down mode, @ref PWC_PDMode_Sel for details. */
uint8_t u8IOState; /*!< IO state in power down mode, @ref PWC_PDMode_IO_Sel for details. */
uint8_t u8WkUpSpeed; /*!< Wakeup speed selection, @ref PWC_PDMode_WKUP_TIME_Sel for details. */
}stc_pwc_pd_mode_config_t;
typedef struct
{
uint8_t u8StopDrv; /*!< Stop mode drive capacity, @ref PWC_STOP_DRV_Sel for details. */
uint16_t u16ExBusHold; /*!< Exbus status in stop mode, @ref PWC_STOP_EXBUS_Sel for details. */
uint16_t u16ClkKeep; /*!< System clock setting after wake-up from stop mode,
@ref PWC_STOP_CLK_Sel for details. */
uint16_t u16FlashWait; /*!< Waiting flash stable after wake-up from stop mode,
@ref STOP_FLASH_WAIT_Sel for details. */
} stc_pwc_stop_mode_config;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup PWC_Global_Macros PWC Global Macros
* @{
*/
/**
* @defgroup PWC_PDMode_Sel Power down mode selection
* @{
*/
#define PWC_PD_MODE1 (0x00U) /*!< Power down mode 0 */
#define PWC_PD_MODE2 (0x01U) /*!< Power down mode 1 */
#define PWC_PD_MODE3 (0x02U) /*!< Power down mode 2 */
#define PWC_PD_MODE4 (0x03U) /*!< Power down mode 3 */
/**
* @}
*/
/**
* @defgroup PWC_PDMode_IO_Sel IO state config in Power down mode
* @{
*/
#define PWC_PD_IO_STATE1 (0x00U) /*!< IO state retain in PD mode and configurable after wakeup */
#define PWC_PD_IO_STATE2 (PWC_PWRC0_IORTN_0) /*!< IO state retain in PD mode and configurable after wakeup & set IORTN[1:0]=00b */
#define PWC_PD_IO_STATE3 (PWC_PWRC0_IORTN_1) /*!< IO state switch to HiZ */
/**
* @}
*/
/**
* @defgroup PWC_STOP_DRV_Sel Drive capacity while enter stop mode
* @{
*/
#define PWC_STOP_DRV_HIGH (0x00U) /*!< Enter stop mode from high speed mode */
#define PWC_STOP_DRV_LOW (PWC_PWRC1_STPDAS) /*!< Enter stop mode from ultra low speed mode */
/**
* @}
*/
/**
* @defgroup PWC_STOP_EXBUS_Sel ExBus status while enter stop mode
* @{
*/
#define PWC_STOP_EXBUS_HIZ (0x00U) /*!< Ex-Bus Hiz in stop mode */
#define PWC_STOP_EXBUS_HOLD (PWC_STPMCR_EXBUSOE) /*!< Ex-Bus keep in stop mode */
/**
* @}
*/
/**
* @defgroup PWC_STOP_CLK_Sel System clock setting after wake-up from stop mode
* @{
*/
#define PWC_STOP_CLK_KEEP (0x00U) /*!< Keep System clock setting after wake-up from stop mode */
#define PWC_STOP_CLK_MRC (PWC_STPMCR_CKSMRC) /*!< System clock switch to MRC after wake-up from stop mode */
/**
* @}
*/
/**
* @defgroup STOP_FLASH_WAIT_Sel Whether wait flash stable or not after wake-up from stop mode
* @{
*/
#define PWC_STOP_FLASH_WAIT (0x00U) /*!< Wait flash stable after wake-up from stop mode */
#define PWC_STOP_FLASH_NOWAIT (PWC_STPMCR_FLNWT) /*!< Don't wait flash stable after wake-up from stop mode */
/**
* @}
*/
/**
* @defgroup PWC_PWR_DRV_Sel Drive capacity selection
* @{
*/
#define PWC_NOR_DRV_HIGH (PWC_PWRC2_DVS) /*!< Drive capacity in high speed operation */
#define PWC_NOR_DRV_LOW (PWC_PWRC2_DVS_1) /*!< Drive capacity in ultra low speed operation */
/**
* @}
*/
/**
* @defgroup PWC_PDMode_WKUP_TIME_Sel Wakeup speed config in Power down mode
* @{
*/
#define PWC_PD_WKUP_SLOW (0x00U) /*!< VCAP1/VCAP2 = 0.1uF x2 or 0.22uF x1 */
#define PWC_PD_WKUP_FAST (0x01U) /*!< VCAP1/VCAP2 = 0.047uF x2 or 0.1uF x1 */
/**
* @}
*/
/**
* @defgroup PWC_RAM_Config Operating mode for RAM Config
* @{
*/
#define PWC_RAM_HIGH (0x8043U) /*!< MCU operating under high frequency (lower than 240MHz) */
#define PWC_RAM_LOW (0x9062U) /*!< MCU operating under ultra low frequency (lower than 8MHz) */
/**
* @}
*/
/**
* @defgroup PWC_PWMON_Config PWC Power Monitor Config
* @{
*/
#define PWC_PWRMON_ON (PWC_PWRC_PWMONE)
#define PWC_PWRMON_OFF (0x00U)
/**
* @}
*/
/**
* @defgroup PWC_PWMON_Sel PWC Power Monitor Selection
* @{
*/
#define PWC_PWRMON_VINREF (0x00U) /*!< Internal reference voltage */
#define PWC_PWRMON_VOTS (PWC_PWRC_PWMONSEL) /*!< temperature sensor voltage */
/**
* @}
*/
/**
* @defgroup PWC_DRV_Sel PWC Driver ability selection
* @{
*/
#define PWC_DRV_LOW (0x00U) /*!< system clock = 32kHz */
#define PWC_DRV_HIGH (0x07U) /*!< system clock < 48Mhz */
/**
* @}
*/
/**
* @defgroup PWC_PVD_Channel PWC PVD channel
* @{
*/
#define PWC_PVD_CH1 (0x00U)
#define PWC_PVD_CH2 (0x01U)
/**
* @}
*/
/**
* @defgroup PWC_PVD_Config PWC PVD Config
* @{
*/
#define PWC_PVD_ON (0x01U)
#define PWC_PVD_OFF (0x00U)
/**
* @}
*/
/**
* @defgroup PWC_PVD2_ExtIn_Config PWC PVD2 external input Config
* @{
*/
#define PWC_PVD2_EXINP_ON (PWC_PVDCR0_EXVCCINEN)
#define PWC_PVD2_EXINP_OFF (0x00U)
/**
* @}
*/
/**
* @defgroup PWC_PVD_IR_Config PWC PVD Interrupt/Reset Config
* @{
*/
#define PWC_PVD_IR_ON (PWC_PVDCR1_PVD1IRE)
#define PWC_PVD_IR_OFF (0x00U)
/**
* @}
*/
/**
* @defgroup PWC_PVD_IntRst_Sel set PVD to interrupt or reset
* @{
*/
#define PWC_PVD_INT (0x00U)
#define PWC_PVD_RST (PWC_PVDCR1_PVD1IRS)
/**
* @}
*/
/**
* @defgroup PWC_PVD_CMP_Config PWC PVD Compare Config
* @{
*/
#define PWC_PVD_CMP_ON (PWC_PVDCR1_PVD1CMPOE)
#define PWC_PVD_CMP_OFF (0x00U)
/**
* @}
*/
/**
* @defgroup PWC_PVD_DF_Config PVD digital filter ON or OFF
* @{
*/
#define PWC_PVD_DF_ON (0x00U)
#define PWC_PVD_DF_OFF (PWC_PVDFCR_PVD1NFDIS)
/**
* @}
*/
/**
* @defgroup PWC_PVD_DFS_Clk_Sel PVD digital filter sample ability
* @note modified this value must when PWC_PVD_DF_OFF
* @{
*/
#define PWC_PVD_DFS_DIV4 (0x00U) /*!< 0.25 LRC cycle */
#define PWC_PVD_DFS_DIV2 (PWC_PVDFCR_PVD1NFCKS_0) /*!< 0.5 LRC cycle */
#define PWC_PVD_DFS_DIV1 (PWC_PVDFCR_PVD1NFCKS_1) /*!< 1 LRC cycle */
#define PWC_PVD_DFS_MUL2 (PWC_PVDFCR_PVD1NFCKS) /*!< 2 LRC cycles */
/**
* @}
*/
/**
* @defgroup PWC_PVD_detection_Vol PWC PVD Detection voltage
* @{
*/
#define PWC_PVD1_2V0_PVD2_2V1 (0x00U) /*!< Specifies the voltage of PVD1 is 2.0V or PVD2 is 2.0V. */
#define PWC_PVD1_2V1_PVD2_2V3 (0x01U) /*!< Specifies the voltage of PVD1 is 2.1V or PVD2 is 2.1V. */
#define PWC_PVD1_2V3_PVD2_2V5 (0x02U) /*!< Specifies the voltage of PVD1 is 2.3V or PVD2 is 2.3V. */
#define PWC_PVD1_2V5_PVD2_2V6 (0x03U) /*!< Specifies the voltage of PVD1 is 2.5V or PVD2 is 2.5V. */
#define PWC_PVD1_2V6_PVD2_2V7 (0x04U) /*!< Specifies the voltage of PVD1 is 2.6V or PVD2 is 2.6V. */
#define PWC_PVD1_2V7_PVD2_2V8 (0x05U) /*!< Specifies the voltage of PVD1 is 2.7V or PVD2 is 2.7V. */
#define PWC_PVD1_2V8_PVD2_2V9 (0x06U) /*!< Specifies the voltage of PVD1 is 2.8V or PVD2 is 2.8V. */
#define PWC_PVD1_2V9_PVD2_1V1 (0x07U) /*!< Specifies the voltage of PVD1 is 2.9V or PVD2 is 1.1V (only ext. input). */
/**
* @}
*/
/**
* @defgroup PWC_PVD_Int_Mode_Config PVD interrupt set to maskable or non_maskable
* @{
*/
#define PWC_PVD_INT_MASK (PWC_PVDICR_PVD1NMIS)
#define PWC_PVD_INT_NONMASK (0x00U)
/**
* @}
*/
/**
* @defgroup PWC_PVD_Trigger_Sel PVD trigger setting
* @{
*/
#define PWC_PVD_TRIGGER_FALLING (0x00U)
#define PWC_PVD_TRIGGER_RISING (PWC_PVDICR_PVD1EDGS_0)
#define PWC_PVD_TRIGGER_BOTH (PWC_PVDICR_PVD1EDGS_1)
/**
* @}
*/
/**
* @defgroup PWC_WKUP_Event_Sel Power down mode wakeup event selection
* @{
*/
#define PWC_PD_WKUP_TRIG_PVD1 (PWC_PDWKES_VD1EGS)
#define PWC_PD_WKUP_TRIG_PVD2 (PWC_PDWKES_VD2EGS)
#define PWC_PD_WKUP_TRIG_WKP0 (PWC_PDWKES_WK0EGS)
#define PWC_PD_WKUP_TRIG_WKP1 (PWC_PDWKES_WK1EGS)
#define PWC_PD_WKUP_TRIG_WKP2 (PWC_PDWKES_WK2EGS)
#define PWC_PD_WKUP_TRIG_WKP3 (PWC_PDWKES_WK3EGS)
#define PWC_PD_WKUP_TRIG_MASK (PWC_PDWKES_VD1EGS | PWC_PDWKES_VD2EGS | \
PWC_PDWKES_WK0EGS | PWC_PDWKES_WK1EGS | \
PWC_PDWKES_WK2EGS | PWC_PDWKES_WK3EGS)
/**
* @}
*/
/**
* @defgroup PWC_WKUP_Trigger_Edge_Sel Power down mode wakeup trigger edge selection
* @{
*/
#define PWC_PD_WKUP_FALLING (0x00U)
#define PWC_PD_WKUP_RISING (0x01U)
/**
* @}
*/
/**
* @defgroup PWC_DBGC_config PWC Debug Config
* @{
*/
#define PWC_AD_INTERN_REF (0x00U)
#define PWC_AD_VBAT_DIV2 (0x01U)
/**
* @}
*/
/**
* @defgroup PWC_VBAT_Voltage_Status PWC VBAT Voltage Status
* @{
*/
#define PWC_VOL_VBAT_MORE_THAN_VBATREF (0x00U) /*!< Vbat > VbatREF */
#define PWC_VOL_VBAT_LESS_THAN_VBATREF (0x01U) /*!< Vbat < VbatREF */
/**
* @}
*/
/**
* @defgroup PWC_VBAT_Reference_Voltage PWC VBAT Reference Voltage
* @{
*/
#define PWC_VBAT_REF_VOL_1P8V (0x00U) /*!< Vbat reference voltage is 1.8V */
#define PWC_VBAT_REF_VOL_2P0V (0x01U) /*!< Vbat reference voltage is 2.0V */
/**
* @}
*/
/**
* @defgroup PWC_BACKUP_RAM_Flag PWC Backup RAM Flag
* @{
*/
#define PWC_BACKUP_RAM_FLAG_RAMPDF (PWC_VBATCR_RAMPDF) /*!< Backup RAM power down flag */
#define PWC_BACKUP_RAM_FLAG_RAMVALID (PWC_VBATCR_RAMVALID) /*!< Backup RAM read/write flag */
/**
* @}
*/
/**
* @defgroup PWC_WKT_Clock_Source PWC WKT Clock Source
* @{
*/
#define PWC_WKT_CLK_SRC_64HZ (0U) /*!< 64Hz Clock */
#define PWC_WKT_CLK_SRC_XTAL32 (PWC_WKTC2_WKCKS_0) /*!< XTAL32 Clock */
#define PWC_WKT_CLK_SRC_RTCLRC (PWC_WKTC2_WKCKS_1) /*!< RTCLRC Clock */
/**
* @}
*/
/**
* @defgroup PWC_REG_Write_Unlock_Code PWC register unlock code.
* @brief Lock/unlock Code for each module
* PWC_UNLOCK_CODE_0:
* Below registers are locked in CLK module.
* XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR,
* MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR,
* SCFGR, UFSCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR,
* XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM.
* PWC_UNLOCK_CODE_1:
* Below registers are locked in PWC module.
* PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0,
* PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM.
* Below registers are locked in CLK module.
* PERICKSEL, I2SCKSEL,
* Below register is locked in RMU module.
* RSTF0
* PWC_UNLOCK_CODE_2:
* Below registers are locked in PWC module.
* PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR
* @{
*/
#define PWC_UNLOCK_CODE_0 (0xA501U)
#define PWC_UNLOCK_CODE_1 (0xA502U)
#define PWC_UNLOCK_CODE_2 (0xA508U)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup PWC_Global_Functions
* @{
*/
/**
* @brief Lock PWC, CLK, RMU register.
* @param [in] u16Module Lock code for each module.
* @arg PWC_UNLOCK_CODE_0:
* Below registers are locked in CLK module.
* XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR,
* MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR,
* SCFGR, UFSCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR,
* XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM.
* @arg PWC_UNLOCK_CODE_1:
* Below registers are locked in PWC module.
* PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0,
* PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM.
* Below registers are locked in VBAT module.
* RSTR, BATCR0, VBTBKR0~VBTBK127.
* Below registers are locked in CLK module.
* PERICKSEL, I2SCKSEL,
* Below register is locked in RMU module.
* RSTF0
* @arg PWC_UNLOCK_CODE_2:
* Below registers are locked in PWC module.
* PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR
* @retval None
*/
__STATIC_INLINE void PWC_Lock(uint16_t u16Module)
{
M4_PWC->FPRC = (0xA500U | (uint16_t)((uint16_t)(~u16Module) & (M4_PWC->FPRC)));
}
/**
* @brief Unlock PWC, CLK, RMU register.
* @param [in] u16Module Unlock code for each module.
* @arg PWC_UNLOCK_CODE_0:
* Below registers are unlocked in CLK module.
* XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR,
* MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR,
* SCFGR, UFSCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR,
* XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM.
* @arg PWC_UNLOCK_CODE_1:
* Below registers are unlocked in PWC module.
* PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0,
* PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM.
* Below registers are unlocked in VBAT module.
* RSTR, BATCR0, VBTBKR0~VBTBK127.
* Below registers are unlocked in CLK module.
* PERICKSEL, I2SCKSEL,
* Below register is unlocked in RMU module.
* RSTF0
* @arg PWC_UNLOCK_CODE_2:
* Below registers are unlocked in PWC module.
* PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR
* @retval None
*/
__STATIC_INLINE void PWC_Unlock(uint16_t u16Module)
{
SET_REG16_BIT(M4_PWC->FPRC, u16Module);
}
/**
* @brief Lock PWC_FCG0 register .
* @param None
* @retval None
*/
__STATIC_INLINE void PWC_FCG0_Lock(void)
{
WRITE_REG32(M4_PWC->FCG0PC, 0xA5A50000UL);
}
/**
* @brief Unlock PWR_FCG0 register.
* @param None
* @retval None
* @note Call this function before PWC_Fcg0PeriphClockCmd()
*/
__STATIC_INLINE void PWC_FCG0_Unlock(void)
{
WRITE_REG32(M4_PWC->FCG0PC, 0xA5A50001UL);
}
en_result_t PWC_PowerDownStructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig);
en_result_t PWC_PowerDownConfig(const stc_pwc_pd_mode_config_t *pstcPDModeConfig);
void PWC_EnterPowerDownMode(void);
void PWC_EnterStopMode(void);
void PWC_EnterSleepMode(void);
en_result_t PWC_StopStructInit(stc_pwc_stop_mode_config *pstcStopConfig);
en_result_t PWC_StopConfig(const stc_pwc_stop_mode_config *pstcStopConfig);
void PWC_StopDrvConfig(uint8_t u8StopDrv);
void PWC_StopClockKeepConfig(uint16_t u16ClkKeep);
void PWC_StopFlashWaitConfig(uint16_t u16FlashWait);
void PWC_StopExBusHoldConfig(uint16_t u16ExBusHold);
en_result_t PWC_HighSpeedToLowSpeed(void);
en_result_t PWC_LowSpeedToHighSpeed(void);
void PWC_HrcPwrCmd(en_functional_state_t enNewState);
void PWC_PllPwrCmd(en_functional_state_t enNewState);
void PWC_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState);
void PWC_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState);
void PWC_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState);
void PWC_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState);
en_result_t PWC_RamConfig(const stc_pwc_ram_config_t *pstcRamConfig);
en_result_t PWC_PVD_Init(uint8_t u8Ch, const stc_pwc_pvd_config_t *pstcPvdConfig);
en_result_t PWC_PVD_StructInit(stc_pwc_pvd_config_t *pstcPvdConfig);
en_flag_status_t PWC_PVD_GetStatus(uint8_t u8Flag);
void PWC_PVD_ClearStatus(void);
void PWC_PdWakeup0Cmd(uint8_t u8Wkup0Evt, en_functional_state_t enNewState);
void PWC_PdWakeup1Cmd(uint8_t u8Wkup1Evt, en_functional_state_t enNewState);
void PWC_PdWakeup2Cmd(uint8_t u8Wkup2Evt, en_functional_state_t enNewState);
void PWC_PdWakeupTrigConfig(uint8_t u8WkupEvt, uint8_t u8TrigEdge);
en_flag_status_t PWC_GetWakeup0Status(uint8_t u8Flag);
en_flag_status_t PWC_GetWakeup1Status(uint8_t u8Flag);
void PWC_AdcBufCmd(en_functional_state_t enNewState);
void PWC_AdcInternVolSel(uint8_t u8AdcInternVol);
void PWC_VBAT_MonitorVolSel(uint8_t u8RefVol);
void PWC_VBAT_MonitorCmd(en_functional_state_t enNewState);
uint8_t PWC_VBAT_GetVolStatus(void);
void PWC_VBAT_MeasureVolCmd(en_functional_state_t enNewState);
void PWC_VBAT_Reset(void);
void PWC_VBAT_PwrCmd(en_functional_state_t enNewState);
void PWC_BkRamPwrCmd(en_functional_state_t enNewState);
en_flag_status_t PWC_GetBkRamStatus(uint8_t u8Flag);
void PWC_WriteBackupReg(uint8_t u8RegNum, uint8_t u8RegVal);
uint8_t PWC_ReadBackupReg(uint8_t u8RegNum);
void PWC_WKT_Init(uint8_t u8ClkSrc, uint16_t u16CmpVal);
void PWC_WKT_SetCompareValue(uint16_t u16CmpVal);
uint16_t PWC_WKT_GetCompareValue(void);
void PWC_WKT_Cmd(en_functional_state_t enNewState);
en_flag_status_t PWC_WKT_GetStatus(void);
void PWC_WKT_ClearStatus(void);
/**
* @}
*/
#endif /* DDL_PWC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_PWC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_qspi.h
* @brief This file contains all the functions prototypes of the QSPI driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Wuze First version
2020-07-15 Wuze Corrected the definition of 'QSPI_4BIC_ENABLE'.
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_QSPI_H__
#define __HC32F4A0_QSPI_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_QSPI
* @{
*/
#if (DDL_QSPI_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup QSPI_Global_Types QSPI Global Types
* @{
*/
/**
* @brief QSPI initialization structure.
*/
typedef struct
{
uint32_t u32ClkDiv; /*!< Specifies the clock divider for QSCK. QSCK = HCLK / u32ClkDiv.
This parameter can be a value between 2U and 64U, inclusive. */
uint32_t u32CSSetupTiming; /*!< Specifies the setup timing of CS.
This parameter can be a value of @ref QSPI_CS_Setup_Timing */
uint32_t u32CSReleaseTiming; /*!< Specifies the hold timing of CS.
This parameter can be a value of @ref QSPI_CS_Release_Timing */
uint32_t u32CSIdleTime; /*!< Specifies the minimum idle time for CS. CS needs idle(stay high) for several cycles between commands.
This parameter can be a value of between 1U and 16U, inclusive. */
uint32_t u32CSExtendTime; /*!< Extend the time of chip-select signal after SPI bus access.
This parameter can be a value of @ref QSPI_CS_Extend_Time */
uint32_t u32SPIMode; /*!< Specifies the SPI mode. The difference between SPI modes 0 and 3 is the standby level of the QSCK signal.
The standby level of the QSCK signal in SPI mode 0 is low, and high in SPI mode 3.
This parameter can be a value of @ref QSPI_SPI_Mode */
uint32_t u32PrefetchCmd; /*!< Enable or disable prefeth function.
This parameter can be a value of @ref QSPI_Prefetch_Cmd */
uint32_t u32PrefetchStopPos; /*!< Specifies the position of prefetch stop.
This parameter can be a value of @ref QSPI_Prefetch_Stop_Position */
uint32_t u32WPLevel; /*!< Specifies the level of pin WP(IO2).
This parameter can be a value of @ref QSPI_WP_Level */
uint32_t u32CommMode; /*!< Specifies the communication mode.
This parameter can be a value of @ref QSPI_Communication_Mode */
uint32_t u32AddrWidth; /*!< Specifies the address width.
This parameter can be a value of @ref QSPI_Addr_Width */
uint32_t u32InstrMode; /*!< Specifies the instruction mode.
This parameter can be a value of @ref QSPI_Instruction_Mode */
uint32_t u32AddrMode; /*!< Specifies the address mode.
This parameter can be a value of @ref QSPI_Addr_Mode */
uint32_t u32DataMode; /*!< Specifies the data mode (used for dummy cycles and data phases)
This parameter can be a value of @ref QSPI_Data_Mode */
uint32_t u32ReadMode; /*!< Specifies the read mode.
This parameter can be a value of @ref QSPI_Read_Mode */
uint8_t u8RomAccessInstr; /*!< Rom access instruction. This parameter only supports read instruction of QSPI flash now.
Tis instruction must correspond to the read mode that specified by parameter 'u32ReadMode'. */
uint32_t u32DummyCycles; /*!< Specifies the number of dummy cycles for fast read.
This parameter can be a value between 3U and 18U. */
} stc_qspi_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup QSPI_Global_Macros QSPI Global Macros
* @{
*/
/**
* @defgroup QSPI_Read_Mode QSPI Read Mode
* @{
*/
#define QSPI_READ_STANDARD_READ (0x0U) /*!< Standard read mode (no dummy cycles). */
#define QSPI_READ_FAST_READ (QSPI_CR_MDSEL_0) /*!< Fast read mode (dummy cycles between address and data). */
#define QSPI_READ_FAST_READ_DUAL_OUTPUT (QSPI_CR_MDSEL_1) /*!< Fast read dual output mode (data on 2 lines). */
#define QSPI_READ_FAST_READ_DUAL_IO (QSPI_CR_MDSEL_1 | \
QSPI_CR_MDSEL_0) /*!< Fast read dual I/O mode (address and data on 2 lines). */
#define QSPI_READ_FAST_READ_QUAD_OUTPUT (QSPI_CR_MDSEL_2) /*!< Fast read quad output mode (data on 4 lines). */
#define QSPI_READ_FAST_READ_QUAD_IO (QSPI_CR_MDSEL_2 | \
QSPI_CR_MDSEL_0) /*!< Fast read quad I/O mode (address and data on 4 lines). */
#define QSPI_READ_CUSTOM_STANDARD_READ (QSPI_CR_MDSEL_2 | \
QSPI_CR_MDSEL_1) /*!< Custom standard read mode. */
#define QSPI_READ_CUSTOM_FAST_READ (QSPI_CR_MDSEL_2 | \
QSPI_CR_MDSEL_1 | \
QSPI_CR_MDSEL_0) /*!< Custom fast read mode. */
/**
* @}
*/
/**
* @defgroup QSPI_Prefetch_Cmd QSPI Prefetch Cmd
* @{
*/
#define QSPI_PREFETCH_DISABLE (0x0U) /*!< Disable prefetch. */
#define QSPI_PREFETCH_ENABLE (QSPI_CR_PFE) /*!< Enable prefetch. */
/**
* @}
*/
/**
* @defgroup QSPI_Prefetch_Stop_Position QSPI Prefetch Stop Position
* @{
*/
#define QSPI_PREFETCH_STOP_BYTE_EDGE (0x0U) /*!< Stop prefetch at the edge of byte. */
#define QSPI_PREFETCH_STOP_IMMED (QSPI_CR_PFSAE) /*!< Stop prefetch at current position immediately. */
/**
* @}
*/
/**
* @defgroup QSPI_Communication_Mode QSPI Communication Mode
* @{
*/
#define QSPI_COMM_ROM_ACCESS (0x0U) /*!< ROM access mode. */
#define QSPI_COMM_DIRECT_COMM (QSPI_CR_DCOME) /*!< Direct communication mode. */
/**
* @}
*/
/**
* @defgroup QSPI_XIP_Mode_Command QSPI XIP Mode Command
* @{
*/
#define QSPI_XIP_DISABLE (0x0U) /*!< XIP mode disable. */
#define QSPI_XIP_ENABLE (QSPI_CR_XIPE) /*!< XIP mode enable. */
/**
* @}
*/
/**
* @defgroup QSPI_SPI_Mode QSPI SPI Mode
* @{
*/
#define QSPI_SPI_MODE_0 (0x0U) /*!< Selects SPI mode 0. */
#define QSPI_SPI_MODE_3 (QSPI_CR_SPIMD3) /*!< Selects SPI mode 3. */
/**
* @}
*/
/**
* @defgroup QSPI_Instruction_Mode QSPI Instruction Mode
* @{
*/
#define QSPI_INSTR_1LINE (0x0U) /*!< Instruction on a single line. */
#define QSPI_INSTR_2LINE (QSPI_CR_IPRSL_0) /*!< Instruction on 2 lines. */
#define QSPI_INSTR_4LINE (QSPI_CR_IPRSL_1) /*!< Instruction on 4 lines. */
/**
* @}
*/
/**
* @defgroup QSPI_Addr_Mode QSPI Address Mode
* @{
*/
#define QSPI_ADDR_1LINE (0x0U) /*!< Address on a single line. */
#define QSPI_ADDR_2LINE (QSPI_CR_APRSL_0) /*!< Address on 2 lines. */
#define QSPI_ADDR_4LINE (QSPI_CR_APRSL_1) /*!< Address on 4 lines. */
/**
* @}
*/
/**
* @defgroup QSPI_Data_Mode QSPI Data Mode
* @{
*/
#define QSPI_DATA_1LINE (0x0U) /*!< Data on a single line. */
#define QSPI_DATA_2LINE (QSPI_CR_DPRSL_0) /*!< Data on 2 lines. */
#define QSPI_DATA_4LINE (QSPI_CR_DPRSL_1) /*!< Data on 4 lines. */
/**
* @}
*/
/**
* @defgroup QSPI_CS_Extend_Time QSPI Chip-select Extend Time
* @{
*/
#define QSPI_CS_EXTEND_0CYCLE (0x0U) /*!< Do not extend chip-select signal time. */
#define QSPI_CS_EXTEND_32CYCLE (QSPI_CSCR_SSNW_0) /*!< Extend chip-select time by 32 QSCK cycles. */
#define QSPI_CS_EXTEND_128CYCLE (QSPI_CSCR_SSNW_1) /*!< Extend chip-select time by 128 QSCK cycles. */
#define QSPI_CS_EXTEND_INFINITE (QSPI_CSCR_SSNW_1 | \
QSPI_CSCR_SSNW_0) /*!< Extend chip-select time infinitely. */
/**
* @}
*/
/**
* @defgroup QSPI_Addr_Width QSPI Address Width
* @{
*/
#define QSPI_ADDR_WIDTH_1BYTE (0x0U) /*!< QSPI address width is 1 byte. */
#define QSPI_ADDR_WIDTH_2BYTE (QSPI_FCR_AWSL_0) /*!< QSPI address width is 2 bytes. */
#define QSPI_ADDR_WIDTH_3BYTE (QSPI_FCR_AWSL_1) /*!< QSPI address width is 3 bytes. */
#define QSPI_ADDR_WIDTH_4BYTE (QSPI_FCR_AWSL_1 | \
QSPI_FCR_AWSL_0) /*!< QSPI address width is 4 bytes. */
/**
* @}
*/
/**
* @defgroup QSPI_4BIC_Command QSPI 4-Byte Address Instruction Read Code Command
* @note Valid when the serial interface address width is 4 bytes.
* @{
*/
#define QSPI_4BIC_DISABLE (0x0U) /*!< Do not use 4-byte address read instruction code. */
#define QSPI_4BIC_ENABLE (QSPI_FCR_FOUR_BIC) /*!< Use 4-byte address read instruction code. */
/**
* @}
*/
/**
* @defgroup QSPI_CS_Release_Timing QSPI Chip-select Hold Timing
* @{
*/
#define QSPI_CS_RELEASE_AFTER_0P5_CYCLE (0x0U) /*!< Release chip-select signal 0.5 QSCK cycles after the last rising edge of QSCK. */
#define QSPI_CS_RELEASE_AFTER_1P5_CYCLE (QSPI_FCR_SSNHD) /*!< Release chip-select signal 1.5 QSCK cycles after the last rising edge of QSCK. */
/**
* @}
*/
/**
* @defgroup QSPI_CS_Setup_Timing QSPI Chip-select Setup Timing
* @{
*/
#define QSPI_CS_SETUP_BEFORE_0P5_CYCLE (0x0U) /*!< Output chip-select signal 0.5 QSCK cycles before the first rising edge of QSCK. */
#define QSPI_CS_SETUP_BEFORE_1P5_CYCLE (QSPI_FCR_SSNLD) /*!< Output chip-select signal 1.5 QSCK cycles before the first rising edge of QSCK. */
/**
* @}
*/
/**
* @defgroup QSPI_WP_Level QSPI Write Protect Pin Level
* @{
*/
#define QSPI_WP_LOW (0x0U) /*!< WP(QIO2) output low. */
#define QSPI_WP_HIGH (QSPI_FCR_WPOL) /*!< WP(QIO2) output high. */
/**
* @}
*/
/**
* @defgroup QSPI_QSCK_Duty_Correction_Command QSPI QSCK Duty Correction Command
* @{
*/
#define QSPI_DUTY_CORRECTION_DISABLE (0x0U) /*!< Make no duty ratio correction on QSCK. */
#define QSPI_DUTY_CORRECTION_ENABLE (QSPI_FCR_DUTY) /*!< Delay the rising of the QSCK signal by 0.5 HCLK cycles. \
(Valid when HCLK is multiplied by an odd number.) */
/**
* @}
*/
/**
* @defgroup QSPI_Status_Flag QSPI Status Flag
* @{
*/
#define QSPI_FLAG_DIRECT_COMM_BUSY (QSPI_SR_BUSY) /*!< Serial transfer being processed. */
#define QSPI_FLAG_XIP_MODE (QSPI_SR_XIPF) /*!< XIP mode. */
#define QSPI_FLAG_ROM_ACCESS_ERR (QSPI_SR_RAER) /*!< ROM access detection status in direct communication mode. */
#define QSPI_FLAG_PREFETCH_BUF_FULL (QSPI_SR_PFFUL) /*!< Prefetch buffer is full. */
#define QSPI_FLAG_PREFETCH_ACTIVE (QSPI_SR_PFAN) /*!< Prefetch function operating. */
#define QSPI_FLAG_ALL (QSPI_FLAG_DIRECT_COMM_BUSY | \
QSPI_FLAG_XIP_MODE | \
QSPI_FLAG_ROM_ACCESS_ERR | \
QSPI_FLAG_PREFETCH_BUF_FULL | \
QSPI_FLAG_PREFETCH_ACTIVE)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup QSPI_Global_Functions
* @{
*/
/**
* @brief Enter direct communication mode.
* @param None
* @retval None
*/
__STATIC_INLINE void QSPI_EnterDirectCommMode(void)
{
/* Set standard read mode. */
CLEAR_REG32_BIT(M4_QSPI->CR, QSPI_CR_MDSEL);
/* Enter direct communication mode. */
SET_REG32_BIT(M4_QSPI->CR, QSPI_CR_DCOME);
}
/**
* @brief Exit direct communication mode.
* @param None
* @retval None
*/
__STATIC_INLINE void QSPI_ExitDirectCommMode(void)
{
CLEAR_REG32_BIT(M4_QSPI->CR, QSPI_CR_DCOME);
}
/**
* @brief Write data in direct communication mode.
* @param [in] u8Val Byte data.
* @retval None
*/
__STATIC_INLINE void QSPI_WriteDirectCommValue(uint8_t u8Val)
{
WRITE_REG32(M4_QSPI->DCOM, u8Val);
}
/**
* @brief Read data in communication mode.
* @param None
* @retval Byte data.
*/
__STATIC_INLINE uint8_t QSPI_ReadDirectCommValue(void)
{
return (uint8_t)M4_QSPI->DCOM;
}
/**
* @brief Set ROM access instruction.
* @param [in] u8Instr ROM access instruction.
* @retval None
*/
__STATIC_INLINE void QSPI_SetRomAccressInstr(uint8_t u8Instr)
{
WRITE_REG32(M4_QSPI->CCMD, u8Instr);
}
en_result_t QSPI_Init(const stc_qspi_init_t *pstcInit);
void QSPI_DeInit(void);
en_result_t QSPI_StructInit(stc_qspi_init_t *pstcInit);
en_result_t QSPI_WriteData(uint32_t u32Instr, uint32_t u32Address, \
const uint8_t pu8Src[], uint32_t u32SrcSize);
en_result_t QSPI_ReadData(uint32_t u32Address, uint8_t pu8Dest[], uint32_t u32DestSize);
void QSPI_SetReadMode(uint32_t u32ReadMode, uint8_t u8ReadInstr, uint32_t u32DummyCycles);
void QSPI_DutyCorrectCmd(en_functional_state_t enNewState);
void QSPI_PrefetchCmd(en_functional_state_t enNewState);
void QSPI_XIPModeCmd(en_functional_state_t enNewState);
void QSPI_SetWPPinLevel(uint32_t u32Level);
void QSPI_4ByteAddrModeCmd(en_functional_state_t enNewState);
void QSPI_SelectBlock(uint32_t u32Block);
uint32_t QSPI_GetPrefetchedSize(void);
en_flag_status_t QSPI_GetStatus(uint32_t u32Flag);
void QSPI_ClrStatus(uint32_t u32Flag);
void QSPI_EnterDirectCommMode(void);
void QSPI_ExitDirectCommMode(void);
void QSPI_WriteDirectCommValue(uint8_t u8Val);
uint8_t QSPI_ReadDirectCommValue(void);
void QSPI_SetRomAccressInstr(uint8_t u8Instr);
/**
* @}
*/
#endif /* DDL_QSPI_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_QSPI_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_rmu.h
* @brief This file contains all the functions prototypes of the RMU driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Heqb First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_RMU_H__
#define __HC32F4A0_RMU_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_RMU
* @{
*/
#if (DDL_RMU_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup RMU_Global_Macros RMU Global Macros
* @{
*/
/**
* @defgroup RMU_ResetCause Rmu reset cause
* @{
*/
#define RMU_RST_POWER_ON (RMU_RSTF0_PORF) /*!< Power on reset */
#define RMU_RST_RESET_PIN (RMU_RSTF0_PINRF) /*!< Reset pin reset */
#define RMU_RST_BROWN_OUT (RMU_RSTF0_BORF) /*!< Brown-out reset */
#define RMU_RST_PVD1 (RMU_RSTF0_PVD1RF) /*!< Program voltage Detection 1 reset */
#define RMU_RST_PVD2 (RMU_RSTF0_PVD2RF) /*!< Program voltage Detection 2 reset */
#define RMU_RST_WDT (RMU_RSTF0_WDRF) /*!< Watchdog timer reset */
#define RMU_RST_SWDT (RMU_RSTF0_SWDRF) /*!< Special watchdog timer reset */
#define RMU_RST_POWER_DOWN (RMU_RSTF0_PDRF) /*!< Power down reset */
#define RMU_RST_SOFTWARE (RMU_RSTF0_SWRF) /*!< Software reset */
#define RMU_RST_MPU_ERR (RMU_RSTF0_MPUERF) /*!< Mpu error reset */
#define RMU_RST_RAM_PARITY_ERR (RMU_RSTF0_RAPERF) /*!< Ram parity error reset */
#define RMU_RST_RAM_ECC (RMU_RSTF0_RAECRF) /*!< Ram ECC reset */
#define RMU_RST_CLK_ERR (RMU_RSTF0_CKFERF) /*!< Clk frequence error reset */
#define RMU_RST_XTAL_ERR (RMU_RSTF0_XTALERF) /*!< Xtal error reset */
#define RMU_RST_LOCKUP (RMU_RSTF0_LKUPRF) /*!< M4 Lockup reset */
#define RMU_RST_MULTI (RMU_RSTF0_MULTIRF) /*!< Multiply reset cause */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup RMU_Global_Functions
* @{
*/
en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause);
void RMU_ClrStatus(void);
void RMU_CPULockUpCmd(en_functional_state_t enNewState);
/**
* @}
*/
#endif /* DDL_RMU_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_RMU_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_rtc.h
* @brief This file contains all the functions prototypes of the RTC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_RTC_H__
#define __HC32F4A0_RTC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_RTC
* @{
*/
#if (DDL_RTC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup RTC_Global_Types RTC Global Types
* @{
*/
/**
* @brief RTC Init structure definition
*/
typedef struct
{
uint8_t u8ClockSource; /*!< Specifies the RTC clock source.
This parameter can be a value of @ref RTC_Clock_Source */
uint8_t u8HourFormat; /*!< Specifies the RTC hour format.
This parameter can be a value of @ref RTC_Hour_Format */
uint8_t u8PeriodInterrupt; /*!< Specifies the RTC period interrupt.
This parameter can be a value of @ref RTC_Period_Interrupt */
uint8_t u8ClkCompenEn; /*!< Specifies the validity of RTC clock compensation.
This parameter can be a value of @ref RTC_Clock_Compensation */
uint16_t u16ClkCompenValue; /*!< Specifies the value of RTC clock compensation.
This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF */
uint8_t u8CompenMode; /*!< Specifies the compensation mode of one Hz output.
This parameter can be a value of @ref RTC_Output_Compen_Mode */
} stc_rtc_init_t;
/**
* @brief RTC Date structure definition
*/
typedef struct
{
uint8_t u8Year; /*!< Specifies the RTC Year.
This parameter can be a number between Min_Data = 0 and Max_Data = 99 */
uint8_t u8Month; /*!< Specifies the RTC Month (in Decimal format).
This parameter can be a value of @ref RTC_Month */
uint8_t u8Day; /*!< Specifies the RTC Day.
This parameter can be a number between Min_Data = 1 and Max_Data = 31 */
uint8_t u8Weekday; /*!< Specifies the RTC Weekday.
This parameter can be a value of @ref RTC_Weekday */
} stc_rtc_date_t;
/**
* @brief RTC Time structure definition
*/
typedef struct
{
uint8_t u8Hour; /*!< Specifies the RTC Hour.
This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FORMAT_12 is selected.
This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FORMAT_24 is selected */
uint8_t u8Minute; /*!< Specifies the RTC Minute.
This parameter can be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t u8Second; /*!< Specifies the RTC Second.
This parameter can be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t u8AmPm; /*!< Specifies the RTC Am/Pm Time (in RTC_HOUR_FORMAT_12 mode).
This parameter can be a value of @ref RTC_Hour12_AM_PM */
} stc_rtc_time_t;
/**
* @brief RTC Alarm structure definition
*/
typedef struct
{
uint8_t u8AlarmHour; /*!< Specifies the RTC Alarm Hour.
This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FORMAT_12 is selected.
This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FORMAT_24 is selected */
uint8_t u8AlarmMinute; /*!< Specifies the RTC Alarm Minute.
This parameter can be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t u8AlarmWeekday; /*!< Specifies the RTC Alarm Weekday.
This parameter can be a value of @ref RTC_Alarm_Weekday */
uint8_t u8AlarmAmPm; /*!< Specifies the RTC Alarm Am/Pm Time (in RTC_HOUR_FORMAT_12 mode).
This parameter can be a value of @ref RTC_Hour12_AM_PM */
} stc_rtc_alarm_t;
/**
* @brief RTC Intrusion structure definition
*/
typedef struct
{
uint8_t u8TimeStampEn; /*!< Specifies the validity of RTC intrusion timestemp.
This parameter can be a value of @ref RTC_Intrusion_Timestamp */
uint8_t u8ResetBackupRegEn; /*!< Specifies the validity of RTC intrusion event that trigger backup registers reset.
This parameter can be a value of @ref RTC_Reset_Backup_Register */
uint8_t u8Filter; /*!< Specifies the RTC intrusion pin filter.
This parameter can be a value of @ref RTC_Intrusion_Filter */
uint8_t u8TrigEdge; /*!< Specifies the RTC intrusion detect edge.
This parameter can be a value of @ref RTC_Intrusion_Detect_Edge */
} stc_rtc_intrusion_t;
/**
* @brief RTC Timestamp structure definition
*/
typedef struct
{
stc_rtc_time_t stcTSTime; /*!< Specifies the RTC Intrusion Timestamp Time members */
uint8_t u8TSMonth; /*!< Specifies the Month of RTC timestamp (in Decimal format).
This parameter can be a value of @ref RTC_Month */
uint8_t u8TSDay; /*!< Specifies the Day of RTC timestamp.
This parameter can be a number between Min_Data = 1 and Max_Data = 31 */
} stc_rtc_timestamp_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup RTC_Global_Macros RTC Global Macros
* @{
*/
/**
* @defgroup RTC_Data_Format RTC Data Format
* @{
*/
#define RTC_DATA_FORMAT_DEC (0x00U) /*!< Decimal data format */
#define RTC_DATA_FORMAT_BCD (0x01U) /*!< BCD data format */
/**
* @}
*/
/**
* @defgroup RTC_Clock_Source RTC Clock Source
* @{
*/
#define RTC_CLOCK_SOURCE_XTAL32 (0U) /*!< XTAL32 Clock */
#define RTC_CLOCK_SOURCE_RTCLRC (RTC_CR3_RCKSEL | RTC_CR3_LRCEN) /*!< RTC LRC Clock */
/**
* @}
*/
/**
* @defgroup RTC_Hour_Format RTC Hour Format
* @{
*/
#define RTC_HOUR_FORMAT_12 (0U) /*!< 12 hour time system */
#define RTC_HOUR_FORMAT_24 (RTC_CR1_AMPM) /*!< 24 hour time system */
/**
* @}
*/
/**
* @defgroup RTC_Period_Interrupt RTC Period Interrupt
* @{
*/
#define RTC_PERIOD_INT_INVALID (0U) /*!< Periodic interrupt invalid */
#define RTC_PERIOD_INT_HALF_SECOND (RTC_CR1_PRDS_0) /*!< Periodic interrupt per half second */
#define RTC_PERIOD_INT_ONE_SECOND (RTC_CR1_PRDS_1) /*!< Periodic interrupt per second */
#define RTC_PERIOD_INT_ONE_MINUTE (RTC_CR1_PRDS_0 | RTC_CR1_PRDS_1) /*!< Periodic interrupt per minute */
#define RTC_PERIOD_INT_ONE_HOUR (RTC_CR1_PRDS_2) /*!< Periodic interrupt per hour */
#define RTC_PERIOD_INT_ONE_DAY (RTC_CR1_PRDS_0 | RTC_CR1_PRDS_2) /*!< Periodic interrupt per day */
#define RTC_PERIOD_INT_ONE_MONTH (RTC_CR1_PRDS_1 | RTC_CR1_PRDS_2) /*!< Periodic interrupt per month */
/**
* @}
*/
/**
* @defgroup RTC_Clock_Compensation RTC Clock Compensation
* @{
*/
#define RTC_CLOCK_COMPEN_DISABLE (0U)
#define RTC_CLOCK_COMPEN_ENABLE (RTC_ERRCRH_COMPEN)
/**
* @}
*/
/**
* @defgroup RTC_Output_Compen_Mode RTC Output Compensation Mode
* @{
*/
#define RTC_OUTPUT_COMPEN_MODE_DISTRIBUTED (0U) /*!< Distributed compensation 1Hz output */
#define RTC_OUTPUT_COMPEN_MODE_UNIFORM (RTC_CR1_ONEHZSEL) /*!< Uniform compensation 1Hz output */
/**
* @}
*/
/**
* @defgroup RTC_Hour12_AM_PM RTC Hour12 AM/PM
* @{
*/
#define RTC_HOUR12_AM_HOUR24 (0U) /*!< AM or 24-hour format */
#define RTC_HOUR12_PM (RTC_HOUR_HOURD_1) /*!< PM */
/**
* @}
*/
/**
* @defgroup RTC_Month RTC Month
* @{
*/
#define RTC_MONTH_JANUARY (0x01U)
#define RTC_MONTH_FEBRUARY (0x02U)
#define RTC_MONTH_MARCH (0x03U)
#define RTC_MONTH_APRIL (0x04U)
#define RTC_MONTH_MAY (0x05U)
#define RTC_MONTH_JUNE (0x06U)
#define RTC_MONTH_JULY (0x07U)
#define RTC_MONTH_AUGUST (0x08U)
#define RTC_MONTH_SEPTEMBER (0x09U)
#define RTC_MONTH_OCTOBER (0x0AU)
#define RTC_MONTH_NOVEMBER (0x0BU)
#define RTC_MONTH_DECEMBER (0x0CU)
/**
* @}
*/
/**
* @defgroup RTC_Weekday RTC Weekday
* @{
*/
#define RTC_WEEKDAY_SUNDAY (0x00U)
#define RTC_WEEKDAY_MONDAY (0x01U)
#define RTC_WEEKDAY_TUESDAY (0x02U)
#define RTC_WEEKDAY_WEDNESDAY (0x03U)
#define RTC_WEEKDAY_THURSDAY (0x04U)
#define RTC_WEEKDAY_FRIDAY (0x05U)
#define RTC_WEEKDAY_SATURDAY (0x06U)
/**
* @}
*/
/**
* @defgroup RTC_Alarm_Weekday RTC Alarm Weekday
* @{
*/
#define RTC_ALARM_WEEKDAY_SUNDAY (0x01U)
#define RTC_ALARM_WEEKDAY_MONDAY (0x02U)
#define RTC_ALARM_WEEKDAY_TUESDAY (0x04U)
#define RTC_ALARM_WEEKDAY_WEDNESDAY (0x08U)
#define RTC_ALARM_WEEKDAY_THURSDAY (0x10U)
#define RTC_ALARM_WEEKDAY_FRIDAY (0x20U)
#define RTC_ALARM_WEEKDAY_SATURDAY (0x40U)
/**
* @}
*/
/**
* @defgroup RTC_Intrusion_Channel RTC Intrustion Channel
* @{
*/
#define RTC_INTRU_CH0 (0x00U)
#define RTC_INTRU_CH1 (0x04U)
/**
* @}
*/
/**
* @defgroup RTC_Intrusion_Timestamp RTC Intrustion Timestamp
* @{
*/
#define RTC_INTRU_TIMESTAMP_DISABLE (0U)
#define RTC_INTRU_TIMESTAMP_ENABLE (RTC_TPCR0_TSTPE0)
/**
* @}
*/
/**
* @defgroup RTC_Reset_Backup_Register RTC Reset Backup Register
* @{
*/
#define RTC_RESET_BACKUP_REG_DISABLE (0U)
#define RTC_RESET_BACKUP_REG_ENABLE (RTC_TPCR0_TPRSTE0)
/**
* @}
*/
/**
* @defgroup RTC_Intrusion_Filter RTC Intrusion Filter
* @{
*/
#define RTC_INTRU_FILTER_INVALID (0U) /*!< Invalid filter function */
#define RTC_INTRU_FILTER_THREE_TIME (RTC_TPCR0_TPNF0_1) /*!< The filter detection is consistent with the timing clock for 3 times */
#define RTC_INTRU_FILTER_THREE_TIME_CLK_DIV32 (RTC_TPCR0_TPNF0) /*!< The filter detection is consistent with the 32 frequency division of the timing clock for 3 times */
/**
* @}
*/
/**
* @defgroup RTC_Intrusion_Detect_Edge RTC Intrusion Detect Edge
* @{
*/
#define RTC_DETECT_EDGE_NONE (0U) /*!< No detect */
#define RTC_DETECT_EDGE_RISING (RTC_TPCR0_TPCT0_0) /*!< Detect rising edge */
#define RTC_DETECT_EDGE_FALLING (RTC_TPCR0_TPCT0_1) /*!< Detect falling edge */
#define RTC_DETECT_EDGE_RISING_FALLING (RTC_TPCR0_TPCT0) /*!< Detect rising and falling edge */
/**
* @}
*/
/**
* @defgroup RTC_Flag RTC Flag
* @{
*/
#define RTC_FLAG_PRDF (RTC_CR2_PRDF) /*!< Period flag */
#define RTC_FLAG_ALMF (RTC_CR2_ALMF) /*!< Alarm flag */
#define RTC_FLAG_RWEN (RTC_CR2_RWEN) /*!< Read and write permission flag */
#define RTC_FLAG_TPOVF ((uint32_t)RTC_TPSR_TPOVF << 16U) /*!< Intrusion overflow flag */
#define RTC_FLAG_TPF0 ((uint32_t)RTC_TPSR_TPF0 << 16U) /*!< RTCIC0 intrusion flag */
#define RTC_FLAG_TPF1 ((uint32_t)RTC_TPSR_TPF1 << 16U) /*!< RTCIC1 intrusion flag */
/**
* @}
*/
/**
* @defgroup RTC_Interrupt RTC Interrupt
* @{
*/
#define RTC_INT_PRDIE (RTC_CR2_PRDIE) /*!< Period interrupt */
#define RTC_INT_ALMIE (RTC_CR2_ALMIE) /*!< Alarm interrupt */
#define RTC_INT_TPIE0 ((uint32_t)RTC_TPCR0_TPIE0 << 8U) /*!< RTCIC0 intrusion interrupt */
#define RTC_INT_TPIE1 ((uint32_t)RTC_TPCR1_TPIE1 << 16U) /*!< RTCIC1 intrusion interrupt */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup RTC_Global_Functions
* @{
*/
/* Initialization and configuration functions */
en_result_t RTC_DeInit(void);
en_result_t RTC_Init(const stc_rtc_init_t *pstcRtcInit);
en_result_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit);
en_result_t RTC_EnterRwMode(void);
en_result_t RTC_ExitRwMode(void);
void RTC_PeriodIntConfig(uint8_t u8IntCond);
en_result_t RTC_LowPowerCheck(void);
void RTC_SetClkCompenValue(uint16_t u16CompenVal);
void RTC_Cmd(en_functional_state_t enNewSta);
void RTC_LrcCmd(en_functional_state_t enNewSta);
en_functional_state_t RTC_GetCounterState(void);
void RTC_OneHzOutputCmd(en_functional_state_t enNewSta);
void RTC_ClkCompenCmd(en_functional_state_t enNewSta);
/* Date and time functions */
en_result_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate);
en_result_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate);
en_result_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime);
en_result_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime);
/* Alarm configuration functions */
en_result_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm);
en_result_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm);
void RTC_AlarmCmd(en_functional_state_t enNewSta);
/* Intrusion timestamp functions */
en_result_t RTC_IntrusionConfig(uint8_t u8Ch, const stc_rtc_intrusion_t *pstcIntru);
en_result_t RTC_GetIntrusionTimestamp(uint8_t u8Format, stc_rtc_timestamp_t *pstcTimestamp);
void RTC_IntrusionCmd(uint8_t u8Ch, en_functional_state_t enNewSta);
/* Interrupt and flag management functions */
void RTC_IntCmd(uint32_t u32IntSrc, en_functional_state_t enNewSta);
en_flag_status_t RTC_GetStatus(uint32_t u32Flag);
void RTC_ClearStatus(uint32_t u32Flag);
/**
* @}
*/
#endif /* DDL_RTC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_RTC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_sdioc.h
* @brief This file contains all the functions prototypes of the SDIOC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_SDIOC_H__
#define __HC32F4A0_SDIOC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_SDIOC
* @{
*/
#if (DDL_SDIOC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup SDIOC_Global_Types SDIOC Global Types
* @{
*/
/**
* @brief SDIOC Init structure definition
*/
typedef struct
{
uint32_t u32Mode; /*!< Specifies the SDIOC work mode.
This parameter can be a value of @ref SDIOC_Mode */
uint8_t u8CardDetectSelect; /*!< Specifies the SDIOC card detect source select.
This parameter can be a value of @ref SDIOC_Card_Detect_Select */
uint8_t u8SpeedMode; /*!< Specifies the SDIOC speed mode.
This parameter can be a value of @ref SDIOC_Speed_Mode */
uint8_t u8BusWidth; /*!< Specifies the SDIOC bus width.
This parameter can be a value of @ref SDIOC_Bus_Width */
uint16_t u16ClockDiv; /*!< Specifies the SDIOC clock division.
This parameter can be a value of @ref SDIOC_Clock_Division */
} stc_sdioc_init_t;
/**
* @brief SDIOC Command Init structure definition
*/
typedef struct
{
uint32_t u32Argument; /*!< Specifies the SDIOC command argument. */
uint16_t u16CmdIndex; /*!< Specifies the SDIOC command index.
This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
uint16_t u16CmdType; /*!< Specifies the SDIOC command type.
This parameter can be a value of @ref SDIOC_Command_Type */
uint16_t u16DataLineEn; /*!< Specifies whether SDIOC uses data lines in current command.
This parameter can be a value of @ref SDIOC_Data_Line_Valid */
uint16_t u16RespType; /*!< Specifies the SDIOC response type.
This parameter can be a value of @ref SDIOC_Response_Type */
} stc_sdioc_cmd_init_t;
/**
* @brief SDIOC Data Init structure definition
*/
typedef struct
{
uint16_t u16BlockSize; /*!< Specifies the SDIOC data block size.
This parameter must be a number between Min_Data = 1 and Max_Data = 512 */
uint16_t u16BlockCount; /*!< Specifies the SDIOC data block count.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF */
uint16_t u16TransferDir; /*!< Specifies the SDIOC data transfer direction.
This parameter can be a value of @ref SDIOC_Transfer_Direction */
uint16_t u16AutoCMD12En; /*!< Specifies the validity of the SDIOC Auto Send CMD12.
This parameter can be a value of @ref SDIOC_Auto_Send_CMD12 */
uint16_t u16TransferMode; /*!< Specifies the SDIOC data transfer mode.
This parameter can be a value of @ref SDIOC_Transfer_Mode */
uint8_t u16DataTimeout; /*!< Specifies the SDIOC data timeout time.
This parameter can be a value of @ref SDIOC_Data_Timeout_Time */
} stc_sdioc_data_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup SDIOC_Global_Macros SDIOC Global Macros
* @{
*/
/**
* @defgroup SDIOC_Mode SDIOC Mode
* @{
*/
#define SDIOC_MODE_SD (0x00UL) /*!< SDIOCx selects SD mode */
#define SDIOC_MODE_MMC (0x01UL) /*!< SDIOCx selects MMC mode */
/**
* @}
*/
/**
* @defgroup SDIOC_Card_Detect_Select SDIOC Card Detect Select
* @{
*/
#define SDIOC_CARD_DETECT_CD_PIN_LEVEL (0x00U) /*!< SDIOCx_CD(x=1~2) line is selected (for normal use) */
#define SDIOC_CARD_DETECT_TEST_SIGNAL (SDIOC_HOSTCON_CDSS) /*!< The Card Detect Test Level is selected(for test purpose) */
/**
* @}
*/
/**
* @defgroup SDIOC_Card_Detect_Test_Level SDIOC Card Detect Test Level
* @{
*/
#define SDIOC_CARD_DETECT_TEST_LEVEL_LOW (0x00U) /*!< Card identification test signal is low level (with device insertion) */
#define SDIOC_CARD_DETECT_TEST_LEVEL_HIGH (SDIOC_HOSTCON_CDTL) /*!< Card identification test signal is high level (no device insertion) */
/**
* @}
*/
/**
* @defgroup SDIOC_Speed_Mode SDIOC Speed Mode
* @{
*/
#define SDIOC_SPEED_MODE_NORMAL (0x00U) /*!< Normal speed mode */
#define SDIOC_SPEED_MODE_HIGH (SDIOC_HOSTCON_HSEN) /*!< High speed mode */
/**
* @}
*/
/**
* @defgroup SDIOC_Bus_Width SDIOC Bus Width
* @{
*/
#define SDIOC_BUS_WIDTH_1BIT (0x00U) /*!< The Bus width is 1 bit */
#define SDIOC_BUS_WIDTH_4BIT (SDIOC_HOSTCON_DW) /*!< The Bus width is 4 bit */
#define SDIOC_BUS_WIDTH_8BIT (SDIOC_HOSTCON_EXDW) /*!< The Bus width is 8 bit */
/**
* @}
*/
/**
* @defgroup SDIOC_Clock_Division SDIOC Clock Division
* @{
*/
#define SDIOC_CLOCK_DIV_1 (0x00U) /*!< PCLK1/1 */
#define SDIOC_CLOCK_DIV_2 (SDIOC_CLKCON_FS_0) /*!< PCLK1/2 */
#define SDIOC_CLOCK_DIV_4 (SDIOC_CLKCON_FS_1) /*!< PCLK1/4 */
#define SDIOC_CLOCK_DIV_8 (SDIOC_CLKCON_FS_2) /*!< PCLK1/8 */
#define SDIOC_CLOCK_DIV_16 (SDIOC_CLKCON_FS_3) /*!< PCLK1/16 */
#define SDIOC_CLOCK_DIV_32 (SDIOC_CLKCON_FS_4) /*!< PCLK1/32 */
#define SDIOC_CLOCK_DIV_64 (SDIOC_CLKCON_FS_5) /*!< PCLK1/64 */
#define SDIOC_CLOCK_DIV_128 (SDIOC_CLKCON_FS_6) /*!< PCLK1/128 */
#define SDIOC_CLOCK_DIV_256 (SDIOC_CLKCON_FS_7) /*!< PCLK1/256 */
/**
* @}
*/
/**
* @defgroup SDIOC_Command_Type SDIOC Command Type
* @{
*/
#define SDIOC_CMD_TYPE_NORMAL (0x00U) /*!< Other commands */
#define SDIOC_CMD_TYPE_SUSPEND (SDIOC_CMD_TYP_0) /*!< CMD52 for writing "Bus Suspend" in CCCR */
#define SDIOC_CMD_TYPE_RESUME (SDIOC_CMD_TYP_1) /*!< CMD52 for writing "Function Select" in CCCR */
#define SDIOC_CMD_TYPE_ABORT (SDIOC_CMD_TYP) /*!< CMD12, CMD52 for writing "I/O Abort" in CCCR */
/**
* @}
*/
/**
* @defgroup SDIOC_Data_Line_Valid SDIOC Data Line Valid
* @{
*/
#define SDIOC_DATA_LINE_DISABLE (0x00U) /*!< The current command uses only SDIOCx_CMD(x=1~2) command line */
#define SDIOC_DATA_LINE_ENABLE (SDIOC_CMD_DAT) /*!< The current command requires the use of SDIOCx_Dy(x=1~2) data line */
/**
* @}
*/
/**
* @defgroup SDIOC_Transfer_Direction SDIOC Transfer Direction
* @{
*/
#define SDIOC_TRANSFER_DIR_TO_CARD (0x00U) /*!< Write (Host to Card) */
#define SDIOC_TRANSFER_DIR_TO_HOST (SDIOC_TRANSMODE_DDIR) /*!< Read (Card to Host) */
/**
* @}
*/
/**
* @defgroup SDIOC_Auto_Send_CMD12 SDIOC Auto Send CMD12
* @{
*/
#define SDIOC_AUTO_SEND_CMD12_DISABLE (0x00U) /*!< Do not send autocommands */
#define SDIOC_AUTO_SEND_CMD12_ENABLE (SDIOC_TRANSMODE_ATCEN_0) /*!< CMD12 is automatically sent after multiple block transfers */
/**
* @}
*/
/**
* @defgroup SDIOC_Transfer_Mode SDIOC Transfer Mode
* @{
*/
#define SDIOC_TRANSFER_MODE_SINGLE (0x00U) /*!< Single Block transfer */
#define SDIOC_TRANSFER_MODE_INFINITE (SDIOC_TRANSMODE_MULB) /*!< Infinite Block transfer */
#define SDIOC_TRANSFER_MODE_MULTIPLE (SDIOC_TRANSMODE_MULB | SDIOC_TRANSMODE_BCE) /*!< Multiple Block transfer */
#define SDIOC_TRANSFER_MODE_STOP_MULTIPLE (0x8000U | SDIOC_TRANSFER_MODE_MULTIPLE) /*!< Stop Multiple Block transfer */
/**
* @}
*/
/**
* @defgroup SDIOC_Data_Timeout_Time SDIOC Data Timeout Time
* @{
*/
#define SDIOC_DATA_TIMEOUT_CLK_2_13 (0x00U) /*!< Timeout time: PCLK1*2^13 */
#define SDIOC_DATA_TIMEOUT_CLK_2_14 (0x01U) /*!< Timeout time: PCLK1*2^14 */
#define SDIOC_DATA_TIMEOUT_CLK_2_15 (0x02U) /*!< Timeout time: PCLK1*2^15 */
#define SDIOC_DATA_TIMEOUT_CLK_2_16 (0x03U) /*!< Timeout time: PCLK1*2^16 */
#define SDIOC_DATA_TIMEOUT_CLK_2_17 (0x04U) /*!< Timeout time: PCLK1*2^17 */
#define SDIOC_DATA_TIMEOUT_CLK_2_18 (0x05U) /*!< Timeout time: PCLK1*2^18 */
#define SDIOC_DATA_TIMEOUT_CLK_2_19 (0x06U) /*!< Timeout time: PCLK1*2^19 */
#define SDIOC_DATA_TIMEOUT_CLK_2_20 (0x07U) /*!< Timeout time: PCLK1*2^20 */
#define SDIOC_DATA_TIMEOUT_CLK_2_21 (0x08U) /*!< Timeout time: PCLK1*2^21 */
#define SDIOC_DATA_TIMEOUT_CLK_2_22 (0x09U) /*!< Timeout time: PCLK1*2^22 */
#define SDIOC_DATA_TIMEOUT_CLK_2_23 (0x0AU) /*!< Timeout time: PCLK1*2^23 */
#define SDIOC_DATA_TIMEOUT_CLK_2_24 (0x0BU) /*!< Timeout time: PCLK1*2^24 */
#define SDIOC_DATA_TIMEOUT_CLK_2_25 (0x0CU) /*!< Timeout time: PCLK1*2^25 */
#define SDIOC_DATA_TIMEOUT_CLK_2_26 (0x0DU) /*!< Timeout time: PCLK1*2^26 */
#define SDIOC_DATA_TIMEOUT_CLK_2_27 (0x0EU) /*!< Timeout time: PCLK1*2^27 */
/**
* @}
*/
/**
* @defgroup SDIOC_Response_Register SDIOC Response Register
* @{
*/
#define SDIOC_RESPONSE_REG_BIT0_31 (0x00U) /*!< Command Response Register 0-31bit */
#define SDIOC_RESPONSE_REG_BIT32_63 (0x04U) /*!< Command Response Register 32-63bit */
#define SDIOC_RESPONSE_REG_BIT64_95 (0x08U) /*!< Command Response Register 64-95bit */
#define SDIOC_RESPONSE_REG_BIT96_127 (0x0CU) /*!< Command Response Register 96-127bit */
/**
* @}
*/
/**
* @defgroup SDIOC_Software_Reset_Type SDIOC_Software_Reset_Type
* @{
*/
#define SDIOC_SW_RESET_DATA_LINE (SDIOC_SFTRST_RSTD) /*!< Only part of data circuit is reset */
#define SDIOC_SW_RESET_CMD_LINE (SDIOC_SFTRST_RSTC) /*!< Only part of command circuit is reset */
#define SDIOC_SW_RESET_ALL (SDIOC_SFTRST_RSTA) /*!< Reset the entire Host Controller except for the card detection circuit */
/**
* @}
*/
/**
* @defgroup SDIOC_Output_Clock_Frequency SDIOC Output Clock Frequency
* @{
*/
#define SDIOC_OUTPUT_CLK_FREQ_400K (400000UL) /*!< SDIOC clock: 400KHz */
#define SDIOC_OUTPUT_CLK_FREQ_25M (25000000UL) /*!< SDIOC clock: 25MHz */
#define SDIOC_OUTPUT_CLK_FREQ_26M (26000000UL) /*!< SDIOC clock: 26MHz */
#define SDIOC_OUTPUT_CLK_FREQ_50M (50000000UL) /*!< SDIOC clock: 50MHz */
#define SDIOC_OUTPUT_CLK_FREQ_52M (52000000UL) /*!< SDIOC clock: 52MHz */
/**
* @}
*/
/**
* @defgroup SDIOC_Host_Status SDIOC Host Status
* @{
*/
#define SDIOC_HOST_FLAG_CMDL (SDIOC_PSTAT_CMDL) /*!< CMD Line Level status */
#define SDIOC_HOST_FLAG_DATL (SDIOC_PSTAT_DATL) /*!< DAT[3:0] Line Level status */
#define SDIOC_HOST_FLAG_DATL_D0 (SDIOC_PSTAT_DATL_0) /*!< DAT[0] Line Level status */
#define SDIOC_HOST_FLAG_DATL_D1 (SDIOC_PSTAT_DATL_1) /*!< DAT[1] Line Level status */
#define SDIOC_HOST_FLAG_DATL_D2 (SDIOC_PSTAT_DATL_2) /*!< DAT[2] Line Level status */
#define SDIOC_HOST_FLAG_DATL_D3 (SDIOC_PSTAT_DATL_3) /*!< DAT[3] Line Level status */
#define SDIOC_HOST_FLAG_WPL (SDIOC_PSTAT_WPL) /*!< Write Protect Line Level status */
#define SDIOC_HOST_FLAG_CDL (SDIOC_PSTAT_CDL) /*!< Card Detect Line Level status */
#define SDIOC_HOST_FLAG_CSS (SDIOC_PSTAT_CSS) /*!< Device Stable Status */
#define SDIOC_HOST_FLAG_CIN (SDIOC_PSTAT_CIN) /*!< Device Inserted status */
#define SDIOC_HOST_FLAG_BRE (SDIOC_PSTAT_BRE) /*!< Data buffer full status */
#define SDIOC_HOST_FLAG_BWE (SDIOC_PSTAT_BWE) /*!< Data buffer empty status */
#define SDIOC_HOST_FLAG_RTA (SDIOC_PSTAT_RTA) /*!< Read operation status */
#define SDIOC_HOST_FLAG_WTA (SDIOC_PSTAT_WTA) /*!< Write operation status */
#define SDIOC_HOST_FLAG_DA (SDIOC_PSTAT_DA) /*!< DAT Line transfer status */
#define SDIOC_HOST_FLAG_CID (SDIOC_PSTAT_CID) /*!< Command Inhibit with data status */
#define SDIOC_HOST_FLAG_CIC (SDIOC_PSTAT_CIC) /*!< Command Inhibit status */
/**
* @}
*/
/**
* @defgroup SDIOC_Normal_Error_Interrupt_Status SDIOC Normal Error Interrupt Status
* @{
*/
#define SDIOC_NORMAL_INT_FLAG_EI (SDIOC_NORINTST_EI) /*!< Error Interrupt Status */
#define SDIOC_NORMAL_INT_FLAG_CINT (SDIOC_NORINTST_CINT) /*!< Card Interrupt status */
#define SDIOC_NORMAL_INT_FLAG_CRM (SDIOC_NORINTST_CRM) /*!< Card Removal status */
#define SDIOC_NORMAL_INT_FLAG_CIST (SDIOC_NORINTST_CIST) /*!< Card Insertion status */
#define SDIOC_NORMAL_INT_FLAG_BRR (SDIOC_NORINTST_BRR) /*!< Buffer Read Ready status */
#define SDIOC_NORMAL_INT_FLAG_BWR (SDIOC_NORINTST_BWR) /*!< Buffer Write Ready status */
#define SDIOC_NORMAL_INT_FLAG_BGE (SDIOC_NORINTST_BGE) /*!< Block Gap Event status */
#define SDIOC_NORMAL_INT_FLAG_TC (SDIOC_NORINTST_TC) /*!< Transfer Complete status */
#define SDIOC_NORMAL_INT_FLAG_CC (SDIOC_NORINTST_CC) /*!< Command Complete status */
#define SDIOC_ERROR_INT_FLAG_ACE ((uint32_t)SDIOC_ERRINTST_ACE << 16U) /*!< Auto CMD12 Error Status */
#define SDIOC_ERROR_INT_FLAG_DEBE ((uint32_t)SDIOC_ERRINTST_DEBE << 16U) /*!< Data End Bit Error status */
#define SDIOC_ERROR_INT_FLAG_DCE ((uint32_t)SDIOC_ERRINTST_DCE << 16U) /*!< Data CRC Error status */
#define SDIOC_ERROR_INT_FLAG_DTOE ((uint32_t)SDIOC_ERRINTST_DTOE << 16U) /*!< Data Timeout Error status */
#define SDIOC_ERROR_INT_FLAG_CIE ((uint32_t)SDIOC_ERRINTST_CIE << 16U) /*!< Command Index Error status */
#define SDIOC_ERROR_INT_FLAG_CEBE ((uint32_t)SDIOC_ERRINTST_CEBE << 16U) /*!< Command End Bit Error status */
#define SDIOC_ERROR_INT_FLAG_CCE ((uint32_t)SDIOC_ERRINTST_CCE << 16U) /*!< Command CRC Error status */
#define SDIOC_ERROR_INT_FLAG_CTOE ((uint32_t)SDIOC_ERRINTST_CTOE << 16U) /*!< Command Timeout Error status */
#define SDIOC_ERROR_INT_STATIC_FLAGS ((uint32_t)SDIOC_ERROR_INT_FLAG_ACE | SDIOC_ERROR_INT_FLAG_DEBE | \
SDIOC_ERROR_INT_FLAG_DCE | SDIOC_ERROR_INT_FLAG_DTOE | \
SDIOC_ERROR_INT_FLAG_CIE | SDIOC_ERROR_INT_FLAG_CEBE | \
SDIOC_ERROR_INT_FLAG_CCE | SDIOC_ERROR_INT_FLAG_CTOE | \
SDIOC_NORMAL_INT_FLAG_TC | SDIOC_NORMAL_INT_FLAG_CC)
/**
* @}
*/
/**
* @defgroup SDIOC_Normal_Error_Interrupt SDIOC Normal Error Interrupt
* @{
*/
#define SDIOC_NORMAL_INT_CINTSEN (SDIOC_NORINTSGEN_CINTSEN) /*!< Card Interrupt */
#define SDIOC_NORMAL_INT_CRMSEN (SDIOC_NORINTSGEN_CRMSEN) /*!< Card Removal Interrupt */
#define SDIOC_NORMAL_INT_CISTSEN (SDIOC_NORINTSGEN_CISTSEN) /*!< Card Insertion Interrupt */
#define SDIOC_NORMAL_INT_BRRSEN (SDIOC_NORINTSGEN_BRRSEN) /*!< Buffer Read Ready Interrupt */
#define SDIOC_NORMAL_INT_BWRSEN (SDIOC_NORINTSGEN_BWRSEN) /*!< Buffer Write Ready Interrupt */
#define SDIOC_NORMAL_INT_BGESEN (SDIOC_NORINTSGEN_BGESEN) /*!< Block Gap Event Interrupt */
#define SDIOC_NORMAL_INT_TCSEN (SDIOC_NORINTSGEN_TCSEN) /*!< Transfer Complete Interrupt */
#define SDIOC_NORMAL_INT_CCSEN (SDIOC_NORINTSGEN_CCSEN) /*!< Command Complete Interrupt */
#define SDIOC_ERROR_INT_ACESEN ((uint32_t)SDIOC_ERRINTSGEN_ACESEN << 16U) /*!< Auto CMD12 Error Interrupt */
#define SDIOC_ERROR_INT_DEBESEN ((uint32_t)SDIOC_ERRINTSGEN_DEBESEN << 16U) /*!< Data End Bit Error Interrupt */
#define SDIOC_ERROR_INT_DCESEN ((uint32_t)SDIOC_ERRINTSGEN_DCESEN << 16U) /*!< Data CRC Error Interrupt */
#define SDIOC_ERROR_INT_DTOESEN ((uint32_t)SDIOC_ERRINTSGEN_DTOESEN << 16U) /*!< Data Timeout Error Interrupt */
#define SDIOC_ERROR_INT_CIESEN ((uint32_t)SDIOC_ERRINTSGEN_CIESEN << 16U) /*!< Command Index Error Interrupt */
#define SDIOC_ERROR_INT_CEBESEN ((uint32_t)SDIOC_ERRINTSGEN_CEBESEN << 16U) /*!< Command End Bit Error Interrupt */
#define SDIOC_ERROR_INT_CCESEN ((uint32_t)SDIOC_ERRINTSGEN_CCESEN << 16U) /*!< Command CRC Error Interrupt */
#define SDIOC_ERROR_INT_CTOESEN ((uint32_t)SDIOC_ERRINTSGEN_CTOESEN << 16U) /*!< Command Timeout Error Interrupt */
/**
* @}
*/
/**
* @defgroup SDIOC_Auto_CMD_Error_Status SDIOC Auto CMD Error Status
* @{
*/
#define SDIOC_AUTO_CMD_ERROR_FLAG_CMDE (SDIOC_ATCERRST_CMDE) /*!< Command Not Issued By Auto CMD12 Error Status */
#define SDIOC_AUTO_CMD_ERROR_FLAG_IE (SDIOC_ATCERRST_IE) /*!< Auto CMD12 Index Error status */
#define SDIOC_AUTO_CMD_ERROR_FLAG_EBE (SDIOC_ATCERRST_EBE) /*!< Auto CMD12 End Bit Error status */
#define SDIOC_AUTO_CMD_ERROR_FLAG_CE (SDIOC_ATCERRST_CE) /*!< Auto CMD12 CRC Error status */
#define SDIOC_AUTO_CMD_ERROR_FLAG_TOE (SDIOC_ATCERRST_TOE) /*!< Auto CMD12 Timeout Error status */
#define SDIOC_AUTO_CMD_ERROR_FLAG_NE (SDIOC_ATCERRST_NE) /*!< Auto CMD12 Not Executed status */
/**
* @}
*/
/**
* @defgroup SDIOC_Force_Auto_CMD_Error SDIOC Force Auto CMD Error
* @{
*/
#define SDIOC_FORCE_AUTO_CMD_ERROR_FCMDE (SDIOC_FEA_FCMDE) /*!< Force Event for Command Not Issued By Auto CMD12 Error */
#define SDIOC_FORCE_AUTO_CMD_ERROR_FIE (SDIOC_FEA_FIE) /*!< Force Event for Auto CMD12 Index Error */
#define SDIOC_FORCE_AUTO_CMD_ERROR_FEBE (SDIOC_FEA_FEBE) /*!< Force Event for Auto CMD12 End Bit Error */
#define SDIOC_FORCE_AUTO_CMD_ERROR_FCE (SDIOC_FEA_FCE) /*!< Force Event for Auto CMD12 CRC Error */
#define SDIOC_FORCE_AUTO_CMD_ERROR_FTOE (SDIOC_FEA_FTOE) /*!< Force Event for Auto CMD12 Timeout Error */
#define SDIOC_FORCE_AUTO_CMD_ERROR_FNE (SDIOC_FEA_FNE) /*!< Force Event for Auto CMD12 Not Executed */
/**
* @}
*/
/**
* @defgroup SDIOC_Force_Error_Interrupt SDIOC Force Error Interrupt
* @{
*/
#define SDIOC_FORCE_ERROR_INT_FACE (SDIOC_FEE_FACE) /*!< Force Event for Auto CMD12 Error */
#define SDIOC_FORCE_ERROR_INT_FDEBE (SDIOC_FEE_FDEBE) /*!< Force Event for Data End Bit Error */
#define SDIOC_FORCE_ERROR_INT_FDCE (SDIOC_FEE_FDCE) /*!< Force Event for Data CRC Error */
#define SDIOC_FORCE_ERROR_INT_FDTOE (SDIOC_FEE_FDTOE) /*!< Force Event for Data Timeout Error */
#define SDIOC_FORCE_ERROR_INT_FCIE (SDIOC_FEE_FCIE) /*!< Force Event for Command Index Error */
#define SDIOC_FORCE_ERROR_INT_FCEBE (SDIOC_FEE_FCEBE) /*!< Force Event for Command End Bit Error */
#define SDIOC_FORCE_ERROR_INT_FCCE (SDIOC_FEE_FCCE) /*!< Force Event for Command CRC Error */
#define SDIOC_FORCE_ERROR_INT_FCTOE (SDIOC_FEE_FCTOE) /*!< Force Event for Command Timeout Error */
/**
* @}
*/
/**
* @defgroup SDIOC_Response_Type SDIOC Response Type
* @{
*/
#define SDIOC_RESOPNE_TYPE_NO (0x00U) /*!< No Response */
#define SDIOC_RESOPNE_TYPE_R2 (SDIOC_CMD_RESTYP_0 | SDIOC_CMD_CCE) /*!< Command Response 2 */
#define SDIOC_RESOPNE_TYPE_R3_R4 (SDIOC_CMD_RESTYP_1) /*!< Command Response 3, 4 */
#define SDIOC_RESOPNE_TYPE_R1_R5_R6_R7 (SDIOC_CMD_RESTYP_1 | SDIOC_CMD_ICE | SDIOC_CMD_CCE) /*!< Command Response 1, 5, 6, 7 */
#define SDIOC_RESOPNE_TYPE_R1B_R5B (SDIOC_CMD_RESTYP | SDIOC_CMD_ICE | SDIOC_CMD_CCE) /*!< Command Response 1 and 5 with busy */
/**
* @}
*/
/**
* @defgroup SDIOC_Commands_Index SDIOC Commands Index
* @{
*/
#define SDIOC_CMD0_GO_IDLE_STATE (0U) /*!< Resets the SD memory card. */
#define SDIOC_CMD1_SEND_OP_COND (1U) /*!< Sends host capacity support information and activates the card's initialization process. */
#define SDIOC_CMD2_ALL_SEND_CID (2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
#define SDIOC_CMD3_SEND_RELATIVE_ADDR (3U) /*!< Asks the card to publish a new relative address (RCA). */
#define SDIOC_CMD4_SET_DSR (4U) /*!< Programs the DSR of all cards. */
#define SDIOC_CMD5_IO_SEND_OP_COND (5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its \
operating condition register (OCR) content in the response on the CMD line. */
#define SDIOC_CMD6_SWITCH_FUNC (6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
#define SDIOC_CMD7_SELECT_DESELECT_CARD (7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
#define SDIOC_CMD8_SEND_IF_COND (8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information \
and asks the card whether card supports voltage. */
#define SDIOC_CMD9_SEND_CSD (9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
#define SDIOC_CMD10_SEND_CID (10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
#define SDIOC_CMD11_READ_DAT_UNTIL_STOP (11U) /*!< SD card doesn't support it. */
#define SDIOC_CMD12_STOP_TRANSMISSION (12U) /*!< Forces the card to stop transmission. */
#define SDIOC_CMD13_SEND_STATUS (13U) /*!< Addressed card sends its status register. */
#define SDIOC_CMD14_HS_BUSTEST_READ (14U) /*!< Reserved */
#define SDIOC_CMD15_GO_INACTIVE_STATE (15U) /*!< Sends an addressed card into the inactive state. */
#define SDIOC_CMD16_SET_BLOCKLEN (16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands(read, write). \
Default block length is fixed to 512 Bytes. Not effective for SDHS and SDXC. */
#define SDIOC_CMD17_READ_SINGLE_BLOCK (17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed \
512 bytes in case of SDHC and SDXC. */
#define SDIOC_CMD18_READ_MULTIPLE_BLOCK (18U) /*!< Continuously transfers data blocks from card to host until interrupted by \
STOP_TRANSMISSION command. */
#define SDIOC_CMD19_HS_BUSTEST_WRITE (19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
#define SDIOC_CMD20_WRITE_DAT_UNTIL_STOP (20U) /*!< Speed class control command. */
#define SDIOC_CMD23_SET_BLOCK_COUNT (23U) /*!< Specify block count for CMD18 and CMD25. */
#define SDIOC_CMD24_WRITE_SINGLE_BLOCK (24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed\
512 bytes in case of SDHC and SDXC. */
#define SDIOC_CMD25_WRITE_MULTIPLE_BLOCK (25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
#define SDIOC_CMD26_PROGRAM_CID (26U) /*!< Reserved for manufacturers. */
#define SDIOC_CMD27_PROGRAM_CSD (27U) /*!< Programming of the programmable bits of the CSD. */
#define SDIOC_CMD28_SET_WRITE_PROT (28U) /*!< Sets the write protection bit of the addressed group. */
#define SDIOC_CMD29_CLR_WRITE_PROT (29U) /*!< Clears the write protection bit of the addressed group. */
#define SDIOC_CMD30_SEND_WRITE_PROT (30U) /*!< Asks the card to send the status of the write protection bits. */
#define SDIOC_CMD32_ERASE_WR_BLK_START (32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
#define SDIOC_CMD33_ERASE_WR_BLK_END (33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
#define SDIOC_CMD35_ERASE_GRP_START (35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system \
set by switch function command (CMD6). */
#define SDIOC_CMD36_ERASE_GRP_END (36U) /*!< Sets the address of the last write block of the continuous range to be erased. \
Reserved for each command system set by switch function command (CMD6). */
#define SDIOC_CMD38_ERASE (38U) /*!< Reserved for SD security applications. */
#define SDIOC_CMD39_FAST_IO (39U) /*!< SD card doesn't support it (Reserved). */
#define SDIOC_CMD40_GO_IRQ_STATE (40U) /*!< SD card doesn't support it (Reserved). */
#define SDIOC_CMD42_LOCK_UNLOCK (42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by \
the SET_BLOCK_LEN command. */
#define SDIOC_CMD55_APP_CMD (55U) /*!< Indicates to the card that the next command is an application specific command rather \
than a standard command. */
#define SDIOC_CMD56_GEN_CMD (56U) /*!< Used either to transfer a data block to the card or to get a data block from the card \
for general purpose/application specific commands. */
#define SDIOC_CMD64_NO_CMD (64U) /*!< No command */
/**
* @brief Following commands are SD Card Specific commands.
* CMD55_APP_CMD should be sent before sending these commands.
*/
#define SDIOC_ACMD6_SET_BUS_WIDTH (6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus \
widths are given in SCR register. */
#define SDIOC_ACMD13_SD_STATUS (13U) /*!< (ACMD13) Sends the SD status. */
#define SDIOC_ACMD22_SEND_NUM_WR_BLOCKS (22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with \
32bit+CRC data block. */
#define SDIOC_ACMD41_SD_APP_OP_COND (41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to \
send its operating condition register (OCR) content in the response on the CMD line. */
#define SDIOC_ACMD42_SET_CLR_CARD_DETECT (42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
#define SDIOC_ACMD51_SEND_SCR (51U) /*!< Reads the SD Configuration Register (SCR). */
#define SDIOC_ACMD52_RW_DIRECT (52U) /*!< For SD I/O card only, reserved for security specification. */
#define SDIOC_ACMD53_RW_EXTENDED (53U) /*!< For SD I/O card only, reserved for security specification. */
/**
* @brief Following commands are SD Card Specific security commands.
* CMD55_APP_CMD should be sent before sending these commands.
*/
#define SDIOC_ACMD43_GET_MKB (43U)
#define SDIOC_ACMD44_GET_MID (44U)
#define SDIOC_ACMD45_SET_CER_RN1 (45U)
#define SDIOC_ACMD46_GET_CER_RN2 (46U)
#define SDIOC_ACMD47_SET_CER_RES2 (47U)
#define SDIOC_ACMD48_GET_CER_RES1 (48U)
#define SDIOC_ACMD18_SECURE_READ_MULTIPLE_BLOCK (18U)
#define SDIOC_ACMD25_SECURE_WRITE_MULTIPLE_BLOCK (25U)
#define SDIOC_ACMD38_SECURE_ERASE (38U)
#define SDIOC_ACMD49_CHANGE_SECURE_AREA (49U)
#define SDIOC_ACMD48_SECURE_WRITE_MKB (48U)
/**
* @}
*/
/**
* @defgroup SDMMC_Error_Code SDMMC Error Code
* @{
*/
#define SDMMC_ERROR_NONE (0x00000000UL) /*!< No error */
#define SDMMC_ERROR_ADDR_OUT_OF_RANGE (0x80000000UL) /*!< Error when addressed block is out of range */
#define SDMMC_ERROR_ADDR_MISALIGNED (0x40000000UL) /*!< Misaligned address */
#define SDMMC_ERROR_BLOCK_LEN_ERR (0x20000000UL) /*!< Transferred block length is not allowed for the card or the \
number of transferred bytes does not match the block length */
#define SDMMC_ERROR_ERASE_SEQ_ERR (0x10000000UL) /*!< An error in the sequence of erase command occurs */
#define SDMMC_ERROR_BAD_ERASE_PARAM (0x08000000UL) /*!< An invalid selection for erase groups */
#define SDMMC_ERROR_WRITE_PROT_VIOLATION (0x04000000UL) /*!< Attempt to program a write protect block */
#define SDMMC_ERROR_LOCK_UNLOCK_FAILED (0x01000000UL) /*!< Sequence or password error has been detected in unlock command \
or if there was an attempt to access a locked card */
#define SDMMC_ERROR_COM_CRC_FAILED (0x00800000UL) /*!< CRC check of the previous command failed */
#define SDMMC_ERROR_ILLEGAL_CMD (0x00400000UL) /*!< Command is not legal for the card state */
#define SDMMC_ERROR_CARD_ECC_FAILED (0x00200000UL) /*!< Card internal ECC was applied but failed to correct the data */
#define SDMMC_ERROR_CC_ERR (0x00100000UL) /*!< Internal card controller error */
#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR (0x00080000UL) /*!< General or unknown error */
#define SDMMC_ERROR_STREAM_READ_UNDERRUN (0x00040000UL) /*!< The card could not sustain data reading in stream rmode */
#define SDMMC_ERROR_STREAM_WRITE_OVERRUN (0x00020000UL) /*!< The card could not sustain data programming in stream mode */
#define SDMMC_ERROR_CID_CSD_OVERWRITE (0x00010000UL) /*!< CID/CSD overwrite error */
#define SDMMC_ERROR_WP_ERASE_SKIP (0x00008000UL) /*!< Only partial address space was erased */
#define SDMMC_ERROR_CARD_ECC_DISABLED (0x00004000UL) /*!< Command has been executed without using internal ECC */
#define SDMMC_ERROR_ERASE_RESET (0x00002000UL) /*!< Erase sequence was cleared before executing because an out of \
erase sequence command was received */
#define SDMMC_ERROR_CMD_AUTO_SEND (0x00001000UL) /*!< An error occurred in sending the command automatically */
#define SDMMC_ERROR_CMD_INDEX (0x00000800UL) /*!< The received response contains a command number error */
#define SDMMC_ERROR_CMD_STOP_BIT (0x00000400UL) /*!< Command line detects low level at stop bit */
#define SDMMC_ERROR_CMD_CRC_FAIL (0x00000200UL) /*!< Command response received (but CRC check failed) */
#define SDMMC_ERROR_CMD_TIMEOUT (0x00000100UL) /*!< Command response timeout */
#define SDMMC_ERROR_SWITCH_ERROR (0x00000080UL) /*!< The card did not switch to the expected mode as requested by \
the SWITCH command */
#define SDMMC_ERROR_DATA_STOP_BIT (0x00000040UL) /*!< Data line detects low level at stop bit */
#define SDMMC_ERROR_DATA_CRC_FAIL (0x00000020UL) /*!< Data block sent/received (CRC check failed) */
#define SDMMC_ERROR_DATA_TIMEOUT (0x00000010UL) /*!< Data timeout */
#define SDMMC_ERROR_AKE_SEQ_ERR (0x00000008UL) /*!< Error in sequence of authentication */
#define SDMMC_ERROR_INVALID_VOLTRANGE (0x00000004UL) /*!< Error in case of invalid voltage range */
#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE (0x00000002UL) /*!< Error when command request is not applicable */
#define SDMMC_ERROR_UNSUPPORTED_FEATURE (0x00000001UL) /*!< Error when feature is not insupported */
#define SDMMC_CARD_ERROR_BITS_MASK (0xFDFFE048UL) /*!< SD/MMC Error status bits mask */
/**
* @}
*/
/**
* @defgroup SDMMC_Card_Status_Bit SDMMC Card Status Bit
* @{
*/
#define SDMMC_STATUS_CARD_IS_LOCKED_POS (24U)
#define SDMMC_STATUS_CARD_IS_LOCKED (0x02000000UL) /*!< When set, signals that the card is locked by the host */
#define SDMMC_STATUS_CURRENT_STATE_POS (9U)
#define SDMMC_STATUS_CURRENT_STATE (0x00001E00UL) /*!< The state of the card when receiving the command */
#define SDMMC_STATUS_READY_FOR_DATA_POS (8U)
#define SDMMC_STATUS_READY_FOR_DATA (0x00000100UL) /*!< Corresponds to buffer empty signaling on the bus */
#define SDMMC_STATUS_APP_CMD_POS (5U)
#define SDMMC_STATUS_APP_CMD (0x00000020UL) /*!< The card will expect ACMD, or an indication that the command has been interpreted as ACMD */
/**
* @}
*/
/**
* @defgroup SDMMC_SCR_Register SDMMC SCR Register
* @{
*/
#define SDMMC_SCR_PHY_SPEC_VER_1P0 (0x00000000UL)
#define SDMMC_SCR_PHY_SPEC_VER_1P1 (0x01000000UL)
#define SDMMC_SCR_PHY_SPEC_VER_2P0 (0x02000000UL)
#define SDMMC_SCR_BUS_WIDTH_4BIT (0x00040000UL)
#define SDMMC_SCR_BUS_WIDTH_1BIT (0x00010000UL)
/**
* @}
*/
/**
* @defgroup SDMMC_OCR_Register SDMMC OCR Register
* @{
*/
#define SDMMC_OCR_HIGH_CAPACITY (0x40000000UL)
#define SDMMC_OCR_STD_CAPACITY (0x00000000UL)
/**
* @}
*/
/**
* @defgroup SDMMC_CSD_Register SDMMC CSD Register
* @{
*/
/* Command Class supported */
#define SDMMC_CSD_SUPPORT_CLASS5_ERASE (0x00000020UL)
/**
* @}
*/
/**
* @defgroup SDMMC_Common_Parameter SDMMC Common Parameter
* @{
*/
#define SDMMC_DATA_TIMEOUT (0x0000FFFFUL)
#define SDMMC_MAX_VOLTAGE_TRIAL (0x0000FFFFUL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup SDIOC_Global_Functions
* @{
*/
en_result_t SDIOC_DeInit(M4_SDIOC_TypeDef *SDIOCx);
en_result_t SDIOC_Init(M4_SDIOC_TypeDef *SDIOCx, const stc_sdioc_init_t *pstcSdiocInit);
en_result_t SDIOC_StructInit(stc_sdioc_init_t *pstcSdiocInit);
en_result_t SDIOC_SoftwareReset(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8ResetType);
void SDIOC_PowerCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta);
en_functional_state_t SDIOC_GetPowerState(const M4_SDIOC_TypeDef *SDIOCx);
uint32_t SDIOC_GetMode(const M4_SDIOC_TypeDef *SDIOCx);
void SDIOC_ClockCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta);
void SDIOC_SetClockDiv(M4_SDIOC_TypeDef *SDIOCx, uint16_t u16ClkDiv);
en_result_t SDIOC_GetOptimumClockDiv(uint32_t u32ClkFreq, uint16_t *pu16ClkDiv);
en_result_t SDIOC_VerifyClockDiv(uint32_t u32Mode, uint8_t u8SpeedMode, uint16_t u16ClkDiv);
en_functional_state_t SDIOC_GetDeviceInsertState(const M4_SDIOC_TypeDef *SDIOCx);
void SDIOC_SetSpeedMode(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8SpeedMode);
void SDIOC_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8BusWidth);
void SDIOC_SetCardDetectSource(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8Src);
void SDIOC_SetCardDetectTestLevel(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8Level);
en_result_t SDIOC_SendCommand(M4_SDIOC_TypeDef *SDIOCx, const stc_sdioc_cmd_init_t *pstcCmd);
en_result_t SDIOC_CmdStructInit(stc_sdioc_cmd_init_t *pstcCmd);
en_result_t SDIOC_GetResponse(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8RespReg, uint32_t *pu32RespVal);
en_result_t SDIOC_ConfigData(M4_SDIOC_TypeDef *SDIOCx, const stc_sdioc_data_init_t *pstcData);
en_result_t SDIOC_DataStructInit(stc_sdioc_data_init_t *pstcData);
en_result_t SDIOC_ReadBuffer(M4_SDIOC_TypeDef *SDIOCx, uint8_t au8Data[], uint32_t u32Len);
en_result_t SDIOC_WriteBuffer(M4_SDIOC_TypeDef *SDIOCx, const uint8_t au8Data[], uint32_t u32Len);
void SDIOC_BlockGapStopCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta);
void SDIOC_RestartTransfer(M4_SDIOC_TypeDef *SDIOCx);
void SDIOC_ReadWaitCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta);
void SDIOC_BlockGapInterruptCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta);
void SDIOC_IntCmd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32IntSrc, en_functional_state_t enNewSta);
en_functional_state_t SDIOC_GetIntEnableState(const M4_SDIOC_TypeDef *SDIOCx, uint32_t u32IntSrc);
en_flag_status_t SDIOC_GetIntStatus(const M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag);
void SDIOC_ClearIntStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag);
void SDIOC_IntStatusCmd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32IntSrc, en_functional_state_t enNewSta);
en_flag_status_t SDIOC_GetHostStatus(const M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag);
en_flag_status_t SDIOC_GetAutoCmdErrorStatus(const M4_SDIOC_TypeDef *SDIOCx, uint16_t u16Flag);
void SDIOC_ForceAutoCmdErrorEvent(M4_SDIOC_TypeDef *SDIOCx, uint16_t u16CmdFlag);
void SDIOC_ForceErrorInterruptEvent(M4_SDIOC_TypeDef *SDIOCx, uint16_t u16IntFlag);
/* SDMMC Commands management functions */
en_result_t SDMMC_CMD0_GoIdleState(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD2_AllSendCID(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD3_SendRelativeAddr(M4_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD6_SwitchFunc(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD7_SelectDeselectCard(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD8_SendInterfaceCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD9_SendCSD(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD12_StopTransmission(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD13_SendStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD16_SetBlockLength(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32BlockLen, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD17_ReadSingleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD18_ReadMultipleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD24_WriteSingleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD25_WriteMultipleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD32_EraseBlockStartAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD33_EraseBlockEndAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD38_Erase(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD55_AppCmd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrSta);
en_result_t SDMMC_ACMD6_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32BusWidth, uint32_t *pu32ErrSta);
en_result_t SDMMC_ACMD13_SendStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta);
en_result_t SDMMC_ACMD41_SendOperatCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrSta);
en_result_t SDMMC_ACMD51_SendSCR(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD1_SendOperatCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD35_EraseGroupStartAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrSta);
en_result_t SDMMC_CMD36_EraseGroupEndAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrSta);
/**
* @}
*/
#endif /* DDL_SDIOC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_SDIOC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_smc.h
* @brief This file contains all the functions prototypes of the EXMC SMC
* (External Memory Controller: Static Memory Controller) driver library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hongjh First version
2020-07-14 Hongjh Merge API from EXMC_SMC_Enable/Disable to EXMC_SMC_Cmd
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_SMC_H__
#define __HC32F4A0_SMC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_EXMC_SMC
* @{
*/
#if (DDL_SMC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup EXMC_SMC_Global_Types Static Memory Controller Global Types
* @{
*/
/**
* @brief EXMC SMC Chip Configuration Structure definition
*/
typedef struct
{
uint32_t u32ReadMode; /*!< Defines the read sync enable.
This parameter can be a value of @ref EXMC_SMC_Memory_Read_Mode */
uint32_t u32WriteMode; /*!< Defines the write sync enable.
This parameter can be a value of @ref EXMC_SMC_Memory_Write_Mode */
uint32_t u32ReadBurstLen; /*!< Defines the number of read data access.
This parameter can be a value of @ref EXMC_SMC_Memory_Read_Burst_Length. */
uint32_t u32WriteBurstLen; /*!< Defines the number of write data access.
This parameter can be a value of @ref EXMC_SMC_Memory_Write_Burst_Length. */
uint32_t u32SmcMemWidth; /*!< Defines the SMC memory width.
This parameter can be a value of @ref EXMC_SMC_Memory_Width. */
uint32_t u32BAA; /*!< Defines the SMC BAA signal enable.
This parameter can be a value of @ref EXMC_SMC_BAA_Port_Selection. */
uint32_t u32ADV; /*!< Defines the SMC ADVS signal enable.
This parameter can be a value of @ref EXMC_SMC_ADV_Port_Selection. */
uint32_t u32BLS; /*!< Defines the SMC BLS signal selection.
This parameter can be a value of @ref EXMC_SMC_BLS_Synchronization_Selection. */
uint32_t u32AddressMask; /*!< Defines the address mask.
This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
uint32_t u32AddressMatch; /*!< Defines the address match.
This parameter can be a value between Min_Data = 0x60 and Max_Data = 0x7F */
}stc_exmc_smc_chip_cfg_t;
/**
* @brief EXMC SMC Timing Configuration Structure definition
*/
typedef struct
{
uint32_t u32RC; /*!< Defines the RC in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
uint32_t u32WC; /*!< Defines the WC in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
uint32_t u32CEOE; /*!< Defines the CEOE in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint32_t u32WP; /*!< Defines the WP in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint32_t u32PC; /*!< Defines the PC in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
uint32_t u32TR; /*!< Defines the TR in memory clock cycles.
This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
} stc_exmc_smc_timing_cfg_t;
/**
* @brief EXMC SMC Initialization Structure definition
*/
typedef struct
{
stc_exmc_smc_chip_cfg_t stcChipCfg; /*!< SMC memory chip configure.
This structure details refer @ref stc_exmc_smc_chip_cfg_t. */
stc_exmc_smc_timing_cfg_t stcTimingCfg; /*!< SMC memory timing configure.
This structure details refer @ref stc_exmc_smc_timing_cfg_t. */
} stc_exmc_smc_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup EXMC_SMC_Global_Macros Static Memory Controller Global Macros
* @{
*/
/**
* @defgroup EXMC_SMC_Chip EXMC SMC Chip
* @{
*/
#define EXMC_SMC_CHIP_0 (0UL) /*!< Chip 0 */
#define EXMC_SMC_CHIP_1 (1UL) /*!< Chip 1 */
#define EXMC_SMC_CHIP_2 (2UL) /*!< Chip 2 */
#define EXMC_SMC_CHIP_3 (3UL) /*!< Chip 3 */
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Memory_Read_Mode EXMC SMC Memory Read Mode
* @{
*/
#define EXMC_SMC_MEM_READ_ASYNC (0UL)
#define EXMC_SMC_MEM_READ_SYNC (SMC_CPCR_RSYN)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Memory_Write_Mode EXMC SMC Memory Write Mode
* @{
*/
#define EXMC_SMC_MEM_WRITE_ASYNC (0UL)
#define EXMC_SMC_MEM_WRITE_SYNC (SMC_CPCR_WSYN)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Memory_Read_Burst_Length EXMC SMC Memory Read Burst Length
* @{
*/
#define EXMC_SMC_MEM_READ_BURST_1 (0UL) /*!< 1 beat */
#define EXMC_SMC_MEM_READ_BURST_4 (SMC_CPCR_RBL_0) /*!< 4 beats */
#define EXMC_SMC_MEM_READ_BURST_8 (SMC_CPCR_RBL_1) /*!< 8 beats */
#define EXMC_SMC_MEM_READ_BURST_16 (SMC_CPCR_RBL_1 | \
SMC_CPCR_RBL_0) /*!< 16 beats */
#define EXMC_SMC_MEM_READ_BURST_32 (SMC_CPCR_RBL_2) /*!< 32 beats */
#define EXMC_SMC_MEM_READ_BURST_CONTINUOUS (SMC_CPCR_RBL_2 | \
SMC_CPCR_RBL_0) /*!< continuous */
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Memory_Write_Burst_Length EXMC SMC Memory Write Burst Length
* @{
*/
#define EXMC_SMC_MEM_WRITE_BURST_1 (0UL) /*!< 1 beat */
#define EXMC_SMC_MEM_WRITE_BURST_4 (SMC_CPCR_WBL_0) /*!< 4 beats */
#define EXMC_SMC_MEM_WRITE_BURST_8 (SMC_CPCR_WBL_1) /*!< 8 beats */
#define EXMC_SMC_MEM_WRITE_BURST_16 (SMC_CPCR_WBL_1 | \
SMC_CPCR_WBL_0) /*!< 16 beats */
#define EXMC_SMC_MEM_WRITE_BURST_32 (SMC_CPCR_WBL_2) /*!< 32 beats */
#define EXMC_SMC_MEM_WRITE_BURST_CONTINUOUS (SMC_CPCR_WBL_2 | \
SMC_CPCR_WBL_0) /*!< continuous */
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Memory_Width EXMC SMC Memory Width
* @{
*/
#define EXMC_SMC_MEMORY_WIDTH_16BIT (SMC_CPCR_MW_0)
#define EXMC_SMC_MEMORY_WIDTH_32BIT (SMC_CPCR_MW_1)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_BAA_Port_Selection EXMC SMC BAA Port Selection
* @{
*/
#define EXMC_SMC_BAA_PORT_DISABLE (0UL)
#define EXMC_SMC_BAA_PORT_ENABLE (SMC_CPCR_BAAS)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_ADV_Port_Selection EXMC SMC ADV Port Selection
* @{
*/
#define EXMC_SMC_ADV_PORT_DISABLE (0UL)
#define EXMC_SMC_ADV_PORT_ENABLE (SMC_CPCR_ADVS)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_BLS_Synchronization_Selection EXMC SMC BLS Synchronization Selection
* @{
*/
#define EXMC_SMC_BLS_SYNC_CS (0UL)
#define EXMC_SMC_BLS_SYNC_WE (SMC_CPCR_BLSS)
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Command EXMC SMC Command
* @{
*/
#define EXMC_SMC_CMD_MDREGCONFIG (SMC_CMDR_CMD_0) /*!< Command: MdRetConfig */
#define EXMC_SMC_CMD_UPDATEREGS (SMC_CMDR_CMD_1) /*!< Command: UpdateRegs */
#define EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS (SMC_CMDR_CMD) /*!< Command: MdRetConfig & UpdateRegs */
/**
* @}
*/
/**
* @defgroup EXMC_SMC_CRE_Polarity EXMC SMC CRE Polarity
* @{
*/
#define EXMC_SMC_CRE_POLARITY_LOW (0UL) /*!< CRE is LOW */
#define EXMC_SMC_CRE_POLARITY_HIGH (SMC_CMDR_CRES) /*!< CRE is HIGH when ModeReg write occurs */
/**
* @}
*/
/**
* @defgroup EXMC_SMC_Status EXMC SMC Status
* @{
*/
#define EXMC_SMC_READY (0UL) /*!< SMC is ready */
#define EXMC_SMC_LOWPOWER (SMC_STSR_STATUS) /*!< SMC is low power */
/**
* @}
*/
/**
* @brief SMC device memory address shifting.
* @param [in] mem_base_address SMC base address
* @param [in] mem_width SMC memory width
* @param [in] address SMC device memory address
* @retval SMC device shifted address value
*/
#define SMC_ADDR_SHIFT(mem_base_address, mem_width, address) \
( ((EXMC_SMC_MEMORY_WIDTH_16BIT == (mem_width))? (((mem_base_address) + ((address) << 1UL))):\
(((mem_base_address) + ((address) << 2UL)))))
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup EXMC_SMC_Global_Functions
* @{
*/
/**
* @brief SMC entry low power state
* @param None
* @retval None
*/
__STATIC_INLINE void EXMC_SMC_EntryLowPower(void)
{
WRITE_REG32(M4_SMC->STCR0, SMC_STCR0_LPWIR);
}
/**
* @brief SMC exit low power state
* @param None
* @retval None
*/
__STATIC_INLINE void EXMC_SMC_ExitLowPower(void)
{
WRITE_REG32(M4_SMC->STCR1, SMC_STCR1_LPWOR);
}
/**
* @brief Get SMC status
* @param None
* @retval Returned value can be one of the following values:
* @arg EXMC_SMC_READY: SMC is ready
* @arg EXMC_SMC_LOWPOWER: SMC is low power
*/
__STATIC_INLINE uint32_t EXMC_SMC_GetStatus(void)
{
return READ_REG32_BIT(M4_SMC->STSR, SMC_STSR_STATUS);
}
/* Initialization and configuration EXMC SMC functions */
en_result_t EXMC_SMC_Init(uint32_t u32Chip, const stc_exmc_smc_init_t *pstcInit);
void EXMC_SMC_DeInit(void);
en_result_t EXMC_SMC_StructInit(stc_exmc_smc_init_t *pstcInit);
void EXMC_SMC_Cmd(en_functional_state_t enNewState);
void EXMC_SMC_SetCommand(uint32_t u32Chip,
uint32_t u32Cmd,
uint32_t u32CrePolarity,
uint32_t u32Address);
uint32_t EXMC_SMC_ChipStartAddress(uint32_t u32Chip);
uint32_t EXMC_SMC_ChipEndAddress(uint32_t u32Chip);
en_result_t EXMC_SMC_CheckChipStatus(uint32_t u32Chip,
const stc_exmc_smc_chip_cfg_t *pstcChipCfg);
en_result_t EXMC_SMC_CheckTimingStatus(uint32_t u32Chip,
const stc_exmc_smc_timing_cfg_t *pstcTimingCfg);
void EXMC_SMC_PinMuxCmd(en_functional_state_t enNewState);
void EXMC_SMC_SetRefreshPeriod(uint32_t u32PeriodVal);
/**
* @}
*/
#endif /* DDL_SMC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_SMC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_spi.h
* @brief This file contains all the functions prototypes of the SPI driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Wangmin First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_SPI_H__
#define __HC32F4A0_SPI_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_SPI
* @{
*/
#if (DDL_SPI_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup SPI_Global_Types SPI Global Types
* @{
*/
/**
* @brief Structure definition of SPI initialization.
*/
typedef struct
{
uint32_t u32WireMode; /*!< SPI wire mode, 3 wire mode or 4 wire mode.
This parameter can be a value of @ref SPI_Wire_Mode_Define */
uint32_t u32TransMode; /*!< SPI transfer mode, send only or full duplex.
This parameter can be a value of @ref SPI_Transfer_Mode_Define */
uint32_t u32MasterSlave; /*!< SPI master/slave mode.
This parameter can be a value of @ref SPI_Master_Slave_Mode_Define */
uint32_t u32SuspMode; /*!< SPI communication suspend function.
This parameter can be a value of @ref SPI_Communication_Suspend_Function_Define */
uint32_t u32Modfe; /*!< SPI mode fault detect command.
This parameter can be a value of @ref SPI_Mode_Fault_Dectet_Command_Define */
uint32_t u32Parity; /*!< SPI parity check selection.
This parameter can be a value of @ref SPI_Parity_Check_Define */
uint32_t u32SpiMode; /*!< SPI mode.
This parameter can be a value of @ref SPI_Mode_Define */
uint32_t u32BaudRatePrescaler; /*!< SPI baud rate prescaler.
This parameter can be a value of @ref SPI_Baud_Rate_Prescaler_Define */
uint32_t u32DataBits; /*!< SPI data bits, 4 bits ~ 32 bits.
This parameter can be a value of @ref SPI_Data_Size_Define */
uint32_t u32FirstBit; /*!< MSB first or LSB first.
This parameter can be a value of @ref SPI_First_Bit_Define */
uint32_t u32FrameLevel; /*!< SPI frame level, SPI_FRAME_1 ~ SPI_FRAME_4.
This parameter can be a value of @ref SPI_Frame_Level_Define */
} stc_spi_init_t;
/**
* @brief Structure definition of SPI delay time configuration.
*/
typedef struct
{
uint32_t u32IntervalDelay; /*!< SPI interval time delay (Next access delay time)
This parameter can be a value of @ref SPI_Interval_Delay_Time_define */
uint32_t u32ReleaseDelay; /*!< SPI release time delay (SCK invalid delay time)
This parameter can be a value of @ref SPI_Release_Delay_Time_define */
uint32_t u32SetupDelay; /*!< SPI Setup time delay (SCK valid delay time) define
This parameter can be a value of @ref SPI_Setup_Delay_Time_define */
} stc_spi_delay_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup SPI_Global_Macros SPI Global Macros
* @{
*/
/**
* @defgroup SPI_Wire_Mode_Define SPI wire mode define
* @{
*/
#define SPI_WIRE_4 (0UL)
#define SPI_WIRE_3 (SPI_CR1_SPIMDS)
/**
* @}
*/
/**
* @defgroup SPI_Transfer_Mode_Define SPI transfer mode define
* @{
*/
#define SPI_FULL_DUPLEX (0UL) /*!< Full duplex. */
#define SPI_SEND_ONLY (SPI_CR1_TXMDS) /*!< Send only. */
/**
* @}
*/
/**
* @defgroup SPI_Master_Slave_Mode_Define SPI master slave mode define
* @{
*/
#define SPI_SLAVE (0UL)
#define SPI_MASTER (SPI_CR1_MSTR)
/**
* @}
*/
/**
* @defgroup SPI_Loopback_Selection_Define SPI loopback selection define
* @note Loopback mode is mainly used for parity self-diagnosis in 4-wire full-duplex mode.
* @{
*/
#define SPI_SPLPBK_INVALID (0UL)
#define SPI_SPLPBK_MOSI_INVERT (SPI_CR1_SPLPBK) /*!< MISO data is the inverse of the data output by MOSI. */
#define SPI_SPLPBK_MOSI (SPI_CR1_SPLPBK2) /*!< MISO data is the data output by MOSI. */
/**
* @}
*/
/**
* @defgroup SPI_Communication_Suspend_Function_Define SPI communication suspend function define
* @{
*/
#define SPI_COM_SUSP_FUNC_OFF (0UL)
#define SPI_COM_SUSP_FUNC_ON (SPI_CR1_CSUSPE)
/**
* @}
*/
/**
* @defgroup SPI_Interrupt_Type_Define SPI interrupt type define
* @{
*/
#define SPI_INT_ERROR (SPI_CR1_EIE) /*!< Including overload, underload and parity error. */
#define SPI_INT_TX_BUFFER_EMPTY (SPI_CR1_TXIE)
#define SPI_INT_RX_BUFFER_FULL (SPI_CR1_RXIE)
#define SPI_INT_IDLE (SPI_CR1_IDIE)
/**
* @}
*/
/**
* @defgroup SPI_Mode_Fault_Dectet_Command_Define SPI mode fault dectect command define
* @{
*/
#define SPI_MODFE_DISABLE (0UL) /*!< Disable mode fault detection. */
#define SPI_MODFE_ENABLE (SPI_CR1_MODFE) /*!< Enable mode fault detection. */
/**
* @}
*/
/**
* @defgroup SPI_Parity_Check_Error_Self_Diagnosis_Define SPI parity check error self diagnosis define
* @{
*/
#define SPI_PATE_DISABLE (0UL) /*!< Disable self diagnosis of parity check. */
#define SPI_PATE_ENABLE (SPI_CR1_PATE) /*!< Enable self diagnosis of parity check. */
/**
* @}
*/
/**
* @defgroup SPI_Parity_Check_Define SPI parity check mode define
* @{
*/
#define SPI_PARITY_INVALID (0UL) /*!< Parity check invalid. */
#define SPI_PARITY_EVEN (SPI_CR1_PAE) /*!< Parity check selection even parity. */
#define SPI_PARITY_ODD (SPI_CR1_PAE | SPI_CR1_PAOE) /*!< Parity check selection odd parity. */
/**
* @}
*/
/**
* @defgroup SPI_Interval_Delay_Time_define SPI interval time delay (Next access delay time) define
* @{
*/
#define SPI_INTERVAL_TIME_1SCK_2PCLK1 (0UL)
#define SPI_INTERVAL_TIME_2SCK_2PCLK1 (SPI_CFG1_MIDI_0)
#define SPI_INTERVAL_TIME_3SCK_2PCLK1 (SPI_CFG1_MIDI_1)
#define SPI_INTERVAL_TIME_4SCK_2PCLK1 (SPI_CFG1_MIDI_1 | SPI_CFG1_MIDI_0)
#define SPI_INTERVAL_TIME_5SCK_2PCLK1 (SPI_CFG1_MIDI_2)
#define SPI_INTERVAL_TIME_6SCK_2PCLK1 (SPI_CFG1_MIDI_2 | SPI_CFG1_MIDI_0)
#define SPI_INTERVAL_TIME_7SCK_2PCLK1 (SPI_CFG1_MIDI_2 | SPI_CFG1_MIDI_1)
#define SPI_INTERVAL_TIME_8SCK_2PCLK1 (SPI_CFG1_MIDI_2 | SPI_CFG1_MIDI_1 | SPI_CFG1_MIDI_0)
/**
* @}
*/
/**
* @defgroup SPI_Release_Delay_Time_define SPI release time delay (SCK invalid delay time) define
* @{
*/
#define SPI_RELEASE_TIME_1SCK (0UL)
#define SPI_RELEASE_TIME_2SCK (SPI_CFG1_MSSDL_0)
#define SPI_RELEASE_TIME_3SCK (SPI_CFG1_MSSDL_1)
#define SPI_RELEASE_TIME_4SCK (SPI_CFG1_MSSDL_1 | SPI_CFG1_MSSDL_0)
#define SPI_RELEASE_TIME_5SCK (SPI_CFG1_MSSDL_2)
#define SPI_RELEASE_TIME_6SCK (SPI_CFG1_MSSDL_2 | SPI_CFG1_MSSDL_0)
#define SPI_RELEASE_TIME_7SCK (SPI_CFG1_MSSDL_2 | SPI_CFG1_MSSDL_1)
#define SPI_RELEASE_TIME_8SCK (SPI_CFG1_MSSDL_2 | SPI_CFG1_MSSDL_1 | SPI_CFG1_MSSDL_0)
/**
* @}
*/
/**
* @defgroup SPI_Setup_Delay_Time_define SPI Setup time delay (SCK valid delay time) define
* @{
*/
#define SPI_SETUP_TIME_1SCK (0UL)
#define SPI_SETUP_TIME_2SCK (SPI_CFG1_MSSI_0)
#define SPI_SETUP_TIME_3SCK (SPI_CFG1_MSSI_1)
#define SPI_SETUP_TIME_4SCK (SPI_CFG1_MSSI_1 | SPI_CFG1_MSSI_0)
#define SPI_SETUP_TIME_5SCK (SPI_CFG1_MSSI_2)
#define SPI_SETUP_TIME_6SCK (SPI_CFG1_MSSI_2 | SPI_CFG1_MSSI_0)
#define SPI_SETUP_TIME_7SCK (SPI_CFG1_MSSI_2 | SPI_CFG1_MSSI_1)
#define SPI_SETUP_TIME_8SCK (SPI_CFG1_MSSI_2 | SPI_CFG1_MSSI_1 | SPI_CFG1_MSSI_0)
/**
* @}
*/
/**
* @defgroup SPI_SS_Pin_Define SPI SSx define
* @{
*/
#define SPI_PIN_SS0 (SPI_CFG1_SS0PV)
#define SPI_PIN_SS1 (SPI_CFG1_SS1PV)
#define SPI_PIN_SS2 (SPI_CFG1_SS2PV)
#define SPI_PIN_SS3 (SPI_CFG1_SS3PV)
/**
* @}
*/
/**
* @defgroup SPI_SS_Active_Level_Define SPI SSx Active Level define
* @{
*/
#define SPI_SS_ACTIVE_LOW (0UL) /*!< SS pin active low. */
#define SPI_SS_ACTIVE_HIGH (1UL) /*!< SS pin active high. */
/**
* @}
*/
/**
* @defgroup SPI_Read_Target_Buffer_Define SPI read data register target buffer define
* @{
*/
#define SPI_RD_TARGET_RD_BUF (0UL) /*!< Read RX buffer. */
#define SPI_RD_TARGET_WR_BUF (SPI_CFG1_SPRDTD) /*!< Read TX buffer. */
/**
* @}
*/
/**
* @defgroup SPI_Frame_Level_Define SPI data frame level define, The Data in the
* SPI_DR register will be send to TX_BUFF after
* enough data frame write to the SPI_DR
* @{
*/
#define SPI_FRAME_1 (0UL) /*!< Data 1 frame */
#define SPI_FRAME_2 (SPI_CFG1_FTHLV_0) /*!< Data 2 frame.*/
#define SPI_FRAME_3 (SPI_CFG1_FTHLV_1) /*!< Data 3 frame.*/
#define SPI_FRAME_4 (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1) /*!< Data 4 frame.*/
/**
* @}
*/
/**
* @defgroup SPI_Mode_Define SPI Mode define
* @{
*/
/* SCK pin output low in idle state; MOSI/MISO pin data valid in odd edge , MOSI/MISO pin data change in even edge */
#define SPI_MODE_0 (0UL)
/* SCK pin output low in idle state; MOSI/MISO pin data valid in even edge , MOSI/MISO pin data change in odd edge */
#define SPI_MODE_1 (SPI_CFG2_CPHA)
/* SCK pin output high in idle state; MOSI/MISO pin data valid in odd edge , MOSI/MISO pin data change in even edge */
#define SPI_MODE_2 (SPI_CFG2_CPOL)
/* SCK pin output high in idle state; MOSI/MISO pin data valid in even edge , MOSI/MISO pin data change in odd edge */
#define SPI_MODE_3 (SPI_CFG2_CPOL | SPI_CFG2_CPHA)
/**
* @}
*/
/**
* @defgroup SPI_Baud_Rate_Prescaler_Define SPI baudrate prescaler define
* @{
*/
#define SPI_BR_PCLK1_DIV2 (0UL) /*!< SPI baud rate is the pclk1 divided by 2. */
#define SPI_BR_PCLK1_DIV4 (SPI_CFG2_MBR_0) /*!< SPI baud rate is the pclk1 clock divided by 4. */
#define SPI_BR_PCLK1_DIV8 (SPI_CFG2_MBR_1) /*!< SPI baud rate is the pclk1 clock divided by 8. */
#define SPI_BR_PCLK1_DIV16 (SPI_CFG2_MBR_1 | SPI_CFG2_MBR_0) /*!< SPI baud rate is the pclk1 clock divided by 16. */
#define SPI_BR_PCLK1_DIV32 (SPI_CFG2_MBR_2) /*!< SPI baud rate is the pclk1 clock divided by 32. */
#define SPI_BR_PCLK1_DIV64 (SPI_CFG2_MBR_2 | SPI_CFG2_MBR_0) /*!< SPI baud rate is the pclk1 clock divided by 64. */
#define SPI_BR_PCLK1_DIV128 (SPI_CFG2_MBR_2 | SPI_CFG2_MBR_1) /*!< SPI baud rate is the pclk1 clock divided by 128. */
#define SPI_BR_PCLK1_DIV256 (SPI_CFG2_MBR_2 | SPI_CFG2_MBR_1 | SPI_CFG2_MBR_0) /*!< SPI baud rate is the pclk1 divided by 256. */
/**
* @}
*/
/**
* @defgroup SPI_Data_Size_Define SPI data size define
* @{
*/
#define SPI_DATA_SIZE_4BIT (0UL)
#define SPI_DATA_SIZE_5BIT (SPI_CFG2_DSIZE_0)
#define SPI_DATA_SIZE_6BIT (SPI_CFG2_DSIZE_1)
#define SPI_DATA_SIZE_7BIT (SPI_CFG2_DSIZE_0 | SPI_CFG2_DSIZE_1)
#define SPI_DATA_SIZE_8BIT (SPI_CFG2_DSIZE_2)
#define SPI_DATA_SIZE_9BIT (SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_0)
#define SPI_DATA_SIZE_10BIT (SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_1)
#define SPI_DATA_SIZE_11BIT (SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_1 | SPI_CFG2_DSIZE_0)
#define SPI_DATA_SIZE_12BIT (SPI_CFG2_DSIZE_3)
#define SPI_DATA_SIZE_13BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_0)
#define SPI_DATA_SIZE_14BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_1)
#define SPI_DATA_SIZE_15BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_1 | SPI_CFG2_DSIZE_0)
#define SPI_DATA_SIZE_16BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_2)
#define SPI_DATA_SIZE_20BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_0)
#define SPI_DATA_SIZE_24BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_1)
#define SPI_DATA_SIZE_32BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_1 | SPI_CFG2_DSIZE_0)
/**
* @}
*/
/**
* @defgroup SPI_First_Bit_Define SPI first bit define
* @{
*/
#define SPI_FIRST_MSB (0UL)
#define SPI_FIRST_LSB (SPI_CFG2_LSBF)
/**
* @}
*/
/**
* @defgroup SPI_State_Flag_Define SPI state flag define
* @{
*/
#define SPI_FLAG_OVERLOAD (SPI_SR_OVRERF)
#define SPI_FLAG_IDLE (SPI_SR_IDLNF)
#define SPI_FLAG_MODE_FAULT (SPI_SR_MODFERF)
#define SPI_FLAG_PARITY_ERROR (SPI_SR_PERF)
#define SPI_FLAG_UNDERLOAD (SPI_SR_UDRERF)
#define SPI_FLAG_TX_BUFFER_EMPTY (SPI_SR_TDEF) /*!< This flag is set when the data in the data register \
is copied into the shift register, but the transmission \
of the data bit may not have been completed. */
#define SPI_FLAG_RX_BUFFER_FULL (SPI_SR_RDFF) /*!< When this flag is set, it indicates that a data was received. */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup SPI_Global_Functions
* @{
*/
en_result_t SPI_StructInit(stc_spi_init_t *pstcInit);
en_result_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayCfg);
en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcInit);
void SPI_DeInit(M4_SPI_TypeDef *SPIx);
void SPI_IntCmd(M4_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState);
void SPI_FunctionCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewState);
void SPI_WriteDataReg(M4_SPI_TypeDef *SPIx, uint32_t u32Data);
uint32_t SPI_ReadDataReg(const M4_SPI_TypeDef *SPIx);
en_flag_status_t SPI_GetStatus(const M4_SPI_TypeDef *SPIx, uint32_t u32Flag);
void SPI_ClearFlag(M4_SPI_TypeDef *SPIx, uint32_t u32Flag);
void SPI_LoopbackModeCfg(M4_SPI_TypeDef *SPIx, uint32_t u32Mode);
void SPI_PateCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewState);
en_result_t SPI_DelayTimeCfg(M4_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayCfg);
void SPI_SSValidLevelCfg(M4_SPI_TypeDef *SPIx, uint32_t u32SSPin, en_functional_state_t enNewState);
void SPI_SSPinSel(M4_SPI_TypeDef *SPIx, uint32_t u32SSPin);
void SPI_ReadBufCfg(M4_SPI_TypeDef *SPIx, uint32_t u32ReadBuf);
en_result_t SPI_Transmit(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLength);
en_result_t SPI_Receive(M4_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLength);
en_result_t SPI_TransmitReceive(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Length);
/**
* @}
*/
#endif /* DDL_SPI_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_SPI_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_sram.h
* @brief This file contains all the functions prototypes of the SRAM driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Wuze First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_SRAM_H__
#define __HC32F4A0_SRAM_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_SRAM
* @{
*/
#if (DDL_SRAM_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup SRAM_Global_Macros SRAM Global Macros
* @{
*/
/**
* @defgroup SRAM_Index_Bit_Mask SRAM Index Bit Mask
* @{
*/
#define SRAM_SRAMH (1UL << 2U) /*!< 0x1FFE0000~0x1FFFFFFF, 128KB */
#define SRAM_SRAM123 (1UL << 0U) /*!< SRAM1: 0x20000000~0x2001FFFF, 128KB \
SRAM2: 0x20020000~0x2003FFFF, 128KB \
SRAM3: 0x20040000~0x20057FFF, 96KB */
#define SRAM_SRAM4 (1UL << 1U) /*!< 0x20058000~0x2005FFFF, 32KB */
#define SRAM_SRAMB (1UL << 3U) /*!< 0x200F0000~0x200F0FFF, 4KB */
#define SRAM_SRAM_ALL (SRAM_SRAMH | SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB)
/**
* @}
*/
/**
* @defgroup SRAM_Access_Wait_Cycle SRAM Access Wait Cycle
* @{
*/
#define SRAM_WAIT_CYCLE_0 (0U) /*!< Wait 0 CPU cycle. */
#define SRAM_WAIT_CYCLE_1 (1U) /*!< Wait 1 CPU cycle. */
#define SRAM_WAIT_CYCLE_2 (2U) /*!< Wait 2 CPU cycles. */
#define SRAM_WAIT_CYCLE_3 (3U) /*!< Wait 3 CPU cycles. */
#define SRAM_WAIT_CYCLE_4 (4U) /*!< Wait 4 CPU cycles. */
#define SRAM_WAIT_CYCLE_5 (5U) /*!< Wait 5 CPU cycles. */
#define SRAM_WAIT_CYCLE_6 (6U) /*!< Wait 6 CPU cycles. */
#define SRAM_WAIT_CYCLE_7 (7U) /*!< Wait 7 CPU cycles. */
/**
* @}
*/
/**
* @defgroup SRAM_Operation_After_Check_Error SRAM Operation After Check Error
* @note For: Even-parity check error of SRAM1, SRAM2, SRAM3 and SRAMH. ECC check error of SRAM4 and SRAMB.
* @{
*/
#define SRAM_ERR_OP_NMI (0U) /*!< Non-maskable interrupt occurres while check error occurres. */
#define SRAM_ERR_OP_RESET (SRAMC_CKCR_PYOAD) /*!< System reset occurres while check error occurres. */
/**
* @}
*/
/**
* @defgroup SRAM_ECC_Mode SRAM ECC Mode
* @note For: SRAM4 and SRAMB.
* @{
*/
#define SRAM_ECC_MODE_INVALID (0U) /*!< The ECC mode is invalid. */
#define SRAM_ECC_MODE_1 (SRAMC_CKCR_ECCMOD_0) /*!< When 1-bit error occurres: \
ECC error corrects. \
No 1-bit-error status flag setting, no interrupt or reset. \
When 2-bit error occurres: \
ECC error detects. \
2-bit-error status flag sets and interrupt or reset occurres. */
#define SRAM_ECC_MODE_2 (SRAMC_CKCR_ECCMOD_1) /*!< When 1-bit error occurres: \
ECC error corrects. \
1-bit-error status flag sets, no interrupt or reset. \
When 2-bit error occurres: \
ECC error detects. \
2-bit-error status flag sets and interrupt or reset occurres. */
#define SRAM_ECC_MODE_3 (SRAMC_CKCR_ECCMOD_1 | \
SRAMC_CKCR_ECCMOD_0) /*!< When 1-bit error occurres: \
ECC error corrects. \
1-bit-error status flag sets and interrupt or reset occurres. \
When 2-bit error occurres: \
ECC error detects. \
2-bit-error status flag sets and interrupt or reset occurres. */
/**
* @}
*/
/**
* @defgroup SRAM_Check_Status_Flag SRAM Check Status Flag
* @{
*/
#define SRAM_FLAG_SRAM1_PYERR (SRAMC_CKSR_SRAM1_PYERR) /*!< SRAM1 parity error. */
#define SRAM_FLAG_SRAM2_PYERR (SRAMC_CKSR_SRAM2_PYERR) /*!< SRAM2 parity error. */
#define SRAM_FLAG_SRAM3_PYERR (SRAMC_CKSR_SRAM3_PYERR) /*!< SRAM3 parity error. */
#define SRAM_FLAG_SRAMH_PYERR (SRAMC_CKSR_SRAMH_PYERR) /*!< SRAMH parity error. */
#define SRAM_FLAG_SRAM4_1ERR (SRAMC_CKSR_SRAM4_1ERR) /*!< SRAM4 ECC 1-bit error. */
#define SRAM_FLAG_SRAM4_2ERR (SRAMC_CKSR_SRAM4_2ERR) /*!< SRAM4 ECC 2-bit error. */
#define SRAM_FLAG_SRAMB_1ERR (SRAMC_CKSR_SRAMB_1ERR) /*!< SRAMB ECC 1-bit error. */
#define SRAM_FLAG_SRAMB_2ERR (SRAMC_CKSR_SRAMB_2ERR) /*!< SRAMB ECC 2-bit error. */
#define SRAM_FLAG_CACHE_PYERR (SRAMC_CKSR_CACHE_PYERR) /*!< Cache RAM parity error. */
#define SRAM_FLAG_ALL (0x1FFUL)
/**
* @}
*/
/**
* @defgroup SRAM_Register_Protect_Command SRAM Register Protect Command
* @{
*/
#define SRAM_LOCK_CMD (0x76U)
#define SRAM_UNLOCK_CMD (0x77U)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup SRAM_Global_Functions
* @{
*/
/**
* @brief Lock access wait cycle control register.
* @param None
* @retval None
*/
__STATIC_INLINE void SRAM_WTCR_Lock(void)
{
WRITE_REG32(M4_SRAMC->WTPR, SRAM_LOCK_CMD);
}
/**
* @brief Unlock access wait cycle control register.
* @param None
* @retval None
*/
__STATIC_INLINE void SRAM_WTCR_Unlock(void)
{
WRITE_REG32(M4_SRAMC->WTPR, SRAM_UNLOCK_CMD);
}
/**
* @brief Lock check control register.
* @param None
* @retval None
*/
__STATIC_INLINE void SRAM_CKCR_Lock(void)
{
WRITE_REG32(M4_SRAMC->CKPR, SRAM_LOCK_CMD);
}
/**
* @brief Unlock check control register.
* @param None
* @retval None
*/
__STATIC_INLINE void SRAM_CKCR_Unlock(void)
{
WRITE_REG32(M4_SRAMC->CKPR, SRAM_UNLOCK_CMD);
}
void SRAM_Init(void);
void SRAM_DeInit(void);
void SRAM_WTCR_Lock(void);
void SRAM_WTCR_Unlock(void);
void SRAM_CKCR_Lock(void);
void SRAM_CKCR_Unlock(void);
void SRAM_SetWaitCycle(uint32_t u32SramIndex, uint32_t u32WriteCycle, uint32_t u32ReadCycle);
void SRAM_SetEccMode(uint32_t u32SramIndex, uint32_t u32EccMode);
void SRAM_SetErrOperation(uint32_t u32SramIndex, uint32_t u32OpAfterError);
en_flag_status_t SRAM_GetStatus(uint32_t u32Flag);
void SRAM_ClrStatus(uint32_t u32Flag);
/**
* @}
*/
#endif /* DDL_SRAM_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_SRAM_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_swdt.h
* @brief This file contains all the functions prototypes of the SWDT driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_SWDT_H__
#define __HC32F4A0_SWDT_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_SWDT
* @{
*/
#if (DDL_SWDT_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup SWDT_Global_Types SWDT Global Types
* @{
*/
/**
* @brief SWDT Init structure definition
*/
typedef struct
{
uint32_t u32CountCycle; /*!< Specifies the SWDT Count Cycle.
This parameter can be a value of @ref SWDT_Counter_Cycle */
uint32_t u32ClockDivision; /*!< Specifies the SWDT Clock Division.
This parameter can be a value of @ref SWDT_Clock_Division */
uint32_t u32RefreshRange; /*!< Specifies the SWDT Allow Refresh Range.
This parameter can be a value of @ref SWDT_Refresh_Percent_Range */
uint32_t u32LPModeCountEn; /*!< Specifies the SWDT Count Enable/Disable In Low Power Mode(Sleep/Stop Mode).
This parameter can be a value of @ref SWDT_LPW_Mode_Count */
uint32_t u32TrigType; /*!< Specifies the SWDT Refresh Error or Count Underflow trigger event Type.
This parameter can be a value of @ref SWDT_Trigger_Event_Type */
} stc_swdt_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup SWDT_Global_Macros SWDT Global Macros
* @{
*/
/**
* @defgroup SWDT_Counter_Cycle SWDT Counter Cycle
* @{
*/
#define SWDT_COUNTER_CYCLE_256 (0UL) /*!< 256 clock cycle */
#define SWDT_COUNTER_CYCLE_4096 (SWDT_CR_PERI_0) /*!< 4096 clock cycle */
#define SWDT_COUNTER_CYCLE_16384 (SWDT_CR_PERI_1) /*!< 16384 clock cycle */
#define SWDT_COUNTER_CYCLE_65536 (SWDT_CR_PERI) /*!< 65536 clock cycle */
/**
* @}
*/
/**
* @defgroup SWDT_Clock_Division SWDT Clock Division
* @{
*/
#define SWDT_CLOCK_DIV1 (0UL) /*!< SWDTCLK */
#define SWDT_CLOCK_DIV16 (SWDT_CR_CKS_2) /*!< SWDTCLK/16 */
#define SWDT_CLOCK_DIV32 (SWDT_CR_CKS_2 | SWDT_CR_CKS_0) /*!< SWDTCLK/32 */
#define SWDT_CLOCK_DIV64 (SWDT_CR_CKS_2 | SWDT_CR_CKS_1) /*!< SWDTCLK/64 */
#define SWDT_CLOCK_DIV128 (SWDT_CR_CKS_2 | SWDT_CR_CKS_1 | SWDT_CR_CKS_0) /*!< SWDTCLK/128 */
#define SWDT_CLOCK_DIV256 (SWDT_CR_CKS_3) /*!< SWDTCLK/256 */
#define SWDT_CLOCK_DIV2048 (SWDT_CR_CKS_3 | SWDT_CR_CKS_1 | SWDT_CR_CKS_0) /*!< SWDTCLK/2048 */
/**
* @}
*/
/**
* @defgroup SWDT_Refresh_Percent_Range SWDT Refresh Percent Range
* @{
*/
#define SWDT_RANGE_0TO100PCT (0UL) /*!< 0%~100% */
#define SWDT_RANGE_0TO25PCT (SWDT_CR_WDPT_0) /*!< 0%~25% */
#define SWDT_RANGE_25TO50PCT (SWDT_CR_WDPT_1) /*!< 25%~50% */
#define SWDT_RANGE_0TO50PCT (SWDT_CR_WDPT_1 | SWDT_CR_WDPT_0) /*!< 0%~50% */
#define SWDT_RANGE_50TO75PCT (SWDT_CR_WDPT_2) /*!< 50%~75% */
#define SWDT_RANGE_0TO25PCT_50TO75PCT (SWDT_CR_WDPT_2 | SWDT_CR_WDPT_0) /*!< 0%~25% & 50%~75% */
#define SWDT_RANGE_25TO75PCT (SWDT_CR_WDPT_2 | SWDT_CR_WDPT_1) /*!< 25%~75% */
#define SWDT_RANGE_0TO75PCT (SWDT_CR_WDPT_2 | SWDT_CR_WDPT_1 | SWDT_CR_WDPT_0) /*!< 0%~75% */
#define SWDT_RANGE_75TO100PCT (SWDT_CR_WDPT_3) /*!< 75%~100% */
#define SWDT_RANGE_0TO25PCT_75TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_0) /*!< 0%~25% & 75%~100% */
#define SWDT_RANGE_25TO50PCT_75TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_1) /*!< 25%~50% & 75%~100% */
#define SWDT_RANGE_0TO50PCT_75TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_1 | SWDT_CR_WDPT_0) /*!< 0%~50% & 75%~100% */
#define SWDT_RANGE_50TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_2) /*!< 50%~100% */
#define SWDT_RANGE_0TO25PCT_50TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_2 | SWDT_CR_WDPT_0) /*!< 0%~25% & 50%~100% */
#define SWDT_RANGE_25TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_2 | SWDT_CR_WDPT_1) /*!< 25%~100% */
/**
* @}
*/
/**
* @defgroup SWDT_LPW_Mode_Count SWDT Low Power Mode Count
* @brief SWDT count control in the sleep/stop mode
* @{
*/
#define SWDT_LPM_COUNT_CONTINUE (0UL) /*!< SWDT count continue in the sleep/stop mode */
#define SWDT_LPM_COUNT_STOP (SWDT_CR_SLPOFF) /*!< SWDT count stop in the sleep/stop mode */
/**
* @}
*/
/**
* @defgroup SWDT_Trigger_Event_Type SWDT Trigger Event Type
* @{
*/
#define SWDT_TRIG_EVENT_INT (0UL) /*!< SWDT trigger interrupt */
#define SWDT_TRIG_EVENT_RESET (SWDT_CR_ITS) /*!< SWDT trigger reset */
/**
* @}
*/
/**
* @defgroup SWDT_Flag SWDT Flag
* @{
*/
#define SWDT_FLAG_UDF (SWDT_SR_UDF) /*!< Count underflow flag */
#define SWDT_FLAG_REF (SWDT_SR_REF) /*!< Refresh error flag */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup SWDT_Global_Functions
* @{
*/
/**
* @brief Get SWDT count value.
* @param None
* @retval Count value
*/
__STATIC_INLINE uint16_t SWDT_GetCountValue(void)
{
return (uint16_t)(READ_REG32(M4_SWDT->SR) & SWDT_SR_CNT);
}
/* Initialization and configuration functions */
en_result_t SWDT_Init(const stc_swdt_init_t *pstcSwdtInit);
void SWDT_Feed(void);
uint16_t SWDT_GetCountValue(void);
/* Flags management functions */
en_flag_status_t SWDT_GetStatus(uint32_t u32Flag);
en_result_t SWDT_ClearStatus(uint32_t u32Flag);
/**
* @}
*/
#endif /* DDL_SWDT_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_SWDT_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_tmr0.h
* @brief This file contains all the functions prototypes of the TMR0 driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Heqb First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_TMR0_H__
#define __HC32F4A0_TMR0_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_TMR0
* @{
*/
#if (DDL_TMR0_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup TMR0_Global_Types TMR0 Global Types
* @{
*/
/**
* @brief Tmr0 base counter function init structrue definition
*/
typedef struct
{
uint32_t u32ClockDivision; /*!< Specifies the TMR0 clock division,
and this parameter can be a value of
@ref TMR0_Clock_Division_define */
uint32_t u32ClockSource; /*!< Specifies the TMR0 clock source,
and this parameter can be a value of
@ref TMR0_Clock_Source_define*/
uint32_t u32Tmr0Func; /*!< Specifies the TMR0 function,
compare output or capture input
@ref TMR0_Function_define */
uint32_t u32HwTrigFunc; /*!< Specifies the TMR0 compare
function hardware trigger function, and
this parameter can be a value of @ref
TMR0_HardwareTrigger_Func_define */
uint16_t u16CmpValue; /*!< Specifies the TMR0 compare value
This value can be set 0-0xFFFF */
uint16_t u16CntValue; /*!< Specifies the TMR0 count value
This value can be set 0-0xFFFF */
}stc_tmr0_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup TMR0_Global_Macros TMR0 Global Macros
* @{
*/
/** @defgroup TMR0_Clock_Division_define TMR0 clock division define
* @{
*/
#define TMR0_CLK_DIV1 (0UL<<TMR0_BCONR_CKDIVA_POS)
#define TMR0_CLK_DIV2 (1UL<<TMR0_BCONR_CKDIVA_POS)
#define TMR0_CLK_DIV4 (2UL<<TMR0_BCONR_CKDIVA_POS)
#define TMR0_CLK_DIV8 (3UL<<TMR0_BCONR_CKDIVA_POS)
#define TMR0_CLK_DIV16 (4UL<<TMR0_BCONR_CKDIVA_POS)
#define TMR0_CLK_DIV32 (5UL<<TMR0_BCONR_CKDIVA_POS)
#define TMR0_CLK_DIV64 (6UL<<TMR0_BCONR_CKDIVA_POS)
#define TMR0_CLK_DIV128 (7UL<<TMR0_BCONR_CKDIVA_POS)
#define TMR0_CLK_DIV256 (8UL<<TMR0_BCONR_CKDIVA_POS)
#define TMR0_CLK_DIV512 (9UL<<TMR0_BCONR_CKDIVA_POS)
#define TMR0_CLK_DIV1024 (10UL<<TMR0_BCONR_CKDIVA_POS)
/**
* @}
*/
/**
* @defgroup TMR0_Channel_Index TMR0 Channel Index
* @{
*/
#define TMR0_CH_A (0U)
#define TMR0_CH_B (1U)
/**
* @}
*/
/** @defgroup TMR0_Clock_Source_define TMR0 clock source define
* @{
*/
#define TMR0_CLK_SRC_PCLK1 (0x00000000UL)
#define TMR0_CLK_SRC_INTHWTRIG (TMR0_BCONR_SYNCLKA)
#define TMR0_CLK_SRC_LRC (TMR0_BCONR_SYNSA)
#define TMR0_CLK_SRC_XTAL32 (TMR0_BCONR_ASYNCLKA | TMR0_BCONR_SYNSA)
/**
* @}
*/
/** @defgroup TMR0_Function_define TMR0 Function define
* @{
*/
#define TMR0_FUNC_CMP (0x00000000UL)
#define TMR0_FUNC_CAP (TMR0_BCONR_CAPMDA | TMR0_BCONR_HICPA)
/**
* @}
*/
/** @defgroup TMR0_HardwareTrigger_Func_define TMR0 hardware trigger function define
* @{
*/
#define TMR0_BT_HWTRG_FUNC_START (TMR0_BCONR_HSTAA)
#define TMR0_BT_HWTRG_FUNC_CLEAR (TMR0_BCONR_HCLEA)
#define TMR0_BT_HWTRG_FUNC_STOP (TMR0_BCONR_HSTPA)
#define TMR0_BT_HWTRG_FUNC_NONE (0x00000000UL)
#define TMR0_BT_HETRG_FUNC_MASK (TMR0_BT_HWTRG_FUNC_START | \
TMR0_BT_HWTRG_FUNC_CLEAR | \
TMR0_BT_HWTRG_FUNC_STOP)
/**
* @}
*/
/**
* @defgroup TMR0_CAMPAR_FLAG TMR0 Compare Status
* @{
*/
#define TMR0_FLAG_CMP_A (TMR0_STFLR_CMFA)
#define TMR0_FLAG_CMP_B (TMR0_STFLR_CMFB)
/**
* @}
*/
/**
* @defgroup TMR0_Common_Trigger_Sel TMR0 common Trigger source select
* @{
*/
#define TMR0_COM_TRIG1 (AOS_TMR0_HTSSR_COMTRG_EN_0)
#define TMR0_COM_TRIG2 (AOS_TMR0_HTSSR_COMTRG_EN_1)
#define TMR0_COM_TRIG_MASk (AOS_TMR0_HTSSR_COMTRG_EN)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup TMR0_Global_Functions
* @{
*/
en_result_t TMR0_StructInit(stc_tmr0_init_t* pstcInitStruct);
en_result_t TMR0_Init(M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel, \
const stc_tmr0_init_t* pstcTmr0Init);
void TMR0_DeInit(M4_TMR0_TypeDef* TMR0x);
void TMR0_Cmd(M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel, \
en_functional_state_t enNewState);
void TMR0_IntCmd(M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel, \
en_functional_state_t enNewState);
void TMR0_SetClkSrc(M4_TMR0_TypeDef *TMR0x, uint8_t u8Channel, uint32_t u32ClkSrc);
void TMR0_SetClkDiv(M4_TMR0_TypeDef *TMR0x, uint8_t u8Channel, uint32_t u32ClkDiv);
void TMR0_HWTrigCmd(M4_TMR0_TypeDef *TMR0x, uint8_t u8Channel, \
uint32_t u32HWFunc, en_functional_state_t enNewState);
void TMR0_SetFunc(M4_TMR0_TypeDef *TMR0x, uint8_t u8Channel, uint32_t u32Func);
void TMR0_SetCntVal(M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel, uint16_t u16Value);
void TMR0_SetCmpVal(M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel, uint16_t u16Value);
void TMR0_ClearStatus(M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel);
void TMR0_SetTriggerSrc(en_event_src_t enEvent);
void TMR0_ComTriggerCmd(uint32_t u32ComTrig, en_functional_state_t enNewState);
en_flag_status_t TMR0_GetStatus(const M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel);
uint16_t TMR0_GetCntVal(const M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel);
uint16_t TMR0_GetCmpVal(const M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel);
/**
* @}
*/
#endif /* DDL_TMR0_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_TMR0_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_tmr2.h
* @brief This file contains all the functions prototypes of the TMR2(Timer2)
* driver library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Wuze First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_TMR2_H__
#define __HC32F4A0_TMR2_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_TMR2
* @{
*/
#if (DDL_TMR2_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup TMR2_Global_Types TMR2 Global Types
* @{
*/
/**
* @brief TMR2 initialization structure.
*/
typedef struct
{
uint32_t u32FuncMode; /*!< Specify the function mode for TMR2's channel.
This parameter can be a value of @ref TMR2_Function_Mode */
uint32_t u32ClkSrc; /*!< Specify the clock source for TMR2's channel.
This parameter can be a value of @ref TMR2_Clock_Source */
uint32_t u32ClkDiv; /*!< Specify the division of the clock source.
This parameter can be a value of @ref TMR2_Clock_Divider */
uint32_t u32CmpVal; /*!< Specify the compare value depends on your application.
This parameter can be a number between 0U and 0xFFFFU, inclusive. */
uint32_t u32CntVal; /*!< Initial value of the count register.
This parameter can be a number between 0U and 0xFFFFU, inclusive. */
} stc_tmr2_init_t;
/**
* @brief TMR2 PWM output polarity configuration structure.
*/
typedef struct
{
uint32_t u32StartPolarity; /*!< Specify the polarity of PWM output when TMR2 counting start.
This parameter can be a value of @ref TMR2_PWM_Start_Polarity */
uint32_t u32StopPolarity; /*!< Specify the polarity of PWM output when TMR2 counting stop.
This parameter can be a value of @ref TMR2_PWM_Stop_Polarity */
uint32_t u32CmpPolarity; /*!< Specify the polarity of PWM output when TMR2 counting matches the compare value.
This parameter can be a value of @ref TMR2_PWM_Cmp_Polarity */
} stc_tmr2_pwm_cfg_t;
/**
* @brief TMR2 hardware trigger condition configuration structure.
*/
typedef struct
{
uint32_t u32StartCond; /*!< Specify the trigger condition of start counting.
This parameter can be a value of @ref TMR2_Hardware_Start_Condition */
uint32_t u32StopCond; /*!< Specify the trigger condition of stop counting.
This parameter can be a value of @ref TMR2_Hardware_Stop_Condition */
uint32_t u32ClrCond; /*!< Specify the trigger condition of clearing counter register.
This parameter can be a value of @ref TMR2_Hardware_Clear_Condition */
uint32_t u32CaptCond; /*!< Specify the trigger condition of start capturing.
This parameter can be a value of @ref TMR2_Hardware_Capture_Condition */
} stc_tmr2_trig_cond_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup TMR2_Global_Macros TMR2 Global Macros
* @{
*/
/**
* @defgroup TMR2_Channel_Number TMR2 Channel Number
* @{
*/
#define TMR2_CH_A (0U) /*!< Channel A of TMR2. */
#define TMR2_CH_B (1U) /*!< Channel B of TMR2. */
/**
* @}
*/
/**
* @defgroup TMR2_Function_Mode TMR2 Function Mode
* @{
*/
#define TMR2_FUNC_COMPARE (0x0U) /*!< The function mode of TMR2 is comparison ouput. */
#define TMR2_FUNC_CAPTURE (TMR2_BCONR_CAPMDA) /*!< The function mode of TMR2 is capture the input. */
/**
* @}
*/
/**
* @defgroup TMR2_Clock_Divider TMR2 Clock Divider
* @{
*/
#define TMR2_CLK_DIV1 (0x0U) /*!< Clock source. */
#define TMR2_CLK_DIV2 (TMR2_BCONR_CKDIVA_0) /*!< Clock source / 2. */
#define TMR2_CLK_DIV4 (TMR2_BCONR_CKDIVA_1) /*!< Clock source / 4. */
#define TMR2_CLK_DIV8 (TMR2_BCONR_CKDIVA_1 | \
TMR2_BCONR_CKDIVA_0) /*!< Clock source / 8. */
#define TMR2_CLK_DIV16 (TMR2_BCONR_CKDIVA_2) /*!< Clock source / 16. */
#define TMR2_CLK_DIV32 (TMR2_BCONR_CKDIVA_2 | \
TMR2_BCONR_CKDIVA_0) /*!< Clock source / 32. */
#define TMR2_CLK_DIV64 (TMR2_BCONR_CKDIVA_2 | \
TMR2_BCONR_CKDIVA_1) /*!< Clock source / 64. */
#define TMR2_CLK_DIV128 (TMR2_BCONR_CKDIVA_2 | \
TMR2_BCONR_CKDIVA_1 | \
TMR2_BCONR_CKDIVA_0) /*!< Clock source / 128. */
#define TMR2_CLK_DIV256 (TMR2_BCONR_CKDIVA_3) /*!< Clock source / 256. */
#define TMR2_CLK_DIV512 (TMR2_BCONR_CKDIVA_3 | \
TMR2_BCONR_CKDIVA_0) /*!< Clock source / 512. */
#define TMR2_CLK_DIV1024 (TMR2_BCONR_CKDIVA_3 | \
TMR2_BCONR_CKDIVA_1) /*!< Clock source / 1024. */
/**
* @}
*/
/**
* @defgroup TMR2_Clock_Source TMR2 Clock Source
* @{
*/
#define TMR2_CLK_SYNC_PCLK1 (0x0U) /*!< Synchronous clock source, PCLK1. */
#define TMR2_CLK_SYNC_TRIGR (TMR2_BCONR_SYNCLKA_0) /*!< Synchronous clock source, rising edge of TIM2_x_TRIGA/B. \
One rising edge causes one count. */
#define TMR2_CLK_SYNC_TRIGF (TMR2_BCONR_SYNCLKA_1) /*!< Synchronous clock source, falling edge of TIM2_x_TRIGA/B. \
One falling edge causes one count. */
#define TMR2_CLK_SYNC_EVENT (TMR2_BCONR_SYNCLKA) /*!< Synchronous clock source, peripheral event. The event is specified by register TMR2_HTSSR. \
The event causes one count. */
#define TMR2_CLK_SYNC_TIMER6_OVF (TMR2_BCONR_SYNCLKAT_0) /*!< Synchronous clock source, the event of counting overflow of TIMER6. \
It is NO need to set register TMR2_HTSSR. */
#define TMR2_CLK_SYNC_TIMER6_UDF (TMR2_BCONR_SYNCLKAT_1) /*!< Synchronous clock source, the event of counting underflow of TIMER6. \
It is NO need to set register TMR2_HTSSR. */
#define TMR2_CLK_ASYNC_LRC (TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, LRC(32.768KHz). */
#define TMR2_CLK_ASYNC_XTAL32 (TMR2_BCONR_ASYNCLKA_0 | \
TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, XTAL32(32.768KHz). */
#define TMR2_CLK_ASYNC_PIN_CLK (TMR2_BCONR_ASYNCLKA_1 | \
TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, input from pin TIM2_x_CLKA/B. */
/**
* @}
*/
/**
* @defgroup TMR2_Interrupt_Type TMR2 Interrupt Type
* @{
*/
#define TMR2_INT_CMP (TMR2_ICONR_CMENA) /*!< TMR2 count match interrupt. */
#define TMR2_INT_OVF (TMR2_ICONR_OVENA) /*!< TMR2 count overflow interrupt. */
/**
* @}
*/
/**
* @defgroup TMR2_PWM_Start_Polarity TMR2 PWM Start Polarity
* @{
*/
#define TMR2_PWM_START_LOW (0x0U) /*!< PWM output low when counting start. */
#define TMR2_PWM_START_HIGH (TMR2_PCONR_STACA_0) /*!< PWM output high when counting start. */
#define TMR2_PWM_START_KEEP (TMR2_PCONR_STACA_1) /*!< PWM output keeps the current polarity when counting start. */
/**
* @}
*/
/**
* @defgroup TMR2_PWM_Stop_Polarity TMR2 PWM Stop Polarity
* @{
*/
#define TMR2_PWM_STOP_LOW (0x0U) /*!< PWM output low when counting stop. */
#define TMR2_PWM_STOP_HIGH (TMR2_PCONR_STPCA_0) /*!< PWM output high when counting stop. */
#define TMR2_PWM_STOP_KEEP (TMR2_PCONR_STPCA_1) /*!< PWM output keeps the current polarity when counting stop. */
/**
* @}
*/
/**
* @defgroup TMR2_PWM_Cmp_Polarity TMR2 PWM Polarity When Counting Compare Matches The Compare Value
* @{
*/
#define TMR2_PWM_CMP_LOW (0x0U) /*!< PWM output low when counting match. */
#define TMR2_PWM_CMP_HIGH (TMR2_PCONR_CMPCA_0) /*!< PWM output high when counting match. */
#define TMR2_PWM_CMP_KEEP (TMR2_PCONR_CMPCA_1) /*!< PWM output keeps the current polarity when counting match. */
#define TMR2_PWM_CMP_REVERSE (TMR2_PCONR_CMPCA_1 | \
TMR2_PCONR_CMPCA_0) /*!< PWM output reverses the current polarity when counting match. */
/**
* @}
*/
/**
* @defgroup TMR2_Filter_Clock_Divider TMR2 Filter Clock Divider
* @{
*/
#define TMR2_FILTER_CLK_DIV1 (0x0U) /*!< Clock source. */
#define TMR2_FILTER_CLK_DIV4 (TMR2_PCONR_NOFICKA_0) /*!< Clock source / 4. */
#define TMR2_FILTER_CLK_DIV16 (TMR2_PCONR_NOFICKA_1) /*!< Clock source / 16. */
#define TMR2_FILTER_CLK_DIV64 (TMR2_PCONR_NOFICKA) /*!< Clock source / 64. */
/**
* @}
*/
/**
* @defgroup TMR2_Hardware_Start_Condition TMR2 Hardware Start Condition
* @{
*/
#define TMR2_START_COND_INVALID (0x0U) /*!< The start condition of TMR2 is INVALID. */
#define TMR2_START_COND_TRIGR (TMR2_HCONR_HSTAA0) /*!< The start condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
#define TMR2_START_COND_TRIGF (TMR2_HCONR_HSTAA1) /*!< The start condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
#define TMR2_START_COND_EVENT (TMR2_HCONR_HSTAA2) /*!< The start condition of TMR2 is the specified event occurred. */
/**
* @}
*/
/**
* @defgroup TMR2_Hardware_Stop_Condition TMR2 Hardware Stop Condition
* @{
*/
#define TMR2_STOP_COND_INVALID (0x0U) /*!< The stop condition of TMR2 is INVALID. */
#define TMR2_STOP_COND_TRIGR (TMR2_HCONR_HSTPA0) /*!< The stop condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
#define TMR2_STOP_COND_TRIGF (TMR2_HCONR_HSTPA1) /*!< The stop condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
#define TMR2_STOP_COND_EVENT (TMR2_HCONR_HSTPA2) /*!< The stop condition of TMR2 is the specified event occurred. */
/**
* @}
*/
/**
* @defgroup TMR2_Hardware_Clear_Condition TMR2 Hardware Clear Condition
* @{
*/
#define TMR2_CLR_COND_INVALID (0x0U) /*!< The clear condition of TMR2 is INVALID. */
#define TMR2_CLR_COND_TRIGR (TMR2_HCONR_HCLEA0) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
#define TMR2_CLR_COND_TRIGF (TMR2_HCONR_HCLEA1) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
#define TMR2_CLR_COND_EVENT (TMR2_HCONR_HCLEA2) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the specified event occurred. */
/**
* @}
*/
/**
* @defgroup TMR2_Hardware_Capture_Condition TMR2 Hardware Capture Condition
* @{
*/
#define TMR2_CAPT_COND_INVALID (0x0U) /*!< The capture condition of TMR2 is INVALID. */
#define TMR2_CAPT_COND_TRIGR (TMR2_HCONR_HICPA0) /*!< The capture condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
#define TMR2_CAPT_COND_TRIGF (TMR2_HCONR_HICPA1) /*!< The capture condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
#define TMR2_CAPT_COND_EVENT (TMR2_HCONR_HICPA2) /*!< The capture condition of TMR2 is the specified event occurred. */
/**
* @}
*/
/**
* @defgroup TMR2_State_Flag TMR2 State Flag
* @{
*/
#define TMR2_FLAG_CMP (TMR2_STFLR_CMFA) /*!< Counter match flag. */
#define TMR2_FLAG_OVF (TMR2_STFLR_OVFA) /*!< Counter overflow flag. */
#define TMR2_FLAG_ALL (TMR2_FLAG_CMP | TMR2_FLAG_OVF)
/**
* @}
*/
/**
* @defgroup TMR2_Common_Trigger_Sel TMR2 Common Trigger Source Select
* @{
*/
#define TMR2_COM_TRIG1 (AOS_TMR2_HTSSR_COMTRG_EN_0)
#define TMR2_COM_TRIG2 (AOS_TMR2_HTSSR_COMTRG_EN_1)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup TMR2_Global_Functions
* @{
*/
en_result_t TMR2_Init(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, const stc_tmr2_init_t *pstcInit);
en_result_t TMR2_StructInit(stc_tmr2_init_t *pstcInit);
void TMR2_DeInit(M4_TMR2_TypeDef *TMR2x);
en_result_t TMR2_PWM_Config(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, const stc_tmr2_pwm_cfg_t *pstcCfg);
en_result_t TMR2_PWM_StructInit(stc_tmr2_pwm_cfg_t *pstcCfg);
void TMR2_PWM_Cmd(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, en_functional_state_t enNewState);
en_result_t TMR2_SetTrigCond(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, const stc_tmr2_trig_cond_t *pstcCond);
en_result_t TMR2_TrigCondStructInit(stc_tmr2_trig_cond_t *pstcCond);
void TMR2_SetTriggerSrc(en_event_src_t enEvent);
void TMR2_ComTriggerCmd(uint32_t u32ComTrig, en_functional_state_t enNewState);
void TMR2_FilterConfig(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32ClkDiv);
void TMR2_FilterCmd(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, en_functional_state_t enNewState);
void TMR2_IntCmd(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, \
uint32_t u32IntType, en_functional_state_t enNewState);
void TMR2_Start(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch);
void TMR2_Stop(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch);
en_flag_status_t TMR2_GetStatus(const M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Flag);
void TMR2_ClrStatus(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Flag);
void TMR2_SetCmpVal(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Val);
uint32_t TMR2_GetCmpVal(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch);
void TMR2_SetCntVal(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Val);
uint32_t TMR2_GetCntVal(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch);
void TMR2_SetFuncMode(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32FuncMode);
void TMR2_SetClkSrc(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32ClkSrc);
void TMR2_SetClkDiv(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32ClkDiv);
void TMR2_TrigCondCmd(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Cond, en_functional_state_t enNewState);
void TMR2_PWM_SetStartPolarity(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Polarity);
void TMR2_PWM_SetStopPolarity(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Polarity);
void TMR2_PWM_SetCmpPolarity(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Polarity);
/**
* @}
*/
#endif /* DDL_TMR2_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_TMR2_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_tmr6.h
* @brief Head file for TMR6 module.
*
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Wangmin First version
2020-07-15 Wangmin Refine macro define
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_TMR6_H__
#define __HC32F4A0_TMR6_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_TMR6
* @{
*/
#if (DDL_TMR6_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup TMR6_Global_Types TMR6 Global Types
* @{
*/
/**
* @brief Timer6 base counter function structure definition
*/
typedef struct
{
uint32_t u32CntMode; /*!< Count mode, @ref TMR6_Count_Mode_define */
uint32_t u32CntDir; /*!< Count direction, @ref TMR6_Count_Direction_define */
uint32_t u32CntClkDiv; /*!< Count clock division select, @ref TMR6_Count_Clock_define */
uint32_t u32CntStpAftOvf; /*!< Count stop after overflow @ref TMR6_Count_Stop_After_Overflow_define*/
}stc_tmr6_basecnt_cfg_t;
/**
* @brief Timer6 buffer function configuration structure definition
*/
typedef struct
{
uint32_t u32BufFunCmd; /*!< specifies the buffer function status,
and this parameter can be a value of
@ref TMR6_Buffer_Function_sta_Define */
uint32_t u32BufNum; /*!< specifies the buffer number,
and this parameter can be a value of
@ref TMR6_Buffer_Number_Chose_Define */
uint32_t u32BufTransTim; /*!< specifies the buffer send time,
and this parameter can be a value of
@ref TMR6_Buffer_Transfer_Time_Cfg_Define */
}stc_tmr6_buf_func_cfg_t;
/**
* @brief Timer6 Valid period function configuration structure definition
*/
typedef struct
{
uint32_t u32StatChA; /*!< specifies the valid period function status for channel A,
and this parameter can be a value of
@ref TMR6_Valid_Period_CHA_STAT_Define */
uint32_t u32StatChB; /*!< specifies the valid period function status for channel B,
and this parameter can be a value of
@ref TMR6_Valid_Period_CHB_STAT_Define */
uint32_t u32CntCond; /*!< specifies the count condition,
and this parameter can be a value of
@ref TMR6_Valid_Period_Count_Condition_Define */
uint32_t u32PeriodInterval; /*!< specifies the interval of the valid period,
@ref TMR6_Valid_Period_Count_Define */
}stc_tmr6_valid_period_func_cfg_t;
/**
* @brief Timer6 port input configuration structure definition
*/
typedef struct
{
uint32_t u32PortMode; /*!< Port function mode @ref TMR6_Port_Mode_Func */
uint32_t u32FilterSta; /*!< trig source capture input filter status
@ref TMR6_Port_Input_Filter_Sta*/
uint32_t u32FltClk; /*!< Filter clock @ref TMR6_Input_Port_Filter_Clk*/
}stc_tmr6_port_input_cfg_t;
/**
* @brief Timer6 port output configuration structure definition
*/
typedef struct
{
uint32_t u32PortMode; /*!< Port function mode @ref TMR6_Port_Mode_Func */
uint32_t u32NextPeriodForceSta; /*!< Port State Next period @ref TMR6_Force_Port_Output_Sta */
uint32_t u32DownCntMatchAnotherCmpRegSta; /*!< Port state when counter match another compare register
(CHA matched GCMBR, CHB matched GCMAR) in count-down mode
@ref TMR6_Port_Output_Sta */
uint32_t u32UpCntMatchAnotherCmpRegSta; /*!< Port state when counter match another compare register
(CHA matched GCMBR, CHB matched GCMAR) in count-up mode
@ref TMR6_Port_Output_Sta*/
uint32_t u32DownCntMatchCmpRegSta; /*!< Port state when counter match compare register
(CHA matched GCMAR, CHB matched GCMBR) in count-down mode
@ref TMR6_Port_Output_Sta */
uint32_t u32UpCntMatchCmpRegSta; /*!< Port state when counter match compare register
(CHA matched GCMAR, CHB matched GCMBR) in count-up mode
@ref TMR6_Port_Output_Sta */
uint32_t u32UnderflowSta; /*!< Port State when counter underflow @ref TMR6_Port_Output_Sta */
uint32_t u32OverflowSta; /*!< Port State when counter overflow @ref TMR6_Port_Output_Sta */
uint32_t u32StopSta; /*!< Port State when count stop @ref TMR6_Port_Output_Sta */
uint32_t u32StartSta; /*!< Port State when count start @ref TMR6_Port_Output_Sta */
}stc_tmr6_port_output_cfg_t;
/**
* @brief Timer6 EMB configuration structure definition
*/
typedef struct
{
uint32_t u32ValidCh; /*!< Valid EMB event channel @ref TMR6_Emb_channel */
uint32_t u32ReleaseMode; /*!< Port release mode when EMB event invalid @ref TMR6_Emb_Release_Mode */
uint32_t u32PortSta; /*!< Port Output status when EMB event valid @ref TMR6_Emb_Port_Sta */
}stc_tmr6_emb_cfg_t;
/**
* @brief Timer6 Dead time function configuration structure definition
*/
typedef struct
{
uint32_t u32DtEqualUpDwn; /*!< Enable down count dead time register equal to up count DT register
@ref TMR6_Deadtime_Reg_Equal_Func_define */
uint32_t u32EnDtBufUp; /*!< Enable buffer transfer for up count dead time register
(DTUBR-->DTUAR) @ref TMR6_Deadtime_CountUp_Buf_Func_define*/
uint32_t u32EnDtBufDwn; /*!< Enable buffer transfer for down count dead time register
(DTDBR-->DTDAR) @ref TMR6_Deadtime_CountDown_Buf_Func_define*/
uint32_t u32DtUpdCond; /*!< Buffer transfer condition for triangular wave mode
@ref TMR6_Deadtime_Buf_Transfer_Condition_define */
}stc_tmr6_deadtime_cfg_t;
/**
* @brief Timer6 Dead time function configuration structure definition
*/
typedef struct
{
uint32_t u32ZMaskCycle; /*!< Z phase input mask periods selection @ref TMR6_Zmask_Cycle_define*/
uint32_t u32PosCntMaskEn; /*!< As position count timer, clear function enable(TRUE) or disable(FALSE)
during the time of Z phase input mask @ref TMR6_Zmask_Position_Unit_Clear_Func_define*/
uint32_t u32RevCntMaskEn; /*!< As revolution count timer, the counter function enable(TRUE) or
disable(FALSE) during the time of Z phase input mask @ref TMR6_Zmask_Revolution_Unit_Count_Func_define*/
}stc_tmr6_zmask_cfg_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup TMR6_Global_Macros TMR6 Global Macros
* @{
*/
/** @defgroup TMR6_Sta_Bit_Get_Define TMR6 status bit define
* @{
*/
/* Status bit indicate that GCMAR register matched with counter register */
#define TMR6_STAT_CNT_MATCH_A (TMR6_STFLR_CMAF)
/* Status bit indicate that GCMBR register matched with counter register */
#define TMR6_STAT_CNT_MATCH_B (TMR6_STFLR_CMBF)
/* Status bit indicate that GCMCR register matched with counter register */
#define TMR6_STAT_CNT_MATCH_C (TMR6_STFLR_CMCF)
/* Status bit indicate that GCMDR register matched with counter register */
#define TMR6_STAT_CNT_MATCH_D (TMR6_STFLR_CMDF)
/* Status bit indicate that GCMER register matched with counter register */
#define TMR6_STAT_CNT_MATCH_E (TMR6_STFLR_CMEF)
/* Status bit indicate that GCMFR register matched with counter register */
#define TMR6_STAT_CNT_MATCH_F (TMR6_STFLR_CMFF)
/* Status bit indicate that counter register overflow */
#define TMR6_STAT_OVERFLOW (TMR6_STFLR_OVFF)
/* Status bit indicate that counter register underflow */
#define TMR6_STAT_UNDERFLOW (TMR6_STFLR_UDFF)
/* Status bit indicate that dead time error */
#define TMR6_STAT_DEAD_TIME_ERR (TMR6_STFLR_DTEF)
/* Status bit indicate that SCMAR register matched with counter register during count-up */
#define TMR6_STAT_UPCNT_SP_MATCH_A (TMR6_STFLR_CMSAUF)
/* Status bit indicate that SCMAR register matched with counter register during count-down */
#define TMR6_STAT_DOWNCNT_SP_MATCH_A (TMR6_STFLR_CMSADF)
/* Status bit indicate that SCMBR register matched with counter register during count-up */
#define TMR6_STAT_UPCNT_SP_MATCH_B (TMR6_STFLR_CMSBUF)
/* Status bit indicate that SCMBR register matched with counter register during count-down */
#define TMR6_STAT_DOWNCNT_SP_MATCH_B (TMR6_STFLR_CMSBDF)
/* Counter direction flag */
#define TMR6_STAT_CNT_DIR (TMR6_STFLR_DIRF)
/**
* @}
*/
/** @defgroup TMR6_Interrupt_Enable_Bit_Define TMR6 interrupt configuration bit define
* @{
*/
/* Interrupt enable bit for GCMAR register matched */
#define TMR6_IRQ_EN_CNT_MATCH_A (TMR6_ICONR_INTENA)
/* Interrupt enable bit for GCMBR register matched */
#define TMR6_IRQ_EN_CNT_MATCH_B (TMR6_ICONR_INTENB)
/* Interrupt enable bit for GCMCR register matched */
#define TMR6_IRQ_EN_CNT_MATCH_C (TMR6_ICONR_INTENC)
/* Interrupt enable bit for GCMDR register matched */
#define TMR6_IRQ_EN_CNT_MATCH_D (TMR6_ICONR_INTEND)
/* Interrupt enable bit for GCMER register matched */
#define TMR6_IRQ_EN_CNT_MATCH_E (TMR6_ICONR_INTENE)
/* Interrupt enable bit for GCMFR register matched */
#define TMR6_IRQ_EN_CNT_MATCH_F (TMR6_ICONR_INTENF)
/* Interrupt enable bit for counter register overflow */
#define TMR6_IRQ_EN_OVERFLOW (TMR6_ICONR_INTENOVF)
/* Interrupt enable bit for counter register underflow */
#define TMR6_IRQ_EN_UNDERFLOW (TMR6_ICONR_INTENUDF)
/* Interrupt enable bit for dead time */
#define TMR6_IRQ_EN_DEAD_TIME_ERR (TMR6_ICONR_INTENDTE)
/* Interrupt enable bit for SCMAR register matched during count-up*/
#define TMR6_IRQ_EN_UPCNT_SP_MATCH_A (TMR6_ICONR_INTENSAU)
/* Interrupt enable bit for SCMAR register matched during count-down*/
#define TMR6_IRQ_EN_DOWNCNT_SP_MATCH_A (TMR6_ICONR_INTENSAD)
/* Interrupt enable bit for SCMBR register matched during count-up*/
#define TMR6_IRQ_EN_UPCNT_SP_MATCH_B (TMR6_ICONR_INTENSBU)
/* Interrupt enable bit for SCMBR register matched during count-down*/
#define TMR6_IRQ_EN_DOWNCNT_SP_MATCH_B (TMR6_ICONR_INTENSBD)
/**
* @}
*/
/** @defgroup TMR6_Period_Register_Index_Define TMR6 period register Index define
* @{
*/
#define TMR6_PERIOD_REG_A (0x00UL)
#define TMR6_PERIOD_REG_B (0x01UL)
#define TMR6_PERIOD_REG_C (0x02UL)
/**
* @}
*/
/** @defgroup TMR6_Compare_Register_Index_Define TMR6 compare register Index define
* @{
*/
#define TMR6_CMP_REG_A (0x00UL)
#define TMR6_CMP_REG_B (0x01UL)
#define TMR6_CMP_REG_C (0x02UL)
#define TMR6_CMP_REG_D (0x03UL)
#define TMR6_CMP_REG_E (0x04UL)
#define TMR6_CMP_REG_F (0x05UL)
/**
* @}
*/
/** @defgroup TMR6_Compare_channel_Define TMR6 general/special compare channel index define
* @{
*/
#define TMR6_CH_A (0x00UL)
#define TMR6_CH_B (0x01UL)
/**
* @}
*/
/** @defgroup TMR6_Buffer_Function_sta_Define TMR6 buffer function status define
* @{
*/
#define TMR6_BUF_FUNC_OFF (0x00000000UL)
#define TMR6_BUF_FUNC_ON (TMR6_BCONR_BENA)
/**
* @}
*/
/** @defgroup TMR6_Buffer_Number_Chose_Define TMR6 buffer number configuration define
* @{
*/
#define TMR6_BUF_FUNC_SINGLE (0x00000000UL)
#define TMR6_BUF_FUNC_DOUBLE (TMR6_BCONR_BSEA)
/**
* @}
*/
/** @defgroup TMR6_Buffer_Transfer_Time_Cfg_Define TMR6 buffer transfer time configuration define
* @{
*/
#define TMR6_BUF_TRANS_TIM_NONE (0x00000000UL)
#define TMR6_BUF_TRANS_TIM_OVERFLOW (TMR6_BCONR_BTRUA)
#define TMR6_BUF_TRANS_TIM_UNDERFLOW (TMR6_BCONR_BTRDA)
#define TMR6_BUF_TRANS_TIM_BOTH (TMR6_BCONR_BTRUA | TMR6_BCONR_BTRDA)
/**
* @}
*/
/** @defgroup TMR6_Valid_Period_Count_Condition_Define TMR6 valid period function count condition define
* @{
*/
/* Valid period function off */
#define TMR6_VALID_PERIOD_FUNC_OFF (0x00000000UL)
/* Counted when Sawtooth waveform overflow and underflow, triangular wave underflow */
#define TMR6_VALID_PERIOD_CNT_COND_UNDERFLOW (TMR6_VPERR_PCNTE_0)
/* Counted when Sawtooth waveform overflow and underflow, triangular wave overflow */
#define TMR6_VALID_PERIOD_CNT_COND_OVERFLOW (TMR6_VPERR_PCNTE_1)
/* Counted when Sawtooth waveform overflow and underflow, triangular wave overflow and underflow */
#define TMR6_VALID_PERIOD_CNT_COND_BOTH (TMR6_VPERR_PCNTE_0 | TMR6_VPERR_PCNTE_1)
/**
* @}
*/
/** @defgroup TMR6_Valid_Period_Count_Define TMR6 valid period function count define
* @{
*/
/* Valid period count function invalid */
#define TMR6_VALID_PERIOD_CNT_INVALID (0x00000000UL)
/* Interrupt and event valid every other 1 period */
#define TMR6_VALID_PERIOD_CNT_1 (TMR6_VPERR_PCNTS_0)
/* Interrupt and event valid every other 2 period */
#define TMR6_VALID_PERIOD_CNT_2 (TMR6_VPERR_PCNTS_1)
/* Interrupt and event valid every other 3 period */
#define TMR6_VALID_PERIOD_CNT_3 (TMR6_VPERR_PCNTS_0 | TMR6_VPERR_PCNTS_1)
/* Interrupt and event valid every other 4 period */
#define TMR6_VALID_PERIOD_CNT_4 (TMR6_VPERR_PCNTS_2)
/* Interrupt and event valid every other 5 period */
#define TMR6_VALID_PERIOD_CNT_5 (TMR6_VPERR_PCNTS_2 | TMR6_VPERR_PCNTS_0)
/* Interrupt and event valid every other 6 period */
#define TMR6_VALID_PERIOD_CNT_6 (TMR6_VPERR_PCNTS_2 | TMR6_VPERR_PCNTS_1)
/* Interrupt and event valid every other 7 period */
#define TMR6_VALID_PERIOD_CNT_7 (TMR6_VPERR_PCNTS_2 | TMR6_VPERR_PCNTS_1 | TMR6_VPERR_PCNTS_0)
/**
* @}
*/
/** @defgroup TMR6_Valid_Period_CHA_STAT_Define TMR6 valid period function channel A status define
* @{
*/
#define TMR6_VALID_PERIOD_FUNC_CHA_OFF (0x00000000UL)
#define TMR6_VALID_PERIOD_FUNC_CHA_ON (TMR6_VPERR_SPPERIA)
/**
* @}
*/
/** @defgroup TMR6_Valid_Period_CHB_STAT_Define TMR6 valid period function channel B status define
* @{
*/
#define TMR6_VALID_PERIOD_FUNC_CHB_OFF (0x00000000UL)
#define TMR6_VALID_PERIOD_FUNC_CHB_ON (TMR6_VPERR_SPPERIB)
/**
* @}
*/
/** @defgroup TMR6_DeadTime_Reg_Define TMR6 dead time register define
* @{
*/
/* Register DTUAR */
#define TMR6_DEADTIME_REG_UP_A (0x00U)
/* Register DTDAR */
#define TMR6_DEADTIME_REG_DOWN_A (0x01U)
/* Register DTUBR */
#define TMR6_DEADTIME_REG_UP_B (0x02U)
/* Register DTDBR */
#define TMR6_DEADTIME_REG_DOWN_B (0x03U)
/**
* @}
*/
/** @defgroup TMR6_Port_Define TMR6 input and output port define
* @{
*/
/* port TIM6_<t>_PWMA */
#define TMR6_IO_PWMA (0x00U)
/* port TIM6_<t>_PWMB */
#define TMR6_IO_PWMB (0x01U)
/* Input port TIM6_TRIGA */
#define TMR6_INPUT_TRIGA (0x02U)
/* Input port TIM6_TRIGB */
#define TMR6_INPUT_TRIGB (0x03U)
/* Input port TIM6_TRIGC */
#define TMR6_INPUT_TRIGC (0x04U)
/* Input port TIM6_TRIGD */
#define TMR6_INPUT_TRIGD (0x05U)
/**
* @}
*/
/** @defgroup TMR6_Input_Port_Filter_Clk TMR6 input port define
* @{
*/
#define TMR6_INPUT_FILTER_PCLK0_DIV1 (0x00U)
#define TMR6_INPUT_FILTER_PCLK0_DIV4 (0x01U)
#define TMR6_INPUT_FILTER_PCLK0_DIV16 (0x02U)
#define TMR6_INPUT_FILTER_PCLK0_DIV64 (0x03U)
/**
* @}
*/
/** @defgroup TMR6_Port_Mode_Func TMR6 port function mode selection
* @{
*/
#define TMR6_PORT_COMPARE_OUTPUT (0x00U)
#define TMR6_PORT_CAPTURE_INPUT (TMR6_PCNAR_CAPMDA)
/**
* @}
*/
/** @defgroup TMR6_Port_Input_Filter_Sta TMR6 port input filter function status
* @{
*/
#define TMR6_PORT_INPUT_FILTER_OFF (0x00U)
#define TMR6_PORT_INPUT_FILTER_ON (0x01U)
/**
* @}
*/
/** @defgroup TMR6_Port_Output_Sta TMR6 port output status
* @{
*/
#define TMR6_PORT_OUTPUT_STA_LOW (0x00U)
#define TMR6_PORT_OUTPUT_STA_HIGH (0x01U)
#define TMR6_PORT_OUTPUT_STA_HOLD (0x02U)
#define TMR6_PORT_OUTPUT_STA_REVERSE (0x03U)
/**
* @}
*/
/** @defgroup TMR6_Force_Port_Output_Sta TMR6 force port output status next period
* @{
*/
#define TMR6_FORCE_PORT_OUTPUT_INVALID (0x00U)
#define TMR6_FORCE_PORT_OUTPUT_STA_LOW (0x02U)
#define TMR6_FORCE_PORT_OUTPUT_STA_HIGH (0x03U)
/**
* @}
*/
/** @defgroup TMR6_Emb_channel TMR6 EMB event valid channel
* @{
*/
#define TMR6_EMB_EVENT_VALID_CH0 (0x00U)
#define TMR6_EMB_EVENT_VALID_CH1 (TMR6_PCNAR_EMBSA_0)
#define TMR6_EMB_EVENT_VALID_CH2 (TMR6_PCNAR_EMBSA_1)
#define TMR6_EMB_EVENT_VALID_CH3 (TMR6_PCNAR_EMBSA_0 | TMR6_PCNAR_EMBSA_1)
/**
* @}
*/
/** @defgroup TMR6_Emb_Release_Mode TMR6 EMB function release mode when EMB event invalid
* @{
*/
#define TMR6_EMB_RELEASE_IMMEDIATE (0x00U)
#define TMR6_EMB_RELEASE_OVERFLOW (TMR6_PCNAR_EMBRA_0)
#define TMR6_EMB_RELEASE_UNDERFLOW (TMR6_PCNAR_EMBRA_1)
#define TMR6_EMB_RELEASE_OVERFLOW_UNDERFLOW (TMR6_PCNAR_EMBRA_0 | TMR6_PCNAR_EMBRA_1)
/**
* @}
*/
/** @defgroup TMR6_Emb_Port_Sta TMR6 EMB port output status when EMB event valid
* @{
*/
#define TMR6_EMB_PORTSTA_NORMAL (0x00U)
#define TMR6_EMB_PORTSTA_HIZ (TMR6_PCNAR_EMBCA_0)
#define TMR6_EMB_PORTSTA_LOW (TMR6_PCNAR_EMBCA_1)
#define TMR6_EMB_PORTSTA_HIGH (TMR6_PCNAR_EMBCA_0 | TMR6_PCNAR_EMBCA_1)
/**
* @}
*/
/** @defgroup TMR6_Deadtime_CountUp_Buf_Func_define TMR6 Dead time buffer function for count up stage
* @{
*/
#define TMR6_DEADTIME_CNT_UP_BUF_OFF (0x00U)
#define TMR6_DEADTIME_CNT_UP_BUF_ON (TMR6_DCONR_DTBENU)
/**
* @}
*/
/** @defgroup TMR6_Deadtime_CountDown_Buf_Func_define TMR6 Dead time buffer function for count down stage
* @{
*/
#define TMR6_DEADTIME_CNT_DOWN_BUF_OFF (0x00U)
#define TMR6_DEADTIME_CNT_DOWN_BUF_ON (TMR6_DCONR_DTBEND)
/**
* @}
*/
/** @defgroup TMR6_Deadtime_Buf_Transfer_Condition_define TMR6 Dead time buffer transfer condition define for triangular count mode
* @{
*/
#define TMR6_DEADTIME_TRANS_COND_NONE (0x00U)
#define TMR6_DEADTIME_TRANS_COND_OVERFLOW (TMR6_DCONR_DTBTRU)
#define TMR6_DEADTIME_TRANS_COND_UNDERFLOW (TMR6_DCONR_DTBTRD)
#define TMR6_DEADTIME_TRANS_COND_BOTH (TMR6_DCONR_DTBTRU | TMR6_DCONR_DTBTRD)
/**
* @}
*/
/** @defgroup TMR6_Deadtime_Reg_Equal_Func_define TMR6 Dead time function DTDAR equal DTUAR
* @{
*/
#define TMR6_DEADTIME_EQUAL_OFF (0x00U)
#define TMR6_DEADTIME_EQUAL_ON (TMR6_DCONR_SEPA)
/**
* @}
*/
/** @defgroup TMR6_Soft_Sync_Ctrl_Unit_Number_define TMR6 Software synchronization start/stop/clear/update unit number define
* @{
*/
#define TMR6_SOFT_SYNC_CTRL_U1 (TMR6_SSTAR_SSTA1)
#define TMR6_SOFT_SYNC_CTRL_U2 (TMR6_SSTAR_SSTA2)
#define TMR6_SOFT_SYNC_CTRL_U3 (TMR6_SSTAR_SSTA3)
#define TMR6_SOFT_SYNC_CTRL_U4 (TMR6_SSTAR_SSTA4)
#define TMR6_SOFT_SYNC_CTRL_U5 (TMR6_SSTAR_SSTA5)
#define TMR6_SOFT_SYNC_CTRL_U6 (TMR6_SSTAR_SSTA6)
#define TMR6_SOFT_SYNC_CTRL_U7 (TMR6_SSTAR_SSTA7)
#define TMR6_SOFT_SYNC_CTRL_U8 (TMR6_SSTAR_SSTA8)
/**
* @}
*/
/** @defgroup TMR6_hardware_control_event_define TMR6 hardware start/stop/clear/update/capture events define
* @{
*/
#define TMR6_HW_CTRL_PWMA_RISING (TMR6_HSTAR_HSTA0)
#define TMR6_HW_CTRL_PWMA_FAILLING (TMR6_HSTAR_HSTA1)
#define TMR6_HW_CTRL_PWMB_RISING (TMR6_HSTAR_HSTA2)
#define TMR6_HW_CTRL_PWMB_FAILLING (TMR6_HSTAR_HSTA3)
#define TMR6_HW_CTRL_INTER_EVENT0 (TMR6_HSTAR_HSTA8)
#define TMR6_HW_CTRL_INTER_EVENT1 (TMR6_HSTAR_HSTA9)
#define TMR6_HW_CTRL_INTER_EVENT2 (TMR6_HSTAR_HSTA10)
#define TMR6_HW_CTRL_INTER_EVENT3 (TMR6_HSTAR_HSTA11)
#define TMR6_HW_CTRL_TRIGEA_RISING (TMR6_HSTAR_HSTA16)
#define TMR6_HW_CTRL_TRIGEA_FAILLING (TMR6_HSTAR_HSTA17)
#define TMR6_HW_CTRL_TRIGEB_RISING (TMR6_HSTAR_HSTA18)
#define TMR6_HW_CTRL_TRIGEB_FAILLING (TMR6_HSTAR_HSTA19)
#define TMR6_HW_CTRL_TRIGEC_RISING (TMR6_HSTAR_HSTA20)
#define TMR6_HW_CTRL_TRIGEC_FAILLING (TMR6_HSTAR_HSTA21)
#define TMR6_HW_CTRL_TRIGED_RISING (TMR6_HSTAR_HSTA22)
#define TMR6_HW_CTRL_TRIGED_FAILLING (TMR6_HSTAR_HSTA23)
/**
* @}
*/
/** @defgroup TMR6_hardware_count_event_define TMR6 hardware increase/decrease events define
* @{
*/
#define TMR6_HW_CNT_PWMAL_PWMBRISING (TMR6_HCUPR_HCUP0)
#define TMR6_HW_CNT_PWMAL_PWMBFAILLING (TMR6_HCUPR_HCUP1)
#define TMR6_HW_CNT_PWMAH_PWMBRISING (TMR6_HCUPR_HCUP2)
#define TMR6_HW_CNT_PWMAH_PWMBFAILLING (TMR6_HCUPR_HCUP3)
#define TMR6_HW_CNT_PWMBL_PWMARISING (TMR6_HCUPR_HCUP4)
#define TMR6_HW_CNT_PWMBL_PWMAFAILLING (TMR6_HCUPR_HCUP5)
#define TMR6_HW_CNT_PWMBH_PWMARISING (TMR6_HCUPR_HCUP6)
#define TMR6_HW_CNT_PWMBH_PWMAFAILLING (TMR6_HCUPR_HCUP7)
#define TMR6_HW_CNT_INTER_EVENT0 (TMR6_HCUPR_HCUP8)
#define TMR6_HW_CNT_INTER_EVENT1 (TMR6_HCUPR_HCUP9)
#define TMR6_HW_CNT_INTER_EVENT2 (TMR6_HCUPR_HCUP10)
#define TMR6_HW_CNT_INTER_EVENT3 (TMR6_HCUPR_HCUP11)
#define TMR6_HW_CNT_TRIGEA_RISING (TMR6_HCUPR_HCUP16)
#define TMR6_HW_CNT_TRIGEA_FAILLING (TMR6_HCUPR_HCUP17)
#define TMR6_HW_CNT_TRIGEB_RISING (TMR6_HCUPR_HCUP18)
#define TMR6_HW_CNT_TRIGEB_FAILLING (TMR6_HCUPR_HCUP19)
#define TMR6_HW_CNT_TRIGEC_RISING (TMR6_HCUPR_HCUP20)
#define TMR6_HW_CNT_TRIGEC_FAILLING (TMR6_HCUPR_HCUP21)
#define TMR6_HW_CNT_TRIGED_RISING (TMR6_HCUPR_HCUP22)
#define TMR6_HW_CNT_TRIGED_FAILLING (TMR6_HCUPR_HCUP23)
/**
* @}
*/
/** @defgroup TMR6_Count_Direction_define TMR6 base counter function direction define
* @{
*/
#define TMR6_CNT_INCREASE (TMR6_GCONR_DIR)
#define TMR6_CNT_DECREASE (0x00U)
/**
* @}
*/
/** @defgroup TMR6_Count_Mode_define TMR6 base counter function mode define
* @{
*/
#define TMR6_MODE_SAWTOOTH (0x00U)
#define TMR6_MODE_TRIANGLE (TMR6_GCONR_MODE)
/**
* @}
*/
/** @defgroup TMR6_Count_Clock_define TMR6 base counter clock source define
* @{
*/
#define TMR6_CLK_PCLK0_DIV1 (0x00UL)
#define TMR6_CLK_PCLK0_DIV2 (0x01UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_PCLK0_DIV4 (0x02UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_PCLK0_DIV8 (0x03UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_PCLK0_DIV16 (0x04UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_PCLK0_DIV32 (0x05UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_PCLK0_DIV64 (0x06UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_PCLK0_DIV128 (0x07UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_PCLK0_DIV256 (0x08UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_PCLK0_DIV512 (0x09UL << TMR6_GCONR_CKDIV_POS)
#define TMR6_CLK_PCLK0_DIV1024 (0x0AUL << TMR6_GCONR_CKDIV_POS)
/**
* @}
*/
/** @defgroup TMR6_Count_Stop_After_Overflow_define TMR6 count stop after overflow function define
* @{
*/
#define TMR6_CNT_CONTINUOUS (0x00U)
#define TMR6_STOP_AFTER_OVF (TMR6_GCONR_OVSTP)
/**
* @}
*/
/** @defgroup TMR6_Zmask_Cycle_define TMR6 Z Mask input function mask cycles number define
* @{
*/
#define TMR6_ZMASK_CYCLE_FUNC_INVALID (0x00U)
#define TMR6_ZMASK_CYCLE_4 (TMR6_GCONR_ZMSKVAL_0)
#define TMR6_ZMASK_CYCLE_8 (TMR6_GCONR_ZMSKVAL_1)
#define TMR6_ZMASK_CYCLE_16 (TMR6_GCONR_ZMSKVAL_0 | TMR6_GCONR_ZMSKVAL_1)
/**
* @}
*/
/** @defgroup TMR6_Zmask_Position_Unit_Clear_Func_define TMR6 unit as position timer, z phase input mask function define for clear action
* @{
*/
#define TMR6_POS_CLR_ZMASK_FUNC_INVALID (0x00U)
#define TMR6_POS_CLR_ZMASK_FUNC_VALID (TMR6_GCONR_ZMSKPOS)
/**
* @}
*/
/** @defgroup TMR6_Zmask_Revolution_Unit_Count_Func_define TMR6 unit as revolution timer, z phase input mask function define for count action
* @{
*/
#define TMR6_REVO_CNT_ZMASK_FUNC_INVALID (0x00U)
#define TMR6_REVO_CNT_ZMASK_FUNC_VALID (TMR6_GCONR_ZMSKREV)
/**
* @}
*/
/** @defgroup TMR6_Hardware_Trigger_Index_define TMR6 hardware trigger index define
* @{
*/
#define TMR6_HW_TRIG_0 (0x00U)
#define TMR6_HW_TRIG_1 (0x01U)
#define TMR6_HW_TRIG_2 (0x02U)
#define TMR6_HW_TRIG_3 (0x03U)
/**
* @}
*/
/** @defgroup TMR6_Common_Trigger_Source_Cfg_define TMR6 common Trigger Source Config
* @{
*/
#define TMR6_COM_TRIG1 (AOS_TMR6_HTSSR_COMTRG_EN_0)
#define TMR6_COM_TRIG2 (AOS_TMR6_HTSSR_COMTRG_EN_1)
#define TMR6_COM_TRIG_MASK (AOS_TMR6_HTSSR_COMTRG_EN)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup TMR6_Global_Functions
* @{
*/
/**
* @brief Get Software Sync start status
* @param None
* @retval An uint32_t data indicate the read status.
*/
__STATIC_INLINE uint32_t TMR6_GetSwSyncStaState(void)
{
return READ_REG32(M4_TMR6_1->SSTAR);
}
/* TMR6 interrupt request enable or disable */
void TMR6_IntCmd(M4_TMR6_TypeDef *TMR6x, uint32_t u32Tmr6Irq, en_functional_state_t enNewState);
/* Get Timer6 status flag */
en_flag_status_t TMR6_GetSta(const M4_TMR6_TypeDef *TMR6x, uint32_t u32StaBit);
/* Get Timer6 period number when valid period function enable */
uint32_t TMR6_GetPeriodNum(const M4_TMR6_TypeDef *TMR6x);
/* De-initialize the timer6 unit */
void TMR6_DeInit(M4_TMR6_TypeDef *TMR6x);
/* Initialize the timer6 unit */
en_result_t TMR6_Init(M4_TMR6_TypeDef *TMR6x, const stc_tmr6_basecnt_cfg_t* pstcTmr6BaseCntCfg);
/* Timer6 counter function command */
void TMR6_CountCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
/* Timer6 counter register set */
void TMR6_SetCntReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32Value);
/* Timer6 update register set */
void TMR6_SetUpdateReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32Value);
/* Timer6 set period register(A~C) */
void TMR6_SetPeriodReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32PeriodReg, uint32_t u32PeriodVal);
/* Timer6 set general compare register(A~F) */
void TMR6_SetGenCmpReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32GenCmpReg, uint32_t u32CmpVal);
/* Timer6 set special compare register(A~F) */
void TMR6_SetSpecialCmpReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32SpecialCmpReg, uint32_t u32CmpVal);
/* Timer6 set dead time registerr */
void TMR6_SetDeadTimeReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32DeadTimeReg, uint32_t u32CmpVal);
/* Timer6 get counter register value */
uint32_t TMR6_GetCntReg(const M4_TMR6_TypeDef *TMR6x);
/* Timer6 get update register value */
uint32_t TMR6_GetUpdateReg(const M4_TMR6_TypeDef *TMR6x);
/* Timer6 Get period register(A~C) */
uint32_t TMR6_GetPeriodReg(const M4_TMR6_TypeDef *TMR6x, uint32_t u32PeriodReg);
/* Timer6 get general compare registers value(A~F) */
uint32_t TMR6_GetGenCmpReg(const M4_TMR6_TypeDef *TMR6x, uint32_t u32GenCmpReg);
/* Timer6 get special compare registers value(A~F) */
uint32_t TMR6_GetSpecialCmpReg(const M4_TMR6_TypeDef *TMR6x, uint32_t u32SpecialCmpReg);
/* Timer6 get dead time register */
uint32_t TMR6_GetDeadTimeReg(const M4_TMR6_TypeDef *TMR6x, uint32_t u32DeadTimeReg);
/* Timer6 general compare buffer function configuration */
en_result_t TMR6_GenCmpBufCfg(M4_TMR6_TypeDef *TMR6x, uint32_t u32CmpChIdx, const stc_tmr6_buf_func_cfg_t* pstcGenBufCfg);
/* Timer6 special compare buffer function configuration */
en_result_t TMR6_SpecialCmpBufCfg(M4_TMR6_TypeDef *TMR6x, uint32_t u32CmpChIdx, const stc_tmr6_buf_func_cfg_t* pstcSpecialBufCfg);
/* Timer6 period buffer function configuration */
en_result_t TMR6_PeriodBufCfg(M4_TMR6_TypeDef *TMR6x, const stc_tmr6_buf_func_cfg_t* pstcPeriodBufCfg);
/* Timer6 valid period function configuration for special compare function */
en_result_t TMR6_ValidPeriodCfg(M4_TMR6_TypeDef *TMR6x, const stc_tmr6_valid_period_func_cfg_t* pstcValidPeriodCfg);
/* Port input configuration(Trig) */
en_result_t TMR6_PortInputConfig(M4_TMR6_TypeDef *TMR6x,
uint32_t u32PortSel,
const stc_tmr6_port_input_cfg_t* pstcTmr6PortInputCfg);
/* Port output configuration(Trig) */
en_result_t TMR6_PortOutputConfig(M4_TMR6_TypeDef *TMR6x,
uint32_t u32PortSel,
const stc_tmr6_port_output_cfg_t* pstcTmr6PortOutputCfg);
/* EMB function configuration */
en_result_t TMR6_EMBConfig(M4_TMR6_TypeDef *TMR6x,
uint32_t u32PortSel,
const stc_tmr6_emb_cfg_t* pstcTmr6EmbCfg);
/* Timer6 dead time function command */
void TMR6_DeadTimeFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
/* DeadTime function configuration */
en_result_t TMR6_DeadTimeCfg(M4_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_cfg_t* pstcTmr6DTCfg);
/* Timer6 unit Z phase input mask config */
en_result_t TMR6_ZMaskCfg(M4_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_cfg_t* pstcTmr6ZMaskCfg);
/* Software Sync Start */
void TMR6_SwSyncStart(uint32_t u32UnitCombine);
/* Software Sync Stop */
void TMR6_SwSyncStop(uint32_t u32UnitCombine);
/* Software Sync clear */
void TMR6_SwSyncClr(uint32_t u32UnitCombine);
/* Software Sync update */
void TMR6_SwSyncUpdate(uint32_t u32UnitCombine);
/* Hardware start function command */
void TMR6_HwStartFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
/* Hardware stop function command */
void TMR6_HwStopFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
/* Hardware clear function command */
void TMR6_HwClrFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
/* Hardware update function command */
void TMR6_HwUpdateFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
/* Hardware start condtion command */
void TMR6_HwStartCondCmd(M4_TMR6_TypeDef *TMR6x,
uint32_t u32CondSrc,
en_functional_state_t enNewState);
/* Hardware stop condtion command */
void TMR6_HwStopCondCmd(M4_TMR6_TypeDef *TMR6x,
uint32_t u32CondSrc,
en_functional_state_t enNewState);
/* Hardware clear condtion command */
void TMR6_HwClrCondCmd(M4_TMR6_TypeDef *TMR6x,
uint32_t u32CondSrc,
en_functional_state_t enNewState);
/* Hardware update condtion command */
void TMR6_HwUpdCondCmd(M4_TMR6_TypeDef *TMR6x,
uint32_t u32CondSrc,
en_functional_state_t enNewState);
/* Hardware capture condtion command for channel A */
void TMR6_HwCaptureChACondCmd(M4_TMR6_TypeDef *TMR6x,
uint32_t u32CondSrc,
en_functional_state_t enNewState);
/* Hardware capture condtion command for channel B */
void TMR6_HwCaptureChBCondCmd(M4_TMR6_TypeDef *TMR6x,
uint32_t u32CondSrc,
en_functional_state_t enNewState);
/* Hardware increase conditon command */
void TMR6_HwIncreaseCondCmd(M4_TMR6_TypeDef *TMR6x,
uint32_t u32CondSrc,
en_functional_state_t enNewState);
/* Hardware decrease conditon command */
void TMR6_HwDecreaseCondCmd(M4_TMR6_TypeDef *TMR6x,
uint32_t u32CondSrc,
en_functional_state_t enNewState);
/* Hardware start function condition clear */
void TMR6_HwStartCondClr(M4_TMR6_TypeDef *TMR6x);
/* Hardware stop function condition clear */
void TMR6_HwStopCondClr(M4_TMR6_TypeDef *TMR6x);
/* Hardware clear function condition clear */
void TMR6_HwClrCondClr(M4_TMR6_TypeDef *TMR6x);
/* Hardware update function condition clear */
void TMR6_HwUpdCondClr(M4_TMR6_TypeDef *TMR6x);
/* Hardware capture condition clear for channel A */
void TMR6_HwCaptureChACondClr(M4_TMR6_TypeDef *TMR6x);
/* Hardware capture condition clear for channel B */
void TMR6_HwCaptureChBCondClr(M4_TMR6_TypeDef *TMR6x);
/* Hardware increase condition clear */
void TMR6_HwIncreaseCondClr(M4_TMR6_TypeDef *TMR6x);
/* Hardware decrease condition clear */
void TMR6_HwDecreaseCondClr(M4_TMR6_TypeDef *TMR6x);
/* Timer6 Hardware trigger event configuration for(trigger0~trigger3) */
void TMR6_SetTriggerSrc(uint32_t u32TrigIndex, en_event_src_t enEvent);
/* Timer6 Hardware trigger common event function command for(trigger0~trigger3) */
void TMR6_ComTriggerCmd(uint32_t u32TrigIndex, uint32_t u32ComTrig, en_functional_state_t enNewState);
/* Set the fields of structure stc_timer4_pwm_init_t to default values */
en_result_t TMR6_BaseCntStructInit(stc_tmr6_basecnt_cfg_t *pstcInit);
/* Set the fields of structure stc_tmr6_buf_func_cfg_t to default values */
en_result_t TMR6_BufFuncStructInit(stc_tmr6_buf_func_cfg_t *pstcInit);
/* Set the fields of structure stc_tmr6_valid_period_func_cfg_t to default values */
en_result_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_func_cfg_t *pstcInit);
/* Set the fields of structure stc_tmr6_port_input_cfg_t to default values */
en_result_t TMR6_PortInputStructInit(stc_tmr6_port_input_cfg_t *pstcInit);
/* Set the fields of structure stc_tmr6_port_output_cfg_t to default values */
en_result_t TMR6_PortOutputStructInit(stc_tmr6_port_output_cfg_t *pstcInit);
/* Set the fields of structure stc_tmr6_emb_cfg_t to default values */
en_result_t TMR6_EMBCfgStructInit(stc_tmr6_emb_cfg_t *pstcInit);
/* Set the fields of structure stc_tmr6_deadtime_cfg_t to default values */
en_result_t TMR6_DeadTimeCfgStructInit(stc_tmr6_deadtime_cfg_t *pstcInit);
/* Set the fields of structure stc_tmr6_zmask_cfg_t to default values */
en_result_t TMR6_ZMaskCfgStructInit(stc_tmr6_zmask_cfg_t *pstcInit);
/**
* @}
*/
#endif /* DDL_TMR6_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_TMR6_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_tmra.h
* @brief This file contains all the functions prototypes of the TMRA(TimerA)
* driver library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Wuze First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_TMRA_H__
#define __HC32F4A0_TMRA_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_TMRA
* @{
*/
#if (DDL_TMRA_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup TMRA_Global_Types TMRA Global Types
* @{
*/
/**
* @brief TMRA initialization structure.
* @note 'u32PCLKDiv', 'u32CntDir' and 'u32CntMode' are valid only when the clock source is PCLK(PCLK0 for unit1 ~ uint4. PCLK1 for unit5 ~ uint12).
*/
typedef struct
{
uint32_t u32ClkSrc; /*!< Specify the counting clock source of TMRA.
This parameter can be a value of @ref TMRA_Clock_Source */
uint32_t u32PCLKDiv; /*!< Specify the divider of clock source while the clock source is PCLK.
This parameter can be a value of @ref TMRA_PCLK_Divider */
uint32_t u32CntDir; /*!< Specify the direction of counting.
This parameter can be a value of @ref TMRA_Count_Direction */
uint32_t u32CntMode; /*!< Specify the mode of counting.
This parameter can be a value of @ref TMRA_Count_Mode */
uint32_t u32CntOvfOp; /*!< Specify the operation when counting overflow/underflow.
This parameter can be a value of @ref TMRA_Count_Overflow_Operation */
uint32_t u32PeriodVal; /*!< Specify the period reference value.
This parameter can be a number between 0U and 0xFFFFU, inclusive. */
uint32_t u32CntVal; /*!< Specify the initial value of count register.
This parameter can be a number between 0U and 0xFFFFU, inclusive. */
} stc_tmra_init_t;
/**
* @brief TMRA PWM configuration structure.
*/
typedef struct
{
uint32_t u32StartPolarity; /*!< Specify the polarity when the specified TMRA channel start counting.
This parameter can be a value of @ref TMRA_PWM_Start_Polarity */
uint32_t u32StopPolarity; /*!< Specify the polarity when the specified TMRA channel stop counting.
This parameter can be a value of @ref TMRA_PWM_Stop_Polarity */
uint32_t u32CmpPolarity; /*!< Specify the polarity when the specified TMRA channel counting matches the compare register.
This parameter can be a value of @ref TMRA_PWM_Match_Cmp_Polarity */
uint32_t u32PeriodPolarity; /*!< Specify the polarity when the specified TMRA channel counting matches the period register.
This parameter can be a value of @ref TMRA_PWM_Match_Period_Polarity */
uint32_t u32ForcePolarity; /*!< Specify the polarity when the specified TMRA channel at the beginning of the next cycle.
This parameter can be a value of @ref TMRA_PWM_Force_Polarity */
} stc_tmra_pwm_cfg_t;
/**
* @brief TMRA hardware trigger condition configuration structure.
*/
typedef struct
{
uint32_t u32StartCond; /*!< Specify the condition to start the specified TMRA unit.
This parameter can be a value of @ref TMRA_Hardware_Start_Condition */
uint32_t u32StopCond; /*!< Specify the condition to stop the specified TMRA unit.
This parameter can be a value of @ref TMRA_Hardware_Stop_Condition */
uint32_t u32ClrCond; /*!< Specify the condition to clear the specified TMRA unit's count register.
This parameter can be a value of @ref TMRA_Hardware_Clear_Condition */
} stc_tmra_trig_cond_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup TMRA_Global_Macros TMRA Global Macros
* @{
*/
/**
* @defgroup TMRA_Channel TMRA Channel
* @{
*/
#define TMRA_CH_1 (0U) /*!< Channel 1 of TMRA. */
#define TMRA_CH_2 (1U) /*!< Channel 2 of TMRA. */
#define TMRA_CH_3 (2U) /*!< Channel 3 of TMRA. */
#define TMRA_CH_4 (3U) /*!< Channel 4 of TMRA. */
/**
* @}
*/
/**
* @defgroup TMRA_Input_Pin TMRA Input Pin
* @{
*/
#define TMRA_PIN_TRIG (1UL << 0U) /*!< Pin TIMA_<t>_TRIG. */
#define TMRA_PIN_CLKA (1UL << 1U) /*!< Pin TIMA_<t>_CLKA. */
#define TMRA_PIN_CLKB (1UL << 2U) /*!< Pin TIMA_<t>_CLKB. */
#define TMRA_PIN_PWM1 (1UL << 3U) /*!< Pin TIMA_<t>_PWM1. */
#define TMRA_PIN_PWM2 (1UL << 4U) /*!< Pin TIMA_<t>_PWM2. */
#define TMRA_PIN_PWM3 (1UL << 5U) /*!< Pin TIMA_<t>_PWM3. */
#define TMRA_PIN_PWM4 (1UL << 6U) /*!< Pin TIMA_<t>_PWM4. */
#define TMRA_PIN_ALL (TMRA_PIN_TRIG | \
TMRA_PIN_CLKA | \
TMRA_PIN_CLKB | \
TMRA_PIN_PWM1 | \
TMRA_PIN_PWM2 | \
TMRA_PIN_PWM3 | \
TMRA_PIN_PWM4)
/**
* @}
*/
/**
* @defgroup TMRA_Count_Direction TMRA Counting Direction
* @{
*/
#define TMRA_DIR_DOWN (0x0U) /*!< TMRA count down. */
#define TMRA_DIR_UP (TMRA_BCSTR_DIR) /*!< TMRA count up. */
/**
* @}
*/
/**
* @defgroup TMRA_Count_Mode TMRA Counting Mode
* @{
*/
#define TMRA_MODE_SAWTOOTH (0x0U) /*!< Count mode is sawtooth wave. */
#define TMRA_MODE_TRIANGLE (TMRA_BCSTR_MODE) /*!< Count mode is triangle wave. */
/**
* @}
*/
/**
* @defgroup TMRA_Clock_Source TMRA Counting Clock Source
* @note PCLK is automatically disabled when other clock is selected.
* @note Symmetric units: uint 1 and 2; uint 3 and 4; ...; uint 11 and 12.
* @{
*/
#define TMRA_CLK_PCLK (0x0U) /*!< PCLK. PCLK0 for unit1 ~ uint4. PCLK1 for unit5 ~ uint12. */
#define TMRA_CLK_HW_UP_CLKAL_CLKBR (1UL << 0U) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts up. */
#define TMRA_CLK_HW_UP_CLKAL_CLKBF (1UL << 1U) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts up. */
#define TMRA_CLK_HW_UP_CLKAH_CLKBR (1UL << 2U) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts up. */
#define TMRA_CLK_HW_UP_CLKAH_CLKBF (1UL << 3U) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts up. */
#define TMRA_CLK_HW_UP_CLKBL_CLKAR (1UL << 4U) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts up. */
#define TMRA_CLK_HW_UP_CLKBL_CLKAF (1UL << 5U) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts up. */
#define TMRA_CLK_HW_UP_CLKBH_CLKAR (1UL << 6U) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts up. */
#define TMRA_CLK_HW_UP_CLKBH_CLKAF (1UL << 7U) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts up. */
#define TMRA_CLK_HW_UP_TRIGR (1UL << 8U) /*!< When a rising edge occurred on TRIG, the counter register counts up. */
#define TMRA_CLK_HW_UP_TRIGF (1UL << 9U) /*!< When a falling edge occurred on TRIG, the counter register counts up. */
#define TMRA_CLK_HW_UP_EVENT (1UL << 10U) /*!< When the event specified by TMRA_HTSSR occurred, the counter register counts up. */
#define TMRA_CLK_HW_UP_SYM_OVF (1UL << 11U) /*!< When the symmetric unit overflow, the counter register counts up. */
#define TMRA_CLK_HW_UP_SYM_UNF (1UL << 12U) /*!< When the symmetric unit underflow, the counter register counts up. */
#define TMRA_CLK_HW_UP_ALL (0x1FFFUL)
#define TMRA_CLK_HW_DOWN_CLKAL_CLKBR (1UL << 16U) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts down. */
#define TMRA_CLK_HW_DOWN_CLKAL_CLKBF (1UL << 17U) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts down. */
#define TMRA_CLK_HW_DOWN_CLKAH_CLKBR (1UL << 18U) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts down. */
#define TMRA_CLK_HW_DOWN_CLKAH_CLKBF (1UL << 19U) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts down. */
#define TMRA_CLK_HW_DOWN_CLKBL_CLKAR (1UL << 20U) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts down. */
#define TMRA_CLK_HW_DOWN_CLKBL_CLKAF (1UL << 21U) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts down. */
#define TMRA_CLK_HW_DOWN_CLKBH_CLKAR (1UL << 22U) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts down. */
#define TMRA_CLK_HW_DOWN_CLKBH_CLKAF (1UL << 23U) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts down. */
#define TMRA_CLK_HW_DOWN_TRIGR (1UL << 24U) /*!< When a rising edge occurred on TRIG, the counter register counts down. */
#define TMRA_CLK_HW_DOWN_TRIGF (1UL << 25U) /*!< When a falling edge occurred on TRIG, the counter register counts down. */
#define TMRA_CLK_HW_DOWN_EVENT (1UL << 26U) /*!< When the event specified by TMRA_HTSSR occurred, the counter register counts down. */
#define TMRA_CLK_HW_DOWN_SYM_OVF (1UL << 27U) /*!< When the symmetric unit overflow, the counter register counts down. */
#define TMRA_CLK_HW_DOWN_SYM_UNF (1UL << 28U) /*!< When the symmetric unit underflow, the counter register counts down. */
#define TMRA_CLK_HW_DOWN_ALL (0x1FFF0000UL)
/**
* @}
*/
/**
* @defgroup TMRA_PCLK_Divider TMRA PCLK Divider
* @note Clock divider is only valid for PCLK(PCLK0 for unit1 ~ uint4. PCLK1 for unit5 ~ uint12).
* @{
*/
#define TMRA_PCLK_DIV1 (0x0U) /*!< The clock source of TMRA is PCLK. */
#define TMRA_PCLK_DIV2 (TMRA_BCSTR_CKDIV_0) /*!< The clock source of TMRA is PCLK / 2. */
#define TMRA_PCLK_DIV4 (TMRA_BCSTR_CKDIV_1) /*!< The clock source of TMRA is PCLK / 4. */
#define TMRA_PCLK_DIV8 (TMRA_BCSTR_CKDIV_1 | \
TMRA_BCSTR_CKDIV_0) /*!< The clock source of TMRA is PCLK / 8. */
#define TMRA_PCLK_DIV16 (TMRA_BCSTR_CKDIV_2) /*!< The clock source of TMRA is PCLK / 16. */
#define TMRA_PCLK_DIV32 (TMRA_BCSTR_CKDIV_2 | \
TMRA_BCSTR_CKDIV_0) /*!< The clock source of TMRA is PCLK / 32. */
#define TMRA_PCLK_DIV64 (TMRA_BCSTR_CKDIV_2 | \
TMRA_BCSTR_CKDIV_1) /*!< The clock source of TMRA is PCLK / 64. */
#define TMRA_PCLK_DIV128 (TMRA_BCSTR_CKDIV_2 | \
TMRA_BCSTR_CKDIV_1 | \
TMRA_BCSTR_CKDIV_0) /*!< The clock source of TMRA is PCLK / 128. */
#define TMRA_PCLK_DIV256 (TMRA_BCSTR_CKDIV_3) /*!< The clock source of TMRA is PCLK / 256. */
#define TMRA_PCLK_DIV512 (TMRA_BCSTR_CKDIV_3 | \
TMRA_BCSTR_CKDIV_0) /*!< The clock source of TMRA is PCLK / 512. */
#define TMRA_PCLK_DIV1024 (TMRA_BCSTR_CKDIV_3 | \
TMRA_BCSTR_CKDIV_1) /*!< The clock source of TMRA is PCLK / 1024. */
/**
* @}
*/
/**
* @defgroup TMRA_Count_Overflow_Operation TMRA Count Overflow Operation
* @note Count up corresponds to overflow, counter zeroing when counting value overflow period value.
* @note Count down corresponds to underflow, counter reload period value when counting value underflow 0.
* @{
*/
#define TMRA_OVF_CNT_CONTINUE (0x0U) /*!< When counting overflow(or underflow), counting continue. */
#define TMRA_OVF_CNT_STOP (TMRA_BCSTR_OVSTP) /*!< When counting overflow(or underflow), counting stop. */
/**
* @}
*/
/**
* @defgroup TMRA_Interrupt_Type TMRA Interrupt Type
* @{
*/
#define TMRA_INT_OVF (1UL << 12U) /*!< The interrupt of counting overflow. */
#define TMRA_INT_UNF (1UL << 13U) /*!< The interrupt of counting underflow. */
#define TMRA_INT_CMP_CH1 (1UL << 16U) /*!< The interrupt of compare-match of channel 1. */
#define TMRA_INT_CMP_CH2 (1UL << 17U) /*!< The interrupt of compare-match of channel 2. */
#define TMRA_INT_CMP_CH3 (1UL << 18U) /*!< The interrupt of compare-match of channel 3. */
#define TMRA_INT_CMP_CH4 (1UL << 19U) /*!< The interrupt of compare-match of channel 4. */
#define TMRA_INT_ALL (TMRA_INT_OVF | \
TMRA_INT_UNF | \
TMRA_INT_CMP_CH1 | \
TMRA_INT_CMP_CH2 | \
TMRA_INT_CMP_CH3 | \
TMRA_INT_CMP_CH4)
/**
* @}
*/
/**
* @defgroup TMRA_Event_Type TMRA Event Type
* @{
*/
#define TMRA_EVENT_CMP_CH1 (TMRA_ECONR_ETEN1) /*!< The event of compare-match of channel 1. */
#define TMRA_EVENT_CMP_CH2 (TMRA_ECONR_ETEN2) /*!< The event of compare-match of channel 2. */
#define TMRA_EVENT_CMP_CH3 (TMRA_ECONR_ETEN3) /*!< The event of compare-match of channel 3. */
#define TMRA_EVENT_CMP_CH4 (TMRA_ECONR_ETEN4) /*!< The event of compare-match of channel 4. */
#define TMRA_EVENT_ALL (TMRA_EVENT_CMP_CH1 | \
TMRA_EVENT_CMP_CH2 | \
TMRA_EVENT_CMP_CH3 | \
TMRA_EVENT_CMP_CH4)
/**
* @}
*/
/**
* @defgroup TMRA_Status_Flag TMRA Status Flag
* @{
*/
#define TMRA_FLAG_OVF (1UL << 14U) /*!< The flag of counting overflow. */
#define TMRA_FLAG_UNF (1UL << 15U) /*!< The flag of counting underflow. */
#define TMRA_FLAG_CMP_CH1 (1UL << 16U) /*!< The flag of compare-match of channel 1. */
#define TMRA_FLAG_CMP_CH2 (1UL << 17U) /*!< The flag of compare-match of channel 2. */
#define TMRA_FLAG_CMP_CH3 (1UL << 18U) /*!< The flag of compare-match of channel 3. */
#define TMRA_FLAG_CMP_CH4 (1UL << 19U) /*!< The flag of compare-match of channel 4. */
#define TMRA_FLAG_ALL (TMRA_FLAG_OVF | \
TMRA_FLAG_UNF | \
TMRA_FLAG_CMP_CH1 | \
TMRA_FLAG_CMP_CH2 | \
TMRA_FLAG_CMP_CH3 | \
TMRA_FLAG_CMP_CH4)
/**
* @}
*/
/**
* @defgroup TMRA_Cmp_Value_Cache_Condition TMRA Compare Value Cache Condition
* @{
*/
#define TMRA_CACHE_COND_OVF_CLR (0x0U) /*!< This configuration value applies to non-triangular wave counting mode. \
When counting overflow or underflow or counting register was cleared, \
transfer CMPARm(m=2, 4) to CMPARn(n=1, 3). */
#define TMRA_CACHE_COND_TW_PEAK (TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak, \
transfer CMPARm(m=2, 4) to CMPARn(n=1, 3). */
#define TMRA_CACHE_COND_TW_VALLEY (TMRA_BCONR_BSE1) /*!< In triangle wave count mode, when count reached valley, \
transfer CMPARm(m=2, 4) to CMPARn(n=1, 3). */
/**
* @}
*/
/**
* @defgroup TMRA_Function_Mode TMRA Function Mode
* @{
*/
#define TMRA_FUNC_COMPARE (0x0U) /*!< The function mode of TMRA is comparison ouput. */
#define TMRA_FUNC_CAPTURE (TMRA_CCONR_CAPMD) /*!< The function mode of TMRA is capture the input. */
/**
* @}
*/
/**
* @defgroup TMRA_Channel_Capture_Condition TMRA Capturing Condition Of Channel
* @note 'TMRA_CAPT_COND_TRIGR' and 'TMRA_CAPT_COND_TRIGF' are only valid for channel 4.
* @{
*/
#define TMRA_CAPT_COND_INVALID (0x0U) /*!< The condition of capture is INVALID. */
#define TMRA_CAPT_COND_PWMR (TMRA_CCONR_HICP0) /*!< The condition of capture is a rising edge is sampled on pin TIMA_<t>_PWMn. */
#define TMRA_CAPT_COND_PWMF (TMRA_CCONR_HICP1) /*!< The condition of capture is a falling edge is sampled on pin TIMA_<t>_PWMn. */
#define TMRA_CAPT_COND_EVENT (TMRA_CCONR_HICP2) /*!< The condition of capture is the specified event occurred. */
#define TMRA_CAPT_COND_TRIGR (TMRA_CCONR_HICP3) /*!< The condition of capture is a rising edge is sampled on pin TIMA_<t>_TRIG. \
This condition is only valid for channel 4. */
#define TMRA_CAPT_COND_TRIGF (TMRA_CCONR_HICP4) /*!< The condition of capture is a falling edge is sampled on pin TIMA_<t>_TRIG. \
This condition is only valid for channel 4. */
#define TMRA_CAPT_COND_ALL (TMRA_CAPT_COND_PWMR | \
TMRA_CAPT_COND_PWMF | \
TMRA_CAPT_COND_EVENT | \
TMRA_CAPT_COND_TRIGR | \
TMRA_CAPT_COND_TRIGF)
/**
* @}
*/
/**
* @defgroup TMRA_Filter_Clock_Divider TMRA Filter Clock Divider
* @{
*/
#define TMRA_FILTER_CLK_DIV1 (0x0U) /*!< The filter clock is PCLK / 1. */
#define TMRA_FILTER_CLK_DIV4 (0x1U) /*!< The filter clock is PCLK / 4. */
#define TMRA_FILTER_CLK_DIV16 (0x2U) /*!< The filter clock is PCLK / 16. */
#define TMRA_FILTER_CLK_DIV64 (0x3U) /*!< The filter clock is PCLK / 64. */
/**
* @}
*/
/**
* @defgroup TMRA_PWM_Out_Command TMRA PWM Out Command
* @{
*/
#define TMRA_PWM_DISABLE (0x0U) /*!< Disable PWM output. */
#define TMRA_PWM_ENABLE (TMRA_PCONR_OUTEN) /*!< Enable PWM output. */
/**
* @}
*/
/**
* @defgroup TMRA_PWM_Start_Polarity TMRA PWM Start Polarity
* @note The 'START' in the following macros is the state 'counting start'.
* @{
*/
#define TMRA_PWM_START_LOW (0x0U) /*!< PWM output low. */
#define TMRA_PWM_START_HIGH (TMRA_PCONR_STAC_0) /*!< PWM output high. */
#define TMRA_PWM_START_KEEP (TMRA_PCONR_STAC_1) /*!< PWM output keeps the current polarity. */
/**
* @}
*/
/**
* @defgroup TMRA_PWM_Stop_Polarity TMRA PWM Stop Polarity
* @note The 'STOP' in the following macros is the state 'counting stop'.
* @{
*/
#define TMRA_PWM_STOP_LOW (0x0U) /*!< PWM output low. */
#define TMRA_PWM_STOP_HIGH (TMRA_PCONR_STPC_0) /*!< PWM output high. */
#define TMRA_PWM_STOP_KEEP (TMRA_PCONR_STPC_1) /*!< PWM output keeps the current polarity. */
/**
* @}
*/
/**
* @defgroup TMRA_PWM_Match_Cmp_Polarity TMRA PWM Polarity When Counting Matchs Compare Reference Value
* @{
*/
#define TMRA_PWM_CMP_LOW (0x0U) /*!< PWM output low. */
#define TMRA_PWM_CMP_HIGH (TMRA_PCONR_CMPC_0) /*!< PWM output high. */
#define TMRA_PWM_CMP_KEEP (TMRA_PCONR_CMPC_1) /*!< PWM output keeps the current polarity. */
#define TMRA_PWM_CMP_REVERSE (TMRA_PCONR_CMPC_1 | \
TMRA_PCONR_CMPC_0) /*!< PWM output reverses the current polarity. */
/**
* @}
*/
/**
* @defgroup TMRA_PWM_Match_Period_Polarity TMRA PWM Polarity When Counting Matchs Period Reference Value
* @{
*/
#define TMRA_PWM_PERIOD_LOW (0x0U) /*!< PWM output low. */
#define TMRA_PWM_PERIOD_HIGH (TMRA_PCONR_PERC_0) /*!< PWM output high. */
#define TMRA_PWM_PERIOD_KEEP (TMRA_PCONR_PERC_1) /*!< PWM output keeps the current polarity. */
#define TMRA_PWM_PERIOD_REVERSE (TMRA_PCONR_PERC_1 | \
TMRA_PCONR_PERC_0) /*!< PWM output reverses the current polarity. */
/**
* @}
*/
/**
* @defgroup TMRA_PWM_Force_Polarity TMRA PWM Force Polarity
* @{
*/
#define TMRA_PWM_FORCE_INVALID (0x0U) /*!< Force polarity is invalid. */
#define TMRA_PWM_FORCE_LOW (TMRA_PCONR_FORC_1) /*!< Force the PWM output low at the beginning of the next cycle. \
The beginning of the next cycle: overflow position or underflow position \
of sawtooth wave; valley position of triangle wave. */
#define TMRA_PWM_FORCE_HIGH (TMRA_PCONR_FORC_1 | \
TMRA_PCONR_FORC_0) /*!< Force the PWM output high at the beginning of the next cycle. \
The beginning of the next cycle: overflow position or underflow position \
of sawtooth wave; valley position of triangle wave. */
/**
* @}
*/
/**
* @defgroup TMRA_Hardware_Start_Condition TMRA Hardware Start Condition
* @{
*/
#define TMRA_START_COND_INVALID (0x0U) /*!< The condition of start is INVALID. */
#define TMRA_START_COND_TRIGR (TMRA_HCONR_HSTA0) /*!< 1. Sync start is invalid: The condition is that a rising edge is sampled on TRIG of the current TMRA unit. \
2. Sync start is valid: The condition is that a rising edge is sampled on TRIG of the symmetric TMRA unit. */
#define TMRA_START_COND_TRIGF (TMRA_HCONR_HSTA1) /*!< 1. Sync start is invalid: The condition is that a falling edge is sampled on TRIG of the current TMRA unit. \
2. Sync start is valid: The condition is that a falling edge is sampled on TRIG of the symmetric TMRA unit. */
#define TMRA_START_COND_EVENT (TMRA_HCONR_HSTA2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */
#define TMRA_START_COND_ALL (TMRA_START_COND_TRIGR | \
TMRA_START_COND_TRIGF | \
TMRA_START_COND_EVENT)
/**
* @}
*/
/**
* @defgroup TMRA_Hardware_Stop_Condition TMRA Hardware Stop Condition
* @{
*/
#define TMRA_STOP_COND_INVALID (0x0U) /*!< The condition of stop is INVALID. */
#define TMRA_STOP_COND_TRIGR (TMRA_HCONR_HSTP0) /*!< The condition is that a rising edge is sampled on pin TRIG of the current TMRA unit. */
#define TMRA_STOP_COND_TRIGF (TMRA_HCONR_HSTP1) /*!< The condition is that a falling edge is sampled on pin TRIG of the current TMRA unit. */
#define TMRA_STOP_COND_EVENT (TMRA_HCONR_HSTP2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */
#define TMRA_STOP_COND_ALL (TMRA_STOP_COND_TRIGR | \
TMRA_STOP_COND_TRIGF | \
TMRA_STOP_COND_EVENT)
/**
* @}
*/
/**
* @defgroup TMRA_Hardware_Clear_Condition TMRA Hardware Clear Condition
* @note Symmetric units: uint 1 and 2; uint 3 and 4; ... ; uint 11 and 12.
* @{
*/
#define TMRA_CLR_COND_INVALID (0x0U) /*!< The condition of clear is INVALID. */
#define TMRA_CLR_COND_TRIGR (TMRA_HCONR_HCLE0) /*!< The condition is that a rising edge is sampled on TRIG of the current TMRA unit. */
#define TMRA_CLR_COND_TRIGF (TMRA_HCONR_HCLE1) /*!< The condition is that a falling edge is sampled on TRIG of the current TMRA unit. */
#define TMRA_CLR_COND_EVENT (TMRA_HCONR_HCLE2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */
#define TMRA_CLR_COND_SYM_TRIGR (TMRA_HCONR_HCLE3) /*!< The condition is that a rising edge is sampled on TRIG of the symmetric unit. */
#define TMRA_CLR_COND_SYM_TRIGF (TMRA_HCONR_HCLE4) /*!< The condition is that a falling edge is sampled on TRIG of the symmetric unit. */
#define TMRA_CLR_COND_PWM3R (TMRA_HCONR_HCLE5) /*!< The condition is that a rising edge is sampled on PWM3 of the current TMRA unit. */
#define TMRA_CLR_COND_PWM3F (TMRA_HCONR_HCLE6) /*!< The condition is that a falling edge is sampled on PWM3 of the current TMRA unit. */
#define TMRA_CLR_COND_ALL (TMRA_CLR_COND_TRIGR | \
TMRA_CLR_COND_TRIGF | \
TMRA_CLR_COND_EVENT | \
TMRA_CLR_COND_SYM_TRIGR | \
TMRA_CLR_COND_SYM_TRIGF | \
TMRA_CLR_COND_PWM3R | \
TMRA_CLR_COND_PWM3F)
/**
* @}
*/
/**
* @defgroup TMRA_Event_Usage TMRA Event Usage
* @{
*/
#define TMRA_EVENT_USAGE_CNT (0U) /*!< The specified event is used for counting. */
#define TMRA_EVENT_USAGE_CAPT (1U) /*!< The specified event is used for capturing. */
/**
* @}
*/
/**
* @defgroup TMRA_Common_Trigger_Sel TMRA Common Trigger Source Select
* @{
*/
#define TMRA_COM_TRIG1 (AOS_TMRA_HTSSR_COMTRG_EN_0)
#define TMRA_COM_TRIG2 (AOS_TMRA_HTSSR_COMTRG_EN_1)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup TMRA_Global_Functions
* @{
*/
en_result_t TMRA_Init(M4_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcInit);
en_result_t TMRA_StructInit(stc_tmra_init_t *pstcInit);
void TMRA_DeInit(M4_TMRA_TypeDef *TMRAx);
void TMRA_SetCntVal(M4_TMRA_TypeDef *TMRAx, uint32_t u32Val);
uint32_t TMRA_GetCntVal(const M4_TMRA_TypeDef *TMRAx);
void TMRA_SetPeriodVal(M4_TMRA_TypeDef *TMRAx, uint32_t u32Val);
uint32_t TMRA_GetPeriodVal(const M4_TMRA_TypeDef *TMRAx);
void TMRA_SetFuncMode(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32FuncMode);
void TMRA_SetCmpVal(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Val);
uint32_t TMRA_GetCmpVal(const M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh);
en_result_t TMRA_PWM_Config(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, const stc_tmra_pwm_cfg_t *pstcCfg);
en_result_t TMRA_PWM_StructInit(stc_tmra_pwm_cfg_t *pstcCfg);
void TMRA_PWM_Cmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, en_functional_state_t enNewState);
void TMRA_FilterConfig(M4_TMRA_TypeDef *TMRAx, uint8_t u8InputPin, uint32_t u32ClkDiv);
void TMRA_FilterCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8InputPin, en_functional_state_t enNewState);
void TMRA_SetCaptCond(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Cond);
en_result_t TMRA_SetTrigCond(M4_TMRA_TypeDef *TMRAx, const stc_tmra_trig_cond_t *pstcCond);
en_result_t TMRA_TrigCondStructInit(stc_tmra_trig_cond_t *pstcCond);
void TMRA_SetTriggerSrc(M4_TMRA_TypeDef *TMRAx, uint8_t u8EvtUsage, en_event_src_t enEvent);
void TMRA_ComTriggerCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8EvtUsage, \
uint32_t u32ComTrig, en_functional_state_t enNewState);
void TMRA_CmpValCacheConfig(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32CacheCond);
void TMRA_CmpValCacheCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, en_functional_state_t enNewState);
void TMRA_SetOvfOperation(M4_TMRA_TypeDef *TMRAx, uint32_t u32OvfOp);
void TMRA_SyncStartCmd(M4_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState);
void TMRA_IntCmd(M4_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState);
void TMRA_EventCmd(M4_TMRA_TypeDef *TMRAx, uint32_t u32EvtType, en_functional_state_t enNewState);
en_flag_status_t TMRA_GetStatus(const M4_TMRA_TypeDef *TMRAx, uint32_t u32Flag);
void TMRA_ClrStatus(M4_TMRA_TypeDef *TMRAx, uint32_t u32Flag);
void TMRA_Start(M4_TMRA_TypeDef *TMRAx);
void TMRA_Stop(M4_TMRA_TypeDef *TMRAx);
void TMRA_SetCntDir(M4_TMRA_TypeDef *TMRAx, uint32_t u32CntDir);
void TMRA_SetCntMode(M4_TMRA_TypeDef *TMRAx, uint32_t u32CntMode);
void TMRA_SetPCLKDiv(M4_TMRA_TypeDef *TMRAx, uint32_t u32ClkDiv);
uint32_t TMRA_GetCntDir(const M4_TMRA_TypeDef *TMRAx);
void TMRA_SetClkSrc(M4_TMRA_TypeDef *TMRAx, uint32_t u32ClkSrc);
void TMRA_HwClkSrcCmd(M4_TMRA_TypeDef *TMRAx, uint32_t u32HwClkSrc, en_functional_state_t enNewState);
void TMRA_PWM_SetStartPolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity);
void TMRA_PWM_SetStopPolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity);
void TMRA_PWM_SetMatchCmpPolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity);
void TMRA_PWM_SetMatchPeriodPolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity);
void TMRA_PWM_SetForcePolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity);
void TMRA_CaptCondCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32CaptCond, en_functional_state_t enNewState);
void TMRA_TrigCondCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32TrigCond, en_functional_state_t enNewState);
/**
* @}
*/
#endif /* DDL_TMRA_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_TMRA_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_trng.h
* @brief This file contains all the functions prototypes of the TRNG driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Heqb First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_TRNG_H__
#define __HC32F4A0_TRNG_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_TRNG
* @{
*/
#if (DDL_TRNG_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup TRNG_Global_Macros TRNG Global Macros
* @{
*/
/**
* @defgroup TRNG_Load_New_Value TRNG load new value
* @{
*/
#define TRNG_RELOAD_ENABLE (TRNG_MR_LOAD) /* Enable load new initial values. */
#define TRNG_RELOAD_DISABLE (0x00000000UL) /* Disable load new initial values. */
/**
* @}
*/
/**
* @defgroup TRNG_Shift_Control TRNG Shift Control
* @{
*/
#define TRNG_SHIFT_COUNT_32 (0x0000000CUL) /* Shift 32 times when capturing random noise. */
#define TRNG_SHIFT_COUNT_64 (0x00000010UL) /* Shift 64 times when capturing random noise. */
#define TRNG_SHIFT_COUNT_128 (0x00000014UL) /* Shift 128 times when capturing random noise. */
#define TRNG_SHIFT_COUNT_256 (0x00000018UL) /* Shift 256 times when capturing random noise. */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup TRNG_Global_Functions
* @{
*/
void TRNG_SetShiftCnt(uint32_t u32ShiftCount);
void TRNG_ReloadCmd(uint32_t u32ReloadCmd);
en_result_t TRNG_Generate(uint32_t au32Random[]);
/**
* @}
*/
#endif /* DDL_TRNG_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_TRNG_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_usart.h
* @brief This file contains all the functions prototypes of the USART(Universal
* Synchronous/Asynchronous Receiver Transmitter) driver library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hongjh First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_USART_H__
#define __HC32F4A0_USART_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_USART
* @{
*/
#if (DDL_USART_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup USART_Global_Types USART Global Types
* @{
*/
/**
* @brief UART mode initialization structure definition
*/
typedef struct
{
uint32_t u32Baudrate; /*!< UART baudrate. The baudrate is valid when clock source is PCLK. */
uint32_t u32ClkMode; /*!< Clock mode.
This parameter can be a value of @ref USART_Clock_Mode */
uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK.
This parameter can be a value of @ref USART_PCLK_Division */
uint32_t u32Parity; /*!< Parity format.
This parameter can be a value of @ref USART_Parity_Control */
uint32_t u32DataWidth; /*!< Data width.
This parameter can be a value of @ref USART_Data_Length_Bits */
uint32_t u32StopBit; /*!< Stop Bits.
This parameter can be a value of @ref USART_Stop_Bits */
uint32_t u32OversamplingBits; /*!< Oversampling Bits.
This parameter can be a value of @ref USART_Oversampling_Bits */
uint32_t u32BitDirection; /*!< Significant bit.
This parameter can be a value of @ref USART_Significant_Bit */
uint32_t u32NoiseFilterState; /*!< RX pin noise filter state.
This parameter can be a value of @ref USART_Noise_Filter_State */
uint32_t u32SbDetectPolarity; /*!< Start Bit Detect Polarity.
This parameter can be a value of @ref USART_Start_Bit_Detect_Polarity */
uint32_t u32HwFlowCtrl; /*!< Hardware flow control.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} stc_usart_uart_init_t;
/**
* @brief UART multiple-processor initialization structure definition
*/
typedef struct
{
uint32_t u32Baudrate; /*!< UART baudrate. The baudrate is valid when clock source is PCLK. */
uint32_t u32ClkMode; /*!< Clock mode.
This parameter can be a value of @ref USART_Clock_Mode */
uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK.
This parameter can be a value of @ref USART_PCLK_Division */
uint32_t u32DataWidth; /*!< Data width.
This parameter can be a value of @ref USART_Data_Length_Bits */
uint32_t u32StopBit; /*!< Stop Bits.
This parameter can be a value of @ref USART_Stop_Bits */
uint32_t u32OversamplingBits; /*!< Oversampling Bits.
This parameter can be a value of @ref USART_Oversampling_Bits */
uint32_t u32BitDirection; /*!< Significant bit.
This parameter can be a value of @ref USART_Significant_Bit */
uint32_t u32NoiseFilterState; /*!< RX pin noise filter state.
This parameter can be a value of @ref USART_Noise_Filter_State */
uint32_t u32SbDetectPolarity; /*!< Start Bit Detect Polarity.
This parameter can be a value of @ref USART_Start_Bit_Detect_Polarity */
uint32_t u32HwFlowCtrl; /*!< Hardware flow control.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} stc_usart_multiprocessor_init_t;
/**
* @brief LIN mode initialization structure definition
*/
typedef struct
{
uint32_t u32Baudrate; /*!< UART baudrate. The baudrate is valid when clock source is PCLK. */
uint32_t u32ClkMode; /*!< Clock mode.
This parameter can be a value of @ref USART_Clock_Mode */
uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK.
This parameter can be a value of @ref USART_PCLK_Division */
uint32_t u32BmcPclkDiv; /*!< BMC PCLK division. The PCLK division function is valid when clock source is PCLK.
This parameter can be a value of @ref USART_LIN_BMC_PCLK_Division */
uint32_t u32OversamplingBits; /*!< Oversampling Bits.
This parameter can be a value of @ref USART_Oversampling_Bits */
uint32_t u32DetectBreakLen; /*!< Detect break length.
This parameter can be a value of @ref USART_LIN_Detect_Break_Length */
uint32_t u32SendBreakLen; /*!< Send break length.
This parameter can be a value of @ref USART_LIN_Send_Break_Length */
uint32_t u32SendBreakMode; /*!< Send break mode.
This parameter can be a value of @ref USART_LIN_Send_Break_Mode */
} stc_usart_lin_init_t;
/**
* @brief Smart card mode initialization structure definition
*/
typedef struct
{
uint32_t u32Baudrate; /*!< UART baudrate */
uint32_t u32ClkMode; /*!< Clock mode.
This parameter can be a value of @ref USART_Clock_Mode */
uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK.
This parameter can be a value of @ref USART_PCLK_Division */
uint32_t u32StopBit; /*!< Stop Bits.
This parameter can be a value of @ref USART_Stop_Bits */
uint32_t u32BitDirection; /*!< Significant bit.
This parameter can be a value of @ref USART_Significant_Bit */
} stc_usart_smartcard_init_t;
/**
* @brief clock synchronization mode initialization structure definition
*/
typedef struct
{
uint32_t u32Baudrate; /*!< UART baudrate. The baudrate is valid when clock source is PCLK. */
uint32_t u32ClkMode; /*!< Clock mode.
This parameter can be a value of @ref USART_Clock_Mode */
uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK.
This parameter can be a value of @ref USART_PCLK_Division */
uint32_t u32BitDirection; /*!< Significant bit.
This parameter can be a value of @ref USART_Significant_Bit */
uint32_t u32HwFlowCtrl; /*!< Hardware flow control.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} stc_usart_clksync_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup USART_Global_Macros USART Global Macros
* @{
*/
/**
* @defgroup USART_Flag USART Flag
* @{
*/
#define USART_FLAG_PE (USART_SR_PE) /*!< Parity error flag */
#define USART_FLAG_FE (USART_SR_FE) /*!< Framing error flag */
#define USART_FLAG_ORE (USART_SR_ORE) /*!< Overrun error flag */
#define USART_FLAG_BE (USART_SR_BE) /*!< LIN bus error flag */
#define USART_FLAG_RXNE (USART_SR_RXNE) /*!< Receive data register not empty flag */
#define USART_FLAG_TC (USART_SR_TC) /*!< Transmission complete flag */
#define USART_FLAG_TXE (USART_SR_TXE) /*!< Transmit data register empty flag */
#define USART_FLAG_RTOF (USART_SR_RTOF) /*!< Receive timeout flag */
#define USART_FLAG_LBD (USART_SR_LBD) /*!< LIN break signal detection flag */
#define USART_FLAG_WKUP (USART_SR_WKUP) /*!< LIN wakeup signal detection flag */
#define USART_FLAG_MPB (USART_SR_MPB) /*!< Receive processor ID flag */
/**
* @}
*/
/**
* @defgroup USART_Transmission_Type USART Transmission Type
* @{
*/
#define USART_TRANSMISSION_ID (USART_DR_MPID)
#define USART_TRANSMISSION_DATA (0UL)
/**
* @}
*/
/**
* @defgroup USART_Clear_Flag USART Clear Flag
* @{
*/
#define USART_CLEAR_FLAG_PE (USART_CR1_CPE) /*!< Clear Parity error flag */
#define USART_CLEAR_FLAG_FE (USART_CR1_CFE) /*!< Clear Framing error flag */
#define USART_CLEAR_FLAG_ORE (USART_CR1_CORE) /*!< Clear Overrun error flag */
#define USART_CLEAR_FLAG_RTOF (USART_CR1_CRTOF) /*!< Clear RX timeout flag */
#define USART_CLEAR_FLAG_BE (USART_CR1_CBE) /*!< Clear LIN bus error flag */
#define USART_CLEAR_FLAG_WKUP (USART_CR1_CWKUP) /*!< Clear LIN wakeup signal flag */
#define USART_CLEAR_FLAG_LBD (USART_CR1_CLBD) /*!< Clear LIN break detection flag */
/**
* @}
*/
/**
* @defgroup USART_Transmit_Receive_Function USART Transmit/Receive Function
* @{
*/
#define USART_RX (USART_CR1_RE) /*!< USART RX function */
#define USART_TX (USART_CR1_TE) /*!< USART TX function */
#define USART_RTO (USART_CR1_RTOE) /*!< USART RX timerout function */
#define USART_INT_RX (USART_CR1_RIE) /*!< USART receive data register not empty && receive error interrupt */
#define USART_INT_TXE (USART_CR1_TXEIE) /*!< USART transmit data register empty interrupt */
#define USART_INT_TC (USART_CR1_TCIE) /*!< USART transmission complete interrupt */
#define USART_INT_RTO (USART_CR1_RTOIE) /*!< USART RX timerout interrupt */
/**
* @}
*/
/**
* @defgroup USART_LIN_Function USART LIN Function
* @{
*/
#define USART_LIN (USART_CR2_LINEN) /*!< USART LIN function */
#define USART_LIN_WKUP (USART_CR2_WKUPE) /*!< USART LIN wakeup signal detect function */
#define USART_LIN_INT_WKUP (USART_CR2_WKUPIE) /*!< USART LIN wakeup signal detect interrupt function */
#define USART_LIN_BUSERR (USART_CR2_BEE) /*!< USART LIN bus error detect function */
#define USART_LIN_INT_BUSERR (USART_CR2_BEIE) /*!< USART LIN bus error detect interrupt function */
#define USART_LIN_INT_BREAK (USART_CR2_LBDIE) /*!< USART LIN break field detect interrupt function */
/**
* @}
*/
/**
* @defgroup USART_Parity_Control USART Parity Control
* @{
*/
#define USART_PARITY_NONE (0UL) /*!< Parity control disabled */
#define USART_PARITY_EVEN (USART_CR1_PCE) /*!< Parity control enabled and Even Parity is selected */
#define USART_PARITY_ODD (USART_CR1_PCE | \
USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
/**
* @}
*/
/**
* @defgroup USART_Data_Length_Bits Data Length Bits
* @{
*/
#define USART_DATA_LENGTH_8BIT (0UL) /*!< 8 bits */
#define USART_DATA_LENGTH_9BIT (USART_CR1_M) /*!< 9 bits */
/**
* @}
*/
/**
* @defgroup USART_Oversampling_Bits USART Oversampling Bits
* @{
*/
#define USART_OVERSAMPLING_16BIT (0UL) /*!< Oversampling by 16 bits */
#define USART_OVERSAMPLING_8BIT (USART_CR1_OVER8) /*!< Oversampling by 8 bits */
/**
* @}
*/
/**
* @defgroup USART_Significant_Bit USART Significant Bit
* @{
*/
#define USART_LSB (0UL) /*!< LSB(Least Significant Bit) */
#define USART_MSB (USART_CR1_ML) /*!< MSB(Most Significant Bit) */
/**
* @}
*/
/**
* @defgroup USART_Noise_Filter_State USART Noise Filter State
* @{
*/
#define USART_NOISE_FILTER_DISABLE (0UL) /*!< Disable noise filter */
#define USART_NOISE_FILTER_ENABLE (USART_CR1_NFE) /*!< Enable noise filter */
/**
* @}
*/
/**
* @defgroup USART_Start_Bit_Detect_Polarity USART Start Bit Detect Polarity
* @{
*/
#define USART_SB_DETECT_LOW (0UL) /*!< Detect RX pin low level */
#define USART_SB_DETECT_FALLING (USART_CR1_SBS) /*!< Detect RX pin falling edge */
/**
* @}
*/
/**
* @defgroup USART_LIN_Send_Break_Mode USART LIN Send Break Mode
* @{
*/
#define USART_LIN_SEND_BREAK_MODE_SBK (0UL) /*!< Start send break after USART_CR2 SBK bit set 1 value */
#define USART_LIN_SEND_BREAK_MODE_TDR (USART_CR2_SBKM) /*!< Start send break after USART_DR TDR write 0x00 value */
/**
* @}
*/
/**
* @defgroup USART_Multiple_Processor_State USART Multiple Processor State
* @{
*/
#define USART_MULTIPLE_PROCESSOR_DISABLE (0UL) /*!< Disable multiple processor function */
#define USART_MULTIPLE_PROCESSOR_ENABLE (USART_CR2_MPE) /*!< Enable multiple processor function */
/**
* @}
*/
/**
* @defgroup USART_LIN_Detect_Break_Length USART LIN Detect Break Length
* @{
*/
#define USART_LIN_DETECT_BREAK_10BIT (0UL) /*!< Detect break 10-bit */
#define USART_LIN_DETECT_BREAK_11BIT (USART_CR2_LBDL) /*!< Detect break 11-bit */
/**
* @}
*/
/**
* @defgroup USART_LIN_Send_Break_Length USART LIN Send Break Length
* @{
*/
#define USART_LIN_SEND_BREAK_10BIT (0UL) /*!< Send break 10-bit */
#define USART_LIN_SEND_BREAK_11BIT (USART_CR2_SBKL_0) /*!< Send break 11-bit */
#define USART_LIN_SEND_BREAK_13BIT (USART_CR2_SBKL_1) /*!< Send break 13-bit */
#define USART_LIN_SEND_BREAK_14BIT (USART_CR2_SBKL) /*!< Send break 14-bit */
/**
* @}
*/
/**
* @defgroup USART_Clock_Mode USART Clock Mode Selection
* @{
*/
#define USART_EXTCLK (USART_CR2_CLKC_1) /*!< Select external clock source. */
#define USART_INTERNCLK_OUTPUT (USART_CR2_CLKC_0) /*!< Select internal clock source and output clock. */
#define USART_INTERNCLK_NONE_OUTPUT (0UL) /*!< Select internal clock source and don't output clock */
/**
* @}
*/
/**
* @defgroup USART_Stop_Bits USART Stop Bits
* @{
*/
#define USART_STOPBIT_1BIT (0UL) /*!< 1 stop bit */
#define USART_STOPBIT_2BIT (USART_CR2_STOP) /*!< 2 stop bit */
/**
* @}
*/
/**
* @defgroup USART_DUPLEX_SEL USART Half-duplex/Full-duplex Selection
* @{
*/
#define USART_FULLDUPLEX_MODE (0UL) /*!< USART full-duplex mode */
#define USART_HALFDUPLEX_MODE (USART_CR3_HDSEL) /*!< USART half-duplex mode */
/**
* @}
*/
/**
* @defgroup USART_Hardware_Flow_Control USART Hardware Flow Control RTS/CTS
* @{
*/
#define USART_HWFLOWCTRL_NONE (0UL) /*!< Disable USART hardware flow controle */
#define USART_HWFLOWCTRL_RTS (USART_CR3_RTSE) /*!< USART hardware flow control RTS mode */
#define USART_HWFLOWCTRL_CTS (USART_CR3_CTSE) /*!< USART hardware flow control CTS mode */
#define USART_HWFLOWCTRL_RTS_CTS (USART_CR3_RTSE | \
USART_CR3_CTSE) /*!< USART hardware flow control RTS and CTS mode */
/**
* @}
*/
/**
* @defgroup USART_Smartcard_ETU_Clock USART Smartcard ETU Clock
* @{
*/
#define USART_SC_ETU_CLK_32 (0UL) /*!< 1 etu = 32/f */
#define USART_SC_ETU_CLK_64 (USART_CR3_BCN_0) /*!< 1 etu = 64/f */
#define USART_SC_ETU_CLK_128 (USART_CR3_BCN_1 | \
USART_CR3_BCN_0) /*!< 1 etu = 128/f */
#define USART_SC_ETU_CLK_256 (USART_CR3_BCN_2 | \
USART_CR3_BCN_0) /*!< 1 etu = 256/f */
#define USART_SC_ETU_CLK_372 (USART_CR3_BCN_2 | \
USART_CR3_BCN_1) /*!< 1 etu = 372/f */
/**
* @}
*/
/**
* @defgroup USART_PCLK_Division USART PCLK Clock Prescaler Division
* @{
*/
#define USART_PCLK_DIV1 (0UL) /*!< PCLK */
#define USART_PCLK_DIV4 (USART_PR_PSC_0) /*!< PCLK/4 */
#define USART_PCLK_DIV16 (USART_PR_PSC_1) /*!< PCLK/16 */
#define USART_PCLK_DIV64 (USART_PR_PSC) /*!< PCLK/64 */
/**
* @}
*/
/**
* @defgroup USART_LIN_BMC_PCLK_Division USART LIN Baudrate Measure Counter PCLK Division
* @{
*/
#define USART_LIN_BMC_PCLK_DIV1 (0UL) /*!< PCLK */
#define USART_LIN_BMC_PCLK_DIV2 (USART_PR_LBMPSC_0) /*!< PCLK/2 */
#define USART_LIN_BMC_PCLK_DIV4 (USART_PR_LBMPSC_1) /*!< PCLK/4 */
#define USART_LIN_BMC_PCLK_DIV8 (USART_PR_LBMPSC) /*!< PCLK/8 */
/**
* @}
*/
/**
* @defgroup USART_Stop_Mode_Noise_Filter USART Stop Mode Noise_Filter
* @{
*/
#define USART_STOP_MODE_FILTER_NONE (0UL) /*!< Disable noise filter */
#define USART_STOP_MODE_FILTER_WIDTH_LEVEL_1 (PERIC_USART1_NFC_NFE) /*!< Filter width level 1 */
#define USART_STOP_MODE_FILTER_WIDTH_LEVEL_2 (PERIC_USART1_NFC_NFE | \
PERIC_USART1_NFC_NFS_0) /*!< Filter width level 2 */
#define USART_STOP_MODE_FILTER_WIDTH_LEVEL_3 (PERIC_USART1_NFC_NFE | \
PERIC_USART1_NFC_NFS_1) /*!< Filter width level 3 */
#define USART_STOP_MODE_FILTER_WIDTH_LEVEL_4 (PERIC_USART1_NFC_NFE | \
PERIC_USART1_NFC_NFS) /*!< Filter width level 4 */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup USART_Global_Functions
* @{
*/
en_result_t USART_UartInit(M4_USART_TypeDef *USARTx,
const stc_usart_uart_init_t *pstcInit);
en_result_t USART_HalfduplexInit(M4_USART_TypeDef *USARTx,
const stc_usart_uart_init_t *pstcInit);
en_result_t USART_UartStructInit(stc_usart_uart_init_t *pstcInit);
en_result_t USART_MultiProcessorInit(M4_USART_TypeDef *USARTx,
const stc_usart_multiprocessor_init_t *pstcInit);
en_result_t USART_MultiProcessorStructInit(stc_usart_multiprocessor_init_t *pstcInit);
en_result_t USART_LinInit(M4_USART_TypeDef *USARTx,
const stc_usart_lin_init_t *pstcInit);
en_result_t USART_LinStructInit(stc_usart_lin_init_t *pstcInit);
en_result_t USART_SmartcardInit(M4_USART_TypeDef *USARTx,
const stc_usart_smartcard_init_t *pstcInit);
en_result_t USART_SmartcardStructInit(stc_usart_smartcard_init_t *pstcInit);
en_result_t USART_ClkSyncInit(M4_USART_TypeDef *USARTx,
const stc_usart_clksync_init_t *pstcInit);
en_result_t USART_ClkSyncStructInit(stc_usart_clksync_init_t *pstcInit);
void USART_DeInit(M4_USART_TypeDef *USARTx);
void USART_FuncCmd(M4_USART_TypeDef *USARTx,
uint32_t u32Func,
en_functional_state_t enNewState);
en_functional_state_t USART_GetFuncState(const M4_USART_TypeDef *USARTx,
uint32_t u32Func);
en_flag_status_t USART_GetStatus(const M4_USART_TypeDef *USARTx,
uint32_t u32Flag);
void USART_ClearStatus(M4_USART_TypeDef *USARTx, uint32_t u32Flag);
void USART_SetTransmissionType(M4_USART_TypeDef *USARTx, uint32_t u32Type);
uint32_t USART_GetTransmissionType(const M4_USART_TypeDef *USARTx);
void USART_SetParity(M4_USART_TypeDef *USARTx, uint32_t u32Parity);
uint32_t USART_GetParity(const M4_USART_TypeDef *USARTx);
void USART_SetDataWidth(M4_USART_TypeDef *USARTx, uint32_t u32DataWidth);
uint32_t USART_GetDataWidth(const M4_USART_TypeDef *USARTx);
void USART_SetOversmaplingBits(M4_USART_TypeDef *USARTx,
uint32_t u32OversamplingBits);
uint32_t USART_GetOversmaplingBits(const M4_USART_TypeDef *USARTx);
void USART_SetBitDirection(M4_USART_TypeDef *USARTx, uint32_t u32BitDir);
uint32_t USART_GetBitDirection(const M4_USART_TypeDef *USARTx);
void USART_SetSbDetectPolarity(M4_USART_TypeDef *USARTx,
uint32_t u32Polarity);
uint32_t USART_GetSbDetectPolarity(const M4_USART_TypeDef *USARTx);
void USART_SetClockMode(M4_USART_TypeDef *USARTx, uint32_t u32ClkMode);
uint32_t USART_GetClockMode(const M4_USART_TypeDef *USARTx);
void USART_SetStopBits(M4_USART_TypeDef *USARTx, uint32_t u32StopBits);
uint32_t USART_GetStopBits(const M4_USART_TypeDef *USARTx);
uint16_t USART_RecData(const M4_USART_TypeDef *USARTx);
void USART_SendData(M4_USART_TypeDef *USARTx, uint16_t u16Data);
void USART_SendId(M4_USART_TypeDef *USARTx, uint16_t u16ID);
void USART_SilenceCmd(M4_USART_TypeDef *USARTx,
en_functional_state_t enNewState);
void USART_LinLoopCmd(M4_USART_TypeDef *USARTx,
en_functional_state_t enNewState);
void USART_LinRequestBreakSending(M4_USART_TypeDef *USARTx);
en_flag_status_t USART_GetLinRequestBreakStatus(const M4_USART_TypeDef *USARTx);
void USART_SetLinBreakMode(M4_USART_TypeDef *USARTx, uint32_t u32Mode);
uint32_t USART_GetLinBreakMode(const M4_USART_TypeDef *USARTx);
void USART_SetDuplexMode(M4_USART_TypeDef *USARTx, uint32_t u32Mode);
uint32_t USART_GetDuplexMode(const M4_USART_TypeDef *USARTx);
void USART_SetHwFlowCtrl(M4_USART_TypeDef *USARTx, uint32_t u32HwFlowCtrl);
uint32_t USART_GetHwFlowCtrl(const M4_USART_TypeDef *USARTx);
void USART_SetSmartcardEtuClk(M4_USART_TypeDef *USARTx,
uint32_t u32EtuClk);
uint32_t USART_GetSmartcardEtuClk(const M4_USART_TypeDef *USARTx);
void USART_SetPclkDiv(M4_USART_TypeDef *USARTx,
uint32_t u32PclkDiv);
uint32_t USART_GetPclkDiv(const M4_USART_TypeDef *USARTx);
void USART_SetLinBmcPclkDiv(M4_USART_TypeDef *USARTx,
uint32_t u32PclkDiv);
uint32_t USART_GetLinBmcPclkDiv(const M4_USART_TypeDef *USARTx);
void USART_SetStopModeNoiseFilter(const M4_USART_TypeDef *USARTx,
uint32_t u32Filter);
uint32_t USART_GetStopModeNoiseFilter(const M4_USART_TypeDef *USARTx);
void USART_LinFuncCmd(M4_USART_TypeDef *USARTx,
uint32_t u32Func,
en_functional_state_t enNewState);
en_functional_state_t USART_GetLinFuncState(const M4_USART_TypeDef *USARTx,
uint32_t u32Func);
uint32_t USART_GetLinMeasureCnt(const M4_USART_TypeDef *USARTx);
uint32_t USART_GetLinMeasureBaudrate(const M4_USART_TypeDef *USARTx);
void USART_SetLinDetectBreakLen(M4_USART_TypeDef *USARTx,
uint32_t u32Len);
uint32_t USART_GetLinDetectBreakLen(const M4_USART_TypeDef *USARTx);
void USART_SetLinSendBreakLen(M4_USART_TypeDef *USARTx, uint32_t u32Len);
uint32_t USART_GetLinSendBreakLen(const M4_USART_TypeDef *USARTx);
en_result_t USART_SetBaudrate(M4_USART_TypeDef *USARTx,
uint32_t u32Baudrate,
float32_t *pf32Err);
/**
* @}
*/
#endif /* DDL_USART_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_USART_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_utility.h
* @brief This file contains all the functions prototypes of the DDL utility.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_UTILITY_H__
#define __HC32F4A0_UTILITY_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_UTILITY
* @{
*/
#if (DDL_UTILITY_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup UTILITY_Global_Functions
* @{
*/
/* Imprecise delay */
void DDL_DelayMS(uint32_t u32Cnt);
void DDL_DelayUS(uint32_t u32Cnt);
/* Systick functions */
en_result_t SysTick_Init(uint32_t u32Freq);
void SysTick_Delay(uint32_t u32Delay);
void SysTick_IncTick(void);
uint32_t SysTick_GetTick(void);
void SysTick_Suspend(void);
void SysTick_Resume(void);
/* You can add your own assert functions by implement the function DDL_AssertHandler
definition follow the function DDL_AssertHandler declaration */
#ifdef __DEBUG
#define DDL_ASSERT(x) \
do{ \
((x) ? (void)0 : DDL_AssertHandler(__FILE__, __LINE__)); \
}while(0)
/* Exported function */
void DDL_AssertHandler(const char *file, int line);
#else
#define DDL_ASSERT(x) ((void)0U)
#endif /* __DEBUG */
#if (DDL_PRINT_ENABLE == DDL_ON)
#include <stdio.h>
en_result_t DDL_PrintfInit(void);
#endif
/**
* @}
*/
#endif /* DDL_UTILITY_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_UTILITY_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_wdt.h
* @brief This file contains all the functions prototypes of the WDT driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_WDT_H__
#define __HC32F4A0_WDT_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_WDT
* @{
*/
#if (DDL_WDT_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup WDT_Global_Types WDT Global Types
* @{
*/
/**
* @brief WDT Init structure definition
*/
typedef struct
{
uint32_t u32CountCycle; /*!< Specifies the WDT Count Cycle.
This parameter can be a value of @ref WDT_Counter_Cycle */
uint32_t u32ClockDivision; /*!< Specifies the WDT Clock Division.
This parameter can be a value of @ref WDT_Clock_Division */
uint32_t u32RefreshRange; /*!< Specifies the WDT Allow Refresh Range.
This parameter can be a value of @ref WDT_Refresh_Percent_Range */
uint32_t u32LPModeCountEn; /*!< Specifies the WDT Count Enable/Disable In Low Power Mode(Sleep Mode).
This parameter can be a value of @ref WDT_LPW_Mode_Count */
uint32_t u32TrigType; /*!< Specifies the WDT Refresh Error or Count Underflow trigger event Type.
This parameter can be a value of @ref WDT_Trigger_Event_Type */
} stc_wdt_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup WDT_Global_Macros WDT Global Macros
* @{
*/
/**
* @defgroup WDT_Counter_Cycle WDT Counter Cycle
* @{
*/
#define WDT_COUNTER_CYCLE_256 (0UL) /*!< 256 clock cycle */
#define WDT_COUNTER_CYCLE_4096 (WDT_CR_PERI_0) /*!< 4096 clock cycle */
#define WDT_COUNTER_CYCLE_16384 (WDT_CR_PERI_1) /*!< 16384 clock cycle */
#define WDT_COUNTER_CYCLE_65536 (WDT_CR_PERI) /*!< 65536 clock cycle */
/**
* @}
*/
/**
* @defgroup WDT_Clock_Division WDT Clock Division
* @{
*/
#define WDT_CLOCK_DIV4 (WDT_CR_CKS_1) /*!< PLCK3/4 */
#define WDT_CLOCK_DIV64 (WDT_CR_CKS_2 | WDT_CR_CKS_1) /*!< PLCK3/64 */
#define WDT_CLOCK_DIV128 (WDT_CR_CKS_2 | WDT_CR_CKS_1 | WDT_CR_CKS_0) /*!< PLCK3/128 */
#define WDT_CLOCK_DIV256 (WDT_CR_CKS_3) /*!< PLCK3/256 */
#define WDT_CLOCK_DIV512 (WDT_CR_CKS_3 | WDT_CR_CKS_0) /*!< PLCK3/512 */
#define WDT_CLOCK_DIV1024 (WDT_CR_CKS_3 | WDT_CR_CKS_1) /*!< PLCK3/1024 */
#define WDT_CLOCK_DIV2048 (WDT_CR_CKS_3 | WDT_CR_CKS_1 | WDT_CR_CKS_0) /*!< PLCK3/2048 */
#define WDT_CLOCK_DIV8192 (WDT_CR_CKS_3 | WDT_CR_CKS_2 | WDT_CR_CKS_0) /*!< PLCK3/8192 */
/**
* @}
*/
/**
* @defgroup WDT_Refresh_Percent_Range WDT Refresh Percent Range
* @{
*/
#define WDT_RANGE_0TO100PCT (0UL) /*!< 0%~100% */
#define WDT_RANGE_0TO25PCT (WDT_CR_WDPT_0) /*!< 0%~25% */
#define WDT_RANGE_25TO50PCT (WDT_CR_WDPT_1) /*!< 25%~50% */
#define WDT_RANGE_0TO50PCT (WDT_CR_WDPT_1 | WDT_CR_WDPT_0) /*!< 0%~50% */
#define WDT_RANGE_50TO75PCT (WDT_CR_WDPT_2) /*!< 50%~75% */
#define WDT_RANGE_0TO25PCT_50TO75PCT (WDT_CR_WDPT_2 | WDT_CR_WDPT_0) /*!< 0%~25% & 50%~75% */
#define WDT_RANGE_25TO75PCT (WDT_CR_WDPT_2 | WDT_CR_WDPT_1) /*!< 25%~75% */
#define WDT_RANGE_0TO75PCT (WDT_CR_WDPT_2 | WDT_CR_WDPT_1 | WDT_CR_WDPT_0) /*!< 0%~75% */
#define WDT_RANGE_75TO100PCT (WDT_CR_WDPT_3) /*!< 75%~100% */
#define WDT_RANGE_0TO25PCT_75TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_0) /*!< 0%~25% & 75%~100% */
#define WDT_RANGE_25TO50PCT_75TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_1) /*!< 25%~50% & 75%~100% */
#define WDT_RANGE_0TO50PCT_75TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_1 | WDT_CR_WDPT_0) /*!< 0%~50% & 75%~100% */
#define WDT_RANGE_50TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_2) /*!< 50%~100% */
#define WDT_RANGE_0TO25PCT_50TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_2 | WDT_CR_WDPT_0) /*!< 0%~25% & 50%~100% */
#define WDT_RANGE_25TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_2 | WDT_CR_WDPT_1) /*!< 25%~100% */
/**
* @}
*/
/**
* @defgroup WDT_LPW_Mode_Count WDT Low Power Mode Count
* @brief WDT count control in the sleep mode
* @{
*/
#define WDT_LPM_COUNT_CONTINUE (0UL) /*!< WDT count continue in the sleep mode */
#define WDT_LPM_COUNT_STOP (WDT_CR_SLPOFF) /*!< WDT count stop in the sleep mode */
/**
* @}
*/
/**
* @defgroup WDT_Trigger_Event_Type WDT Trigger Event Type
* @{
*/
#define WDT_TRIG_EVENT_INT (0UL) /*!< WDT trigger interrupt */
#define WDT_TRIG_EVENT_RESET (WDT_CR_ITS) /*!< WDT trigger reset */
/**
* @}
*/
/**
* @defgroup WDT_Flag WDT Flag
* @{
*/
#define WDT_FLAG_UDF (WDT_SR_UDF) /*!< Count underflow flag */
#define WDT_FLAG_REF (WDT_SR_REF) /*!< Refresh error flag */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup WDT_Global_Functions
* @{
*/
/**
* @brief Get WDT count value.
* @param None
* @retval Count value
*/
__STATIC_INLINE uint16_t WDT_GetCountValue(void)
{
return (uint16_t)(READ_REG32(M4_WDT->SR) & WDT_SR_CNT);
}
/* Initialization and configuration functions */
en_result_t WDT_Init(const stc_wdt_init_t *pstcWdtInit);
void WDT_Feed(void);
uint16_t WDT_GetCountValue(void);
/* Flags management functions */
en_flag_status_t WDT_GetStatus(uint32_t u32Flag);
en_result_t WDT_ClearStatus(uint32_t u32Flag);
/**
* @}
*/
#endif /* DDL_WDT_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_WDT_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_aes.c
* @brief This file provides firmware functions to manage the Advanced Encryption
* Standard(AES).
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Heqb First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32f4a0_aes.h"
#include "hc32f4a0_utility.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @defgroup DDL_AES AES
* @brief AES Driver Library
* @{
*/
#if (DDL_AES_ENABLE == DDL_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup AES_Local_Macros AES Local Macros
* @{
*/
/* Delay count for timeout */
#define AES_TIMEOUT (30000UL)
/**
* @defgroup AES_KEY_LENGTH AES key length in bytes
* @{
*/
#define AES_KEY_LEN_128BIT (16U)
#define AES_KEY_LEN_192BIT (24U)
#define AES_KEY_LEN_256BIT (32U)
/**
* @}
*/
/**
* @defgroup AES_Check_Parameters_Validity AES Check Parameters Validity
* @{
*/
#define IS_AES_KEYLENGTH(x) \
( ((x) == AES_KEY_LEN_128BIT) || \
((x) == AES_KEY_LEN_192BIT) || \
((x) == AES_KEY_LEN_256BIT))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
static void AES_WriteData(const uint8_t *pu8Srcdata);
static void AES_ReadData(const uint8_t *pu8Result);
static void AES_WriteKey(const uint8_t *pu8Key, uint8_t u8KeyLength);
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup AES_Global_Functions AES Global Functions
* @{
*/
/**
* @brief AES encryption.
* @param [in] au8Plaintext Buffer of the plaintext(the source data which will be encrypted).
* @param [in] u32PlaintextSize Length of plaintext in bytes.
* @param [in] pu8Key Pointer to the AES key.
* @param [in] u8KeyLength Buffer of the key in bytes.
* @param [out] au8Ciphertext Buffer of the ciphertext.
* @retval An en_result_t enumeration value:
* Ok: Encryption successfully.
* ErrorInvalidParameter: Invalid parameter
* ErrorTimeout: Encryption error timeout
*/
en_result_t AES_Encrypt(uint8_t au8Plaintext[],
uint32_t u32PlaintextSize,
const uint8_t *pu8Key,
uint8_t u8KeyLength,
uint8_t au8Ciphertext[])
{
en_result_t enRet = ErrorInvalidParameter;
uint32_t u32TimeCount = 0UL;
uint32_t u32Index = 0UL;
uint8_t au8FillBuffer[16U] = {0U};
if((au8Plaintext != NULL) && (u32PlaintextSize != 0UL) \
&& (pu8Key != NULL) && (u8KeyLength != 0U) \
&& (au8Ciphertext != NULL))
{
DDL_ASSERT(IS_AES_KEYLENGTH(u8KeyLength));
enRet = Ok;
while(u32PlaintextSize > 0UL)
{
/* Wait for AES to stop */
while(READ_REG32_BIT(M4_AES->CR, AES_CR_START) == 1U)
{
if(u32TimeCount++ >= AES_TIMEOUT)
{
enRet = ErrorTimeout;
break;
}
}
if (enRet == Ok)
{
if (u32PlaintextSize >= AES_BLOCK_LEN)
{
AES_WriteData(&au8Plaintext[u32Index]);
}
else
{
(void)memcpy(au8FillBuffer, &au8Plaintext[u32Index], u32PlaintextSize);
AES_WriteData(&au8FillBuffer[0U]);
}
AES_WriteKey(pu8Key, u8KeyLength);
switch (u8KeyLength)
{
case AES_KEY_LEN_128BIT:
MODIFY_REG32(M4_AES->CR, AES_CR_KEYSIZE, AES_KEY_SIZE_128BIT);
break;
case AES_KEY_LEN_192BIT:
MODIFY_REG32(M4_AES->CR, AES_CR_KEYSIZE, AES_KEY_SIZE_192BIT);
break;
case AES_KEY_LEN_256BIT:
MODIFY_REG32(M4_AES->CR, AES_CR_KEYSIZE, AES_KEY_SIZE_256BIT);
break;
default:
break;
}
/* Set AES encrypt. */
CLEAR_REG32_BIT(M4_AES->CR, AES_CR_MODE);
/* Start AES calculating. */
SET_REG32_BIT(M4_AES->CR, AES_CR_START);
/* Wait for AES to stop */
u32TimeCount = 0UL;
while(READ_REG32_BIT(M4_AES->CR, AES_CR_START) == 1U)
{
if(u32TimeCount++ > AES_TIMEOUT)
{
enRet = ErrorTimeout;
break;
}
}
if (enRet == Ok)
{
AES_ReadData(&au8Ciphertext[u32Index]);
if (u32PlaintextSize < AES_BLOCK_LEN)
{
u32PlaintextSize = 0UL;
}
else
{
u32PlaintextSize -= AES_BLOCK_LEN;
}
u32Index += AES_BLOCK_LEN;
}
}
}
}
return enRet;
}
/**
* @brief AES decryption.
* @param [in] au8Ciphertext Buffer of the Ciphertext(the source data which will be decrypted).
* @param [in] u32CiphertextSize Length of ciphertext in bytes.
* @param [in] pu8Key Pointer to the AES key.
* @param [in] u8KeyLength Length of key in bytes.
* @param [out] au8Plaintext Buffer of the plaintext.
* @retval An en_result_t enumeration value:
* Ok: Decryption successfully.
* ErrorInvalidParameter: Invalid parameter
* ErrorTimeout: Decryption error timeout
*/
en_result_t AES_Decrypt(uint8_t au8Ciphertext[],
uint32_t u32CiphertextSize,
const uint8_t *pu8Key,
uint8_t u8KeyLength,
uint8_t au8Plaintext[])
{
en_result_t enRet = Ok;
uint32_t u32TimeCount = 0UL;
uint32_t u32Index = 0UL;
if((au8Plaintext != NULL) && (u32CiphertextSize != 0UL) \
&& (pu8Key != NULL) && (u8KeyLength != 0U) \
&& (au8Ciphertext != NULL))
{
DDL_ASSERT(IS_AES_KEYLENGTH(u8KeyLength));
enRet = Ok;
while(u32CiphertextSize > 0UL)
{
/* Wait for AES to stop */
while(READ_REG32_BIT(M4_AES->CR, AES_CR_START) == 1U)
{
if(u32TimeCount++ > AES_TIMEOUT)
{
enRet = ErrorTimeout;
break;
}
}
if (enRet == Ok)
{
AES_WriteData(&au8Ciphertext[u32Index]);
AES_WriteKey(pu8Key, u8KeyLength);
switch (u8KeyLength)
{
case AES_KEY_LEN_128BIT:
MODIFY_REG32(M4_AES->CR, AES_CR_KEYSIZE, AES_KEY_SIZE_128BIT);
break;
case AES_KEY_LEN_192BIT:
MODIFY_REG32(M4_AES->CR, AES_CR_KEYSIZE, AES_KEY_SIZE_192BIT);
break;
case AES_KEY_LEN_256BIT:
MODIFY_REG32(M4_AES->CR, AES_CR_KEYSIZE, AES_KEY_SIZE_256BIT);
break;
default:
break;
}
/* Set AES decrypt. */
SET_REG32_BIT(M4_AES->CR, AES_CR_MODE);
/* Start AES calculating. */
SET_REG32_BIT(M4_AES->CR, AES_CR_START);
/* Wait for AES to stop */
u32TimeCount = 0UL;
while(READ_REG32_BIT(M4_AES->CR, AES_CR_START) == 1UL)
{
if(u32TimeCount++ >= AES_TIMEOUT)
{
enRet = ErrorTimeout;
break;
}
}
if (enRet == Ok)
{
AES_ReadData(&au8Plaintext[u32Index]);
u32CiphertextSize -= AES_BLOCK_LEN;
u32Index += AES_BLOCK_LEN;
}
}
}
}
return enRet;
}
/**
* @brief Write the input buffer in data register.
* @param [in] pu8Srcdata Point to the source data buffer.
* @retval None
*/
static void AES_WriteData(const uint8_t *pu8Srcdata)
{
uint8_t i;
uint32_t u32DrAddr = (uint32_t)&(M4_AES->DR0);
uint32_t u32SrcAddr = (uint32_t)pu8Srcdata;
for(i = 0U; i < 4U; i++)
{
RW_MEM32(u32DrAddr) = RW_MEM32(u32SrcAddr);
u32SrcAddr += 4UL;
u32DrAddr += 4UL;
}
}
/**
* @brief Read the from data register.
* @param [out] pu8Result Point to the result buffer.
* @retval None
*/
static void AES_ReadData(const uint8_t *pu8Result)
{
uint8_t i;
uint32_t u32DrAddr = (uint32_t)&(M4_AES->DR0);
uint32_t u32ResultAddr = (uint32_t)pu8Result;
for(i = 0U; i < 4U; i++)
{
RW_MEM32(u32ResultAddr) = RW_MEM32(u32DrAddr);
u32DrAddr += 4U;
u32ResultAddr += 4UL;
}
}
/**
* @brief Write the input buffer in key register.
* @param [in] pu8Key Pointer to the kry buffer.
* @param [in] u8KeyLength Length of key in bytes.
* @retval None
*/
static void AES_WriteKey(const uint8_t *pu8Key, uint8_t u8KeyLength)
{
uint8_t i;
uint8_t Length = 0U;
uint32_t u32KeyAddr = (uint32_t)&(M4_AES->KR0);
uint32_t u32DataAddr = (uint32_t)pu8Key;
switch (u8KeyLength)
{
case AES_KEY_LEN_128BIT:
Length = 4U;
break;
case AES_KEY_LEN_192BIT:
Length = 6U;
break;
case AES_KEY_LEN_256BIT:
Length = 8U;
break;
default:
break;
}
for(i = 0U; i < Length; i++)
{
RW_MEM32(u32KeyAddr) = RW_MEM32(u32DataAddr);
u32DataAddr += 4UL;
u32KeyAddr += 4UL;
}
}
/**
* @}
*/
#endif /* DDL_AES_ENABLE */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_cmp.c
* @brief This file provides firmware functions to manage the Comparator(CMP).
*
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Heqb First version
2020-08-31 Heqb Replace CMP_Delay300ns() with the function DDL_DelayUS()
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32f4a0_cmp.h"
#include "hc32f4a0_utility.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @defgroup DDL_CMP CMP
* @brief CMP Driver Library
* @{
*/
#if (DDL_CMP_ENABLE == DDL_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup CMP_Local_Macros CMP Local Macros
* @{
*/
/**
* @defgroup CMP_Check_Parameters_Validity CMP Check Parameters Validity
* @{
*/
#define IS_CMP_INSTANCE(x) \
( ((x) == M4_CMP1) || \
((x) == M4_CMP2) || \
((x) == M4_CMP3) || \
((x) == M4_CMP4))
#define IS_CMP_MODE(x) \
( ((x) == CMP_MODE_NORMAL) || \
((x) == CMP_MODE_WINDOW))
#define IS_CMP_CVSL_CH(x) \
( ((x) == CMP_CVSL_NONE) || \
((x) == CMP_CVSL_INP1) || \
((x) == CMP_CVSL_INP2) || \
((x) == CMP_CVSL_INP3) || \
((x) == CMP_CVSL_INP4))
#define IS_CMP1_CVSL_SOURCE(x) \
( ((x) == CMP1_INP3_NONE) || \
((x) == CMP1_INP3_CMP1_INP3) || \
((x) == CMP1_INP3_CMP2_INP3) || \
((x) == CMP1_INP2_NONE) || \
((x) == CMP1_INP2_PGA1) || \
((x) == CMP1_INP2_PGA2) || \
((x) == CMP1_INP2_CMP1_INP2))
#define IS_CMP3_CVSL_SOURCE(x) \
( ((x) == CMP3_INP3_NONE) || \
((x) == CMP3_INP3_CMP3_INP3) || \
((x) == CMP3_INP3_CMP4_INP3) || \
((x) == CMP3_INP2_NONE) || \
((x) == CMP3_INP2_PGA3) || \
((x) == CMP3_INP2_PGA4) || \
((x) == CMP3_INP2_CMP3_INP2))
#define IS_CMP_RVSL(x) \
( ((x) == CMP_RVSL_NONE) || \
((x) == CMP_RVSL_INM1) || \
((x) == CMP_RVSL_INM2) || \
((x) == CMP_RVSL_INM3) || \
((x) == CMP_RVSL_INM4))
#define IS_CMP_OUT_POLARITY(x) \
( ((x) == CMP_OUT_REVERSE_OFF) || \
((x) == CMP_OUT_REVERSE_ON))
#define IS_CMP_OUT_DETECT_EDGE(x) \
( ((x) == CMP_DETECT_EDGS_NONE) || \
((x) == CMP_DETECT_EDGS_RISING) || \
((x) == CMP_DETECT_EDGS_FALLING) || \
((x) == CMP_DETECT_EDGS_BOTH))
#define IS_CMP_OUT_FILTER(x) \
( ((x) == CMP_OUT_FILTER_NONE) || \
((x) == CMP_OUT_FILTER_PCLK3) || \
((x) == CMP_OUT_FILTER_PCLK3_DIV8) || \
((x) == CMP_OUT_FILTER_PCLK3_DIV32))
#define IS_CMP_TIMWIN_FUNC(x) \
( ((x) == CMP_TIMERWIN_OFF) || \
((x) == CMP_TIMERWIN_ON))
#define IS_CMP_TIMWIN_INVALIDLEVEL(x) \
( ((x) == CMP_TIMERWIN_INVALID_LEVEL_LOW) || \
((x) == CMP_TIMERWIN_INVALID_LEVEL_HIGH))
#define IS_CMP_TIMWIN_OUT_LEVEL(x) \
( ((x) == CMP_TIMERWIN_OUT_LEVEL_LOW) || \
((x) == CMP_TIMERWIN_OUT_LEVEL_HIGH))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup CMP_Global_Functions CMP Global Functions
* @{
*/
/**
* @brief Initialize structure stc_cmp_init_t variable with default value.
* @param [in] pstcCMP_InitStruct Pointer to a stc_cmp_init_t structure variable which will be initialized.
* @arg See the struct @ref stc_cmp_init_t.
* @retval Ok: Success
* ErrorInvalidParameter: Parameter error
*/
en_result_t CMP_StructInit(stc_cmp_init_t *pstcCMP_InitStruct)
{
en_result_t enRet = ErrorInvalidParameter;
if (pstcCMP_InitStruct != NULL)
{
pstcCMP_InitStruct->u8CmpCh = CMP_CVSL_NONE;
pstcCMP_InitStruct->u8RefVol = CMP_RVSL_NONE;
pstcCMP_InitStruct->u8OutDetectEdges = CMP_DETECT_EDGS_NONE;
pstcCMP_InitStruct->u8OutFilter = CMP_OUT_FILTER_NONE;
pstcCMP_InitStruct->u8OutPolarity = CMP_OUT_REVERSE_OFF;
enRet = Ok;
}
return enRet;
}
/**
* @brief De-initialize CMP unit
* @param [in] CMPx Pointer to CMP instance register base,This
* parameter can be one of the following values:
* @arg M0P_CMP1: CMP unit 1 instance register base
* @arg M0P_CMP2: CMP unit 2 instance register base
* @arg M0P_CMP3: CMP unit 3 instance register base
* @arg M0P_CMP4: CMP unit 4 instance register base
* @retval None
*/
void CMP_DeInit(M4_CMP_TypeDef *CMPx)
{
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
CLEAR_REG8(CMPx->MDR);
CLEAR_REG8(CMPx->FIR);
CLEAR_REG8(CMPx->OCR);
CLEAR_REG8(CMPx->PMSR);
CLEAR_REG16(CMPx->VISR);
CLEAR_REG16(CMPx->TWSR);
CLEAR_REG16(CMPx->TWPR);
}
/**
* @brief CMP normal mode initialize
* @param [in] CMPx Pointer to CMP instance register base
* This parameter can be one of the following values:
* @arg M4_CMP1: CMP unit 1 instance register base
* @arg M4_CMP2: CMP unit 2 instance register base
* @arg M4_CMP3: CMP unit 3 instance register base
* @arg M4_CMP4: CMP unit 4 instance register base
* @param [in] pstcCmpInit CMP function base parameter structure
* @arg See the structure definition for @ref stc_cmp_init_t
* @retval Ok: Success
* ErrorInvalidParameter: Parameter error
*/
en_result_t CMP_NormalModeInit(M4_CMP_TypeDef *CMPx,
const stc_cmp_init_t *pstcCmpInit)
{
en_result_t enRet = ErrorInvalidParameter;
/* Check CMPx instance and configuration structure*/
if (NULL != pstcCmpInit)
{
/* Check parameters */
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
DDL_ASSERT(IS_CMP_CVSL_CH(pstcCmpInit->u8CmpCh));
DDL_ASSERT(IS_CMP_RVSL(pstcCmpInit->u8RefVol));
DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(pstcCmpInit->u8OutDetectEdges));
DDL_ASSERT(IS_CMP_OUT_FILTER(pstcCmpInit->u8OutFilter));
DDL_ASSERT(IS_CMP_OUT_POLARITY(pstcCmpInit->u8OutPolarity));
/* Stop CMP compare */
CLEAR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
/* Set compare voltage */
WRITE_REG8(CMPx->PMSR, pstcCmpInit->u8CmpCh);
if((M4_CMP1 == CMPx) && ((pstcCmpInit->u8CmpCh == CMP_CVSL_INP2) ||
(pstcCmpInit->u8CmpCh == CMP_CVSL_INP3)))
{
DDL_ASSERT(IS_CMP1_CVSL_SOURCE(pstcCmpInit->u16CmpVol));
WRITE_REG8(CMPx->VISR, pstcCmpInit->u16CmpVol);
}
if((M4_CMP3 == CMPx) && ((pstcCmpInit->u8CmpCh == CMP_CVSL_INP2) ||
(pstcCmpInit->u8CmpCh == CMP_CVSL_INP3)))
{
DDL_ASSERT(IS_CMP3_CVSL_SOURCE(pstcCmpInit->u16CmpVol));
WRITE_REG8(CMPx->VISR, pstcCmpInit->u16CmpVol);
}
/* Set reference voltage */
MODIFY_REG8(CMPx->PMSR, CMP_PMSR_RVSL, pstcCmpInit->u8RefVol);
/* Delay 1us*/
DDL_DelayUS(1U);
/* Start CMP compare */
SET_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
/* Delay 1us*/
DDL_DelayUS(1U);
/* Set output filter and output detect edge and output polarity */
WRITE_REG8(CMPx->FIR, (pstcCmpInit->u8OutFilter | pstcCmpInit->u8OutDetectEdges));
WRITE_REG8(CMPx->OCR, pstcCmpInit->u8OutPolarity);
enRet = Ok;
}
return enRet;
}
/**
* @brief CMP window mode initialize
* @param [in] CMPx Pointer to CMP instance register base
* This parameter can be one of the following values:
* @arg M4_CMP1: Select CMP1 and CMP2 for window comparison
* @arg M4_CMP2: Select CMP1 and CMP2 for window comparison
* @arg M4_CMP3: Select CMP3 and CMP4 for window comparison
* @arg M4_CMP4: Select CMP3 and CMP4 for window comparison
* @param [in] pstcCmpInit Configuration structure for window mode initialize
* @arg See the structure definition for @ref stc_cmp_init_t
* @param [in] pstcCmpWinRef Configuration structure for window mode reference voltage
* @arg See the structure definition for @ref stc_cmp_win_ref_t
* @retval Ok: Success
* ErrorInvalidParameter: Parameter error
*/
en_result_t CMP_WindowModeInit(const M4_CMP_TypeDef *CMPx,
const stc_cmp_init_t *pstcCmpInit,
const stc_cmp_win_ref_t *pstcCmpWinRef)
{
en_result_t enRet = ErrorInvalidParameter;
/* Check configuration structure */
if (NULL != pstcCmpInit)
{
/* Check parameters */
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
DDL_ASSERT(IS_CMP_CVSL_CH(pstcCmpWinRef->u8CmpCh1));
DDL_ASSERT(IS_CMP_CVSL_CH(pstcCmpWinRef->u8CmpCh2));
DDL_ASSERT(IS_CMP_RVSL(pstcCmpWinRef->u8WinVolLow));
DDL_ASSERT(IS_CMP_RVSL(pstcCmpWinRef->u8WinVolHigh));
DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(pstcCmpInit->u8OutDetectEdges));
DDL_ASSERT(IS_CMP_OUT_FILTER(pstcCmpInit->u8OutFilter));
DDL_ASSERT(IS_CMP_OUT_POLARITY(pstcCmpInit->u8OutPolarity));
if((CMPx == M4_CMP1) || (CMPx == M4_CMP2))
{
/* Stop CMP1 CMP2 compare */
CLEAR_REG8_BIT(M4_CMP1->MDR, CMP_MDR_CENB);
CLEAR_REG8_BIT(M4_CMP2->MDR, CMP_MDR_CENB);
/* Set compare voltage */
WRITE_REG8(M4_CMP1->PMSR, pstcCmpWinRef->u8CmpCh1);
WRITE_REG8(M4_CMP1->VISR, pstcCmpWinRef->u16CmpVol);
WRITE_REG8(M4_CMP2->PMSR, pstcCmpWinRef->u8CmpCh2);
/* Set reference Voltage */
MODIFY_REG8(M4_CMP1->PMSR, CMP_PMSR_RVSL, pstcCmpWinRef->u8WinVolLow);
MODIFY_REG8(M4_CMP2->PMSR, CMP_PMSR_RVSL, pstcCmpWinRef->u8WinVolHigh);
/* Select window compare mode */
SET_REG8_BIT(M4_CMP2->MDR, CMP_MDR_CWDE);
/* Start CMP compare function */
SET_REG8_BIT(M4_CMP1->MDR, CMP_MDR_CENB);
SET_REG8_BIT(M4_CMP2->MDR, CMP_MDR_CENB);
/* Delay 1us*/
DDL_DelayUS(1U);
/* Set output filter and output detect edge and output polarity */
WRITE_REG8(M4_CMP2->FIR, pstcCmpInit->u8OutFilter | pstcCmpInit->u8OutDetectEdges);
WRITE_REG8(M4_CMP2->OCR, pstcCmpInit->u8OutPolarity);
}
else
{
/* Stop CMP3 CMP4 compare */
CLEAR_REG8_BIT(M4_CMP3->MDR, CMP_MDR_CENB);
CLEAR_REG8_BIT(M4_CMP4->MDR, CMP_MDR_CENB);
/* Set compare voltage */
WRITE_REG8(M4_CMP3->PMSR, pstcCmpWinRef->u8CmpCh1);
WRITE_REG8(M4_CMP3->VISR, pstcCmpWinRef->u16CmpVol);
WRITE_REG8(M4_CMP4->PMSR, pstcCmpWinRef->u8CmpCh2);
/* Set reference Voltage */
MODIFY_REG8(M4_CMP3->PMSR, CMP_PMSR_RVSL, pstcCmpWinRef->u8WinVolLow);
MODIFY_REG8(M4_CMP4->PMSR, CMP_PMSR_RVSL, pstcCmpWinRef->u8WinVolHigh);
/* Select window compare mode */
SET_REG8_BIT(M4_CMP4->MDR, CMP_MDR_CWDE);
/* Start CMP compare function */
SET_REG8_BIT(M4_CMP3->MDR, CMP_MDR_CENB);
SET_REG8_BIT(M4_CMP4->MDR, CMP_MDR_CENB);
/* Delay 1us*/
DDL_DelayUS(1U);
/* Set output filter and output detect edge and output polarity */
WRITE_REG8(M4_CMP4->FIR, pstcCmpInit->u8OutFilter | pstcCmpInit->u8OutDetectEdges);
WRITE_REG8(M4_CMP4->OCR, pstcCmpInit->u8OutPolarity);
}
enRet = Ok;
}
return enRet;
}
/**
* @brief Voltage compare function command
* @param [in] CMPx Pointer to CMP instance register base
* This parameter can be one of the following values:
* @arg M4_CMP1: CMP unit 1 instance register base
* @arg M4_CMP2: CMP unit 2 instance register base
* @arg M4_CMP3: CMP unit 3 instance register base
* @arg M4_CMP4: CMP unit 4 instance register base
* @param [in] enNewStatus The function new status.
* This parameter can be: Enable or Disable.
* @retval None
*/
void CMP_FuncCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus)
{
/* Check CMPx instance */
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewStatus));
if(Enable == enNewStatus)
{
SET_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
/* Delay 1us*/
DDL_DelayUS(1U);
}
else
{
CLEAR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
}
}
/**
* @brief Voltage compare interrupt function command
* @param [in] CMPx Pointer to CMP instance register base
* This parameter can be one of the following values:
* @arg M4_CMP1: CMP unit 1 instance register base
* @arg M4_CMP2: CMP unit 2 instance register base
* @arg M4_CMP3: CMP unit 3 instance register base
* @arg M4_CMP4: CMP unit 4 instance register base
* @param [in] enNewStatus The function new status.
* @arg This parameter can be: Enable or Disable.
* @retval None
*/
void CMP_IntCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus)
{
/* Check parameters */
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewStatus));
if(Enable == enNewStatus)
{
SET_REG8_BIT(CMPx->FIR, CMP_FIR_CIEN);
}
else
{
CLEAR_REG8_BIT(CMPx->FIR, CMP_FIR_CIEN);
}
}
/**
* @brief Voltage compare output command
* @param [in] CMPx Pointer to CMP instance register base
* This parameter can be one of the following values:
* @arg M4_CMP1: CMP unit 1 instance register base
* @arg M4_CMP2: CMP unit 2 instance register base
* @arg M4_CMP3: CMP unit 3 instance register base
* @arg M4_CMP4: CMP unit 4 instance register base
* @param [in] enNewStatus The function new status.
* @arg This parameter can be: Enable or Disable.
* @retval None
*/
void CMP_OutputCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus)
{
/* Check parameters */
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewStatus));
if(Enable == enNewStatus)
{
SET_REG8_BIT(CMPx->OCR, CMP_OCR_COEN);
}
else
{
CLEAR_REG8_BIT(CMPx->OCR, CMP_OCR_COEN);
}
}
/**
* @brief Voltage compare output port VCOUT function command
* @param [in] CMPx Pointer to CMP instance register base
* This parameter can be one of the following values:
* @arg M4_CMP1: CMP unit 1 instance register base
* @arg M4_CMP2: CMP unit 2 instance register base
* @arg M4_CMP3: CMP unit 3 instance register base
* @arg M4_CMP4: CMP unit 4 instance register base
* @param [in] enNewStatus The function new status.
* This parameter can be: Enable or Disable.
* @retval None
*/
void CMP_VCOUTCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus)
{
/* Check parameters */
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewStatus));
if(Enable == enNewStatus)
{
SET_REG8_BIT(CMPx->OCR, CMP_OCR_CPOE);
}
else
{
CLEAR_REG8_BIT(CMPx->OCR, CMP_OCR_CPOE);
}
}
/**
* @brief Voltage compare result flag read
* @param [in] CMPx Pointer to CMP instance register base
* This parameter can be one of the following values:
* @arg M4_CMP1: CMP unit 1 instance register base
* @arg M4_CMP2: CMP unit 2 instance register base
* @arg M4_CMP3: CMP unit 3 instance register base
* @arg M4_CMP4: CMP unit 4 instance register base
* @retval In normal mode:
* Reset: compare voltage < reference voltage
* Set: compare voltage > reference voltage
* In Window mode:
* Reset: compare voltage < reference low voltage or
* compare voltage > reference high voltage
* Set: reference low voltage < compare voltage < reference high voltage
*/
en_flag_status_t CMP_GetResult(const M4_CMP_TypeDef *CMPx)
{
en_flag_status_t enRet;
/* Check CMPx instance */
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
enRet = READ_REG8_BIT(CMPx->MDR, CMP_MDR_CMON) ? Set : Reset;
return enRet;
}
/**
* @brief Voltage compare timer window function configuration
* @param [in] CMPx Pointer to CMP instance register base
* This parameter can be one of the following values:
* @arg M4_CMP1: CMP unit 1 instance register base
* @arg M4_CMP2: CMP unit 2 instance register base
* @arg M4_CMP3: CMP unit 3 instance register base
* @arg M4_CMP4: CMP unit 4 instance register base
* @param [in] pstcCMP_TimerWinStruct Configuration structure for Timer window mode.
* @retval Ok: Successfully
* ErrorInvalidParameter: Parameter error
*/
en_result_t CMP_TimerWindowConfig(M4_CMP_TypeDef *CMPx,
const stc_cmp_timerwindow_t *pstcCMP_TimerWinStruct)
{
en_result_t enRet = ErrorInvalidParameter;
/* Check CMPx instance and configuration structure*/
if (NULL != pstcCMP_TimerWinStruct)
{
enRet = Ok;
/* Check parameters */
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
DDL_ASSERT(IS_CMP_TIMWIN_INVALIDLEVEL(pstcCMP_TimerWinStruct->u8TWInvalidLevel));
DDL_ASSERT(IS_CMP_TIMWIN_OUT_LEVEL(pstcCMP_TimerWinStruct->u8TWOutLevel));
/* Select timer window mode */
SET_REG8_BIT(CMPx->OCR, CMP_OCR_TWOE);
/* Select output level when timer window invalid */
MODIFY_REG8(CMPx->OCR, CMP_OCR_TWOL, pstcCMP_TimerWinStruct->u8TWInvalidLevel);
/* Select Timer window source */
WRITE_REG16(CMPx->TWSR, pstcCMP_TimerWinStruct->u16TWSelect);
/* Select timer window mode output level */
if(CMP_TIMERWIN_OUT_LEVEL_HIGH == pstcCMP_TimerWinStruct->u8TWOutLevel)
{
SET_REG16_BIT(CMPx->TWPR, pstcCMP_TimerWinStruct->u16TWSelect);
}
else
{
CLEAR_REG16_BIT(CMPx->TWPR, pstcCMP_TimerWinStruct->u16TWSelect);
}
}
return enRet;
}
/**
* @brief Set output detect edge
* @param [in] CMPx Pointer to CMP instance register base
* This parameter can be one of the following values:
* @arg M4_CMP1: CMP unit 1 instance register base
* @arg M4_CMP2: CMP unit 2 instance register base
* @arg M4_CMP3: CMP unit 3 instance register base
* @arg M4_CMP4: CMP unit 4 instance register base
* @param [in] u8CmpEdges CMP output detect edge selection.
* This parameter can be one of the following values:
* @arg CMP_DETECT_EDGS_NONE: Do not detect edge
* @arg CMP_DETECT_EDGS_RISING: Detect rising edge
* @arg CMP_DETECT_EDGS_FALLING: Detect falling edge
* @arg CMP_DETECT_EDGS_BOTH: Detect rising and falling edges
* @retval None
*/
void CMP_SetOutDetectEdges(M4_CMP_TypeDef *CMPx, uint8_t u8CmpEdges)
{
uint8_t u8temp;
/* Check parameters */
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(u8CmpEdges));
/* Read CMP status */
u8temp = READ_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
/* Stop CMP function */
CLEAR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
/* CMP output detect edge selection */
MODIFY_REG8(CMPx->FIR, CMP_FIR_EDGS, u8CmpEdges);
if(u8temp != 0U)
{
/* Recover CMP status */
MODIFY_REG8(CMPx->MDR, CMP_MDR_CENB, u8temp);
/* Delay 1us */
DDL_DelayUS(1U);
}
}
/**
* @brief Set output filter
* @param [in] CMPx Pointer to CMP instance register base
* This parameter can be one of the following values:
* @arg M4_CMP1: CMP unit 1 instance register base
* @arg M4_CMP2: CMP unit 2 instance register base
* @arg M4_CMP3: CMP unit 3 instance register base
* @arg M4_CMP4: CMP unit 4 instance register base
* @param [in] u8CmpFilter CMP output filter selection.
* This parameter can be one of the following values:
* @arg CMP_OUT_FILTER_NONE: Don't filter
* @arg CMP_OUT_FILTER_PCLK3: Use PCLK3
* @arg CMP_OUT_FILTER_PCLK3_DIV8: Use PCLK3 / 8
* @arg CMP_OUT_FILTER_PCLK3_DIV32: Use PCLK3 / 32
* @retval None
*/
void CMP_SetOutputFilter(M4_CMP_TypeDef *CMPx, uint8_t u8CmpFilter)
{
uint8_t u8temp;
/* Check parameters */
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
DDL_ASSERT(IS_CMP_OUT_FILTER(u8CmpFilter));
/* Read CMP status */
u8temp = READ_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
/* Stop CMP function */
CLEAR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
/* CMP output filter selection */
MODIFY_REG8(CMPx->FIR, CMP_FIR_FCKS, u8CmpFilter);
if(u8temp != 0U)
{
/* Recover CMP status */
MODIFY_REG8(CMPx->MDR, CMP_MDR_CENB, u8temp);
/* Delay 1us */
DDL_DelayUS(1U);
}
}
/**
* @brief Set output polarity
* @param [in] CMPx Pointer to CMP instance register base
* This parameter can be one of the following values:
* @arg M4_CMP1: CMP unit 1 instance register base
* @arg M4_CMP2: CMP unit 2 instance register base
* @arg M4_CMP3: CMP unit 3 instance register base
* @arg M4_CMP4: CMP unit 4 instance register base
* @param [in] u8CmpPolarity CMP output polarity selection.
* This parameter can be one of the following values:
* @arg CMP_OUT_REVERSE_OFF: CMP output don't reverse
* @arg CMP_OUT_REVERSE_ON: CMP output level reverse
* @retval None
*/
void CMP_SetOutputPolarity(M4_CMP_TypeDef *CMPx, uint8_t u8CmpPolarity)
{
uint8_t u8temp;
/* Check parameters */
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
DDL_ASSERT(IS_CMP_OUT_POLARITY(u8CmpPolarity));
/* Read CMP status */
u8temp = READ_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
/* Stop CMP function */
CLEAR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
/* CMP output polarity selection */
MODIFY_REG8(CMPx->OCR, CMP_OCR_COPS, u8CmpPolarity);
if(u8temp != 0U)
{
/* Recover CMP status */
MODIFY_REG8(CMPx->MDR, CMP_MDR_CENB, u8temp);
/* Delay 1us */
DDL_DelayUS(1U);
}
}
/**
* @brief Set compare voltage
* @param [in] CMPx Pointer to CMP instance register base
* This parameter can be one of the following values:
* @arg M4_CMP1: CMP unit 1 instance register base
* @arg M4_CMP2: CMP unit 2 instance register base
* @arg M4_CMP3: CMP unit 3 instance register base
* @arg M4_CMP4: CMP unit 4 instance register base
* @param [in] u8CmpCh Select the compare voltage.
* This parameter can be one of the following values:
* @arg CMP_CVSL_NONE: Don't input compare voltage
* @arg CMP_CVSL_INP1: Select INP1 as compare voltage
* @arg CMP_CVSL_INP2: Select INP2 as compare voltage
* @arg CMP_CVSL_INP3: Select INP3 as compare voltage
* @arg CMP_CVSL_INP4: Select INP4 as compare voltage
* @param [in] u8CmpVol Select the compare voltage source (Config the parameter when use CMP1 or CMP3)
* This parameter can be one of the following values:
* When use CMP1:
* @arg CMP1_INP3_NONE: Don't input voltage to CMP1 INP3
* @arg CMP1_INP3_CMP1_INP3: Select CMP1_INP3 as CMP1 INP3 input
* @arg CMP1_INP3_CMP2_INP3: Select CMP2_INP3 as CMP1 INP3 input
* @arg CMP1_INP2_NONE: Don't input voltage to CMP1 INP2
* @arg CMP1_INP2_PGA1: Select PGA1 as CMP1 INP2 input
* @arg CMP1_INP2_PGA2: Select PGA2 as CMP1 INP2 input
* @arg CMP1_INP2_CMP1_INP2: Select CMP1_INP2 as CMP1 INP2 input
* When use CMP3:
* @arg CMP3_INP3_NONE: Don't input voltage to CMP3 INP3
* @arg CMP3_INP3_CMP3_INP3: Select CMP3_INP3 as CMP3 INP3 input
* @arg CMP3_INP3_CMP4_INP3: Select CMP4_INP3 as CMP3 INP3 input
* @arg CMP3_INP2_NONE: Don't input voltage to CMP3 INP2
* @arg CMP3_INP2_PGA3: Select PGA3 as CMP3 INP2 input
* @arg CMP3_INP2_PGA4: Select PGA4 as CMP3 INP2 input
* @arg CMP3_INP2_CMP3_INP2: Select CMP3_INP2 as CMp3 INP2 input
* @retval None
* @note When use INP1 or INP4, please set u8CmpVol to 0
*/
void CMP_SetCompareVol(M4_CMP_TypeDef *CMPx, uint8_t u8CmpCh, uint8_t u8CmpVol)
{
uint8_t u8temp;
/* Check parameters */
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
DDL_ASSERT(IS_CMP_CVSL_CH(u8CmpCh));
/* Read CMP status */
u8temp = READ_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
/* Stop CMP function */
CLEAR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
/* Set compare voltage */
MODIFY_REG8(CMPx->PMSR, CMP_PMSR_CVSL, u8CmpCh);
if((M4_CMP1 == CMPx) && ((u8CmpCh == CMP_CVSL_INP2) || (u8CmpCh == CMP_CVSL_INP3)))
{
DDL_ASSERT(IS_CMP1_CVSL_SOURCE(u8CmpVol));
WRITE_REG8(CMPx->VISR, u8CmpVol);
}
if((M4_CMP3 == CMPx) && ((u8CmpCh == CMP_CVSL_INP2) || (u8CmpCh == CMP_CVSL_INP3)))
{
DDL_ASSERT(IS_CMP3_CVSL_SOURCE(u8CmpVol));
WRITE_REG8(CMPx->VISR, u8CmpVol);
}
if(u8temp != 0U)
{
/* Recover CMP status */
MODIFY_REG8(CMPx->MDR, CMP_MDR_CENB, u8temp);
/* Delay 1us */
DDL_DelayUS(1U);
}
}
/**
* @brief Set reference voltage
* @param [in] CMPx Pointer to CMP instance register base
* This parameter can be one of the following values:
* @arg M4_CMP1: CMP unit 1 instance register base
* @arg M4_CMP2: CMP unit 2 instance register base
* @arg M4_CMP3: CMP unit 3 instance register base
* @arg M4_CMP4: CMP unit 4 instance register base
* @param [in] u8RefVol Select the reference voltage.
* This parameter can be one of the following values:
* @arg CMP_RVSL_NONE: Don't input reference voltage
* @arg CMP_RVSL_INM1: Select INM1 as reference voltage
* @arg CMP_RVSL_INM2: Select INM2 as reference voltage
* @arg CMP_RVSL_INM3: Select INM3 as reference voltage
* @arg CMP_RVSL_INM4: Select INM4 as reference voltage
* @retval None
*/
void CMP_SetRefVol(M4_CMP_TypeDef *CMPx, uint8_t u8RefVol)
{
uint8_t u8temp;
/* Check parameters */
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
DDL_ASSERT(IS_CMP_RVSL(u8RefVol));
/* Read CMP status */
u8temp = READ_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
/* Stop CMP function */
CLEAR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
/* Set reference voltage */
MODIFY_REG8(CMPx->PMSR, CMP_PMSR_RVSL, u8RefVol);
if(u8temp != 0U)
{
/* Recover CMP status */
MODIFY_REG8(CMPx->MDR, CMP_MDR_CENB, u8temp);
/* Delay 1us */
DDL_DelayUS(1U);
}
}
/**
* @brief Ste CMP Timer window signal.
* @param [in] CMPx Pointer to CMP instance register base
* This parameter can be one of the following values:
* @arg M4_CMP1: CMP unit 1 instance register base
* @arg M4_CMP2: CMP unit 2 instance register base
* @arg M4_CMP3: CMP unit 3 instance register base
* @arg M4_CMP4: CMP unit 4 instance register base
* @param [in] u16TWSignal Selection timer window signal
* This parameter can be value of @ref CMP_TimerWin_Select
* @param [in] enNewStatus The function new status.
* This parameter can be: Enable or Disable.
* @retval None
*/
void CMP_SetTimerWinSignal(M4_CMP_TypeDef *CMPx, \
uint16_t u16TWSignal, en_functional_state_t enNewStatus)
{
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewStatus));
DDL_ASSERT(IS_CMP_INSTANCE(CMPx));
if (enNewStatus == Enable)
{
MODIFY_REG16(CMPx->TWSR, u16TWSignal, u16TWSignal);
}
else
{
CLEAR_REG16_BIT(CMPx->TWSR, u16TWSignal);
}
}
/**
* @}
*/
#endif /* DDL_CMP_ENABLE */
/**
* @}
*/
/**
* @}
*/
/******************************************************************************
* EOF (not truncated)
*****************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_crc.c
* @brief This file provides firmware functions to manage the Cyclic Redundancy
* Check(CRC).
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Heqb First version
2020-07-21 Heqb Fixed a bug for CRC_Check function
2020-08-11 Heqb Modify macro definition name IS_CRC_PROCOTOL
to IS_CRC_PROTOCOL
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32f4a0_crc.h"
#include "hc32f4a0_utility.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @defgroup DDL_CRC CRC
* @brief Cyclic Redundancy Check Driver Library
* @{
*/
#if (DDL_CRC_ENABLE == DDL_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup CRC_Local_Macros CRC Local Macros
* @{
*/
/**
* @defgroup CRC_Check_Parameters_Validity CRC check parameters validity
* @{
*/
#define IS_CRC_PROTOCOL(x) \
( ((x) == CRC_CRC16) || \
((x) == CRC_CRC32))
#define IS_CRC_BIT_WIDTH(x) \
( ((x) == CRC_BW_8) || \
((x) == CRC_BW_16) || \
((x) == CRC_BW_32))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/**
* @defgroup CRC_Local_Functions CRC Local Functions
* @{
*/
static void CRC_8BitWrite(const uint8_t au8Data[], uint32_t u32Length);
static void CRC_16BitWrite(const uint16_t au16Data[], uint32_t u32Length);
static void CRC_32BitWrite(const uint32_t au32Data[], uint32_t u32Length);
/**
* @}
*/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup CRC_Global_Functions CRC Global Functions
* @{
*/
/**
* @brief CRC16 calculation.
* @param [in] u32CrcProtocol CRC protocol control bit.
* This parameter can be a value of @ref CRC_Protocol_Control_Bit
* @param [in] pvData Pointer to the buffer containing the data to be computed.
* @param [in] u32InitVal Initialize the CRC calculation.
* @param [in] u32Length The length(countted in bytes or half word or word, depending on
* the bit width) of the data to be computed.
* @param [in] u8BitWidth Bit width of the data.
* @arg CRC_BW_8: 8 Bit.
* @arg CRC_BW_16: 16 Bit.
* @arg CRC_BW_32: 32 Bit.
* @retval CRC checksum.
*/
uint32_t CRC_Calculate(uint32_t u32CrcProtocol,
const void *pvData,
uint32_t u32InitVal,
uint32_t u32Length,
uint8_t u8BitWidth)
{
uint32_t u32CheckSum = 0UL;
if ((pvData != NULL) && (u32Length != 0U))
{
DDL_ASSERT(IS_CRC_PROTOCOL(u32CrcProtocol));
DDL_ASSERT(IS_CRC_BIT_WIDTH(u8BitWidth));
/* Set operation mode (CRC16 or CRC32) */
WRITE_REG32(M4_CRC->CR, u32CrcProtocol);
/* Set initial value */
if (u32CrcProtocol == CRC_CRC32)
{
WRITE_REG32(M4_CRC->RESLT, u32InitVal);
}
else
{
WRITE_REG16(M4_CRC->RESLT, u32InitVal);
}
/* Write data */
if (u8BitWidth == CRC_BW_8)
{
CRC_8BitWrite(pvData, u32Length);
}
else if (u8BitWidth == CRC_BW_16)
{
CRC_16BitWrite(pvData, u32Length);
}
else
{
CRC_32BitWrite(pvData, u32Length);
}
/* Get checksum */
if (u32CrcProtocol == CRC_CRC32)
{
u32CheckSum = READ_REG32(M4_CRC->RESLT);
}
else
{
u32CheckSum = READ_REG16(M4_CRC->RESLT);
}
}
return u32CheckSum;
}
/**
* @brief CRC check.
* @param [in] u32CrcProtocol CRC protocol control bit.
* This parameter can be a value of @ref CRC_Protocol_Control_Bit
* @param [in] u32CheckSum The checksum of the data pointed by pointer pvData.
* @param [in] pvData Pointer to the buffer containing the data to be checked.
* @param [in] u32InitVal Initialize the CRC calculation.
* @param [in] u32Length The length(countted in bytes or half word or word, depending on
* the bit width) of the data to be computed.
* @param [in] u8BitWidth Bit width of the data.
* @arg CRC_BW_8: 8 Bit.
* @arg CRC_BW_16: 16 Bit.
* @arg CRC_BW_32: 32 Bit.
* @retval A en_flag_status_t value.
* @arg Set: CRC checks successfully.
* @arg Reset: CRC checks unsuccessfully.
*/
en_flag_status_t CRC_Check(uint32_t u32CrcProtocol,
uint32_t u32CheckSum,
const void *pvData,
uint32_t u32InitVal,
uint32_t u32Length,
uint8_t u8BitWidth)
{
en_flag_status_t enFlag = Reset;
uint32_t u32DataAddr = (uint32_t)&M4_CRC->DAT0;
DDL_ASSERT(IS_CRC_PROTOCOL(u32CrcProtocol));
DDL_ASSERT(IS_CRC_BIT_WIDTH(u8BitWidth));
if ((pvData != NULL) && (u32Length != 0UL))
{
/* Set operation mode (CRC16 or CRC32) */
WRITE_REG32(M4_CRC->CR, u32CrcProtocol);
/* Set initial value */
if (u32CrcProtocol == CRC_CRC32)
{
WRITE_REG32(M4_CRC->RESLT, u32InitVal);
}
else
{
WRITE_REG16(M4_CRC->RESLT, u32InitVal);
}
/* Write data */
if (u8BitWidth == CRC_BW_8)
{
CRC_8BitWrite(pvData, u32Length);
}
else if (u8BitWidth == CRC_BW_16)
{
CRC_16BitWrite(pvData, u32Length);
}
else
{
CRC_32BitWrite(pvData, u32Length);
}
/* Write checksum */
if (u32CrcProtocol == CRC_CRC32)
{
RW_MEM32(u32DataAddr) = u32CheckSum;
}
else
{
RW_MEM16(u32DataAddr) = (uint16_t)u32CheckSum;
}
/* Get flag */
if (READ_REG32_BIT(M4_CRC->CR, CRC_CR_FLAG) != 0UL)
{
enFlag = Set;
}
}
return enFlag;
}
/**
* @}
*/
/**
* @addtogroup CRC_Local_Functions CRC Local Functions
* @{
*/
/**
* @brief Write CRC data register in bytes.
* @param [in] au8Data The buffer for writing.
* @param [in] u32Length The length of data the in bytes.
* @retval None
*/
static void CRC_8BitWrite(const uint8_t au8Data[], uint32_t u32Length)
{
uint32_t i;
const uint32_t u32DataAddr = (uint32_t)(&M4_CRC->DAT0);
for (i = 0UL; i < u32Length; i++)
{
RW_MEM8(u32DataAddr) = au8Data[i];
}
}
/**
* @brief Write CRC data register in half words.
* @param [in] au16Data The buffer for writing.
* @param [in] u32Length The length of the data in half words.
* @retval None
*/
static void CRC_16BitWrite(const uint16_t au16Data[], uint32_t u32Length)
{
uint32_t i;
const uint32_t u32DataAddr = (uint32_t)(&M4_CRC->DAT0);
for (i = 0UL; i < u32Length; i++)
{
RW_MEM16(u32DataAddr) = au16Data[i];
}
}
/**
* @brief Write CRC data register in words.
* @param [in] au32Data The buffer for writing.
* @param [in] u32Length The length of the data in words.
* @retval None
*/
static void CRC_32BitWrite(const uint32_t au32Data[], uint32_t u32Length)
{
uint32_t i;
const uint32_t u32DataAddr = (uint32_t)(&M4_CRC->DAT0);
for (i = 0UL; i < u32Length; i++)
{
RW_MEM32(u32DataAddr) = au32Data[i];
}
}
/**
* @}
*/
#endif /* DDL_CRC_ENABLE */
/**
* @}
*/
/**
* @}
*/
/******************************************************************************
* EOF (not truncated)
*****************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_ctc.c
* @brief This file provides firmware functions to manage the Clock Trimming
* Controller(CTC).
@verbatim
Change Logs:
Date Author Notes
2020-09-01 Hongjh First version
2020-10-30 Hongjh Modify for refining CTC initialization structure
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32f4a0_ctc.h"
#include "hc32f4a0_utility.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @defgroup DDL_CTC CTC
* @brief CTC Driver Library
* @{
*/
#if (DDL_CTC_ENABLE == DDL_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup CTC_Local_Macros CTC Local Macros
* @{
*/
/**
* @defgroup CTC_Check_Parameters_Validity CTC Check Parameters Validity
* @{
*/
#define IS_CTC_REF_CLK_SRC(x) \
( ((x) == CTC_REF_CLK_XTAL) || \
((x) == CTC_REF_CLK_XTAL32) || \
((x) == CTC_REF_CLK_CTCREF))
#define IS_CTC_REF_CLK_DIV(x) \
( ((x) == CTC_REF_CLK_DIV8) || \
((x) == CTC_REF_CLK_DIV32) || \
((x) == CTC_REF_CLK_DIV128) || \
((x) == CTC_REF_CLK_DIV256) || \
((x) == CTC_REF_CLK_DIV512) || \
((x) == CTC_REF_CLK_DIV1024) || \
((x) == CTC_REF_CLK_DIV2048) || \
((x) == CTC_REF_CLK_DIV4096))
#define IS_CTC_OFFSET_VALUE(x) ((x) <= 0xFFUL)
#define IS_CTC_RELOAD_VALUE(x) ((x) <= 0xFFFFUL)
#define IS_CTC_TRIM_VALUE(x) ((x) <= 0x3FUL)
#define IS_CTC_TOLERANCE_DEVIATION(x) (((x) >= 0.0F) && \
((x) <= CTC_TOLERANCE_DEVIATION_MAX))
#define IS_CTC_FLAG(x) \
( ((x) != 0UL) && \
(((x) | CTC_FLAG_ALL) == CTC_FLAG_ALL))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup CTC_Global_Functions CTC Global Functions
* @{
*/
/**
* @brief Initialize CTC function.
* @param [in] pstcCtcInit Pointer to a @ref stc_ctc_init_t structure.
* @retval An en_result_t enumeration value:
* - Ok: Initialize success
* - ErrorNotReady: CTC state is busy
* - ErrorInvalidParameter: If one of following cases matches:
* - pstcCtcInit is NULL
* - Reference frequency is out of range
* - Calculate reload & offset value out of range
*/
en_result_t CTC_Init(const stc_ctc_init_t *pstcCtcInit)
{
float f32OffsetValue;
uint32_t u32RegValue;
uint32_t u32ReloadValue;
uint32_t u32OffsetValue;
uint32_t u32RefClockDiv;
uint32_t u32Multiplier;
uint64_t u64InterClock;
uint32_t u32HrcFreq = HRC_VALUE;
en_result_t enRet = ErrorNotReady;
/* Check CTC status */
if (CTC_FLAG_BUSY != (READ_REG32_BIT(M4_CTC->STR, CTC_FLAG_BUSY)))
{
if ((NULL == pstcCtcInit) || (0UL == pstcCtcInit->u32RefClockFreq))
{
enRet = ErrorInvalidParameter;
}
else
{
/* Check parameters */
DDL_ASSERT(IS_CTC_REF_CLK_SRC(pstcCtcInit->u32RefClockSrc));
DDL_ASSERT(IS_CTC_REF_CLK_DIV(pstcCtcInit->u32RefClockDiv));
DDL_ASSERT(IS_CTC_TRIM_VALUE(pstcCtcInit->u32TrimValue));
DDL_ASSERT(IS_CTC_TOLERANCE_DEVIATION(pstcCtcInit->f32ToleranceDeviation));
if (pstcCtcInit->u32RefClockDiv < CTC_REF_CLK_DIV128)
{
u32RefClockDiv = (8UL << (2UL * pstcCtcInit->u32RefClockDiv));
}
else
{
u32RefClockDiv = (32UL << pstcCtcInit->u32RefClockDiv);
}
u64InterClock = ((uint64_t)u32HrcFreq) * ((uint64_t)(u32RefClockDiv));
u32Multiplier = (uint32_t)(u64InterClock / pstcCtcInit->u32RefClockFreq);
/* Calculate offset value formula: OFSVAL = (Fhrc / (Fref * Fref_divsion)) * TA */
f32OffsetValue = ((float)u32Multiplier) * (pstcCtcInit->f32ToleranceDeviation);
u32OffsetValue = (uint32_t)(f32OffsetValue);
/* Calculate reload value formula: RLDVAL = (Fhrc / (Fref * Fref_divsion)) + OFSVAL */
u32ReloadValue = u32Multiplier + u32OffsetValue;
if ((IS_CTC_OFFSET_VALUE(u32OffsetValue)) && (IS_CTC_RELOAD_VALUE(u32ReloadValue)))
{
/* Set CR1 */
u32RegValue = (pstcCtcInit->u32RefClockDiv | \
pstcCtcInit->u32RefClockSrc | \
(pstcCtcInit->u32TrimValue << CTC_CR1_TRMVAL_POS));
WRITE_REG32(M4_CTC->CR1, u32RegValue);
/* Set CR2 */
u32RegValue = ((u32ReloadValue << CTC_CR2_RLDVAL_POS) | u32OffsetValue);
WRITE_REG32(M4_CTC->CR2, u32RegValue);
enRet = Ok;
}
}
}
return enRet;
}
/**
* @brief Set the fields of structure stc_uart_init_t to default values.
* @param [out] pstcCtcInit Pointer to a @ref stc_ctc_init_t structure.
* @retval An en_result_t enumeration value:
* - Ok: Initialize success
* - ErrorInvalidParameter: pstcCtcInit is NULL
*/
en_result_t CTC_StructInit(stc_ctc_init_t *pstcCtcInit)
{
en_result_t enRet = ErrorInvalidParameter;
/* Check parameters */
if (NULL != pstcCtcInit)
{
pstcCtcInit->u32RefClockFreq = 0UL;
pstcCtcInit->u32RefClockSrc = CTC_REF_CLK_CTCREF;
pstcCtcInit->u32RefClockDiv = CTC_REF_CLK_DIV8;
pstcCtcInit->f32ToleranceDeviation = 0.0F;
pstcCtcInit->u32TrimValue = 0UL;
enRet = Ok;
}
return enRet;
}
/**
* @brief De-Initialize CTC function.
* @param None
* @retval An en_result_t enumeration value:
* - Ok: De-Initialize success
* - ErrorNotReady: CTC state is busy
*/
en_result_t CTC_DeInit(void)
{
en_result_t enRet = ErrorNotReady;
/* Check CTC status */
if (CTC_FLAG_BUSY != (READ_REG32_BIT(M4_CTC->STR, CTC_FLAG_BUSY)))
{
/* Configures the registers to reset value. */
WRITE_REG32(M4_CTC->CR1, 0UL);
WRITE_REG32(M4_CTC->CR2, 0UL);
enRet = Ok;
}
return enRet;
}
/**
* @brief Set CTC reference clock division.
* @param [in] u32Div CTC reference clock prescaler
* This parameter can be one of the following values:
* @arg CTC_REF_CLK_DIV8: REFCLK/8
* @arg CTC_REF_CLK_DIV32: REFCLK/32
* @arg CTC_REF_CLK_DIV128: REFCLK/128
* @arg CTC_REF_CLK_DIV256: REFCLK/256
* @arg CTC_REF_CLK_DIV512: REFCLK/512
* @arg CTC_REF_CLK_DIV1024: REFCLK/1024
* @arg CTC_REF_CLK_DIV2048: REFCLK/2048
* @arg CTC_REF_CLK_DIV4096: REFCLK/4096
* @retval None
*/
void CTC_SetRefClockDiv(uint32_t u32Div)
{
/* Check parameters */
DDL_ASSERT(IS_CTC_REF_CLK_DIV(u32Div));
MODIFY_REG32(M4_CTC->CR1, CTC_CR1_REFPSC, u32Div);
}
/**
* @brief Set CTC reference clock source.
* @param [in] u32ClockSrc CTC reference clock source
* This parameter can be one of the following values:
* @arg CTC_REF_CLK_CTCREF: Clock source CTCREF
* @arg CTC_REF_CLK_XTAL: Clock source XTAL
* @retval None
*/
void CTC_SetRefClockSrc(uint32_t u32ClockSrc)
{
/* Check parameters */
DDL_ASSERT(IS_CTC_REF_CLK_SRC(u32ClockSrc));
MODIFY_REG32(M4_CTC->CR1, CTC_CR1_REFCKS, u32ClockSrc);
}
/**
* @brief Enable or disable CTC error interrupt function.
* @param [in] enNewState The function new state.
* This parameter can be one of the following values:
* @arg Enable: Enable CTC error interrupt function.
* @arg Disable: Disable CTC error interrupt function.
* @retval None
*/
void CTC_IntCmd(en_functional_state_t enNewState)
{
/* Check parameters */
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
WRITE_REG32(bM4_CTC->CR1_b.ERRIE, enNewState);
}
/**
* @brief Get CTC flag.
* @param [in] u32Flag CTC flag
* This parameter can be any composed value of the following values::
* @arg CTC_FLAG_TRIM_OK: Trimming OK flag
* @arg CTC_FLAG_TRIM_OVF: Trimming overflow flag
* @arg CTC_FLAG_TRIM_UDF: Trimming underflow flag
* @arg CTC_FLAG_BUSY: CTC busy flag
* @retval Returned value can be one of the following values:
* - Set: Any bit of the composed flag is set.
* - Reset: All bit of the composed flag is reset.
*/
en_flag_status_t CTC_GetStatus(uint32_t u32Flag)
{
/* Check parameters */
DDL_ASSERT(IS_CTC_FLAG(u32Flag));
return ((0UL == READ_REG32_BIT(M4_CTC->STR, u32Flag)) ? Reset : Set);
}
/**
* @brief Set CTC trimming value.
* @param [in] u32TrimValue CTC trimming value
* This parameter can be min=0 && max=0x3F
* @retval None
*/
void CTC_SetTrimValue(uint32_t u32TrimValue)
{
/* Check parameters */
DDL_ASSERT(IS_CTC_TRIM_VALUE(u32TrimValue));
MODIFY_REG32(M4_CTC->CR1, CTC_CR1_TRMVAL, (u32TrimValue << CTC_CR1_TRMVAL_POS));
}
/**
* @brief Get CTC trimming value.
* @param None
* @retval CTC trimming value(between Min_Data=0 and Max_Data=0x3F)
*/
uint32_t CTC_GetTrimValue(void)
{
return (READ_REG32_BIT(M4_CTC->CR1, CTC_CR1_TRMVAL) >> CTC_CR1_TRMVAL_POS);
}
/**
* @brief Set CTC reload value.
* @param [in] u32ReloadValue CTC reload value
* This parameter can be between Min_Data=0 and Max_Data=0xFFFF
* @retval None
*/
void CTC_SetReloadValue(uint32_t u32ReloadValue)
{
/* Check parameters */
DDL_ASSERT(IS_CTC_RELOAD_VALUE(u32ReloadValue));
MODIFY_REG32(M4_CTC->CR2, CTC_CR2_RLDVAL, (u32ReloadValue << CTC_CR2_RLDVAL_POS));
}
/**
* @brief Get CTC reload value.
* @param None
* @retval CTC reload value (between Min_Data=0 and Max_Data=0xFFFF)
*/
uint16_t CTC_GetReloadValue(void)
{
return (uint16_t)(READ_REG32_BIT(M4_CTC->CR2, CTC_CR2_RLDVAL) >> CTC_CR2_RLDVAL_POS);
}
/**
* @brief Set CTC offset value.
* @param [in] u32OffsetValue CTC offset value
* This parameter can be between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
void CTC_SetOffsetValue(uint32_t u32OffsetValue)
{
/* Check parameters */
DDL_ASSERT(IS_CTC_OFFSET_VALUE(u32OffsetValue));
MODIFY_REG32(M4_CTC->CR2, CTC_CR2_OFSVAL, (u32OffsetValue << CTC_CR2_OFSVAL_POS));
}
/**
* @brief Get CTC offset value.
* @param None
* @retval CTC offset value (between Min_Data=0 and Max_Data=0xFF)
*/
uint32_t CTC_GetOffsetValue(void)
{
return (READ_REG32_BIT(M4_CTC->CR2, CTC_CR2_OFSVAL) >> CTC_CR2_OFSVAL_POS);
}
/**
* @}
*/
#endif /* DDL_CTC_ENABLE */
/**
* @}
*/
/**
* @}
*/
/******************************************************************************
* EOF (not truncated)
*****************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_dac.c
* @brief This file provides firmware functions to manage the Digital-to-Analog
* Converter(DAC).
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hexiao First version
2020-07-15 Hexiao 1. Modify DAC_ChannelCmd to DAC_Start and DAC_Stop
2. Modify DAC_DualChannelCmd to DAC_DualChannelStart
and DAC_DualChannelStop
2020-08-31 Hexiao Refine DAC_AMPCmd
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32f4a0_dac.h"
#include "hc32f4a0_utility.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @defgroup DDL_DAC DAC
* @brief DAC Driver Library
* @{
*/
#if (DDL_DAC_ENABLE == DDL_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup DAC_Local_Macros DAC Local Macros
* @{
*/
#define DAC_ADP_SELECT_ALL (DAC_DAADPCR_ADPSL1 | DAC_DAADPCR_ADPSL2 | DAC_DAADPCR_ADPSL3)
/**
* @defgroup DAC_Check_Parameters_Validity DAC Check Parameters Validity
* @{
*/
#define IS_VALID_UNIT(x) \
( ((x) == M4_DAC1) || \
((x) == M4_DAC2))
#define IS_VALID_CH(x) \
( ((x) == DAC_CH_1) || \
((x) == DAC_CH_2))
#define IS_VALID_DATA_ALIGN(x) \
( ((x) == DAC_DATA_ALIGN_L) || \
((x) == DAC_DATA_ALIGN_R))
#define IS_VALID_DATA_SRC(x) \
( ((x) == DAC_DATA_SRC_DATAREG) || \
((x) == DAC_DATA_SRC_DCU))
#define IS_VALID_ADCPRIO_CONFIG(x) \
( (0U != (x)) && \
(DAC_ADP_SELECT_ALL == ((x) | DAC_ADP_SELECT_ALL)))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup DAC_Global_Functions DAC Global Functions
* @{
*/
/**
* @brief Set DAC data source for specified channel
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @param [in] u16Ch Specify the DAC channel @ref DAC_CH.
* This parameter can be one of the following values:
* @arg DAC_CH_1
* @arg DAC_CH_2
* @param [in] u16Src Specify the data source.
* This parameter can be a value of @ref DAC_DATA_SRC
* - DAC_DATA_SRC_DATAREG: convert source is from data register
* - DAC_DATA_SRC_DCU: convert source is from DCU
* @retval None
*/
void DAC_SetDataSource(M4_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Src)
{
DDL_ASSERT(IS_VALID_UNIT(DACx));
DDL_ASSERT(IS_VALID_CH(u16Ch));
DDL_ASSERT(IS_VALID_DATA_SRC(u16Src));
SET_REG16_BIT(DACx->DACR, u16Src << (DAC_DACR_EXTDSL1_POS + u16Ch));
}
/**
* @brief DAC data register's data alignment pattern configuration
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @param [in] u16Align Specify the data alignment.
* This parameter can be a value of @ref DAC_DATAREG_ALIGN_PATTERN
* - DAC_DATA_ALIGN_L: left alignment
* - DAC_DATA_ALIGN_R: right alignment
* @retval None
*/
void DAC_DataRegAlignConfig(M4_DAC_TypeDef *DACx, uint16_t u16Align)
{
DDL_ASSERT(IS_VALID_UNIT(DACx));
DDL_ASSERT(IS_VALID_DATA_ALIGN(u16Align));
SET_REG16_BIT(DACx->DACR, u16Align);
}
/**
* @brief DAC output function command
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @param [in] u16Ch Specify DAC channel @ref DAC_CH.
* This parameter can be one of the following values:
* @arg DAC_CH_1
* @arg DAC_CH_2
* @param [in] enNewState New state of the DAC output function,
* @ref en_functional_state_t
* @retval None
*/
void DAC_OutputCmd(M4_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState)
{
DDL_ASSERT(IS_VALID_UNIT(DACx));
DDL_ASSERT(IS_VALID_CH(u16Ch));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
const uint16_t u16Cmd = (uint16_t)1U << (DAC_DAOCR_DAODIS1_POS + u16Ch);
if(Enable == enNewState)
{
CLEAR_REG16_BIT(DACx->DAOCR, u16Cmd);
}
else
{
SET_REG16_BIT(DACx->DAOCR, u16Cmd);
}
}
/**
* @brief DAC AMP function command
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @param [in] u16Ch Specify DAC channel @ref DAC_CH.
* This parameter can be one of the following values:
* @arg DAC_CH_1
* @arg DAC_CH_2
* @param [in] enNewState New state of the AMP function,
* @ref en_functional_state_t
* @retval An en_result_t enumeration value:
* - Ok: No errors occurred
* - ErrorInvalidMode: cannot enable AMP when data source is from DCU
*/
en_result_t DAC_AMPCmd(M4_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState)
{
DDL_ASSERT(IS_VALID_UNIT(DACx));
DDL_ASSERT(IS_VALID_CH(u16Ch));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
en_result_t ret = Ok;
uint16_t u16Cmd = (uint16_t)1U << (DAC_DACR_EXTDSL1_POS + u16Ch);
if((0U != (READ_REG16_BIT(DACx->DACR, u16Cmd))) && (Enable == enNewState))
{
ret = ErrorInvalidMode;
}
else
{
u16Cmd = (uint16_t)1U << (DAC_DACR_DAAMP1_POS + u16Ch);
if(Enable == enNewState)
{
SET_REG16_BIT(DACx->DACR, u16Cmd);
}
else
{
CLEAR_REG16_BIT(DACx->DACR, u16Cmd);
}
}
return ret;
}
/**
* @brief DAC ADC priority function command
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @param [in] enNewState New state of the ADC priority function,
* @ref en_functional_state_t
* @retval None
* @note please make sure ADC is in stoped status before calling DAC_ADCPrioCmd
*/
void DAC_ADCPrioCmd(M4_DAC_TypeDef *DACx, en_functional_state_t enNewState)
{
DDL_ASSERT(IS_VALID_UNIT(DACx));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
if(Enable == enNewState)
{
SET_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN);
}
else
{
CLEAR_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN);
}
}
/**
* @brief Enable or Disable the ADP priority for the selected ADCx
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @param [in] u16ADCxPrio ADCx priority to be enabled or disabled.
* This parameter can be one or any combination of the following values:
* @arg DAC_ADP_SELECT_ADC1
* @arg DAC_ADP_SELECT_ADC2
* @arg DAC_ADP_SELECT_ADC3
* @param [in] enNewState New state of ADCx priority
* @ref en_functional_state_t
* @retval None
* @note please make sure ADC is in stoped status before calling DAC_ADCPrioConfig
*/
void DAC_ADCPrioConfig(M4_DAC_TypeDef *DACx, uint16_t u16ADCxPrio, en_functional_state_t enNewState)
{
DDL_ASSERT(IS_VALID_UNIT(DACx));
DDL_ASSERT(IS_VALID_ADCPRIO_CONFIG(u16ADCxPrio));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
if(Enable == enNewState)
{
SET_REG16_BIT(DACx->DAADPCR, u16ADCxPrio);
}
else
{
CLEAR_REG16_BIT(DACx->DAADPCR, u16ADCxPrio);
}
}
/**
* @brief Start the specified DAC channel
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @param [in] u16Ch Specify DAC channel @ref DAC_CH.
* This parameter can be one of the following values:
* @arg DAC_CH_1
* @arg DAC_CH_2
* @retval An en_result_t enumeration value:
* - Ok: No errors occurred
* - ErrorInvalidMode: cannot start single channel when \n
* this channel have already been started by \n
* @ref DAC_DualChannelStart
*/
en_result_t DAC_Start(M4_DAC_TypeDef *DACx, uint16_t u16Ch)
{
en_result_t enRet = Ok;
DDL_ASSERT(IS_VALID_UNIT(DACx));
DDL_ASSERT(IS_VALID_CH(u16Ch));
if((DACx->DACR & DAC_DACR_DAE) != 0U)
{
enRet = ErrorInvalidMode;
}
else
{
const uint16_t u16Cmd = (uint16_t)1U << (DAC_DACR_DA1E_POS + u16Ch);
SET_REG16_BIT(DACx->DACR, u16Cmd);
}
return enRet;
}
/**
* @brief Stop the specified DAC channel
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @param [in] u16Ch Specify DAC channel @ref DAC_CH.
* This parameter can be one of the following values:
* @arg DAC_CH_1
* @arg DAC_CH_2
* @retval An en_result_t enumeration value:
* - Ok: No errors occurred
* - ErrorInvalidMode: cannot stop single channel when \n
* this channel is started by \n
* @ref DAC_DualChannelStart
*/
en_result_t DAC_Stop(M4_DAC_TypeDef *DACx, uint16_t u16Ch)
{
en_result_t enRet = Ok;
DDL_ASSERT(IS_VALID_UNIT(DACx));
DDL_ASSERT(IS_VALID_CH(u16Ch));
if((DACx->DACR & DAC_DACR_DAE) != 0U)
{
enRet = ErrorInvalidMode;
}
else
{
const uint16_t u16Cmd = (uint16_t)1U << (DAC_DACR_DA1E_POS + u16Ch);
CLEAR_REG16_BIT(DACx->DACR, u16Cmd);
}
return enRet;
}
/**
* @brief Start DAC channel 1 and channel 2
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @retval None
*/
void DAC_DualChannelStart(M4_DAC_TypeDef *DACx)
{
DDL_ASSERT(IS_VALID_UNIT(DACx));
SET_REG16_BIT(DACx->DACR, DAC_DACR_DAE);
}
/**
* @brief Stop DAC channel 1 and channel 2
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @retval None
*/
void DAC_DualChannelStop(M4_DAC_TypeDef *DACx)
{
DDL_ASSERT(IS_VALID_UNIT(DACx));
CLEAR_REG16_BIT(DACx->DACR, DAC_DACR_DAE);
}
/**
* @brief Set the specified data holding register value for DAC channel 1
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @param [in] data Data to be loaded into data holding register of channel 1
* @retval None
*/
void DAC_SetChannel1Data(M4_DAC_TypeDef *DACx, uint16_t data)
{
DDL_ASSERT(IS_VALID_UNIT(DACx));
if(READ_REG16_BIT(DACx->DACR, DAC_DACR_DPSEL) == DAC_DATA_ALIGN_L)
{
DDL_ASSERT(0U == (data & 0xFU));
}
else
{
DDL_ASSERT(0U == (data & 0xF000U));
}
WRITE_REG16(DACx->DADR1,data);
}
/**
* @brief Set the specified data holding register value for DAC channel 2
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @param [in] data Data to be loaded into data holding register of channel 2
* @retval None
*/
void DAC_SetChannel2Data(M4_DAC_TypeDef *DACx, uint16_t data)
{
DDL_ASSERT(IS_VALID_UNIT(DACx));
if(READ_REG16_BIT(DACx->DACR, DAC_DACR_DPSEL) == DAC_DATA_ALIGN_L)
{
DDL_ASSERT(0U == (data & 0xFU));
}
else
{
DDL_ASSERT(0U == (data & 0xF000U));
}
WRITE_REG16(DACx->DADR2,data);
}
/**
* @brief Set the specified data holding register value for channel 1 and channel 2
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @param data2: Data to be loaded into data holding register of channel 2
* @param data1: Data to be loaded into data holding register of channel 1
* @retval None
*/
void DAC_SetDualChannelData(M4_DAC_TypeDef *DACx, uint16_t data2, uint16_t data1)
{
DDL_ASSERT(IS_VALID_UNIT(DACx));
if(READ_REG16_BIT(DACx->DACR, DAC_DACR_DPSEL) == DAC_DATA_ALIGN_L)
{
DDL_ASSERT(0U == (data1 & 0xFU));
DDL_ASSERT(0U == (data2 & 0xFU));
}
else
{
DDL_ASSERT(0U == (data1 & 0xF000U));
DDL_ASSERT(0U == (data2 & 0xF000U));
}
WRITE_REG16(DACx->DADR1,data1);
WRITE_REG16(DACx->DADR2,data2);
}
/**
* @brief Get convert status of channel 1 in ADC priority mode
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @retval An en_dac_conv_sate_t enumeration value:
* - ErrorInvalidMode: Could not get convert status when adc priority is not enabled
* - Ok: Data convert completed
* - OperationInProgress: Data convert is ongoing
*/
en_result_t DAC_GetChannel1ConvState(const M4_DAC_TypeDef *DACx)
{
en_result_t enStat = ErrorInvalidMode;
DDL_ASSERT(IS_VALID_UNIT(DACx));
if(0U != READ_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN))
{
enStat = OperationInProgress;
if(READ_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_DA1SF) == 0U)
{
enStat = Ok;
}
}
return enStat;
}
/**
* @brief Get convert status of channel 2 in ADC priority mode
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @retval An en_dac_conv_sate_t enumeration value:
* - ErrorInvalidMode: Could not get convert status when adc priority is not enabled
* - Ok: Data convert completed
* - OperationInProgress: Data convert is ongoing
*/
en_result_t DAC_GetChannel2ConvState(const M4_DAC_TypeDef *DACx)
{
en_result_t enStat = ErrorInvalidMode;
DDL_ASSERT(IS_VALID_UNIT(DACx));
if(0U != READ_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN))
{
enStat = OperationInProgress;
if(READ_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_DA2SF) == 0U)
{
enStat = Ok;
}
}
return enStat;
}
/**
* @brief Fills each pstcInit member with its default value
* @param [in] pstcInit pointer to a stc_dac_init_t structure which will
* be initialized.
* @retval An en_result_t enumeration value.
* - Ok: No errors occurred.
* - ErrorInvalidParameter: pstcInit = NULL
*/
en_result_t DAC_StructInit(stc_dac_init_t *pstcInit)
{
en_result_t enRet = ErrorInvalidParameter;
if(pstcInit != NULL)
{
pstcInit->u16Src = DAC_DATA_SRC_DATAREG;
pstcInit->enOutput = Enable;
enRet = Ok;
}
return enRet;
}
/**
* @brief Initialize the DAC peripheral according to the specified parameters
* in the stc_dac_init_t
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @param [in] u16Ch Specify the DAC channel @ref DAC_CH.
* This parameter can be one of the following values:
* @arg DAC_CH_1
* @arg DAC_CH_2
* @param [in] pstcInit pointer to a stc_dac_init_t structure that contains
* the configuration information for the specified DAC channel.
* @retval An en_result_t enumeration value:
* - Ok: Initialize successfully
* - ErrorInvalidParameter: pstcInit = NULL
*/
en_result_t DAC_Init(M4_DAC_TypeDef *DACx, uint16_t u16Ch, const stc_dac_init_t *pstcInit)
{
DDL_ASSERT(IS_VALID_UNIT(DACx));
DDL_ASSERT(IS_VALID_CH(u16Ch));
en_result_t enRet = ErrorInvalidParameter;
if(pstcInit != NULL)
{
DDL_ASSERT(IS_VALID_DATA_SRC(pstcInit->u16Src));
DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInit->enOutput));
DAC_SetDataSource(DACx, u16Ch, pstcInit->u16Src);
DAC_OutputCmd(DACx, u16Ch, pstcInit->enOutput);
enRet = Ok;
}
return enRet;
}
/**
* @brief Deinitialize the DAC peripheral registers to their default reset values.
* @param [in] DACx Pointer to the DAC peripheral register.
* This parameter can be one of the following values:
* @arg M4_DAC1
* @arg M4_DAC2
* @retval None
*/
void DAC_DeInit(M4_DAC_TypeDef *DACx)
{
DAC_DualChannelStop(DACx);
DAC_SetDataSource(DACx, DAC_CH_1, DAC_DATA_SRC_DATAREG);
DAC_SetDataSource(DACx, DAC_CH_2, DAC_DATA_SRC_DATAREG);
DAC_DataRegAlignConfig(DACx, DAC_DATA_ALIGN_R);
(void)DAC_AMPCmd(DACx, DAC_CH_1,Disable);
(void)DAC_AMPCmd(DACx, DAC_CH_2,Disable);
DAC_OutputCmd(DACx, DAC_CH_1, Enable);
DAC_OutputCmd(DACx, DAC_CH_2, Enable);
DAC_ADCPrioConfig(DACx, DAC_ADP_SELECT_ALL, Disable);
DAC_ADCPrioCmd(DACx, Disable);
}
/**
* @}
*/
#endif /* DDL_DAC_ENABLE */
/**
* @}
*/
/**
* @}
*/
/******************************************************************************
* EOF (not truncated)
*****************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_dmc.c
* @brief This file provides firmware functions to manage the EXMC DMC
* (External Memory Controller: Dynamic Memory Controller) driver library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hongjh First version
2020-07-14 Hongjh Merge API from EXMC_DMC_Enable/Disable to EXMC_DMC_Cmd
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32f4a0_dmc.h"
#include "hc32f4a0_utility.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @defgroup DDL_EXMC_DMC EXMC_DMC
* @brief Dynamic Memory Controller Driver Library
* @{
*/
#if (DDL_DMC_ENABLE == DDL_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup EXMC_DMC_Local_Macros Dynamic Memory Controller Local Macros
* @{
*/
/**
* @defgroup EXMC_DMC_Check_Parameters_Validity EXMC DMC Check Parameters Validity
* @{
*/
#define IS_EXMC_DMC_MEM_WIDTH(x) \
( (EXMC_DMC_MEMORY_WIDTH_16BIT == (x)) || \
(EXMC_DMC_MEMORY_WIDTH_32BIT == (x)))
#define IS_EXMC_DMC_CHIP(x) \
( (EXMC_DMC_CHIP_0 == (x)) || \
(EXMC_DMC_CHIP_1 == (x)) || \
(EXMC_DMC_CHIP_2 == (x)) || \
(EXMC_DMC_CHIP_3 == (x)))
#define IS_EXMC_DMC_BANK(x) \
( (EXMC_DMC_BANK_0 == (x)) || \
(EXMC_DMC_BANK_1 == (x)) || \
(EXMC_DMC_BANK_2 == (x)) || \
(EXMC_DMC_BANK_3 == (x)))
#define IS_EXMC_DMC_CMD(x) \
( (EXMC_DMC_CMD_PRECHARGEALL == (x)) || \
(EXMC_DMC_CMD_AUTOREFRESH == (x)) || \
(EXMC_DMC_CMD_MDREGCONFIG == (x)) || \
(EXMC_DMC_CMD_NOP == (x)))
#define IS_EXMC_DMC_CS_DECODE_MODE(x) \
( (EXMC_DMC_CS_DECODE_ROWBANKCOL == (x)) || \
(EXMC_DMC_CS_DECODE_BANKROWCOL == (x)))
#define IS_EXMC_DMC_COLUMN_BITS_NUM(x) \
( (EXMC_DMC_COLUMN_BITS_NUM_8 == (x)) || \
(EXMC_DMC_COLUMN_BITS_NUM_9 == (x)) || \
(EXMC_DMC_COLUMN_BITS_NUM_10 == (x)) || \
(EXMC_DMC_COLUMN_BITS_NUM_11 == (x)) || \
(EXMC_DMC_COLUMN_BITS_NUM_12 == (x)))
#define IS_EXMC_DMC_ROW_BITS_NUM(x) \
( (EXMC_DMC_ROW_BITS_NUM_11 == (x)) || \
(EXMC_DMC_ROW_BITS_NUM_12 == (x)) || \
(EXMC_DMC_ROW_BITS_NUM_13 == (x)) || \
(EXMC_DMC_ROW_BITS_NUM_14 == (x)) || \
(EXMC_DMC_ROW_BITS_NUM_15 == (x)) || \
(EXMC_DMC_ROW_BITS_NUM_16 == (x)))
#define IS_EXMC_DMC_AUTO_PRECHARGE_PIN(x) \
( (EXMC_DMC_AUTO_PRECHARGE_A8 == (x)) || \
(EXMC_DMC_AUTO_PRECHARGE_A10 == (x)))
#define IS_EXMC_DMC_CKE_OUTPUT_SEL(x) \
( (EXMC_DMC_CKE_OUTPUT_ENABLE == (x)) || \
(EXMC_DMC_CKE_OUTPUT_DISABLE == (x)))
#define EXMC_DMC_MEMCLK_SEL(x) \
( (EXMC_DMC_MEMCLK_NORMAL_OUTPUT == (x)) || \
(EXMC_DMC_MEMCLK_NOP_STOP_OUTPUT == (x)))
#define IS_EXMC_DMC_MEM_BURST(x) \
( (EXMC_DMC_MEM_BURST_1 == (x)) || \
(EXMC_DMC_MEM_BURST_2 == (x)) || \
(EXMC_DMC_MEM_BURST_4 == (x)) || \
(EXMC_DMC_MEM_BURST_8 == (x)) || \
(EXMC_DMC_MEM_BURST_16 == (x)))
#define IS_EXMC_DMC_AUTO_REFRESH_CHIPS(x) \
( (EXMC_DMC_AUTO_REFRESH_CHIP_0 == (x)) || \
(EXMC_DMC_AUTO_REFRESH_CHIPS_01 == (x)) || \
(EXMC_DMC_AUTO_REFRESH_CHIPS_012 == (x)) || \
(EXMC_DMC_AUTO_REFRESH_CHIPS_0123 == (x)))
#define IS_EXMC_DMC_CS_ADDRESS_MASK(x) \
( (EXMC_DMC_ADDR_MASK_16MB == (x)) || \
(EXMC_DMC_ADDR_MASK_32MB == (x)) || \
(EXMC_DMC_ADDR_MASK_64MB == (x)) || \
(EXMC_DMC_ADDR_MASK_128MB == (x)))
#define IS_EXMC_DMC_CS_ADDRESS_MATCH(x) \
( (EXMC_DMC_ADDR_MATCH_0X80000000 == (x)) || \
(EXMC_DMC_ADDR_MATCH_0X81000000 == (x)) || \
(EXMC_DMC_ADDR_MATCH_0X82000000 == (x)) || \
(EXMC_DMC_ADDR_MATCH_0X83000000 == (x)) || \
(EXMC_DMC_ADDR_MATCH_0X84000000 == (x)) || \
(EXMC_DMC_ADDR_MATCH_0X85000000 == (x)) || \
(EXMC_DMC_ADDR_MATCH_0X86000000 == (x)) || \
(EXMC_DMC_ADDR_MATCH_0X87000000 == (x)))
#define IS_EXMC_DMC_ADDRESS(match, mask) \
( (~((((mask) >> DMC_CSCR_ADDMSK_POS) ^ ((match) >> DMC_CSCR_ADDMAT_POS)) << 24UL)) <= 0x87FFFFFFUL)
#define IS_EXMC_DMC_STATE(x) \
( (EXMC_DMC_CTL_STATE_GO == (x)) || \
(EXMC_DMC_CTL_STATE_SLEEP == (x)) || \
(EXMC_DMC_CTL_STATE_WAKEUP == (x)) || \
(EXMC_DMC_CTL_STATE_PAUSE == (x)) || \
(EXMC_DMC_CTL_STATE_CONFIGURE == (x)))
#define IS_EXMC_DMC_TIMING_CASL_CYCLE(x) ((x) <= 7UL)
#define IS_EXMC_DMC_TIMING_DQSS_CYCLE(x) ((x) <= 3UL)
#define IS_EXMC_DMC_TIMING_MRD_CYCLE(x) ((x) <= 0x7FUL)
#define IS_EXMC_DMC_TIMING_RAS_CYCLE(x) ((x) <= 0x0FUL)
#define IS_EXMC_DMC_TIMING_RC_CYCLE(x) ((x) <= 0x0FUL)
#define IS_EXMC_DMC_TIMING_RCD_CYCLE(x) ((x) <= 7UL)
#define IS_EXMC_DMC_TIMING_RFC_CYCLE(x) ((x) <= 0x1FUL)
#define IS_EXMC_DMC_TIMING_RP_CYCLE(x) ((x) <= 7UL)
#define IS_EXMC_DMC_TIMING_RRD_CYCLE(x) ((x) <= 0x0FUL)
#define IS_EXMC_DMC_TIMING_WR_CYCLE(x) ((x) <= 7UL)
#define IS_EXMC_DMC_TIMING_WTR_CYCLE(x) ((x) <= 7UL)
#define IS_EXMC_DMC_TIMING_XP_CYCLE(x) ((x) <= 0xFFUL)
#define IS_EXMC_DMC_TIMING_XSR_CYCLE(x) ((x) <= 0xFFUL)
#define IS_EXMC_DMC_TIMING_ESR_CYCLE(x) ((x) <= 0xFFUL)
#define IS_EXMC_DMC_CKE_DISABLE_PERIOD(x) ((x) <= 0x3FUL)
#define IS_EXMC_DMC_CMDADD(x) ((x) <= 0x7FFFUL)
#define IS_EXMC_DMC_REFRESH_PERIOD(x) ((x) <= 0x7FFFUL)
/**
* @}
*/
/**
* @defgroup EXMC_DMC_Register EXMC DMC Register
* @{
*/
#define EXMC_DMC_CSCRx(__CHIPx__) ((__IO uint32_t *)(((uint32_t)(&M4_DMC->CSCR0)) + (4UL * (__CHIPx__))))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup EXMC_DMC_Global_Functions Dynamic Memory Controller Global Functions
* @{
*/
/**
* @brief Initialize EXMC DMC function.
* @param [in] pstcInit Pointer to a @ref stc_exmc_dmc_init_t structure (EXMC DMC function configuration structure).
* @retval An en_result_t enumeration value:
* - Ok: Initialize success
* - ErrorInvalidParameter: pstcInit = NULL
*/
en_result_t EXMC_DMC_Init(const stc_exmc_dmc_init_t *pstcInit)
{
uint32_t u32RegVal;
en_result_t enRet = ErrorInvalidParameter;
/* Check the pointer pstcInit */
if (NULL != pstcInit)
{
/* Check parameters */
DDL_ASSERT(IS_EXMC_DMC_MEM_WIDTH(pstcInit->u32DmcMemWidth));
DDL_ASSERT(IS_EXMC_DMC_REFRESH_PERIOD(pstcInit->u32RefreshPeriod));
DDL_ASSERT(IS_EXMC_DMC_COLUMN_BITS_NUM(pstcInit->stcChipCfg.u32ColumnBitsNumber));
DDL_ASSERT(IS_EXMC_DMC_ROW_BITS_NUM(pstcInit->stcChipCfg.u32RowBitsNumber));
DDL_ASSERT(IS_EXMC_DMC_AUTO_PRECHARGE_PIN(pstcInit->stcChipCfg.u32AutoPrechargePin));
DDL_ASSERT(IS_EXMC_DMC_CKE_OUTPUT_SEL(pstcInit->stcChipCfg.u32CkeOutputSel));
DDL_ASSERT(EXMC_DMC_MEMCLK_SEL(pstcInit->stcChipCfg.u32MemClkSel));
DDL_ASSERT(IS_EXMC_DMC_CKE_DISABLE_PERIOD(pstcInit->stcChipCfg.u32CkeDisablePeriod));
DDL_ASSERT(IS_EXMC_DMC_MEM_BURST(pstcInit->stcChipCfg.u32MemBurst));
DDL_ASSERT(IS_EXMC_DMC_AUTO_REFRESH_CHIPS(pstcInit->stcChipCfg.u32AutoRefreshChips));
DDL_ASSERT(IS_EXMC_DMC_TIMING_CASL_CYCLE(pstcInit->stcTimingCfg.u32CASL));
DDL_ASSERT(IS_EXMC_DMC_TIMING_DQSS_CYCLE(pstcInit->stcTimingCfg.u32DQSS));
DDL_ASSERT(IS_EXMC_DMC_TIMING_MRD_CYCLE(pstcInit->stcTimingCfg.u32MRD));
DDL_ASSERT(IS_EXMC_DMC_TIMING_RAS_CYCLE(pstcInit->stcTimingCfg.u32RAS));
DDL_ASSERT(IS_EXMC_DMC_TIMING_RC_CYCLE(pstcInit->stcTimingCfg.u32RC));
DDL_ASSERT(IS_EXMC_DMC_TIMING_RCD_CYCLE(pstcInit->stcTimingCfg.u32RCD));
DDL_ASSERT(IS_EXMC_DMC_TIMING_RFC_CYCLE(pstcInit->stcTimingCfg.u32RFC));
DDL_ASSERT(IS_EXMC_DMC_TIMING_RP_CYCLE(pstcInit->stcTimingCfg.u32RP));
DDL_ASSERT(IS_EXMC_DMC_TIMING_RRD_CYCLE(pstcInit->stcTimingCfg.u32RRD));
DDL_ASSERT(IS_EXMC_DMC_TIMING_WR_CYCLE(pstcInit->stcTimingCfg.u32WR));
DDL_ASSERT(IS_EXMC_DMC_TIMING_WTR_CYCLE(pstcInit->stcTimingCfg.u32WTR));
DDL_ASSERT(IS_EXMC_DMC_TIMING_XP_CYCLE(pstcInit->stcTimingCfg.u32XP));
DDL_ASSERT(IS_EXMC_DMC_TIMING_XSR_CYCLE(pstcInit->stcTimingCfg.u32XSR));
DDL_ASSERT(IS_EXMC_DMC_TIMING_ESR_CYCLE(pstcInit->stcTimingCfg.u32ESR));
/* Set memrory width(16bit or 32bit) for DMC.*/
MODIFY_REG32(M4_DMC->BACR, DMC_BACR_DMCMW, pstcInit->u32DmcMemWidth);
/* set auto refresh period*/
WRITE_REG32(M4_DMC->RFTR, pstcInit->u32RefreshPeriod);
/* Set timing parameters for DMC.*/
WRITE_REG32(M4_DMC->TMCR_T_CASL, pstcInit->stcTimingCfg.u32CASL);
WRITE_REG32(M4_DMC->TMCR_T_DQSS, pstcInit->stcTimingCfg.u32DQSS);
WRITE_REG32(M4_DMC->TMCR_T_MRD, pstcInit->stcTimingCfg.u32MRD);
WRITE_REG32(M4_DMC->TMCR_T_RAS, pstcInit->stcTimingCfg.u32RAS);
WRITE_REG32(M4_DMC->TMCR_T_RC, pstcInit->stcTimingCfg.u32RC);
WRITE_REG32(M4_DMC->TMCR_T_RRD, pstcInit->stcTimingCfg.u32RRD);
WRITE_REG32(M4_DMC->TMCR_T_WR, pstcInit->stcTimingCfg.u32WR);
WRITE_REG32(M4_DMC->TMCR_T_WTR, pstcInit->stcTimingCfg.u32WTR);
WRITE_REG32(M4_DMC->TMCR_T_XP, pstcInit->stcTimingCfg.u32XP);
WRITE_REG32(M4_DMC->TMCR_T_XSR, pstcInit->stcTimingCfg.u32XSR);
WRITE_REG32(M4_DMC->TMCR_T_ESR, pstcInit->stcTimingCfg.u32ESR);
MODIFY_REG32(M4_DMC->TMCR_T_RP, DMC_TMCR_T_RP_T_RP, pstcInit->stcTimingCfg.u32RP);
MODIFY_REG32(M4_DMC->TMCR_T_RCD, DMC_TMCR_T_RCD_T_RCD, pstcInit->stcTimingCfg.u32RCD);
MODIFY_REG32(M4_DMC->TMCR_T_RFC, DMC_TMCR_T_RFC_T_RFC, pstcInit->stcTimingCfg.u32RFC);
/* Set base parameters for DMC: burst lenth, Rowbitwidth,ColbitWidth etc.*/
u32RegVal = (pstcInit->stcChipCfg.u32ColumnBitsNumber | \
pstcInit->stcChipCfg.u32RowBitsNumber | \
pstcInit->stcChipCfg.u32AutoPrechargePin | \
pstcInit->stcChipCfg.u32CkeOutputSel | \
pstcInit->stcChipCfg.u32MemClkSel | \
(pstcInit->stcChipCfg.u32CkeDisablePeriod << DMC_CPCR_CKEDISPRD_POS) | \
pstcInit->stcChipCfg.u32MemBurst | \
pstcInit->stcChipCfg.u32AutoRefreshChips);
WRITE_REG32(M4_DMC->CPCR, u32RegVal);
enRet = Ok;
}
return enRet;
}
/**
* @brief De-Initialize EXMC DMC function.
* @param None
* @retval None
*/
void EXMC_DMC_DeInit(void)
{
/* Disable */
WRITE_REG32(bM4_PERIC->EXMC_ENAR_b.DMCEN, 0UL);
/* Configures the registers to reset value. */
WRITE_REG32(M4_DMC->CPCR, 0x00020040UL);
WRITE_REG32(M4_DMC->TMCR_T_CASL, 0x00000003UL);
WRITE_REG32(M4_DMC->TMCR_T_DQSS, 0x00000001UL);
WRITE_REG32(M4_DMC->TMCR_T_MRD, 0x00000002UL);
WRITE_REG32(M4_DMC->TMCR_T_RAS, 0x00000007UL);
WRITE_REG32(M4_DMC->TMCR_T_RC, 0x0000000BUL);
WRITE_REG32(M4_DMC->TMCR_T_RCD, 0x00000035UL);
WRITE_REG32(M4_DMC->TMCR_T_RFC, 0x00001012UL);
WRITE_REG32(M4_DMC->TMCR_T_RP, 0x00000035UL);
WRITE_REG32(M4_DMC->TMCR_T_RRD, 0x00000002UL);
WRITE_REG32(M4_DMC->TMCR_T_WR, 0x00000003UL);
WRITE_REG32(M4_DMC->TMCR_T_WTR, 0x00000002UL);
WRITE_REG32(M4_DMC->TMCR_T_XP, 0x00000001UL);
WRITE_REG32(M4_DMC->TMCR_T_XSR, 0x0000000AUL);
WRITE_REG32(M4_DMC->TMCR_T_ESR, 0x00000014UL);
}
/**
* @brief Set the fields of structure stc_exmc_dmc_init_t to default values
* @param [out] pstcInit Pointer to a @ref stc_exmc_dmc_init_t structure (EXMC DMC function configuration structure)
* @retval An en_result_t enumeration value:
* - Ok: Initialize successfully
* - ErrorInvalidParameter: pstcInit = NULL
*/
en_result_t EXMC_DMC_StructInit(stc_exmc_dmc_init_t *pstcInit)
{
en_result_t enRet = ErrorInvalidParameter;
if (NULL != pstcInit)
{
pstcInit->u32DmcMemWidth = EXMC_DMC_MEMORY_WIDTH_16BIT;
pstcInit->u32RefreshPeriod = 0xA60UL;
pstcInit->stcChipCfg.u32ColumnBitsNumber = EXMC_DMC_COLUMN_BITS_NUM_8;
pstcInit->stcChipCfg.u32RowBitsNumber = EXMC_DMC_ROW_BITS_NUM_15;
pstcInit->stcChipCfg.u32AutoPrechargePin = EXMC_DMC_AUTO_PRECHARGE_A10;
pstcInit->stcChipCfg.u32CkeOutputSel = EXMC_DMC_CKE_OUTPUT_ENABLE;
pstcInit->stcChipCfg.u32MemClkSel = EXMC_DMC_MEMCLK_NORMAL_OUTPUT;
pstcInit->stcChipCfg.u32CkeDisablePeriod = 0UL;
pstcInit->stcChipCfg.u32MemBurst = EXMC_DMC_MEM_BURST_4;
pstcInit->stcChipCfg.u32AutoRefreshChips = EXMC_DMC_AUTO_REFRESH_CHIP_0;
pstcInit->stcTimingCfg.u32CASL = 0x3UL;
pstcInit->stcTimingCfg.u32DQSS = 0x1UL;
pstcInit->stcTimingCfg.u32MRD = 0x02UL;
pstcInit->stcTimingCfg.u32RAS = 0x07UL;
pstcInit->stcTimingCfg.u32RC = 0x0BUL;
pstcInit->stcTimingCfg.u32RCD = 0x05UL;
pstcInit->stcTimingCfg.u32RFC = 0x12UL;
pstcInit->stcTimingCfg.u32RP = 0x05UL;
pstcInit->stcTimingCfg.u32RRD = 0x02UL;
pstcInit->stcTimingCfg.u32WR = 0x03UL;
pstcInit->stcTimingCfg.u32WTR = 0x02UL;
pstcInit->stcTimingCfg.u32XP = 0x01UL;
pstcInit->stcTimingCfg.u32XSR = 0x0AUL;
pstcInit->stcTimingCfg.u32ESR = 0x14UL;
enRet = Ok;
}
return enRet;
}
/**
* @brief Enable/disable DMC.
* @param [in] enNewState An en_functional_state_t enumeration value.
* This parameter can be one of the following values:
* @arg Enable: Enable function.
* @arg Disable: Disable function.
* @retval None
*/
void EXMC_DMC_Cmd(en_functional_state_t enNewState)
{
/* Check parameters */
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
WRITE_REG32(bM4_PERIC->EXMC_ENAR_b.DMCEN, enNewState);
}
/**
* @brief Configure EXMC DMC CS function.
* @param [in] u32Chip The command chip number.
* This parameter can be one of the following values:
* @arg EXMC_DMC_CHIP_0: Chip 0
* @arg EXMC_DMC_CHIP_1: Chip 1
* @arg EXMC_DMC_CHIP_2: Chip 2
* @arg EXMC_DMC_CHIP_3: Chip 3
* @param [in] pstcCfg Pointer to a @ref stc_exmc_dmc_cs_cfg_t structure (EXMC DMC CS function configuration structure).
* @retval An en_result_t enumeration value:
* - Ok: Initialize success
* - ErrorInvalidParameter: pstcCfg = NULL
*/
en_result_t EXMC_DMC_CsConfig(uint32_t u32Chip,
const stc_exmc_dmc_cs_cfg_t *pstcCfg)
{
uint32_t u32RegVal;
__IO uint32_t *DMC_CSCRx;
en_result_t enRet = ErrorInvalidParameter;
/* Check the pointer pstcInit */
if (NULL != pstcCfg)
{
/* Check parameters */
DDL_ASSERT(IS_EXMC_DMC_CHIP(u32Chip));
DDL_ASSERT(IS_EXMC_DMC_CS_ADDRESS_MASK(pstcCfg->u32AddrMask));
DDL_ASSERT(IS_EXMC_DMC_CS_ADDRESS_MATCH(pstcCfg->u32AddrMatch));
DDL_ASSERT(IS_EXMC_DMC_CS_DECODE_MODE(pstcCfg->u32AddrDecodeMode));
DDL_ASSERT(IS_EXMC_DMC_ADDRESS(pstcCfg->u32AddrMatch, pstcCfg->u32AddrMask));
/* Set chip selection for DMC.*/
DMC_CSCRx = EXMC_DMC_CSCRx(u32Chip);
u32RegVal = (pstcCfg->u32AddrMask | pstcCfg->u32AddrMatch | pstcCfg->u32AddrDecodeMode);
WRITE_REG32(*DMC_CSCRx, u32RegVal);
enRet = Ok;
}
return enRet;
}
/**
* @brief Get the start address of the specified DMC chip.
* @param [in] u32Chip The chip number.
* This parameter can be one of the following values:
* @arg EXMC_DMC_CHIP_0: Chip 0
* @arg EXMC_DMC_CHIP_1: Chip 1
* @arg EXMC_DMC_CHIP_2: Chip 2
* @arg EXMC_DMC_CHIP_3: Chip 3
* @retval The start address of the specified DMC chip.
*/
uint32_t EXMC_DMC_ChipStartAddress(uint32_t u32Chip)
{
__IO uint32_t *DMC_CSCRx;
/* Check parameters */
DDL_ASSERT(IS_EXMC_DMC_CHIP(u32Chip));
DMC_CSCRx = EXMC_DMC_CSCRx(u32Chip);
return (READ_REG32_BIT(*DMC_CSCRx, DMC_CSCR_ADDMAT) << 16UL);
}
/**
* @brief Get the end address of the specified DMC chip.
* @param [in] u32Chip The chip number.
* This parameter can be one of the following values:
* @arg EXMC_DMC_CHIP_0: Chip 0
* @arg EXMC_DMC_CHIP_1: Chip 1
* @arg EXMC_DMC_CHIP_2: Chip 2
* @arg EXMC_DMC_CHIP_3: Chip 3
* @retval The end address of the specified DMC chip
*/
uint32_t EXMC_DMC_ChipEndAddress(uint32_t u32Chip)
{
uint32_t u32Mask;
uint32_t u32Match;
__IO uint32_t *DMC_CSCRx;
/* Check parameters */
DDL_ASSERT(IS_EXMC_DMC_CHIP(u32Chip));
DMC_CSCRx = EXMC_DMC_CSCRx(u32Chip);
u32Mask = (READ_REG32_BIT(*DMC_CSCRx, DMC_CSCR_ADDMSK) >> DMC_CSCR_ADDMSK_POS);
u32Match = (READ_REG32_BIT(*DMC_CSCRx, DMC_CSCR_ADDMAT) >> DMC_CSCR_ADDMAT_POS);
return (~((u32Match ^ u32Mask) << 24UL));
}
/**
* @brief Set EXMC SMC command.
* @param [in] u32Chip The command chip number.
* This parameter can be one of the following values:
* @arg EXMC_DMC_CHIP_0: Chip 0
* @arg EXMC_DMC_CHIP_1: Chip 1
* @arg EXMC_DMC_CHIP_2: Chip 2
* @arg EXMC_DMC_CHIP_3: Chip 3
* @param [in] u32Bank The command bank.
* This parameter can be one of the following values:
* @arg EXMC_DMC_BANK_0: Bank 0
* @arg EXMC_DMC_BANK_1: Bank 1
* @arg EXMC_DMC_BANK_2: Bank 2
* @arg EXMC_DMC_BANK_3: Bank 3
* @param [in] u32Cmd The command.
* This parameter can be one of the following values:
* @arg EXMC_DMC_CMD_PRECHARGEALL:Precharge all
* @arg EXMC_DMC_CMD_AUTOREFRESH: Auto refresh
* @arg EXMC_DMC_CMD_MDREGCONFIG: Set memory device mode register
* @arg EXMC_DMC_CMD_NOP: NOP
* @param [in] u32Address The address parameter for CMD MdRegConfig only.
* This parameter can be a value between Min_Data = 0 and Max_Data = 0x7FFFUL
* @retval An en_result_t enumeration value:
* - Ok: Command success
*/
en_result_t EXMC_DMC_SetCommand(uint32_t u32Chip,
uint32_t u32Bank,
uint32_t u32Cmd,
uint32_t u32Address)
{
uint32_t u32DmcCmdr;
/* Check parameters */
DDL_ASSERT(IS_EXMC_DMC_CHIP(u32Chip));
DDL_ASSERT(IS_EXMC_DMC_BANK(u32Bank));
DDL_ASSERT(IS_EXMC_DMC_CMD(u32Cmd));
DDL_ASSERT(IS_EXMC_DMC_CMDADD(u32Address));
/* Set DMC_CMDR register for DMC.*/
u32DmcCmdr = (u32Address | \
(u32Bank << DMC_CMDR_CMDBA_POS) | \
u32Cmd | \
(u32Chip << DMC_CMDR_CMDCHIP_POS));
WRITE_REG32(M4_DMC->CMDR, u32DmcCmdr);
return Ok;
}
/**
* @brief Set EXMC DMC state.
* @param [in] u32State The command chip number.
* @arg EXMC_DMC_CTL_STATE_GO: Go
* @arg EXMC_DMC_CTL_STATE_SLEEP: Sleep for low power
* @arg EXMC_DMC_CTL_STATE_WAKEUP: Wake up
* @arg EXMC_DMC_CTL_STATE_PAUSE: Pause
* @arg EXMC_DMC_CTL_STATE_CONFIGURE: Configure
* @retval None
*/
void EXMC_DMC_SetState(uint32_t u32State)
{
DDL_ASSERT(IS_EXMC_DMC_STATE(u32State));
WRITE_REG32(M4_DMC->STCR, u32State);
}
/**
* @}
*/
#endif /* DDL_DMC_ENABLE */
/**
* @}
*/
/**
* @}
*/
/******************************************************************************
* EOF (not truncated)
*****************************************************************************/

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bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dvp.c Normal file
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@ -0,0 +1,484 @@
/**
*******************************************************************************
* @file hc32f4a0_dvp.c
* @brief This file provides firmware functions to manage the DVP(Digital Video
* Processor) driver library.
@verbatim
Change Logs:
Date Author Notes
2020-08-20 Hongjh First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32f4a0_dvp.h"
#include "hc32f4a0_utility.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @defgroup DDL_DVP DVP
* @brief Digital Video Processor Driver Library
* @{
*/
#if (DDL_DVP_ENABLE == DDL_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup DVP_Local_Macros DVP Local Macros
* @{
*/
/**
* @defgroup DVP_Check_Parameters_Validity DVP Check Parameters Validity
* @{
*/
#define IS_DVP_CAPT_MD(x) \
( ((x) == DVP_CAPT_MD_CONTINUOS_FRAME) || \
((x) == DVP_CAPT_MD_SINGLE_FRAME))
#define IS_DVP_SYNC_MD(x) \
( ((x) == DVP_SYNC_MD_HW) || \
((x) == DVP_SYNC_MD_SW))
#define IS_DVP_PIXCLK_POLARITY(x) \
( ((x) == DVP_PIXCLK_RISING) || \
((x) == DVP_PIXCLK_FALLING))
#define IS_DVP_HSYNC_POLARITY(x) \
( ((x) == DVP_HSYNC_LOW) || \
((x) == DVP_HSYNC_HIGH))
#define IS_DVP_VSYNC_POLARITY(x) \
( ((x) == DVP_VSYNC_LOW) || \
((x) == DVP_VSYNC_HIGH))
#define IS_DVP_CAPT_FREQ(x) \
( ((x) == DVP_CAPT_FREQ_ALL_FRAME) || \
((x) == DVP_CAPT_FREQ_ONT_TIME_2FRAME) || \
((x) == DVP_CAPT_FREQ_ONT_TIME_4FRAME))
#define IS_DVP_DATA_WIDTH(x) \
( ((x) == DVP_DATA_WIDTH_8BIT) || \
((x) == DVP_DATA_WIDTH_10BIT) || \
((x) == DVP_DATA_WIDTH_12BIT) || \
((x) == DVP_DATA_WIDTH_14BIT))
#define IS_DVP_FLAG(x) \
( ((x) != 0UL) || \
(((x) | DVP_FLAG_ALL) == DVP_FLAG_ALL))
#define IS_DVP_INT(x) \
( ((x) != 0UL) || \
(((x) | DVP_INT_ALL) == DVP_INT_ALL))
#define IS_DVP_CROP_WIN_X(x) ((x) <= 0x3FFFUL)
#define IS_DVP_CROP_WIN_Y(x) ((x) <= 0x3FFFUL)
#define IS_DVP_CROP_WIN_XSIZE(x) ((x) <= 0x3FFFUL)
#define IS_DVP_CROP_WIN_YSIZE(x) ((x) <= 0x3FFFUL)
#define IS_DVP_SYNC_CODE(x) ((x) <= 0xFFUL)
#define IS_DVP_MASK_CODE(x) ((x) <= 0xFFUL)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup DVP_Global_Functions DVP Global Functions
* @{
*/
/**
* @brief Initialize DVP function.
* @param [in] pstcDvpInit Pointer to a @ref stc_dvp_init_t structure.
* @retval An en_result_t enumeration value:
* - Ok: Initialize successfully
* - ErrorInvalidParameter: The parameter pstcDvpInit is NULL
*/
en_result_t DVP_Init(const stc_dvp_init_t *pstcDvpInit)
{
uint32_t u32RegValue;
en_result_t enRet = ErrorInvalidParameter;
if (NULL != pstcDvpInit)
{
/* Check parameters */
DDL_ASSERT(IS_DVP_SYNC_MD(pstcDvpInit->u32SyncMode));
DDL_ASSERT(IS_DVP_DATA_WIDTH(pstcDvpInit->u32DataWidth));
DDL_ASSERT(IS_DVP_CAPT_MD(pstcDvpInit->u32CaptureMode));
DDL_ASSERT(IS_DVP_CAPT_FREQ(pstcDvpInit->u32CaptureFreq));
DDL_ASSERT(IS_DVP_PIXCLK_POLARITY(pstcDvpInit->u32PIXCLKPolarity));
DDL_ASSERT(IS_DVP_HSYNC_POLARITY(pstcDvpInit->u32HSYNCPolarity));
DDL_ASSERT(IS_DVP_VSYNC_POLARITY(pstcDvpInit->u32VSYNCPolarity));
/* De-init DVP*/
WRITE_REG32(M4_DVP->CTR, 0UL);
WRITE_REG32(M4_DVP->STR, 0UL);
WRITE_REG32(M4_DVP->IER, 0UL);
WRITE_REG32(M4_DVP->SSYNDR, 0UL);
WRITE_REG32(M4_DVP->SSYNMR, 0xFFFFFFFFUL);
WRITE_REG32(M4_DVP->CPSFTR, 0UL);
WRITE_REG32(M4_DVP->CPSZER, 0UL);
u32RegValue = (pstcDvpInit->u32SyncMode | \
pstcDvpInit->u32DataWidth | \
pstcDvpInit->u32CaptureMode | \
pstcDvpInit->u32CaptureFreq | \
pstcDvpInit->u32PIXCLKPolarity | \
pstcDvpInit->u32HSYNCPolarity | \
pstcDvpInit->u32VSYNCPolarity);
/* Configure DVP */
WRITE_REG32(M4_DVP->CTR, u32RegValue);
enRet = Ok;
}
return enRet;
}
/**
* @brief De-Initialize DVP function.
* @param None
* @retval None
*/
void DVP_DeInit(void)
{
WRITE_REG32(M4_DVP->CTR, 0UL);
WRITE_REG32(M4_DVP->STR, 0UL);
WRITE_REG32(M4_DVP->IER, 0UL);
WRITE_REG32(M4_DVP->SSYNDR, 0UL);
WRITE_REG32(M4_DVP->SSYNMR, 0xFFFFFFFFUL);
WRITE_REG32(M4_DVP->CPSFTR, 0UL);
WRITE_REG32(M4_DVP->CPSZER, 0UL);
}
/**
* @brief Set the fields of structure stc_dvp_init_t to default values
* @param [out] pstcDvpInit Pointer to a @ref stc_dvp_init_t structure
* @retval An en_result_t enumeration value:
* - Ok: Initialize successfully
* - ErrorInvalidParameter: The parameter pstcDvpInit is NULL
*/
en_result_t DVP_StructInit(stc_dvp_init_t *pstcDvpInit)
{
en_result_t enRet = ErrorInvalidParameter;
if (NULL != pstcDvpInit)
{
pstcDvpInit->u32SyncMode = DVP_SYNC_MD_HW;
pstcDvpInit->u32DataWidth = DVP_DATA_WIDTH_8BIT;
pstcDvpInit->u32CaptureMode = DVP_CAPT_MD_CONTINUOS_FRAME;
pstcDvpInit->u32CaptureFreq = DVP_CAPT_FREQ_ALL_FRAME;
pstcDvpInit->u32PIXCLKPolarity = DVP_PIXCLK_FALLING;
pstcDvpInit->u32HSYNCPolarity = DVP_HSYNC_LOW;
pstcDvpInit->u32VSYNCPolarity = DVP_VSYNC_LOW;
enRet = Ok;
}
return enRet;
}
/**
* @brief Enable/disable DVP.
* @param [in] enNewState An en_functional_state_t enumeration value.
* This parameter can be one of the following values:
* @arg Enable: Enable function.
* @arg Disable: Disable function.
* @retval None
*/
void DVP_Cmd(en_functional_state_t enNewState)
{
/* Check parameters */
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
WRITE_REG32(bM4_DVP->CTR_b.DVPEN, enNewState);
}
/**
* @brief Enable/disable the specified DVP interrupt.
* @param [in] u32IntType DVP interrupt type
* This parameter can be any composed value of the following values:
* @arg DVP_INT_FRAME_START: Frame start interrupt
* @arg DVP_INT_LINE_START: Line start interrupt
* @arg DVP_INT_LINE_END: Line end interrupt
* @arg DVP_INT_FRAME_END: Frame end interrupt
* @arg DVP_INT_FIFO_OVF: FIFO overflow error interrupt
* @arg DVP_INT_SYNC_ERR: Sync error interrupt
* @param [in] enNewState An en_functional_state_t enumeration value.
* This parameter can be one of the following values:
* @arg Enable: Enable function.
* @arg Disable: Disable function.
* @retval None
*/
void DVP_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState)
{
/* Check parameters */
DDL_ASSERT(IS_DVP_INT(u32IntType));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
if (Enable == enNewState)
{
SET_REG32_BIT(M4_DVP->IER, u32IntType);
}
else
{
CLEAR_REG32_BIT(M4_DVP->IER, u32IntType);
}
}
/**
* @brief Enable/disable DVP crop.
* @param [in] enNewState An en_functional_state_t enumeration value.
* This parameter can be one of the following values:
* @arg Enable: Enable function.
* @arg Disable: Disable function.
* @retval None
*/
void DVP_CropCmd(en_functional_state_t enNewState)
{
/* Check parameters */
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
WRITE_REG32(bM4_DVP->CTR_b.CROPEN, enNewState);
}
/**
* @brief Enable/disable DVP JPEG format.
* @param [in] enNewState An en_functional_state_t enumeration value.
* This parameter can be one of the following values:
* @arg Enable: Enable function.
* @arg Disable: Disable function.
* @retval None
*/
void DVP_JPEGCmd(en_functional_state_t enNewState)
{
/* Check parameters */
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
WRITE_REG32(bM4_DVP->CTR_b.JPEGEN, enNewState);
}
/**
* @brief Enable/disable DVP capture.
* @param [in] enNewState An en_functional_state_t enumeration value.
* This parameter can be one of the following values:
* @arg Enable: Enable function.
* @arg Disable: Disable function.
* @retval None
*/
void DVP_CaptrueCmd(en_functional_state_t enNewState)
{
/* Check parameters */
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
WRITE_REG32(bM4_DVP->CTR_b.CAPEN, enNewState);
}
/**
* @brief Get DVP capture function state.
* @param None
* @retval An en_flag_status_t enumeration value:
* - Enable: Capture function is enabled.
* - Disable: Capture function is disabled.
*/
en_functional_state_t DVP_GetCaptrueCmdState(void)
{
return ((0UL == READ_REG32(bM4_DVP->CTR_b.CAPEN)) ? Disable : Enable);
}
/**
* @brief Get the specified DVP flag status.
* @param [in] u32Flag DVP flag
* This parameter can be any composed value of the following values:
* @arg DVP_FLAG_FRAME_START: Frame start flag
* @arg DVP_FLAG_LINE_START: Line start flag
* @arg DVP_FLAG_LINE_END: Line end flag
* @arg DVP_FLAG_FRAME_END: Frame end flag
* @arg DVP_FLAG_FIFO_OVF: FIFO overflow error flag
* @arg DVP_FLAG_SYNC_ERR: Sync error interrupt
* @retval An en_flag_status_t enumeration value:
* - Set: Any bit of the composed flag is set.
* - Reset: All bit of the composed flag is reset.
*/
en_flag_status_t DVP_GetStatus(uint32_t u32Flag)
{
/* Check parameters */
DDL_ASSERT(IS_DVP_FLAG(u32Flag));
return ((READ_REG32_BIT(M4_DVP->STR, u32Flag) == 0UL) ? Reset : Set);
}
/**
* @brief Clear the specified DVP flag status.
* @param [in] u32Flag DVP flag
* This parameter can be any composed value of the following values:
* @arg DVP_FLAG_FRAME_START: Frame start flag
* @arg DVP_FLAG_LINE_START: Line start flag
* @arg DVP_FLAG_LINE_END: Line end flag
* @arg DVP_FLAG_FRAME_END: Frame end flag
* @arg DVP_FLAG_FIFO_OVF: FIFO overflow error flag
* @arg DVP_FLAG_SYNC_ERR: Sync error interrupt
* @retval None
*/
void DVP_ClearStatus(uint32_t u32Flag)
{
/* Check parameters */
DDL_ASSERT(IS_DVP_FLAG(u32Flag));
CLEAR_REG32_BIT(M4_DVP->STR, u32Flag);
}
/**
* @brief Set DVP software sync code.
* @param [in] pstcSyncCode Pointer to a @ref stc_dvp_sw_sync_code_t structure.
* @retval An en_result_t enumeration value:
* - Ok: Initialize successfully
* - ErrorInvalidParameter: The parameter pstcSyncCode is NULL
*/
en_result_t DVP_SetSWSyncCode(const stc_dvp_sw_sync_code_t *pstcSyncCode)
{
uint32_t u32RegValue;
en_result_t enRet = ErrorInvalidParameter;
if (NULL != pstcSyncCode)
{
/* Check parameters */
DDL_ASSERT(IS_DVP_SYNC_CODE(pstcSyncCode->u32FrameStartSyncCode));
DDL_ASSERT(IS_DVP_SYNC_CODE(pstcSyncCode->u32LineStartSyncCode));
DDL_ASSERT(IS_DVP_SYNC_CODE(pstcSyncCode->u32LineEndSyncCode));
DDL_ASSERT(IS_DVP_SYNC_CODE(pstcSyncCode->u32FrameEndSyncCode));
/* Set sync code. */
u32RegValue = ((pstcSyncCode->u32FrameStartSyncCode << DVP_SSYNDR_FSDAT_POS) | \
(pstcSyncCode->u32LineStartSyncCode << DVP_SSYNDR_LSDAT_POS) | \
(pstcSyncCode->u32LineEndSyncCode << DVP_SSYNDR_LEDAT_POS) | \
(pstcSyncCode->u32FrameEndSyncCode << DVP_SSYNDR_FEDAT_POS));
WRITE_REG32(M4_DVP->SSYNDR, u32RegValue);
enRet = Ok;
}
return enRet;
}
/**
* @brief Set DVP software sync mask code.
* @param [in] pstcMaskCode Pointer to a @ref stc_dvp_sw_mask_code_t structure.
* @retval An en_result_t enumeration value:
* - Ok: Initialize successfully
* - ErrorInvalidParameter: The parameter pstcMaskCode is NULL
*/
en_result_t DVP_SetSWMaskCode(const stc_dvp_sw_mask_code_t *pstcMaskCode)
{
uint32_t u32RegValue;
en_result_t enRet = ErrorInvalidParameter;
if (NULL != pstcMaskCode)
{
/* Check parameters */
DDL_ASSERT(IS_DVP_MASK_CODE(pstcMaskCode->u32FrameStartMaskCode));
DDL_ASSERT(IS_DVP_MASK_CODE(pstcMaskCode->u32LineStartMaskCode));
DDL_ASSERT(IS_DVP_MASK_CODE(pstcMaskCode->u32LineEndMaskCode));
DDL_ASSERT(IS_DVP_MASK_CODE(pstcMaskCode->u32FrameEndMaskCode));
/* Set sync code. */
u32RegValue = ((pstcMaskCode->u32FrameStartMaskCode << DVP_SSYNMR_FSMSK_POS) | \
(pstcMaskCode->u32LineStartMaskCode << DVP_SSYNMR_LSMSK_POS) | \
(pstcMaskCode->u32LineEndMaskCode << DVP_SSYNMR_LEMSK_POS) | \
(pstcMaskCode->u32FrameEndMaskCode << DVP_SSYNMR_FEMSK_POS));
WRITE_REG32(M4_DVP->SSYNMR, u32RegValue);
enRet = Ok;
}
return enRet;
}
/**
* @brief Set DVP software sync mask code.
* @param [in] pstcConfig Pointer to a @ref stc_dvp_crop_window_config_t structure.
* @retval An en_result_t enumeration value:
* - Ok: Initialize successfully
* - ErrorInvalidParameter: The parameter pstcConfig is NULL
*/
en_result_t DVP_CropWindowConfig(const stc_dvp_crop_window_config_t *pstcConfig)
{
en_result_t enRet = ErrorInvalidParameter;
if (NULL != pstcConfig)
{
/* Check parameters */
DDL_ASSERT(IS_DVP_CROP_WIN_X(pstcConfig->u32X));
DDL_ASSERT(IS_DVP_CROP_WIN_Y(pstcConfig->u32Y));
DDL_ASSERT(IS_DVP_CROP_WIN_XSIZE(pstcConfig->u32XSize));
DDL_ASSERT(IS_DVP_CROP_WIN_YSIZE(pstcConfig->u32YSize));
/* Configure crop window */
WRITE_REG32(M4_DVP->CPSFTR, (pstcConfig->u32X | (pstcConfig->u32Y << DVP_CPSFTR_CSHIFT_POS)));
WRITE_REG32(M4_DVP->CPSZER, (pstcConfig->u32XSize | (pstcConfig->u32YSize << DVP_CPSZER_CSIZE_POS)));
enRet = Ok;
}
return enRet;
}
/**
* @}
*/
#endif /* DDL_DVP_ENABLE */
/**
* @}
*/
/**
* @}
*/
/******************************************************************************
* EOF (not truncated)
*****************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_emb.c
* @brief This file provides firmware functions to manage the EMB
* (Emergency Brake).
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hongjh First version
2020-07-07 Hongjh Replace the word Timer with TMR abbreviation
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32f4a0_emb.h"
#include "hc32f4a0_utility.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @defgroup DDL_EMB EMB
* @brief Emergency Brake Driver Library
* @{
*/
#if (DDL_EMB_ENABLE == DDL_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup EMB_Local_Macros EMB Local Macros
* @{
*/
/**
* @defgroup EMB_Check_Parameters_Validity EMB Check Parameters Validity
* @{
*/
#define IS_VALID_EMB(x) \
( ((x) == M4_EMB0) || \
((x) == M4_EMB1) || \
((x) == M4_EMB2) || \
((x) == M4_EMB3) || \
((x) == M4_EMB4) || \
((x) == M4_EMB5) || \
((x) == M4_EMB6))
#define IS_VALID_EMB_TMR6(x) \
( ((x) == M4_EMB0) || \
((x) == M4_EMB1) || \
((x) == M4_EMB2) || \
((x) == M4_EMB3))
#define IS_VALID_EMB_TIMER4(x) \
( ((x) == M4_EMB4) || \
((x) == M4_EMB5) || \
((x) == M4_EMB6))
#define IS_VALID_EMB_CMP1_SEL(x) \
( ((x) == EMB_CMP1_ENABLE) || \
((x) == EMB_CMP1_DISABLE))
#define IS_VALID_EMB_CMP2_SEL(x) \
( ((x) == EMB_CMP2_ENABLE) || \
((x) == EMB_CMP2_DISABLE))
#define IS_VALID_EMB_CMP3_SEL(x) \
( ((x) == EMB_CMP3_ENABLE) || \
((x) == EMB_CMP3_DISABLE))
#define IS_VALID_EMB_CMP4_SEL(x) \
( ((x) == EMB_CMP4_ENABLE) || \
((x) == EMB_CMP4_DISABLE))
#define IS_VALID_EMB_PORT1_SEL(x) \
( ((x) == EMB_PORT1_ENABLE) || \
((x) == EMB_PORT1_DISABLE))
#define IS_VALID_EMB_PORT2_SEL(x) \
( ((x) == EMB_PORT2_ENABLE) || \
((x) == EMB_PORT2_DISABLE))
#define IS_VALID_EMB_PORT3_SEL(x) \
( ((x) == EMB_PORT3_ENABLE) || \
((x) == EMB_PORT3_DISABLE))
#define IS_VALID_EMB_PORT4_SEL(x) \
( ((x) == EMB_PORT4_ENABLE) || \
((x) == EMB_PORT4_DISABLE))
#define IS_VALID_EMB_OSC_SEL(x) \
( ((x) == EMB_OSC_ENABLE) || \
((x) == EMB_OSC_DISABLE))
#define IS_VALID_EMB_TMR4_PWM_W_SEL(x) \
( ((x) == EMB_TMR4_PWM_W_ENABLE) || \
((x) == EMB_TMR4_PWM_W_DISABLE))
#define IS_VALID_EMB_TMR4_PWM_V_SEL(x) \
( ((x) == EMB_TMR4_PWM_V_ENABLE) || \
((x) == EMB_TMR4_PWM_V_DISABLE))
#define IS_VALID_EMB_TMR4_PWM_U_SEL(x) \
( ((x) == EMB_TMR4_PWM_U_ENABLE) || \
((x) == EMB_TMR4_PWM_U_DISABLE))
#define IS_VALID_EMB_TMR6_1_PWM_SEL(x) \
( ((x) == EMB_TMR6_1_PWM_ENABLE) || \
((x) == EMB_TMR6_1_PWM_DISABLE))
#define IS_VALID_EMB_TMR6_2_PWM_SEL(x) \
( ((x) == EMB_TMR6_2_PWM_ENABLE) || \
((x) == EMB_TMR6_2_PWM_DISABLE))
#define IS_VALID_EMB_TMR6_3_PWM_SEL(x) \
( ((x) == EMB_TMR6_3_PWM_ENABLE) || \
((x) == EMB_TMR6_3_PWM_DISABLE))
#define IS_VALID_EMB_TMR6_4_PWM_SEL(x) \
( ((x) == EMB_TMR6_4_PWM_ENABLE) || \
((x) == EMB_TMR6_4_PWM_DISABLE))
#define IS_VALID_EMB_TMR6_5_PWM_SEL(x) \
( ((x) == EMB_TMR6_5_PWM_ENABLE) || \
((x) == EMB_TMR6_5_PWM_DISABLE))
#define IS_VALID_EMB_TMR6_6_PWM_SEL(x) \
( ((x) == EMB_TMR6_6_PWM_ENABLE) || \
((x) == EMB_TMR6_6_PWM_DISABLE))
#define IS_VALID_EMB_TMR6_7_PWM_SEL(x) \
( ((x) == EMB_TMR6_7_PWM_ENABLE) || \
((x) == EMB_TMR6_7_PWM_DISABLE))
#define IS_VALID_EMB_TMR6_8_PWM_SEL(x) \
( ((x) == EMB_TMR6_8_PWM_ENABLE) || \
((x) == EMB_TMR6_8_PWM_DISABLE))
#define IS_VALID_EMB_DETECT_PORT1_LEVEL(x) \
( ((x) == EMB_DETECT_PORT1_LEVEL_LOW) || \
((x) == EMB_DETECT_PORT1_LEVEL_HIGH))
#define IS_VALID_EMB_DETECT_PORT2_LEVEL(x) \
( ((x) == EMB_DETECT_PORT2_LEVEL_LOW) || \
((x) == EMB_DETECT_PORT2_LEVEL_HIGH))
#define IS_VALID_EMB_DETECT_PORT3_LEVEL(x) \
( ((x) == EMB_DETECT_PORT3_LEVEL_LOW) || \
((x) == EMB_DETECT_PORT3_LEVEL_HIGH))
#define IS_VALID_EMB_DETECT_PORT4_LEVEL(x) \
( ((x) == EMB_DETECT_PORT4_LEVEL_LOW) || \
((x) == EMB_DETECT_PORT4_LEVEL_HIGH))
#define IS_VALID_EMB_DETECT_TMR4_PWM_W_LEVEL(x) \
( ((x) == EMB_DETECT_TMR4_PWM_W_BOTH_LOW) || \
((x) == EMB_DETECT_TMR4_PWM_W_BOTH_HIGH))
#define IS_VALID_EMB_DETECT_TMR4_PWM_V_LEVEL(x) \
( ((x) == EMB_DETECT_TMR4_PWM_V_BOTH_LOW) || \
((x) == EMB_DETECT_TMR4_PWM_V_BOTH_HIGH))
#define IS_VALID_EMB_DETECT_TMR4_PWM_U_LEVEL(x) \
( ((x) == EMB_DETECT_TMR4_PWM_U_BOTH_LOW) || \
((x) == EMB_DETECT_TMR4_PWM_U_BOTH_HIGH))
#define IS_VALID_EMB_DETECT_TMR6_1_PWM_LEVEL(x) \
( ((x) == EMB_DETECT_TMR6_1_PWM_BOTH_LOW) || \
((x) == EMB_DETECT_TMR6_1_PWM_BOTH_HIGH))
#define IS_VALID_EMB_DETECT_TMR6_2_PWM_LEVEL(x) \
( ((x) == EMB_DETECT_TMR6_2_PWM_BOTH_LOW) || \
((x) == EMB_DETECT_TMR6_2_PWM_BOTH_HIGH))
#define IS_VALID_EMB_DETECT_TMR6_3_PWM_LEVEL(x) \
( ((x) == EMB_DETECT_TMR6_3_PWM_BOTH_LOW) || \
((x) == EMB_DETECT_TMR6_3_PWM_BOTH_HIGH))
#define IS_VALID_EMB_DETECT_TMR6_4_PWM_LEVEL(x) \
( ((x) == EMB_DETECT_TMR6_4_PWM_BOTH_LOW) || \
((x) == EMB_DETECT_TMR6_4_PWM_BOTH_HIGH))
#define IS_VALID_EMB_DETECT_TMR6_5_PWM_LEVEL(x) \
( ((x) == EMB_DETECT_TMR6_5_PWM_BOTH_LOW) || \
((x) == EMB_DETECT_TMR6_5_PWM_BOTH_HIGH))
#define IS_VALID_EMB_DETECT_TMR6_6_PWM_LEVEL(x) \
( ((x) == EMB_DETECT_TMR6_6_PWM_BOTH_LOW) || \
((x) == EMB_DETECT_TMR6_6_PWM_BOTH_HIGH))
#define IS_VALID_EMB_DETECT_TMR6_7_PWM_LEVEL(x) \
( ((x) == EMB_DETECT_TMR6_7_PWM_BOTH_LOW) || \
((x) == EMB_DETECT_TMR6_7_PWM_BOTH_HIGH))
#define IS_VALID_EMB_DETECT_TMR6_8_PWM_LEVEL(x) \
( ((x) == EMB_DETECT_TMR6_8_PWM_BOTH_LOW) || \
((x) == EMB_DETECT_TMR6_8_PWM_BOTH_HIGH))
#define IS_VALID_EMB_INT(x) \
( (0UL != (x)) && \
(0UL == ((x) & (~IS_EMB_INT_MASK))))
#define IS_VALID_EMB_FLAG(x) \
( (0UL != (x)) && \
(0UL == ((x) & (~IS_EMB_FLAG_MASK))))
#define IS_VALID_EMB_STATUS(x) \
( (0UL != (x)) && \
(0UL == ((x) & (~IS_EMB_STATUS_MASK))))
#define IS_VALID_EMB_PORT1_FILTER_DIV(x) \
( ((x) == EMB_PORT1_FILTER_NONE) || \
((x) == EMB_PORT1_FILTER_CLK_DIV1) || \
((x) == EMB_PORT1_FILTER_CLK_DIV8) || \
((x) == EMB_PORT1_FILTER_CLK_DIV32) || \
((x) == EMB_PORT1_FILTER_CLK_DIV128))
#define IS_VALID_EMB_PORT2_FILTER_DIV(x) \
( ((x) == EMB_PORT2_FILTER_NONE) || \
((x) == EMB_PORT2_FILTER_CLK_DIV1) || \
((x) == EMB_PORT2_FILTER_CLK_DIV8) || \
((x) == EMB_PORT2_FILTER_CLK_DIV32) || \
((x) == EMB_PORT2_FILTER_CLK_DIV128))
#define IS_VALID_EMB_PORT3_FILTER_DIV(x) \
( ((x) == EMB_PORT3_FILTER_NONE) || \
((x) == EMB_PORT3_FILTER_CLK_DIV1) || \
((x) == EMB_PORT3_FILTER_CLK_DIV8) || \
((x) == EMB_PORT3_FILTER_CLK_DIV32) || \
((x) == EMB_PORT3_FILTER_CLK_DIV128))
#define IS_VALID_EMB_PORT4_FILTER_DIV(x) \
( ((x) == EMB_PORT4_FILTER_NONE) || \
((x) == EMB_PORT4_FILTER_CLK_DIV1) || \
((x) == EMB_PORT4_FILTER_CLK_DIV8) || \
((x) == EMB_PORT4_FILTER_CLK_DIV32) || \
((x) == EMB_PORT4_FILTER_CLK_DIV128))
#define IS_VALID_EMB_RELEASE_PWM_SEL(x) \
( ((x) == EMB_RELEASE_PWM_SEL_FLAG_ZERO) || \
((x) == EMB_RELEASE_PWM_SEL_STATE_ZERO))
#define IS_VALID_EMB_MONITOR_EVENT(x) \
( ((x) == EMB_EVENT_PWMS) || \
((x) == EMB_EVENT_CMP) || \
((x) == EMB_EVENT_OSC) || \
((x) == EMB_EVENT_PORT1) || \
((x) == EMB_EVENT_PORT2) || \
((x) == EMB_EVENT_PORT3) || \
((x) == EMB_EVENT_PORT4))
/**
* @}
*/
/**
* @defgroup EMB_INT_Mask EMB interrupt mask definition
* @{
*/
#define IS_EMB_INT_MASK (EMB_INT_PWMS | \
EMB_INT_CMP | \
EMB_INT_OSC | \
EMB_INT_PORT1 | \
EMB_INT_PORT2 | \
EMB_INT_PORT3 | \
EMB_INT_PORT4)
/**
* @}
*/
/**
* @defgroup EMB_Flag_Mask EMB flag mask definition
* @{
*/
#define IS_EMB_FLAG_MASK (EMB_FLAG_PWMS | \
EMB_FLAG_CMP | \
EMB_FLAG_OSC | \
EMB_FLAG_PORT1 | \
EMB_FLAG_PORT2 | \
EMB_FLAG_PORT3 | \
EMB_FLAG_PORT4)
/**
* @}
*/
/**
* @defgroup EMB_Status_Mask EMB status mask definition
* @{
*/
#define IS_EMB_STATUS_MASK (EMB_STATE_PWMS | \
EMB_STATE_CMP | \
EMB_STATE_OSC | \
EMB_STATE_PORT1 | \
EMB_STATE_PORT2 | \
EMB_STATE_PORT3 | \
EMB_STATE_PORT4)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup EMB_Global_Functions EMB Global Functions
* @{
*/
/**
* @brief Initialize EMB for TMR4.
* @param [in] EMBx Pointer to EMB instance register base
* This parameter can be one of the following values:
* @arg M4_EMB4: EMB group 4 instance register base
* @arg M4_EMB5: EMB group 5 instance register base
* @arg M4_EMB6: EMB group 6 instance register base
* @param [in] pstcInit Pointer to a @ref stc_emb_tmr4_init_t structure
* @retval An en_result_t enumeration value:
* - Ok: Initialize successfully
* - ErrorInvalidParameter: pstcInit = NULL
* @note TMR4 feature is supported by M4_EMB4/M4_EMB5/M4_EMB6
*/
en_result_t EMB_Tmr4Init(M4_EMB_TypeDef *EMBx,
const stc_emb_tmr4_init_t *pstcInit)
{
uint32_t u32RegVal;
en_result_t enRet = ErrorInvalidParameter;
/* Check structure pointer */
if (NULL != pstcInit)
{
/* Check parameters */
DDL_ASSERT(IS_VALID_EMB_TIMER4(EMBx));
DDL_ASSERT(IS_VALID_EMB_CMP1_SEL(pstcInit->u32Cmp1));
DDL_ASSERT(IS_VALID_EMB_CMP2_SEL(pstcInit->u32Cmp2));
DDL_ASSERT(IS_VALID_EMB_CMP3_SEL(pstcInit->u32Cmp3));
DDL_ASSERT(IS_VALID_EMB_CMP4_SEL(pstcInit->u32Cmp4));
DDL_ASSERT(IS_VALID_EMB_OSC_SEL(pstcInit->u32Osc));
DDL_ASSERT(IS_VALID_EMB_PORT1_SEL(pstcInit->stcPort1.u32PortSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_PORT1_LEVEL(pstcInit->stcPort1.u32PortLevel));
DDL_ASSERT(IS_VALID_EMB_PORT1_FILTER_DIV(pstcInit->stcPort1.u32PortFilterDiv));
DDL_ASSERT(IS_VALID_EMB_PORT2_SEL(pstcInit->stcPort2.u32PortSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_PORT2_LEVEL(pstcInit->stcPort2.u32PortLevel));
DDL_ASSERT(IS_VALID_EMB_PORT2_FILTER_DIV(pstcInit->stcPort2.u32PortFilterDiv));
DDL_ASSERT(IS_VALID_EMB_PORT3_SEL(pstcInit->stcPort3.u32PortSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_PORT3_LEVEL(pstcInit->stcPort3.u32PortLevel));
DDL_ASSERT(IS_VALID_EMB_PORT3_FILTER_DIV(pstcInit->stcPort3.u32PortFilterDiv));
DDL_ASSERT(IS_VALID_EMB_PORT4_SEL(pstcInit->stcPort4.u32PortSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_PORT4_LEVEL(pstcInit->stcPort4.u32PortLevel));
DDL_ASSERT(IS_VALID_EMB_PORT4_FILTER_DIV(pstcInit->stcPort4.u32PortFilterDiv));
DDL_ASSERT(IS_VALID_EMB_TMR4_PWM_U_SEL(pstcInit->stcTmr4PwmU.u32PwmSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_TMR4_PWM_U_LEVEL(pstcInit->stcTmr4PwmU.u32PwmLevel));
DDL_ASSERT(IS_VALID_EMB_TMR4_PWM_V_SEL(pstcInit->stcTmr4PwmV.u32PwmSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_TMR4_PWM_V_LEVEL(pstcInit->stcTmr4PwmV.u32PwmLevel));
DDL_ASSERT(IS_VALID_EMB_TMR4_PWM_W_SEL(pstcInit->stcTmr4PwmW.u32PwmSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_TMR4_PWM_W_LEVEL(pstcInit->stcTmr4PwmW.u32PwmLevel));
/* Set default value && clear flag */
WRITE_REG32(EMBx->SOE, 0x00UL);
WRITE_REG32(EMBx->RLSSEL, 0x00UL);
WRITE_REG32(EMBx->INTEN, 0x00UL);
WRITE_REG32(EMBx->STATCLR, (EMB_STATCLR_PWMSFCLR | \
EMB_STATCLR_CMPFCLR | \
EMB_STATCLR_OSFCLR | \
EMB_STATCLR_PORTINFCLR1 | \
EMB_STATCLR_PORTINFCLR2 | \
EMB_STATCLR_PORTINFCLR3 | \
EMB_STATCLR_PORTINFCLR4));
/* Set EMB_CTL register */
u32RegVal = (pstcInit->u32Cmp1 | \
pstcInit->u32Cmp2 | \
pstcInit->u32Cmp3 | \
pstcInit->u32Cmp4 | \
pstcInit->u32Osc | \
pstcInit->stcTmr4PwmW.u32PwmSel | \
pstcInit->stcTmr4PwmV.u32PwmSel | \
pstcInit->stcTmr4PwmU.u32PwmSel | \
pstcInit->stcPort1.u32PortSel | \
pstcInit->stcPort2.u32PortSel | \
pstcInit->stcPort3.u32PortSel | \
pstcInit->stcPort4.u32PortSel | \
pstcInit->stcPort1.u32PortLevel | \
pstcInit->stcPort2.u32PortLevel | \
pstcInit->stcPort3.u32PortLevel | \
pstcInit->stcPort4.u32PortLevel);
WRITE_REG32(EMBx->CTL1, u32RegVal);
/* Check writing EMB_CTL1 because EMB_CTL1 can write once only after reset */
if (READ_REG32(EMBx->CTL1) == u32RegVal)
{
u32RegVal = (pstcInit->stcTmr4PwmW.u32PwmLevel | \
pstcInit->stcTmr4PwmV.u32PwmLevel | \
pstcInit->stcTmr4PwmU.u32PwmLevel | \
pstcInit->stcPort1.u32PortFilterDiv | \
pstcInit->stcPort2.u32PortFilterDiv | \
pstcInit->stcPort3.u32PortFilterDiv | \
pstcInit->stcPort4.u32PortFilterDiv);
WRITE_REG32(EMBx->CTL2, u32RegVal);
/* Check writing EMB_CTL2 because EMB_CTL2 can write once only after reset */
if (READ_REG32(EMBx->CTL2) == u32RegVal)
{
enRet = Ok;
}
}
}
return enRet;
}
/**
* @brief Set the fields of structure stc_emb_tmr4_init_t to default values
* @param [out] pstcInit Pointer to a @ref stc_emb_tmr4_init_t structure
* @retval An en_result_t enumeration value:
* - Ok: Initialize successfully
* - ErrorInvalidParameter: pstcInit = NULL
*/
en_result_t EMB_Tmr4StructInit(stc_emb_tmr4_init_t *pstcInit)
{
en_result_t enRet = ErrorInvalidParameter;
/* Check structure pointer */
if (NULL != pstcInit)
{
pstcInit->u32Cmp1 = EMB_CMP1_DISABLE;
pstcInit->u32Cmp2 = EMB_CMP2_DISABLE;
pstcInit->u32Cmp3 = EMB_CMP3_DISABLE;
pstcInit->u32Cmp4 = EMB_CMP4_DISABLE;
pstcInit->u32Osc = EMB_OSC_DISABLE;
pstcInit->stcPort1.u32PortSel = EMB_PORT1_DISABLE;
pstcInit->stcPort1.u32PortLevel = EMB_DETECT_PORT1_LEVEL_HIGH;
pstcInit->stcPort1.u32PortFilterDiv = EMB_PORT1_FILTER_NONE;
pstcInit->stcPort2.u32PortSel = EMB_PORT2_DISABLE;
pstcInit->stcPort2.u32PortLevel = EMB_DETECT_PORT2_LEVEL_HIGH;
pstcInit->stcPort2.u32PortFilterDiv = EMB_PORT2_FILTER_NONE;
pstcInit->stcPort3.u32PortSel = EMB_PORT3_DISABLE;
pstcInit->stcPort3.u32PortLevel = EMB_DETECT_PORT3_LEVEL_HIGH;
pstcInit->stcPort3.u32PortFilterDiv = EMB_PORT3_FILTER_NONE;
pstcInit->stcPort4.u32PortSel = EMB_PORT4_DISABLE;
pstcInit->stcPort4.u32PortLevel = EMB_DETECT_PORT4_LEVEL_HIGH;
pstcInit->stcPort4.u32PortFilterDiv = EMB_PORT4_FILTER_NONE;
pstcInit->stcTmr4PwmU.u32PwmSel = EMB_TMR4_PWM_U_DISABLE;
pstcInit->stcTmr4PwmU.u32PwmLevel = EMB_DETECT_TMR4_PWM_U_BOTH_LOW;
pstcInit->stcTmr4PwmV.u32PwmSel = EMB_TMR4_PWM_V_DISABLE;
pstcInit->stcTmr4PwmV.u32PwmLevel = EMB_DETECT_TMR4_PWM_V_BOTH_LOW;
pstcInit->stcTmr4PwmW.u32PwmSel = EMB_TMR4_PWM_W_DISABLE;
pstcInit->stcTmr4PwmW.u32PwmLevel = EMB_DETECT_TMR4_PWM_W_BOTH_LOW;
enRet = Ok;
}
return enRet;
}
/**
* @brief Initialize EMB for TMR6.
* @param [in] EMBx Pointer to EMB instance register base
* This parameter can be one of the following values:
* @arg M4_EMB0: EMB group 0 instance register base
* @arg M4_EMB1: EMB group 1 instance register base
* @arg M4_EMB2: EMB group 2 instance register base
* @arg M4_EMB3: EMB group 3 instance register base
* @param [in] pstcInit Pointer to a @ref stc_emb_tmr6_init_t structure
* @retval An en_result_t enumeration value:
* - Ok: Initialize successfully
* - ErrorInvalidParameter: pstcInit = NULL
* @note TMR6 feature is supported by M4_EMB0/M4_EMB1/M4_EMB2/M4_EMB3
*/
en_result_t EMB_Tmr6Init(M4_EMB_TypeDef *EMBx,
const stc_emb_tmr6_init_t *pstcInit)
{
uint32_t u32RegVal;
en_result_t enRet = ErrorInvalidParameter;
/* Check structure pointer */
if (NULL != pstcInit)
{
/* Check parameters */
DDL_ASSERT(IS_VALID_EMB_TMR6(EMBx));
DDL_ASSERT(IS_VALID_EMB_CMP1_SEL(pstcInit->u32Cmp1));
DDL_ASSERT(IS_VALID_EMB_CMP2_SEL(pstcInit->u32Cmp2));
DDL_ASSERT(IS_VALID_EMB_CMP3_SEL(pstcInit->u32Cmp3));
DDL_ASSERT(IS_VALID_EMB_CMP4_SEL(pstcInit->u32Cmp4));
DDL_ASSERT(IS_VALID_EMB_OSC_SEL(pstcInit->u32Osc));
DDL_ASSERT(IS_VALID_EMB_PORT1_SEL(pstcInit->stcPort1.u32PortSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_PORT1_LEVEL(pstcInit->stcPort1.u32PortLevel));
DDL_ASSERT(IS_VALID_EMB_PORT1_FILTER_DIV(pstcInit->stcPort1.u32PortFilterDiv));
DDL_ASSERT(IS_VALID_EMB_PORT2_SEL(pstcInit->stcPort2.u32PortSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_PORT2_LEVEL(pstcInit->stcPort2.u32PortLevel));
DDL_ASSERT(IS_VALID_EMB_PORT2_FILTER_DIV(pstcInit->stcPort2.u32PortFilterDiv));
DDL_ASSERT(IS_VALID_EMB_PORT3_SEL(pstcInit->stcPort3.u32PortSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_PORT3_LEVEL(pstcInit->stcPort3.u32PortLevel));
DDL_ASSERT(IS_VALID_EMB_PORT3_FILTER_DIV(pstcInit->stcPort3.u32PortFilterDiv));
DDL_ASSERT(IS_VALID_EMB_PORT4_SEL(pstcInit->stcPort4.u32PortSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_PORT4_LEVEL(pstcInit->stcPort4.u32PortLevel));
DDL_ASSERT(IS_VALID_EMB_PORT4_FILTER_DIV(pstcInit->stcPort4.u32PortFilterDiv));
DDL_ASSERT(IS_VALID_EMB_TMR6_1_PWM_SEL(pstcInit->stcTmr6_1.u32PwmSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_1_PWM_LEVEL(pstcInit->stcTmr6_1.u32PwmLevel));
DDL_ASSERT(IS_VALID_EMB_TMR6_2_PWM_SEL(pstcInit->stcTmr6_2.u32PwmSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_2_PWM_LEVEL(pstcInit->stcTmr6_2.u32PwmLevel));
DDL_ASSERT(IS_VALID_EMB_TMR6_3_PWM_SEL(pstcInit->stcTmr6_3.u32PwmSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_3_PWM_LEVEL(pstcInit->stcTmr6_3.u32PwmLevel));
DDL_ASSERT(IS_VALID_EMB_TMR6_4_PWM_SEL(pstcInit->stcTmr6_4.u32PwmSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_4_PWM_LEVEL(pstcInit->stcTmr6_4.u32PwmLevel));
DDL_ASSERT(IS_VALID_EMB_TMR6_5_PWM_SEL(pstcInit->stcTmr6_5.u32PwmSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_5_PWM_LEVEL(pstcInit->stcTmr6_5.u32PwmLevel));
DDL_ASSERT(IS_VALID_EMB_TMR6_6_PWM_SEL(pstcInit->stcTmr6_6.u32PwmSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_6_PWM_LEVEL(pstcInit->stcTmr6_6.u32PwmLevel));
DDL_ASSERT(IS_VALID_EMB_TMR6_7_PWM_SEL(pstcInit->stcTmr6_7.u32PwmSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_7_PWM_LEVEL(pstcInit->stcTmr6_7.u32PwmLevel));
DDL_ASSERT(IS_VALID_EMB_TMR6_8_PWM_SEL(pstcInit->stcTmr6_8.u32PwmSel));
DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_8_PWM_LEVEL(pstcInit->stcTmr6_8.u32PwmLevel));
/* Set default value && clear flag */
WRITE_REG32(EMBx->SOE, 0x00UL);
WRITE_REG32(EMBx->RLSSEL, 0x00UL);
WRITE_REG32(EMBx->INTEN, 0x00UL);
WRITE_REG32(EMBx->STATCLR, (EMB_STATCLR_PWMSFCLR | \
EMB_STATCLR_CMPFCLR | \
EMB_STATCLR_OSFCLR | \
EMB_STATCLR_PORTINFCLR1 | \
EMB_STATCLR_PORTINFCLR2 | \
EMB_STATCLR_PORTINFCLR3 | \
EMB_STATCLR_PORTINFCLR4));
/* Set EMB_CTL register */
u32RegVal = (pstcInit->u32Cmp1 | \
pstcInit->u32Cmp2 | \
pstcInit->u32Cmp3 | \
pstcInit->u32Cmp4 | \
pstcInit->u32Osc | \
pstcInit->stcTmr6_1.u32PwmSel | \
pstcInit->stcTmr6_2.u32PwmSel | \
pstcInit->stcTmr6_3.u32PwmSel | \
pstcInit->stcTmr6_4.u32PwmSel | \
pstcInit->stcTmr6_5.u32PwmSel | \
pstcInit->stcTmr6_6.u32PwmSel | \
pstcInit->stcTmr6_7.u32PwmSel | \
pstcInit->stcTmr6_8.u32PwmSel | \
pstcInit->stcPort1.u32PortSel | \
pstcInit->stcPort2.u32PortSel | \
pstcInit->stcPort3.u32PortSel | \
pstcInit->stcPort4.u32PortSel | \
pstcInit->stcPort1.u32PortLevel | \
pstcInit->stcPort2.u32PortLevel | \
pstcInit->stcPort3.u32PortLevel | \
pstcInit->stcPort4.u32PortLevel);
WRITE_REG32(EMBx->CTL1, u32RegVal);
/* Check writing EMB_CTL1 because EMB_CTL1 can write once only after reset */
if (READ_REG32(EMBx->CTL1) == u32RegVal)
{
u32RegVal = (pstcInit->stcTmr6_1.u32PwmLevel | \
pstcInit->stcTmr6_2.u32PwmLevel | \
pstcInit->stcTmr6_3.u32PwmLevel | \
pstcInit->stcTmr6_4.u32PwmLevel | \
pstcInit->stcTmr6_5.u32PwmLevel | \
pstcInit->stcTmr6_6.u32PwmLevel | \
pstcInit->stcTmr6_7.u32PwmLevel | \
pstcInit->stcTmr6_8.u32PwmLevel | \
pstcInit->stcPort1.u32PortFilterDiv | \
pstcInit->stcPort2.u32PortFilterDiv | \
pstcInit->stcPort3.u32PortFilterDiv | \
pstcInit->stcPort4.u32PortFilterDiv);
WRITE_REG32(EMBx->CTL2, u32RegVal);
/* Check writing EMB_CTL2 because EMB_CTL2 can write once only after reset */
if (READ_REG32(EMBx->CTL2) == u32RegVal)
{
enRet = Ok;
}
}
}
return enRet;
}
/**
* @brief Set the fields of structure stc_emb_tmr6_init_t to default values
* @param [out] pstcInit Pointer to a @ref stc_emb_tmr6_init_t structure
* @retval An en_result_t enumeration value:
* - Ok: Initialize successfully
* - ErrorInvalidParameter: pstcInit = NULL
*/
en_result_t EMB_Tmr6StructInit(stc_emb_tmr6_init_t *pstcInit)
{
en_result_t enRet = ErrorInvalidParameter;
/* Check structure pointer */
if (NULL != pstcInit)
{
pstcInit->u32Cmp1 = EMB_CMP1_DISABLE;
pstcInit->u32Cmp2 = EMB_CMP2_DISABLE;
pstcInit->u32Cmp3 = EMB_CMP3_DISABLE;
pstcInit->u32Cmp4 = EMB_CMP4_DISABLE;
pstcInit->u32Osc = EMB_OSC_DISABLE;
pstcInit->stcPort1.u32PortSel = EMB_PORT1_DISABLE;
pstcInit->stcPort1.u32PortLevel = EMB_DETECT_PORT1_LEVEL_HIGH;
pstcInit->stcPort1.u32PortFilterDiv = EMB_PORT1_FILTER_NONE;
pstcInit->stcPort2.u32PortSel = EMB_PORT2_DISABLE;
pstcInit->stcPort2.u32PortLevel = EMB_DETECT_PORT2_LEVEL_HIGH;
pstcInit->stcPort2.u32PortFilterDiv = EMB_PORT2_FILTER_NONE;
pstcInit->stcPort3.u32PortSel = EMB_PORT3_DISABLE;
pstcInit->stcPort3.u32PortLevel = EMB_DETECT_PORT3_LEVEL_HIGH;
pstcInit->stcPort3.u32PortFilterDiv = EMB_PORT3_FILTER_NONE;
pstcInit->stcPort4.u32PortSel = EMB_PORT4_DISABLE;
pstcInit->stcPort4.u32PortLevel = EMB_DETECT_PORT4_LEVEL_HIGH;
pstcInit->stcPort4.u32PortFilterDiv = EMB_PORT4_FILTER_NONE;
pstcInit->stcTmr6_1.u32PwmSel = EMB_TMR6_1_PWM_DISABLE;
pstcInit->stcTmr6_1.u32PwmLevel = EMB_DETECT_TMR6_1_PWM_BOTH_LOW;
pstcInit->stcTmr6_2.u32PwmSel = EMB_TMR6_2_PWM_DISABLE;
pstcInit->stcTmr6_2.u32PwmLevel = EMB_DETECT_TMR6_2_PWM_BOTH_LOW;
pstcInit->stcTmr6_3.u32PwmSel = EMB_TMR6_3_PWM_DISABLE;
pstcInit->stcTmr6_3.u32PwmLevel = EMB_DETECT_TMR6_3_PWM_BOTH_LOW;
pstcInit->stcTmr6_4.u32PwmSel = EMB_TMR6_4_PWM_DISABLE;
pstcInit->stcTmr6_4.u32PwmLevel = EMB_DETECT_TMR6_4_PWM_BOTH_LOW;
pstcInit->stcTmr6_5.u32PwmSel = EMB_TMR6_5_PWM_DISABLE;
pstcInit->stcTmr6_5.u32PwmLevel = EMB_DETECT_TMR6_5_PWM_BOTH_LOW;
pstcInit->stcTmr6_6.u32PwmSel = EMB_TMR6_6_PWM_DISABLE;
pstcInit->stcTmr6_6.u32PwmLevel = EMB_DETECT_TMR6_6_PWM_BOTH_LOW;
pstcInit->stcTmr6_7.u32PwmSel = EMB_TMR6_7_PWM_DISABLE;
pstcInit->stcTmr6_7.u32PwmLevel = EMB_DETECT_TMR6_7_PWM_BOTH_LOW;
pstcInit->stcTmr6_8.u32PwmSel = EMB_TMR6_8_PWM_DISABLE;
pstcInit->stcTmr6_8.u32PwmLevel = EMB_DETECT_TMR6_8_PWM_BOTH_LOW;
enRet = Ok;
}
return enRet;
}
/**
* @brief De-Initialize EMB function
* @param [in] EMBx Pointer to EMB instance register base
* This parameter can be one of the following values:
* @arg M4_EMB0: EMB group 0 instance register base
* @arg M4_EMB1: EMB group 1 instance register base
* @arg M4_EMB2: EMB group 2 instance register base
* @arg M4_EMB3: EMB group 3 instance register base
* @arg M4_EMB4: EMB group 4 instance register base
* @arg M4_EMB5: EMB group 5 instance register base
* @arg M4_EMB6: EMB group 6 instance register base
* @retval None
*/
void EMB_DeInit(M4_EMB_TypeDef *EMBx)
{
/* Check parameters */
DDL_ASSERT(IS_VALID_EMB(EMBx));
/* Configures the registers to reset value. */
WRITE_REG32(EMBx->SOE, 0x00UL);
WRITE_REG32(EMBx->RLSSEL, 0x00UL);
WRITE_REG32(EMBx->INTEN, 0x00UL);
WRITE_REG32(EMBx->STATCLR, (EMB_STATCLR_PWMSFCLR | \
EMB_STATCLR_CMPFCLR | \
EMB_STATCLR_OSFCLR | \
EMB_STATCLR_PORTINFCLR1 | \
EMB_STATCLR_PORTINFCLR2 | \
EMB_STATCLR_PORTINFCLR3 | \
EMB_STATCLR_PORTINFCLR4));
}
/**
* @brief Set the EMB interrupt function
* @param [in] EMBx Pointer to EMB instance register base
* This parameter can be one of the following values:
* @arg M4_EMB0: EMB group 0 instance register base
* @arg M4_EMB1: EMB group 1 instance register base
* @arg M4_EMB2: EMB group 2 instance register base
* @arg M4_EMB3: EMB group 3 instance register base
* @arg M4_EMB4: EMB group 4 instance register base
* @arg M4_EMB5: EMB group 5 instance register base
* @arg M4_EMB6: EMB group 6 instance register base
* @param [in] u32IntSource EMB interrupt source
* This parameter can be one of the following values:
* @arg EMB_INT_PWMS: PWM same phase event interrupt
* @arg EMB_INT_CMP: CMP result event interrupt
* @arg EMB_INT_OSC: OSC stop event interrupt
* @arg EMB_INT_PORT1: Port1 input event interrupt
* @arg EMB_INT_PORT2: Port2 input event interrupt
* @arg EMB_INT_PORT3: Port3 input event interrupt
* @arg EMB_INT_PORT4: Port4 input event interrupt
* @param [in] enNewState The function new state
* @arg This parameter can be: Enable or Disable
* @retval None
*/
void EMB_IntCmd(M4_EMB_TypeDef *EMBx,
uint32_t u32IntSource,
en_functional_state_t enNewState)
{
/* Check parameters */
DDL_ASSERT(IS_VALID_EMB(EMBx));
DDL_ASSERT(IS_VALID_EMB_INT(u32IntSource));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
if (Enable == enNewState)
{
SET_REG32_BIT(EMBx->INTEN, u32IntSource);
}
else
{
CLEAR_REG32_BIT(EMBx->INTEN, u32IntSource);
}
}
/**
* @brief Set EMB release PWM mode
* @param [in] EMBx Pointer to EMB instance register base
* This parameter can be one of the following values:
* @arg M4_EMB0: EMB group 0 instance register base
* @arg M4_EMB1: EMB group 1 instance register base
* @arg M4_EMB2: EMB group 2 instance register base
* @arg M4_EMB3: EMB group 3 instance register base
* @arg M4_EMB4: EMB group 4 instance register base
* @arg M4_EMB5: EMB group 5 instance register base
* @arg M4_EMB6: EMB group 6 instance register base
* @param [in] u32Event Monitor event
* This parameter can be any composed value of the following values:
* @arg EMB_EVENT_PWMS: PWM same phase event
* @arg EMB_EVENT_CMP: CMP result event
* @arg EMB_EVENT_OSC: OSC stop event
* @arg EMB_EVENT_PORT1: Port1 input event
* @arg EMB_EVENT_PORT2: Port2 input event
* @arg EMB_EVENT_PORT3: Port3 input event
* @arg EMB_EVENT_PORT4: Port4 input event
* @param [in] u32Mode Release mode
* This parameter can be one of the following values:
* @arg EMB_RELEASE_PWM_SEL_FLAG_ZERO: Release PWM when flag bit is zero
* @arg EMB_RELEASE_PWM_SEL_STATE_ZERO: Release PWM when state bit is zero
* @retval None
*/
void EMB_SetReleasePwmMode(M4_EMB_TypeDef *EMBx,
uint32_t u32Event,
uint32_t u32Mode)
{
/* Check parameters */
DDL_ASSERT(IS_VALID_EMB(EMBx));
DDL_ASSERT(IS_VALID_EMB_MONITOR_EVENT(u32Event));
DDL_ASSERT(IS_VALID_EMB_RELEASE_PWM_SEL(u32Mode));
if (EMB_RELEASE_PWM_SEL_FLAG_ZERO == u32Mode)
{
CLEAR_REG32_BIT(EMBx->RLSSEL, u32Event);
}
else
{
SET_REG32_BIT(EMBx->RLSSEL, u32Event);
}
}
/**
* @brief Get EMB status
* @param [in] EMBx Pointer to EMB instance register base
* This parameter can be one of the following values:
* @arg M4_EMB0: EMB group 0 instance register base
* @arg M4_EMB1: EMB group 1 instance register base
* @arg M4_EMB2: EMB group 2 instance register base
* @arg M4_EMB3: EMB group 3 instance register base
* @arg M4_EMB4: EMB group 4 instance register base
* @arg M4_EMB5: EMB group 5 instance register base
* @arg M4_EMB6: EMB group 6 instance register base
* @param [in] u32Flag EMB flag
* This parameter can be one of the following values:
* @arg EMB_FLAG_PWMS: PWM same phase trigger stop PWM
* @arg EMB_FLAG_CMP: CMP trigger stop PWM
* @arg EMB_FLAG_OSC: OSC trigger stop PWM
* @arg EMB_FLAG_PORT1: EMB Port1 input trigger stop PWM
* @arg EMB_FLAG_PORT2: EMB Port2 input trigger stop PWM
* @arg EMB_FLAG_PORT3: EMB Port3 input trigger stop PWM
* @arg EMB_FLAG_PORT4: EMB Port4 input trigger stop PWM
* @retval An en_flag_status_t enumeration value:
* - Set: Flag is set
* - Reset: Flag is reset
*/
en_flag_status_t EMB_GetFlag(const M4_EMB_TypeDef *EMBx, uint32_t u32Flag)
{
/* Check parameters */
DDL_ASSERT(IS_VALID_EMB(EMBx));
DDL_ASSERT(IS_VALID_EMB_FLAG(u32Flag));
return READ_REG32_BIT(EMBx->STAT, u32Flag) ? Set : Reset;
}
/**
* @brief Get EMB status
* @param [in] EMBx Pointer to EMB instance register base
* This parameter can be one of the following values:
* @arg M4_EMB0: EMB group 0 instance register base
* @arg M4_EMB1: EMB group 1 instance register base
* @arg M4_EMB2: EMB group 2 instance register base
* @arg M4_EMB3: EMB group 3 instance register base
* @arg M4_EMB4: EMB group 4 instance register base
* @arg M4_EMB5: EMB group 5 instance register base
* @arg M4_EMB6: EMB group 6 instance register base
* @param [in] u32Flag EMB flag
* This parameter can be one of the following values:
* @arg EMB_FLAG_PWMS: PWM same phase trigger stop PWM
* @arg EMB_FLAG_CMP: CMP trigger stop PWM
* @arg EMB_FLAG_OSC: OSC trigger stop PWM
* @arg EMB_FLAG_PORT1: EMB Port1 input trigger stop PWM
* @arg EMB_FLAG_PORT2: EMB Port2 input trigger stop PWM
* @arg EMB_FLAG_PORT3: EMB Port3 input trigger stop PWM
* @arg EMB_FLAG_PORT4: EMB Port4 input trigger stop PWM
* @retval None
*/
void EMB_ClearFlag(M4_EMB_TypeDef *EMBx, uint32_t u32Flag)
{
/* Check parameters */
DDL_ASSERT(IS_VALID_EMB(EMBx));
DDL_ASSERT(IS_VALID_EMB_FLAG(u32Flag));
SET_REG32_BIT(EMBx->STATCLR, u32Flag);
}
/**
* @brief Get EMB status
* @param [in] EMBx Pointer to EMB instance register base
* This parameter can be one of the following values:
* @arg M4_EMB0: EMB group 0 instance register base
* @arg M4_EMB1: EMB group 1 instance register base
* @arg M4_EMB2: EMB group 2 instance register base
* @arg M4_EMB3: EMB group 3 instance register base
* @arg M4_EMB4: EMB group 4 instance register base
* @arg M4_EMB5: EMB group 5 instance register base
* @arg M4_EMB6: EMB group 6 instance register base
* @param [in] u32Status EMB state
* This parameter can be one of the following values:
* @arg EMB_STATE_PWMS: PWM same phase occur
* @arg EMB_STATE_CMP: CMP comapre event occur
* @arg EMB_STATE_OSC: OSC stop event occur
* @arg EMB_STATE_PORT1: EMB Port1 input control state
* @arg EMB_STATE_PORT2: EMB Port2 input control state
* @arg EMB_STATE_PORT3: EMB Port3 input control state
* @arg EMB_STATE_PORT4: EMB Port4 input control state
* @retval An en_flag_status_t enumeration value:
* - Set: Flag is set
* - Reset: Flag is reset
*/
en_flag_status_t EMB_GetStatus(const M4_EMB_TypeDef *EMBx,
uint32_t u32Status)
{
/* Check parameters */
DDL_ASSERT(IS_VALID_EMB(EMBx));
DDL_ASSERT(IS_VALID_EMB_STATUS(u32Status));
return READ_REG32_BIT(EMBx->STAT, u32Status) ? Set : Reset;
}
/**
* @brief Start/stop EMB software brake
* @param [in] EMBx Pointer to EMB instance register base
* This parameter can be one of the following values:
* @arg M4_EMB0: EMB group 0 instance register base
* @arg M4_EMB1: EMB group 1 instance register base
* @arg M4_EMB2: EMB group 2 instance register base
* @arg M4_EMB3: EMB group 3 instance register base
* @arg M4_EMB4: EMB group 4 instance register base
* @arg M4_EMB5: EMB group 5 instance register base
* @arg M4_EMB6: EMB group 6 instance register base
* @param [in] enNewState The function new state
* @arg This parameter can be: Enable or Disable
* @retval None
*/
void EMB_SwBrake(M4_EMB_TypeDef *EMBx, en_functional_state_t enNewState)
{
/* Check parameters */
DDL_ASSERT(IS_VALID_EMB(EMBx));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
WRITE_REG32(EMBx->SOE, enNewState);
}
/**
* @}
*/
#endif /* DDL_EMB_ENABLE */
/**
* @}
*/
/**
* @}
*/
/******************************************************************************
* EOF (not truncated)
*****************************************************************************/

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bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_eth.c Normal file
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