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Merge remote-tracking branch 'gitee/gitee_master'

This commit is contained in:
bernard 2020-12-19 15:13:36 +08:00
parent eaf3e4795d c1fa39a821
commit c924330469
269 changed files with 43125 additions and 38906 deletions
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108
bsp/essemi/es32f0334/.config
View File

@ -64,7 +64,7 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40002
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@ -115,18 +115,29 @@ CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
CONFIG_RT_USING_HWTIMER=y
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_I2C=y
# CONFIG_RT_I2C_DEBUG is not set
CONFIG_RT_USING_I2C_BITOPS=y
# CONFIG_RT_I2C_BITOPS_DEBUG is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_PWM is not set
CONFIG_RT_USING_ADC=y
# CONFIG_RT_USING_DAC is not set
CONFIG_RT_USING_PWM=y
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
CONFIG_RT_USING_PM=y
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
@ -192,11 +203,15 @@ CONFIG_RT_USING_PIN=y
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
@ -223,6 +238,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
@ -235,8 +251,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
@ -251,6 +269,15 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
#
# security packages
@ -258,6 +285,8 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
@ -274,6 +303,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_HELIX is not set
#
# tools packages
@ -289,6 +319,12 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
#
# system packages
@ -299,6 +335,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@ -307,6 +344,15 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_PPOOL is not set
#
# peripheral libraries and drivers
@ -323,6 +369,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
@ -336,9 +386,27 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_LCD_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
#
# miscellaneous packages
@ -373,8 +441,14 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
#
# Hardware Drivers Config
@ -442,4 +516,18 @@ CONFIG_BSP_USING_UART1=y
#
# Offboard Peripheral Drivers
#
#
# Peripheral Drivers test example
#
# CONFIG_BSP_USING_EXAMPLE_ADC_VOL is not set
# CONFIG_BSP_USING_EXAMPLE_HWTIMER is not set
# CONFIG_BSP_USING_EXAMPLE_I2C is not set
# CONFIG_BSP_USING_EXAMPLE_LED_BLINK is not set
# CONFIG_BSP_USING_EXAMPLE_PIN_BEEP is not set
# CONFIG_BSP_USING_EXAMPLE_PWM_LED is not set
# CONFIG_BSP_USING_EXAMPLE_RTC is not set
# CONFIG_BSP_USING_EXAMPLE_SPI is not set
# CONFIG_BSP_USING_EXAMPLE_UART is not set
# CONFIG_BSP_USING_EXAMPLE_PM is not set
CONFIG_SOC_ES32F0334LT=y

18
bsp/essemi/es32f0334/README.md
View File

@ -86,6 +86,22 @@ msh >
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
a）如果需要使用内核用例，先配置rt-thread内核，如图：
![kernel_config](figures/k_conf.jpg)
然后配置内核用例，如图：
![kernel_samples](figures/k_ex.jpg)
b）如果需要使用驱动用例：先使能驱动，如图：
![driver_config](figures/drv_conf.jpg)
然后配置驱动用例，如图：
![driver_sample](figures/drv_ex.jpg)
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
@ -94,7 +110,7 @@ msh >
## 4. 联系人信息
- [wangyongquan](https://github.com/wangyq2018)
- [liuhongyan](https://gitee.com/liuhongyan98)
## 5. 参考

46
bsp/essemi/es32f0334/drivers/Kconfig
View File

@ -127,4 +127,50 @@ menu "Hardware Drivers Config"
endmenu
menu "Peripheral Drivers test example"
config BSP_USING_EXAMPLE_ADC_VOL
bool "BSP_USING_EXAMPLE_ADC_VOL"
default n
config BSP_USING_EXAMPLE_HWTIMER
bool "BSP_USING_EXAMPLE_HWTIMER"
default n
config BSP_USING_EXAMPLE_I2C
bool "BSP_USING_EXAMPLE_I2C"
default n
config BSP_USING_EXAMPLE_LED_BLINK
bool "BSP_USING_EXAMPLE_LED_BLINK"
default y
config BSP_USING_EXAMPLE_PIN_BEEP
bool "BSP_USING_EXAMPLE_PIN_BEEP"
default y
config BSP_USING_EXAMPLE_PWM_LED
bool "BSP_USING_EXAMPLE_PWM_LED"
default n
config BSP_USING_EXAMPLE_RTC
bool "BSP_USING_EXAMPLE_RTC"
default n
config BSP_USING_EXAMPLE_SPI
bool "BSP_USING_EXAMPLE_SPI"
default n
config BSP_USING_EXAMPLE_UART
bool "BSP_USING_EXAMPLE_UART"
default y
config BSP_USING_EXAMPLE_PM
bool "BSP_USING_EXAMPLE_PM"
default n
endmenu
endmenu

42
bsp/essemi/es32f0334/drivers/SConscript
View File

@ -2,6 +2,8 @@ from building import *
cwd = GetCurrentDir()
objs = []
# add the general drivers.
src = Split('''
board.c
@ -50,5 +52,43 @@ if GetDepend(['BSP_USING_ADC']):
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
objs = objs + group
Return('group')
src = []
cwd = GetCurrentDir()
include_path = [cwd]
if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'):
src += ['bsp_driver_example/adc_vol_sample.c']
if GetDepend('BSP_USING_EXAMPLE_HWTIMER'):
src += ['bsp_driver_example/hwtimer_sample.c']
if GetDepend('BSP_USING_EXAMPLE_I2C'):
src += ['bsp_driver_example/i2c_sample.c']
if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'):
src += ['bsp_driver_example/led_blink_sample.c']
if GetDepend('BSP_USING_EXAMPLE_PIN_BEEP'):
src += ['bsp_driver_example/pin_beep_sample.c']
if GetDepend('BSP_USING_EXAMPLE_PWM_LED'):
src += ['bsp_driver_example/pwm_led_sample.c']
if GetDepend('BSP_USING_EXAMPLE_RTC'):
src += ['bsp_driver_example/rtc_sample.c']
if GetDepend('BSP_USING_EXAMPLE_UART'):
src += ['bsp_driver_example/uart_sample.c']
if GetDepend('BSP_USING_EXAMPLE_SPI'):
src += ['bsp_driver_example/spi_sample.c']
if GetDepend('BSP_USING_EXAMPLE_PM'):
src += ['bsp_driver_example/pm_sample.c']
group = DefineGroup('bsp-drivers-test-samples', src, depend = [''], CPPPATH = include_path)
objs = objs + group
Return('objs')

52
bsp/essemi/es32f0334/drivers/bsp_driver_example/.gitignore vendored Normal file
View File

@ -0,0 +1,52 @@
# Prerequisites
*.d
# Object files
*.o
*.ko
*.obj
*.elf
# Linker output
*.ilk
*.map
*.exp
# Precompiled Headers
*.gch
*.pch
# Libraries
*.lib
*.a
*.la
*.lo
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
*.i*86
*.x86_64
*.hex
# Debug files
*.dSYM/
*.su
*.idb
*.pdb
# Kernel Module Compile Results
*.mod*
*.cmd
.tmp_versions/
modules.order
Module.symvers
Mkfile.old
dkms.conf

47
bsp/essemi/es32f0334/drivers/bsp_driver_example/README.md Normal file
View File

@ -0,0 +1,47 @@
# 外设驱动测试用例
## 1、介绍
这个软件包包含一些外设设备操作的例程。
### 1.1 例程说明
| 文件 | 说明 |
| ---------------- | ------------------------------- |
| adc_vol_sample.c | 使用 ADC 设备转换电压数据 |
| can_sample.c | 通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。 |
| hwtimer_sample.c | 使用 硬件定时器定时 |
| i2c_sample.c | 使用 i2c 设备进行读写 |
| pm.c | 反复进入不同程度的睡眠。 |
| led_blink_sample.c | 使用 pin 设备控制 LED 闪烁 |
| pin_beep_sample.c | 使用 pin 设备控制蜂鸣器 |
| pwm_led_sample.c | 使用 pwm 设备控制 LED 的亮度 |
| rtc_sample.c | 使用 rtc 设备设置年月日时分秒信息 |
| spi_sample.c | 使用 spi 设备进行读写 |
| uart_sample.c | 使用 serial 设备中断接收及轮询发送模式收发数据 |
### 1.2 依赖
依赖设备管理模块提供的设备驱动。
## 2、如何打开 外设驱动测试用例
使用 外设驱动测试用例 需要在 RT-Thread 的menuconfig中选择它，具体路径如下：
```
Hardware Driver Config --->
Peripheral Driver test example--->
```
## 3、使用 外设驱动测试用例
在打开 Peripheral Driver test example 后，当进行 BSP 编译时，选择的软件包相关源代码会被加入到 BSP 工程中进行编译。
## 4、注意事项
暂无。
## 5、联系方式 & 感谢
* 维护：[misonyo](https://github.com/misonyo)
* 主页：https://github.com/RT-Thread-packages/peripheral-sample

57
bsp/essemi/es32f0334/drivers/bsp_driver_example/adc_vol_sample.c Normal file
View File

@ -0,0 +1,57 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-29 misonyo first implementation.
*/
/*
* 程序清单： ADC 设备使用例程
* 例程导出了 adc_sample 命令到控制终端
* 命令调用格式：adc_sample
* 程序功能：通过 ADC 设备采样电压值并转换为数值。
* 示例代码参考电压为3.3V,转换位数为12位。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define ADC_DEV_NAME "adc0" /* ADC 设备名称 */
#define ADC_DEV_CHANNEL 5 /* PA1 ADC 通道 */
#define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/
#define CONVERT_BITS (1 << 12) /* 转换位数为12位 */
static int adc_vol_sample(int argc, char *argv[])
{
rt_adc_device_t adc_dev;
rt_uint32_t value, vol;
rt_err_t ret = RT_EOK;
/* 查找设备 */
adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME);
if (adc_dev == RT_NULL)
{
rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME);
return RT_ERROR;
}
/* 使能设备 */
ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
/* 读取采样值 */
value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
rt_kprintf("the value is :%d \n", value);
/* 转换为对应电压值 */
vol = value * REFER_VOLTAGE / CONVERT_BITS;
rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
/* 关闭通道 */
ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
return ret;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample);

144
bsp/essemi/es32f0334/drivers/bsp_driver_example/can_sample.c Normal file
View File

@ -0,0 +1,144 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-06-25 misonyo first implementation.
*/
/*
* 程序清单：这是一个 CAN 设备使用例程
* 例程导出了 can_sample 命令到控制终端
* 命令调用格式：can_sample can2
* 命令解释：命令第二个参数是要使用的 CAN 设备名称，为空则使用默认的 CAN 设备
* 程序功能：通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。
*/
#include <rtthread.h>
#include "rtdevice.h"
#define CAN_DEV_NAME "can2" /* CAN 设备名称 */
static struct rt_semaphore rx_sem; /* 用于接收消息的信号量 */
static rt_device_t can_dev; /* CAN 设备句柄 */
/* 接收数据回调函数 */
static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size)
{
/* CAN 接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */
rt_sem_release(&rx_sem);
return RT_EOK;
}
static void can_rx_thread(void *parameter)
{
int i;
struct rt_can_msg rxmsg = {0};
/* 设置接收回调函数 */
rt_device_set_rx_indicate(can_dev, can_rx_call);
#ifdef RT_CAN_USING_HDR
rt_err_t res;
struct rt_can_filter_item items[5] =
{
RT_CAN_FILTER_ITEM_INIT(0x100, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x100~0x1ff，hdr为-1，设置默认过滤表 */
RT_CAN_FILTER_ITEM_INIT(0x300, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x300~0x3ff，hdr为-1 */
RT_CAN_FILTER_ITEM_INIT(0x211, 0, 0, 0, 0x7ff, RT_NULL, RT_NULL), /* std,match ID:0x211，hdr为-1 */
RT_CAN_FILTER_STD_INIT(0x486, RT_NULL, RT_NULL), /* std,match ID:0x486，hdr为-1 */
{0x555, 0, 0, 0, 0x7ff, 7,} /* std,match ID:0x555，hdr为7，指定设置7号过滤表 */
};
struct rt_can_filter_config cfg = {5, 1, items}; /* 一共有5个过滤表 */
/* 设置硬件过滤表 */
res = rt_device_control(can_dev, RT_CAN_CMD_SET_FILTER, &cfg);
RT_ASSERT(res == RT_EOK);
#endif
while (1)
{
/* hdr值为-1，表示直接从uselist链表读取数据 */
rxmsg.hdr = -1;
/* 阻塞等待接收信号量 */
rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
/* 从CAN读取一帧数据 */
rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg));
/* 打印数据ID及内容 */
rt_kprintf("ID:%x ", rxmsg.id);
for (i = 0; i < 8; i++)
{
rt_kprintf("%2x ", rxmsg.data[i]);
}
rt_kprintf("\n");
}
}
int can_sample(int argc, char *argv[])
{
struct rt_can_msg msg = {0};
rt_err_t res;
rt_size_t size;
rt_thread_t thread;
char can_name[RT_NAME_MAX];
if (argc == 2)
{
rt_strncpy(can_name, argv[1], RT_NAME_MAX);
}
else
{
rt_strncpy(can_name, CAN_DEV_NAME, RT_NAME_MAX);
}
can_dev = rt_device_find(can_name);
if (!can_dev)
{
rt_kprintf("find %s failed!\n", can_name);
return RT_ERROR;
}
/* 初始化CAN接收信号量 */
rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
/* 以中断接收及发送方式打开CAN设备 */
res = rt_device_open(can_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX);
RT_ASSERT(res == RT_EOK);
thread = rt_thread_create("can_rx", can_rx_thread, RT_NULL, 1024, 25, 10);
if (thread != RT_NULL)
{
rt_thread_startup(thread);
}
else
{
rt_kprintf("create can_rx thread failed!\n");
}
msg.id = 0x78; /* ID为0x78 */
msg.ide = RT_CAN_STDID; /* 标准格式 */
msg.rtr = RT_CAN_DTR; /* 数据帧 */
msg.len = 8; /* 数据长度为8 */
/* 待发送的8字节数据 */
msg.data[0] = 0x00;
msg.data[1] = 0x11;
msg.data[2] = 0x22;
msg.data[3] = 0x33;
msg.data[4] = 0x44;
msg.data[5] = 0x55;
msg.data[6] = 0x66;
msg.data[7] = 0x77;
/* 发送一帧CAN数据 */
size = rt_device_write(can_dev, 0, &msg, sizeof(msg));
if (size == 0)
{
rt_kprintf("can dev write data failed!\n");
}
return res;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(can_sample, can device sample);

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-30 misonyo first implementation.
*/
/*
* 程序清单：这是一个 hwtimer 设备使用例程
* 例程导出了 hwtimer_sample 命令到控制终端
* 命令调用格式：hwtimer_sample
* 程序功能：硬件定时器超时回调函数周期性的打印当前tick值，2次tick值之差换算为时间等同于定时时间值。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define HWTIMER_DEV_NAME "timer0" /* 定时器名称 */
/* 定时器超时回调函数 */
static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
{
rt_kprintf("tick is :%d !\n", rt_tick_get());
return 0;
}
static int hwtimer_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
rt_hwtimerval_t timeout_s; /* 定时器超时值 */
rt_device_t hw_dev = RT_NULL; /* 定时器设备句柄 */
rt_hwtimer_mode_t mode; /* 定时器模式 */
/* 查找定时器设备 */
hw_dev = rt_device_find(HWTIMER_DEV_NAME);
if (hw_dev == RT_NULL)
{
rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME);
return RT_ERROR;
}
/* 以读写方式打开设备 */
ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
if (ret != RT_EOK)
{
rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME);
return ret;
}
/* 设置超时回调函数 */
rt_device_set_rx_indicate(hw_dev, timeout_cb);
/* 设置模式为周期性定时器 */
mode = HWTIMER_MODE_PERIOD;
ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode);
if (ret != RT_EOK)
{
rt_kprintf("set mode failed! ret is :%d\n", ret);
return ret;
}
/* 设置定时器超时值为5s并启动定时器 */
timeout_s.sec = 5; /* 秒 */
timeout_s.usec = 0; /* 微秒 */
if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
{
rt_kprintf("set timeout value failed\n");
return RT_ERROR;
}
/* 延时3500ms */
rt_thread_mdelay(3500);
/* 读取定时器当前值 */
rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
return ret;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);

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bsp/essemi/es32f0334/drivers/bsp_driver_example/i2c_sample.c Normal file
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/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-12-15 liuhy first implementation.
*/
/*
* 程序清单：这是一个 I2C 设备使用例程
* 例程导出了 i2c_io_sample 命令到控制终端
* 命令调用格式：i2c_io_sample
* 命令解释：使用默认的I2C总线设备
* 程序功能：通过 I2C 设备接收数据并打印，然后将接收的字符加1输出。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define I2C_BUS_NAME "i2c1" /* I2C总线设备名称 */
#define SLAVE_ADDR 0x2D /* 从机地址 */
#define STR_LEN 16 /* 接收发送的数据长度 */
static void i2c_io_sample(int argc, char *argv[])
{
struct rt_i2c_bus_device *i2c_bus = RT_NULL; /* I2C总线设备句柄 */
struct rt_i2c_msg temp_msg; /* I2C消息 */
rt_uint8_t buffer[STR_LEN] = { 0U };
rt_uint32_t i,num_msg;
rt_size_t s_stat;
i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(I2C_BUS_NAME); /* 通过名字获取I2C总线设备的句柄 */
if( i2c_bus == RT_NULL)
{
rt_kprintf("can't find i2c device :%s !\n",I2C_BUS_NAME);
return;
}
/*初始化消息*/
temp_msg.addr = SLAVE_ADDR; /* 从机地址 */
temp_msg.len = STR_LEN; /* 传输的数据长度 */
temp_msg.buf = buffer; /* 读写缓存器 */
num_msg = 1; /* 传输一条消息 */
temp_msg.flags = RT_I2C_RD; /* I2C读 */
s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输消息 */
rt_thread_mdelay(400);
if( s_stat == num_msg )
{
rt_kprintf("receive successful. \n receive messege : %s \n:",buffer);
for( i = 0 ; i < STR_LEN ; i++)
rt_kprintf(" %x",(unsigned int)buffer[i]);
rt_kprintf("\n");
}
else
{
rt_kprintf("device s% recieve fail \n buffer : s%\n",I2C_BUS_NAME,buffer);
return;
}
for( i = 0 ; i < STR_LEN ; i++)
buffer[i]++;
temp_msg.flags = RT_I2C_WR; /* I2C写 */
s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输一条 */
rt_thread_mdelay(400);
if( s_stat == num_msg )
{
rt_kprintf(" send successful \n messege : %s \n:",buffer);
for( i = 0 ; i < STR_LEN ; i++)
rt_kprintf(" %x",(unsigned int)buffer[i]);
rt_kprintf("\n");
}
else
{
rt_kprintf("device s% send fail \n",I2C_BUS_NAME);
return;
}
return;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(i2c_io_sample, i2c io sample);

83
bsp/essemi/es32f0334/drivers/bsp_driver_example/led_blink_sample.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-09-25 misonyo first edition.
*/
/*
* 程序清单：这是一个通过PIN脚控制LED亮灭的使用例程
* 例程导出了 led_sample 命令到控制终端
* 命令调用格式：led_sample
* 命令解释：命令第二个参数是要使用的PIN脚编号，为空则使用例程默认的引脚编号。
* 程序功能：程序创建一个led线程，线程每隔1000ms改变PIN脚状态，达到控制led灯
* 亮灭的效果。
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <stdlib.h>
/* PIN脚编号，查看驱动文件drv_gpio.c确定 */
#define LED_PIN_NUM 45 /*PA12*/
static int pin_num;
static void led_entry(void *parameter)
{
int count = 0;
/* 设置PIN脚模式为输出 */
rt_pin_mode(pin_num, PIN_MODE_OUTPUT);
while (1)
{
count++;
rt_kprintf("thread run count : %d\r\n", count);
/* 拉低PIN脚 */
rt_pin_write(pin_num, PIN_LOW);
rt_kprintf("led on!\r\n");
/* 延时1000ms */
rt_thread_mdelay(1000);
/* 拉高PIN脚 */
rt_pin_write(pin_num, PIN_HIGH);
rt_kprintf("led off!\r\n");
rt_thread_mdelay(1000);
}
}
static int led_sample(int argc, char *argv[])
{
rt_thread_t tid;
rt_err_t ret = RT_EOK;
/* 判断命令行参数是否给定了PIN脚编号 */
if (argc == 2)
{
pin_num = atoi(argv[1]);
}
else
{
pin_num = LED_PIN_NUM;
}
tid = rt_thread_create("led",
led_entry,
RT_NULL,
512,
RT_THREAD_PRIORITY_MAX / 3,
20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
ret = RT_ERROR;
}
return ret;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(led_sample, led sample);

67
bsp/essemi/es32f0334/drivers/bsp_driver_example/pin_beep_sample.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-08-15 misonyo first implementation.
*/
/*
* 程序清单：这是一个 PIN 设备使用例程
* 例程导出了 pin_beep_sample 命令到控制终端
* 命令调用格式：pin_beep_sample
* 程序功能：通过按键控制蜂鸣器对应引脚的电平状态控制蜂鸣器
*/
#include <rtthread.h>
#include <rtdevice.h>
/* 引脚编号，通过查看驱动文件drv_gpio.c确定 */
#ifndef BEEP_PIN_NUM
#define BEEP_PIN_NUM 45 /* PA12 */
#endif
#ifndef KEY0_PIN_NUM
#define KEY0_PIN_NUM 18 /* PF0 */
#endif
#ifndef KEY1_PIN_NUM
#define KEY1_PIN_NUM 19 /* PF1 */
#endif
void beep_on(void *args)
{
rt_kprintf("turn on beep!\n");
rt_pin_write(BEEP_PIN_NUM, PIN_HIGH);
}
void beep_off(void *args)
{
rt_kprintf("turn off beep!\n");
rt_pin_write(BEEP_PIN_NUM, PIN_LOW);
}
static void pin_beep_sample(void)
{
/* 蜂鸣器引脚为输出模式 */
rt_pin_mode(BEEP_PIN_NUM, PIN_MODE_OUTPUT);
/* 默认低电平 */
rt_pin_write(BEEP_PIN_NUM, PIN_LOW);
/* 按键0引脚为输入模式 */
rt_pin_mode(KEY0_PIN_NUM, PIN_MODE_INPUT_PULLUP);
/* 绑定中断，下降沿模式，回调函数名为beep_on */
rt_pin_attach_irq(KEY0_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_on, RT_NULL);
/* 使能中断 */
rt_pin_irq_enable(KEY0_PIN_NUM, PIN_IRQ_ENABLE);
/* 按键1引脚为输入模式 */
rt_pin_mode(KEY1_PIN_NUM, PIN_MODE_INPUT_PULLUP);
/* 绑定中断，下降沿模式，回调函数名为beep_off */
rt_pin_attach_irq(KEY1_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_off, RT_NULL);
/* 使能中断 */
rt_pin_irq_enable(KEY1_PIN_NUM, PIN_IRQ_ENABLE);
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(pin_beep_sample, pin beep sample);

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bsp/essemi/es32f0334/drivers/bsp_driver_example/pm_sample.c Normal file
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/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-12-15 liuhy first implementation.
*/
/*
* 程序清单：这是一个 pm睡眠唤醒的使用例程
* 例程导出了 pm_sample 命令到控制终端
* 命令调用格式：pm_sample
* 命令解释：进入不同的睡眠模式，然后用按键唤醒
* 程序功能：通过串口输出字符串，告知进入睡眠和唤醒睡眠的情况。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define PM_NAME "pm" /* 设备名称 */
#define WAKE_UP_PIN 18 /* 唤醒源 */
#define SLEEP_TIMES 12 /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */
struct pm_callback_t
{
volatile int in_fun_times; /*进入函数的次数*/
volatile char flag; /*标志*/
volatile int mode; /*需要打印的模式*/
};
volatile struct pm_callback_t g_pm_data;
/*进入睡眠前，睡眠唤醒后，都会进入。*/
/*函数打印睡眠相关的信息*/
void sleep_in_out_callback(rt_uint8_t event, rt_uint8_t mode, void *data)
{
/*没有标志，不处理*/
if(!(g_pm_data.flag))
{
return;
}
/*标志不正常，清空标志*/
if((g_pm_data.flag) > 2)
{
(g_pm_data.flag) = 0;
return;
}
/*模式不匹配*/
if(g_pm_data.mode != mode )
{
return;
}
/*进入的事件*/
switch(event)
{
/*进入睡眠前*/
case RT_PM_ENTER_SLEEP: g_pm_data.flag = 1;
rt_kprintf("\n\r##%d : ENTER ",g_pm_data.in_fun_times);
g_pm_data.in_fun_times++; /*进入睡眠次数+1*/
break;
/*睡眠唤醒后*/
case RT_PM_EXIT_SLEEP: g_pm_data.flag = 0; /*睡眠唤醒后*/
rt_kprintf("\n\rEXIT\n\r");
rt_pm_release(mode); /*释放休眠模式*/
return;
default: break;
};
/*当前的睡眠模式*/
switch(mode)
{
case PM_SLEEP_MODE_NONE: rt_kprintf("PM_SLEEP_MODE_NONE\n\r");
break;
case PM_SLEEP_MODE_IDLE: rt_kprintf("PM_SLEEP_MODE_IDLE\n\r");
break;
case PM_SLEEP_MODE_LIGHT: rt_kprintf("PM_SLEEP_MODE_LIGHT\n\r");
break;
case PM_SLEEP_MODE_DEEP: rt_kprintf("PM_SLEEP_MODE_DEEP\n\r");
break;
case PM_SLEEP_MODE_STANDBY: rt_kprintf("PM_SLEEP_MODE_STANDBY\n\r");
break;
case PM_SLEEP_MODE_SHUTDOWN: rt_kprintf("PM_SLEEP_MODE_SHUTDOWN\n\r");
break;
case PM_SLEEP_MODE_MAX: rt_kprintf("PM_SLEEP_MODE_MAX\n\r");
break;
default: break;
}
}
/* pm测试函数 */
static void pm_test(void *parameter)
{
int in_mode[7],i = 0;
g_pm_data.in_fun_times = 0;
g_pm_data.flag = 0;
in_mode[0] = PM_SLEEP_MODE_NONE;
in_mode[1] = PM_SLEEP_MODE_IDLE;
in_mode[2] = PM_SLEEP_MODE_LIGHT;
in_mode[3] = PM_SLEEP_MODE_DEEP;
in_mode[4] = PM_SLEEP_MODE_STANDBY;
in_mode[5] = PM_SLEEP_MODE_SHUTDOWN;
in_mode[6] = PM_SLEEP_MODE_MAX;
/*设置回调函数和私有数据*/
rt_pm_notify_set(sleep_in_out_callback,RT_NULL);
while(i < SLEEP_TIMES)
{
g_pm_data.mode = in_mode[i%6];
/*无休眠模式，不赋予标志*/
if(g_pm_data.mode != PM_SLEEP_MODE_NONE)
{
g_pm_data.flag = 2;
}
/*请求选择的休眠模式*/
rt_pm_request(in_mode[i%6]);
rt_thread_mdelay(500);
/*无休眠模式，不需要额外的等待*/
while(( g_pm_data.flag != 0 )&&(g_pm_data.mode != PM_SLEEP_MODE_NONE))
{
rt_thread_mdelay(500);
}
/*释放选择的休眠模式*/
rt_pm_release(in_mode[i%6]);
i++;
}
/*清除回调函数和私有数据*/
rt_pm_notify_set(RT_NULL,RT_NULL);
rt_kprintf("thread pm_test close\n\r");
}
/*按键唤醒的回调函数*/
void wake_by_pin(void *args)
{
}
static int pm_sample(int argc, char *argv[])
{
rt_thread_t thread;
/* 按键引脚为输入模式 */
rt_pin_mode(WAKE_UP_PIN, PIN_MODE_INPUT_PULLUP);
/* 绑定中断，下降沿模式，回调函数名为wake_by_pin */
rt_pin_attach_irq(WAKE_UP_PIN, PIN_IRQ_MODE_RISING, wake_by_pin, RT_NULL);
/* 使能中断 */
rt_pin_irq_enable(WAKE_UP_PIN, PIN_IRQ_ENABLE);
thread = rt_thread_create("pm_test", pm_test, RT_NULL, 1024, 25, 10);
if (thread != RT_NULL)
{
rt_thread_startup(thread);
}
else
{
rt_kprintf("create pm_test thread failed!\n\r");
}
return RT_EOK;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(pm_sample, pm sample);

72
bsp/essemi/es32f0334/drivers/bsp_driver_example/pwm_led_sample.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-25 misonyo first implementation.
*/
/*
* 程序清单：这是一个 PWM 设备使用例程
* 例程导出了 pwm_led_sample 命令到控制终端
* 命令调用格式：pwm_led_sample
* 程序功能：通过 PWM 设备控制 LED 灯的亮度，可以看到LED不停的由暗变到亮，然后又从亮变到暗。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define LED_PIN_NUM 45 /* PA12 LED PIN脚编号，查看驱动文件drv_gpio.c确定 */
#define PWM_DEV_NAME "pwm0" /* PWM设备名称 */
#define PWM_DEV_CHANNEL 2 /* PA9 PWM通道 */
struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */
static int pwm_led_sample(int argc, char *argv[])
{
rt_uint32_t period, pulse, dir;
period = 500000; /* 周期为0.5ms，单位为纳秒ns */
dir = 1; /* PWM脉冲宽度值的增减方向 */
pulse = 0; /* PWM脉冲宽度值，单位为纳秒ns */
/* 查找设备 */
pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
if (pwm_dev == RT_NULL)
{
rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME);
return RT_ERROR;
}
/* 设置PWM周期和脉冲宽度默认值 */
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
/* 使能设备 */
rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
while (1)
{
rt_thread_mdelay(50);
if (dir)
{
pulse += 5000; /* 从0值开始每次增加5000ns */
}
else
{
pulse -= 5000; /* 从最大值开始每次减少5000ns */
}
if (pulse >= period)
{
dir = 0;
}
if (0 == pulse)
{
dir = 1;
}
/* 设置PWM周期和脉冲宽度 */
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
}
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(pwm_led_sample, pwm sample);

51
bsp/essemi/es32f0334/drivers/bsp_driver_example/rtc_sample.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-30 misonyo first implementation.
*/
/*
* 程序清单：这是一个 RTC 设备使用例程
* 例程导出了 rtc_sample 命令到控制终端
* 命令调用格式：rtc_sample
* 程序功能：设置RTC设备的日期和时间，延时一段时间后获取当前时间并打印显示。
*/
#include <rtthread.h>
#include <rtdevice.h>
static int rtc_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
time_t now;
/* 设置日期 */
ret = set_date(2018, 12, 3);
if (ret != RT_EOK)
{
rt_kprintf("set RTC date failed\n");
return ret;
}
/* 设置时间 */
ret = set_time(11, 15, 50);
if (ret != RT_EOK)
{
rt_kprintf("set RTC time failed\n");
return ret;
}
/* 延时3秒 */
rt_thread_mdelay(3000);
/* 获取时间 */
now = time(RT_NULL);
rt_kprintf("%s\n", ctime(&now));
return ret;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(rtc_sample, rtc sample);

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bsp/essemi/es32f0334/drivers/bsp_driver_example/spi_sample.c Normal file
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@ -0,0 +1,152 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-12-15 liuhy first implementation.
*/
/*
* 程序清单：这是一个 SPI 设备使用例程
* 例程导出了 spi_io_sample 命令到控制终端
* 命令调用格式：spi_io_sample
* 程序功能：通过SPI设备先读取数据，然后每个字符加1后输出。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define SPI_DEVICE_NAME "spi00"
#define BUF_LEN 16
static void spi_io_sample(int argc, char *argv[])
{
struct rt_spi_device * spi_dev; /* spi设备的句柄 */
struct rt_spi_configuration spi_config;
rt_uint8_t i,buffer[BUF_LEN] = { 0U };
rt_err_t s_stat;
rt_err_t result;
/* 查找 spi设备 获取spi设备句柄 */
spi_dev = (struct rt_spi_device *)rt_device_find(SPI_DEVICE_NAME);
if (spi_dev == RT_NULL)
{
rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_DEVICE_NAME);
return;
}
/* 清空配置结构体 */
rt_memset(&spi_config,0,sizeof(struct rt_spi_configuration));
spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */
spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */
spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */
spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */
spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */
spi_config.mode |= RT_SPI_MSB; /* 高位在前 */
spi_config.data_width = 8; /* 数据长度：8 */
spi_config.max_hz = 2000000; /* 最快时钟频率 */
/* 配置SPI设备 */
s_stat = rt_spi_configure(spi_dev,&spi_config);
if(s_stat != RT_EOK)
{
rt_kprintf(" spi config fail !\n ");
return;
}
/* 获取总线 ，防止总线被多个线程同时使用 */
result = rt_spi_take_bus(spi_dev);
if (result != RT_EOK)
{
rt_kprintf(" %s take spi bus failed! \n", SPI_DEVICE_NAME);
return;
}
/* 选中片选 */
result = rt_spi_take(spi_dev);
if (result != RT_EOK)
{
rt_kprintf(" %s take spi cs failed! \n", SPI_DEVICE_NAME);
return;
}
/*接收一次数据*/
result = rt_spi_recv(spi_dev,buffer,BUF_LEN);
if(result != BUF_LEN)
{
rt_kprintf("receive fail. \n buffer is : %s \n:",buffer);
for( i = 0 ; i < BUF_LEN ; i++)
rt_kprintf(" %x",(unsigned int)buffer[i]);
rt_kprintf("\n");
return;
}
rt_kprintf("receive successful. \n buffer is : %s \n:",buffer);
for( i = 0 ; i < BUF_LEN ; i++)
rt_kprintf(" %x",(unsigned int)buffer[i]);
rt_kprintf("\n");
/* 将接收到的数据加1 */
for( i = 0 ; i < BUF_LEN ; i++)
buffer[i]++;
/*发送数据*/
result = rt_spi_send(spi_dev,buffer,BUF_LEN);
if(result != BUF_LEN)
{
rt_kprintf("send fail. \n buffer is : %s \n:",buffer);
for( i = 0 ; i < BUF_LEN ; i++)
rt_kprintf(" %x",(unsigned int)buffer[i]);
rt_kprintf("\n");
return;
}
rt_kprintf("send successful. \n buffer is : %s \n:",buffer);
for( i = 0 ; i < BUF_LEN ; i++)
rt_kprintf(" %x",(unsigned int)buffer[i]);
rt_kprintf("\n");
/* 释放片选 */
result = rt_spi_release(spi_dev);
if (result != RT_EOK)
{
rt_kprintf(" %s release spi cs failed! \n", SPI_DEVICE_NAME);
return;
}
/* 释放总线 */
result = rt_spi_release_bus(spi_dev);
if (result != RT_EOK)
{
rt_kprintf(" %s release spi bus failed! \n", SPI_DEVICE_NAME);
return;
}
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(spi_io_sample, spi sample);

100
bsp/essemi/es32f0334/drivers/bsp_driver_example/uart_sample.c Normal file
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@ -0,0 +1,100 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-08-15 misonyo first implementation.
*/
/*
* 程序清单：这是一个 串口 设备使用例程
* 例程导出了 uart_sample 命令到控制终端
* 命令调用格式：uart_sample uart2
* 命令解释：命令第二个参数是要使用的串口设备名称，为空则使用默认的串口设备
* 程序功能：通过串口输出字符串"hello RT-Thread!"，然后错位输出输入的字符
*/
#include <rtthread.h>
#define SAMPLE_UART_NAME "uart1" /* 串口设备名称 */
/* 用于接收消息的信号量 */
static struct rt_semaphore rx_sem;
static rt_device_t serial;
/* 接收数据回调函数 */
static rt_err_t uart_input(rt_device_t dev, rt_size_t size)
{
/* 串口接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */
rt_sem_release(&rx_sem);
return RT_EOK;
}
static void serial_thread_entry(void *parameter)
{
char ch;
while (1)
{
/* 从串口读取一个字节的数据，没有读取到则等待接收信号量 */
while (rt_device_read(serial, -1, &ch, 1) != 1)
{
/* 阻塞等待接收信号量，等到信号量后再次读取数据 */
rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
}
/* 读取到的数据通过串口错位输出 */
ch = ch + 1;
rt_device_write(serial, 0, &ch, 1);
}
}
static int uart_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
char uart_name[RT_NAME_MAX];
char str[] = "hello RT-Thread!\r\n";
if (argc == 2)
{
rt_strncpy(uart_name, argv[1], RT_NAME_MAX);
}
else
{
rt_strncpy(uart_name, SAMPLE_UART_NAME, RT_NAME_MAX);
}
/* 查找串口设备 */
serial = rt_device_find(uart_name);
if (!serial)
{
rt_kprintf("find %s failed!\n", uart_name);
return RT_ERROR;
}
/* 初始化信号量 */
rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
/* 以中断接收及轮询发送方式打开串口设备 */
rt_device_open(serial, RT_DEVICE_FLAG_INT_RX);
/* 设置接收回调函数 */
rt_device_set_rx_indicate(serial, uart_input);
/* 发送字符串 */
rt_device_write(serial, 0, str, (sizeof(str) - 1));
/* 创建 serial 线程 */
rt_thread_t thread = rt_thread_create("serial", serial_thread_entry, RT_NULL, 1024, 25, 10);
/* 创建成功则启动线程 */
if (thread != RT_NULL)
{
rt_thread_startup(thread);
}
else
{
ret = RT_ERROR;
}
return ret;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(uart_sample, uart device sample);

24
bsp/essemi/es32f0334/drivers/drv_adc.c
View File

@ -146,9 +146,9 @@ static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t c
RT_ASSERT(value != RT_NULL);
/* config adc channel */
nm_config.channel = es32f0_adc_get_channel(channel);
nm_config.rank = ADC_NCH_RANK_1;
nm_config.samp_time = ADC_SAMPLETIME_4;
nm_config.ch = es32f0_adc_get_channel(channel);
nm_config.idx = ADC_NCH_IDX_1;
nm_config.samp = ADC_SAMPLETIME_4;
ald_adc_normal_channel_config(_hadc, &nm_config);
ald_adc_normal_start(_hadc);
@ -172,16 +172,16 @@ int rt_hw_adc_init(void)
/* adc function initialization */
_h_adc0.perh = ADC0;
_h_adc0.init.data_align = ADC_DATAALIGN_RIGHT;
_h_adc0.init.scan_mode = DISABLE;
_h_adc0.init.cont_mode = DISABLE;
_h_adc0.init.disc_mode = ADC_ALL_DISABLE;
_h_adc0.init.disc_nbr = ADC_DISC_NBR_1;
_h_adc0.init.conv_res = ADC_CONV_RES_10;
_h_adc0.init.clk_div = ADC_CKDIV_128;
_h_adc0.init.align = ADC_DATAALIGN_RIGHT;
_h_adc0.init.scan = DISABLE;
_h_adc0.init.cont = DISABLE;
_h_adc0.init.disc = ADC_ALL_DISABLE;
_h_adc0.init.disc_nr = ADC_DISC_NR_1;
_h_adc0.init.data_bit = ADC_CONV_BIT_12;
_h_adc0.init.div = ADC_CKDIV_128;
_h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL;
_h_adc0.init.neg_ref = ADC_NEG_REF_VSS;
_h_adc0.init.pos_ref = ADC_POS_REF_VDD;
_h_adc0.init.n_ref = ADC_NEG_REF_VSS;
_h_adc0.init.p_ref = ADC_POS_REF_VDD;
ald_adc_init(&_h_adc0);
rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, &_h_adc0);

3
bsp/essemi/es32f0334/drivers/drv_i2c.c
View File

@ -7,6 +7,7 @@
* Date Author Notes
* 2019-03-19 wangyq the first version
* 2019-11-01 wangyq update libraries
* 2020-12-15 liuhy update libraries
*/
#include <rtthread.h>
@ -29,7 +30,7 @@ static void _i2c_init(void)
/* Initialize I2C Pin */
gpio_instruct.mode = GPIO_MODE_OUTPUT;
gpio_instruct.odos = GPIO_PUSH_PULL;
gpio_instruct.odos = GPIO_OPEN_DRAIN;
gpio_instruct.pupd = GPIO_PUSH_UP;
gpio_instruct.odrv = GPIO_OUT_DRIVE_NORMAL;
gpio_instruct.flt = GPIO_FILTER_DISABLE;

21
bsp/essemi/es32f0334/drivers/drv_pm.c
View File

@ -8,7 +8,7 @@
* 2019-04-08 wangyq the first version
* 2019-11-01 wangyq adapt to the new power management interface
*/
#include <rthw.h>
#include <board.h>
#include <rtdevice.h>
#include <drv_lptim.h>
@ -24,6 +24,21 @@ static void uart_console_reconfig(void)
rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config);
}
static void delay(void)
{
long i;
rt_base_t level;
level = rt_hw_interrupt_disable();
i = 0;
do{
i++;
}
while (i < 10000);
rt_hw_interrupt_enable(level);
}
/**
* This function will put ES32F033x into sleep mode.
*
@ -50,22 +65,26 @@ static void sleep(struct rt_pm *pm, uint8_t mode)
{
/* Enter SLEEP Mode, Main regulator is ON */
ald_pmu_stop1_enter();
delay();
}
break;
case PM_SLEEP_MODE_DEEP:
/* Enter STOP 2 mode */
ald_pmu_stop2_enter();
delay();
break;
case PM_SLEEP_MODE_STANDBY:
/* Enter STANDBY mode */
ald_pmu_stop2_enter();
delay();
break;
case PM_SLEEP_MODE_SHUTDOWN:
/* Enter SHUTDOWNN mode */
ald_pmu_stop2_enter();
delay();
break;
default:

188
bsp/essemi/es32f0334/drivers/drv_spi.c
View File

@ -5,8 +5,9 @@
*
* Change Logs:
* Date Author Notes
* 2019-03-19 wangyq the first version
* 2019-01-24 wangyq the first version
* 2019-11-01 wangyq update libraries
* 2020-12-15 liuhy update libraries
*/
#include <rtthread.h>
@ -146,11 +147,30 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
hspi = (spi_handle_t *)device->bus->parent.user_data;
cs = device->parent.user_data;
if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL)
{
/* send & receive */
if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL))
{
if (message->cs_take)
{
rt_pin_write(cs->pin, 0);
}
res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
(rt_int32_t)message->length, SPITIMEOUT);
if (message->cs_release)
{
rt_pin_write(cs->pin, 1);
}
if (res != RT_EOK)
return RT_ERROR;
}
else
{
/* only send data */
if (message->recv_buf == RT_NULL)
{
@ -166,7 +186,6 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
if (res != RT_EOK)
return RT_ERROR;
}
/* only receive data */
if (message->send_buf == RT_NULL)
{
@ -182,25 +201,24 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
if (res != RT_EOK)
return RT_ERROR;
}
}
/* send & receive */
}
else
{
if (message->cs_take)
{
rt_pin_write(cs->pin, 0);
}
res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
(rt_int32_t)message->length, SPITIMEOUT);
if (message->cs_release)
{
rt_pin_write(cs->pin, 1);
}
if (res != RT_EOK)
return RT_ERROR;
return RT_EOK;
}
return message->length;
}
const struct rt_spi_ops es32f0_spi_ops =
@ -209,62 +227,6 @@ const struct rt_spi_ops es32f0_spi_ops =
spixfer,
};
static struct rt_spi_bus _spi_bus0, _spi_bus1;
static spi_handle_t _spi0, _spi1;
int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
{
struct rt_spi_bus *spi_bus;
spi_handle_t *spi;
gpio_init_t gpio_instruct;
if (SPIx == SPI0)
{
_spi0.perh = SPI0;
spi_bus = &_spi_bus0;
spi = &_spi0;
/* SPI0 gpio init */
gpio_instruct.mode = GPIO_MODE_OUTPUT;
gpio_instruct.odos = GPIO_PUSH_PULL;
gpio_instruct.func = GPIO_FUNC_4;
gpio_instruct.type = GPIO_TYPE_CMOS;
gpio_instruct.flt = GPIO_FILTER_DISABLE;
/* PB3->SPI0_SCK, PB5->SPI0_MOSI */
ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct);
/* PB4->SPI0_MISO */
gpio_instruct.mode = GPIO_MODE_INPUT;
ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct);
}
else if (SPIx == SPI1)
{
_spi1.perh = SPI1;
spi_bus = &_spi_bus1;
spi = &_spi1;
/* SPI1 gpio init */
gpio_instruct.mode = GPIO_MODE_OUTPUT;
gpio_instruct.odos = GPIO_PUSH_PULL;
gpio_instruct.func = GPIO_FUNC_4;
gpio_instruct.type = GPIO_TYPE_CMOS;
gpio_instruct.flt = GPIO_FILTER_DISABLE;
/* PB13->SPI1_SCK, PB15->SPI1_MOSI */
ald_gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct);
/* PB14->SPI1_MISO */
gpio_instruct.mode = GPIO_MODE_INPUT;
ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct);
}
else
{
return -1;
}
spi_bus->parent.user_data = spi;
return rt_spi_bus_register(spi_bus, name, &es32f0_spi_ops);
}
rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name)
{
@ -279,16 +241,100 @@ rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const c
return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
}
int rt_hw_spi_init(void)
{
int result = 0;
#ifdef BSP_USING_SPI0
result = es32f0_spi_register_bus(SPI0, "spi0");
static struct rt_spi_bus _spi_bus0;
static spi_handle_t _spi0;
#endif
#ifdef BSP_USING_SPI1
result = es32f0_spi_register_bus(SPI1, "spi1");
static struct rt_spi_bus _spi_bus1;
static spi_handle_t _spi1;
#endif
int rt_hw_spi_init(void)
{
int result = RT_EOK;
struct rt_spi_bus *spi_bus;
spi_handle_t *spi;
gpio_init_t gpio_instruct;
#ifdef BSP_USING_SPI0
_spi0.perh = SPI0;
spi_bus = &_spi_bus0;
spi = &_spi0;
rt_device_t spi_bus_dev0;
/* SPI0 gpio init */
gpio_instruct.mode = GPIO_MODE_OUTPUT;
gpio_instruct.odos = GPIO_PUSH_PULL;
gpio_instruct.func = GPIO_FUNC_4;
gpio_instruct.type = GPIO_TYPE_CMOS;
gpio_instruct.flt = GPIO_FILTER_DISABLE;
/* PB3->SPI0_SCK, PB5->SPI0_MOSI */
ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct);
/* PB4->SPI0_MISO */
gpio_instruct.mode = GPIO_MODE_INPUT;
ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct);
spi_bus->parent.user_data = spi;
result = rt_spi_bus_register(spi_bus, "spi0", &es32f0_spi_ops);
if (result != RT_EOK)
{
return result;
}
rt_device_register(spi_bus_dev0, "spi00", RT_DEVICE_FLAG_RDWR);
/* SPI0_NSS = PA15 = PIN 50 */
result = es32f0_spi_device_attach(50, "spi0", "spi00");
if (result != RT_EOK)
{
return result;
}
#endif
#ifdef BSP_USING_SPI1
_spi1.perh = SPI1;
spi_bus = &_spi_bus1;
spi = &_spi1;
rt_device_t spi_bus_dev0;
/* SPI1 gpio init */
gpio_instruct.mode = GPIO_MODE_OUTPUT;
gpio_instruct.odos = GPIO_PUSH_PULL;
gpio_instruct.func = GPIO_FUNC_4;
gpio_instruct.type = GPIO_TYPE_CMOS;
gpio_instruct.flt = GPIO_FILTER_DISABLE;
/* PB13->SPI1_SCK, PB15->SPI1_MOSI */
ald_gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct);
/* PB14->SPI1_MISO */
gpio_instruct.mode = GPIO_MODE_INPUT;
ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct);
spi_bus->parent.user_data = spi;
result = rt_spi_bus_register(spi_bus, "spi1", &es32f0_spi_ops);
if (result != RT_EOK)
{
return result;
}
rt_device_register(spi_bus_dev0, "spi10", RT_DEVICE_FLAG_RDWR);
/* SPI1_NSS = PC00 = PIN 8 */
result = es32f0_spi_device_attach(8, "spi1", "spi10");
if (result != RT_EOK)
{
return result;
}
#endif
return result;

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801
bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Include/es32f033x.h
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@ -284,21 +284,11 @@ typedef struct
#define BKPC_PCCR_RTCCS_POSE 1U
#define BKPC_PCCR_RTCCS_MSK BITS(BKPC_PCCR_RTCCS_POSS,BKPC_PCCR_RTCCS_POSE)
/****************** Bit definition for BKPC_PCR register ************************/
#define BKPC_PCR_BORS_POSS 1U
#define BKPC_PCR_BORS_POSE 4U
#define BKPC_PCR_BORS_MSK BITS(BKPC_PCR_BORS_POSS,BKPC_PCR_BORS_POSE)
#define BKPC_PCR_BOREN_POS 0U
#define BKPC_PCR_BOREN_MSK BIT(BKPC_PCR_BOREN_POS)
typedef struct
{
__IO uint32_t PROT;
__IO uint32_t CR;
__IO uint32_t PCCR;
__IO uint32_t PCR;
} BKPC_TypeDef;
/****************** Bit definition for PMU_CR register ************************/
@ -1847,18 +1837,18 @@ typedef struct
#define RTC_TAMPCON_TAMPTS_POS 16U
#define RTC_TAMPCON_TAMPTS_MSK BIT(RTC_TAMPCON_TAMPTS_POS)
#define RTC_TAMPCON_TAMP2LV_POS 9U
#define RTC_TAMPCON_TAMP2LV_MSK BIT(RTC_TAMPCON_TAMP2LV_POS)
#define RTC_TAMPCON_TAMP2EN_POS 8U
#define RTC_TAMPCON_TAMP2EN_MSK BIT(RTC_TAMPCON_TAMP2EN_POS)
#define RTC_TAMPCON_TAMP1LV_POS 1U
#define RTC_TAMPCON_TAMP1LV_POS 9U
#define RTC_TAMPCON_TAMP1LV_MSK BIT(RTC_TAMPCON_TAMP1LV_POS)
#define RTC_TAMPCON_TAMP1EN_POS 0U
#define RTC_TAMPCON_TAMP1EN_POS 8U
#define RTC_TAMPCON_TAMP1EN_MSK BIT(RTC_TAMPCON_TAMP1EN_POS)
#define RTC_TAMPCON_TAMP0LV_POS 1U
#define RTC_TAMPCON_TAMP0LV_MSK BIT(RTC_TAMPCON_TAMP0LV_POS)
#define RTC_TAMPCON_TAMP0EN_POS 0U
#define RTC_TAMPCON_TAMP0EN_MSK BIT(RTC_TAMPCON_TAMP0EN_POS)
/****************** Bit definition for RTC_TIME register ************************/
#define RTC_TIME_PM_POS 22U
@ -2151,12 +2141,12 @@ typedef struct
#define RTC_IER_RSC_POS 16U
#define RTC_IER_RSC_MSK BIT(RTC_IER_RSC_POS)
#define RTC_IER_TAMP2_POS 13U
#define RTC_IER_TAMP2_MSK BIT(RTC_IER_TAMP2_POS)
#define RTC_IER_TAMP1_POS 12U
#define RTC_IER_TAMP1_POS 13U
#define RTC_IER_TAMP1_MSK BIT(RTC_IER_TAMP1_POS)
#define RTC_IER_TAMP0_POS 12U
#define RTC_IER_TAMP0_MSK BIT(RTC_IER_TAMP0_POS)
#define RTC_IER_TSOV_POS 11U
#define RTC_IER_TSOV_MSK BIT(RTC_IER_TSOV_POS)
@ -2204,12 +2194,12 @@ typedef struct
#define RTC_IFR_RSCF_POS 16U
#define RTC_IFR_RSCF_MSK BIT(RTC_IFR_RSCF_POS)
#define RTC_IFR_TAMP2F_POS 13U
#define RTC_IFR_TAMP2F_MSK BIT(RTC_IFR_TAMP2F_POS)
#define RTC_IFR_TAMP1F_POS 12U
#define RTC_IFR_TAMP1F_POS 13U
#define RTC_IFR_TAMP1F_MSK BIT(RTC_IFR_TAMP1F_POS)
#define RTC_IFR_TAMP0F_POS 12U
#define RTC_IFR_TAMP0F_MSK BIT(RTC_IFR_TAMP0F_POS)
#define RTC_IFR_TSOVF_POS 11U
#define RTC_IFR_TSOVF_MSK BIT(RTC_IFR_TSOVF_POS)
@ -2257,17 +2247,17 @@ typedef struct
#define RTC_IFCR_RSCFC_POS 16U
#define RTC_IFCR_RSCFC_MSK BIT(RTC_IFCR_RSCFC_POS)
#define RTC_IFCR_TAMP2FC_POS 13U
#define RTC_IFCR_TAMP2FC_MSK BIT(RTC_IFCR_TAMP2FC_POS)
#define RTC_IFCR_TAMP1FC_POS 12U
#define RTC_IFCR_TAMP1FC_POS 13U
#define RTC_IFCR_TAMP1FC_MSK BIT(RTC_IFCR_TAMP1FC_POS)
#define RTC_IFCR_TAMP0FC_POS 12U
#define RTC_IFCR_TAMP0FC_MSK BIT(RTC_IFCR_TAMP0FC_POS)
#define RTC_IFCR_TSOVFC_POS 11U
#define RTC_IFCR_TSOVFC_MSK BIT(RTC_IFCR_TSOVFC_POS)
#define RTC_IFCR_TSSTC_POS 10U
#define RTC_IFCR_TSSTC_MSK BIT(RTC_IFCR_TSSTC_POS)
#define RTC_IFCR_TSFC_POS 10U
#define RTC_IFCR_TSFC_MSK BIT(RTC_IFCR_TSFC_POS)
#define RTC_IFCR_ALMBFC_POS 9U
#define RTC_IFCR_ALMBFC_MSK BIT(RTC_IFCR_ALMBFC_POS)
@ -2310,12 +2300,12 @@ typedef struct
#define RTC_ISR_RSCF_POS 16U
#define RTC_ISR_RSCF_MSK BIT(RTC_ISR_RSCF_POS)
#define RTC_ISR_TAMP2F_POS 13U
#define RTC_ISR_TAMP2F_MSK BIT(RTC_ISR_TAMP2F_POS)
#define RTC_ISR_TAMP1F_POS 12U
#define RTC_ISR_TAMP1F_POS 13U
#define RTC_ISR_TAMP1F_MSK BIT(RTC_ISR_TAMP1F_POS)
#define RTC_ISR_TAMP0F_POS 12U
#define RTC_ISR_TAMP0F_MSK BIT(RTC_ISR_TAMP0F_POS)
#define RTC_ISR_TSOVF_POS 11U
#define RTC_ISR_TSOVF_MSK BIT(RTC_ISR_TSOVF_POS)
@ -4361,736 +4351,6 @@ typedef struct
__IO uint32_t RT;
} I2C_TypeDef;
/****************** Bit definition for CAN_CON register ************************/
#define CAN_CON_DBGSTP_POS 16U
#define CAN_CON_DBGSTP_MSK BIT(CAN_CON_DBGSTP_POS)
#define CAN_CON_RST_POS 15U
#define CAN_CON_RST_MSK BIT(CAN_CON_RST_POS)
#define CAN_CON_TTCEN_POS 7U
#define CAN_CON_TTCEN_MSK BIT(CAN_CON_TTCEN_POS)
#define CAN_CON_ABOFFEN_POS 6U
#define CAN_CON_ABOFFEN_MSK BIT(CAN_CON_ABOFFEN_POS)
#define CAN_CON_AWKEN_POS 5U
#define CAN_CON_AWKEN_MSK BIT(CAN_CON_AWKEN_POS)
#define CAN_CON_ARTXDIS_POS 4U
#define CAN_CON_ARTXDIS_MSK BIT(CAN_CON_ARTXDIS_POS)
#define CAN_CON_RXFOPM_POS 3U
#define CAN_CON_RXFOPM_MSK BIT(CAN_CON_RXFOPM_POS)
#define CAN_CON_TXMP_POS 2U
#define CAN_CON_TXMP_MSK BIT(CAN_CON_TXMP_POS)
#define CAN_CON_SLPREQ_POS 1U
#define CAN_CON_SLPREQ_MSK BIT(CAN_CON_SLPREQ_POS)
#define CAN_CON_INIREQ_POS 0U
#define CAN_CON_INIREQ_MSK BIT(CAN_CON_INIREQ_POS)
/****************** Bit definition for CAN_STAT register ************************/
#define CAN_STAT_RX_POS 11U
#define CAN_STAT_RX_MSK BIT(CAN_STAT_RX_POS)
#define CAN_STAT_PRESMP_POS 10U
#define CAN_STAT_PRESMP_MSK BIT(CAN_STAT_PRESMP_POS)
#define CAN_STAT_RXSTAT_POS 9U
#define CAN_STAT_RXSTAT_MSK BIT(CAN_STAT_RXSTAT_POS)
#define CAN_STAT_TXSTAT_POS 8U
#define CAN_STAT_TXSTAT_MSK BIT(CAN_STAT_TXSTAT_POS)
#define CAN_STAT_SLPIF_POS 4U
#define CAN_STAT_SLPIF_MSK BIT(CAN_STAT_SLPIF_POS)
#define CAN_STAT_WKIF_POS 3U
#define CAN_STAT_WKIF_MSK BIT(CAN_STAT_WKIF_POS)
#define CAN_STAT_ERRIF_POS 2U
#define CAN_STAT_ERRIF_MSK BIT(CAN_STAT_ERRIF_POS)
#define CAN_STAT_SLPSTAT_POS 1U
#define CAN_STAT_SLPSTAT_MSK BIT(CAN_STAT_SLPSTAT_POS)
#define CAN_STAT_INISTAT_POS 0U
#define CAN_STAT_INISTAT_MSK BIT(CAN_STAT_INISTAT_POS)
/****************** Bit definition for CAN_IFC register ************************/
#define CAN_IFC_SLPIFC_POS 4U
#define CAN_IFC_SLPIFC_MSK BIT(CAN_IFC_SLPIFC_POS)
#define CAN_IFC_WKIFC_POS 3U
#define CAN_IFC_WKIFC_MSK BIT(CAN_IFC_WKIFC_POS)
#define CAN_IFC_ERRIFC_POS 2U
#define CAN_IFC_ERRIFC_MSK BIT(CAN_IFC_ERRIFC_POS)
/****************** Bit definition for CAN_TXSTAT register ************************/
#define CAN_TXSTAT_TXM2LPF_POS 31U
#define CAN_TXSTAT_TXM2LPF_MSK BIT(CAN_TXSTAT_TXM2LPF_POS)
#define CAN_TXSTAT_TXM1LPF_POS 30U
#define CAN_TXSTAT_TXM1LPF_MSK BIT(CAN_TXSTAT_TXM1LPF_POS)
#define CAN_TXSTAT_TXM0LPF_POS 29U
#define CAN_TXSTAT_TXM0LPF_MSK BIT(CAN_TXSTAT_TXM0LPF_POS)
#define CAN_TXSTAT_TXM2EF_POS 28U
#define CAN_TXSTAT_TXM2EF_MSK BIT(CAN_TXSTAT_TXM2EF_POS)
#define CAN_TXSTAT_TXM1EF_POS 27U
#define CAN_TXSTAT_TXM1EF_MSK BIT(CAN_TXSTAT_TXM1EF_POS)
#define CAN_TXSTAT_TXM0EF_POS 26U
#define CAN_TXSTAT_TXM0EF_MSK BIT(CAN_TXSTAT_TXM0EF_POS)
#define CAN_TXSTAT_CODE_POSS 24U
#define CAN_TXSTAT_CODE_POSE 25U
#define CAN_TXSTAT_CODE_MSK BITS(CAN_TXSTAT_CODE_POSS,CAN_TXSTAT_CODE_POSE)
#define CAN_TXSTAT_M2STPREQ_POS 23U
#define CAN_TXSTAT_M2STPREQ_MSK BIT(CAN_TXSTAT_M2STPREQ_POS)
#define CAN_TXSTAT_M2TXERR_POS 19U
#define CAN_TXSTAT_M2TXERR_MSK BIT(CAN_TXSTAT_M2TXERR_POS)
#define CAN_TXSTAT_M2ARBLST_POS 18U
#define CAN_TXSTAT_M2ARBLST_MSK BIT(CAN_TXSTAT_M2ARBLST_POS)
#define CAN_TXSTAT_M2TXC_POS 17U
#define CAN_TXSTAT_M2TXC_MSK BIT(CAN_TXSTAT_M2TXC_POS)
#define CAN_TXSTAT_M2REQC_POS 16U
#define CAN_TXSTAT_M2REQC_MSK BIT(CAN_TXSTAT_M2REQC_POS)
#define CAN_TXSTAT_M1STPREQ_POS 15U
#define CAN_TXSTAT_M1STPREQ_MSK BIT(CAN_TXSTAT_M1STPREQ_POS)
#define CAN_TXSTAT_M1TXERR_POS 11U
#define CAN_TXSTAT_M1TXERR_MSK BIT(CAN_TXSTAT_M1TXERR_POS)
#define CAN_TXSTAT_M1ARBLST_POS 10U
#define CAN_TXSTAT_M1ARBLST_MSK BIT(CAN_TXSTAT_M1ARBLST_POS)
#define CAN_TXSTAT_M1TXC_POS 9U
#define CAN_TXSTAT_M1TXC_MSK BIT(CAN_TXSTAT_M1TXC_POS)
#define CAN_TXSTAT_M1REQC_POS 8U
#define CAN_TXSTAT_M1REQC_MSK BIT(CAN_TXSTAT_M1REQC_POS)
#define CAN_TXSTAT_M0STPREQ_POS 7U
#define CAN_TXSTAT_M0STPREQ_MSK BIT(CAN_TXSTAT_M0STPREQ_POS)
#define CAN_TXSTAT_M0TXERR_POS 3U
#define CAN_TXSTAT_M0TXERR_MSK BIT(CAN_TXSTAT_M0TXERR_POS)
#define CAN_TXSTAT_M0ARBLST_POS 2U
#define CAN_TXSTAT_M0ARBLST_MSK BIT(CAN_TXSTAT_M0ARBLST_POS)
#define CAN_TXSTAT_M0TXC_POS 1U
#define CAN_TXSTAT_M0TXC_MSK BIT(CAN_TXSTAT_M0TXC_POS)
#define CAN_TXSTAT_M0REQC_POS 0U
#define CAN_TXSTAT_M0REQC_MSK BIT(CAN_TXSTAT_M0REQC_POS)
/****************** Bit definition for CAN_TXSTATC register ************************/
#define CAN_TXSTATC_M2TXERR_POS 19U
#define CAN_TXSTATC_M2TXERR_MSK BIT(CAN_TXSTATC_M2TXERR_POS)
#define CAN_TXSTATC_M2ARBLST_POS 18U
#define CAN_TXSTATC_M2ARBLST_MSK BIT(CAN_TXSTATC_M2ARBLST_POS)
#define CAN_TXSTATC_M2TXC_POS 17U
#define CAN_TXSTATC_M2TXC_MSK BIT(CAN_TXSTATC_M2TXC_POS)
#define CAN_TXSTATC_M2REQC_POS 16U
#define CAN_TXSTATC_M2REQC_MSK BIT(CAN_TXSTATC_M2REQC_POS)
#define CAN_TXSTATC_M1TXERR_POS 11U
#define CAN_TXSTATC_M1TXERR_MSK BIT(CAN_TXSTATC_M1TXERR_POS)
#define CAN_TXSTATC_M1ARBLST_POS 10U
#define CAN_TXSTATC_M1ARBLST_MSK BIT(CAN_TXSTATC_M1ARBLST_POS)
#define CAN_TXSTATC_M1TXC_POS 9U
#define CAN_TXSTATC_M1TXC_MSK BIT(CAN_TXSTATC_M1TXC_POS)
#define CAN_TXSTATC_M1REQC_POS 8U
#define CAN_TXSTATC_M1REQC_MSK BIT(CAN_TXSTATC_M1REQC_POS)
#define CAN_TXSTATC_M0TXERR_POS 3U
#define CAN_TXSTATC_M0TXERR_MSK BIT(CAN_TXSTATC_M0TXERR_POS)
#define CAN_TXSTATC_M0ARBLST_POS 2U
#define CAN_TXSTATC_M0ARBLST_MSK BIT(CAN_TXSTATC_M0ARBLST_POS)
#define CAN_TXSTATC_M0TXC_POS 1U
#define CAN_TXSTATC_M0TXC_MSK BIT(CAN_TXSTATC_M0TXC_POS)
#define CAN_TXSTATC_M0REQC_POS 0U
#define CAN_TXSTATC_M0REQC_MSK BIT(CAN_TXSTATC_M0REQC_POS)
/****************** Bit definition for CAN_RXF0 register ************************/
#define CAN_RXF0_FREE_POS 5U
#define CAN_RXF0_FREE_MSK BIT(CAN_RXF0_FREE_POS)
#define CAN_RXF0_OVR_POS 4U
#define CAN_RXF0_OVR_MSK BIT(CAN_RXF0_OVR_POS)
#define CAN_RXF0_FULL_POS 3U
#define CAN_RXF0_FULL_MSK BIT(CAN_RXF0_FULL_POS)
#define CAN_RXF0_PEND_POSS 0U
#define CAN_RXF0_PEND_POSE 1U
#define CAN_RXF0_PEND_MSK BITS(CAN_RXF0_PEND_POSS,CAN_RXF0_PEND_POSE)
/****************** Bit definition for CAN_RXF0C register ************************/
#define CAN_RXF0C_OVRC_POS 4U
#define CAN_RXF0C_OVRC_MSK BIT(CAN_RXF0C_OVRC_POS)
#define CAN_RXF0C_FULLC_POS 3U
#define CAN_RXF0C_FULLC_MSK BIT(CAN_RXF0C_FULLC_POS)
/****************** Bit definition for CAN_RXF1 register ************************/
#define CAN_RXF1_FREE_POS 5U
#define CAN_RXF1_FREE_MSK BIT(CAN_RXF1_FREE_POS)
#define CAN_RXF1_OVR_POS 4U
#define CAN_RXF1_OVR_MSK BIT(CAN_RXF1_OVR_POS)
#define CAN_RXF1_FULL_POS 3U
#define CAN_RXF1_FULL_MSK BIT(CAN_RXF1_FULL_POS)
#define CAN_RXF1_PEND_POSS 0U
#define CAN_RXF1_PEND_POSE 1U
#define CAN_RXF1_PEND_MSK BITS(CAN_RXF1_PEND_POSS,CAN_RXF1_PEND_POSE)
/****************** Bit definition for CAN_RXF1C register ************************/
#define CAN_RXF1C_OVRC_POS 4U
#define CAN_RXF1C_OVRC_MSK BIT(CAN_RXF1C_OVRC_POS)
#define CAN_RXF1C_FULLC_POS 3U
#define CAN_RXF1C_FULLC_MSK BIT(CAN_RXF1C_FULLC_POS)
/****************** Bit definition for CAN_IE register ************************/
#define CAN_IE_SLPIE_POS 17U
#define CAN_IE_SLPIE_MSK BIT(CAN_IE_SLPIE_POS)
#define CAN_IE_WKIE_POS 16U
#define CAN_IE_WKIE_MSK BIT(CAN_IE_WKIE_POS)
#define CAN_IE_ERRIE_POS 15U
#define CAN_IE_ERRIE_MSK BIT(CAN_IE_ERRIE_POS)
#define CAN_IE_PRERRIE_POS 11U
#define CAN_IE_PRERRIE_MSK BIT(CAN_IE_PRERRIE_POS)
#define CAN_IE_BOFFIE_POS 10U
#define CAN_IE_BOFFIE_MSK BIT(CAN_IE_BOFFIE_POS)
#define CAN_IE_PERRIE_POS 9U
#define CAN_IE_PERRIE_MSK BIT(CAN_IE_PERRIE_POS)
#define CAN_IE_WARNIE_POS 8U
#define CAN_IE_WARNIE_MSK BIT(CAN_IE_WARNIE_POS)
#define CAN_IE_F1OVRIE_POS 6U
#define CAN_IE_F1OVRIE_MSK BIT(CAN_IE_F1OVRIE_POS)
#define CAN_IE_F1FULIE_POS 5U
#define CAN_IE_F1FULIE_MSK BIT(CAN_IE_F1FULIE_POS)
#define CAN_IE_F1PIE_POS 4U
#define CAN_IE_F1PIE_MSK BIT(CAN_IE_F1PIE_POS)
#define CAN_IE_F0OVRIE_POS 3U
#define CAN_IE_F0OVRIE_MSK BIT(CAN_IE_F0OVRIE_POS)
#define CAN_IE_F0FULIE_POS 2U
#define CAN_IE_F0FULIE_MSK BIT(CAN_IE_F0FULIE_POS)
#define CAN_IE_F0PIE_POS 1U
#define CAN_IE_F0PIE_MSK BIT(CAN_IE_F0PIE_POS)
#define CAN_IE_TXMEIE_POS 0U
#define CAN_IE_TXMEIE_MSK BIT(CAN_IE_TXMEIE_POS)
/****************** Bit definition for CAN_ERRSTAT register ************************/
#define CAN_ERRSTAT_RXERRC_POSS 24U
#define CAN_ERRSTAT_RXERRC_POSE 31U
#define CAN_ERRSTAT_RXERRC_MSK BITS(CAN_ERRSTAT_RXERRC_POSS,CAN_ERRSTAT_RXERRC_POSE)
#define CAN_ERRSTAT_TXERRC_POSS 16U
#define CAN_ERRSTAT_TXERRC_POSE 23U
#define CAN_ERRSTAT_TXERRC_MSK BITS(CAN_ERRSTAT_TXERRC_POSS,CAN_ERRSTAT_TXERRC_POSE)
#define CAN_ERRSTAT_PRERRF_POSS 4U
#define CAN_ERRSTAT_PRERRF_POSE 6U
#define CAN_ERRSTAT_PRERRF_MSK BITS(CAN_ERRSTAT_PRERRF_POSS,CAN_ERRSTAT_PRERRF_POSE)
#define CAN_ERRSTAT_BOFF_POS 2U
#define CAN_ERRSTAT_BOFF_MSK BIT(CAN_ERRSTAT_BOFF_POS)
#define CAN_ERRSTAT_PERRF_POS 1U
#define CAN_ERRSTAT_PERRF_MSK BIT(CAN_ERRSTAT_PERRF_POS)
#define CAN_ERRSTAT_WARNF_POS 0U
#define CAN_ERRSTAT_WARNF_MSK BIT(CAN_ERRSTAT_WARNF_POS)
/****************** Bit definition for CAN_BTIME register ************************/
#define CAN_BTIME_SILENT_POS 31U
#define CAN_BTIME_SILENT_MSK BIT(CAN_BTIME_SILENT_POS)
#define CAN_BTIME_LOOP_POS 30U
#define CAN_BTIME_LOOP_MSK BIT(CAN_BTIME_LOOP_POS)
#define CAN_BTIME_RESJW_POSS 24U
#define CAN_BTIME_RESJW_POSE 25U
#define CAN_BTIME_RESJW_MSK BITS(CAN_BTIME_RESJW_POSS,CAN_BTIME_RESJW_POSE)
#define CAN_BTIME_SEG2_POSS 20U
#define CAN_BTIME_SEG2_POSE 22U
#define CAN_BTIME_SEG2_MSK BITS(CAN_BTIME_SEG2_POSS,CAN_BTIME_SEG2_POSE)
#define CAN_BTIME_SEG1_POSS 16U
#define CAN_BTIME_SEG1_POSE 19U
#define CAN_BTIME_SEG1_MSK BITS(CAN_BTIME_SEG1_POSS,CAN_BTIME_SEG1_POSE)
#define CAN_BTIME_BPSC_POSS 0U
#define CAN_BTIME_BPSC_POSE 9U
#define CAN_BTIME_BPSC_MSK BITS(CAN_BTIME_BPSC_POSS,CAN_BTIME_BPSC_POSE)
/****************** Bit definition for CAN_TXID0 register ************************/
#define CAN_TXID0_STDID_POSS 21U
#define CAN_TXID0_STDID_POSE 31U
#define CAN_TXID0_STDID_MSK BITS(CAN_TXID0_STDID_POSS,CAN_TXID0_STDID_POSE)
#define CAN_TXID0_EXID_POSS 3U
#define CAN_TXID0_EXID_POSE 20U
#define CAN_TXID0_EXID_MSK BITS(CAN_TXID0_EXID_POSS,CAN_TXID0_EXID_POSE)
#define CAN_TXID0_IDE_POS 2U
#define CAN_TXID0_IDE_MSK BIT(CAN_TXID0_IDE_POS)
#define CAN_TXID0_RTR_POS 1U
#define CAN_TXID0_RTR_MSK BIT(CAN_TXID0_RTR_POS)
#define CAN_TXID0_TXMREQ_POS 0U
#define CAN_TXID0_TXMREQ_MSK BIT(CAN_TXID0_TXMREQ_POS)
/****************** Bit definition for CAN_TXFCON0 register ************************/
#define CAN_TXFCON0_STAMP_POSS 16U
#define CAN_TXFCON0_STAMP_POSE 31U
#define CAN_TXFCON0_STAMP_MSK BITS(CAN_TXFCON0_STAMP_POSS,CAN_TXFCON0_STAMP_POSE)
#define CAN_TXFCON0_TXGT_POS 8U
#define CAN_TXFCON0_TXGT_MSK BIT(CAN_TXFCON0_TXGT_POS)
#define CAN_TXFCON0_DLEN_POSS 0U
#define CAN_TXFCON0_DLEN_POSE 3U
#define CAN_TXFCON0_DLEN_MSK BITS(CAN_TXFCON0_DLEN_POSS,CAN_TXFCON0_DLEN_POSE)
/****************** Bit definition for CAN_TXDL0 register ************************/
#define CAN_TXDL0_BYTE3_POSS 24U
#define CAN_TXDL0_BYTE3_POSE 31U
#define CAN_TXDL0_BYTE3_MSK BITS(CAN_TXDL0_BYTE3_POSS,CAN_TXDL0_BYTE3_POSE)
#define CAN_TXDL0_BYTE2_POSS 16U
#define CAN_TXDL0_BYTE2_POSE 23U
#define CAN_TXDL0_BYTE2_MSK BITS(CAN_TXDL0_BYTE2_POSS,CAN_TXDL0_BYTE2_POSE)
#define CAN_TXDL0_BYTE1_POSS 8U
#define CAN_TXDL0_BYTE1_POSE 15U
#define CAN_TXDL0_BYTE1_MSK BITS(CAN_TXDL0_BYTE1_POSS,CAN_TXDL0_BYTE1_POSE)
#define CAN_TXDL0_BYTE0_POSS 0U
#define CAN_TXDL0_BYTE0_POSE 7U
#define CAN_TXDL0_BYTE0_MSK BITS(CAN_TXDL0_BYTE0_POSS,CAN_TXDL0_BYTE0_POSE)
/****************** Bit definition for CAN_TXDH0 register ************************/
#define CAN_TXDH0_BYTE7_POSS 24U
#define CAN_TXDH0_BYTE7_POSE 31U
#define CAN_TXDH0_BYTE7_MSK BITS(CAN_TXDH0_BYTE7_POSS,CAN_TXDH0_BYTE7_POSE)
#define CAN_TXDH0_BYTE6_POSS 16U
#define CAN_TXDH0_BYTE6_POSE 23U
#define CAN_TXDH0_BYTE6_MSK BITS(CAN_TXDH0_BYTE6_POSS,CAN_TXDH0_BYTE6_POSE)
#define CAN_TXDH0_BYTE5_POSS 8U
#define CAN_TXDH0_BYTE5_POSE 15U
#define CAN_TXDH0_BYTE5_MSK BITS(CAN_TXDH0_BYTE5_POSS,CAN_TXDH0_BYTE5_POSE)
#define CAN_TXDH0_BYTE4_POSS 0U
#define CAN_TXDH0_BYTE4_POSE 7U
#define CAN_TXDH0_BYTE4_MSK BITS(CAN_TXDH0_BYTE4_POSS,CAN_TXDH0_BYTE4_POSE)
/****************** Bit definition for CAN_TXID1 register ************************/
#define CAN_TXID1_STDID_POSS 21U
#define CAN_TXID1_STDID_POSE 31U
#define CAN_TXID1_STDID_MSK BITS(CAN_TXID1_STDID_POSS,CAN_TXID1_STDID_POSE)
#define CAN_TXID1_EXID_POSS 3U
#define CAN_TXID1_EXID_POSE 20U
#define CAN_TXID1_EXID_MSK BITS(CAN_TXID1_EXID_POSS,CAN_TXID1_EXID_POSE)
#define CAN_TXID1_IDE_POS 2U
#define CAN_TXID1_IDE_MSK BIT(CAN_TXID1_IDE_POS)
#define CAN_TXID1_RTR_POS 1U
#define CAN_TXID1_RTR_MSK BIT(CAN_TXID1_RTR_POS)
#define CAN_TXID1_TXMREQ_POS 0U
#define CAN_TXID1_TXMREQ_MSK BIT(CAN_TXID1_TXMREQ_POS)
/****************** Bit definition for CAN_TXFCON1 register ************************/
#define CAN_TXFCON1_STAMP_POSS 16U
#define CAN_TXFCON1_STAMP_POSE 31U
#define CAN_TXFCON1_STAMP_MSK BITS(CAN_TXFCON1_STAMP_POSS,CAN_TXFCON1_STAMP_POSE)
#define CAN_TXFCON1_TXGT_POS 8U
#define CAN_TXFCON1_TXGT_MSK BIT(CAN_TXFCON1_TXGT_POS)
#define CAN_TXFCON1_DLEN_POSS 0U
#define CAN_TXFCON1_DLEN_POSE 3U
#define CAN_TXFCON1_DLEN_MSK BITS(CAN_TXFCON1_DLEN_POSS,CAN_TXFCON1_DLEN_POSE)
/****************** Bit definition for CAN_TXDL1 register ************************/
#define CAN_TXDL1_BYTE3_POSS 24U
#define CAN_TXDL1_BYTE3_POSE 31U
#define CAN_TXDL1_BYTE3_MSK BITS(CAN_TXDL1_BYTE3_POSS,CAN_TXDL1_BYTE3_POSE)
#define CAN_TXDL1_BYTE2_POSS 16U
#define CAN_TXDL1_BYTE2_POSE 23U
#define CAN_TXDL1_BYTE2_MSK BITS(CAN_TXDL1_BYTE2_POSS,CAN_TXDL1_BYTE2_POSE)
#define CAN_TXDL1_BYTE1_POSS 8U
#define CAN_TXDL1_BYTE1_POSE 15U
#define CAN_TXDL1_BYTE1_MSK BITS(CAN_TXDL1_BYTE1_POSS,CAN_TXDL1_BYTE1_POSE)
#define CAN_TXDL1_BYTE0_POSS 0U
#define CAN_TXDL1_BYTE0_POSE 7U
#define CAN_TXDL1_BYTE0_MSK BITS(CAN_TXDL1_BYTE0_POSS,CAN_TXDL1_BYTE0_POSE)
/****************** Bit definition for CAN_TXDH1 register ************************/
#define CAN_TXDH1_BYTE7_POSS 24U
#define CAN_TXDH1_BYTE7_POSE 31U
#define CAN_TXDH1_BYTE7_MSK BITS(CAN_TXDH1_BYTE7_POSS,CAN_TXDH1_BYTE7_POSE)
#define CAN_TXDH1_BYTE6_POSS 16U
#define CAN_TXDH1_BYTE6_POSE 23U
#define CAN_TXDH1_BYTE6_MSK BITS(CAN_TXDH1_BYTE6_POSS,CAN_TXDH1_BYTE6_POSE)
#define CAN_TXDH1_BYTE5_POSS 8U
#define CAN_TXDH1_BYTE5_POSE 15U
#define CAN_TXDH1_BYTE5_MSK BITS(CAN_TXDH1_BYTE5_POSS,CAN_TXDH1_BYTE5_POSE)
#define CAN_TXDH1_BYTE4_POSS 0U
#define CAN_TXDH1_BYTE4_POSE 7U
#define CAN_TXDH1_BYTE4_MSK BITS(CAN_TXDH1_BYTE4_POSS,CAN_TXDH1_BYTE4_POSE)
/****************** Bit definition for CAN_TXID2 register ************************/
#define CAN_TXID2_STDID_POSS 21U
#define CAN_TXID2_STDID_POSE 31U
#define CAN_TXID2_STDID_MSK BITS(CAN_TXID2_STDID_POSS,CAN_TXID2_STDID_POSE)
#define CAN_TXID2_EXID_POSS 3U
#define CAN_TXID2_EXID_POSE 20U
#define CAN_TXID2_EXID_MSK BITS(CAN_TXID2_EXID_POSS,CAN_TXID2_EXID_POSE)
#define CAN_TXID2_IDE_POS 2U
#define CAN_TXID2_IDE_MSK BIT(CAN_TXID2_IDE_POS)
#define CAN_TXID2_RTR_POS 1U
#define CAN_TXID2_RTR_MSK BIT(CAN_TXID2_RTR_POS)
#define CAN_TXID2_TXMREQ_POS 0U
#define CAN_TXID2_TXMREQ_MSK BIT(CAN_TXID2_TXMREQ_POS)
/****************** Bit definition for CAN_TXFCON2 register ************************/
#define CAN_TXFCON2_STAMP_POSS 16U
#define CAN_TXFCON2_STAMP_POSE 31U
#define CAN_TXFCON2_STAMP_MSK BITS(CAN_TXFCON2_STAMP_POSS,CAN_TXFCON2_STAMP_POSE)
#define CAN_TXFCON2_TXGT_POS 8U
#define CAN_TXFCON2_TXGT_MSK BIT(CAN_TXFCON2_TXGT_POS)
#define CAN_TXFCON2_DLEN_POSS 0U
#define CAN_TXFCON2_DLEN_POSE 3U
#define CAN_TXFCON2_DLEN_MSK BITS(CAN_TXFCON2_DLEN_POSS,CAN_TXFCON2_DLEN_POSE)
/****************** Bit definition for CAN_TXDL2 register ************************/
#define CAN_TXDL2_BYTE3_POSS 24U
#define CAN_TXDL2_BYTE3_POSE 31U
#define CAN_TXDL2_BYTE3_MSK BITS(CAN_TXDL2_BYTE3_POSS,CAN_TXDL2_BYTE3_POSE)
#define CAN_TXDL2_BYTE2_POSS 16U
#define CAN_TXDL2_BYTE2_POSE 23U
#define CAN_TXDL2_BYTE2_MSK BITS(CAN_TXDL2_BYTE2_POSS,CAN_TXDL2_BYTE2_POSE)
#define CAN_TXDL2_BYTE1_POSS 8U
#define CAN_TXDL2_BYTE1_POSE 15U
#define CAN_TXDL2_BYTE1_MSK BITS(CAN_TXDL2_BYTE1_POSS,CAN_TXDL2_BYTE1_POSE)
#define CAN_TXDL2_BYTE0_POSS 0U
#define CAN_TXDL2_BYTE0_POSE 7U
#define CAN_TXDL2_BYTE0_MSK BITS(CAN_TXDL2_BYTE0_POSS,CAN_TXDL2_BYTE0_POSE)
/****************** Bit definition for CAN_TXDH2 register ************************/
#define CAN_TXDH2_BYTE7_POSS 24U
#define CAN_TXDH2_BYTE7_POSE 31U
#define CAN_TXDH2_BYTE7_MSK BITS(CAN_TXDH2_BYTE7_POSS,CAN_TXDH2_BYTE7_POSE)
#define CAN_TXDH2_BYTE6_POSS 16U
#define CAN_TXDH2_BYTE6_POSE 23U
#define CAN_TXDH2_BYTE6_MSK BITS(CAN_TXDH2_BYTE6_POSS,CAN_TXDH2_BYTE6_POSE)
#define CAN_TXDH2_BYTE5_POSS 8U
#define CAN_TXDH2_BYTE5_POSE 15U
#define CAN_TXDH2_BYTE5_MSK BITS(CAN_TXDH2_BYTE5_POSS,CAN_TXDH2_BYTE5_POSE)
#define CAN_TXDH2_BYTE4_POSS 0U
#define CAN_TXDH2_BYTE4_POSE 7U
#define CAN_TXDH2_BYTE4_MSK BITS(CAN_TXDH2_BYTE4_POSS,CAN_TXDH2_BYTE4_POSE)
/****************** Bit definition for CAN_RXF0ID register ************************/
#define CAN_RXF0ID_STDID_POSS 21U
#define CAN_RXF0ID_STDID_POSE 31U
#define CAN_RXF0ID_STDID_MSK BITS(CAN_RXF0ID_STDID_POSS,CAN_RXF0ID_STDID_POSE)
#define CAN_RXF0ID_EXID_POSS 3U
#define CAN_RXF0ID_EXID_POSE 20U
#define CAN_RXF0ID_EXID_MSK BITS(CAN_RXF0ID_EXID_POSS,CAN_RXF0ID_EXID_POSE)
#define CAN_RXF0ID_IDE_POS 2U
#define CAN_RXF0ID_IDE_MSK BIT(CAN_RXF0ID_IDE_POS)
#define CAN_RXF0ID_RTR_POS 1U
#define CAN_RXF0ID_RTR_MSK BIT(CAN_RXF0ID_RTR_POS)
/****************** Bit definition for CAN_RXF0INF register ************************/
#define CAN_RXF0INF_STAMP_POSS 16U
#define CAN_RXF0INF_STAMP_POSE 31U
#define CAN_RXF0INF_STAMP_MSK BITS(CAN_RXF0INF_STAMP_POSS,CAN_RXF0INF_STAMP_POSE)
#define CAN_RXF0INF_FLTIDX_POSS 8U
#define CAN_RXF0INF_FLTIDX_POSE 15U
#define CAN_RXF0INF_FLTIDX_MSK BITS(CAN_RXF0INF_FLTIDX_POSS,CAN_RXF0INF_FLTIDX_POSE)
#define CAN_RXF0INF_DLEN_POSS 0U
#define CAN_RXF0INF_DLEN_POSE 3U
#define CAN_RXF0INF_DLEN_MSK BITS(CAN_RXF0INF_DLEN_POSS,CAN_RXF0INF_DLEN_POSE)
/****************** Bit definition for CAN_RXF0DL register ************************/
#define CAN_RXF0DL_BYTE3_POSS 24U
#define CAN_RXF0DL_BYTE3_POSE 31U
#define CAN_RXF0DL_BYTE3_MSK BITS(CAN_RXF0DL_BYTE3_POSS,CAN_RXF0DL_BYTE3_POSE)
#define CAN_RXF0DL_BYTE2_POSS 16U
#define CAN_RXF0DL_BYTE2_POSE 23U
#define CAN_RXF0DL_BYTE2_MSK BITS(CAN_RXF0DL_BYTE2_POSS,CAN_RXF0DL_BYTE2_POSE)
#define CAN_RXF0DL_BYTE1_POSS 8U
#define CAN_RXF0DL_BYTE1_POSE 15U
#define CAN_RXF0DL_BYTE1_MSK BITS(CAN_RXF0DL_BYTE1_POSS,CAN_RXF0DL_BYTE1_POSE)
#define CAN_RXF0DL_BYTE0_POSS 0U
#define CAN_RXF0DL_BYTE0_POSE 7U
#define CAN_RXF0DL_BYTE0_MSK BITS(CAN_RXF0DL_BYTE0_POSS,CAN_RXF0DL_BYTE0_POSE)
/****************** Bit definition for CAN_RXF0DH register ************************/
#define CAN_RXF0DH_BYTE7_POSS 24U
#define CAN_RXF0DH_BYTE7_POSE 31U
#define CAN_RXF0DH_BYTE7_MSK BITS(CAN_RXF0DH_BYTE7_POSS,CAN_RXF0DH_BYTE7_POSE)
#define CAN_RXF0DH_BYTE6_POSS 16U
#define CAN_RXF0DH_BYTE6_POSE 23U
#define CAN_RXF0DH_BYTE6_MSK BITS(CAN_RXF0DH_BYTE6_POSS,CAN_RXF0DH_BYTE6_POSE)
#define CAN_RXF0DH_BYTE5_POSS 8U
#define CAN_RXF0DH_BYTE5_POSE 15U
#define CAN_RXF0DH_BYTE5_MSK BITS(CAN_RXF0DH_BYTE5_POSS,CAN_RXF0DH_BYTE5_POSE)
#define CAN_RXF0DH_BYTE4_POSS 0U
#define CAN_RXF0DH_BYTE4_POSE 7U
#define CAN_RXF0DH_BYTE4_MSK BITS(CAN_RXF0DH_BYTE4_POSS,CAN_RXF0DH_BYTE4_POSE)
/****************** Bit definition for CAN_RXF1ID register ************************/
#define CAN_RXF1ID_STDID_POSS 21U
#define CAN_RXF1ID_STDID_POSE 31U
#define CAN_RXF1ID_STDID_MSK BITS(CAN_RXF1ID_STDID_POSS,CAN_RXF1ID_STDID_POSE)
#define CAN_RXF1ID_EXID_POSS 3U
#define CAN_RXF1ID_EXID_POSE 20U
#define CAN_RXF1ID_EXID_MSK BITS(CAN_RXF1ID_EXID_POSS,CAN_RXF1ID_EXID_POSE)
#define CAN_RXF1ID_IDE_POS 2U
#define CAN_RXF1ID_IDE_MSK BIT(CAN_RXF1ID_IDE_POS)
#define CAN_RXF1ID_RTR_POS 1U
#define CAN_RXF1ID_RTR_MSK BIT(CAN_RXF1ID_RTR_POS)
/****************** Bit definition for CAN_RXF1INF register ************************/
#define CAN_RXF1INF_STAMP_POSS 16U
#define CAN_RXF1INF_STAMP_POSE 31U
#define CAN_RXF1INF_STAMP_MSK BITS(CAN_RXF1INF_STAMP_POSS,CAN_RXF1INF_STAMP_POSE)
#define CAN_RXF1INF_FLTIDX_POSS 8U
#define CAN_RXF1INF_FLTIDX_POSE 15U
#define CAN_RXF1INF_FLTIDX_MSK BITS(CAN_RXF1INF_FLTIDX_POSS,CAN_RXF1INF_FLTIDX_POSE)
#define CAN_RXF1INF_DLEN_POSS 0U
#define CAN_RXF1INF_DLEN_POSE 3U
#define CAN_RXF1INF_DLEN_MSK BITS(CAN_RXF1INF_DLEN_POSS,CAN_RXF1INF_DLEN_POSE)
/****************** Bit definition for CAN_RXF1DL register ************************/
#define CAN_RXF1DL_BYTE3_POSS 24U
#define CAN_RXF1DL_BYTE3_POSE 31U
#define CAN_RXF1DL_BYTE3_MSK BITS(CAN_RXF1DL_BYTE3_POSS,CAN_RXF1DL_BYTE3_POSE)
#define CAN_RXF1DL_BYTE2_POSS 16U
#define CAN_RXF1DL_BYTE2_POSE 23U
#define CAN_RXF1DL_BYTE2_MSK BITS(CAN_RXF1DL_BYTE2_POSS,CAN_RXF1DL_BYTE2_POSE)
#define CAN_RXF1DL_BYTE1_POSS 8U
#define CAN_RXF1DL_BYTE1_POSE 15U
#define CAN_RXF1DL_BYTE1_MSK BITS(CAN_RXF1DL_BYTE1_POSS,CAN_RXF1DL_BYTE1_POSE)
#define CAN_RXF1DL_BYTE0_POSS 0U
#define CAN_RXF1DL_BYTE0_POSE 7U
#define CAN_RXF1DL_BYTE0_MSK BITS(CAN_RXF1DL_BYTE0_POSS,CAN_RXF1DL_BYTE0_POSE)
/****************** Bit definition for CAN_RXF1DH register ************************/
#define CAN_RXF1DH_BYTE7_POSS 24U
#define CAN_RXF1DH_BYTE7_POSE 31U
#define CAN_RXF1DH_BYTE7_MSK BITS(CAN_RXF1DH_BYTE7_POSS,CAN_RXF1DH_BYTE7_POSE)
#define CAN_RXF1DH_BYTE6_POSS 16U
#define CAN_RXF1DH_BYTE6_POSE 23U
#define CAN_RXF1DH_BYTE6_MSK BITS(CAN_RXF1DH_BYTE6_POSS,CAN_RXF1DH_BYTE6_POSE)
#define CAN_RXF1DH_BYTE5_POSS 8U
#define CAN_RXF1DH_BYTE5_POSE 15U
#define CAN_RXF1DH_BYTE5_MSK BITS(CAN_RXF1DH_BYTE5_POSS,CAN_RXF1DH_BYTE5_POSE)
#define CAN_RXF1DH_BYTE4_POSS 0U
#define CAN_RXF1DH_BYTE4_POSE 7U
#define CAN_RXF1DH_BYTE4_MSK BITS(CAN_RXF1DH_BYTE4_POSS,CAN_RXF1DH_BYTE4_POSE)
/****************** Bit definition for CAN_FLTCON register ************************/
#define CAN_FLTCON_FLTINI_POS 0U
#define CAN_FLTCON_FLTINI_MSK BIT(CAN_FLTCON_FLTINI_POS)
/****************** Bit definition for CAN_FLTM register ************************/
#define CAN_FLTM_MOD_POSS 0U
#define CAN_FLTM_MOD_POSE 13U
#define CAN_FLTM_MOD_MSK BITS(CAN_FLTM_MOD_POSS,CAN_FLTM_MOD_POSE)
/****************** Bit definition for CAN_FLTWS register ************************/
#define CAN_FLTWS_SEL_POSS 0U
#define CAN_FLTWS_SEL_POSE 13U
#define CAN_FLTWS_SEL_MSK BITS(CAN_FLTWS_SEL_POSS,CAN_FLTWS_SEL_POSE)
/****************** Bit definition for CAN_FLTAS register ************************/
#define CAN_FLTAS_ASSIGN_POSS 0U
#define CAN_FLTAS_ASSIGN_POSE 13U
#define CAN_FLTAS_ASSIGN_MSK BITS(CAN_FLTAS_ASSIGN_POSS,CAN_FLTAS_ASSIGN_POSE)
/****************** Bit definition for CAN_FLTGO register ************************/
#define CAN_FLTGO_GO_POSS 0U
#define CAN_FLTGO_GO_POSE 13U
#define CAN_FLTGO_GO_MSK BITS(CAN_FLTGO_GO_POSS,CAN_FLTGO_GO_POSE)
typedef struct {
__IO uint32_t TXID;
__IO uint32_t TXFCON;
__IO uint32_t TXDL;
__IO uint32_t TXDH;
} CAN_TxMailBox_Typedef;
typedef struct {
__IO uint32_t RXFID;
__IO uint32_t RXFINF;
__IO uint32_t RXFDL;
__IO uint32_t RXFDH;
} CAN_RxFIFO_Typedef;
typedef struct {
__IO uint32_t FLT1;
__IO uint32_t FLT2;
} CAN_Filter_Typedef;
typedef struct
{
__IO uint32_t CON;
__I uint32_t STAT;
__O uint32_t IFC;
__IO uint32_t TXSTAT;
__O uint32_t TXSTATC;
__IO uint32_t RXF0;
__O uint32_t RXF0C;
__IO uint32_t RXF1;
__O uint32_t RXF1C;
__IO uint32_t IE;
__IO uint32_t ERRSTAT;
__IO uint32_t BTIME;
uint32_t RESERVED0[84] ;
CAN_TxMailBox_Typedef TxMailBox[3];
CAN_RxFIFO_Typedef RxFIFO[2];
uint32_t RESERVED1[12] ;
__IO uint32_t FLTCON;
__IO uint32_t FLTM;
uint32_t RESERVED2 ;
__IO uint32_t FLTWS;
uint32_t RESERVED3 ;
__IO uint32_t FLTAS;
uint32_t RESERVED4 ;
__IO uint32_t FLTGO;
uint32_t RESERVED5[8] ;
CAN_Filter_Typedef Filter[14];
} CAN_TypeDef;
/****************** Bit definition for CRC_CR register ************************/
#define CRC_CR_BYTORD_POS 24U
#define CRC_CR_BYTORD_MSK BIT(CRC_CR_BYTORD_POS)
@ -6523,20 +5783,16 @@ typedef struct
#define USART1_BASE (APB1_BASE + 0x5400)
#define SPI0_BASE (APB1_BASE + 0x6000)
#define SPI1_BASE (APB1_BASE + 0x6400)
#define SPI2_BASE (APB1_BASE + 0x6800)
#define I2C0_BASE (APB1_BASE + 0x8000)
#define I2C1_BASE (APB1_BASE + 0x8400)
#define CAN0_BASE (APB1_BASE + 0xB000)
#define DMA0_BASE (APB1_BASE + 0xC000)
/* APB2 peripherals Base Address */
#define LPTIM0_BASE (APB2_BASE + 0x0000)
#define LPUART0_BASE (APB2_BASE + 0x1000)
#define ADC0_BASE (APB2_BASE + 0x2000)
#define ADC1_BASE (APB2_BASE + 0x2400)
#define ACMP0_BASE (APB2_BASE + 0x3000)
#define ACMP1_BASE (APB2_BASE + 0x3400)
#define OPAMP_BASE (APB2_BASE + 0x4000)
#define DAC0_BASE (APB2_BASE + 0x5000)
#define WWDT_BASE (APB2_BASE + 0x6000)
#define IWDT_BASE (APB2_BASE + 0x6400)
@ -6584,21 +5840,16 @@ typedef struct
#define USART1 ((USART_TypeDef *)USART1_BASE)
#define SPI0 ((SPI_TypeDef *)SPI0_BASE)
#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
#define I2C0 ((I2C_TypeDef *)I2C0_BASE)
#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
#define CAN0 ((CAN_TypeDef *)CAN0_BASE)
#define DMA0 ((DMA_TypeDef *)DMA0_BASE)
/* APB2 peripherals */
#define LPTIM0 ((LPTIM_TypeDef *)LPTIM0_BASE)
#define LPUART0 ((LPUART_TypeDef *)LPUART0_BASE)
#define ADC0 ((ADC_TypeDef *)ADC0_BASE)
#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE)
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE)
#define OPAMP ((OPAMP_TypeDef *)OPAMP_BASE)
#define DAC0 ((DAC_TypeDef *)DAC0_BASE)
#define WWDT ((WWDT_TypeDef *)WWDT_BASE)
#define IWDT ((IWDT_TypeDef *)IWDT_BASE)
#define LCD ((LCD_TypeDef *)LCD_BASE)

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bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/EASTSOFT_ES32F033x_ALD.chm Normal file
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bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_acmp.h
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@ -18,7 +18,7 @@
#define __ALD_ACMP_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@ -38,8 +38,7 @@ extern "C" {
/**
* @brief Acmp interrupt
*/
typedef enum
{
typedef enum {
ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */
ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */
} acmp_it_t;
@ -47,8 +46,7 @@ typedef enum
/**
* @brief Acmp interrupt
*/
typedef enum
{
typedef enum {
ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */
ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */
} acmp_flag_t;
@ -56,8 +54,7 @@ typedef enum
/**
* @brief Acmp interrupt flag
*/
typedef enum
{
typedef enum {
ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */
ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */
} acmp_status_t;
@ -65,129 +62,118 @@ typedef enum
/**
* @brief Acmp positive input
*/
typedef enum
{
ACMP_POS_CH0 = 0, /**< Channel 0 as positive input */
ACMP_POS_CH1 = 1, /**< Channel 1 as positive input */
ACMP_POS_CH2 = 2, /**< Channel 2 as positive input */
ACMP_POS_CH3 = 3, /**< Channel 3 as positive input */
ACMP_POS_CH4 = 4, /**< Channel 4 as positive input */
ACMP_POS_CH5 = 5, /**< Channel 5 as positive input */
ACMP_POS_CH6 = 6, /**< Channel 6 as positive input */
ACMP_POS_CH7 = 7, /**< Channel 7 as positive input */
typedef enum {
ACMP_POS_CH0 = 0U, /**< Channel 0 as positive input */
ACMP_POS_CH1 = 1U, /**< Channel 1 as positive input */
ACMP_POS_CH2 = 2U, /**< Channel 2 as positive input */
ACMP_POS_CH3 = 3U, /**< Channel 3 as positive input */
ACMP_POS_CH4 = 4U, /**< Channel 4 as positive input */
ACMP_POS_CH5 = 5U, /**< Channel 5 as positive input */
ACMP_POS_CH6 = 6U, /**< Channel 6 as positive input */
ACMP_POS_CH7 = 7U, /**< Channel 7 as positive input */
} acmp_pos_input_t;
/**
* @brief Acmp negative input
*/
typedef enum
{
ACMP_NEG_CH0 = 0, /**< Channel 0 as negative input */
ACMP_NEG_CH1 = 1, /**< Channel 1 as negative input */
ACMP_NEG_CH2 = 2, /**< Channel 2 as negative input */
ACMP_NEG_CH3 = 3, /**< Channel 3 as negative input */
ACMP_NEG_CH4 = 4, /**< Channel 4 as negative input */
ACMP_NEG_CH5 = 5, /**< Channel 5 as negative input */
ACMP_NEG_CH6 = 6, /**< Channel 6 as negative input */
ACMP_NEG_CH7 = 7, /**< Channel 7 as negative input */
ACMP_NEG_1V25 = 8, /**< 1.25v as negative input */
ACMP_NEG_2V5 = 9, /**< 2.5v as negative input */
ACMP_NEG_VDD = 10, /**< VDD as negative input */
typedef enum {
ACMP_NEG_CH0 = 0U, /**< Channel 0 as negative input */
ACMP_NEG_CH1 = 1U, /**< Channel 1 as negative input */
ACMP_NEG_CH2 = 2U, /**< Channel 2 as negative input */
ACMP_NEG_CH3 = 3U, /**< Channel 3 as negative input */
ACMP_NEG_CH4 = 4U, /**< Channel 4 as negative input */
ACMP_NEG_CH5 = 5U, /**< Channel 5 as negative input */
ACMP_NEG_CH6 = 6U, /**< Channel 6 as negative input */
ACMP_NEG_CH7 = 7U, /**< Channel 7 as negative input */
ACMP_NEG_1V25 = 8U, /**< 1.25v as negative input */
ACMP_NEG_2V5 = 9U, /**< 2.5v as negative input */
ACMP_NEG_VDD = 10U, /**< VDD as negative input */
} acmp_neg_input_t;
/**
* @brief Acmp mode
*/
typedef enum
{
ACMP_ULTRA_LOW_POWER = 0, /**< Ultra low power mode */
ACMP_LOW_POWER = 1, /**< Low power mode */
ACMP_MIDDLE_POWER = 2, /**< Middle power mode */
ACMP_HIGH_POWER = 3, /**< High power mode */
typedef enum {
ACMP_ULTRA_LOW_POWER = 0U, /**< Ultra low power mode */
ACMP_LOW_POWER = 1U, /**< Low power mode */
ACMP_MIDDLE_POWER = 2U, /**< Middle power mode */
ACMP_HIGH_POWER = 3U, /**< High power mode */
} acmp_mode_t;
/**
* @brief Acmp warm-up time
*/
typedef enum
{
ACMP_4_PCLK = 0, /**< 4 hfperclk cycles */
ACMP_8_PCLK = 1, /**< 4 hfperclk cycles */
ACMP_16_PCLK = 2, /**< 4 hfperclk cycles */
ACMP_32_PCLK = 3, /**< 4 hfperclk cycles */
ACMP_64_PCLK = 4, /**< 4 hfperclk cycles */
ACMP_128_PCLK = 5, /**< 4 hfperclk cycles */
ACMP_256_PCLK = 6, /**< 4 hfperclk cycles */
ACMP_512_PCLK = 7, /**< 4 hfperclk cycles */
typedef enum {
ACMP_4_PCLK = 0U, /**< 4 hfperclk cycles */
ACMP_8_PCLK = 1U, /**< 4 hfperclk cycles */
ACMP_16_PCLK = 2U, /**< 4 hfperclk cycles */
ACMP_32_PCLK = 3U, /**< 4 hfperclk cycles */
ACMP_64_PCLK = 4U, /**< 4 hfperclk cycles */
ACMP_128_PCLK = 5U, /**< 4 hfperclk cycles */
ACMP_256_PCLK = 6U, /**< 4 hfperclk cycles */
ACMP_512_PCLK = 7U, /**< 4 hfperclk cycles */
} acmp_warm_time_t;
/**
* @brief Acmp hysteresis level
*/
typedef enum
{
ACMP_HYST_0 = 0, /**< No hysteresis */
ACMP_HYST_15 = 1, /**< 15mV hysteresis */
ACMP_HYST_22 = 2, /**< 22mV hysteresis */
ACMP_HYST_29 = 3, /**< 29mV hysteresis */
ACMP_HYST_36 = 4, /**< 36mV hysteresis */
ACMP_HYST_43 = 5, /**< 43mV hysteresis */
ACMP_HYST_50 = 6, /**< 50mV hysteresis */
ACMP_HYST_57 = 7, /**< 57mV hysteresis */
typedef enum {
ACMP_HYST_0 = 0U, /**< No hysteresis */
ACMP_HYST_15 = 1U, /**< 15mV hysteresis */
ACMP_HYST_22 = 2U, /**< 22mV hysteresis */
ACMP_HYST_29 = 3U, /**< 29mV hysteresis */
ACMP_HYST_36 = 4U, /**< 36mV hysteresis */
ACMP_HYST_43 = 5U, /**< 43mV hysteresis */
ACMP_HYST_50 = 6U, /**< 50mV hysteresis */
ACMP_HYST_57 = 7U, /**< 57mV hysteresis */
} acmp_hystsel_t;
/**
* @brief Acmp inactive state
*/
typedef enum
{
ACMP_INACTVAL_LOW = 0, /**< The inactive value is 0 */
ACMP_INACTVAL_HIGH = 1, /**< The inactive value is 1 */
typedef enum {
ACMP_INACTVAL_LOW = 0U, /**< The inactive value is 0 */
ACMP_INACTVAL_HIGH = 1U, /**< The inactive value is 1 */
} acmp_inactval_t;
/**
* @brief which edges set up interrupt
*/
typedef enum
{
ACMP_EDGE_NONE = 0, /**< Disable EDGE interrupt */
ACMP_EDGE_FALL = 1, /**< Falling edges set EDGE interrupt */
ACMP_EDGE_RISE = 2, /**< rise edges set EDGE interrupt */
ACMP_EDGE_ALL = 3, /**< Falling edges and rise edges set EDGE interrupt */
typedef enum {
ACMP_EDGE_NONE = 0U, /**< Disable EDGE interrupt */
ACMP_EDGE_FALL = 1U, /**< Falling edges set EDGE interrupt */
ACMP_EDGE_RISE = 2U, /**< rise edges set EDGE interrupt */
ACMP_EDGE_ALL = 3U, /**< Falling edges and rise edges set EDGE interrupt */
} acmp_edge_t;
/**
* @brief Acmp output function
*/
typedef enum
{
ACMP_OUT_DISABLE = 0, /**< Disable acmp output */
ACMP_OUT_ENABLE = 1, /**< Enable acmp output */
typedef enum {
ACMP_OUT_DISABLE = 0U, /**< Disable acmp output */
ACMP_OUT_ENABLE = 1U, /**< Enable acmp output */
} acmp_out_func_t;
/**
* @brief Acmp warm-up interrupt function
*/
typedef enum
{
ACMP_WARM_DISABLE = 0, /**< Disable acmp warm-up interrupt */
ACMP_WARM_ENABLE = 1, /**< Enable acmp warm-up interrupt */
typedef enum {
ACMP_WARM_DISABLE = 0U, /**< Disable acmp warm-up interrupt */
ACMP_WARM_ENABLE = 1U, /**< Enable acmp warm-up interrupt */
} acmp_warm_it_func;
/**
* @brief Acmp gpio output invert
*/
typedef enum
{
ACMP_GPIO_NO_INV = 0, /**< Acmp output to gpio is not inverted */
ACMP_GPIO_INV = 1, /**< Acmp output to gpio is inverted */
typedef enum {
ACMP_GPIO_NO_INV = 0U, /**< Acmp output to gpio is not inverted */
ACMP_GPIO_INV = 1U, /**< Acmp output to gpio is inverted */
} acmp_invert_t;
/**
* @brief Acmp output config structure definition
*/
typedef struct
{
typedef struct {
acmp_out_func_t out_func; /**< Acmp output function */
acmp_invert_t gpio_inv; /**< If invert gpio output */
} acmp_output_config_t;
@ -195,8 +181,7 @@ typedef struct
/**
* @brief Acmp init structure definition
*/
typedef struct
{
typedef struct {
acmp_mode_t mode; /**< Acmp operation mode */
acmp_warm_time_t warm_time; /**< Acmp warm up time */
acmp_hystsel_t hystsel; /**< Acmp hysteresis level */
@ -211,8 +196,7 @@ typedef struct
/**
* @brief ACMP Handle Structure definition
*/
typedef struct acmp_handle_s
{
typedef struct acmp_handle_s {
ACMP_TypeDef *perh; /**< Register base address */
acmp_init_t init; /**< ACMP required parameters */
lock_state_t lock; /**< Locking object */
@ -348,8 +332,7 @@ uint8_t ald_acmp_out_result(acmp_handle_t *hperh);
* @}
*/
#ifdef __cplusplus
extern "C"
}
extern "C" }
#endif
#endif

450
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_adc.h
View File

@ -17,7 +17,7 @@
#define __ALD_ADC_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@ -40,148 +40,135 @@ extern "C" {
/**
* @brief ADC State structures definition
*/
typedef enum
{
ADC_STATE_RESET = 0x0, /**< ADC not yet initialized or disabled */
ADC_STATE_READY = 0x1, /**< ADC peripheral ready for use */
ADC_STATE_BUSY_INTERNAL = 0x2, /**< ADC is busy to internal process */
ADC_STATE_TIMEOUT = 0x4, /**< TimeOut occurrence */
ADC_STATE_ERROR = 0x10, /**< Internal error occurrence */
ADC_STATE_NM_BUSY = 0x100, /**< Conversion on group normal is ongoing or can occur */
ADC_STATE_NM_EOC = 0x200, /**< Conversion data available on group normal */
ADC_STATE_IST_BUSY = 0x1000, /**< Conversion on group insert is ongoing or can occur */
ADC_STATE_IST_EOC = 0x2000, /**< Conversion data available on group insert */
ADC_STATE_AWD = 0x10000, /**< Out-of-window occurrence of analog watchdog */
typedef enum {
ADC_STATE_RESET = 0x0U, /**< ADC not yet initialized or disabled */
ADC_STATE_READY = 0x1U, /**< ADC peripheral ready for use */
ADC_STATE_BUSY = 0x2U, /**< ADC is busy to internal process */
ADC_STATE_TIMEOUT = 0x4U, /**< TimeOut occurrence */
ADC_STATE_ERROR = 0x8U, /**< Internal error occurrence */
ADC_STATE_BUSY_N = 0x10U, /**< Normal channel busy */
ADC_STATE_BUSY_I = 0x20U, /**< Insert channel busy */
ADC_STATE_BUSY_WDG = 0x40U, /**< Insert channel busy */
} adc_state_t;
/**
*@brief ADC Error Code
*/
typedef enum
{
ADC_ERROR_NONE = 0x0, /**< No error */
ADC_ERROR_INTERNAL = 0x1, /**< ADC IP internal error*/
ADC_ERROR_OVR = 0x2, /**< Overrun error */
ADC_ERROR_DMA = 0x4, /**< DMA transfer error */
typedef enum {
ADC_ERROR_NONE = 0x0U, /**< No error */
ADC_ERROR_INTERNAL = 0x1U, /**< ADC IP internal error*/
ADC_ERROR_OVR = 0x2U, /**< Overrun error */
ADC_ERROR_DMA = 0x4U, /**< DMA transfer error */
} adc_error_t;
/**
*@brief ADC data alignment
*/
typedef enum
{
ADC_DATAALIGN_RIGHT = 0x0, /**< ADC data alignment right */
ADC_DATAALIGN_LEFT = 0x1, /**< ADC data alignment left */
typedef enum {
ADC_DATAALIGN_RIGHT = 0x0U, /**< ADC data alignment right */
ADC_DATAALIGN_LEFT = 0x1U, /**< ADC data alignment left */
} adc_align_t;
/**
*@brief ADC config hannal trigger the EOC IT mode
*/
typedef enum
{
ADC_NCHESEL_MODE_ALL = 0x0, /**< ADC set RCHE after convert sequence finish */
ADC_NCHESEL_MODE_ONE = 0x1, /**< ADC set RCHE after one convert finish */
typedef enum {
ADC_NCHESEL_MODE_ALL = 0x0U, /**< ADC set RCHE after convert sequence finish */
ADC_NCHESEL_MODE_ONE = 0x1U, /**< ADC set RCHE after one convert finish */
} adc_nchesel_t;
/**
*@brief ADC channels
*/
typedef enum
{
ADC_CHANNEL_0 = 0x0, /**< ADC channel 0 */
ADC_CHANNEL_1 = 0x1, /**< ADC channel 1 */
ADC_CHANNEL_2 = 0x2, /**< ADC channel 2 */
ADC_CHANNEL_3 = 0x3, /**< ADC channel 3 */
ADC_CHANNEL_4 = 0x4, /**< ADC channel 4 */
ADC_CHANNEL_5 = 0x5, /**< ADC channel 5 */
ADC_CHANNEL_6 = 0x6, /**< ADC channel 6 */
ADC_CHANNEL_7 = 0x7, /**< ADC channel 7 */
ADC_CHANNEL_8 = 0x8, /**< ADC channel 8 */
ADC_CHANNEL_9 = 0x9, /**< ADC channel 9 */
ADC_CHANNEL_10 = 0xA, /**< ADC channel 10 */
ADC_CHANNEL_11 = 0xB, /**< ADC channel 11 */
ADC_CHANNEL_12 = 0xC, /**< ADC channel 12 */
ADC_CHANNEL_13 = 0xD, /**< ADC channel 13 */
ADC_CHANNEL_14 = 0xE, /**< ADC channel 14 */
ADC_CHANNEL_15 = 0xF, /**< ADC channel 15 */
ADC_CHANNEL_16 = 0x10, /**< ADC channel 16 */
ADC_CHANNEL_17 = 0x11, /**< ADC channel 17 */
ADC_CHANNEL_18 = 0x12, /**< ADC channel 18 */
ADC_CHANNEL_19 = 0x13, /**< ADC channel 19 */
typedef enum {
ADC_CHANNEL_0 = 0x0U, /**< ADC channel 0 */
ADC_CHANNEL_1 = 0x1U, /**< ADC channel 1 */
ADC_CHANNEL_2 = 0x2U, /**< ADC channel 2 */
ADC_CHANNEL_3 = 0x3U, /**< ADC channel 3 */
ADC_CHANNEL_4 = 0x4U, /**< ADC channel 4 */
ADC_CHANNEL_5 = 0x5U, /**< ADC channel 5 */
ADC_CHANNEL_6 = 0x6U, /**< ADC channel 6 */
ADC_CHANNEL_7 = 0x7U, /**< ADC channel 7 */
ADC_CHANNEL_8 = 0x8U, /**< ADC channel 8 */
ADC_CHANNEL_9 = 0x9U, /**< ADC channel 9 */
ADC_CHANNEL_10 = 0xAU, /**< ADC channel 10 */
ADC_CHANNEL_11 = 0xBU, /**< ADC channel 11 */
ADC_CHANNEL_12 = 0xCU, /**< ADC channel 12 */
ADC_CHANNEL_13 = 0xDU, /**< ADC channel 13 */
ADC_CHANNEL_14 = 0xEU, /**< ADC channel 14 */
ADC_CHANNEL_15 = 0xFU, /**< ADC channel 15 */
ADC_CHANNEL_16 = 0x10U, /**< ADC channel 16 */
ADC_CHANNEL_17 = 0x11U, /**< ADC channel 17 */
ADC_CHANNEL_18 = 0x12U, /**< ADC channel 18 */
ADC_CHANNEL_19 = 0x13U, /**< ADC channel 19 */
} adc_channel_t;
/**
*@brief ADC sampling times
*/
typedef enum
{
ADC_SAMPLETIME_1 = 0x0, /**< ADC sampling times 1 clk */
ADC_SAMPLETIME_2 = 0x1, /**< ADC sampling times 2 clk */
ADC_SAMPLETIME_4 = 0x2, /**< ADC sampling times 4 clk */
ADC_SAMPLETIME_15 = 0x3, /**< ADC sampling times 15 clk */
typedef enum {
ADC_SAMPLETIME_1 = 0x0U, /**< ADC sampling times 1 clk */
ADC_SAMPLETIME_2 = 0x1U, /**< ADC sampling times 2 clk */
ADC_SAMPLETIME_4 = 0x2U, /**< ADC sampling times 4 clk */
ADC_SAMPLETIME_15 = 0x3U, /**< ADC sampling times 15 clk */
} adc_samp_t;
/**
*@brief ADC rank into normal group
*@brief ADC index channel in normal group
*/
typedef enum
{
ADC_NCH_RANK_1 = 0x1, /**< ADC normal channel rank 1 */
ADC_NCH_RANK_2 = 0x2, /**< ADC normal channel rank 2 */
ADC_NCH_RANK_3 = 0x3, /**< ADC normal channel rank 3 */
ADC_NCH_RANK_4 = 0x4, /**< ADC normal channel rank 4 */
ADC_NCH_RANK_5 = 0x5, /**< ADC normal channel rank 5 */
ADC_NCH_RANK_6 = 0x6, /**< ADC normal channel rank 6 */
ADC_NCH_RANK_7 = 0x7, /**< ADC normal channel rank 7 */
ADC_NCH_RANK_8 = 0x8, /**< ADC normal channel rank 8 */
ADC_NCH_RANK_9 = 0x9, /**< ADC normal channel rank 9 */
ADC_NCH_RANK_10 = 0xA, /**< ADC normal channel rank 10 */
ADC_NCH_RANK_11 = 0xB, /**< ADC normal channel rank 11 */
ADC_NCH_RANK_12 = 0xC, /**< ADC normal channel rank 12 */
ADC_NCH_RANK_13 = 0xD, /**< ADC normal channel rank 13 */
ADC_NCH_RANK_14 = 0xE, /**< ADC normal channel rank 14 */
ADC_NCH_RANK_15 = 0xF, /**< ADC normal channel rank 15 */
ADC_NCH_RANK_16 = 0x10, /**< ADC normal channel rank 16 */
} adc_nch_rank_t;
typedef enum {
ADC_NCH_IDX_1 = 0x1U, /**< ADC normal channel index 1 */
ADC_NCH_IDX_2 = 0x2U, /**< ADC normal channel index 2 */
ADC_NCH_IDX_3 = 0x3U, /**< ADC normal channel index 3 */
ADC_NCH_IDX_4 = 0x4U, /**< ADC normal channel index 4 */
ADC_NCH_IDX_5 = 0x5U, /**< ADC normal channel index 5 */
ADC_NCH_IDX_6 = 0x6U, /**< ADC normal channel index 6 */
ADC_NCH_IDX_7 = 0x7U, /**< ADC normal channel index 7 */
ADC_NCH_IDX_8 = 0x8U, /**< ADC normal channel index 8 */
ADC_NCH_IDX_9 = 0x9U, /**< ADC normal channel index 9 */
ADC_NCH_IDX_10 = 0xAU, /**< ADC normal channel index 10 */
ADC_NCH_IDX_11 = 0xBU, /**< ADC normal channel index 11 */
ADC_NCH_IDX_12 = 0xCU, /**< ADC normal channel index 12 */
ADC_NCH_IDX_13 = 0xDU, /**< ADC normal channel index 13 */
ADC_NCH_IDX_14 = 0xEU, /**< ADC normal channel index 14 */
ADC_NCH_IDX_15 = 0xFU, /**< ADC normal channel index 15 */
ADC_NCH_IDX_16 = 0x10U, /**< ADC normal channel index 16 */
} adc_nch_idx_t;
/**
* @brief ADC rank into insert group
* @brief ADC index channel in insert group
*/
typedef enum
{
ADC_ICH_RANK_1 = 0x1, /**< ADC insert channel rank 1 */
ADC_ICH_RANK_2 = 0x2, /**< ADC insert channel rank 2 */
ADC_ICH_RANK_3 = 0x3, /**< ADC insert channel rank 3 */
ADC_ICH_RANK_4 = 0x4, /**< ADC insert channel rank 4 */
} adc_ich_rank_t;
typedef enum {
ADC_ICH_IDX_1 = 0x1U, /**< ADC insert channel index 1 */
ADC_ICH_IDX_2 = 0x2U, /**< ADC insert channel index 2 */
ADC_ICH_IDX_3 = 0x3U, /**< ADC insert channel index 3 */
ADC_ICH_IDX_4 = 0x4U, /**< ADC insert channel index 4 */
} adc_ich_idx_t;
/**
* @brief ADC analog watchdog mode
*/
typedef enum
{
ADC_ANAWTD_NONE = 0x0, /**< No watch dog */
ADC_ANAWTD_SING_NM = 0x800200, /**< One normal channel watch dog */
ADC_ANAWTD_SING_IST = 0x400200, /**< One inset channel Injec watch dog */
ADC_ANAWTD_SING_NMIST = 0xC00200, /**< One normal and inset channel watch dog */
ADC_ANAWTD_ALL_NM = 0x800000, /**< All normal channel watch dog */
ADC_ANAWTD_ALL_IST = 0x400000, /**< All inset channel watch dog */
ADC_ANAWTD_ALL_NMIST = 0xC00000, /**< All normal and inset channel watch dog */
} adc_ana_wtd_t;
typedef enum {
ADC_ANAWTD_NONE = 0x0U, /**< No watch dog */
ADC_ANAWTD_SING_NM = 0x800200U, /**< One normal channel watch dog */
ADC_ANAWTD_SING_IST = 0x400200U, /**< One insert channel watch dog */
ADC_ANAWTD_SING_NMIST = 0xC00200U, /**< One normal and insert channel watch dog */
ADC_ANAWTD_ALL_NM = 0x800000U, /**< All normal channel watch dog */
ADC_ANAWTD_ALL_IST = 0x400000U, /**< All insert channel watch dog */
ADC_ANAWTD_ALL_NMIST = 0xC00000U, /**< All normal and insert channel watch dog */
} adc_ana_wdg_t;
/**
* @brief ADC Event type
*/
typedef enum
{
typedef enum {
ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */
} adc_event_type_t;
/**
* @brief ADC interrupts definition
*/
typedef enum
{
typedef enum {
ADC_IT_NCH = (1U << 5), /**< ADC it normal */
ADC_IT_AWD = (1U << 6), /**< ADC it awd */
ADC_IT_ICH = (1U << 7), /**< ADC it insert */
@ -191,176 +178,164 @@ typedef enum
/**
* @brief ADC flags definition
*/
typedef enum
{
typedef enum {
ADC_FLAG_AWD = (1U << 0), /**<ADC flag awd */
ADC_FLAG_NCH = (1U << 1), /**<ADC flag normal mode */
ADC_FLAG_ICH = (1U << 2), /**<ADC flag inset mode */
ADC_FLAG_ICH = (1U << 2), /**<ADC flag insert mode */
ADC_FLAG_OVR = (1U << 3), /**<ADC flag ovr */
ADC_FLAG_NCHS = (1U << 8), /**<ADC flag normal start */
ADC_FLAG_ICHS = (1U << 9), /**<ADC flag inset start */
ADC_FLAG_ICHS = (1U << 9), /**<ADC flag insert start */
} adc_flag_t;
/**
* @brief ADC CLD DIV definition
*/
typedef enum
{
ADC_CKDIV_1 = 0x0, /**< ADC CLK DIV 1 */
ADC_CKDIV_2 = 0x1, /**< ADC CLK DIV 2 */
ADC_CKDIV_4 = 0x2, /**< ADC CLK DIV 4 */
ADC_CKDIV_8 = 0x3, /**< ADC CLK DIV 8 */
ADC_CKDIV_16 = 0x4, /**< ADC CLK DIV 16 */
ADC_CKDIV_32 = 0x5, /**< ADC CLK DIV 32 */
ADC_CKDIV_64 = 0x6, /**< ADC CLK DIV 64 */
ADC_CKDIV_128 = 0x7, /**< ADC CLK DIV 128 */
typedef enum {
ADC_CKDIV_1 = 0x0U, /**< ADC CLK DIV 1 */
ADC_CKDIV_2 = 0x1U, /**< ADC CLK DIV 2 */
ADC_CKDIV_4 = 0x2U, /**< ADC CLK DIV 4 */
ADC_CKDIV_8 = 0x3U, /**< ADC CLK DIV 8 */
ADC_CKDIV_16 = 0x4U, /**< ADC CLK DIV 16 */
ADC_CKDIV_32 = 0x5U, /**< ADC CLK DIV 32 */
ADC_CKDIV_64 = 0x6U, /**< ADC CLK DIV 64 */
ADC_CKDIV_128 = 0x7U, /**< ADC CLK DIV 128 */
} adc_clk_div_t;
/**
* @brief ADC negative reference voltage definition
*/
typedef enum
{
ADC_NEG_REF_VSS = 0x0, /**< ADC negative regerence voltage vss */
ADC_NEG_REF_VREFN = 0x1, /**< ADC negative regerence voltage vrefn */
typedef enum {
ADC_NEG_REF_VSS = 0x0U, /**< ADC negative regerence voltage vss */
ADC_NEG_REF_VREFN = 0x1U, /**< ADC negative regerence voltage vrefn */
} adc_neg_ref_t;
/**
* @brief ADC positive reference voltage definition
*/
typedef enum
{
ADC_POS_REF_VDD = 0x0, /**< ADC posotove reference is VDD */
ADC_POS_REF_VREEFP = 0x2, /**< ADC posotove reference is VREEFP */
ADC_POS_REF_VREEFP_BUF = 0x3, /**< ADC posotove reference is VREEFP BUFFER */
typedef enum {
ADC_POS_REF_VDD = 0x0U, /**< ADC posotove reference is VDD */
ADC_POS_REF_VREEFP = 0x2U, /**< ADC posotove reference is VREEFP */
ADC_POS_REF_VREEFP_BUF = 0x3U, /**< ADC posotove reference is VREEFP BUFFER */
} adc_pos_ref_t;
/**
* @brief ADC numbers of normal conversion channals
*/
typedef enum
{
ADC_NCH_LEN_1 = 0x0, /**< ADC length of normal conversion 1 */
ADC_NCH_LEN_2 = 0x1, /**< ADC length of normal conversion 2 */
ADC_NCH_LEN_3 = 0x2, /**< ADC length of normal conversion 3 */
ADC_NCH_LEN_4 = 0x3, /**< ADC length of normal conversion 4 */
ADC_NCH_LEN_5 = 0x4, /**< ADC length of normal conversion 5 */
ADC_NCH_LEN_6 = 0x5, /**< ADC length of normal conversion 6 */
ADC_NCH_LEN_7 = 0x6, /**< ADC length of normal conversion 7 */
ADC_NCH_LEN_8 = 0x7, /**< ADC length of normal conversion 8 */
ADC_NCH_LEN_9 = 0x8, /**< ADC length of normal conversion 9 */
ADC_NCH_LEN_10 = 0x9, /**< ADC length of normal conversion 10 */
ADC_NCH_LEN_11 = 0xA, /**< ADC length of normal conversion 11 */
ADC_NCH_LEN_12 = 0xB, /**< ADC length of normal conversion 12 */
ADC_NCH_LEN_13 = 0xC, /**< ADC length of normal conversion 13 */
ADC_NCH_LEN_14 = 0xD, /**< ADC length of normal conversion 14 */
ADC_NCH_LEN_15 = 0xE, /**< ADC length of normal conversion 15 */
ADC_NCH_LEN_16 = 0xF, /**< ADC length of normal conversion 16 */
} adc_nch_len_t;
typedef enum {
ADC_NCH_NR_1 = 0x0U, /**< ADC number of normal conversion 1 */
ADC_NCH_NR_2 = 0x1U, /**< ADC number of normal conversion 2 */
ADC_NCH_NR_3 = 0x2U, /**< ADC number of normal conversion 3 */
ADC_NCH_NR_4 = 0x3U, /**< ADC number of normal conversion 4 */
ADC_NCH_NR_5 = 0x4U, /**< ADC number of normal conversion 5 */
ADC_NCH_NR_6 = 0x5U, /**< ADC number of normal conversion 6 */
ADC_NCH_NR_7 = 0x6U, /**< ADC number of normal conversion 7 */
ADC_NCH_NR_8 = 0x7U, /**< ADC number of normal conversion 8 */
ADC_NCH_NR_9 = 0x8U, /**< ADC number of normal conversion 9 */
ADC_NCH_NR_10 = 0x9U, /**< ADC number of normal conversion 10 */
ADC_NCH_NR_11 = 0xAU, /**< ADC number of normal conversion 11 */
ADC_NCH_NR_12 = 0xBU, /**< ADC number of normal conversion 12 */
ADC_NCH_NR_13 = 0xCU, /**< ADC number of normal conversion 13 */
ADC_NCH_NR_14 = 0xDU, /**< ADC number of normal conversion 14 */
ADC_NCH_NR_15 = 0xEU, /**< ADC number of normal conversion 15 */
ADC_NCH_NR_16 = 0xFU, /**< ADC number of normal conversion 16 */
} adc_nch_nr_t;
/**
* @brief ADC numbers of insert conversion channals
*/
typedef enum
{
ADC_ICH_LEN_1 = 0x0, /**< ADC number of insert conversion 1 */
ADC_ICH_LEN_2 = 0x1, /**< ADC number of insert conversion 2 */
ADC_ICH_LEN_3 = 0x2, /**< ADC number of insert conversion 3 */
ADC_ICH_LEN_4 = 0x3, /**< ADC number of insert conversion 4 */
} adc_ich_len_t;
typedef enum {
ADC_ICH_NR_1 = 0x0U, /**< ADC number of insert conversion 1 */
ADC_ICH_NR_2 = 0x1U, /**< ADC number of insert conversion 2 */
ADC_ICH_NR_3 = 0x2U, /**< ADC number of insert conversion 3 */
ADC_ICH_NR_4 = 0x3U, /**< ADC number of insert conversion 4 */
} adc_ich_nr_t;
/**
* @brief ADC discontinuous mode choose
*/
typedef enum
{
ADC_ALL_DISABLE = 0x0, /**< ADC discontinuous mode all disable */
ADC_NCH_DISC_EN = 0x1, /**< ADC normal channel discontinuous mode enable */
ADC_ICH_DISC_EN = 0x2, /**< ADC insert channel discontinuous mode enable */
typedef enum {
ADC_ALL_DISABLE = 0x0U, /**< ADC discontinuous mode all disable */
ADC_NCH_DISC_EN = 0x1U, /**< ADC normal channel discontinuous mode enable */
ADC_ICH_DISC_EN = 0x2U, /**< ADC insert channel discontinuous mode enable */
} adc_disc_mode_t;
/**
* @brief ADC numbers of channals in discontinuous conversion mode
*/
typedef enum
{
ADC_DISC_NBR_1 = 0x0, /**< ADC number of discontinuous conversion 1 */
ADC_DISC_NBR_2 = 0x1, /**< ADC number of discontinuous conversion 2 */
ADC_DISC_NBR_3 = 0x2, /**< ADC number of discontinuous conversion 3 */
ADC_DISC_NBR_4 = 0x3, /**< ADC number of discontinuous conversion 4 */
ADC_DISC_NBR_5 = 0x4, /**< ADC number of discontinuous conversion 5 */
ADC_DISC_NBR_6 = 0x5, /**< ADC number of discontinuous conversion 6 */
ADC_DISC_NBR_7 = 0x6, /**< ADC number of discontinuous conversion 7 */
ADC_DISC_NBR_8 = 0x7, /**< ADC number of discontinuous conversion 8 */
} adc_disc_nbr_t;
typedef enum {
ADC_DISC_NR_1 = 0x0U, /**< ADC number of discontinuous conversion 1 */
ADC_DISC_NR_2 = 0x1U, /**< ADC number of discontinuous conversion 2 */
ADC_DISC_NR_3 = 0x2U, /**< ADC number of discontinuous conversion 3 */
ADC_DISC_NR_4 = 0x3U, /**< ADC number of discontinuous conversion 4 */
ADC_DISC_NR_5 = 0x4U, /**< ADC number of discontinuous conversion 5 */
ADC_DISC_NR_6 = 0x5U, /**< ADC number of discontinuous conversion 6 */
ADC_DISC_NR_7 = 0x6U, /**< ADC number of discontinuous conversion 7 */
ADC_DISC_NR_8 = 0x7U, /**< ADC number of discontinuous conversion 8 */
} adc_disc_nr_t;
/**
* @brief ADC resolution of conversion
*/
typedef enum
{
ADC_CONV_RES_6 = 0x0, /**< ADC resolution of conversion 6 */
ADC_CONV_RES_8 = 0x1, /**< ADC resolution of conversion 8 */
ADC_CONV_RES_10 = 0x2, /**< ADC resolution of conversion 10 */
ADC_CONV_RES_12 = 0x3, /**< ADC resolution of conversion 12 */
} adc_conv_res_t;
typedef enum {
ADC_CONV_BIT_6 = 0x0U, /**< ADC resolution of conversion 6 */
ADC_CONV_BIT_8 = 0x1U, /**< ADC resolution of conversion 8 */
ADC_CONV_BIT_10 = 0x2U, /**< ADC resolution of conversion 10 */
ADC_CONV_BIT_12 = 0x3U, /**< ADC resolution of conversion 12 */
} adc_conv_bit_t;
/**
* @brief Structure definition of ADC and normal group initialization
*/
typedef struct
{
adc_align_t data_align; /**< Specifies ADC data alignment */
type_func_t scan_mode; /**< Choose scan mode enable or not */
type_func_t cont_mode; /**< Choose continuous mode enable or not */
adc_nch_len_t nch_len; /**< Length of normal ranks will be converted */
adc_disc_mode_t disc_mode; /**< Discontinuous mode enable or not */
adc_disc_nbr_t disc_nbr; /**< Number of discontinuous conversions channel */
adc_conv_res_t conv_res; /**< The precision of conversion */
adc_clk_div_t clk_div; /**< ADCCLK divider */
typedef struct {
adc_align_t align; /**< Specifies ADC data alignment */
type_func_t scan; /**< Choose scan mode enable or not */
type_func_t cont; /**< Choose continuous mode enable or not */
adc_nch_nr_t nch_nr; /**< Length of normal ranks will be converted */
adc_disc_mode_t disc; /**< Discontinuous mode enable or not */
adc_disc_nr_t disc_nr; /**< Number of discontinuous conversions channel */
adc_conv_bit_t data_bit; /**< The precision of conversion */
adc_clk_div_t div; /**< ADCCLK divider */
adc_nchesel_t nche_sel; /**< Trigger the NCHE FALG mode */
adc_neg_ref_t neg_ref; /**< The negative reference voltage*/
adc_pos_ref_t pos_ref; /**< The positive reference voltage*/
adc_neg_ref_t n_ref; /**< The negative reference voltage*/
adc_pos_ref_t p_ref; /**< The positive reference voltage*/
} adc_init_t;
/**
* @brief Structure definition of ADC channel for normal group
*/
typedef struct
{
adc_channel_t channel; /**< The channel to configure into ADC normal group */
adc_nch_rank_t rank; /**< The rank in the normal group sequencer */
adc_samp_t samp_time; /**< Sampling time value to be set */
typedef struct {
adc_channel_t ch; /**< The channel to configure into ADC normal group */
adc_nch_idx_t idx; /**< The rank in the normal group sequencer */
adc_samp_t samp; /**< Sampling time value to be set */
} adc_nch_conf_t;
/**
* @brief ADC Configuration analog watchdog definition
*/
typedef struct
{
adc_ana_wtd_t watchdog_mode; /**< Configures the ADC analog watchdog mode*/
adc_channel_t channel; /**< Selects which ADC channel to monitor by analog watchdog */
type_func_t it_mode; /**< Whether the analog watchdog is configured in interrupt */
uint32_t high_threshold; /**< The ADC analog watchdog High threshold value. */
uint32_t low_threshold; /**< The ADC analog watchdog Low threshold value. */
typedef struct {
adc_ana_wdg_t mode; /**< Configures the ADC analog watchdog mode*/
adc_channel_t ch; /**< Selects which ADC channel to monitor by analog watchdog */
type_func_t interrupt; /**< Whether the analog watchdog is configured in interrupt */
uint32_t high_thrd; /**< The ADC analog watchdog High threshold value. */
uint32_t low_thrd; /**< The ADC analog watchdog Low threshold value. */
} adc_analog_wdg_conf_t;
/**
* @brief ADC Configuration insert Channel structure definition
*/
typedef struct
{
adc_channel_t channel; /**< Selection of ADC channel to configure */
adc_ich_rank_t rank; /**< Rank in the insert group sequencer */
adc_samp_t samp_time; /**< Sampling time value for selected channel */
typedef struct {
adc_channel_t ch; /**< Selection of ADC channel to configure */
adc_ich_idx_t idx; /**< Rank in the insert group sequencer */
adc_samp_t samp; /**< Sampling time value for selected channel */
uint32_t offset; /**< The offset about converted data */
adc_ich_len_t ich_len; /**< The number of insert ranks */
type_func_t auto_inj; /**< insert sequence's auto function */
adc_ich_nr_t nr; /**< The number of insert ranks */
type_func_t auto_m; /**< insert sequence's auto function */
} adc_ich_conf_t;
/**
* @brief ADC handle Structure definition
*/
typedef struct adc_handle_s
{
typedef struct adc_handle_s {
ADC_TypeDef *perh; /**< Register base address */
adc_init_t init; /**< ADC required parameters */
#ifdef ALD_DMA
@ -372,18 +347,17 @@ typedef struct adc_handle_s
adc_state_t state; /**< ADC communication state */
adc_error_t error_code; /**< ADC Error code */
void (*adc_reg_cplt_cbk)(struct adc_handle_s *arg); /**< Regluar Conversion complete callback */
void (*adc_inj_cplt_cbk)(struct adc_handle_s *arg); /**< insert Conversion complete callback */
void (*adc_out_of_win_cbk)(struct adc_handle_s *arg); /**< Level out of window callback */
void (*adc_error_cbk)(struct adc_handle_s *arg); /**< adc error callback */
void (*adc_ovr_cbk)(struct adc_handle_s *arg); /**< adc ovr callback */
void (*normal_cplt_cbk)( struct adc_handle_s *arg); /**< Regluar Conversion complete callback */
void (*insert_cplt_cbk)( struct adc_handle_s *arg); /**< insert Conversion complete callback */
void (*wdg_cbk)( struct adc_handle_s *arg); /**< Level out of window callback */
void (*error_cbk)(struct adc_handle_s *arg); /**< adc error callback */
void (*ovr_cbk)(struct adc_handle_s *arg); /**< adc ovr callback */
} adc_handle_t;
/**
* @brief Timer trigger adc config structure definition
*/
typedef struct
{
typedef struct {
uint32_t time; /**< Timer period time uint: us */
uint16_t size; /**< Adc convert times */
uint16_t *buf; /**< Convert data buffer */
@ -391,17 +365,17 @@ typedef struct
adc_pos_ref_t p_ref; /**< The positive reference voltage for adc*/
adc_channel_t adc_ch; /**< Adc channel */
uint8_t dma_ch; /**< Dma channel */
TIMER_TypeDef *p_timer; /**< Adc peripheral */
ADC_TypeDef *p_adc; /**< Dma peripheral */
void (*adc_cplt_cbk)(struct adc_handle_s *arg); /**< Conversion complete callback */
TIMER_TypeDef *p_timer; /**< Timer peripheral */
ADC_TypeDef *p_adc; /**< Adc peripheral */
void (*cplt_cbk)( struct adc_handle_s *arg); /**< Conversion complete callback */
/* private variable */
lock_state_t lock; /**< Locking object */
pis_handle_t lh_pis; /**< Handle of PIS module */
dma_handle_t lh_dma; /**< Handle of DMA module */
timer_handle_t lh_timer; /**< Handle of TIMER module */
adc_handle_t lh_adc; /**< Handle of ADC module */
adc_nch_conf_t lnm_config; /**< Struct for chanel configure */
pis_handle_t h_pis; /**< Handle of PIS module */
dma_handle_t h_dma; /**< Handle of DMA module */
timer_handle_t h_timer; /**< Handle of TIMER module */
adc_handle_t h_adc; /**< Handle of ADC module */
adc_nch_conf_t config; /**< Struct for channel configure */
} adc_timer_config_t;
/**
* @}
@ -417,6 +391,10 @@ typedef struct
#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET)
#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
#define ADC_SPEED_HIGH_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK))
#define ADC_SPEED_HIGH_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK))
#define ADC_CALIBRATE_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK))
#define ADC_CALIBRATE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK))
/**
* @}
*/
@ -424,15 +402,13 @@ typedef struct
/** @defgroup ADC_Private_Macros ADC Private Macros
* @{
*/
#define IS_ADC_ICH_RANK_TYPE(x) ((x) <= ADC_ICH_RANK_4)
#define IS_ADC_NCH_RANK_TYPE(x) ((x) <= ADC_NCH_RANK_16)
#define IS_ADC_ICH_IDX_TYPE(x) ((x) <= ADC_ICH_IDX_4)
#define IS_ADC_NCH_IDX_TYPE(x) ((x) <= ADC_NCH_IDX_16)
#define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ADC_SAMPLETIME_1) || \
((x) == ADC_SAMPLETIME_2) || \
((x) == ADC_SAMPLETIME_4) || \
((x) == ADC_SAMPLETIME_15))
#define IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_19)
#define IS_ADC_SCAN_MODE_TYPE(x) (((x) == DISABLE) || \
((x) == ENABLE))
#define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ADC_DATAALIGN_RIGHT) || \
((x) == ADC_DATAALIGN_LEFT))
#define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ADC_ANAWTD_NONE) || \
@ -465,27 +441,26 @@ typedef struct
#define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ADC_POS_REF_VDD) || \
((x) == ADC_POS_REF_VREEFP) || \
((x) == ADC_POS_REF_VREEFP_BUF))
#define IS_ADC_NCH_LEN_TYPE(x) ((x) <= ADC_NCH_LEN_16)
#define IS_ADC_NBR_OF_IST_TYPE(x) ((x) <= ADC_ICH_LEN_4)
#define IS_ADC_NCH_NR_TYPE(x) ((x) <= ADC_NCH_NR_16)
#define IS_ADC_ICH_NR_TYPE(x) ((x) <= ADC_ICH_NR_4)
#define IS_ADC_DISC_MODE_TYPE(x) (((x) == ADC_ALL_DISABLE) || \
((x) == ADC_NCH_DISC_EN) || \
((x) == ADC_ICH_DISC_EN))
#define IS_ADC_DISC_NBR_TYPE(x) ((x) <= ADC_DISC_NBR_8)
#define IS_ADC_CONV_RES_TYPE(x) (((x) == ADC_CONV_RES_12) || \
((x) == ADC_CONV_RES_6) || \
((x) == ADC_CONV_RES_8) || \
((x) == ADC_CONV_RES_10))
#define IS_ADC_DISC_NR_TYPE(x) ((x) <= ADC_DISC_NR_8)
#define IS_ADC_CONV_BIT_TYPE(x) (((x) == ADC_CONV_BIT_12) || \
((x) == ADC_CONV_BIT_6) || \
((x) == ADC_CONV_BIT_8) || \
((x) == ADC_CONV_BIT_10))
#define IS_ADC_TRIG_MODE_TYPE(x) (((x) == ADC_TRIG_SOFT) || \
((x) == ADC_TRIG_PIS) || \
((x) == ADC_TRIG_PIS_SOFT))
#define IS_ADC_TYPE(x) (((x) == ADC0) || \
((x) == ADC1))
#define IS_ADC_TYPE(x) (((x) == ADC0))
#define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ADC_NCHESEL_MODE_ALL) || \
((x) == ADC_NCHESEL_MODE_ONE))
#define IS_ADC_EVENT_TYPE(x) ((x) == ADC_AWD_EVENT)
#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff)
#define IS_HTR_TYPE(x) ((x) <= 0xfff)
#define IS_LTR_TYPE(x) ((x) <= 0xfff)
#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xFFF)
#define IS_HTR_TYPE(x) ((x) <= 0xFFF)
#define IS_LTR_TYPE(x) ((x) <= 0xFFF)
/**
* @}
*/
@ -514,7 +489,7 @@ ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh);
ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh);
#ifdef ALD_DMA
ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel);
ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh);
ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel);
ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config);
#endif
uint32_t ald_adc_normal_get_value(adc_handle_t *hperh);
@ -524,7 +499,7 @@ ald_status_t ald_adc_insert_stop(adc_handle_t *hperh);
ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout);
ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh);
ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh);
uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank);
uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t ih_rank);
void ald_adc_irq_handler(adc_handle_t *hperh);
/**
* @}
@ -565,8 +540,7 @@ uint32_t ald_adc_get_error(adc_handle_t *hperh);
* @}
*/
#ifdef __cplusplus
extern "C"
}
extern "C" }
#endif
#endif /* __ALD_ADC_H */
#endif /* __ALD_ADC_H__ */

99
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_bkpc.h
View File

@ -35,44 +35,44 @@ extern "C" {
/** @defgroup BKPC_Public_Macros BKPC Public Macros
* @{
*/
#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0))
#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55))
#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0U))
#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55U))
#define BKPC_LRC_ENABLE() \
do { \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
} while (0)
#define BKPC_LRC_DISABLE() \
do { \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
} while (0)
#define BKPC_LOSM_ENABLE() \
do { \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \
BKPC_LOCK(); \
} while (0)
} while (0)
#define BKPC_LOSM_DISABLE() \
do { \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
BKPC_LOCK(); \
} while (0)
} while (0)
#define BKPC_LOSC_ENABLE() \
do { \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \
BKPC_LOCK(); \
} while (0)
} while (0)
#define BKPC_LOSC_DISABLE() \
do { \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
BKPC_LOCK(); \
} while (0)
} while (0)
/**
* @}
*/
@ -83,37 +83,31 @@ extern "C" {
/**
* @brief BKPC ldo output select
*/
typedef enum
{
BKPC_LDO_OUTPUT_1_6 = 0x0, /**< 1.6V */
BKPC_LDO_OUTPUT_1_3 = 0x1, /**< 1.3V */
BKPC_LDO_OUTPUT_1_4 = 0x2, /**< 1.4V */
BKPC_LDO_OUTPUT_1_5 = 0x4, /**< 1.5V */
typedef enum {
BKPC_LDO_OUTPUT_1_6 = 0x0U, /**< 1.6V */
BKPC_LDO_OUTPUT_1_3 = 0x1U, /**< 1.3V */
BKPC_LDO_OUTPUT_1_4 = 0x2U, /**< 1.4V */
BKPC_LDO_OUTPUT_1_5 = 0x4U, /**< 1.5V */
} bkpc_ldo_output_t;
/**
* @brief BKPC BOR voltage select
* @brief Standby wakeup port select
*/
typedef enum
{
BKPC_BOR_VOL_1_7 = 0x0, /**< 1.7V */
BKPC_BOR_VOL_2_0 = 0x1, /**< 2.0V */
BKPC_BOR_VOL_2_1 = 0x2, /**< 2.1V */
BKPC_BOR_VOL_2_2 = 0x3, /**< 2.2V */
BKPC_BOR_VOL_2_3 = 0x4, /**< 2.3V */
BKPC_BOR_VOL_2_4 = 0x5, /**< 2.4V */
BKPC_BOR_VOL_2_5 = 0x6, /**< 2.5V */
BKPC_BOR_VOL_2_6 = 0x7, /**< 2.6V */
BKPC_BOR_VOL_2_8 = 0x8, /**< 2.8V */
BKPC_BOR_VOL_3_0 = 0x9, /**< 3.0V */
BKPC_BOR_VOL_3_1 = 0xA, /**< 3.1V */
BKPC_BOR_VOL_3_3 = 0xB, /**< 3.3V */
BKPC_BOR_VOL_3_6 = 0xC, /**< 3.6V */
BKPC_BOR_VOL_3_7 = 0xD, /**< 3.7V */
BKPC_BOR_VOL_4_0 = 0xE, /**< 4.0V */
BKPC_BOR_VOL_4_3 = 0xF, /**< 4.3V */
} bkpc_bor_vol_t;
typedef enum {
PMU_STANDBY_PORT_SEL_PA0 = 0x0U, /**< Wakeup by PA0 */
PMU_STANDBY_PORT_SEL_PA1 = 0x1U, /**< Wakeup by PA1 */
PMU_STANDBY_PORT_SEL_PA2 = 0x2U, /**< Wakeup by PA2 */
PMU_STANDBY_PORT_SEL_PA3 = 0x3U, /**< Wakeup by PA3 */
PMU_STANDBY_PORT_SEL_NONE = 0xFU, /**< Wakeup by other source */
} bkpc_wakeup_port_t;
/**
* @brief Standby wakeup level
*/
typedef enum {
PMU_STANDBY_LEVEL_HIGH = 0x0U, /**< High level */
PMU_STANDBY_LEVEL_LOW = 0x1U, /**< Low level */
} bkpc_wakeup_level_t;
/**
* @}
*/
@ -126,22 +120,13 @@ typedef enum
((x) == BKPC_LDO_OUTPUT_1_3) || \
((x) == BKPC_LDO_OUTPUT_1_4) || \
((x) == BKPC_LDO_OUTPUT_1_5))
#define IS_BKPC_BOR_VOL(x) (((x) == BKPC_BOR_VOL_1_7) || \
((x) == BKPC_BOR_VOL_2_0) || \
((x) == BKPC_BOR_VOL_2_1) || \
((x) == BKPC_BOR_VOL_2_2) || \
((x) == BKPC_BOR_VOL_2_3) || \
((x) == BKPC_BOR_VOL_2_4) || \
((x) == BKPC_BOR_VOL_2_5) || \
((x) == BKPC_BOR_VOL_2_6) || \
((x) == BKPC_BOR_VOL_2_8) || \
((x) == BKPC_BOR_VOL_3_0) || \
((x) == BKPC_BOR_VOL_3_1) || \
((x) == BKPC_BOR_VOL_3_3) || \
((x) == BKPC_BOR_VOL_3_6) || \
((x) == BKPC_BOR_VOL_3_7) || \
((x) == BKPC_BOR_VOL_4_0) || \
((x) == BKPC_BOR_VOL_4_3))
#define IS_BKPC_WAKEUP_PORT(x) (((x) == PMU_STANDBY_PORT_SEL_PA0) || \
((x) == PMU_STANDBY_PORT_SEL_PA1) || \
((x) == PMU_STANDBY_PORT_SEL_PA2) || \
((x) == PMU_STANDBY_PORT_SEL_PA3) || \
((x) == PMU_STANDBY_PORT_SEL_NONE))
#define IS_BKPC_WAKEUP_LEVEL(x) (((x) == PMU_STANDBY_LEVEL_HIGH) || \
((x) == PMU_STANDBY_LEVEL_LOW))
#define IS_BKPC_RAM_IDX(x) ((x) < 32)
/**
* @}
@ -154,8 +139,8 @@ typedef enum
* @{
*/
/* control functions */
extern void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
extern void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state);
extern void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state);
/**
* @}
*/

352
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_cmu.h
View File

@ -37,91 +37,91 @@ extern "C" {
* @{
*/
#define CMU_LOSC_ENABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define CMU_LOSC_DISABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define CMU_LRC_ENABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define CMU_LRC_DISABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define CMU_ULRC_ENABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define CMU_ULRC_DISABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
/* Low power mode control */
#define CMU_LP_LRC_ENABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define CMU_LP_LRC_DISABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define CMU_LP_LOSC_ENABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define CMU_LP_LOSC_DISABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define CMU_LP_HRC_ENABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define CMU_LP_HRC_DISABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define CMU_LP_HOSC_ENABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define CMU_LP_HOSC_DISABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
/**
* @}
*/
@ -133,214 +133,212 @@ extern "C" {
/**
* @brief CMU state structure definition
*/
typedef enum
{
CMU_CLOCK_HRC = 0x1, /**< HRC */
CMU_CLOCK_LRC = 0x2, /**< LRC */
CMU_CLOCK_LOSC = 0x3, /**< LOSC */
CMU_CLOCK_PLL1 = 0x4, /**< PLL1 */
CMU_CLOCK_HOSC = 0x5, /**< HOSC */
typedef enum {
CMU_CLOCK_HRC = 0x1U, /**< HRC */
CMU_CLOCK_LRC = 0x2U, /**< LRC */
CMU_CLOCK_LOSC = 0x3U, /**< LOSC */
CMU_CLOCK_PLL1 = 0x4U, /**< PLL1 */
CMU_CLOCK_HOSC = 0x5U, /**< HOSC */
} cmu_clock_t;
/**
* @brief PLL1 output clock
*/
typedef enum
{
CMU_PLL1_OUTPUT_32M = 0x0, /**< x8 (32MHz) */
CMU_PLL1_OUTPUT_48M = 0x1, /**< x12 (48MHz) */
typedef enum {
CMU_PLL1_OUTPUT_32M = 0x0U, /**< x8 (32MHz) */
CMU_PLL1_OUTPUT_48M = 0x1U, /**< x12 (48MHz) */
} cmu_pll1_output_t;
/**
* @brief PLL1 referance clock
*/
typedef enum
{
CMU_PLL1_INPUT_HRC_6 = 0x0, /**< HRC / 6 */
CMU_PLL1_INPUT_PLL2 = 0x1, /**< PLL2 */
CMU_PLL1_INPUT_HOSC = 0x2, /**< HOSC / 1 */
CMU_PLL1_INPUT_HOSC_2 = 0x3, /**< HOSC / 2 */
CMU_PLL1_INPUT_HOSC_3 = 0x4, /**< HOSC / 3 */
CMU_PLL1_INPUT_HOSC_4 = 0x5, /**< HOSC / 4 */
CMU_PLL1_INPUT_HOSC_5 = 0x6, /**< HOSC / 5 */
CMU_PLL1_INPUT_HOSC_6 = 0x7, /**< HOSC / 6 */
typedef enum {
CMU_PLL1_INPUT_HRC_6 = 0x0U, /**< HRC / 6 */
CMU_PLL1_INPUT_PLL2 = 0x1U, /**< PLL2 */
CMU_PLL1_INPUT_HOSC = 0x2U, /**< HOSC / 1 */
CMU_PLL1_INPUT_HOSC_2 = 0x3U, /**< HOSC / 2 */
CMU_PLL1_INPUT_HOSC_3 = 0x4U, /**< HOSC / 3 */
CMU_PLL1_INPUT_HOSC_4 = 0x5U, /**< HOSC / 4 */
CMU_PLL1_INPUT_HOSC_5 = 0x6U, /**< HOSC / 5 */
CMU_PLL1_INPUT_HOSC_6 = 0x7U, /**< HOSC / 6 */
} cmu_pll1_input_t;
/**
* @brief HOSC range
*/
typedef enum
{
CMU_HOSC_2M = 0x0,
CMU_HOSC_4M = 0x1,
CMU_HOSC_8M = 0x2,
CMU_HOSC_16M = 0x3,
CMU_HOSC_24M = 0x4,
typedef enum {
CMU_HOSC_2M = 0x0U, /**< 0~2MHz */
CMU_HOSC_4M = 0x1U, /**< 2~4MHz */
CMU_HOSC_8M = 0x2U, /**< 4~8MHz */
CMU_HOSC_16M = 0x3U, /**< 8~16MHz */
CMU_HOSC_24M = 0x4U, /**< 16~24MHz */
} cmu_hosc_range_t;
/**
* @brief Auto-calibrate input
*/
typedef enum
{
CMU_AUTO_CALIB_INPUT_LOSE = 0x0,
CMU_AUTO_CALIB_INPUT_HOSE = 0x1,
typedef enum {
CMU_AUTO_CALIB_INPUT_LOSE = 0x0U, /**< LOSC */
CMU_AUTO_CALIB_INPUT_HOSE = 0x1U, /**< HOSC */
} cmu_auto_calib_input_t;
/**
* @brief Auto-calibrate output
*/
typedef enum
{
CMU_AUTO_CALIB_OUTPUT_24M = 0x0,
CMU_AUTO_CALIB_OUTPUT_2M = 0x1,
typedef enum {
CMU_AUTO_CALIB_OUTPUT_24M = 0x0U, /**< HOSC 24MHz */
CMU_AUTO_CALIB_OUTPUT_2M = 0x1U, /**< HOSC 2MHz */
} cmu_auto_calib_output_t;
/**
* @brief Safe clock source type
*/
typedef enum {
CMU_SAFE_CLK_HOSC = 0x0U, /**< HOSC */
CMU_SAFE_CLK_LOSC = 0x1U, /**< LOSC */
CMU_SAFE_CLK_PLL = 0x2U, /**< PLL */
} cmu_clock_safe_type_t;
/**
* @brief Frequency division select bit
*/
typedef enum
{
CMU_DIV_1 = 0x0, /**< Division by 1 */
CMU_DIV_2 = 0x1, /**< Division by 2 */
CMU_DIV_4 = 0x2, /**< Division by 4 */
CMU_DIV_8 = 0x3, /**< Division by 8 */
CMU_DIV_16 = 0x4, /**< Division by 16 */
CMU_DIV_32 = 0x5, /**< Division by 32 */
CMU_DIV_64 = 0x6, /**< Division by 64 */
CMU_DIV_128 = 0x7, /**< Division by 128 */
CMU_DIV_256 = 0x8, /**< Division by 256 */
CMU_DIV_512 = 0x9, /**< Division by 512 */
CMU_DIV_1024 = 0xA, /**< Division by 1024 */
CMU_DIV_2048 = 0xB, /**< Division by 2048 */
CMU_DIV_4096 = 0xC, /**< Division by 4096 */
typedef enum {
CMU_DIV_1 = 0x0U, /**< Division by 1 */
CMU_DIV_2 = 0x1U, /**< Division by 2 */
CMU_DIV_4 = 0x2U, /**< Division by 4 */
CMU_DIV_8 = 0x3U, /**< Division by 8 */
CMU_DIV_16 = 0x4U, /**< Division by 16 */
CMU_DIV_32 = 0x5U, /**< Division by 32 */
CMU_DIV_64 = 0x6U, /**< Division by 64 */
CMU_DIV_128 = 0x7U, /**< Division by 128 */
CMU_DIV_256 = 0x8U, /**< Division by 256 */
CMU_DIV_512 = 0x9U, /**< Division by 512 */
CMU_DIV_1024 = 0xAU, /**< Division by 1024 */
CMU_DIV_2048 = 0xBU, /**< Division by 2048 */
CMU_DIV_4096 = 0xCU, /**< Division by 4096 */
} cmu_div_t;
/**
* @brief Bus type
*/
typedef enum
{
CMU_HCLK_1 = 0x0, /**< AHB1 bus */
CMU_SYS = 0x1, /**< SYS bus */
CMU_PCLK_1 = 0x2, /**< APB1 bus */
CMU_PCLK_2 = 0x3, /**< APB2 bus */
typedef enum {
CMU_HCLK_1 = 0x0U, /**< AHB1 bus */
CMU_SYS = 0x1U, /**< SYS bus */
CMU_PCLK_1 = 0x2U, /**< APB1 bus */
CMU_PCLK_2 = 0x3U, /**< APB2 bus */
} cmu_bus_t;
/**
* @brief Output high clock select
*/
typedef enum
{
CMU_OUTPUT_HIGH_SEL_HOSC = 0x0, /**< Select HOSC */
CMU_OUTPUT_HIGH_SEL_LOSC = 0x1, /**< Select LOSC */
CMU_OUTPUT_HIGH_SEL_HRC = 0x2, /**< Select HRC */
CMU_OUTPUT_HIGH_SEL_LRC = 0x3, /**< Select LRC */
CMU_OUTPUT_HIGH_SEL_HOSM = 0x4, /**< Select HOSM */
CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5, /**< Select PLL1 */
CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6, /**< Select PLL2 */
CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7, /**< Select SYSCLK */
typedef enum {
CMU_OUTPUT_HIGH_SEL_HOSC = 0x0U, /**< Select HOSC */
CMU_OUTPUT_HIGH_SEL_LOSC = 0x1U, /**< Select LOSC */
CMU_OUTPUT_HIGH_SEL_HRC = 0x2U, /**< Select HRC */
CMU_OUTPUT_HIGH_SEL_LRC = 0x3U, /**< Select LRC */
CMU_OUTPUT_HIGH_SEL_HOSM = 0x4U, /**< Select HOSM */
CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5U, /**< Select PLL1 */
CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6U, /**< Select PLL2 */
CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7U, /**< Select SYSCLK */
} cmu_output_high_sel_t;
/**
* @brief Output frequency division
*/
typedef enum
{
CMU_OUTPUT_DIV_1 = 0x0, /**< Division by 1 */
CMU_OUTPUT_DIV_2 = 0x1, /**< Division by 2 */
CMU_OUTPUT_DIV_4 = 0x2, /**< Division by 4 */
CMU_OUTPUT_DIV_8 = 0x3, /**< Division by 8 */
CMU_OUTPUT_DIV_16 = 0x4, /**< Division by 16 */
CMU_OUTPUT_DIV_32 = 0x5, /**< Division by 32 */
CMU_OUTPUT_DIV_64 = 0x6, /**< Division by 64 */
CMU_OUTPUT_DIV_128 = 0x7, /**< Division by 128 */
typedef enum {
CMU_OUTPUT_DIV_1 = 0x0U, /**< Division by 1 */
CMU_OUTPUT_DIV_2 = 0x1U, /**< Division by 2 */
CMU_OUTPUT_DIV_4 = 0x2U, /**< Division by 4 */
CMU_OUTPUT_DIV_8 = 0x3U, /**< Division by 8 */
CMU_OUTPUT_DIV_16 = 0x4U, /**< Division by 16 */
CMU_OUTPUT_DIV_32 = 0x5U, /**< Division by 32 */
CMU_OUTPUT_DIV_64 = 0x6U, /**< Division by 64 */
CMU_OUTPUT_DIV_128 = 0x7U, /**< Division by 128 */
} cmu_output_high_div_t;
/**
* @brief Output low clock select
*/
typedef enum
{
CMU_OUTPUT_LOW_SEL_LOSC = 0x0, /**< Select LOSC */
CMU_OUTPUT_LOW_SEL_LRC = 0x1, /**< Select LRC */
CMU_OUTPUT_LOW_SEL_LOSM = 0x2, /**< Select LOSM */
CMU_OUTPUT_LOW_SEL_BUZZ = 0x3, /**< Select BUZZ */
CMU_OUTPUT_LOW_SEL_ULRC = 0x4, /**< Select ULRC */
typedef enum {
CMU_OUTPUT_LOW_SEL_LOSC = 0x0U, /**< Select LOSC */
CMU_OUTPUT_LOW_SEL_LRC = 0x1U, /**< Select LRC */
CMU_OUTPUT_LOW_SEL_LOSM = 0x2U, /**< Select LOSM */
CMU_OUTPUT_LOW_SEL_BUZZ = 0x3U, /**< Select BUZZ */
CMU_OUTPUT_LOW_SEL_ULRC = 0x4U, /**< Select ULRC */
} cmu_output_low_sel_t;
/**
* @brief BUZZ frequency division
*/
typedef enum
{
CMU_BUZZ_DIV_2 = 0x0, /**< Division by 2 */
CMU_BUZZ_DIV_4 = 0x1, /**< Division by 4 */
CMU_BUZZ_DIV_8 = 0x2, /**< Division by 8 */
CMU_BUZZ_DIV_16 = 0x3, /**< Division by 16 */
CMU_BUZZ_DIV_32 = 0x4, /**< Division by 32 */
CMU_BUZZ_DIV_64 = 0x5, /**< Division by 64 */
CMU_BUZZ_DIV_128 = 0x6, /**< Division by 128 */
CMU_BUZZ_DIV_256 = 0x7, /**< Division by 256 */
typedef enum {
CMU_BUZZ_DIV_2 = 0x0U, /**< Division by 2 */
CMU_BUZZ_DIV_4 = 0x1U, /**< Division by 4 */
CMU_BUZZ_DIV_8 = 0x2U, /**< Division by 8 */
CMU_BUZZ_DIV_16 = 0x3U, /**< Division by 16 */
CMU_BUZZ_DIV_32 = 0x4U, /**< Division by 32 */
CMU_BUZZ_DIV_64 = 0x5U, /**< Division by 64 */
CMU_BUZZ_DIV_128 = 0x6U, /**< Division by 128 */
CMU_BUZZ_DIV_256 = 0x7U, /**< Division by 256 */
} cmu_buzz_div_t;
/**
* @brief Low power peripheral clock select
*/
typedef enum
{
CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0, /**< Select PCLK2 */
CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1, /**< Select PLL1 */
CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2, /**< Select PLL2 */
CMU_LP_PERH_CLOCK_SEL_HRC = 0x3, /**< Select HRC */
CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4, /**< Select HOSC */
CMU_LP_PERH_CLOCK_SEL_LRC = 0x5, /**< Select LRC */
CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6, /**< Select LOSC */
CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7, /**< Select ULRC */
CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8, /**< Select HRC down to 1MHz */
CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9, /**< Select HOSC down to 1MHz */
CMU_LP_PERH_CLOCK_SEL_LOSM = 0xA, /**< Select LOSM */
CMU_LP_PERH_CLOCK_SEL_HOSM = 0xB, /**< Select HOSM */
typedef enum {
CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0U, /**< Select PCLK2 */
CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1U, /**< Select PLL1 */
CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2U, /**< Select PLL2 */
CMU_LP_PERH_CLOCK_SEL_HRC = 0x3U, /**< Select HRC */
CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4U, /**< Select HOSC */
CMU_LP_PERH_CLOCK_SEL_LRC = 0x5U, /**< Select LRC */
CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6U, /**< Select LOSC */
CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7U, /**< Select ULRC */
CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8U, /**< Select HRC down to 1MHz */
CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9U, /**< Select HOSC down to 1MHz */
CMU_LP_PERH_CLOCK_SEL_LOSM = 0xAU, /**< Select LOSM */
CMU_LP_PERH_CLOCK_SEL_HOSM = 0xBU, /**< Select HOSM */
} cmu_lp_perh_clock_sel_t;
/**
* @brief LCD clock select
*/
typedef enum
{
CMU_LCD_SEL_LOSM = 0x0, /**< Select LOSM */
CMU_LCD_SEL_LOSC = 0x1, /**< Select LOSC */
CMU_LCD_SEL_LRC = 0x2, /**< Select LRC */
CMU_LCD_SEL_ULRC = 0x3, /**< Select ULRC */
CMU_LCD_SEL_HRC_1M = 0x4, /**< Select HRC down to 1MHz */
CMU_LCD_SEL_HOSC_1M = 0x5, /**< Select HOSC down to 1MHz */
typedef enum {
CMU_LCD_SEL_LOSM = 0x0U, /**< Select LOSM */
CMU_LCD_SEL_LOSC = 0x1U, /**< Select LOSC */
CMU_LCD_SEL_LRC = 0x2U, /**< Select LRC */
CMU_LCD_SEL_ULRC = 0x3U, /**< Select ULRC */
CMU_LCD_SEL_HRC_1M = 0x4U, /**< Select HRC down to 1MHz */
CMU_LCD_SEL_HOSC_1M = 0x5U, /**< Select HOSC down to 1MHz */
} cmu_lcd_clock_sel_t;
/**
* @brief Peripheral clock enable/disable
* @note ES32F065x:
* AD16C4T0--TIMER0
* GP16C4T0--TIMER6
* GP16C2T0--TIMER2
* GP16C2T1--TIMER3
* BS16T0----TIMER1
* BS16T1----TIMER4
* BS16T2----TIMER5
* BS16T3----TIMER7
*
* ES32F033x:
* ES32F093x:
* GP16C4T0--TIMER0
* GP16C4T1--TIMER6
* GP16C2T0--TIMER2
* GP16C2T1--TIMER3
* BS16T0----TIMER1
* BS16T1----TIMER4
* BS16T2----TIMER5
* BS16T3----TIMER7
* @verbatim
In this module, for the convenience of code maintenance,
TIMERx is used to indicate the sequence of the timer peripheral.
Different product series TIMERx represent different meanings:
1. For ES32F065x series:
TIMER0 ----> AD16C4T0
TIMER1 ----> BS16T0
TIMER2 ----> GP16C2T0
TIMER3 ----> GP16C2T1
TIMER4 ----> BS16T1
TIMER5 ----> BS16T2
TIMER6 ----> GP16C4T0
TIMER7 ----> BS16T3
2. For ES32F033x/ES32F093x series:
TIMER0 ----> GP16C4T0
TIMER1 ----> BS16T0
TIMER2 ----> GP16C2T0
TIMER3 ----> GP16C2T1
TIMER4 ----> BS16T1
TIMER5 ----> BS16T2
TIMER6 ----> GP16C4T1
TIMER7 ----> BS16T3
@endverbatim
*/
typedef enum
{
typedef enum {
CMU_PERH_GPIO = (1U << 0), /**< GPIO */
CMU_PERH_CRC = (1U << 1), /**< CRC */
CMU_PERH_CALC = (1U << 2), /**< CALC */
@ -381,7 +379,6 @@ typedef enum
CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */
CMU_PERH_TSENSE = (1U << 16) | (1U << 28), /**< TSENSE */
CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */
CMU_PERH_BKRPAM = (1U << 18) | (1U << 28), /**< BKPRAM */
CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */
CMU_PERH_ALL = (0x7FFFFFFF), /**< ALL */
} cmu_perh_t;
@ -389,20 +386,18 @@ typedef enum
/**
* @brief CMU interrupt type
*/
typedef enum
{
CMU_LOSC_STOP = 0x0, /**< LOSC STOP INTERRUPT */
CMU_HOSC_STOP = 0x1, /**< HOSC STOP INTERRUPT */
CMU_PLL1_UNLOCK = 0x2, /**< PLL1 UNLOCK INTERRUPT */
CMU_LOSC_START = 0x3, /**< LOSC START INTERRUPT */
CMU_HOSC_START = 0x4, /**< HOSC START INTERRUPT */
typedef enum {
CMU_LOSC_STOP = 0x0U, /**< LOSC STOP INTERRUPT */
CMU_HOSC_STOP = 0x1U, /**< HOSC STOP INTERRUPT */
CMU_PLL1_UNLOCK = 0x2U, /**< PLL1 UNLOCK INTERRUPT */
CMU_LOSC_START = 0x3U, /**< LOSC START INTERRUPT */
CMU_HOSC_START = 0x4U, /**< HOSC START INTERRUPT */
} cmu_security_t;
/**
* @brief CMU clock state type
*/
typedef enum
{
typedef enum {
CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */
CMU_CLOCK_STATE_LOSCACT = (1U << 1), /**< LOSC active */
CMU_CLOCK_STATE_HRCACT = (1U << 2), /**< HRC active */
@ -485,6 +480,9 @@ typedef enum
((x) == CMU_AUTO_CALIB_INPUT_HOSE))
#define IS_CMU_AUTO_CALIB_OUTPUT(x) (((x) == CMU_AUTO_CALIB_OUTPUT_24M) || \
((x) == CMU_AUTO_CALIB_OUTPUT_2M))
#define IS_CMU_SAFE_CLOCK_TYPE(x) (((x) == CMU_SAFE_CLK_HOSC) || \
((x) == CMU_SAFE_CLK_LOSC) || \
((x) == CMU_SAFE_CLK_PLL))
#define IS_CMU_BUZZ_DIV(x) (((x) == CMU_BUZZ_DIV_2) || \
((x) == CMU_BUZZ_DIV_4) || \
((x) == CMU_BUZZ_DIV_8) || \
@ -551,7 +549,6 @@ typedef enum
((x) == CMU_PERH_RTC) || \
((x) == CMU_PERH_TSENSE) || \
((x) == CMU_PERH_BKPC) || \
((x) == CMU_PERH_BKRPAM ) || \
((x) == CMU_PERH_DBGC) || \
((x) == CMU_PERH_ALL))
#define IS_CMU_CLOCK_STATE(x) (((x) == CMU_CLOCK_STATE_HOSCACT) || \
@ -605,6 +602,7 @@ uint32_t ald_cmu_get_pclk2_clock(void);
void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status);
void ald_cmu_losc_safe_config(type_func_t status);
void ald_cmu_pll_safe_config(type_func_t status);
uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type);
flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr);
void ald_cmu_irq_handler(void);
void ald_cmu_irq_cbk(cmu_security_t se);

48
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crc.h
View File

@ -18,7 +18,7 @@
#define __ALD_CRC_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@ -39,50 +39,45 @@ extern "C" {
/**
* @brief CRC mode
*/
typedef enum
{
CRC_MODE_CCITT = 0, /**< Ccitt */
CRC_MODE_8 = 1, /**< Crc8 */
CRC_MODE_16 = 2, /**< Crc16 */
CRC_MODE_32 = 3, /**< Crc32 */
typedef enum {
CRC_MODE_CCITT = 0U, /**< Ccitt */
CRC_MODE_8 = 1U, /**< Crc8 */
CRC_MODE_16 = 2U, /**< Crc16 */
CRC_MODE_32 = 3U, /**< Crc32 */
} crc_mode_t;
/**
* @brief CRC input length
*/
typedef enum
{
CRC_LEN_AUTO = 0, /**< Auto */
CRC_DATASIZE_8 = 1, /**< Byte */
CRC_DATASIZE_16 = 2, /**< Half word */
CRC_DATASIZE_32 = 3, /**< Word */
typedef enum {
CRC_LEN_AUTO = 0U, /**< Auto */
CRC_DATASIZE_8 = 1U, /**< Byte */
CRC_DATASIZE_16 = 2U, /**< Half word */
CRC_DATASIZE_32 = 3U, /**< Word */
} crc_datasize_t;
/**
* @brief CRC whether write error or no
*/
typedef enum
{
CRC_WERR_NO = 0, /**< No error */
CRC_WERR_ERR = 1, /**< Error */
typedef enum {
CRC_WERR_NO = 0U, /**< No error */
CRC_WERR_ERR = 1U, /**< Error */
} crc_werr_t;
/**
* @brief CRC state structures definition
*/
typedef enum
{
CRC_STATE_RESET = 0x0, /**< Peripheral is not initialized */
CRC_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */
CRC_STATE_BUSY = 0x2, /**< An internal process is ongoing */
CRC_STATE_ERROR = 0x4, /**< Error */
typedef enum {
CRC_STATE_RESET = 0x0U, /**< Peripheral is not initialized */
CRC_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */
CRC_STATE_BUSY = 0x2U, /**< An internal process is ongoing */
CRC_STATE_ERROR = 0x4U, /**< Error */
} crc_state_t;
/**
* @brief CRC init structure definition
*/
typedef struct
{
typedef struct {
crc_mode_t mode; /**< CRC mode */
type_func_t data_rev; /**< CRC data reverse or no */
type_func_t data_inv; /**< CRC data inverse or no */
@ -94,8 +89,7 @@ typedef struct
/**
* @brief CRC Handle Structure definition
*/
typedef struct crc_handle_s
{
typedef struct crc_handle_s {
CRC_TypeDef *perh; /**< Register base address */
crc_init_t init; /**< CRC required parameters */
uint8_t *cal_buf; /**< The pointer of preparing buffer */

71
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crypt.h
View File

@ -18,7 +18,7 @@
#define __ALD_CRYPT_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@ -39,77 +39,69 @@ extern "C" {
/**
* @brief CRYPT encrypt or decrypt select
*/
typedef enum
{
CRYPT_DECRYPT = 0, /**< Decrypt */
CRYPT_ENCRYPT = 1, /**< Encrypt */
typedef enum {
CRYPT_DECRYPT = 0U, /**< Decrypt */
CRYPT_ENCRYPT = 1U, /**< Encrypt */
} crypt_encs_t;
/**
* @brief CRYPT mode select
*/
typedef enum
{
CRYPT_MODE_ECB = 0, /**< ECB */
CRYPT_MODE_CBC = 1, /**< CBC */
CRYPT_MODE_CTR = 2, /**< CTR */
typedef enum {
CRYPT_MODE_ECB = 0U, /**< ECB */
CRYPT_MODE_CBC = 1U, /**< CBC */
CRYPT_MODE_CTR = 2U, /**< CTR */
} crypt_mode_t;
/**
* @brief CRYPT data type
*/
typedef enum
{
CRYPT_DATA_CHANGE_NO = 0, /**< No exchange */
CRYPT_DATA_CHANGE_16 = 1, /**< 16bit exchange */
CRYPT_DATA_CHANGE_8 = 2, /**< 8bit exchange */
CRYPT_DATA_CHANGE_1 = 3, /**< 1bit exchange */
typedef enum {
CRYPT_DATA_CHANGE_NO = 0U, /**< No exchange */
CRYPT_DATA_CHANGE_16 = 1U, /**< 16bit exchange */
CRYPT_DATA_CHANGE_8 = 2U, /**< 8bit exchange */
CRYPT_DATA_CHANGE_1 = 3U, /**< 1bit exchange */
} crypt_datatype_t;
/**
* @brief CRYPT interrupt
*/
typedef enum
{
CRYPT_IT_IT = 0x80, /**< Interrupt */
typedef enum {
CRYPT_IT_IT = 0x80U, /**< Interrupt */
} crypt_it_t;
/**
* @brief CRYPT interrupt flag
*/
typedef enum
{
CRYPT_FLAG_AESIF = 0x1, /**< Aes flag */
CRYPT_FLAG_DONE = 0x100, /**< Complete flag */
typedef enum {
CRYPT_FLAG_AESIF = 0x1U, /**< Aes flag */
CRYPT_FLAG_DONE = 0x100U, /**< Complete flag */
} crypt_flag_t;
/**
* @brief CRYPT state structures definition
*/
typedef enum
{
CRYPT_STATE_RESET = 0x0, /**< Peripheral is not initialized */
CRYPT_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */
CRYPT_STATE_BUSY = 0x2, /**< An internal process is ongoing */
CRYPT_STATE_ERROR = 0x4, /**< Error */
typedef enum {
CRYPT_STATE_RESET = 0x0U, /**< Peripheral is not initialized */
CRYPT_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */
CRYPT_STATE_BUSY = 0x2U, /**< An internal process is ongoing */
CRYPT_STATE_ERROR = 0x4U, /**< Error */
} crypt_state_t;
/**
* @brief CRYPT data type
*/
typedef enum
{
DATA_32_BIT = 0, /**< 32 bit data,don't swap */
DATA_16_BIT = 1, /**< 16 bit data,swap */
DATA_8_BIT = 2, /**< 8 bit data,swap */
DATA_1_BIT = 3, /**< 1 bit data, swap */
typedef enum {
DATA_32_BIT = 0U, /**< 32 bit data,don't swap */
DATA_16_BIT = 1U, /**< 16 bit data,swap */
DATA_8_BIT = 2U, /**< 8 bit data,swap */
DATA_1_BIT = 3U, /**< 1 bit data, swap */
} crypt_data_t;
/**
* @brief CRYPT init structure definition
*/
typedef struct
{
typedef struct {
crypt_mode_t mode; /**< Crypt mode */
crypt_data_t type; /**< Data type select */
} crypt_init_t;
@ -117,8 +109,7 @@ typedef struct
/**
* @brief CRYPT Handle Structure definition
*/
typedef struct crypt_handle_s
{
typedef struct crypt_handle_s {
CRYPT_TypeDef *perh; /**< Register base address */
crypt_init_t init; /**< CRYPT required parameters */
#ifdef ALD_DMA
@ -148,7 +139,7 @@ typedef struct crypt_handle_s
*/
#define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK))
#define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
#define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
#define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))

52
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dbgc.h
View File

@ -18,7 +18,7 @@
#define __ALD_DBGC_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@ -41,34 +41,32 @@ extern "C" {
/**
* @brief Debug mode select
*/
typedef enum
{
DEBC_MODE_SLEEP = (1u << 0), /**< Sleep mode */
DEBC_MODE_STOP1 = (1u << 1), /**< STOP1 mode */
DEBC_MODE_STOP2 = (1u << 2), /**< STOP2 mode */
DEBC_MODE_STANDBY = (1u << 3), /**< Standby mode */
typedef enum {
DEBC_MODE_SLEEP = (1U << 0), /**< Sleep mode */
DEBC_MODE_STOP1 = (1U << 1), /**< STOP1 mode */
DEBC_MODE_STOP2 = (1U << 2), /**< STOP2 mode */
DEBC_MODE_STANDBY = (1U << 3), /**< Standby mode */
} dbgc_mode_t;
/**
* @brief Debug peripheral select
*/
typedef enum
{
DEBC_PERH_TIMER0 = (1u << 0), /**< AD16C4T0 */
DEBC_PERH_TIMER1 = (1u << 1), /**< BS16T0 */
DEBC_PERH_TIMER2 = (1u << 2), /**< GP16C2T0 */
DEBC_PERH_TIMER3 = (1u << 3), /**< GP16C2T1 */
DEBC_PERH_TIMER4 = (1u << 4), /**< BS16T1 */
DEBC_PERH_TIMER5 = (1u << 5), /**< BS16T2 */
DEBC_PERH_TIMER6 = (1u << 6), /**< GP16C4T0 */
DEBC_PERH_TIMER7 = (1u << 7), /**< BS16T3 */
DEBC_PERH_I2C0 = (1u << 8), /**< I2C0 SMBUS */
DEBC_PERH_I2C1 = (1u << 9), /**< I2C1 SMBUS */
DEBC_PERH_CAN = (1u << 12), /**< CAN */
DEBC_PERH_LPTIM0 = (1u << 0) | (1u << 16), /**< LPTIM0 */
DEBC_PERH_IWDT = (1u << 8) | (1u << 16), /**< IWDT */
DEBC_PERH_WWDT = (1u << 9) | (1u << 16), /**< WWDT */
DEBC_PERH_RTC = (1u << 10) | (1u << 16), /**< RTC */
typedef enum {
DEBC_PERH_TIMER0 = (1U << 0), /**< AD16C4T0 */
DEBC_PERH_TIMER1 = (1U << 1), /**< BS16T0 */
DEBC_PERH_TIMER2 = (1U << 2), /**< GP16C2T0 */
DEBC_PERH_TIMER3 = (1U << 3), /**< GP16C2T1 */
DEBC_PERH_TIMER4 = (1U << 4), /**< BS16T1 */
DEBC_PERH_TIMER5 = (1U << 5), /**< BS16T2 */
DEBC_PERH_TIMER6 = (1U << 6), /**< GP16C4T0 */
DEBC_PERH_TIMER7 = (1U << 7), /**< BS16T3 */
DEBC_PERH_I2C0 = (1U << 8), /**< I2C0 SMBUS */
DEBC_PERH_I2C1 = (1U << 9), /**< I2C1 SMBUS */
DEBC_PERH_CAN = (1U << 12), /**< CAN */
DEBC_PERH_LPTIM0 = (1U << 0) | (1U << 16), /**< LPTIM0 */
DEBC_PERH_IWDT = (1U << 8) | (1U << 16), /**< IWDT */
DEBC_PERH_WWDT = (1U << 9) | (1U << 16), /**< WWDT */
DEBC_PERH_RTC = (1U << 10) | (1U << 16), /**< RTC */
} dbgc_perh_t;
/**
* @}
@ -126,15 +124,13 @@ __INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
*/
__INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state)
{
if ((perh >> 16) & 0x1)
{
if ((perh >> 16) & 0x1) {
if (state)
SET_BIT(DBGC->APB2FZ, perh);
else
CLEAR_BIT(DBGC->APB2FZ, perh);
}
else
{
else {
if (state)
SET_BIT(DBGC->APB1FZ, perh);
else

368
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dma.h
View File

@ -18,7 +18,7 @@
#define __ALD_DMA_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@ -36,8 +36,8 @@ extern "C" {
* @defgroup DMA_Public_Macros DMA Public Macros
* @{
*/
#define DMA_CH_COUNT 6
#define DMA_ERR 31
#define DMA_CH_COUNT 6U
#define DMA_ERR 31U
/**
* @}
*/
@ -49,145 +49,145 @@ extern "C" {
/**
* @brief Input source to DMA channel
* @note ES32F065x:
* AD16C4T0--TIMER0
* GP16C4T0--TIMER6
* GP16C2T0--TIMER2
* GP16C2T1--TIMER3
* BS16T0----TIMER1
* BS16T1----TIMER4
* BS16T2----TIMER5
* BS16T3----TIMER7
*
* ES32F033x:
* ES32F093x:
* GP16C4T0--TIMER0
* GP16C4T1--TIMER6
* GP16C2T0--TIMER2
* GP16C2T1--TIMER3
* BS16T0----TIMER1
* BS16T1----TIMER4
* BS16T2----TIMER5
* BS16T3----TIMER7
* @verbatim
In this module, for the convenience of code maintenance,
TIMERx is used to indicate the sequence of the timer peripheral.
Different product series TIMERx represent different meanings:
1. For ES32F065x series:
TIMER0 ----> AD16C4T0
TIMER1 ----> BS16T0
TIMER2 ----> GP16C2T0
TIMER3 ----> GP16C2T1
TIMER4 ----> BS16T1
TIMER5 ----> BS16T2
TIMER6 ----> GP16C4T0
TIMER7 ----> BS16T3
2. For ES32F033x/ES32F093x series:
TIMER0 ----> GP16C4T0
TIMER1 ----> BS16T0
TIMER2 ----> GP16C2T0
TIMER3 ----> GP16C2T1
TIMER4 ----> BS16T1
TIMER5 ----> BS16T2
TIMER6 ----> GP16C4T1
TIMER7 ----> BS16T3
@endverbatim
*/
typedef enum
{
DMA_MSEL_NONE = 0x0, /**< NONE */
DMA_MSEL_GPIO = 0x1, /**< GPIO */
DMA_MSEL_CRYPT = 0x2, /**< CRYPT */
DMA_MSEL_ACMP = 0x3, /**< ACMP */
DMA_MSEL_DAC0 = 0x4, /**< DAC0 */
DMA_MSEL_ADC0 = 0x6, /**< ADC0 */
DMA_MSEL_CRC = 0x7, /**< CRC */
DMA_MSEL_UART0 = 0x8, /**< UART0 */
DMA_MSEL_UART1 = 0x9, /**< UART1 */
DMA_MSEL_UART2 = 0xA, /**< UART2 */
DMA_MSEL_UART3 = 0xB, /**< UART3 */
DMA_MSEL_USART0 = 0xC, /**< USART0 */
DMA_MSEL_USART1 = 0xD, /**< USART1 */
DMA_MSEL_SPI0 = 0xE, /**< SPI0 */
DMA_MSEL_SPI1 = 0xF, /**< SPI1 */
DMA_MSEL_I2C0 = 0x10, /**< I2C0 */
DMA_MSEL_I2C1 = 0x11, /**< I2C1 */
DMA_MSEL_TIMER0 = 0x12, /**< TIMER0 */
DMA_MSEL_TIMER1 = 0x13, /**< TIMER1 */
DMA_MSEL_TIMER2 = 0x14, /**< TIMER2 */
DMA_MSEL_TIMER3 = 0x15, /**< TIMER3 */
DMA_MSEL_RTC = 0x16, /**< RTC */
DMA_MSEL_LPTIM0 = 0x17, /**< LPTIM0 */
DMA_MSEL_LPUART0 = 0x18, /**< LPUART0 */
DMA_MSEL_DMA = 0x19, /**< DMA */
DMA_MSEL_SPI2 = 0x1A, /**< SPI2 */
DMA_MSEL_TIMER4 = 0x1B, /**< TIMER4 */
DMA_MSEL_TIMER5 = 0x1C, /**< TIMER5 */
DMA_MSEL_TIMER6 = 0x1D, /**< TIMER6 */
DMA_MSEL_TIMER7 = 0x1E, /**< TIMER7 */
DMA_MSEL_ADC1 = 0x1F, /**< ADC1 */
DMA_MSEL_PIS = 0x20, /**< PIS */
DMA_MSEL_TRNG = 0x21, /**< TRNG */
typedef enum {
DMA_MSEL_NONE = 0x0U, /**< NONE */
DMA_MSEL_GPIO = 0x1U, /**< GPIO */
DMA_MSEL_CRYPT = 0x2U, /**< CRYPT */
DMA_MSEL_ACMP = 0x3U, /**< ACMP */
DMA_MSEL_DAC0 = 0x4U, /**< DAC0 */
DMA_MSEL_ADC0 = 0x6U, /**< ADC0 */
DMA_MSEL_CRC = 0x7U, /**< CRC */
DMA_MSEL_UART0 = 0x8U, /**< UART0 */
DMA_MSEL_UART1 = 0x9U, /**< UART1 */
DMA_MSEL_UART2 = 0xAU, /**< UART2 */
DMA_MSEL_UART3 = 0xBU, /**< UART3 */
DMA_MSEL_USART0 = 0xCU, /**< USART0 */
DMA_MSEL_USART1 = 0xDU, /**< USART1 */
DMA_MSEL_SPI0 = 0xEU, /**< SPI0 */
DMA_MSEL_SPI1 = 0xFU, /**< SPI1 */
DMA_MSEL_I2C0 = 0x10U, /**< I2C0 */
DMA_MSEL_I2C1 = 0x11U, /**< I2C1 */
DMA_MSEL_TIMER0 = 0x12U, /**< TIMER0 */
DMA_MSEL_TIMER1 = 0x13U, /**< TIMER1 */
DMA_MSEL_TIMER2 = 0x14U, /**< TIMER2 */
DMA_MSEL_TIMER3 = 0x15U, /**< TIMER3 */
DMA_MSEL_RTC = 0x16U, /**< RTC */
DMA_MSEL_LPTIM0 = 0x17U, /**< LPTIM0 */
DMA_MSEL_LPUART0 = 0x18U, /**< LPUART0 */
DMA_MSEL_DMA = 0x19U, /**< DMA */
DMA_MSEL_SPI2 = 0x1AU, /**< SPI2 */
DMA_MSEL_TIMER4 = 0x1BU, /**< TIMER4 */
DMA_MSEL_TIMER5 = 0x1CU, /**< TIMER5 */
DMA_MSEL_TIMER6 = 0x1DU, /**< TIMER6 */
DMA_MSEL_TIMER7 = 0x1EU, /**< TIMER7 */
DMA_MSEL_ADC1 = 0x1FU, /**< ADC1 */
DMA_MSEL_PIS = 0x20U, /**< PIS */
DMA_MSEL_TRNG = 0x21U, /**< TRNG */
} dma_msel_t;
/**
* @brief Input signal to DMA channel
*/
typedef enum
{
DMA_MSIGSEL_NONE = 0x0, /**< NONE */
DMA_MSIGSEL_EXTI_0 = 0x0, /**< External interrupt 0 */
DMA_MSIGSEL_EXTI_1 = 0x1, /**< External interrupt 1 */
DMA_MSIGSEL_EXTI_2 = 0x2, /**< External interrupt 2 */
DMA_MSIGSEL_EXTI_3 = 0x3, /**< External interrupt 3 */
DMA_MSIGSEL_EXTI_4 = 0x4, /**< External interrupt 4 */
DMA_MSIGSEL_EXTI_5 = 0x5, /**< External interrupt 5 */
DMA_MSIGSEL_EXTI_6 = 0x6, /**< External interrupt 6 */
DMA_MSIGSEL_EXTI_7 = 0x7, /**< External interrupt 7 */
DMA_MSIGSEL_EXTI_8 = 0x8, /**< External interrupt 8 */
DMA_MSIGSEL_EXTI_9 = 0x9, /**< External interrupt 9 */
DMA_MSIGSEL_EXTI_10 = 0xA, /**< External interrupt 10 */
DMA_MSIGSEL_EXTI_11 = 0xB, /**< External interrupt 11 */
DMA_MSIGSEL_EXTI_12 = 0xC, /**< External interrupt 12 */
DMA_MSIGSEL_EXTI_13 = 0xD, /**< External interrupt 13 */
DMA_MSIGSEL_EXTI_14 = 0xE, /**< External interrupt 14 */
DMA_MSIGSEL_EXTI_15 = 0xF, /**< External interrupt 15 */
DMA_MSIGSEL_CRYPT_WRITE = 0x0, /**< CRYPT write mode */
DMA_MSIGSEL_CRYPT_READ = 0x1, /**< CRYPT read mode */
DMA_MSIGSEL_CALC_WRITE = 0x0, /**< CALC write mode */
DMA_MSIGSEL_CALC_READ = 0x1, /**< CALC read mode */
DMA_MSIGSEL_DAC0_CH0 = 0x0, /**< DAC0 channel 0 complete */
DMA_MSIGSEL_DAC0_CH1 = 0x1, /**< DAC0 channel 1 complete */
DMA_MSIGSEL_ADC = 0x0, /**< ADC mode */
DMA_MSIGSEL_UART_TXEMPTY = 0x0, /**< UART transmit */
DMA_MSIGSEL_UART_RNR = 0x1, /**< UART receive */
DMA_MSIGSEL_USART_RNR = 0x0, /**< USART reveive */
DMA_MSIGSEL_USART_TXEMPTY = 0x1, /**< USART transmit */
DMA_MSIGSEL_SPI_RNR = 0x0, /**< SPI receive */
DMA_MSIGSEL_SPI_TXEMPTY = 0x1, /**< SPI transmit */
DMA_MSIGSEL_I2C_RNR = 0x0, /**< I2C receive */
DMA_MSIGSEL_I2C_TXEMPTY = 0x1, /**< I2C transmit */
DMA_MSIGSEL_TIMER_CH1 = 0x0, /**< TIM channal 1 */
DMA_MSIGSEL_TIMER_CH2 = 0x1, /**< TIM channal 2 */
DMA_MSIGSEL_TIMER_CH3 = 0x2, /**< TIM channal 3 */
DMA_MSIGSEL_TIMER_CH4 = 0x3, /**< TIM channal 4 */
DMA_MSIGSEL_TIMER_TRI = 0x4, /**< TIM trigger */
DMA_MSIGSEL_TIMER_COMP = 0x5, /**< TIM compare */
DMA_MSIGSEL_TIMER_UPDATE = 0x6, /**< TIM update */
DMA_MSIGSEL_LPUART_RNR = 0x0, /**< LPUART receive */
DMA_MSIGSEL_LPUART_TXEMPTY = 0x1, /**< LPUART transmit */
DMA_MSIGSEL_PIS_CH0 = 0x0, /**< PIS channal 0 */
DMA_MSIGSEL_PIS_CH1 = 0x1, /**< PIS channal 1 */
DMA_MSIGSEL_PIS_CH2 = 0x2, /**< PIS channal 2 */
DMA_MSIGSEL_PIS_CH3 = 0x3, /**< PIS channal 3 */
DMA_MSIGSEL_PIS_CH4 = 0x4, /**< PIS channal 4 */
DMA_MSIGSEL_PIS_CH5 = 0x5, /**< PIS channal 5 */
DMA_MSIGSEL_PIS_CH6 = 0x6, /**< PIS channal 6 */
DMA_MSIGSEL_PIS_CH7 = 0x7, /**< PIS channal 7 */
DMA_MSIGSEL_PIS_CH8 = 0x8, /**< PIS channal 8 */
DMA_MSIGSEL_PIS_CH9 = 0x9, /**< PIS channal 9 */
DMA_MSIGSEL_PIS_CH10 = 0xA, /**< PIS channal 10 */
DMA_MSIGSEL_PIS_CH11 = 0xB, /**< PIS channal 11 */
DMA_MSIGSEL_PIS_CH12 = 0xC, /**< PIS channal 12 */
DMA_MSIGSEL_PIS_CH13 = 0xD, /**< PIS channal 13 */
DMA_MSIGSEL_PIS_CH14 = 0xE, /**< PIS channal 14 */
DMA_MSIGSEL_PIS_CH15 = 0xF, /**< PIS channal 15 */
typedef enum {
DMA_MSIGSEL_NONE = 0x0U, /**< NONE */
DMA_MSIGSEL_EXTI_0 = 0x0U, /**< External interrupt 0 */
DMA_MSIGSEL_EXTI_1 = 0x1U, /**< External interrupt 1 */
DMA_MSIGSEL_EXTI_2 = 0x2U, /**< External interrupt 2 */
DMA_MSIGSEL_EXTI_3 = 0x3U, /**< External interrupt 3 */
DMA_MSIGSEL_EXTI_4 = 0x4U, /**< External interrupt 4 */
DMA_MSIGSEL_EXTI_5 = 0x5U, /**< External interrupt 5 */
DMA_MSIGSEL_EXTI_6 = 0x6U, /**< External interrupt 6 */
DMA_MSIGSEL_EXTI_7 = 0x7U, /**< External interrupt 7 */
DMA_MSIGSEL_EXTI_8 = 0x8U, /**< External interrupt 8 */
DMA_MSIGSEL_EXTI_9 = 0x9U, /**< External interrupt 9 */
DMA_MSIGSEL_EXTI_10 = 0xAU, /**< External interrupt 10 */
DMA_MSIGSEL_EXTI_11 = 0xBU, /**< External interrupt 11 */
DMA_MSIGSEL_EXTI_12 = 0xCU, /**< External interrupt 12 */
DMA_MSIGSEL_EXTI_13 = 0xDU, /**< External interrupt 13 */
DMA_MSIGSEL_EXTI_14 = 0xEU, /**< External interrupt 14 */
DMA_MSIGSEL_EXTI_15 = 0xFU, /**< External interrupt 15 */
DMA_MSIGSEL_CRYPT_WRITE = 0x0U, /**< CRYPT write mode */
DMA_MSIGSEL_CRYPT_READ = 0x1U, /**< CRYPT read mode */
DMA_MSIGSEL_CALC_WRITE = 0x0U, /**< CALC write mode */
DMA_MSIGSEL_CALC_READ = 0x1U, /**< CALC read mode */
DMA_MSIGSEL_DAC0_CH0 = 0x0U, /**< DAC0 channel 0 complete */
DMA_MSIGSEL_DAC0_CH1 = 0x1U, /**< DAC0 channel 1 complete */
DMA_MSIGSEL_ADC = 0x0U, /**< ADC mode */
DMA_MSIGSEL_UART_TXEMPTY = 0x0U, /**< UART transmit */
DMA_MSIGSEL_UART_RNR = 0x1U, /**< UART receive */
DMA_MSIGSEL_USART_RNR = 0x0U, /**< USART reveive */
DMA_MSIGSEL_USART_TXEMPTY = 0x1U, /**< USART transmit */
DMA_MSIGSEL_SPI_RNR = 0x0U, /**< SPI receive */
DMA_MSIGSEL_SPI_TXEMPTY = 0x1U, /**< SPI transmit */
DMA_MSIGSEL_I2C_RNR = 0x0U, /**< I2C receive */
DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, /**< I2C transmit */
DMA_MSIGSEL_TIMER_CH1 = 0x0U, /**< TIM channal 1 */
DMA_MSIGSEL_TIMER_CH2 = 0x1U, /**< TIM channal 2 */
DMA_MSIGSEL_TIMER_CH3 = 0x2U, /**< TIM channal 3 */
DMA_MSIGSEL_TIMER_CH4 = 0x3U, /**< TIM channal 4 */
DMA_MSIGSEL_TIMER_TRI = 0x4U, /**< TIM trigger */
DMA_MSIGSEL_TIMER_COMP = 0x5U, /**< TIM compare */
DMA_MSIGSEL_TIMER_UPDATE = 0x6U, /**< TIM update */
DMA_MSIGSEL_LPUART_RNR = 0x0U, /**< LPUART receive */
DMA_MSIGSEL_LPUART_TXEMPTY = 0x1U, /**< LPUART transmit */
DMA_MSIGSEL_PIS_CH0 = 0x0U, /**< PIS channal 0 */
DMA_MSIGSEL_PIS_CH1 = 0x1U, /**< PIS channal 1 */
DMA_MSIGSEL_PIS_CH2 = 0x2U, /**< PIS channal 2 */
DMA_MSIGSEL_PIS_CH3 = 0x3U, /**< PIS channal 3 */
DMA_MSIGSEL_PIS_CH4 = 0x4U, /**< PIS channal 4 */
DMA_MSIGSEL_PIS_CH5 = 0x5U, /**< PIS channal 5 */
DMA_MSIGSEL_PIS_CH6 = 0x6U, /**< PIS channal 6 */
DMA_MSIGSEL_PIS_CH7 = 0x7U, /**< PIS channal 7 */
DMA_MSIGSEL_PIS_CH8 = 0x8U, /**< PIS channal 8 */
DMA_MSIGSEL_PIS_CH9 = 0x9U, /**< PIS channal 9 */
DMA_MSIGSEL_PIS_CH10 = 0xAU, /**< PIS channal 10 */
DMA_MSIGSEL_PIS_CH11 = 0xBU, /**< PIS channal 11 */
DMA_MSIGSEL_PIS_CH12 = 0xCU, /**< PIS channal 12 */
DMA_MSIGSEL_PIS_CH13 = 0xDU, /**< PIS channal 13 */
DMA_MSIGSEL_PIS_CH14 = 0xEU, /**< PIS channal 14 */
DMA_MSIGSEL_PIS_CH15 = 0xFU, /**< PIS channal 15 */
} dma_msigsel_t;
/**
* @brief DMA Descriptor control type
*/
typedef union
{
struct
{
uint32_t cycle_ctrl : 3; /**< DMA operating mode @ref dma_cycle_ctrl_t */
uint32_t next_useburst : 1; /**< Uses the alternate data structure when complete a DMA cycle */
uint32_t n_minus_1 : 10; /**< Represent the total number of DMA transfers that DMA cycle contains. */
uint32_t R_power : 4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
uint32_t src_prot_ctrl : 3; /**< Control the state of HPROT when reads the source data. */
uint32_t dst_prot_ctrl : 3; /**< Control the state of HPROT when writes the destination data */
uint32_t src_size : 2; /**< Source data size @ref dma_data_size_t */
uint32_t src_inc : 2; /**< Control the source address increment. @ref dma_data_inc_t */
uint32_t dst_size : 2; /**< Destination data size. @ref dma_data_size_t */
uint32_t dst_inc : 2; /**< Destination address increment. @ref dma_data_inc_t */
typedef union {
struct {
uint32_t cycle_ctrl :3; /**< DMA operating mode @ref dma_cycle_ctrl_t */
uint32_t next_useburst :1; /**< Uses the alternate data structure when complete a DMA cycle */
uint32_t n_minus_1 :10; /**< Represent the total number of DMA transfers that DMA cycle contains. */
uint32_t R_power :4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
uint32_t src_prot_ctrl :3; /**< Control the state of HPROT when reads the source data. */
uint32_t dst_prot_ctrl :3; /**< Control the state of HPROT when writes the destination data */
uint32_t src_size :2; /**< Source data size @ref dma_data_size_t */
uint32_t src_inc :2; /**< Control the source address increment. @ref dma_data_inc_t */
uint32_t dst_size :2; /**< Destination data size. @ref dma_data_size_t */
uint32_t dst_inc :2; /**< Destination address increment. @ref dma_data_inc_t */
};
uint32_t word;
} dma_ctrl_t;
@ -195,8 +195,7 @@ typedef union
/**
* @brief Channel control data structure
*/
typedef struct
{
typedef struct {
void *src; /**< Source data end pointer */
void *dst; /**< Destination data end pointer */
dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */
@ -206,63 +205,60 @@ typedef struct
/**
* @brief data increment
*/
typedef enum
{
DMA_DATA_INC_BYTE = 0x0, /**< Address increment by byte */
DMA_DATA_INC_HALFWORD = 0x1, /**< Address increment by halfword */
DMA_DATA_INC_WORD = 0x2, /**< Address increment by word */
DMA_DATA_INC_NONE = 0x3, /**< No increment */
typedef enum {
DMA_DATA_INC_BYTE = 0x0U, /**< Address increment by byte */
DMA_DATA_INC_HALFWORD = 0x1U, /**< Address increment by halfword */
DMA_DATA_INC_WORD = 0x2U, /**< Address increment by word */
DMA_DATA_INC_NONE = 0x3U, /**< No increment */
} dma_data_inc_t;
/**
* @brief Data size
*/
typedef enum
{
DMA_DATA_SIZE_BYTE = 0x0, /**< Byte */
DMA_DATA_SIZE_HALFWORD = 0x1, /**< Halfword */
DMA_DATA_SIZE_WORD = 0x2, /**< Word */
typedef enum {
DMA_DATA_SIZE_BYTE = 0x0U, /**< Byte */
DMA_DATA_SIZE_HALFWORD = 0x1U, /**< Halfword */
DMA_DATA_SIZE_WORD = 0x2U, /**< Word */
} dma_data_size_t;
/**
* @brief The operating mode of the DMA cycle
*/
typedef enum
{
DMA_CYCLE_CTRL_NONE = 0x0, /**< Stop */
DMA_CYCLE_CTRL_BASIC = 0x1, /**< Basic */
DMA_CYCLE_CTRL_AUTO = 0x2, /**< Auto-request */
DMA_CYCLE_CTRL_PINGPONG = 0x3, /**< Ping-pong */
DMA_CYCLE_CTRL_MEM_SCATTER_GATHER = 0x4, /**< Memory scatter/gather */
DMA_CYCLE_CTRL_PER_SCATTER_GATHER = 0x6, /**< Peripheral scatter/gather */
typedef enum {
DMA_CYCLE_CTRL_NONE = 0x0U, /**< Stop */
DMA_CYCLE_CTRL_BASIC = 0x1U, /**< Basic */
DMA_CYCLE_CTRL_AUTO = 0x2U, /**< Auto-request */
DMA_CYCLE_CTRL_PINGPONG = 0x3U, /**< Ping-pong */
DMA_CYCLE_CTRL_MEM_SG_PRIMARY = 0x4U, /**< Memory scatter-gather using the primary structure */
DMA_CYCLE_CTRL_MEM_SG_ALTERNATE = 0x5U, /**< Memory scatter-gather using the alternate structure */
DMA_CYCLE_CTRL_PER_SG_PRIMARY = 0x6U, /**< Peripheral scatter-gather using the primary structure */
DMA_CYCLE_CTRL_PER_SG_ALTERNATE = 0x7U, /**< Peripheral scatter-gather using the alternate structure */
} dma_cycle_ctrl_t;
/**
* @brief Control how many DMA transfers can occur
* before the controller re-arbitrates
*/
typedef enum
{
DMA_R_POWER_1 = 0x0, /**< Arbitrates after each DMA transfer */
DMA_R_POWER_2 = 0x1, /**< Arbitrates after 2 DMA transfer */
DMA_R_POWER_4 = 0x2, /**< Arbitrates after 4 DMA transfer */
DMA_R_POWER_8 = 0x3, /**< Arbitrates after 8 DMA transfer */
DMA_R_POWER_16 = 0x4, /**< Arbitrates after 16 DMA transfer */
DMA_R_POWER_32 = 0x5, /**< Arbitrates after 32 DMA transfer */
DMA_R_POWER_64 = 0x6, /**< Arbitrates after 64 DMA transfer */
DMA_R_POWER_128 = 0x7, /**< Arbitrates after 128 DMA transfer */
DMA_R_POWER_256 = 0x8, /**< Arbitrates after 256 DMA transfer */
DMA_R_POWER_512 = 0x9, /**< Arbitrates after 512 DMA transfer */
DMA_R_POWER_1024 = 0xA, /**< Arbitrates after 1024 DMA transfer */
typedef enum {
DMA_R_POWER_1 = 0x0U, /**< Arbitrates after each DMA transfer */
DMA_R_POWER_2 = 0x1U, /**< Arbitrates after 2 DMA transfer */
DMA_R_POWER_4 = 0x2U, /**< Arbitrates after 4 DMA transfer */
DMA_R_POWER_8 = 0x3U, /**< Arbitrates after 8 DMA transfer */
DMA_R_POWER_16 = 0x4U, /**< Arbitrates after 16 DMA transfer */
DMA_R_POWER_32 = 0x5U, /**< Arbitrates after 32 DMA transfer */
DMA_R_POWER_64 = 0x6U, /**< Arbitrates after 64 DMA transfer */
DMA_R_POWER_128 = 0x7U, /**< Arbitrates after 128 DMA transfer */
DMA_R_POWER_256 = 0x8U, /**< Arbitrates after 256 DMA transfer */
DMA_R_POWER_512 = 0x9U, /**< Arbitrates after 512 DMA transfer */
DMA_R_POWER_1024 = 0xAU, /**< Arbitrates after 1024 DMA transfer */
} dma_arbiter_config_t;
/**
* @brief Callback function pointer and param
*/
typedef struct
{
typedef struct {
void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */
void (*err_cbk)(void *arg); /**< DMA occurs error callback */
void (*err_cbk)(void* arg); /**< DMA occurs error callback */
void *cplt_arg; /**< The parameter of cplt_cbk() */
void *err_arg; /**< The parameter of err_cbk() */
} dma_call_back_t;
@ -270,8 +266,7 @@ typedef struct
/**
* @brief DMA channal configure structure
*/
typedef struct
{
typedef struct {
void *src; /**< Source data begin pointer */
void *dst; /**< Destination data begin pointer */
uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */
@ -280,9 +275,9 @@ typedef struct
dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */
dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
type_func_t primary; /**< Use primary descriptor or alternate descriptor */
type_func_t burst; /**< Uses the alternate data structure when complete a DMA cycle */
type_func_t burst; /**< Enable/Disable the useburst setting for this channel */
type_func_t high_prio; /**< High priority or default priority */
type_func_t iterrupt; /**< Enable/disable interrupt */
type_func_t interrupt; /**< Enable/disable interrupt */
dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */
dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */
uint8_t channel; /**< Channel index */
@ -291,8 +286,7 @@ typedef struct
/**
* @brief DMA handle structure definition
*/
typedef struct
{
typedef struct {
DMA_TypeDef *perh; /**< DMA registers base address */
dma_config_t config; /**< Channel configure structure. @ref dma_config_t */
void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */
@ -300,6 +294,15 @@ typedef struct
void *cplt_arg; /**< The parameter of cplt_cbk() */
void *err_arg; /**< The parameter of err_cbk() */
} dma_handle_t;
/**
* @brief Descriptor complete state
*/
typedef enum {
DMA_DESCP_CPLT_PRI = 0x0U, /**< Primary descriptor has been completed */
DMA_DESCP_CPLT_ALT = 0x1U, /**< Alternate descriptor has been completed */
DMA_DESCP_CPLT_ALL = 0x2U, /**< Both primary and alternate descriptors have been completed */
} dma_descrp_cplt_t;
/**
* @}
*/
@ -321,8 +324,10 @@ typedef struct
((x) == DMA_CYCLE_CTRL_BASIC) || \
((x) == DMA_CYCLE_CTRL_AUTO) || \
((x) == DMA_CYCLE_CTRL_PINGPONG) || \
((x) == DMA_CYCLE_CTRL_MEM_SCATTER_GATHER) || \
((x) == DMA_CYCLE_CTRL_PER_SCATTER_GATHER))
((x) == DMA_CYCLE_CTRL_MEM_SG_PRIMARY) || \
((x) == DMA_CYCLE_CTRL_MEM_SG_ALTERNATE) || \
((x) == DMA_CYCLE_CTRL_PER_SG_PRIMARY) || \
((x) == DMA_CYCLE_CTRL_PER_SG_ALTERNATE))
#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \
((x) == DMA_R_POWER_2) || \
((x) == DMA_R_POWER_4) || \
@ -354,6 +359,7 @@ typedef struct
extern void ald_dma_reset(DMA_TypeDef *DMAx);
extern void ald_dma_init(DMA_TypeDef *DMAx);
extern void ald_dma_config_struct(dma_config_t *p);
extern void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory);
/**
* @}
*/
@ -371,6 +377,12 @@ extern void ald_dma_config_basic(dma_handle_t *hperh);
extern void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
extern void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel,
dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
extern void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config,
uint8_t first, void (*cbk)(void *arg));
extern void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc,
uint32_t nr, uint8_t channel, void (*cbk)(void *arg));
extern void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst,
dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
/**
* @}
*/
@ -384,7 +396,8 @@ extern void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_fu
extern it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel);
extern flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
extern void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
void ald_dma_irq_handler(void);
extern dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel);
extern void ald_dma_irq_handler(void);
/**
* @}
*/
@ -393,7 +406,6 @@ void ald_dma_irq_handler(void);
* @}
*/
/**
* @}
*/

38
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_flash.h
View File

@ -36,21 +36,21 @@ extern "C" {
* @{
*/
#define FLASH_REG_UNLOCK() \
do { \
do { \
if (op_cmd == OP_FLASH) { \
WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \
WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \
WRITE_REG(MSC->FLASHKEY, 0x8ACE0246U); \
WRITE_REG(MSC->FLASHKEY, 0x9BDF1357U); \
} \
else { \
WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \
WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \
WRITE_REG(MSC->INFOKEY, 0x7153BFD9U); \
WRITE_REG(MSC->INFOKEY, 0x0642CEA8U); \
} \
} while (0)
} while (0)
#define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define FLASH_BASE_ADDR 0x00000000
#define FLASH_BASE_ADDR 0x00000000U
#define FLASH_PAGE_SIZE 1024UL
#define FLASH_WORD_SIZE 8UL
#define FLASH_TOTAL_SIZE 256UL
@ -67,9 +67,9 @@ extern "C" {
#define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK))
#ifdef USE_FLASH_FIFO
#define FLASH_FIFO 1
#define FLASH_FIFO 1
#else
#define FLASH_FIFO 0
#define FLASH_FIFO 0
#endif
/**
* @}
@ -78,19 +78,17 @@ extern "C" {
/** @defgroup FLASH_Private_Types FLASH Private Types
* @{
*/
typedef enum
{
FLASH_CMD_AE = 0x000051AE, /**< Program area erase all */
FLASH_CMD_PE = 0x00005EA1, /**< Page erase */
FLASH_CMD_WP = 0x00005DA2, /**< Word program */
FLASH_CMD_DATAPE = 0x00005BA4, /**< Data flash page page erase */
FLASH_CMD_DATAWP = 0x00005AA5, /**< Data flash word program */
typedef enum {
FLASH_CMD_AE = 0x000051AEU, /**< Program area erase all */
FLASH_CMD_PE = 0x00005EA1U, /**< Page erase */
FLASH_CMD_WP = 0x00005DA2U, /**< Word program */
FLASH_CMD_DATAPE = 0x00005BA4U, /**< Data flash page page erase */
FLASH_CMD_DATAWP = 0x00005AA5U, /**< Data flash word program */
} flash_cmd_type;
typedef enum
{
OP_FLASH = 0, /**< Operate Pragram area */
OP_INFO = 1, /**< Operate info area */
typedef enum {
OP_FLASH = 0U, /**< Operate Pragram area */
OP_INFO = 1U, /**< Operate info area */
} op_cmd_type;
/**

99
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_gpio.h
View File

@ -18,7 +18,7 @@
#define __ALD_GPIO_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@ -52,7 +52,7 @@ extern "C" {
#define GPIO_PIN_13 (1U << 13)
#define GPIO_PIN_14 (1U << 14)
#define GPIO_PIN_15 (1U << 15)
#define GPIO_PIN_ALL (0xFFFF)
#define GPIO_PIN_ALL (0xFFFFU)
/**
* @}
*/
@ -65,82 +65,74 @@ extern "C" {
/**
* @brief GPIO mode
*/
typedef enum
{
GPIO_MODE_CLOSE = 0x0, /**< Digital close Analog open */
GPIO_MODE_INPUT = 0x1, /**< Input */
GPIO_MODE_OUTPUT = 0x2, /**< Output */
typedef enum {
GPIO_MODE_CLOSE = 0x0U, /**< Digital close Analog open */
GPIO_MODE_INPUT = 0x1U, /**< Input */
GPIO_MODE_OUTPUT = 0x2U, /**< Output */
} gpio_mode_t;
/**
* @brief GPIO open-drain or push-pull
*/
typedef enum
{
GPIO_PUSH_PULL = 0x0, /**< Push-Pull */
GPIO_OPEN_DRAIN = 0x2, /**< Open-Drain */
GPIO_OPEN_SOURCE = 0x3, /**< Open-Source */
typedef enum {
GPIO_PUSH_PULL = 0x0U, /**< Push-Pull */
GPIO_OPEN_DRAIN = 0x2U, /**< Open-Drain. Can't output high level */
GPIO_OPEN_SOURCE = 0x3U, /**< Open-Source. Can't output low level */
} gpio_odos_t;
/**
* @brief GPIO push-up or push-down
*/
typedef enum
{
GPIO_FLOATING = 0x0,/**< Floating */
GPIO_PUSH_UP = 0x1,/**< Push-Up */
GPIO_PUSH_DOWN = 0x2,/**< Push-Down */
GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */
typedef enum {
GPIO_FLOATING = 0x0U, /**< Floating */
GPIO_PUSH_UP = 0x1U, /**< Push-Up */
GPIO_PUSH_DOWN = 0x2U, /**< Push-Down */
GPIO_PUSH_UP_DOWN = 0x3U, /**< Push-Up and Push-Down */
} gpio_push_t;
/**
* @brief GPIO output drive
*/
typedef enum
{
GPIO_OUT_DRIVE_NORMAL = 0x0, /**< Normal current flow */
GPIO_OUT_DRIVE_STRONG = 0x1, /**< Strong current flow */
typedef enum {
GPIO_OUT_DRIVE_NORMAL = 0x0U, /**< Normal current flow */
GPIO_OUT_DRIVE_STRONG = 0x1U, /**< Strong current flow */
} gpio_out_drive_t;
/**
* @brief GPIO filter
*/
typedef enum
{
GPIO_FILTER_DISABLE = 0x0, /**< Disable filter */
GPIO_FILTER_ENABLE = 0x1, /**< Enable filter */
typedef enum {
GPIO_FILTER_DISABLE = 0x0U, /**< Disable filter */
GPIO_FILTER_ENABLE = 0x1U, /**< Enable filter */
} gpio_filter_t;
/**
* @brief GPIO type
*/
typedef enum
{
GPIO_TYPE_CMOS = 0x0, /**< CMOS Type */
GPIO_TYPE_TTL = 0x1, /**< TTL Type */
typedef enum {
GPIO_TYPE_CMOS = 0x0U, /**< CMOS Type */
GPIO_TYPE_TTL = 0x1U, /**< TTL Type */
} gpio_type_t;
/**
* @brief GPIO functions
*/
typedef enum
{
GPIO_FUNC_0 = 0, /**< function #0 */
GPIO_FUNC_1 = 1, /**< function #1 */
GPIO_FUNC_2 = 2, /**< function #2 */
GPIO_FUNC_3 = 3, /**< function #3 */
GPIO_FUNC_4 = 4, /**< function #4 */
GPIO_FUNC_5 = 5, /**< function #5 */
GPIO_FUNC_6 = 6, /**< function #6 */
GPIO_FUNC_7 = 7, /**< function #7 */
typedef enum {
GPIO_FUNC_0 = 0U, /**< function #0 */
GPIO_FUNC_1 = 1U, /**< function #1 */
GPIO_FUNC_2 = 2U, /**< function #2 */
GPIO_FUNC_3 = 3U, /**< function #3 */
GPIO_FUNC_4 = 4U, /**< function #4 */
GPIO_FUNC_5 = 5U, /**< function #5 */
GPIO_FUNC_6 = 6U, /**< function #6 */
GPIO_FUNC_7 = 7U, /**< function #7 */
} gpio_func_t;
/**
* @brief GPIO Init Structure definition
*/
typedef struct
{
typedef struct {
gpio_mode_t mode; /**< Specifies the operating mode for the selected pins.
This parameter can be any value of @ref gpio_mode_t */
gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins.
@ -160,27 +152,24 @@ typedef struct
/**
* @brief EXTI trigger style
*/
typedef enum
{
EXTI_TRIGGER_RISING_EDGE = 0, /**< Rising edge trigger */
EXTI_TRIGGER_TRAILING_EDGE = 1, /**< Trailing edge trigger */
EXTI_TRIGGER_BOTH_EDGE = 2, /**< Rising and trailing edge trigger */
typedef enum {
EXTI_TRIGGER_RISING_EDGE = 0U, /**< Rising edge trigger */
EXTI_TRIGGER_TRAILING_EDGE = 1U, /**< Trailing edge trigger */
EXTI_TRIGGER_BOTH_EDGE = 2U, /**< Rising and trailing edge trigger */
} exti_trigger_style_t;
/**
* @brief EXTI filter clock select
*/
typedef enum
{
EXTI_FILTER_CLOCK_10K = 0, /**< cks = 10KHz */
EXTI_FILTER_CLOCK_32K = 1, /**< cks = 32KHz */
typedef enum {
EXTI_FILTER_CLOCK_10K = 0U, /**< cks = 10KHz */
EXTI_FILTER_CLOCK_32K = 1U, /**< cks = 32KHz */
} exti_filter_clock_t;
/**
* @brief EXTI Init Structure definition
*/
typedef struct
{
typedef struct {
type_func_t filter; /**< Enable filter. */
exti_filter_clock_t cks; /**< Filter clock select. */
uint8_t filter_time; /**< Filter duration */
@ -193,8 +182,8 @@ typedef struct
* @defgroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define PIN_MASK 0xFFFF
#define UNLOCK_KEY 0x55AA
#define PIN_MASK 0xFFFFU
#define UNLOCK_KEY 0x55AAU
#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0))
#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \

147
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_i2c.h
View File

@ -39,90 +39,81 @@ extern "C" {
/**
* @brief I2C Error Code
*/
typedef enum
{
I2C_ERROR_NONE = 0x0, /**< No error */
I2C_ERROR_BERR = 0x1, /**< Berr error */
I2C_ERROR_ARLO = 0x2, /**< Arlo error */
I2C_ERROR_AF = 0x4, /**< Af error */
I2C_ERROR_OVR = 0x8, /**< Ovr error */
I2C_ERROR_DMA = 0x10, /**< Dma error */
I2C_ERROR_TIMEOUT = 0x20, /**< Timeout error */
typedef enum {
I2C_ERROR_NONE = 0x0U, /**< No error */
I2C_ERROR_BERR = 0x1U, /**< Berr error */
I2C_ERROR_ARLO = 0x2U, /**< Arlo error */
I2C_ERROR_AF = 0x4U, /**< Af error */
I2C_ERROR_OVR = 0x8U, /**< Ovr error */
I2C_ERROR_DMA = 0x10U, /**< Dma error */
I2C_ERROR_TIMEOUT = 0x20U, /**< Timeout error */
} i2c_error_t;
/**
* @brief I2C state structure definition
*/
typedef enum
{
I2C_STATE_RESET = 0x0, /**< Peripheral is not yet Initialized */
I2C_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */
I2C_STATE_BUSY = 0x2, /**< An internal process is ongoing */
I2C_STATE_BUSY_TX = 0x3, /**< Data Transmission process is ongoing */
I2C_STATE_BUSY_RX = 0x4, /**< Data Reception process is ongoing */
I2C_STATE_TIMEOUT = 0x5, /**< timeout state */
I2C_STATE_ERROR = 0x6, /**< Error */
typedef enum {
I2C_STATE_RESET = 0x0U, /**< Peripheral is not yet Initialized */
I2C_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */
I2C_STATE_BUSY = 0x2U, /**< An internal process is ongoing */
I2C_STATE_BUSY_TX = 0x3U, /**< Data Transmission process is ongoing */
I2C_STATE_BUSY_RX = 0x4U, /**< Data Reception process is ongoing */
I2C_STATE_TIMEOUT = 0x5U, /**< timeout state */
I2C_STATE_ERROR = 0x6U, /**< Error */
} i2c_state_t;
/**
* @brief I2C Duty Cycle
*/
typedef enum
{
I2C_DUTYCYCLE_2 = 0x0, /**< duty cycle is 2 */
I2C_DUTYCYCLE_16_9 = 0x4000, /**< duty cycle is 16/9 */
typedef enum {
I2C_DUTYCYCLE_2 = 0x0U, /**< duty cycle is 2 */
I2C_DUTYCYCLE_16_9 = 0x4000U, /**< duty cycle is 16/9 */
} i2c_duty_t;
/**
* @brief I2C Addressing Mode
*/
typedef enum
{
I2C_ADDR_7BIT = 0x1, /**< 7 bit address */
I2C_ADDR_10BIT = 0x2, /**< 10 bit address */
typedef enum {
I2C_ADDR_7BIT = 0x1U, /**< 7 bit address */
I2C_ADDR_10BIT = 0x2U, /**< 10 bit address */
} i2c_addr_t;
/**
* @brief I2C Dual Addressing Mode
*/
typedef enum
{
I2C_DUALADDR_DISABLE = 0x0, /**< dual address is disable */
I2C_DUALADDR_ENABLE = 0x1, /**< dual address is enable */
typedef enum {
I2C_DUALADDR_DISABLE = 0x0U, /**< dual address is disable */
I2C_DUALADDR_ENABLE = 0x1U, /**< dual address is enable */
} i2c_dual_addr_t;
/**
* @brief I2C General Call Addressing mode
*/
typedef enum
{
I2C_GENERALCALL_DISABLE = 0x0, /**< feneral call address is disable */
I2C_GENERALCALL_ENABLE = 0x40, /**< feneral call address is enable */
typedef enum {
I2C_GENERALCALL_DISABLE = 0x0U, /**< feneral call address is disable */
I2C_GENERALCALL_ENABLE = 0x40U, /**< feneral call address is enable */
} i2c_general_addr_t;
/**
* @brief I2C Nostretch Mode
*/
typedef enum
{
I2C_NOSTRETCH_DISABLE = 0x0, /**< Nostretch disable */
I2C_NOSTRETCH_ENABLE = 0x80, /**< Nostretch enable */
typedef enum {
I2C_NOSTRETCH_DISABLE = 0x0U, /**< Nostretch disable */
I2C_NOSTRETCH_ENABLE = 0x80U, /**< Nostretch enable */
} i2c_nostretch_t;
/**
* @brief I2C Memory Address Size
*/
typedef enum
{
I2C_MEMADD_SIZE_8BIT = 0x1, /**< 8 bit memory address size */
I2C_MEMADD_SIZE_16BIT = 0x10 /**< 10 bit memory address size */
typedef enum {
I2C_MEMADD_SIZE_8BIT = 0x1U, /**< 8 bit memory address size */
I2C_MEMADD_SIZE_16BIT = 0x10U, /**< 10 bit memory address size */
} i2c_addr_size_t;
/**
* @brief I2C Flag Definition
*/
typedef enum
{
typedef enum {
I2C_FLAG_SB = (1U << 0),
I2C_FLAG_ADDR = (1U << 1),
I2C_FLAG_BTF = (1U << 2),
@ -151,26 +142,24 @@ typedef enum
*/
typedef enum
{
I2C_MODE_NONE = 0x0, /**< No I2C communication on going */
I2C_MODE_MASTER = 0x10, /**< I2C communication is in Master mode */
I2C_MODE_SLAVE = 0x20, /**< I2C communication is in Slave mode */
I2C_MODE_MEM = 0x40, /**< I2C communication is in Memory mode */
I2C_MODE_NONE = 0x0U, /**< No I2C communication on going */
I2C_MODE_MASTER = 0x10U, /**< I2C communication is in Master mode */
I2C_MODE_SLAVE = 0x20U, /**< I2C communication is in Slave mode */
I2C_MODE_MEM = 0x40U, /**< I2C communication is in Memory mode */
} i2c_mode_t;
/**
* @brief I2C Clock
*/
typedef enum
{
I2C_STANDARD_MODE_MAX_CLK = 100000, /**< Standard mode clock */
I2C_FAST_MODE_MAX_CLK = 400000, /**< Fast mode clock */
typedef enum {
I2C_STANDARD_MODE_MAX_CLK = 100000U, /**< Standard mode clock */
I2C_FAST_MODE_MAX_CLK = 400000U, /**< Fast mode clock */
} i2c_clock_t;
/**
* @brief Interrupt Configuration Definition
*/
typedef enum
{
typedef enum {
I2C_IT_BUF = (1U << 10), /**< Buffer interrupt */
I2C_IT_EVT = (1U << 9), /**< Event interrupt */
I2C_IT_ERR = (1U << 8), /**< Error interrupt */
@ -179,8 +168,7 @@ typedef enum
/**
* @brief I2C CON1 Register
*/
typedef enum
{
typedef enum {
I2C_CON1_PEN = (1U << 0), /**< PEN BIT */
I2C_CON1_PMOD = (1U << 1), /**< PMOD BIT */
I2C_CON1_SMBMOD = (1U << 3), /**< SMBMOD BIT */
@ -200,9 +188,8 @@ typedef enum
/**
* @brief I2C CON2 Register
*/
typedef enum
{
I2C_CON2_CLKF = 0x3F, /**< CLKF BITS */
typedef enum {
I2C_CON2_CLKF = 0x3FU, /**< CLKF BITS */
I2C_CON2_CLKF_0 = (1U << 0), /**< CLKF_0 BIT */
I2C_CON2_CLKF_1 = (1U << 1), /**< CLKF_1 BIT */
I2C_CON2_CLKF_2 = (1U << 2), /**< CLKF_2 BIT */
@ -219,8 +206,7 @@ typedef enum
/**
* @brief I2C ADDR1 Register
*/
typedef enum
{
typedef enum {
I2C_ADDR1_ADDH0 = (1U << 0), /**< ADDH0 BIT */
I2C_ADDR1_ADDH1 = (1U << 1), /**< ADDH1 BIT */
I2C_ADDR1_ADDH2 = (1U << 2), /**< ADDH2 BIT */
@ -237,8 +223,7 @@ typedef enum
/**
* @brief I2C ADDR2 Register
*/
typedef enum
{
typedef enum {
I2C_ADDR2_DUALEN = (1U << 0), /**< DUALEN BIT */
I2C_ADDR2_ADD = (1U << 1), /**< ADD BIT */
} i2c_addr2_t;
@ -246,8 +231,7 @@ typedef enum
/**
* @brief I2C STAT1 Register
*/
typedef enum
{
typedef enum {
I2C_STAT1_SB = (1U << 0), /**< SB BIT */
I2C_STAT1_ADDR = (1U << 1), /**< ADDR BIT */
I2C_STAT1_BTC = (1U << 2), /**< BTC BIT */
@ -267,8 +251,7 @@ typedef enum
/**
* @brief I2C STAT2 Register
*/
typedef enum
{
typedef enum {
I2C_STAT2_MASTER = (1U << 0), /**< MASTER BIT */
I2C_STAT2_BSYF = (1U << 1), /**< BSYF BIT */
I2C_STAT2_TRF = (1U << 2), /**< TRF BIT */
@ -282,9 +265,8 @@ typedef enum
/**
* @brief I2C CKCFG Register
*/
typedef enum
{
I2C_CKCFG_CLKSET = 0xFFF, /**< CLKSET BITS */
typedef enum {
I2C_CKCFG_CLKSET = 0xFFFU, /**< CLKSET BITS */
I2C_CKCFG_DUTY = (1U << 14), /**< DUTY BIT */
I2C_CKCFG_CLKMOD = (1U << 15), /**< CLKMOD BIT */
} i2c_ckcfg_t;
@ -292,16 +274,14 @@ typedef enum
/**
* @brief I2C RT Register
*/
typedef enum
{
I2C_RT_RISET = 0x3F, /**< RISET BITS */
typedef enum {
I2C_RT_RISET = 0x3FU, /**< RISET BITS */
} i2c_trise_t;
/**
* @brief I2C Configuration Structure definition
*/
typedef struct
{
typedef struct {
uint32_t clk_speed; /**< Specifies the clock frequency */
i2c_duty_t duty; /**< Specifies the I2C fast mode duty cycle */
uint32_t own_addr1; /**< Specifies the first device own address */
@ -315,8 +295,7 @@ typedef struct
/**
* @brief I2C handle Structure definition
*/
typedef struct i2c_handle_s
{
typedef struct i2c_handle_s {
I2C_TypeDef *perh; /**< I2C registers base address */
i2c_init_t init; /**< I2C communication parameters */
uint8_t *p_buff; /**< Pointer to I2C transfer buffer */
@ -349,19 +328,19 @@ typedef struct i2c_handle_s
*/
#define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET)
#define I2C_CLEAR_ADDRFLAG(x) \
do { \
do { \
__IO uint32_t tmpreg; \
tmpreg = (x)->perh->STAT1; \
tmpreg = (x)->perh->STAT2; \
UNUSED(tmpreg); \
} while (0)
} while (0)
#define __I2C_CLEAR_STOPFLAG(x) \
do { \
do { \
__IO uint32_t tmpreg; \
tmpreg = (x)->perh->STAT1; \
tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN); \
UNUSED(tmpreg); \
} while (0)
} while (0)
#define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK))
#define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK))
/**
@ -454,7 +433,7 @@ ald_status_t ald_i2c_reset(i2c_handle_t *hperh);
/** @addtogroup I2C_Public_Functions_Group2
* @{
*/
/** Blocking mode: Polling */
/** Blocking mode: Polling */
ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr,
uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr,
@ -467,7 +446,7 @@ ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t m
i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout);
ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout);
/** Non-Blocking mode: Interrupt */
/** Non-Blocking mode: Interrupt */
ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size);
ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size);
ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size);
@ -478,7 +457,7 @@ ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint
i2c_addr_size_t add_size, uint8_t *buf, uint16_t size);
#ifdef ALD_DMA
/** Non-Blocking mode: DMA */
/** Non-Blocking mode: DMA */
ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr,
uint8_t *buf, uint16_t size, uint8_t channel);
ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr,

8
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_iap.h
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@ -36,10 +36,10 @@ extern "C" {
* @defgroup IAP_Private_Macros IAP Private Macros
* @{
*/
#define IAP_WSP_ADDR 0x10000000
#define IAP_PE_ADDR 0x10000004
#define IAP_WP_ADDR 0x10000008
#define IAP_DWP_ADDR 0x1000000c
#define IAP_WSP_ADDR 0x10000000U
#define IAP_PE_ADDR 0x10000004U
#define IAP_WP_ADDR 0x10000008U
#define IAP_DWP_ADDR 0x1000000cU
/**
* @}
*/

261
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lcd.h
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@ -38,217 +38,201 @@ extern "C" {
/**
* @brief Lcd vlcd voltage type
*/
typedef enum
{
LCD_VCHPS_3V2 = 0, /**< 3.2V */
LCD_VCHPS_3V8 = 1, /**< 3.8V */
LCD_VCHPS_4V8 = 2, /**< 4.8V */
LCD_VCHPS_5V4 = 3, /**< 5.4V */
typedef enum {
LCD_VCHPS_3V2 = 0U, /**< 3.2V */
LCD_VCHPS_3V8 = 1U, /**< 3.8V */
LCD_VCHPS_4V8 = 2U, /**< 4.8V */
LCD_VCHPS_5V4 = 3U, /**< 5.4V */
} lcd_vchps_t;
/**
* @brief Lcd function type
*/
typedef enum
{
LCD_FUNC_DISABLE = 0, /**< Lcd's function disable */
LCD_FUNC_ENABLE = 1, /**< Lcd's function enable */
typedef enum {
LCD_FUNC_DISABLE = 0U, /**< Lcd's function disable */
LCD_FUNC_ENABLE = 1U, /**< Lcd's function enable */
} lcd_func_t;
/**
* @brief Lcd voltage type
*/
typedef enum
{
LCD_VSEL_VDD = 0, /**< VDD */
LCD_VSEL_CP = 1, /**< Charge pump output */
LCD_VSEL_VLCD = 2, /**< VLCD input */
typedef enum {
LCD_VSEL_VDD = 0U, /**< VDD */
LCD_VSEL_CP = 1U, /**< Charge pump output */
LCD_VSEL_VLCD = 2U, /**< VLCD input */
} lcd_vsel_t;
/**
* @brief Lcd resistance select bit
*/
typedef enum
{
LCD_RES_1MOHM = 0, /**< 1M ohm */
LCD_RES_2MOHM = 1, /**< 2M ohm */
LCD_RES_3MOHM = 2, /**< 3M ohm */
typedef enum {
LCD_RES_1MOHM = 0U, /**< 1M ohm */
LCD_RES_2MOHM = 1U, /**< 2M ohm */
LCD_RES_3MOHM = 2U, /**< 3M ohm */
} lcd_res_t;
/**
* @brief Lcd bias selector
*/
typedef enum
{
LCD_BIAS_1_4 = 0, /**< 1/4 bias */
LCD_BIAS_1_2 = 2, /**< 1/2 bias */
LCD_BIAS_1_3 = 3, /**< 1/3 bias */
typedef enum {
LCD_BIAS_1_4 = 0U, /**< 1/4 bias */
LCD_BIAS_1_2 = 2U, /**< 1/2 bias */
LCD_BIAS_1_3 = 3U, /**< 1/3 bias */
} lcd_bias_t;
/**
* @brief Lcd duty
*/
typedef enum
{
LCD_DUTY_STATIC = 0, /**< Static duty (COM0) */
LCD_DUTY_1_2 = 1, /**< 1/2 duty (COM0~COM1) */
LCD_DUTY_1_3 = 2, /**< 1/3 duty (COM0~COM2) */
LCD_DUTY_1_4 = 3, /**< 1/4 duty (COM0~COM3) */
LCD_DUTY_1_6 = 4, /**< 1/6 duty (COM0~COM5) */
LCD_DUTY_1_8 = 5, /**< 1/8 duty (COM0~COM7) */
typedef enum {
LCD_DUTY_STATIC = 0U, /**< Static duty (COM0) */
LCD_DUTY_1_2 = 1U, /**< 1/2 duty (COM0~COM1) */
LCD_DUTY_1_3 = 2U, /**< 1/3 duty (COM0~COM2) */
LCD_DUTY_1_4 = 3U, /**< 1/4 duty (COM0~COM3) */
LCD_DUTY_1_6 = 4U, /**< 1/6 duty (COM0~COM5) */
LCD_DUTY_1_8 = 5U, /**< 1/8 duty (COM0~COM7) */
} lcd_duty_t;
/**
* @brief Lcd prescaler
*/
typedef enum
{
LCD_PRS_1 = 0, /**< CLKPRS = LCDCLK / 1 */
LCD_PRS_2 = 1, /**< CLKPRS = LCDCLK / 2 */
LCD_PRS_4 = 2, /**< CLKPRS = LCDCLK / 4 */
LCD_PRS_8 = 3, /**< CLKPRS = LCDCLK / 8 */
LCD_PRS_16 = 4, /**< CLKPRS = LCDCLK / 16 */
LCD_PRS_32 = 5, /**< CLKPRS = LCDCLK / 32 */
LCD_PRS_64 = 6, /**< CLKPRS = LCDCLK / 64 */
LCD_PRS_128 = 7, /**< CLKPRS = LCDCLK / 128 */
LCD_PRS_256 = 8, /**< CLKPRS = LCDCLK / 256 */
LCD_PRS_512 = 9, /**< CLKPRS = LCDCLK / 512 */
LCD_PRS_1024 = 10, /**< CLKPRS = LCDCLK / 1024 */
LCD_PRS_2048 = 11, /**< CLKPRS = LCDCLK / 2048 */
LCD_PRS_4096 = 12, /**< CLKPRS = LCDCLK / 4096 */
LCD_PRS_8192 = 13, /**< CLKPRS = LCDCLK / 8192 */
LCD_PRS_16384 = 14, /**< CLKPRS = LCDCLK / 16384 */
LCD_PRS_32768 = 15, /**< CLKPRS = LCDCLK / 32768 */
typedef enum {
LCD_PRS_1 = 0U, /**< CLKPRS = LCDCLK / 1 */
LCD_PRS_2 = 1U, /**< CLKPRS = LCDCLK / 2 */
LCD_PRS_4 = 2U, /**< CLKPRS = LCDCLK / 4 */
LCD_PRS_8 = 3U, /**< CLKPRS = LCDCLK / 8 */
LCD_PRS_16 = 4U, /**< CLKPRS = LCDCLK / 16 */
LCD_PRS_32 = 5U, /**< CLKPRS = LCDCLK / 32 */
LCD_PRS_64 = 6U, /**< CLKPRS = LCDCLK / 64 */
LCD_PRS_128 = 7U, /**< CLKPRS = LCDCLK / 128 */
LCD_PRS_256 = 8U, /**< CLKPRS = LCDCLK / 256 */
LCD_PRS_512 = 9U, /**< CLKPRS = LCDCLK / 512 */
LCD_PRS_1024 = 10U, /**< CLKPRS = LCDCLK / 1024 */
LCD_PRS_2048 = 11U, /**< CLKPRS = LCDCLK / 2048 */
LCD_PRS_4096 = 12U, /**< CLKPRS = LCDCLK / 4096 */
LCD_PRS_8192 = 13U, /**< CLKPRS = LCDCLK / 8192 */
LCD_PRS_16384 = 14U, /**< CLKPRS = LCDCLK / 16384 */
LCD_PRS_32768 = 15U, /**< CLKPRS = LCDCLK / 32768 */
} lcd_prs_t;
/**
* @brief Lcd divider
*/
typedef enum
{
LCD_DIV_16 = 0, /**< DIVCLK = CLKPRS / 16 */
LCD_DIV_17 = 1, /**< DIVCLK = CLKPRS / 17 */
LCD_DIV_18 = 2, /**< DIVCLK = CLKPRS / 18 */
LCD_DIV_19 = 3, /**< DIVCLK = CLKPRS / 19 */
LCD_DIV_20 = 4, /**< DIVCLK = CLKPRS / 20 */
LCD_DIV_21 = 5, /**< DIVCLK = CLKPRS / 21 */
LCD_DIV_22 = 6, /**< DIVCLK = CLKPRS / 22 */
LCD_DIV_23 = 7, /**< DIVCLK = CLKPRS / 23 */
LCD_DIV_24 = 8, /**< DIVCLK = CLKPRS / 24 */
LCD_DIV_25 = 9, /**< DIVCLK = CLKPRS / 25 */
LCD_DIV_26 = 10, /**< DIVCLK = CLKPRS / 26 */
LCD_DIV_27 = 11, /**< DIVCLK = CLKPRS / 27 */
LCD_DIV_28 = 12, /**< DIVCLK = CLKPRS / 28 */
LCD_DIV_29 = 13, /**< DIVCLK = CLKPRS / 29 */
LCD_DIV_30 = 14, /**< DIVCLK = CLKPRS / 30 */
LCD_DIV_31 = 15, /**< DIVCLK = CLKPRS / 31 */
typedef enum {
LCD_DIV_16 = 0U, /**< DIVCLK = CLKPRS / 16 */
LCD_DIV_17 = 1U, /**< DIVCLK = CLKPRS / 17 */
LCD_DIV_18 = 2U, /**< DIVCLK = CLKPRS / 18 */
LCD_DIV_19 = 3U, /**< DIVCLK = CLKPRS / 19 */
LCD_DIV_20 = 4U, /**< DIVCLK = CLKPRS / 20 */
LCD_DIV_21 = 5U, /**< DIVCLK = CLKPRS / 21 */
LCD_DIV_22 = 6U, /**< DIVCLK = CLKPRS / 22 */
LCD_DIV_23 = 7U, /**< DIVCLK = CLKPRS / 23 */
LCD_DIV_24 = 8U, /**< DIVCLK = CLKPRS / 24 */
LCD_DIV_25 = 9U, /**< DIVCLK = CLKPRS / 25 */
LCD_DIV_26 = 10U, /**< DIVCLK = CLKPRS / 26 */
LCD_DIV_27 = 11U, /**< DIVCLK = CLKPRS / 27 */
LCD_DIV_28 = 12U, /**< DIVCLK = CLKPRS / 28 */
LCD_DIV_29 = 13U, /**< DIVCLK = CLKPRS / 29 */
LCD_DIV_30 = 14U, /**< DIVCLK = CLKPRS / 30 */
LCD_DIV_31 = 15U, /**< DIVCLK = CLKPRS / 31 */
} lcd_div_t;
/**
* @brief Lcd blink mode
*/
typedef enum
{
LCD_BLINK_OFF = 0, /**< Blink disabled */
LCD_BLINK_SEG0_COM0 = 1, /**< Blink enabled on SEG0, COM0 */
LCD_BLINK_SEG0_COMX2 = 2, /**< Blink enabled on SEG0, COMx2 */
LCD_BLINK_ALLSEG_ALLCOM = 3, /**< Blink enabled on all SEG and all COM */
typedef enum {
LCD_BLINK_OFF = 0U, /**< Blink disabled */
LCD_BLINK_SEG0_COM0 = 1U, /**< Blink enabled on SEG0, COM0 */
LCD_BLINK_SEG0_COMX2 = 2U, /**< Blink enabled on SEG0, COMx2 */
LCD_BLINK_ALLSEG_ALLCOM = 3U, /**< Blink enabled on all SEG and all COM */
} lcd_blink_t;
/**
* @brief Lcd blink frequency
*/
typedef enum
{
LCD_BLFRQ_8 = 0, /**< DIVCLK / 8 */
LCD_BLFRQ_16 = 1, /**< DIVCLK / 16 */
LCD_BLFRQ_32 = 2, /**< DIVCLK / 32 */
LCD_BLFRQ_64 = 3, /**< DIVCLK / 64 */
LCD_BLFRQ_128 = 4, /**< DIVCLK / 128 */
LCD_BLFRQ_256 = 5, /**< DIVCLK / 256 */
LCD_BLFRQ_512 = 6, /**< DIVCLK / 512 */
LCD_BLFRQ_1024 = 7, /**< DIVCLK / 1024 */
typedef enum {
LCD_BLFRQ_8 = 0U, /**< DIVCLK / 8 */
LCD_BLFRQ_16 = 1U, /**< DIVCLK / 16 */
LCD_BLFRQ_32 = 2U, /**< DIVCLK / 32 */
LCD_BLFRQ_64 = 3U, /**< DIVCLK / 64 */
LCD_BLFRQ_128 = 4U, /**< DIVCLK / 128 */
LCD_BLFRQ_256 = 5U, /**< DIVCLK / 256 */
LCD_BLFRQ_512 = 6U, /**< DIVCLK / 512 */
LCD_BLFRQ_1024 = 7U, /**< DIVCLK / 1024 */
} lcd_blfrq_t;
/**
* @brief Lcd dead time
*/
typedef enum
{
LCD_DEAD_TIME_NONE = 0, /**< No dead time */
LCD_DEAD_TIME_1_DIVCLK = 1, /**< Dead time is 1 divclk */
LCD_DEAD_TIME_2_DIVCLK = 2, /**< Dead time is 2 divclk */
LCD_DEAD_TIME_3_DIVCLK = 3, /**< Dead time is 3 divclk */
LCD_DEAD_TIME_4_DIVCLK = 4, /**< Dead time is 4 divclk */
LCD_DEAD_TIME_5_DIVCLK = 5, /**< Dead time is 5 divclk */
LCD_DEAD_TIME_6_DIVCLK = 6, /**< Dead time is 6 divclk */
LCD_DEAD_TIME_7_DIVCLK = 7, /**< Dead time is 7 divclk */
typedef enum {
LCD_DEAD_TIME_NONE = 0U, /**< No dead time */
LCD_DEAD_TIME_1_DIVCLK = 1U, /**< Dead time is 1 divclk */
LCD_DEAD_TIME_2_DIVCLK = 2U, /**< Dead time is 2 divclk */
LCD_DEAD_TIME_3_DIVCLK = 3U, /**< Dead time is 3 divclk */
LCD_DEAD_TIME_4_DIVCLK = 4U, /**< Dead time is 4 divclk */
LCD_DEAD_TIME_5_DIVCLK = 5U, /**< Dead time is 5 divclk */
LCD_DEAD_TIME_6_DIVCLK = 6U, /**< Dead time is 6 divclk */
LCD_DEAD_TIME_7_DIVCLK = 7U, /**< Dead time is 7 divclk */
} lcd_dead_t;
/**
* @brief Lcd pulse keep time
*/
typedef enum
{
LCD_PON_NONE = 0, /**< No pulse keep time */
LCD_PON_1_PRSCLK = 1, /**< Pulse keep 1 prsclk */
LCD_PON_2_PRSCLK = 2, /**< Pulse keep 2 prsclk */
LCD_PON_3_PRSCLK = 3, /**< Pulse keep 3 prsclk */
LCD_PON_4_PRSCLK = 4, /**< Pulse keep 4 prsclk */
LCD_PON_5_PRSCLK = 5, /**< Pulse keep 5 prsclk */
LCD_PON_6_PRSCLK = 6, /**< Pulse keep 6 prsclk */
LCD_PON_7_PRSCLK = 7, /**< Pulse keep 7 prsclk */
typedef enum {
LCD_PON_NONE = 0U, /**< No pulse keep time */
LCD_PON_1_PRSCLK = 1U, /**< Pulse keep 1 prsclk */
LCD_PON_2_PRSCLK = 2U, /**< Pulse keep 2 prsclk */
LCD_PON_3_PRSCLK = 3U, /**< Pulse keep 3 prsclk */
LCD_PON_4_PRSCLK = 4U, /**< Pulse keep 4 prsclk */
LCD_PON_5_PRSCLK = 5U, /**< Pulse keep 5 prsclk */
LCD_PON_6_PRSCLK = 6U, /**< Pulse keep 6 prsclk */
LCD_PON_7_PRSCLK = 7U, /**< Pulse keep 7 prsclk */
} lcd_pluse_on_t;
/**
* @brief Lcd vgs select
*/
typedef enum
{
LCD_VGS_0 = 0, /**< Grey level display voltage is 30/45 vlcd */
LCD_VGS_1 = 1, /**< Grey level display voltage is 31/45 vlcd */
LCD_VGS_2 = 2, /**< Grey level display voltage is 32/45 vlcd */
LCD_VGS_3 = 3, /**< Grey level display voltage is 33/45 vlcd */
LCD_VGS_4 = 4, /**< Grey level display voltage is 34/45 vlcd */
LCD_VGS_5 = 5, /**< Grey level display voltage is 35/45 vlcd */
LCD_VGS_6 = 6, /**< Grey level display voltage is 36/45 vlcd */
LCD_VGS_7 = 7, /**< Grey level display voltage is 37/45 vlcd */
LCD_VGS_8 = 8, /**< Grey level display voltage is 38/45 vlcd */
LCD_VGS_9 = 9, /**< Grey level display voltage is 39/45 vlcd */
LCD_VGS_10 = 10, /**< Grey level display voltage is 40/45 vlcd */
LCD_VGS_11 = 11, /**< Grey level display voltage is 41/45 vlcd */
LCD_VGS_12 = 12, /**< Grey level display voltage is 42/45 vlcd */
LCD_VGS_13 = 13, /**< Grey level display voltage is 43/45 vlcd */
LCD_VGS_14 = 14, /**< Grey level display voltage is 44/45 vlcd */
LCD_VGS_15 = 15, /**< Grey level display voltage is equal to vlcd */
typedef enum {
LCD_VGS_0 = 0U, /**< Grey level display voltage is 30/45 vlcd */
LCD_VGS_1 = 1U, /**< Grey level display voltage is 31/45 vlcd */
LCD_VGS_2 = 2U, /**< Grey level display voltage is 32/45 vlcd */
LCD_VGS_3 = 3U, /**< Grey level display voltage is 33/45 vlcd */
LCD_VGS_4 = 4U, /**< Grey level display voltage is 34/45 vlcd */
LCD_VGS_5 = 5U, /**< Grey level display voltage is 35/45 vlcd */
LCD_VGS_6 = 6U, /**< Grey level display voltage is 36/45 vlcd */
LCD_VGS_7 = 7U, /**< Grey level display voltage is 37/45 vlcd */
LCD_VGS_8 = 8U, /**< Grey level display voltage is 38/45 vlcd */
LCD_VGS_9 = 9U, /**< Grey level display voltage is 39/45 vlcd */
LCD_VGS_10 = 10U, /**< Grey level display voltage is 40/45 vlcd */
LCD_VGS_11 = 11U, /**< Grey level display voltage is 41/45 vlcd */
LCD_VGS_12 = 12U, /**< Grey level display voltage is 42/45 vlcd */
LCD_VGS_13 = 13U, /**< Grey level display voltage is 43/45 vlcd */
LCD_VGS_14 = 14U, /**< Grey level display voltage is 44/45 vlcd */
LCD_VGS_15 = 15U, /**< Grey level display voltage is equal to vlcd */
} lcd_vgs_t;
/**
* @brief Lcd wave choose
*/
typedef enum
{
LCD_WAVE_A = 0, /**< Wave type is A */
LCD_WAVE_B = 1, /**< Wave type is B */
typedef enum {
LCD_WAVE_A = 0U, /**< Wave type is A */
LCD_WAVE_B = 1U, /**< Wave type is B */
} lcd_wfs_t;
/**
* @brief Lcd status select bit
*/
typedef enum
{
typedef enum {
LCD_STATUS_RDY = (1U << 0), /**< VLCD voltage state flag */
LCD_STATUS_ENS = (1U << 1), /**< LCD Enable state flag*/
LCD_STATUS_UDR = (1U << 2), /**< Update display request state flag */
LCD_STATUS_FCRSF = (1U << 3), /**< LCD frame control sync flag */
LCD_STATUS_ALL = 0xFFFFFFF, /**< All flag */
LCD_STATUS_ALL = 0xFFFFFFFU, /**< All flag */
} lcd_status_t;
/**
* @brief Lcd interrupt type
*/
typedef enum
{
typedef enum {
LCD_IT_SOF = (1U << 0), /**< Start of frame interrupt enable */
LCD_IT_UDD = (1U << 1), /**< Update display done interrupt enable*/
} lcd_it_t;
@ -256,8 +240,7 @@ typedef enum
/**
* @brief Lcd interrupt flag
*/
typedef enum
{
typedef enum {
LCD_FLAG_SOF = (1U << 0), /**< Start of frame interrupt enable flag*/
LCD_FLAG_UDD = (1U << 1), /**< Update display done interrupt enable flag*/
} lcd_flag_t;
@ -265,10 +248,9 @@ typedef enum
/**
* @brief Lcd interrupt type
*/
typedef enum
{
SEG_0_TO_31 = 0, /**< Segment 0 to 31 to be set */
SEG_32_TO_59 = 1, /**< Segment 32 to 59 to be set */
typedef enum {
SEG_0_TO_31 = 0U, /**< Segment 0 to 31 to be set */
SEG_32_TO_59 = 1U, /**< Segment 32 to 59 to be set */
} lcd_seg_t;
/**
@ -298,8 +280,7 @@ typedef struct
/**
* @brief Lcd handle Structure definition
*/
typedef struct lcd_handle_s
{
typedef struct lcd_handle_s {
LCD_TypeDef *perh; /**< LCD registers base address */
lcd_init_t init; /**< LCD initialize parameters */
lock_state_t lock; /**< Locking object */

168
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lptim.h
View File

@ -19,7 +19,7 @@
#define __ALD_LPTIM_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@ -41,141 +41,128 @@ extern "C" {
/**
* @brief LPTIM clock select
*/
typedef enum
{
LPTIM_CKSEL_INTERNAL = 0, /**< Select internal clock */
LPTIM_CKSEL_EXTERNAL = 1, /**< Select external clock */
typedef enum {
LPTIM_CKSEL_INTERNAL = 0U, /**< Select internal clock */
LPTIM_CKSEL_EXTERNAL = 1U, /**< Select external clock */
} lptim_cksel_t;
/**
* @brief LPTIM clock pol
*/
typedef enum
{
LPTIM_CKPOL_RISING = 0, /**< using rising edge */
LPTIM_CKPOL_FALLING = 1, /**< using falling edge */
typedef enum {
LPTIM_CKPOL_RISING = 0U, /**< using rising edge */
LPTIM_CKPOL_FALLING = 1U, /**< using falling edge */
} lptim_ckpol_t;
/**
* @brief LPTIM clock fliter
*/
typedef enum
{
LPTIM_CKFLT_0 = 0, /**< not clock filter */
LPTIM_CKFLT_2 = 1, /**< 2 cycle filter */
LPTIM_CKFLT_4 = 2, /**< 4 cycle filter */
LPTIM_CKFLT_8 = 3, /**< 8 cycle filter */
typedef enum {
LPTIM_CKFLT_0 = 0U, /**< not clock filter */
LPTIM_CKFLT_2 = 1U, /**< 2 cycle filter */
LPTIM_CKFLT_4 = 2U, /**< 4 cycle filter */
LPTIM_CKFLT_8 = 3U, /**< 8 cycle filter */
} lptim_ckflt_t;
/**
* @brief LPTIM trigger fliter
*/
typedef enum
{
LPTIM_TRGFLT_0 = 0, /**< not clock filter */
LPTIM_TRGFLT_2 = 1, /**< 2 cycle filter */
LPTIM_TRGFLT_4 = 2, /**< 4 cycle filter */
LPTIM_TRGFLT_8 = 3, /**< 8 cycle filter */
typedef enum {
LPTIM_TRGFLT_0 = 0U, /**< not clock filter */
LPTIM_TRGFLT_2 = 1U, /**< 2 cycle filter */
LPTIM_TRGFLT_4 = 2U, /**< 4 cycle filter */
LPTIM_TRGFLT_8 = 3U, /**< 8 cycle filter */
} lptim_trgflt_t;
/**
* @brief LPTIM prescaler
*/
typedef enum
{
LPTIM_PRESC_1 = 0, /**< No prescaler is used */
LPTIM_PRESC_2 = 1, /**< Clock is divided by 2 */
LPTIM_PRESC_4 = 2, /**< Clock is divided by 4 */
LPTIM_PRESC_8 = 3, /**< Clock is divided by 8 */
LPTIM_PRESC_16 = 4, /**< Clock is divided by 16 */
LPTIM_PRESC_32 = 5, /**< Clock is divided by 32 */
LPTIM_PRESC_64 = 6, /**< Clock is divided by 64 */
LPTIM_PRESC_128 = 7, /**< Clock is divided by 128 */
typedef enum {
LPTIM_PRESC_1 = 0U, /**< No prescaler is used */
LPTIM_PRESC_2 = 1U, /**< Clock is divided by 2 */
LPTIM_PRESC_4 = 2U, /**< Clock is divided by 4 */
LPTIM_PRESC_8 = 3U, /**< Clock is divided by 8 */
LPTIM_PRESC_16 = 4U, /**< Clock is divided by 16 */
LPTIM_PRESC_32 = 5U, /**< Clock is divided by 32 */
LPTIM_PRESC_64 = 6U, /**< Clock is divided by 64 */
LPTIM_PRESC_128 = 7U, /**< Clock is divided by 128 */
} lptim_presc_t;
/**
* @brief LPTIM trig select
*/
typedef enum
{
LPTIM_TRIGSEL_EXT0 = 0, /**< Trigger select external channel 0 */
LPTIM_TRIGSEL_EXT1 = 1, /**< Trigger select external channel 1 */
LPTIM_TRIGSEL_EXT2 = 2, /**< Trigger select external channel 2 */
LPTIM_TRIGSEL_EXT3 = 3, /**< Trigger select external channel 3 */
LPTIM_TRIGSEL_EXT4 = 4, /**< Trigger select external channel 4 */
LPTIM_TRIGSEL_EXT5 = 5, /**< Trigger select external channel 5 */
LPTIM_TRIGSEL_EXT6 = 6, /**< Trigger select external channel 6 */
LPTIM_TRIGSEL_EXT7 = 7, /**< Trigger select external channel 7 */
typedef enum {
LPTIM_TRIGSEL_EXT0 = 0U, /**< Trigger select external channel 0 */
LPTIM_TRIGSEL_EXT1 = 1U, /**< Trigger select external channel 1 */
LPTIM_TRIGSEL_EXT2 = 2U, /**< Trigger select external channel 2 */
LPTIM_TRIGSEL_EXT3 = 3U, /**< Trigger select external channel 3 */
LPTIM_TRIGSEL_EXT4 = 4U, /**< Trigger select external channel 4 */
LPTIM_TRIGSEL_EXT5 = 5U, /**< Trigger select external channel 5 */
LPTIM_TRIGSEL_EXT6 = 6U, /**< Trigger select external channel 6 */
LPTIM_TRIGSEL_EXT7 = 7U, /**< Trigger select external channel 7 */
} lptim_trigsel_t;
/**
* @brief LPTIM start mode select
*/
typedef enum
{
LPTIM_MODE_SINGLE = 0, /**< Start single mode */
LPTIM_MODE_CONTINUOUS = 1, /**< Start continuous mode */
typedef enum {
LPTIM_MODE_SINGLE = 0U, /**< Start single mode */
LPTIM_MODE_CONTINUOUS = 1U, /**< Start continuous mode */
} lptim_mode_t;
/**
* @brief LPTIM trig en
*/
typedef enum
{
LPTIM_TRIGEN_SW = 0, /**< software trigger */
LPTIM_TRIGEN_RISING = 1, /**< rising edge trigger */
LPTIM_TRIGEN_FALLING = 2, /**< falling edge trigger */
LPTIM_TRIGEN_BOTH = 3, /**< rising and falling edge trigger */
typedef enum {
LPTIM_TRIGEN_SW = 0U, /**< software trigger */
LPTIM_TRIGEN_RISING = 1U, /**< rising edge trigger */
LPTIM_TRIGEN_FALLING = 2U, /**< falling edge trigger */
LPTIM_TRIGEN_BOTH = 3U, /**< rising and falling edge trigger */
} lptim_trigen_t;
/**
* @brief LPTIM wave
*/
typedef enum
{
LPTIM_WAVE_NONE = 0, /**< Output close */
LPTIM_WAVE_TOGGLE = 1, /**< Output toggle */
LPTIM_WAVE_PULSE = 2, /**< Output pulse */
LPTIM_WAVE_PWM = 3, /**< Output PWM */
typedef enum {
LPTIM_WAVE_NONE = 0U, /**< Output close */
LPTIM_WAVE_TOGGLE = 1U, /**< Output toggle */
LPTIM_WAVE_PULSE = 2U, /**< Output pulse */
LPTIM_WAVE_PWM = 3U, /**< Output PWM */
} lptim_wave_t;
/**
* @brief LPTIM interrupt
*/
typedef enum
{
LPTIM_IT_CMPMAT = 1, /**< Compare interrupt bit */
LPTIM_IT_ARRMAT = 2, /**< Update interrupt bit */
LPTIM_IT_EXTTRIG = 4, /**< external trigger interrupt bit */
typedef enum {
LPTIM_IT_CMPMAT = 1U, /**< Compare interrupt bit */
LPTIM_IT_ARRMAT = 2U, /**< Update interrupt bit */
LPTIM_IT_EXTTRIG = 4U, /**< external trigger interrupt bit */
} lptim_it_t;
/**
* @brief LPTIM Interrupt flag
*/
typedef enum
{
LPTIM_FLAG_CMPMAT = 1, /**< Compare interrupt flag */
LPTIM_FLAG_ARRMAT = 2, /**< Update interrupt flag */
LPTIM_FLAG_EXTTRIG = 4, /**< Update interrupt flag */
typedef enum {
LPTIM_FLAG_CMPMAT = 1U, /**< Compare interrupt flag */
LPTIM_FLAG_ARRMAT = 2U, /**< Update interrupt flag */
LPTIM_FLAG_EXTTRIG = 4U, /**< Update interrupt flag */
} lptim_flag_t;
/**
* @brief LPTIM state structures definition
*/
typedef enum
{
LPTIM_STATE_RESET = 0x00, /**< Peripheral not yet initialized or disabled */
LPTIM_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
LPTIM_STATE_BUSY = 0x02, /**< An internal process is ongoing */
LPTIM_STATE_TIMEOUT = 0x03, /**< Timeout state */
LPTIM_STATE_ERROR = 0x04, /**< Reception process is ongoing */
typedef enum {
LPTIM_STATE_RESET = 0x00U, /**< Peripheral not yet initialized or disabled */
LPTIM_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
LPTIM_STATE_BUSY = 0x02U, /**< An internal process is ongoing */
LPTIM_STATE_TIMEOUT = 0x03U, /**< Timeout state */
LPTIM_STATE_ERROR = 0x04U, /**< Reception process is ongoing */
} lptim_state_t;
/**
* @brief LPTIM Init Structure definition
*/
typedef struct
{
typedef struct {
lptim_presc_t psc; /**< Specifies the prescaler value */
uint16_t arr; /**< Specifies the update value */
uint16_t cmp; /**< Specifies the compare value */
@ -186,8 +173,7 @@ typedef struct
/**
* @brief LPTIM trigger Structure definition
*/
typedef struct
{
typedef struct {
lptim_trigen_t mode; /**< Specifies the trigger mode */
lptim_trigsel_t sel; /**< Specifies the trigger source select */
} lptim_trigger_init_t;
@ -195,8 +181,7 @@ typedef struct
/**
* @brief LPTIM trigger Structure definition
*/
typedef struct
{
typedef struct {
lptim_cksel_t sel; /**< Specifies the clock select */
lptim_ckpol_t polarity; /**< Specifies the clock polarity */
} lptim_clock_source_init_t;
@ -204,8 +189,7 @@ typedef struct
/**
* @brief LPTIM Handle Structure definition
*/
typedef struct lptim_handle_s
{
typedef struct lptim_handle_s {
LPTIM_TypeDef *perh; /**< Register base address */
lptim_init_t init; /**< LPTIM Time required parameters */
lock_state_t lock; /**< Locking object */
@ -303,6 +287,18 @@ void ald_lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt);
/** @addtogroup LPTIM_Public_Functions_Group2
* @{
*/
ald_status_t ald_lptim_base_init(lptim_handle_t *hperh);
void ald_lptim_base_start(lptim_handle_t *hperh);
void ald_lptim_base_stop(lptim_handle_t *hperh);
void ald_lptim_base_start_by_it(lptim_handle_t *hperh);
void ald_lptim_base_stop_by_it(lptim_handle_t *hperh);
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group3
* @{
*/
ald_status_t ald_lptim_toggle_init(lptim_handle_t *hperh);
void ald_lptim_toggle_start(lptim_handle_t *hperh);
void ald_lptim_toggle_stop(lptim_handle_t *hperh);
@ -312,7 +308,7 @@ void ald_lptim_toggle_stop_by_it(lptim_handle_t *hperh);
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group3
/** @addtogroup LPTIM_Public_Functions_Group4
* @{
*/
ald_status_t ald_lptim_pulse_init(lptim_handle_t *hperh);
@ -324,7 +320,7 @@ void ald_lptim_pulse_stop_by_it(lptim_handle_t *hperh);
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group4
/** @addtogroup LPTIM_Public_Functions_Group5
* @{
*/
ald_status_t ald_lptim_pwm_init(lptim_handle_t *hperh);
@ -336,7 +332,7 @@ void ald_lptim_pwm_stop_by_it(lptim_handle_t *hperh);
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group5
/** @addtogroup LPTIM_Public_Functions_Group6
* @{
*/
void ald_lptim_irq_handler(lptim_handle_t *hperh);
@ -348,7 +344,7 @@ void ald_lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag);
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group6
/** @addtogroup LPTIM_Public_Functions_Group7
* @{
*/
lptim_state_t ald_lptim_get_state(lptim_handle_t *hperh);

123
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lpuart.h
View File

@ -126,88 +126,80 @@ extern "C" {
/**
* @brief LPUART Word Length
*/
typedef enum
{
LPUART_WORD_LENGTH_5B = 0x0, /**< 5-bits */
LPUART_WORD_LENGTH_6B = 0x1, /**< 6-bits */
LPUART_WORD_LENGTH_7B = 0x2, /**< 7-bits */
LPUART_WORD_LENGTH_8B = 0x3, /**< 8-bits */
LPUART_WORD_LENGTH_9B = 0x4, /**< 9-bits */
typedef enum {
LPUART_WORD_LENGTH_5B = 0x0U, /**< 5-bits */
LPUART_WORD_LENGTH_6B = 0x1U, /**< 6-bits */
LPUART_WORD_LENGTH_7B = 0x2U, /**< 7-bits */
LPUART_WORD_LENGTH_8B = 0x3U, /**< 8-bits */
LPUART_WORD_LENGTH_9B = 0x4U, /**< 9-bits */
} lpuart_word_length_t;
/**
* @brief LPUART Stop Bits
*/
typedef enum
{
LPUART_STOP_BITS_1 = 0x0, /**< 1-bits */
LPUART_STOP_BITS_2 = 0x1, /**< 2-bits */
typedef enum {
LPUART_STOP_BITS_1 = 0x0U, /**< 1-bits */
LPUART_STOP_BITS_2 = 0x1U, /**< 2-bits */
} lpuart_stop_bits_t;
/**
* @brief LPUART Parity
*/
typedef enum
{
LPUART_PARITY_NONE = 0x0, /**< Not parity */
LPUART_PARITY_ODD = 0x1, /**< Odd parity */
LPUART_PARITY_EVEN = 0x3, /**< Even parity */
typedef enum {
LPUART_PARITY_NONE = 0x0U, /**< Not parity */
LPUART_PARITY_ODD = 0x1U, /**< Odd parity */
LPUART_PARITY_EVEN = 0x3U, /**< Even parity */
} lpuart_parity_t;
/**
* @brief LPUART Mode
*/
typedef enum
{
LPUART_MODE_UART = 0x0, /**< UART */
LPUART_MODE_IrDA = 0x2, /**< IrDA */
LPUART_MODE_RS485 = 0x3, /**< RS485 */
typedef enum {
LPUART_MODE_UART = 0x0U, /**< UART */
LPUART_MODE_IrDA = 0x2U, /**< IrDA */
LPUART_MODE_RS485 = 0x3U, /**< RS485 */
} lpuart_mode_t;
/**
* @brief LPUART Hardware Flow Control
*/
typedef enum
{
LPUART_HW_FLOW_CTL_NONE = 0x0, /**< None */
LPUART_HW_FLOW_CTL_RTS = 0x1, /**< RTS */
LPUART_HW_FLOW_CTL_CTS = 0x2, /**< CTS */
LPUART_HW_FLOW_CTL_RTS_CTS = 0x3, /**< RTS & CTS */
typedef enum {
LPUART_HW_FLOW_CTL_NONE = 0x0U, /**< None */
LPUART_HW_FLOW_CTL_RTS = 0x1U, /**< RTS */
LPUART_HW_FLOW_CTL_CTS = 0x2U, /**< CTS */
LPUART_HW_FLOW_CTL_RTS_CTS = 0x3U, /**< RTS & CTS */
} lpuart_hw_flow_ctl_t;
/**
* @brief ALD LPUART State
*/
typedef enum
{
LPUART_STATE_RESET = 0x00, /**< Peripheral is not initialized */
LPUART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
LPUART_STATE_BUSY = 0x02, /**< an internal process is ongoing */
LPUART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */
LPUART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */
LPUART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */
LPUART_STATE_TIMEOUT = 0x03, /**< Timeout state */
LPUART_STATE_ERROR = 0x04, /**< Error */
typedef enum {
LPUART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */
LPUART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
LPUART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
LPUART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */
LPUART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */
LPUART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */
LPUART_STATE_TIMEOUT = 0x03U, /**< Timeout state */
LPUART_STATE_ERROR = 0x04U, /**< Error */
} lpuart_state_t;
/**
* @brief LPUART Error Codes
*/
typedef enum
{
LPUART_ERROR_NONE = ((uint32_t)0x00), /**< No error */
LPUART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */
LPUART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */
LPUART_ERROR_FE = ((uint32_t)0x04), /**< frame error */
LPUART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */
LPUART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */
typedef enum {
LPUART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */
LPUART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */
LPUART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */
LPUART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */
LPUART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */
LPUART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */
} lpuart_error_t;
/**
* @brief LPUART Init structure definition
*/
typedef struct
{
typedef struct {
uint32_t baud; /**< Specifies the lpuart communication baud rate */
lpuart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */
lpuart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */
@ -220,8 +212,7 @@ typedef struct
/**
* @brief LPUART handle structure definition
*/
typedef struct lpuart_handle_s
{
typedef struct lpuart_handle_s {
LPUART_TypeDef *perh; /**< LPUART registers base address */
lpuart_init_t init; /**< LPUART communication parameters */
uint8_t *tx_buf; /**< Pointer to LPUART Tx transfer Buffer */
@ -246,8 +237,7 @@ typedef struct lpuart_handle_s
/**
* @brief LPUART RS485 Configure Structure definition
*/
typedef struct
{
typedef struct {
type_func_t RS485_NMM; /**< Normal Point Mode */
type_func_t RS485_AAD; /**< Auto-Address Detect */
type_func_t RS485_AUD; /**< Auto-Direction Mode */
@ -258,28 +248,25 @@ typedef struct
/**
* @brief LPUART DMA Requests
*/
typedef enum
{
LPUART_DMA_REQ_TX = 0x0, /**< TX dma */
LPUART_DMA_REQ_RX = 0x1, /**< RX dma */
typedef enum {
LPUART_DMA_REQ_TX = 0x0U, /**< TX dma */
LPUART_DMA_REQ_RX = 0x1U, /**< RX dma */
} lpuart_dma_req_t;
/**
* @brief LPUART RXFIFO size
*/
typedef enum
{
LPUART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */
LPUART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */
LPUART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */
LPUART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */
typedef enum {
LPUART_RXFIFO_1BYTE = 0x0U, /**< 1-Byte */
LPUART_RXFIFO_4BYTE = 0x1U, /**< 4-Bytes */
LPUART_RXFIFO_8BYTE = 0x2U, /**< 8-Bytes */
LPUART_RXFIFO_14BYTE = 0x3U, /**< 14-Bytes */
} lpuart_rxfifo_t;
/**
* @brief LPUART Interrupts Types
*/
typedef enum
{
typedef enum {
LPUART_IT_RBR = (1U << 0), /**< RBR */
LPUART_IT_TBEMP = (1U << 1), /**< TBEMP */
LPUART_IT_CTSDET = (1U << 2), /**< CTSDET */
@ -298,8 +285,7 @@ typedef enum
/**
* @brief LPUART Flags Types
*/
typedef enum
{
typedef enum {
LPUART_IF_RBR = (1U << 0), /**< RBR */
LPUART_IF_TBEMP = (1U << 1), /**< TBEMP */
LPUART_IF_CTSDET = (1U << 2), /**< CTSDET */
@ -318,8 +304,7 @@ typedef enum
/**
* @brief LPUART Status Types
*/
typedef enum
{
typedef enum {
LPUART_STAT_RXEMP = (1U << 6), /**< RX FIFO empty */
LPUART_STAT_RXFULL = (1U << 7), /**< RX FIFO full */
LPUART_STAT_TXEMP = (1U << 14), /**< TX FIFO empty */
@ -395,8 +380,8 @@ typedef enum
((x) == LPUART_STAT_CTSSTAT) || \
((x) == LPUART_STAT_RTSSTAT))
#define LPUART_STATE_TX_MASK (1 << 4)
#define LPUART_STATE_RX_MASK (1 << 5)
#define LPUART_STATE_TX_MASK (1U << 4)
#define LPUART_STATE_RX_MASK (1U << 5)
/**
* @}
*/

525
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pis.h
View File

@ -18,7 +18,7 @@
#define __ALD_PIS_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@ -37,327 +37,277 @@ extern "C" {
*/
/**
* @brief Producer entry
* @note ES32F065x:
* AD16C4T0--TIMER0
* GP16C4T0--TIMER6
* GP16C2T0--TIMER2
* GP16C2T1--TIMER3
* BS16T0----TIMER1
* BS16T1----TIMER4
* BS16T2----TIMER5
* BS16T3----TIMER7
*
* ES32F033x:
* ES32F093x:
* GP16C4T0--TIMER0
* GP16C4T1--TIMER6
* GP16C2T0--TIMER2
* GP16C2T1--TIMER3
* BS16T0----TIMER1
* BS16T1----TIMER4
* BS16T2----TIMER5
* BS16T3----TIMER7
* @verbatim
In this module, for the convenience of code maintenance,
TIMERx is used to indicate the sequence of the timer peripheral.
Different product series TIMERx represent different meanings:
1. For ES32F065x series:
TIMER0 ----> AD16C4T0
TIMER1 ----> BS16T0
TIMER2 ----> GP16C2T0
TIMER3 ----> GP16C2T1
2. For ES32F033x/ES32F093x series:
TIMER0 ----> GP16C4T0
TIMER1 ----> BS16T0
TIMER2 ----> GP16C2T0
TIMER3 ----> GP16C2T1
@endverbatim
*/
typedef enum
{
PIS_NON = 0x0, /**< No async */
PIS_GPIO_PIN0 = 0x10, /**< Pin0, level,support async */
PIS_GPIO_PIN1 = 0x11, /**< Pin1, level,support async */
PIS_GPIO_PIN2 = 0x12, /**< Pin2, level,support async */
PIS_GPIO_PIN3 = 0x13, /**< Pin3, level,support async */
PIS_GPIO_PIN4 = 0x14, /**< Pin4, level,support async */
PIS_GPIO_PIN5 = 0x15, /**< Pin5, level,support async */
PIS_GPIO_PIN6 = 0x16, /**< Pin6, level,support async */
PIS_GPIO_PIN7 = 0x17, /**< Pin7, level,support async */
PIS_GPIO_PIN8 = 0x18, /**< Pin8, level,support async */
PIS_GPIO_PIN9 = 0x19, /**< Pin9, level,support async */
PIS_GPIO_PIN10 = 0x1a, /**< Pin10, level,support async */
PIS_GPIO_PIN11 = 0x1b, /**< Pin11, level,support async */
PIS_GPIO_PIN12 = 0x1c, /**< Pin12, level,support async */
PIS_GPIO_PIN13 = 0x1d, /**< Pin13, level,support async */
PIS_GPIO_PIN14 = 0x1e, /**< Pin14, level,support async */
PIS_GPIO_PIN15 = 0x1f, /**< Pin15, level,support async */
PIS_ACMP_OUT0 = 0x30, /**< Acmp0 output, level,support async */
PIS_ACMP_OUT1 = 0x31, /**< Acmp1 output, level,support async */
PIS_DAC0_CH0 = 0x40, /**< Dac0 channel 0, pclk2 pulse,support async */
PIS_DAC0_CH1 = 0x41, /**< Dac0 channel 1, pclk2 pulse,support async */
PIS_ADC0_INJECT = 0x60, /**< Adc0 inject, pclk2 pulse,support async */
PIS_ADC0_REGULAT = 0x61, /**< Adc0 regulat, pclk2 pulse,support async */
PIS_ADC0_WINDOW = 0x62, /**< Adc0 window, no have */
PIS_LVD = 0x70, /**< Lvd, level,support async */
PIS_UART0_ASY_SEND = 0x80, /**< Uart0 asy send, pulse,support async */
PIS_UART0_ASY_RECV = 0x81, /**< Uart0 asy recv, pulse,support async */
PIS_UART0_IRDAOUT = 0x82, /**< Uart0 irdaout, level,support async */
PIS_UART0_RTSOUT = 0x83, /**< Uart0 rtsout, level,support async */
PIS_UART0_TXOUT = 0x84, /**< Uart0 txout, level,support async */
PIS_UART0_SYN_SEND = 0x85, /**< Uart0 syn send, pulse,support async */
PIS_UART0_SYN_RECV = 0x86, /**< Uart0 syn recv, pulse,support async */
PIS_UART1_ASY_SEND = 0x90, /**< Uart1 asy send, pulse,support async */
PIS_UART1_ASY_RECV = 0x91, /**< Uart1 asy recv, pulse,support async */
PIS_UART1_IRDA = 0x92, /**< Uart1 irdaout, level,support async */
PIS_UART1_RTS = 0x93, /**< Uart1 rtsout, level,support async */
PIS_UART1_TXOUT = 0x94, /**< Uart1 txout, level,support async */
PIS_UART1_SYN_SEND = 0x95, /**< Uart1 syn send, pulse,support async */
PIS_UART1_SYN_RECV = 0x96, /**< Uart1 syn recv, pulse,support async */
PIS_UART2_ASY_SEND = 0xa0, /**< Uart2 asy send, pulse,support async */
PIS_UART2_ASY_RECV = 0xa1, /**< Uart2 asy recv, pulse,support async */
PIS_UART2_IRDA = 0xa2, /**< Uart2 irdaout, level,support async */
PIS_UART2_RTS = 0xa3, /**< Uart2 rtsout, level,support async */
PIS_UART2_TXOUT = 0xa4, /**< Uart2 txout, level,support async */
PIS_UART2_SYN_SEND = 0xa5, /**< Uart2 syn send, pulse,support async */
PIS_UART2_SYN_RECV = 0xa6, /**< Uart2 syn recv, pulse,support async */
PIS_UART3_ASY_SEND = 0xb1, /**< Uart3 asy send, pulse,support async */
PIS_UART3_ASY_RECV = 0xb2, /**< Uart3 asy recv, pulse,support async */
PIS_UART3_IRDA = 0xb3, /**< Uart3 irdaout, level,support async */
PIS_UART3_RTS = 0xb4, /**< Uart3 rtsout, level,support async */
PIS_UART3_TXOUT = 0xb5, /**< Uart3 txout, level,support async */
PIS_UART3_SYN_SEND = 0xb6, /**< Uart3 syn send, pulse,support async */
PIS_UART3_SYN_RECV = 0xb7, /**< Uart3 syn recv, pulse,support async */
PIS_EUART0_RECV = 0xc0, /**< Euart0 recv, plck1 pulse */
PIS_EUART0_SEND = 0xc1, /**< Euart0 send, plck1 pulse */
PIS_EUART0_TXOUT = 0xc2, /**< Euart0 txout, plck1 level */
PIS_EUART1_RECV = 0xd0, /**< Euart1 recv, plck1 pulse */
PIS_EUART1_SEND = 0xd1, /**< Euart1 send, plck1 pulse */
PIS_EUART1_TXOUT = 0xd2, /**< Euart1 txout, plck1 level */
PIS_SPI0_RECV = 0xe0, /**< Spi0 recv, plck1 pulse */
PIS_SPI0_SEND = 0xe1, /**< Spi0 send, plck1 pulse */
PIS_SPI0_NE = 0xe2, /**< Spi0 ne, plck1 level */
PIS_SPI1_RECV = 0xf0, /**< Spi1 recv, plck1 pulse */
PIS_SPI1_SEND = 0xf1, /**< Spi1 send, plck1 pulse */
PIS_SPI1_NE = 0xf2, /**< Spi1 ne, plck1 level */
PIS_I2C0_RECV = 0x100, /**< I2c0 recv, plck1 level */
PIS_I2C0_SEND = 0x101, /**< I2c0 send, plck1 level */
PIS_I2C1_RECV = 0x110, /**< I2c1 recv, plck1 level */
PIS_I2C1_SEND = 0x111, /**< I2c1 send, plck1 level */
PIS_TIMER0_UPDATA = 0x120, /**< Timer0 updata, plck1 pulse */
PIS_TIMER0_TRIG = 0x121, /**< Timer0 trig, plck1 pulse */
PIS_TIMER0_INPUT = 0x122, /**< Timer0 input, plck1 pulse */
PIS_TIMER0_OUTPUT = 0x123, /**< Timer0 output, plck1 pulse */
PIS_TIMER1_UPDATA = 0x130, /**< Timer1 updata, plck1 pulse */
PIS_TIMER1_TRIG = 0x131, /**< Timer1 trig, plck1 pulse */
PIS_TIMER1_INPUT = 0x132, /**< Timer1 input, plck1 pulse */
PIS_TIMER1_OUTPUT = 0x133, /**< Timer1 output, plck1 pulse */
PIS_TIMER2_UPDATA = 0x140, /**< Timer2 updata, plck1 pulse */
PIS_TIMER2_TRIG = 0x141, /**< Timer2 trig, plck1 pulse */
PIS_TIMER2_INPUT = 0x142, /**< Timer2 input, plck1 pulse */
PIS_TIMER2_OUTPUT = 0x143, /**< Timer2 output, plck1 pulse */
PIS_TIMER3_UPDATA = 0x150, /**< Timer0 updata, plck1 pulse */
PIS_TIMER3_TRIG = 0x151, /**< Timer0 trig, plck1 pulse */
PIS_TIMER3_INPUT = 0x152, /**< Timer0 input, plck1 pulse */
PIS_TIMER3_OUTPUT = 0x153, /**< Timer0 output, plck1 pulse */
PIS_RTC_CLOCK = 0x160, /**< Rtc clock, pulse,support async */
PIS_RTC_ALARM = 0x161, /**< Rtc alarm, pulse,support async */
PIS_LPTIM0_SYN_UPDATA = 0x170, /**< Lptimer0 syn updata, pulse,support async */
PIS_LPTIM0_ASY_UPDATA = 0x171, /**< Lptimer0 asy updata, pulse,support async */
PIS_LPUART0_ASY_RECV = 0x180, /**< Lpuart0 asy recv, pulse,support async */
PIS_LPUART0_ASY_SEND = 0x181, /**< Lpuart0 asy send, pulse,support async */
PIS_LPUART0_SYN_RECV = 0x182, /**< Lpuart0 syn recv, pulse,support async */
PIS_LPUART0_SYN_SEND = 0x183, /**< Lpuart0 syn recv, pulse,support async */
PIS_DMA = 0x190, /**< Dma, pulse,support async */
PIS_ADC1_INJECT = 0x1a0, /**< Adc1 inject, pclk2 pulse,support async */
PIS_ADC1_REGULAT = 0x1a1, /**< Adc1 regulat, pclk2 pulse,support async */
PIS_ADC1_WINDOW = 0x1a2, /**< Adc1 window, no have */
typedef enum {
PIS_NON = 0x0U, /**< No async */
PIS_GPIO_PIN0 = 0x10U, /**< Pin0, level,support async */
PIS_GPIO_PIN1 = 0x11U, /**< Pin1, level,support async */
PIS_GPIO_PIN2 = 0x12U, /**< Pin2, level,support async */
PIS_GPIO_PIN3 = 0x13U, /**< Pin3, level,support async */
PIS_GPIO_PIN4 = 0x14U, /**< Pin4, level,support async */
PIS_GPIO_PIN5 = 0x15U, /**< Pin5, level,support async */
PIS_GPIO_PIN6 = 0x16U, /**< Pin6, level,support async */
PIS_GPIO_PIN7 = 0x17U, /**< Pin7, level,support async */
PIS_GPIO_PIN8 = 0x18U, /**< Pin8, level,support async */
PIS_GPIO_PIN9 = 0x19U, /**< Pin9, level,support async */
PIS_GPIO_PIN10 = 0x1aU, /**< Pin10, level,support async */
PIS_GPIO_PIN11 = 0x1bU, /**< Pin11, level,support async */
PIS_GPIO_PIN12 = 0x1cU, /**< Pin12, level,support async */
PIS_GPIO_PIN13 = 0x1dU, /**< Pin13, level,support async */
PIS_GPIO_PIN14 = 0x1eU, /**< Pin14, level,support async */
PIS_GPIO_PIN15 = 0x1fU, /**< Pin15, level,support async */
PIS_ACMP_OUT0 = 0x30U, /**< Acmp0 output, level,support async */
PIS_ACMP_OUT1 = 0x31U, /**< Acmp1 output, level,support async */
PIS_DAC0_CH0 = 0x40U, /**< Dac0 channel 0, pclk2 pulse,support async */
PIS_DAC0_CH1 = 0x41U, /**< Dac0 channel 1, pclk2 pulse,support async */
PIS_ADC0_INJECT = 0x60U, /**< Adc0 inject, pclk2 pulse,support async */
PIS_ADC0_REGULAT = 0x61U, /**< Adc0 regulat, pclk2 pulse,support async */
PIS_ADC0_WINDOW = 0x62U, /**< Adc0 window, no have */
PIS_LVD = 0x70U, /**< Lvd, level,support async */
PIS_UART0_ASY_SEND = 0x80U, /**< Uart0 asy send, pulse,support async */
PIS_UART0_ASY_RECV = 0x81U, /**< Uart0 asy recv, pulse,support async */
PIS_UART0_IRDAOUT = 0x82U, /**< Uart0 irdaout, level,support async */
PIS_UART0_RTSOUT = 0x83U, /**< Uart0 rtsout, level,support async */
PIS_UART0_TXOUT = 0x84U, /**< Uart0 txout, level,support async */
PIS_UART0_SYN_SEND = 0x85U, /**< Uart0 syn send, pulse,support async */
PIS_UART0_SYN_RECV = 0x86U, /**< Uart0 syn recv, pulse,support async */
PIS_UART1_ASY_SEND = 0x90U, /**< Uart1 asy send, pulse,support async */
PIS_UART1_ASY_RECV = 0x91U, /**< Uart1 asy recv, pulse,support async */
PIS_UART1_IRDA = 0x92U, /**< Uart1 irdaout, level,support async */
PIS_UART1_RTS = 0x93U, /**< Uart1 rtsout, level,support async */
PIS_UART1_TXOUT = 0x94U, /**< Uart1 txout, level,support async */
PIS_UART1_SYN_SEND = 0x95U, /**< Uart1 syn send, pulse,support async */
PIS_UART1_SYN_RECV = 0x96U, /**< Uart1 syn recv, pulse,support async */
PIS_UART2_ASY_SEND = 0xa0U, /**< Uart2 asy send, pulse,support async */
PIS_UART2_ASY_RECV = 0xa1U, /**< Uart2 asy recv, pulse,support async */
PIS_UART2_IRDA = 0xa2U, /**< Uart2 irdaout, level,support async */
PIS_UART2_RTS = 0xa3U, /**< Uart2 rtsout, level,support async */
PIS_UART2_TXOUT = 0xa4U, /**< Uart2 txout, level,support async */
PIS_UART2_SYN_SEND = 0xa5U, /**< Uart2 syn send, pulse,support async */
PIS_UART2_SYN_RECV = 0xa6U, /**< Uart2 syn recv, pulse,support async */
PIS_UART3_ASY_SEND = 0xb1U, /**< Uart3 asy send, pulse,support async */
PIS_UART3_ASY_RECV = 0xb2U, /**< Uart3 asy recv, pulse,support async */
PIS_UART3_IRDA = 0xb3U, /**< Uart3 irdaout, level,support async */
PIS_UART3_RTS = 0xb4U, /**< Uart3 rtsout, level,support async */
PIS_UART3_TXOUT = 0xb5U, /**< Uart3 txout, level,support async */
PIS_UART3_SYN_SEND = 0xb6U, /**< Uart3 syn send, pulse,support async */
PIS_UART3_SYN_RECV = 0xb7U, /**< Uart3 syn recv, pulse,support async */
PIS_EUART0_RECV = 0xc0U, /**< Euart0 recv, plck1 pulse */
PIS_EUART0_SEND = 0xc1U, /**< Euart0 send, plck1 pulse */
PIS_EUART0_TXOUT = 0xc2U, /**< Euart0 txout, plck1 level */
PIS_EUART1_RECV = 0xd0U, /**< Euart1 recv, plck1 pulse */
PIS_EUART1_SEND = 0xd1U, /**< Euart1 send, plck1 pulse */
PIS_EUART1_TXOUT = 0xd2U, /**< Euart1 txout, plck1 level */
PIS_SPI0_RECV = 0xe0U, /**< Spi0 recv, plck1 pulse */
PIS_SPI0_SEND = 0xe1U, /**< Spi0 send, plck1 pulse */
PIS_SPI0_NE = 0xe2U, /**< Spi0 ne, plck1 level */
PIS_SPI1_RECV = 0xf0U, /**< Spi1 recv, plck1 pulse */
PIS_SPI1_SEND = 0xf1U, /**< Spi1 send, plck1 pulse */
PIS_SPI1_NE = 0xf2U, /**< Spi1 ne, plck1 level */
PIS_I2C0_RECV = 0x100U, /**< I2c0 recv, plck1 level */
PIS_I2C0_SEND = 0x101U, /**< I2c0 send, plck1 level */
PIS_I2C1_RECV = 0x110U, /**< I2c1 recv, plck1 level */
PIS_I2C1_SEND = 0x111U, /**< I2c1 send, plck1 level */
PIS_TIMER0_UPDATA = 0x120U, /**< Timer0 updata, plck1 pulse */
PIS_TIMER0_TRIG = 0x121U, /**< Timer0 trig, plck1 pulse */
PIS_TIMER0_INPUT = 0x122U, /**< Timer0 input, plck1 pulse */
PIS_TIMER0_OUTPUT = 0x123U, /**< Timer0 output, plck1 pulse */
PIS_TIMER1_UPDATA = 0x130U, /**< Timer1 updata, plck1 pulse */
PIS_TIMER1_TRIG = 0x131U, /**< Timer1 trig, plck1 pulse */
PIS_TIMER1_INPUT = 0x132U, /**< Timer1 input, plck1 pulse */
PIS_TIMER1_OUTPUT = 0x133U, /**< Timer1 output, plck1 pulse */
PIS_TIMER2_UPDATA = 0x140U, /**< Timer2 updata, plck1 pulse */
PIS_TIMER2_TRIG = 0x141U, /**< Timer2 trig, plck1 pulse */
PIS_TIMER2_INPUT = 0x142U, /**< Timer2 input, plck1 pulse */
PIS_TIMER2_OUTPUT = 0x143U, /**< Timer2 output, plck1 pulse */
PIS_TIMER3_UPDATA = 0x150U, /**< Timer0 updata, plck1 pulse */
PIS_TIMER3_TRIG = 0x151U, /**< Timer0 trig, plck1 pulse */
PIS_TIMER3_INPUT = 0x152U, /**< Timer0 input, plck1 pulse */
PIS_TIMER3_OUTPUT = 0x153U, /**< Timer0 output, plck1 pulse */
PIS_RTC_CLOCK = 0x160U, /**< Rtc clock, pulse,support async */
PIS_RTC_ALARM = 0x161U, /**< Rtc alarm, pulse,support async */
PIS_LPTIM0_SYN_UPDATA = 0x170U, /**< Lptimer0 syn updata, pulse,support async */
PIS_LPTIM0_ASY_UPDATA = 0x171U, /**< Lptimer0 asy updata, pulse,support async */
PIS_LPUART0_ASY_RECV = 0x180U, /**< Lpuart0 asy recv, pulse,support async */
PIS_LPUART0_ASY_SEND = 0x181U, /**< Lpuart0 asy send, pulse,support async */
PIS_LPUART0_SYN_RECV = 0x182U, /**< Lpuart0 syn recv, pulse,support async */
PIS_LPUART0_SYN_SEND = 0x183U, /**< Lpuart0 syn recv, pulse,support async */
PIS_DMA = 0x190U, /**< Dma, pulse,support async */
PIS_ADC1_INJECT = 0x1a0U, /**< Adc1 inject, pclk2 pulse,support async */
PIS_ADC1_REGULAT = 0x1a1U, /**< Adc1 regulat, pclk2 pulse,support async */
PIS_ADC1_WINDOW = 0x1a2U, /**< Adc1 window, no have */
} pis_src_t;
/**
* @brief Consumer entry
* @note ES32F065x:
* AD16C4T0--TIMER0
* GP16C4T0--TIMER6
* GP16C2T0--TIMER2
* GP16C2T1--TIMER3
* BS16T0----TIMER1
* BS16T1----TIMER4
* BS16T2----TIMER5
* BS16T3----TIMER7
*
* ES32F033x:
* ES32F093x:
* GP16C4T0--TIMER0
* GP16C4T1--TIMER6
* GP16C2T0--TIMER2
* GP16C2T1--TIMER3
* BS16T0----TIMER1
* BS16T1----TIMER4
* BS16T2----TIMER5
* BS16T3----TIMER7
*/
typedef enum
{
PIS_CH0_TIMER0_BRKIN = 0x0400, /**< Timer0 brkin */
PIS_CH0_SPI1_CLK = 0x0F10, /**< Spi1 clk */
PIS_CH0_LPTIM0_EXT0 = 0x0030, /**< Lptimer0 ext0 */
PIS_CH0_ADC1_NORMAL = 0x0030, /**< Adc1 normal */
PIS_CH1_TIMER0_CH1IN = 0x0001, /**< Timer0 ch1in */
PIS_CH1_TIMER2_CH1IN = 0x1001, /**< Timer2 ch1in */
PIS_CH1_TIMER3_CH1IN = 0x1801, /**< Timer3 ch1in */
PIS_CH1_LPTIM0_EXT1 = 0x0031, /**< Lptime0 ext1 */
PIS_CH1_UART0_RX_IRDA = 0x0011, /**< Uart0 rx irda */
PIS_CH1_ADC1_INSERT = 0x0031, /**< Adc1 insert */
PIS_CH2_TIMER0_CH2IN = 0x0102, /**< Timer0 ch2in */
PIS_CH2_TIMER2_CH2IN = 0x1102, /**< Timer2 ch2in */
PIS_CH2_TIMER3_CH2IN = 0x1902, /**< Timer3 ch2in */
PIS_CH2_LPTIM0_EXT2 = 0x0032, /**< Lptime0 ext2 */
PIS_CH2_UART1_RX_IRDA = 0x0112, /**< Uart1 rx irda */
PIS_CH3_TIMER0_CH3IN = 0x0203, /**< Timer0 ch3in */
PIS_CH3_LPTIM0_EXT3 = 0x0033, /**< Lptime0 ext3 */
PIS_CH3_UART2_RX_IRDA = 0x0213, /**< Uart2 rx irda */
PIS_CH4_TIMER0_CH4IN = 0x0004, /**< Timer0 ch4in */
PIS_CH4_TIMER0_ITR0 = 0x0034, /**< Timer0 itr0 */
PIS_CH4_TIMER2_ITR0 = 0x0034, /**< Timer2 itr0 */
PIS_CH4_TIMER3_ITR0 = 0x0034, /**< Timer3 itr0 */
PIS_CH4_LPTIM0_EXT4 = 0x0434, /**< Lptime0 ext4 */
PIS_CH4_UART3_RX_IRDA = 0x0314, /**< Uart3 rx irda */
PIS_CH5_SPI0_RX = 0x0C15, /**< Spi0 rx */
PIS_CH5_LPTIM0_EXT5 = 0x0035, /**< Lptime0 ext5 */
PIS_CH5_EUART0_RX = 0x0615, /**< Euart0 rx */
PIS_CH5_TIMER0_ITR1 = 0x0035, /**< Timer0 itr1 */
PIS_CH5_TIMER2_ITR1 = 0x0035, /**< Timer2 itr1 */
PIS_CH5_TIMER3_ITR1 = 0x0035, /**< Timer3 itr1 */
PIS_CH6_SPI0_CLK = 0x0D16, /**< Spi0 clk */
PIS_CH6_ADC0_NORMAL = 0x0036, /**< Adc0 normal */
PIS_CH6_LPTIM0_EXT6 = 0x0036, /**< Lptime0 ext6 */
PIS_CH6_EUART1_RX = 0x0716, /**< Euart1 rx */
PIS_CH6_TIMER0_ITR2 = 0x0036, /**< Timer0 itr2 */
PIS_CH6_TIMER2_ITR2 = 0x0036, /**< Timer2 itr2 */
PIS_CH6_TIMER3_ITR2 = 0x0036, /**< Timer3 itr2 */
PIS_CH6_DAC_CH1 = 0x0036, /**< Dac channel 1 */
PIS_CH7_SPI1_RX = 0x0E17, /**< Spi1 rx */
PIS_CH7_ADC0_INSERT = 0x0037, /**< Adc0 insert */
PIS_CH7_LPTIM0_EXT7 = 0x0037, /**< Lptime0 ext7 */
PIS_CH7_DMA = 0x0037, /**< Dma */
PIS_CH7_TIMER0_ITR3 = 0x0037, /**< Timer0 itr3 */
PIS_CH7_TIMER2_ITR3 = 0x0037, /**< Timer2 itr3 */
PIS_CH7_TIMER3_ITR3 = 0x0037, /**< Timer3 itr3 */
PIS_CH7_LPUART_RX = 0x0817, /**< Lpuart rx */
PIS_CH7_DAC_CH0 = 0x0037, /**< Dac channel 0 */
typedef enum {
PIS_CH0_TIMER0_BRKIN = 0x0400U, /**< Timer0 brkin */
PIS_CH0_SPI1_CLK = 0x0F10U, /**< Spi1 clk */
PIS_CH0_LPTIM0_EXT0 = 0x0030U, /**< Lptimer0 ext0 */
PIS_CH0_ADC1_NORMAL = 0x0030U, /**< Adc1 normal */
PIS_CH1_TIMER0_CH1IN = 0x0001U, /**< Timer0 ch1in */
PIS_CH1_TIMER2_CH1IN = 0x1001U, /**< Timer2 ch1in */
PIS_CH1_TIMER3_CH1IN = 0x1801U, /**< Timer3 ch1in */
PIS_CH1_LPTIM0_EXT1 = 0x0031U, /**< Lptime0 ext1 */
PIS_CH1_UART0_RX_IRDA = 0x0011U, /**< Uart0 rx irda */
PIS_CH1_ADC1_INSERT = 0x0031U, /**< Adc1 insert */
PIS_CH2_TIMER0_CH2IN = 0x0102U, /**< Timer0 ch2in */
PIS_CH2_TIMER2_CH2IN = 0x1102U, /**< Timer2 ch2in */
PIS_CH2_TIMER3_CH2IN = 0x1902U, /**< Timer3 ch2in */
PIS_CH2_LPTIM0_EXT2 = 0x0032U, /**< Lptime0 ext2 */
PIS_CH2_UART1_RX_IRDA = 0x0112U, /**< Uart1 rx irda */
PIS_CH3_TIMER0_CH3IN = 0x0203U, /**< Timer0 ch3in */
PIS_CH3_LPTIM0_EXT3 = 0x0033U, /**< Lptime0 ext3 */
PIS_CH3_UART2_RX_IRDA = 0x0213U, /**< Uart2 rx irda */
PIS_CH4_TIMER0_CH4IN = 0x0004U, /**< Timer0 ch4in */
PIS_CH4_TIMER0_ITR0 = 0x0034U, /**< Timer0 itr0 */
PIS_CH4_TIMER2_ITR0 = 0x0034U, /**< Timer2 itr0 */
PIS_CH4_TIMER3_ITR0 = 0x0034U, /**< Timer3 itr0 */
PIS_CH4_LPTIM0_EXT4 = 0x0434U, /**< Lptime0 ext4 */
PIS_CH4_UART3_RX_IRDA = 0x0314U, /**< Uart3 rx irda */
PIS_CH5_SPI0_RX = 0x0C15U, /**< Spi0 rx */
PIS_CH5_LPTIM0_EXT5 = 0x0035U, /**< Lptime0 ext5 */
PIS_CH5_EUART0_RX = 0x0615U, /**< Euart0 rx */
PIS_CH5_TIMER0_ITR1 = 0x0035U, /**< Timer0 itr1 */
PIS_CH5_TIMER2_ITR1 = 0x0035U, /**< Timer2 itr1 */
PIS_CH5_TIMER3_ITR1 = 0x0035U, /**< Timer3 itr1 */
PIS_CH6_SPI0_CLK = 0x0D16U, /**< Spi0 clk */
PIS_CH6_ADC0_NORMAL = 0x0036U, /**< Adc0 normal */
PIS_CH6_LPTIM0_EXT6 = 0x0036U, /**< Lptime0 ext6 */
PIS_CH6_EUART1_RX = 0x0716U, /**< Euart1 rx */
PIS_CH6_TIMER0_ITR2 = 0x0036U, /**< Timer0 itr2 */
PIS_CH6_TIMER2_ITR2 = 0x0036U, /**< Timer2 itr2 */
PIS_CH6_TIMER3_ITR2 = 0x0036U, /**< Timer3 itr2 */
PIS_CH6_DAC_CH1 = 0x0036U, /**< Dac channel 1 */
PIS_CH7_SPI1_RX = 0x0E17U, /**< Spi1 rx */
PIS_CH7_ADC0_INSERT = 0x0037U, /**< Adc0 insert */
PIS_CH7_LPTIM0_EXT7 = 0x0037U, /**< Lptime0 ext7 */
PIS_CH7_DMA = 0x0037U, /**< Dma */
PIS_CH7_TIMER0_ITR3 = 0x0037U, /**< Timer0 itr3 */
PIS_CH7_TIMER2_ITR3 = 0x0037U, /**< Timer2 itr3 */
PIS_CH7_TIMER3_ITR3 = 0x0037U, /**< Timer3 itr3 */
PIS_CH7_LPUART_RX = 0x0817U, /**< Lpuart rx */
PIS_CH7_DAC_CH0 = 0x0037U, /**< Dac channel 0 */
} pis_trig_t;
/**
* @brief Clock select
*/
typedef enum
{
PIS_CLK_PCLK1 = 0, /**< Pclock1 */
PIS_CLK_PCLK2 = 1, /**< Pclock2 */
PIS_CLK_SYS = 2, /**< Sys clock */
PIS_CLK_LP = 3, /**< Low power clock */
typedef enum {
PIS_CLK_PCLK1 = 0U, /**< Pclock1 */
PIS_CLK_PCLK2 = 1U, /**< Pclock2 */
PIS_CLK_SYS = 2U, /**< Sys clock */
PIS_CLK_LP = 3U, /**< Low power clock */
} pis_clock_t;
/**
* @brief Level select
*/
typedef enum
{
PIS_EDGE_NONE = 0, /**< None edge */
PIS_EDGE_UP = 1, /**< Up edge */
PIS_EDGE_DOWN = 2, /**< Down edge */
PIS_EDGE_UP_DOWN = 3, /**< Up and down edge */
typedef enum {
PIS_EDGE_NONE = 0U, /**< None edge */
PIS_EDGE_UP = 1U, /**< Up edge */
PIS_EDGE_DOWN = 2U, /**< Down edge */
PIS_EDGE_UP_DOWN = 3U, /**< Up and down edge */
} pis_edge_t;
/**
* @brief Output style
*/
typedef enum
{
PIS_OUT_LEVEL = 0, /**< Level */
PIS_OUT_PULSE = 1, /**< Pulse */
typedef enum {
PIS_OUT_LEVEL = 0U, /**< Level */
PIS_OUT_PULSE = 1U, /**< Pulse */
} pis_output_t;
/**
* @brief Sync select
*/
typedef enum
{
PIS_SYN_DIRECT = 0, /**< Direct */
PIS_SYN_ASY_PCLK1 = 1, /**< Asy pclk1 */
PIS_SYN_ASY_PCLK2 = 2, /**< Asy pclk2 */
PIS_SYN_ASY_PCLK = 3, /**< Asy pclk */
PIS_SYN_PCLK2_PCLK1 = 4, /**< Pclk2 to pclk1 */
PIS_SYN_PCLK1_PCLK2 = 5, /**< Pclk1 to pclk2 */
PIS_SYN_PCLK12_SYS = 6, /**< Pclk1 or pclk2 to sysclk */
typedef enum {
PIS_SYN_DIRECT = 0U, /**< Direct */
PIS_SYN_ASY_PCLK1 = 1U, /**< Asy pclk1 */
PIS_SYN_ASY_PCLK2 = 2U, /**< Asy pclk2 */
PIS_SYN_ASY_PCLK = 3U, /**< Asy pclk */
PIS_SYN_PCLK2_PCLK1 = 4U, /**< Pclk2 to pclk1 */
PIS_SYN_PCLK1_PCLK2 = 5U, /**< Pclk1 to pclk2 */
PIS_SYN_PCLK12_SYS = 6U, /**< Pclk1 or pclk2 to sysclk */
} pis_syncsel_t;
/**
* @brief Pis channel
*/
typedef enum
{
PIS_CH_0 = 0, /**< Channel 0 */
PIS_CH_1 = 1, /**< Channel 1 */
PIS_CH_2 = 2, /**< Channel 2 */
PIS_CH_3 = 3, /**< Channel 3 */
PIS_CH_4 = 4, /**< Channel 4 */
PIS_CH_5 = 5, /**< Channel 5 */
PIS_CH_6 = 6, /**< Channel 6 */
PIS_CH_7 = 7, /**< Channel 7 */
typedef enum {
PIS_CH_0 = 0U, /**< Channel 0 */
PIS_CH_1 = 1U, /**< Channel 1 */
PIS_CH_2 = 2U, /**< Channel 2 */
PIS_CH_3 = 3U, /**< Channel 3 */
PIS_CH_4 = 4U, /**< Channel 4 */
PIS_CH_5 = 5U, /**< Channel 5 */
PIS_CH_6 = 6U, /**< Channel 6 */
PIS_CH_7 = 7U, /**< Channel 7 */
} pis_ch_t;
/**
* @brief Pis output channel
*/
typedef enum
{
PIS_OUT_CH_0 = 0, /**< Channel 0 */
PIS_OUT_CH_1 = 1, /**< Channel 1 */
PIS_OUT_CH_2 = 2, /**< Channel 2 */
PIS_OUT_CH_3 = 3, /**< Channel 3 */
typedef enum {
PIS_OUT_CH_0 = 0U, /**< Channel 0 */
PIS_OUT_CH_1 = 1U, /**< Channel 1 */
PIS_OUT_CH_2 = 2U, /**< Channel 2 */
PIS_OUT_CH_3 = 3U, /**< Channel 3 */
} pis_out_ch_t;
/**
* @brief Indirect value,no care of it.
*/
typedef enum
{
PIS_CON_0 = 0, /**< Con 0 */
PIS_CON_1 = 1, /**< Con 1 */
PIS_CON_NONE = 2, /**< None */
typedef enum {
PIS_CON_0 = 0U, /**< Con 0 */
PIS_CON_1 = 1U, /**< Con 1 */
PIS_CON_NONE = 2U, /**< None */
} pis_con_t;
/**
* @brief Indirect value,no care of it.
*/
typedef union
{
struct
{
uint8_t ch : 4; /**< Channel */
uint8_t con : 4; /**< Contorl */
uint8_t shift : 8; /**< Shift */
};
uint16_t HalfWord;
} pis_divide_t;
/**
* @brief PIS state structures definition
*/
typedef enum
{
PIS_STATE_RESET = 0x00, /**< Peripheral is not initialized */
PIS_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
PIS_STATE_BUSY = 0x02, /**< An internal process is ongoing */
PIS_STATE_TIMEOUT = 0x03, /**< Timeout state */
PIS_STATE_ERROR = 0x04, /**< Error */
typedef enum {
PIS_STATE_RESET = 0x00U, /**< Peripheral is not initialized */
PIS_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
PIS_STATE_BUSY = 0x02U, /**< An internal process is ongoing */
PIS_STATE_TIMEOUT = 0x03U, /**< Timeout state */
PIS_STATE_ERROR = 0x04U, /**< Error */
} pis_state_t;
/**
* @brief PIS modulate target
*/
typedef enum
{
PIS_UART0_TX = 0, /**< Modulate uart0 tx */
PIS_UART1_TX = 1, /**< Modulate uart1 tx */
PIS_UART2_TX = 2, /**< Modulate uart2 tx */
PIS_UART3_TX = 3, /**< Modulate uart3 tx */
PIS_LPUART0_TX = 4, /**< Modulate lpuart0 tx */
typedef enum {
PIS_UART0_TX = 0U, /**< Modulate uart0 tx */
PIS_UART1_TX = 1U, /**< Modulate uart1 tx */
PIS_UART2_TX = 2U, /**< Modulate uart2 tx */
PIS_UART3_TX = 3U, /**< Modulate uart3 tx */
PIS_LPUART0_TX = 4U, /**< Modulate lpuart0 tx */
} pis_modu_targ_t;
/**
* @brief PIS modulate level
*/
typedef enum
{
PIS_LOW_LEVEL = 0, /**< Modulate low level */
PIS_HIGH_LEVEL = 1, /**< Modulate high level */
typedef enum {
PIS_LOW_LEVEL = 0U, /**< Modulate low level */
PIS_HIGH_LEVEL = 1U, /**< Modulate high level */
} pis_modu_level_t;
/**
@ -383,35 +333,32 @@ typedef enum
* BS16T2----TIMER5
* BS16T3----TIMER7
*/
typedef enum
{
PIS_SRC_NONE = 0, /**< Stop modulate */
PIS_SRC_TIMER0 = 1, /**< Modulate source is TIMER0 */
PIS_SRC_TIMER1 = 2, /**< Modulate source is TIMER1 */
PIS_SRC_TIMER2 = 3, /**< Modulate source is TIMER2 */
PIS_SRC_TIMER3 = 4, /**< Modulate source is TIMER3 */
PIS_SRC_TIMER6 = 5, /**< Modulate source is TIMER6 */
PIS_SRC_TIMER7 = 6, /**< Modulate source is TIMER7 */
PIS_SRC_LPTIM0 = 7, /**< Modulate source is LPTIM0 */
PIS_SRC_BUZ = 8, /**< Modulate source is buz */
typedef enum {
PIS_SRC_NONE = 0U, /**< Stop modulate */
PIS_SRC_TIMER0 = 1U, /**< Modulate source is TIMER0 */
PIS_SRC_TIMER1 = 2U, /**< Modulate source is TIMER1 */
PIS_SRC_TIMER2 = 3U, /**< Modulate source is TIMER2 */
PIS_SRC_TIMER3 = 4U, /**< Modulate source is TIMER3 */
PIS_SRC_TIMER6 = 5U, /**< Modulate source is TIMER6 */
PIS_SRC_TIMER7 = 6U, /**< Modulate source is TIMER7 */
PIS_SRC_LPTIM0 = 7U, /**< Modulate source is LPTIM0 */
PIS_SRC_BUZ = 8U, /**< Modulate source is buz */
} pis_modu_src_t;
/**
* @brief PIS modulate channel
*/
typedef enum
{
PIS_TIMER_CH1 = 0, /**< Src is TIMERx and choose channel 1 */
PIS_TIMER_CH2 = 1, /**< Src is TIMERx and choose channel 2 */
PIS_TIMER_CH3 = 2, /**< Src is TIMERx and choose channel 3 */
PIS_TIMER_CH4 = 3, /**< Src is TIMERx and choose channel 4 */
typedef enum {
PIS_TIMER_CH1 = 0U, /**< Src is TIMERx and choose channel 1 */
PIS_TIMER_CH2 = 1U, /**< Src is TIMERx and choose channel 2 */
PIS_TIMER_CH3 = 2U, /**< Src is TIMERx and choose channel 3 */
PIS_TIMER_CH4 = 3U, /**< Src is TIMERx and choose channel 4 */
} pis_modu_channel_t;
/**
* @brief PIS init structure definition
*/
typedef struct
{
typedef struct {
pis_src_t producer_src; /**< Producer entry */
pis_clock_t producer_clk; /**< Producer module clock */
pis_edge_t producer_edge; /**< Producer module pin output edge */
@ -422,8 +369,7 @@ typedef struct
/**
* @brief PIS modulate config structure definition
*/
typedef struct
{
typedef struct {
pis_modu_targ_t target; /**< Modulate target */
pis_modu_level_t level; /**< Modulate level */
pis_modu_src_t src; /**< Modulate src */
@ -433,8 +379,7 @@ typedef struct
/**
* @brief PIS Handle Structure definition
*/
typedef struct pis_handle_s
{
typedef struct pis_handle_s {
PIS_TypeDef *perh; /**< Register base address */
pis_init_t init; /**< PIS required parameters */
pis_ch_t consumer_ch; /**< Indirect value, no care of it */

110
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pmu.h
View File

@ -23,6 +23,7 @@ extern "C" {
#include "utils.h"
#include "ald_syscfg.h"
#include "ald_bkpc.h"
/** @addtogroup ES32FXXX_ALD
@ -37,66 +38,66 @@ extern "C" {
* @{
*/
#define PMU_SRAM0_ENABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define PMU_SRAM0_DISABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define PMU_SRAM1_ENABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define PMU_SRAM1_DISABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define PMU_BXCAN_ENABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define PMU_BXCAN_DISABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define PMU_LPSTOP_ENABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define PMU_LPSTOP_DISABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define PMU_MTSTOP_ENABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define PMU_MTSTOP_DISABLE() \
do { \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS))
/**
@ -110,57 +111,54 @@ extern "C" {
/**
* @brief Low power mode
*/
typedef enum
{
PMU_LP_STOP1 = 0x0, /**< Stop1 */
PMU_LP_STOP2 = 0x1, /**< Stop2 */
typedef enum {
PMU_LP_STOP1 = 0x0U, /**< Stop1 */
PMU_LP_STOP2 = 0x1U, /**< Stop2 */
PMU_LP_STANDBY = 0x2U, /**< Standby */
} pmu_lp_mode_t;
typedef enum
{
typedef enum {
PMU_SR_WUF = (1U << 0),
PMU_SR_STANDBY = (1U << 1),
} pmu_status_t;
/**
* @brief LVD voltage select
*/
typedef enum
{
PMU_LVD_VOL_SEL_2_0 = 0x0, /**< 2.0V ~ 2.05V */
PMU_LVD_VOL_SEL_2_1 = 0x1, /**< 2.1V ~ 2.15V */
PMU_LVD_VOL_SEL_2_2 = 0x2, /**< 2.2V ~ 2.25V */
PMU_LVD_VOL_SEL_2_4 = 0x3, /**< 2.4V ~ 2.45V */
PMU_LVD_VOL_SEL_2_6 = 0x4, /**< 2.6V ~ 2.65V */
PMU_LVD_VOL_SEL_2_8 = 0x5, /**< 2.8V ~ 2.85V */
PMU_LVD_VOL_SEL_3_0 = 0x6, /**< 3.0V ~ 3.05V */
PMU_LVD_VOL_SEL_3_6 = 0x7, /**< 3.6V ~ 3.65V */
PMU_LVD_VOL_SEL_4_0 = 0x8, /**< 4.0V ~ 4.05V */
PMU_LVD_VOL_SEL_4_6 = 0x9, /**< 4.6V ~ 4.65V */
PMU_LVD_VOL_SEL_2_3 = 0xA, /**< 2.3V ~ 2.35V */
PMU_LVD_VOL_SEL_EXT = 0xF, /**< Select external input. It must be 1.2V */
typedef enum {
PMU_LVD_VOL_SEL_2_0 = 0x0U, /**< 2.0V ~ 2.05V */
PMU_LVD_VOL_SEL_2_1 = 0x1U, /**< 2.1V ~ 2.15V */
PMU_LVD_VOL_SEL_2_2 = 0x2U, /**< 2.2V ~ 2.25V */
PMU_LVD_VOL_SEL_2_4 = 0x3U, /**< 2.4V ~ 2.45V */
PMU_LVD_VOL_SEL_2_6 = 0x4U, /**< 2.6V ~ 2.65V */
PMU_LVD_VOL_SEL_2_8 = 0x5U, /**< 2.8V ~ 2.85V */
PMU_LVD_VOL_SEL_3_0 = 0x6U, /**< 3.0V ~ 3.05V */
PMU_LVD_VOL_SEL_3_6 = 0x7U, /**< 3.6V ~ 3.65V */
PMU_LVD_VOL_SEL_4_0 = 0x8U, /**< 4.0V ~ 4.05V */
PMU_LVD_VOL_SEL_4_6 = 0x9U, /**< 4.6V ~ 4.65V */
PMU_LVD_VOL_SEL_2_3 = 0xAU, /**< 2.3V ~ 2.35V */
PMU_LVD_VOL_SEL_EXT = 0xFU, /**< Select external input. It must be 1.2V */
} pmu_lvd_voltage_sel_t;
/**
* @brief LVD trigger mode
*/
typedef enum
{
PMU_LVD_TRIGGER_RISING_EDGE = 0x0, /**< Rising edge */
PMU_LVD_TRIGGER_FALLING_EDGE = 0x1, /**< Falling edge */
PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2, /**< High level */
PMU_LVD_TRIGGER_LOW_LEVEL = 0x3, /**< Low level */
PMU_LVD_TRIGGER_RISING_FALLING = 0x4, /**< Rising and falling edge */
typedef enum {
PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, /**< Rising edge */
PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, /**< Falling edge */
PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, /**< High level */
PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U, /**< Low level */
PMU_LVD_TRIGGER_RISING_FALLING = 0x4U, /**< Rising and falling edge */
} pmu_lvd_trigger_mode_t;
/**
* @brief LDO output voltage selest in low power mode
*/
typedef enum
{
PMU_LDO_LPMODE_OUTPUT_1_5 = 0x0, /**< 1.5V */
PMU_LDO_LPMODE_OUTPUT_1_4 = 0x1, /**< 1.4V */
PMU_LDO_LPMODE_OUTPUT_1_3 = 0x2, /**< 1.3V */
PMU_LDO_LPMODE_OUTPUT_1_2 = 0x4, /**< 1.2V */
typedef enum {
PMU_LDO_LPMODE_OUTPUT_1_5 = 0x0U, /**< 1.5V */
PMU_LDO_LPMODE_OUTPUT_1_4 = 0x1U, /**< 1.4V */
PMU_LDO_LPMODE_OUTPUT_1_3 = 0x2U, /**< 1.3V */
PMU_LDO_LPMODE_OUTPUT_1_2 = 0x4U, /**< 1.2V */
} pmu_ldo_lpmode_output_t;
/**
* @}
@ -171,8 +169,9 @@ typedef enum
* @{
*/
#define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \
((x) == PMU_LP_STOP2))
#define IS_PMU_STATUS(x) ((x) == PMU_SR_WUF)
((x) == PMU_LP_STOP2) || \
((x) == PMU_LP_STANDBY))
#define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || ((x) == PMU_SR_STANDBY))
#define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_0) || \
((x) == PMU_LVD_VOL_SEL_2_1) || \
((x) == PMU_LVD_VOL_SEL_2_2) || \
@ -218,6 +217,7 @@ __STATIC_INLINE__ void ald_pmu_sleep_deep()
void ald_pmu_stop1_enter(void);
void ald_pmu_stop2_enter(void);
void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state);
flag_status_t ald_pmu_get_status(pmu_status_t sr);
void ald_pmu_clear_status(pmu_status_t sr);

127
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rmu.h
View File

@ -37,45 +37,42 @@ extern "C" {
/**
* @brief RMU BOR fliter
*/
typedef enum
{
RMU_BORFLT_1 = 0x1, /**< 1 cycle */
RMU_BORFLT_2 = 0x2, /**< 2 cycles */
RMU_BORFLT_3 = 0x3, /**< 3 cycles */
RMU_BORFLT_4 = 0x4, /**< 4 cycles */
RMU_BORFLT_5 = 0x5, /**< 5 cycles */
RMU_BORFLT_6 = 0x6, /**< 6 cycles */
RMU_BORFLT_7 = 0x7, /**< 7 cycles */
typedef enum {
RMU_BORFLT_1 = 0x1U, /**< 1 cycle */
RMU_BORFLT_2 = 0x2U, /**< 2 cycles */
RMU_BORFLT_3 = 0x3U, /**< 3 cycles */
RMU_BORFLT_4 = 0x4U, /**< 4 cycles */
RMU_BORFLT_5 = 0x5U, /**< 5 cycles */
RMU_BORFLT_6 = 0x6U, /**< 6 cycles */
RMU_BORFLT_7 = 0x7U, /**< 7 cycles */
} rmu_bor_filter_t;
/**
* @brief RMU BOR voltage
*/
typedef enum
{
RMU_VOL_1_7 = 0x0, /**< 1.7V */
RMU_VOL_2_0 = 0x1, /**< 2.0V */
RMU_VOL_2_1 = 0x2, /**< 2.1V */
RMU_VOL_2_2 = 0x3, /**< 2.2V */
RMU_VOL_2_3 = 0x4, /**< 2.3V */
RMU_VOL_2_4 = 0x5, /**< 2.4V */
RMU_VOL_2_5 = 0x6, /**< 2.5V */
RMU_VOL_2_6 = 0x7, /**< 2.6V */
RMU_VOL_2_8 = 0x8, /**< 2.8V */
RMU_VOL_3_0 = 0x9, /**< 3.0V */
RMU_VOL_3_1 = 0xA, /**< 3.1V */
RMU_VOL_3_3 = 0xB, /**< 3.3V */
RMU_VOL_3_6 = 0xC, /**< 3.6V */
RMU_VOL_3_7 = 0xD, /**< 3.7V */
RMU_VOL_4_0 = 0xE, /**< 4.0V */
RMU_VOL_4_3 = 0xF, /**< 4.3V */
typedef enum {
RMU_VOL_1_8 = 0x0U, /**< 1.8V */
RMU_VOL_2_0 = 0x1U, /**< 2.0V */
RMU_VOL_2_2 = 0x2U, /**< 2.2V */
RMU_VOL_2_4 = 0x3U, /**< 2.4V */
RMU_VOL_2_6 = 0x4U, /**< 2.6V */
RMU_VOL_2_8 = 0x5U, /**< 2.8V */
RMU_VOL_3_0 = 0x6U, /**< 3.0V */
RMU_VOL_3_2 = 0x7U, /**< 3.2V */
RMU_VOL_3_4 = 0x8U, /**< 3.4V */
RMU_VOL_3_6 = 0x9U, /**< 3.6V */
RMU_VOL_3_8 = 0xAU, /**< 3.8V */
RMU_VOL_4_0 = 0xBU, /**< 4.0V */
RMU_VOL_4_2 = 0xCU, /**< 4.2V */
RMU_VOL_4_4 = 0xDU, /**< 4.4V */
RMU_VOL_4_6 = 0xEU, /**< 4.6V */
RMU_VOL_4_8 = 0xFU, /**< 4.8V */
} rmu_bor_vol_t;
/**
* @brief RMU reset status
*/
typedef enum
{
typedef enum {
RMU_RST_POR = (1U << 0), /**< POR */
RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */
RMU_RST_BOR = (1U << 2), /**< BOR */
@ -88,33 +85,37 @@ typedef enum
RMU_RST_CPU = (1U << 9), /**< CPU */
RMU_RST_CFG = (1U << 10), /**< CFG */
RMU_RST_CFGERR = (1U << 16), /**< CFG Error */
RMU_RST_ALL = (0xFFFFFU), /**< ALL */
} rmu_state_t;
/**
* @brief RMU periperal select bit
* @note ES32F065x:
* AD16C4T0--TIMER0
* GP16C4T0--TIMER6
* GP16C2T0--TIMER2
* GP16C2T1--TIMER3
* BS16T0----TIMER1
* BS16T1----TIMER4
* BS16T2----TIMER5
* BS16T3----TIMER7
*
* ES32F033x:
* ES32F093x:
* GP16C4T0--TIMER0
* GP16C4T1--TIMER6
* GP16C2T0--TIMER2
* GP16C2T1--TIMER3
* BS16T0----TIMER1
* BS16T1----TIMER4
* BS16T2----TIMER5
* BS16T3----TIMER7
* @verbatim
In this module, for the convenience of code maintenance,
TIMERx is used to indicate the sequence of the timer peripheral.
Different product series TIMERx represent different meanings:
1. For ES32F065x series:
TIMER0 ----> AD16C4T0
TIMER1 ----> BS16T0
TIMER2 ----> GP16C2T0
TIMER3 ----> GP16C2T1
TIMER4 ----> BS16T1
TIMER5 ----> BS16T2
TIMER6 ----> GP16C4T0
TIMER7 ----> BS16T3
2. For ES32F033x/ES32F093x series:
TIMER0 ----> GP16C4T0
TIMER1 ----> BS16T0
TIMER2 ----> GP16C2T0
TIMER3 ----> GP16C2T1
TIMER4 ----> BS16T1
TIMER5 ----> BS16T2
TIMER6 ----> GP16C4T1
TIMER7 ----> BS16T3
@endverbatim
*/
typedef enum
{
typedef enum {
RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */
RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */
RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */
@ -174,22 +175,22 @@ typedef enum
((x) == RMU_BORFLT_5) || \
((x) == RMU_BORFLT_6) || \
((x) == RMU_BORFLT_7))
#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_7) || \
#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_8) || \
((x) == RMU_VOL_2_0) || \
((x) == RMU_VOL_2_1) || \
((x) == RMU_VOL_2_2) || \
((x) == RMU_VOL_2_3) || \
((x) == RMU_VOL_2_4) || \
((x) == RMU_VOL_2_5) || \
((x) == RMU_VOL_2_6) || \
((x) == RMU_VOL_2_8) || \
((x) == RMU_VOL_3_0) || \
((x) == RMU_VOL_3_1) || \
((x) == RMU_VOL_3_3) || \
((x) == RMU_VOL_3_2) || \
((x) == RMU_VOL_3_4) || \
((x) == RMU_VOL_3_6) || \
((x) == RMU_VOL_3_7) || \
((x) == RMU_VOL_3_8) || \
((x) == RMU_VOL_4_0) || \
((x) == RMU_VOL_4_3))
((x) == RMU_VOL_4_2) || \
((x) == RMU_VOL_4_4) || \
((x) == RMU_VOL_4_6) || \
((x) == RMU_VOL_4_8))
#define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \
((x) == RMU_RST_WAKEUP) || \
((x) == RMU_RST_BOR) || \
@ -201,7 +202,8 @@ typedef enum
((x) == RMU_RST_MCU) || \
((x) == RMU_RST_CPU) || \
((x) == RMU_RST_CFG) || \
((x) == RMU_RST_CFGERR))
((x) == RMU_RST_CFGERR) || \
((x) == RMU_RST_ALL))
#define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \
((x) == RMU_RST_WAKEUP) || \
((x) == RMU_RST_BOR) || \
@ -212,7 +214,8 @@ typedef enum
((x) == RMU_RST_CHIP) || \
((x) == RMU_RST_MCU) || \
((x) == RMU_RST_CPU) || \
((x) == RMU_RST_CFG))
((x) == RMU_RST_CFG) || \
((x) == RMU_RST_ALL))
#define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \
((x) == RMU_PERH_CRC) || \
((x) == RMU_PERH_CALC) || \
@ -264,7 +267,7 @@ typedef enum
* @{
*/
void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state);
flag_status_t ald_rmu_get_reset_status(rmu_state_t state);
uint32_t ald_rmu_get_reset_status(rmu_state_t state);
void ald_rmu_clear_reset_status(rmu_state_t state);
void ald_rmu_reset_periperal(rmu_peripheral_t perh);
/**

306
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rtc.h
View File

@ -38,37 +38,33 @@ extern "C" {
/**
* @brief Hours format
*/
typedef enum
{
RTC_HOUR_FORMAT_24 = 0x0, /**< 24-hours format */
RTC_HOUR_FORMAT_12 = 0x1, /**< 12-hours format */
typedef enum {
RTC_HOUR_FORMAT_24 = 0x0U, /**< 24-hours format */
RTC_HOUR_FORMAT_12 = 0x1U, /**< 12-hours format */
} rtc_hour_format_t;
/**
* @brief Output mode
*/
typedef enum
{
RTC_OUTPUT_DISABLE = 0x0, /**< Disable output */
RTC_OUTPUT_ALARM_A = 0x1, /**< Output alarm_a signal */
RTC_OUTPUT_ALARM_B = 0x2, /**< Output alarm_b signal */
RTC_OUTPUT_WAKEUP = 0x3, /**< Output wakeup signal */
typedef enum {
RTC_OUTPUT_DISABLE = 0x0U, /**< Disable output */
RTC_OUTPUT_ALARM_A = 0x1U, /**< Output alarm_a signal */
RTC_OUTPUT_ALARM_B = 0x2U, /**< Output alarm_b signal */
RTC_OUTPUT_WAKEUP = 0x3U, /**< Output wakeup signal */
} rtc_output_select_t;
/**
* @brief Output polarity
*/
typedef enum
{
RTC_OUTPUT_POLARITY_HIGH = 0x0, /**< Polarity is high */
RTC_OUTPUT_POLARITY_LOW = 0x0, /**< Polarity is low */
typedef enum {
RTC_OUTPUT_POLARITY_HIGH = 0x0U, /**< Polarity is high */
RTC_OUTPUT_POLARITY_LOW = 0x1U, /**< Polarity is low */
} rtc_output_polarity_t;
/**
* @brief Initialization structure
*/
typedef struct
{
typedef struct {
rtc_hour_format_t hour_format; /**< Hours format */
uint32_t asynch_pre_div; /**< Asynchronous predivider value */
uint32_t synch_pre_div; /**< Synchronous predivider value */
@ -79,19 +75,17 @@ typedef struct
/**
* @brief Source select
*/
typedef enum
{
RTC_SOURCE_LOSC = 0x0, /**< LOSC */
RTC_SOURCE_LRC = 0x1, /**< LRC */
RTC_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */
RTC_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */
typedef enum {
RTC_SOURCE_LOSC = 0x0U, /**< LOSC */
RTC_SOURCE_LRC = 0x1U, /**< LRC */
RTC_SOURCE_HRC_DIV_1M = 0x2U, /**< HRC divide to 1MHz */
RTC_SOURCE_HOSC_DIV_1M = 0x3U, /**< HOSC divide to 1MHz */
} rtc_source_sel_t;
/**
* @brief Time structure
*/
typedef struct
{
typedef struct {
uint8_t hour; /**< Hours */
uint8_t minute; /**< Minutes */
uint8_t second; /**< Seconds */
@ -101,8 +95,7 @@ typedef struct
/**
* @brief Date structure
*/
typedef struct
{
typedef struct {
uint8_t week; /**< Weeks */
uint8_t day; /**< days */
uint8_t month; /**< months */
@ -112,78 +105,71 @@ typedef struct
/**
* @brief Data format
*/
typedef enum
{
RTC_FORMAT_DEC = 0,
RTC_FORMAT_BCD = 1,
typedef enum {
RTC_FORMAT_DEC = 0U, /**< DEC format */
RTC_FORMAT_BCD = 1U, /**< BCD format */
} rtc_format_t;
/**
* @brief Index of alarm
*/
typedef enum
{
RTC_ALARM_A = 0x0, /**< Alarm-A */
RTC_ALARM_B = 0x1, /**< Alarm-B */
typedef enum {
RTC_ALARM_A = 0x0U, /**< Alarm-A */
RTC_ALARM_B = 0x1U, /**< Alarm-B */
} rtc_alarm_idx_t;
/**
* @brief Alarm mask
*/
typedef enum
{
RTC_ALARM_MASK_NONE = 0x0, /**< Mask is disable */
typedef enum {
RTC_ALARM_MASK_NONE = 0x0U, /**< Mask is disable */
RTC_ALARM_MASK_WEEK_DAY = (1U << 30), /**< Mask week or day */
RTC_ALARM_MASK_HOUR = (1U << 23), /**< Mask hour */
RTC_ALARM_MASK_MINUTE = (1U << 15), /**< Mask minute */
RTC_ALARM_MASK_SECOND = (1U << 7), /**< Mask second */
RTC_ALARM_MASK_ALL = 0x40808080, /**< Mask all */
RTC_ALARM_MASK_ALL = 0x40808080U, /**< Mask all */
} rtc_alarm_mask_t;
/**
* @brief Alarm sub-second mask
*/
typedef enum
{
RTC_ALARM_SS_MASK_NONE = 0xF, /**< Mask is disable */
RTC_ALARM_SS_MASK_14_1 = 0x1, /**< Mask bit(1-14) */
RTC_ALARM_SS_MASK_14_2 = 0x2, /**< Mask bit(2-14) */
RTC_ALARM_SS_MASK_14_3 = 0x3, /**< Mask bit(3-14) */
RTC_ALARM_SS_MASK_14_4 = 0x4, /**< Mask bit(4-14) */
RTC_ALARM_SS_MASK_14_5 = 0x5, /**< Mask bit(5-14) */
RTC_ALARM_SS_MASK_14_6 = 0x6, /**< Mask bit(6-14) */
RTC_ALARM_SS_MASK_14_7 = 0x7, /**< Mask bit(7-14) */
RTC_ALARM_SS_MASK_14_8 = 0x8, /**< Mask bit(8-14) */
RTC_ALARM_SS_MASK_14_9 = 0x9, /**< Mask bit(9-14) */
RTC_ALARM_SS_MASK_14_10 = 0xA, /**< Mask bit(10-14) */
RTC_ALARM_SS_MASK_14_11 = 0xB, /**< Mask bit(11-14) */
RTC_ALARM_SS_MASK_14_12 = 0xC, /**< Mask bit(12-14) */
RTC_ALARM_SS_MASK_14_13 = 0xD, /**< Mask bit(13-14) */
RTC_ALARM_SS_MASK_14 = 0xE, /**< Mask bit14 */
RTC_ALARM_SS_MASK_ALL = 0x0, /**< Mask bit(0-14) */
typedef enum {
RTC_ALARM_SS_MASK_NONE = 0xFU, /**< Mask is disable */
RTC_ALARM_SS_MASK_14_1 = 0x1U, /**< Mask bit(1-14) */
RTC_ALARM_SS_MASK_14_2 = 0x2U, /**< Mask bit(2-14) */
RTC_ALARM_SS_MASK_14_3 = 0x3U, /**< Mask bit(3-14) */
RTC_ALARM_SS_MASK_14_4 = 0x4U, /**< Mask bit(4-14) */
RTC_ALARM_SS_MASK_14_5 = 0x5U, /**< Mask bit(5-14) */
RTC_ALARM_SS_MASK_14_6 = 0x6U, /**< Mask bit(6-14) */
RTC_ALARM_SS_MASK_14_7 = 0x7U, /**< Mask bit(7-14) */
RTC_ALARM_SS_MASK_14_8 = 0x8U, /**< Mask bit(8-14) */
RTC_ALARM_SS_MASK_14_9 = 0x9U, /**< Mask bit(9-14) */
RTC_ALARM_SS_MASK_14_10 = 0xAU, /**< Mask bit(10-14) */
RTC_ALARM_SS_MASK_14_11 = 0xBU, /**< Mask bit(11-14) */
RTC_ALARM_SS_MASK_14_12 = 0xCU, /**< Mask bit(12-14) */
RTC_ALARM_SS_MASK_14_13 = 0xDU, /**< Mask bit(13-14) */
RTC_ALARM_SS_MASK_14 = 0xEU, /**< Mask bit14 */
RTC_ALARM_SS_MASK_ALL = 0x0U, /**< Mask bit(0-14) */
} rtc_sub_second_mask_t;
/**
* @brief Alarm select week or day */
typedef enum
{
RTC_SELECT_DAY = 0x0, /**< Alarm select day */
RTC_SELECT_WEEK = 0x1, /**< Alarm select week */
typedef enum {
RTC_SELECT_DAY = 0x0U, /**< Alarm select day */
RTC_SELECT_WEEK = 0x1U, /**< Alarm select week */
} rtc_week_day_sel_t;
/**
* @brief Alarm structure
*/
typedef struct
{
typedef struct {
rtc_alarm_idx_t idx; /**< Index of alarm */
rtc_time_t time; /**< Time structure */
uint32_t mask; /**< Alarm mask */
rtc_sub_second_mask_t ss_mask; /**< Alarm sub-second mask */
rtc_week_day_sel_t sel; /**< Select week or day */
union
{
union {
uint8_t week; /**< Alarm select week */
uint8_t day; /**< Alarm select day */
};
@ -192,70 +178,63 @@ typedef struct
/**
* @brief Time stamp signel select
*/
typedef enum
{
RTC_TS_SIGNAL_SEL_TAMPER0 = 0, /**< Select tamper0 */
RTC_TS_SIGNAL_SEL_TAMPER1 = 1, /**< Select tamper1 */
typedef enum {
RTC_TS_SIGNAL_SEL_TAMPER0 = 0U, /**< Select tamper0 */
RTC_TS_SIGNAL_SEL_TAMPER1 = 1U, /**< Select tamper1 */
} rtc_ts_signal_sel_t;
/**
* @brief Time stamp trigger style
*/
typedef enum
{
RTC_TS_RISING_EDGE = 0, /**< Rising edge */
RTC_TS_FALLING_EDGE = 1, /**< Falling edge */
typedef enum {
RTC_TS_RISING_EDGE = 0U, /**< Rising edge */
RTC_TS_FALLING_EDGE = 1U, /**< Falling edge */
} rtc_ts_trigger_style_t;
/**
* @brief Index of tamper
*/
typedef enum
{
RTC_TAMPER_0 = 0, /**< Tamper0 */
RTC_TAMPER_1 = 1, /**< Tamper1 */
typedef enum {
RTC_TAMPER_0 = 0U, /**< Tamper0 */
RTC_TAMPER_1 = 1U, /**< Tamper1 */
} rtc_tamper_idx_t;
/**
* @brief Tamper trigger type
*/
typedef enum
{
RTC_TAMPER_TRIGGER_LOW = 0, /**< High trigger */
RTC_TAMPER_TRIGGER_HIGH = 1, /**< Low trigger */
typedef enum {
RTC_TAMPER_TRIGGER_LOW = 0U, /**< High trigger */
RTC_TAMPER_TRIGGER_HIGH = 1U, /**< Low trigger */
} rtc_tamper_trigger_t;
/**
* @brief Tamper sampling frequency
*/
typedef enum
{
RTC_TAMPER_SAMPLING_FREQ_32768 = 0, /**< RTCCLK / 32768 */
RTC_TAMPER_SAMPLING_FREQ_16384 = 1, /**< RTCCLK / 16384 */
RTC_TAMPER_SAMPLING_FREQ_8192 = 2, /**< RTCCLK / 8192 */
RTC_TAMPER_SAMPLING_FREQ_4096 = 3, /**< RTCCLK / 4096 */
RTC_TAMPER_SAMPLING_FREQ_2048 = 4, /**< RTCCLK / 2048 */
RTC_TAMPER_SAMPLING_FREQ_1024 = 5, /**< RTCCLK / 1024 */
RTC_TAMPER_SAMPLING_FREQ_512 = 6, /**< RTCCLK / 512 */
RTC_TAMPER_SAMPLING_FREQ_256 = 7, /**< RTCCLK / 256 */
typedef enum {
RTC_TAMPER_SAMPLING_FREQ_32768 = 0U, /**< RTCCLK / 32768 */
RTC_TAMPER_SAMPLING_FREQ_16384 = 1U, /**< RTCCLK / 16384 */
RTC_TAMPER_SAMPLING_FREQ_8192 = 2U, /**< RTCCLK / 8192 */
RTC_TAMPER_SAMPLING_FREQ_4096 = 3U, /**< RTCCLK / 4096 */
RTC_TAMPER_SAMPLING_FREQ_2048 = 4U, /**< RTCCLK / 2048 */
RTC_TAMPER_SAMPLING_FREQ_1024 = 5U, /**< RTCCLK / 1024 */
RTC_TAMPER_SAMPLING_FREQ_512 = 6U, /**< RTCCLK / 512 */
RTC_TAMPER_SAMPLING_FREQ_256 = 7U, /**< RTCCLK / 256 */
} rtc_tamper_sampling_freq_t;
/**
* @brief Tamper filter time
*/
typedef enum
{
RTC_TAMPER_DURATION_1 = 0, /**< Duration 1 sampling */
RTC_TAMPER_DURATION_2 = 1, /**< Duration 2 sampling */
RTC_TAMPER_DURATION_4 = 2, /**< Duration 4 sampling */
RTC_TAMPER_DURATION_8 = 3, /**< Duration 8 sampling */
typedef enum {
RTC_TAMPER_DURATION_1 = 0U, /**< Duration 1 sampling */
RTC_TAMPER_DURATION_2 = 1U, /**< Duration 2 sampling */
RTC_TAMPER_DURATION_4 = 2U, /**< Duration 4 sampling */
RTC_TAMPER_DURATION_8 = 3U, /**< Duration 8 sampling */
} rtc_tamper_duration_t;
/**
* @brief Tamper structure
*/
typedef struct
{
typedef struct {
rtc_tamper_idx_t idx; /**< Index of tamper */
rtc_tamper_trigger_t trig; /**< Trigger type */
rtc_tamper_sampling_freq_t freq; /**< Sampling frequency */
@ -266,84 +245,77 @@ typedef struct
/**
* @brief Wake-up clock
*/
typedef enum
{
RTC_WAKEUP_CLOCK_DIV_16 = 0, /**< RTCCLK / 16 */
RTC_WAKEUP_CLOCK_DIV_8 = 1, /**< RTCCLK / 8 */
RTC_WAKEUP_CLOCK_DIV_4 = 2, /**< RTCCLK / 4 */
RTC_WAKEUP_CLOCK_DIV_2 = 3, /**< RTCCLK / 2 */
RTC_WAKEUP_CLOCK_1HZ = 4, /**< 1Hz */
RTC_WAKEUP_CLOCK_1HZ_PULS = 6, /**< 1Hz and WUT + 65536 */
typedef enum {
RTC_WAKEUP_CLOCK_DIV_16 = 0U, /**< RTCCLK / 16 */
RTC_WAKEUP_CLOCK_DIV_8 = 1U, /**< RTCCLK / 8 */
RTC_WAKEUP_CLOCK_DIV_4 = 2U, /**< RTCCLK / 4 */
RTC_WAKEUP_CLOCK_DIV_2 = 3U, /**< RTCCLK / 2 */
RTC_WAKEUP_CLOCK_1HZ = 4U, /**< 1Hz */
RTC_WAKEUP_CLOCK_1HZ_PULS = 6U, /**< 1Hz and WUT + 65536 */
} rtc_wakeup_clock_t;
/**
* @brief RTC clock output type
*/
typedef enum
{
RTC_CLOCK_OUTPUT_32768 = 0, /**< 32768Hz */
RTC_CLOCK_OUTPUT_1024 = 1, /**< 1024Hz */
RTC_CLOCK_OUTPUT_32 = 2, /**< 32Hz */
RTC_CLOCK_OUTPUT_1 = 3, /**< 1Hz */
RTC_CLOCK_OUTPUT_CAL_1 = 4, /**< 1Hz after calibration */
RTC_CLOCK_OUTPUT_EXA_1 = 5, /**< Exact 1Hz */
typedef enum {
RTC_CLOCK_OUTPUT_32768 = 0U, /**< 32768Hz */
RTC_CLOCK_OUTPUT_1024 = 1U, /**< 1024Hz */
RTC_CLOCK_OUTPUT_32 = 2U, /**< 32Hz */
RTC_CLOCK_OUTPUT_1 = 3U, /**< 1Hz */
RTC_CLOCK_OUTPUT_CAL_1 = 4U, /**< 1Hz after calibration */
RTC_CLOCK_OUTPUT_EXA_1 = 5U, /**< Exact 1Hz */
} rtc_clock_output_t;
/**
* @ Calibration frequency
*/
typedef enum
{
RTC_CALI_FREQ_10_SEC = 0, /**< Calibrate every 10 seconds */
RTC_CALI_FREQ_20_SEC = 1, /**< Calibrate every 20 seconds */
RTC_CALI_FREQ_1_MIN = 2, /**< Calibrate every 1 minute */
RTC_CALI_FREQ_2_MIN = 3, /**< Calibrate every 2 minutes */
RTC_CALI_FREQ_5_MIN = 4, /**< Calibrate every 5 minutes */
RTC_CALI_FREQ_10_MIN = 5, /**< Calibrate every 10 minutes */
RTC_CALI_FREQ_20_MIN = 6, /**< Calibrate every 20 minutes */
RTC_CALI_FREQ_1_SEC = 7, /**< Calibrate every 1 second */
typedef enum {
RTC_CALI_FREQ_10_SEC = 0U, /**< Calibrate every 10 seconds */
RTC_CALI_FREQ_20_SEC = 1U, /**< Calibrate every 20 seconds */
RTC_CALI_FREQ_1_MIN = 2U, /**< Calibrate every 1 minute */
RTC_CALI_FREQ_2_MIN = 3U, /**< Calibrate every 2 minutes */
RTC_CALI_FREQ_5_MIN = 4U, /**< Calibrate every 5 minutes */
RTC_CALI_FREQ_10_MIN = 5U, /**< Calibrate every 10 minutes */
RTC_CALI_FREQ_20_MIN = 6U, /**< Calibrate every 20 minutes */
RTC_CALI_FREQ_1_SEC = 7U, /**< Calibrate every 1 second */
} rtc_cali_freq_t;
/**
* @brief Temperature compensate type
*/
typedef enum
{
RTC_CALI_TC_NONE = 0, /**< Temperature compensate disable */
RTC_CALI_TC_AUTO_BY_HW = 1, /**< Temperature compensate by hardware */
RTC_CALI_TC_AUTO_BY_SF = 2, /**< Temperature compensate by software */
RTC_CALI_TC_AUTO_BY_HW_SF = 3, /**< Temperature compensate by hardware, trigger by software */
typedef enum {
RTC_CALI_TC_NONE = 0U, /**< Temperature compensate disable */
RTC_CALI_TC_AUTO_BY_HW = 1U, /**< Temperature compensate by hardware */
RTC_CALI_TC_AUTO_BY_SF = 2U, /**< Temperature compensate by software */
RTC_CALI_TC_AUTO_BY_HW_SF = 3U, /**< Temperature compensate by hardware, trigger by software */
} rtc_cali_tc_t;
/**
* @ Calculate frequency
*/
typedef enum
{
RTC_CALI_CALC_FREQ_10_SEC = 0, /**< Calculate every 10 seconds */
RTC_CALI_CALC_FREQ_20_SEC = 1, /**< Calculate every 20 seconds */
RTC_CALI_CALC_FREQ_1_MIN = 2, /**< Calculate every 1 minute */
RTC_CALI_CALC_FREQ_2_MIN = 3, /**< Calculate every 2 minutes */
RTC_CALI_CALC_FREQ_5_MIN = 4, /**< Calculate every 5 minutes */
RTC_CALI_CALC_FREQ_10_MIN = 5, /**< Calculate every 10 minutes */
RTC_CALI_CALC_FREQ_20_MIN = 6, /**< Calculate every 20 minutes */
RTC_CALI_CALC_FREQ_1_HOUR = 7, /**< Calculate every 1 hour */
typedef enum {
RTC_CALI_CALC_FREQ_10_SEC = 0U, /**< Calculate every 10 seconds */
RTC_CALI_CALC_FREQ_20_SEC = 1U, /**< Calculate every 20 seconds */
RTC_CALI_CALC_FREQ_1_MIN = 2U, /**< Calculate every 1 minute */
RTC_CALI_CALC_FREQ_2_MIN = 3U, /**< Calculate every 2 minutes */
RTC_CALI_CALC_FREQ_5_MIN = 4U, /**< Calculate every 5 minutes */
RTC_CALI_CALC_FREQ_10_MIN = 5U, /**< Calculate every 10 minutes */
RTC_CALI_CALC_FREQ_20_MIN = 6U, /**< Calculate every 20 minutes */
RTC_CALI_CALC_FREQ_1_HOUR = 7U, /**< Calculate every 1 hour */
} rtc_cali_calc_freq_t;
/**
* @brief Calibration algorithm
*/
typedef enum
{
RTC_CALI_CALC_4 = 0, /**< 4-polynomial */
RTC_CALI_CALC_2 = 1, /**< 2-parabola */
typedef enum {
RTC_CALI_CALC_4 = 0U, /**< 4-polynomial */
RTC_CALI_CALC_2 = 1U, /**< 2-parabola */
} rtc_cali_calc_t;
/**
* @brief Calibration structure
*/
typedef struct
{
typedef struct {
rtc_cali_freq_t cali_freq; /**< calibrate frequency */
rtc_cali_tc_t tc; /**< Temperature compensate type */
rtc_cali_calc_freq_t calc_freq; /**< Calculate frequency */
@ -354,8 +326,7 @@ typedef struct
/**
* @brief Interrupt type
*/
typedef enum
{
typedef enum {
RTC_IT_SEC = (1U << 0), /**< Second */
RTC_IT_MIN = (1U << 1), /**< Minute */
RTC_IT_HR = (1U << 2), /**< Hour */
@ -378,8 +349,7 @@ typedef enum
/**
* @brief Interrupt flag
*/
typedef enum
{
typedef enum {
RTC_IF_SEC = (1U << 0), /**< Second */
RTC_IF_MIN = (1U << 1), /**< Minute */
RTC_IF_HR = (1U << 2), /**< Hour */
@ -405,44 +375,44 @@ typedef enum
/** @defgroup RTC_Public_Macro RTC Public Macros
* @{
*/
#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55))
#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0))
#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55U))
#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0U))
#define RTC_BY_PASS_ENABLE() \
do { \
do { \
RTC_UNLOCK(); \
SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \
RTC_LOCK(); \
} while (0)
} while (0)
#define RTC_BY_PASS_DISABLE() \
do { \
do { \
RTC_UNLOCK(); \
CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \
RTC_LOCK(); \
} while (0)
} while (0)
#define RTC_SUMMER_TIME_ENABLE() \
do { \
do { \
RTC_UNLOCK(); \
SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \
RTC_LOCK(); \
} while (0)
} while (0)
#define RTC_SUMMER_TIME_DISABLE() \
do { \
do { \
RTC_UNLOCK(); \
CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \
RTC_LOCK(); \
} while (0)
} while (0)
#define RTC_WINTER_TIME_ENABLE() \
do { \
do { \
RTC_UNLOCK(); \
SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \
RTC_LOCK(); \
} while (0)
} while (0)
#define RTC_WINTER_TIME_DISABLE() \
do { \
do { \
RTC_UNLOCK(); \
CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \
RTC_LOCK(); \
} while (0)
} while (0)
/**
* @}
*/
@ -450,10 +420,10 @@ typedef enum
/** @defgroup CAN_Private_Macros CAN Private Macros
* @{
*/
#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AA))
#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0))
#define ALARM_MASK_ALL 0x40808080
#define RTC_TIMEOUT_VALUE 100
#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AAU))
#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0U))
#define ALARM_MASK_ALL 0x40808080U
#define RTC_TIMEOUT_VALUE 100U
#define IS_SHIFT_SUB_SS(x) ((x) < (1U << 15))
#define IS_RTC_HOUR_FORMAT(x) (((x) == RTC_HOUR_FORMAT_24) || \

107
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_smartcard.h
View File

@ -18,7 +18,7 @@
#define __ALD_SMARTCARD_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@ -41,52 +41,50 @@ extern "C" {
/**
* @brief SMARTCARD error codes
*/
typedef enum
{
SMARTCARD_ERROR_NONE = ((uint32_t)0x00), /**< No error */
SMARTCARD_ERROR_PE = ((uint32_t)0x01), /**< Parity error */
SMARTCARD_ERROR_NE = ((uint32_t)0x02), /**< Noise error */
SMARTCARD_ERROR_FE = ((uint32_t)0x04), /**< frame error */
SMARTCARD_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */
SMARTCARD_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */
typedef enum {
SMARTCARD_ERROR_NONE = ((uint32_t)0x00U), /**< No error */
SMARTCARD_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */
SMARTCARD_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */
SMARTCARD_ERROR_FE = ((uint32_t)0x04U), /**< frame error */
SMARTCARD_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */
SMARTCARD_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */
} smartcard_error_t;
/**
* @brief SMARTCARD Prescaler
*/
typedef enum
{
SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1), /**< SYSCLK divided by 2 */
SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2), /**< SYSCLK divided by 4 */
SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3), /**< SYSCLK divided by 6 */
SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4), /**< SYSCLK divided by 8 */
SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5), /**< SYSCLK divided by 10 */
SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6), /**< SYSCLK divided by 12 */
SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7), /**< SYSCLK divided by 14 */
SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8), /**< SYSCLK divided by 16 */
SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9), /**< SYSCLK divided by 18 */
SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xA), /**< SYSCLK divided by 20 */
SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xB), /**< SYSCLK divided by 22 */
SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xC), /**< SYSCLK divided by 24 */
SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xD), /**< SYSCLK divided by 26 */
SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xE), /**< SYSCLK divided by 28 */
SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xF), /**< SYSCLK divided by 30 */
SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10), /**< SYSCLK divided by 32 */
SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11), /**< SYSCLK divided by 34 */
SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12), /**< SYSCLK divided by 36 */
SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13), /**< SYSCLK divided by 38 */
SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14), /**< SYSCLK divided by 40 */
SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15), /**< SYSCLK divided by 42 */
SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16), /**< SYSCLK divided by 44 */
SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17), /**< SYSCLK divided by 46 */
SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18), /**< SYSCLK divided by 48 */
SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19), /**< SYSCLK divided by 50 */
SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1A), /**< SYSCLK divided by 52 */
SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1B), /**< SYSCLK divided by 54 */
SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1C), /**< SYSCLK divided by 56 */
SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1D), /**< SYSCLK divided by 58 */
SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1E), /**< SYSCLK divided by 60 */
SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1F), /**< SYSCLK divided by 62 */
typedef enum {
SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1U), /**< SYSCLK divided by 2 */
SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2U), /**< SYSCLK divided by 4 */
SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3U), /**< SYSCLK divided by 6 */
SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4U), /**< SYSCLK divided by 8 */
SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5U), /**< SYSCLK divided by 10 */
SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6U), /**< SYSCLK divided by 12 */
SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7U), /**< SYSCLK divided by 14 */
SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8U), /**< SYSCLK divided by 16 */
SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9U), /**< SYSCLK divided by 18 */
SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xAU), /**< SYSCLK divided by 20 */
SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xBU), /**< SYSCLK divided by 22 */
SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xCU), /**< SYSCLK divided by 24 */
SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xDU), /**< SYSCLK divided by 26 */
SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xEU), /**< SYSCLK divided by 28 */
SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xFU), /**< SYSCLK divided by 30 */
SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10U), /**< SYSCLK divided by 32 */
SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11U), /**< SYSCLK divided by 34 */
SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12U), /**< SYSCLK divided by 36 */
SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13U), /**< SYSCLK divided by 38 */
SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14U), /**< SYSCLK divided by 40 */
SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15U), /**< SYSCLK divided by 42 */
SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16U), /**< SYSCLK divided by 44 */
SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17U), /**< SYSCLK divided by 46 */
SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18U), /**< SYSCLK divided by 48 */
SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19U), /**< SYSCLK divided by 50 */
SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1AU), /**< SYSCLK divided by 52 */
SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1BU), /**< SYSCLK divided by 54 */
SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1CU), /**< SYSCLK divided by 56 */
SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1DU), /**< SYSCLK divided by 58 */
SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1EU), /**< SYSCLK divided by 60 */
SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1FU), /**< SYSCLK divided by 62 */
} smartcard_prescaler_t;
/**
@ -100,8 +98,7 @@ typedef enum
/**
* @brief SMARTCARD Init Structure definition
*/
typedef struct
{
typedef struct {
uint32_t baud; /**< This member configures the SmartCard communication baud rate. */
usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */
usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */
@ -126,24 +123,22 @@ typedef struct
/**
* @brief ALD state structures definition
*/
typedef enum
{
SMARTCARD_STATE_RESET = 0x00, /**< Peripheral is not yet Initialized */
SMARTCARD_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
SMARTCARD_STATE_BUSY = 0x02, /**< an internal process is ongoing */
SMARTCARD_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */
SMARTCARD_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */
SMARTCARD_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission and Reception process is ongoing */
SMARTCARD_STATE_TIMEOUT = 0x03, /**< Timeout state */
SMARTCARD_STATE_ERROR = 0x04 /**< Error */
typedef enum {
SMARTCARD_STATE_RESET = 0x00U, /**< Peripheral is not yet Initialized */
SMARTCARD_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
SMARTCARD_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
SMARTCARD_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */
SMARTCARD_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */
SMARTCARD_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission and Reception process is ongoing */
SMARTCARD_STATE_TIMEOUT = 0x03U, /**< Timeout state */
SMARTCARD_STATE_ERROR = 0x04U, /**< Error */
} smartcard_state_t;
/**
* @brief SMARTCARD handle structure definition
*/
typedef struct smartcard_handle_s
{
typedef struct smartcard_handle_s {
USART_TypeDef *perh; /**< USART registers base address */
smartcard_init_t init; /**< SmartCard communication parameters */
uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */

147
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_spi.h
View File

@ -18,7 +18,7 @@
#define __ALD_SPI_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@ -39,68 +39,61 @@ extern "C" {
/**
* @brief clock phase
*/
typedef enum
{
SPI_CPHA_FIRST = 0, /**< Transiting data in the first edge */
SPI_CPHA_SECOND = 1, /**< Transiting data in the seconde edge */
typedef enum {
SPI_CPHA_FIRST = 0U, /**< Transiting data in the first edge */
SPI_CPHA_SECOND = 1U, /**< Transiting data in the seconde edge */
} spi_cpha_t;
/**
* @brief clock polarity
*/
typedef enum
{
SPI_CPOL_LOW = 0, /**< Polarity hold low when spi-bus is idle */
SPI_CPOL_HIGH = 1, /**< Polarity hold high when spi-bus is idle */
typedef enum {
SPI_CPOL_LOW = 0U, /**< Polarity hold low when spi-bus is idle */
SPI_CPOL_HIGH = 1U, /**< Polarity hold high when spi-bus is idle */
} spi_cpol_t;
/**
* @brief master selection
*/
typedef enum
{
SPI_MODE_SLAVER = 0, /**< Slave mode */
SPI_MODE_MASTER = 1, /**< Master mode */
typedef enum {
SPI_MODE_SLAVER = 0U, /**< Slave mode */
SPI_MODE_MASTER = 1U, /**< Master mode */
} spi_mode_t;
/**
* @brief baud rate control
*/
typedef enum
{
SPI_BAUD_2 = 0, /**< fpclk/2 */
SPI_BAUD_4 = 1, /**< fpclk/4 */
SPI_BAUD_8 = 2, /**< fpclk/8 */
SPI_BAUD_16 = 3, /**< fpclk/16 */
SPI_BAUD_32 = 4, /**< fpclk/32 */
SPI_BAUD_64 = 5, /**< fpclk/64 */
SPI_BAUD_128 = 6, /**< fpclk/128 */
SPI_BAUD_256 = 7, /**< fpclk/256 */
typedef enum {
SPI_BAUD_2 = 0U, /**< fpclk/2 */
SPI_BAUD_4 = 1U, /**< fpclk/4 */
SPI_BAUD_8 = 2U, /**< fpclk/8 */
SPI_BAUD_16 = 3U, /**< fpclk/16 */
SPI_BAUD_32 = 4U, /**< fpclk/32 */
SPI_BAUD_64 = 5U, /**< fpclk/64 */
SPI_BAUD_128 = 6U, /**< fpclk/128 */
SPI_BAUD_256 = 7U, /**< fpclk/256 */
} spi_baud_t;
/**
* @brief frame format
*/
typedef enum
{
SPI_FIRSTBIT_MSB = 0, /**< MSB transmitted first */
SPI_FIRSTBIT_LSB = 1, /**< LSB transmitted first */
typedef enum {
SPI_FIRSTBIT_MSB = 0U, /**< MSB transmitted first */
SPI_FIRSTBIT_LSB = 1U, /**< LSB transmitted first */
} spi_firstbit_t;
/**
* @brief data frame format
*/
typedef enum
{
SPI_DATA_SIZE_8 = 0, /**< 8-bit data frame format is selected for transmission/reception */
SPI_DATA_SIZE_16 = 1, /**< 16-bit data frame format is selected for transmission/reception */
typedef enum {
SPI_DATA_SIZE_8 = 0U, /**< 8-bit data frame format is selected for transmission/reception */
SPI_DATA_SIZE_16 = 1U, /**< 16-bit data frame format is selected for transmission/reception */
} spi_datasize_t;
/**
* @brief interrupt control
*/
typedef enum
{
typedef enum {
SPI_IT_ERR = (1U << 5), /**< error interrupt */
SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */
SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */
@ -109,8 +102,7 @@ typedef enum
/**
* @brief interrupt flag
*/
typedef enum
{
typedef enum {
SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */
SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */
SPI_IF_CRCERR = (1U << 4), /**< crc error flag */
@ -122,14 +114,13 @@ typedef enum
/**
* @brief SPI error status
*/
typedef enum
{
SPI_ERROR_NONE = 0, /**< none */
SPI_ERROR_MODF = 1, /**< mode fault */
SPI_ERROR_CRC = 2, /**< crc error */
SPI_ERROR_OVE = 4, /**< overrun error */
SPI_ERROR_DMA = 8, /**< dma error */
SPI_ERROR_FLAG = 0x10, /**< interrupt flag error */
typedef enum {
SPI_ERROR_NONE = 0U, /**< none */
SPI_ERROR_MODF = 1U, /**< mode fault */
SPI_ERROR_CRC = 2U, /**< crc error */
SPI_ERROR_OVE = 4U, /**< overrun error */
SPI_ERROR_DMA = 8U, /**< dma error */
SPI_ERROR_FLAG = 0x10U, /**< interrupt flag error */
} spi_error_t;
@ -137,23 +128,21 @@ typedef enum
/**
* @brief SPI state structures definition
*/
typedef enum
{
SPI_STATE_RESET = 0x00, /**< Peripheral is not initialized */
SPI_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
SPI_STATE_BUSY = 0x02, /**< an internal process is ongoing */
SPI_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */
SPI_STATE_BUSY_RX = 0x21, /**< receive is ongoing */
SPI_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */
SPI_STATE_TIMEOUT = 0x03, /**< Timeout state */
SPI_STATE_ERROR = 0x04, /**< Error */
typedef enum {
SPI_STATE_RESET = 0x00U, /**< Peripheral is not initialized */
SPI_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
SPI_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
SPI_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */
SPI_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */
SPI_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */
SPI_STATE_TIMEOUT = 0x03U, /**< Timeout state */
SPI_STATE_ERROR = 0x04U, /**< Error */
} spi_state_t;
/**
* @brief SPI status definition
*/
typedef enum
{
typedef enum {
SPI_STATUS_RXBNE = (1U << 0), /**< Receive not empty status */
SPI_STATUS_TXBE = (1U << 1), /**< Transmit empty status */
SPI_STATUS_CRCERR = (1U << 4), /**< CRC error status */
@ -166,38 +155,34 @@ typedef enum
/**
* @brief SPI direction definition
*/
typedef enum
{
SPI_DIRECTION_2LINES = 0, /**< 2 lines */
SPI_DIRECTION_2LINES_RXONLY = 1, /**< 2 lines only rx */
SPI_DIRECTION_1LINE = 2, /**< 1 line */
SPI_DIRECTION_1LINE_RX = 3, /**< 1 line only rx */
typedef enum {
SPI_DIRECTION_2LINES = 0U, /**< 2 lines */
SPI_DIRECTION_2LINES_RXONLY = 1U, /**< 2 lines only rx */
SPI_DIRECTION_1LINE = 2U, /**< 1 line */
SPI_DIRECTION_1LINE_RX = 3U, /**< 1 line only rx */
} spi_direction_t;
/**
* @brief SPI dma request definition
*/
typedef enum
{
SPI_DMA_REQ_TX = 0, /**< TX dma request */
SPI_DMA_REQ_RX = 1, /**< RX dma request */
typedef enum {
SPI_DMA_REQ_TX = 0U, /**< TX dma request */
SPI_DMA_REQ_RX = 1U, /**< RX dma request */
} spi_dma_req_t;
/**
* @brief SPI TXE/RXNE status definition
*/
typedef enum
{
SPI_SR_TXBE = 0, /**< SR.TXE set */
SPI_SR_RXBNE = 1, /**< SR.RXNE set */
SPI_SR_TXBE_RXBNE = 2, /**< SR.TXE and SR.RXNE set */
typedef enum {
SPI_SR_TXBE = 0U, /**< SR.TXE set */
SPI_SR_RXBNE = 1U, /**< SR.RXNE set */
SPI_SR_TXBE_RXBNE = 2U, /**< SR.TXE and SR.RXNE set */
} spi_sr_status_t;
/**
* @brief SPI init structure definition
*/
typedef struct
{
typedef struct {
spi_mode_t mode; /**< SPI mode */
spi_direction_t dir; /**< SPI direction */
spi_datasize_t data_size; /**< SPI data size */
@ -213,8 +198,7 @@ typedef struct
/**
* @brief SPI handle structure definition
*/
typedef struct spi_handle_s
{
typedef struct spi_handle_s {
SPI_TypeDef *perh; /**< SPI registers base address */
spi_init_t init; /**< SPI communication parameters */
uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */
@ -247,10 +231,10 @@ typedef struct spi_handle_s
#define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS))
#define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS))
#define SPI_CRC_RESET(x) \
do { \
do { \
CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
} while (0)
} while (0)
#define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
#define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
#define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
@ -268,9 +252,12 @@ typedef struct spi_handle_s
/** @defgroup SPI_Private_Macros SPI Private Macros
* @{
*/
#define IS_SPI(x) (((x) == SPI0) || \
((x) == SPI1) || \
((x) == SPI2))
#if defined(ES32F065x) || defined(ES32F033x)
#define IS_SPI(x) (((x) == SPI0) || ((x) == SPI1))
#endif
#if defined(ES32F093x)
#define IS_SPI(x) (((x) == SPI0) || ((x) == SPI1) || ((x) == SPI2))
#endif
#define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \
((x) == SPI_CPHA_SECOND))
#define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \
@ -287,6 +274,8 @@ typedef struct spi_handle_s
((x) == SPI_BAUD_256))
#define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \
((x) == SPI_DATA_SIZE_16))
#define IS_SPI_FIRSTBIT(x) (((x) == SPI_FIRSTBIT_MSB) || \
((x) == SPI_FIRSTBIT_LSB))
#define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \
((x) == SPI_BID_TX))
#define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \

26
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_syscfg.h
View File

@ -18,7 +18,7 @@
#define __ALD_SYSCFG_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@ -36,33 +36,33 @@ extern "C" {
/** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros
* @{
*/
#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0)
#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996)
#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0U)
#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996U)
#define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK)
#define BOOT_FROM_BOOT_ROM() \
do { \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define BOOT_FROM_BOOT_FLASH() \
do { \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
#define BOOT_FROM_FLASH() \
do { \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
} while (0)
/**
* @}
*/
@ -75,13 +75,11 @@ __STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status)
{
SYSCFG_UNLOCK();
if (status)
{
MODIFY_REG(SYSCFG->VTOR, SYSCFG_VTOR_VTO_MSK, (offset & ~0x3F));
if (status) {
MODIFY_REG(SYSCFG->VTOR, SYSCFG_VTOR_VTO_MSK, (offset & ~0x3FU));
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK);
}
else
{
else {
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK);
}

393
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_timer.h
View File

@ -19,7 +19,7 @@
#define __ALD_TIMER_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@ -40,111 +40,100 @@ extern "C" {
/**
* @brief TIMER counter mode
*/
typedef enum
{
TIMER_CNT_MODE_UP = 0, /**< Counter mode up */
TIMER_CNT_MODE_DOWN = 1, /**< Counter mode down */
TIMER_CNT_MODE_CENTER1 = 2, /**< Counter mode center1 */
TIMER_CNT_MODE_CENTER2 = 3, /**< Counter mode center2 */
TIMER_CNT_MODE_CENTER3 = 4, /**< Counter mode center3 */
typedef enum {
TIMER_CNT_MODE_UP = 0U, /**< Counter mode up */
TIMER_CNT_MODE_DOWN = 1U, /**< Counter mode down */
TIMER_CNT_MODE_CENTER1 = 2U, /**< Counter mode center1 */
TIMER_CNT_MODE_CENTER2 = 3U, /**< Counter mode center2 */
TIMER_CNT_MODE_CENTER3 = 4U, /**< Counter mode center3 */
} timer_cnt_mode_t;
/**
* @brief TIMER clock division
*/
typedef enum
{
TIMER_CLOCK_DIV1 = 0, /**< No prescaler is used */
TIMER_CLOCK_DIV2 = 1, /** Clock is divided by 2 */
TIMER_CLOCK_DIV4 = 2, /** Clock is divided by 4 */
typedef enum {
TIMER_CLOCK_DIV1 = 0U, /**< No prescaler is used */
TIMER_CLOCK_DIV2 = 1U, /** Clock is divided by 2 */
TIMER_CLOCK_DIV4 = 2U, /** Clock is divided by 4 */
} timer_clock_division_t;
/**
* @brief TIMER output compare and PWM modes
*/
typedef enum
{
TIMER_OC_MODE_TIMERING = 0, /**< Output compare mode is timering */
TIMER_OC_MODE_ACTIVE = 1, /**< Output compare mode is active */
TIMER_OC_MODE_INACTIVE = 2, /**< Output compare mode is inactive */
TIMER_OC_MODE_TOGGLE = 3, /**< Output compare mode is toggle */
TIMER_OC_MODE_FORCE_INACTIVE = 4, /**< Output compare mode is force inactive */
TIMER_OC_MODE_FORCE_ACTIVE = 5, /**< Output compare mode is force active */
TIMER_OC_MODE_PWM1 = 6, /**< Output compare mode is pwm1 */
TIMER_OC_MODE_PWM2 = 7, /**< Output compare mode is pwm2 */
typedef enum {
TIMER_OC_MODE_TIMERING = 0U, /**< Output compare mode is timering */
TIMER_OC_MODE_ACTIVE = 1U, /**< Output compare mode is active */
TIMER_OC_MODE_INACTIVE = 2U, /**< Output compare mode is inactive */
TIMER_OC_MODE_TOGGLE = 3U, /**< Output compare mode is toggle */
TIMER_OC_MODE_FORCE_INACTIVE = 4U, /**< Output compare mode is force inactive */
TIMER_OC_MODE_FORCE_ACTIVE = 5U, /**< Output compare mode is force active */
TIMER_OC_MODE_PWM1 = 6U, /**< Output compare mode is pwm1 */
TIMER_OC_MODE_PWM2 = 7U, /**< Output compare mode is pwm2 */
} timer_oc_mode_t;
/**
* @brief TIMER output compare polarity
*/
typedef enum
{
TIMER_OC_POLARITY_HIGH = 0, /**< Output compare polarity is high */
TIMER_OC_POLARITY_LOW = 1, /**< Output compare polarity is low */
typedef enum {
TIMER_OC_POLARITY_HIGH = 0U, /**< Output compare polarity is high */
TIMER_OC_POLARITY_LOW = 1U, /**< Output compare polarity is low */
} timer_oc_polarity_t;
/**
* @brief TIMER complementary output compare polarity
*/
typedef enum
{
TIMER_OCN_POLARITY_HIGH = 0, /**< Complementary output compare polarity is high */
TIMER_OCN_POLARITY_LOW = 1, /**< Complementary output compare polarity is low */
typedef enum {
TIMER_OCN_POLARITY_HIGH = 0U, /**< Complementary output compare polarity is high */
TIMER_OCN_POLARITY_LOW = 1U, /**< Complementary output compare polarity is low */
} timer_ocn_polarity_t;
/**
* @brief TIMER output compare idle state
*/
typedef enum
{
TIMER_OC_IDLE_RESET = 0, /**< Output compare idle state is reset */
TIMER_OC_IDLE_SET = 1, /**< Output compare idle state is set */
typedef enum {
TIMER_OC_IDLE_RESET = 0U, /**< Output compare idle state is reset */
TIMER_OC_IDLE_SET = 1U, /**< Output compare idle state is set */
} timer_oc_idle_t;
/**
* @brief TIMER complementary output compare idle state
*/
typedef enum
{
TIMER_OCN_IDLE_RESET = 0, /**< Complementary output compare idle state is reset */
TIMER_OCN_IDLE_SET = 1, /**< Complementary output compare idle state is set */
typedef enum {
TIMER_OCN_IDLE_RESET = 0U, /**< Complementary output compare idle state is reset */
TIMER_OCN_IDLE_SET = 1U, /**< Complementary output compare idle state is set */
} timer_ocn_idle_t;
/**
* @brief TIMER channel
*/
typedef enum
{
TIMER_CHANNEL_1 = 0, /**< Channel 1 */
TIMER_CHANNEL_2 = 1, /**< Channel 2 */
TIMER_CHANNEL_3 = 2, /**< Channel 3 */
TIMER_CHANNEL_4 = 4, /**< Channel 4 */
TIMER_CHANNEL_ALL = 0xF, /**< All channel */
typedef enum {
TIMER_CHANNEL_1 = 0U, /**< Channel 1 */
TIMER_CHANNEL_2 = 1U, /**< Channel 2 */
TIMER_CHANNEL_3 = 2U, /**< Channel 3 */
TIMER_CHANNEL_4 = 4U, /**< Channel 4 */
TIMER_CHANNEL_ALL = 0xFU, /**< All channel */
} timer_channel_t;
/**
* @brief TIMER one pulse mode
*/
typedef enum
{
TIMER_OP_MODE_REPEAT = 0, /**< Repetitive */
TIMER_OP_MODE_SINGLE = 1, /**< single */
typedef enum {
TIMER_OP_MODE_REPEAT = 0U, /**< Repetitive */
TIMER_OP_MODE_SINGLE = 1U, /**< single */
} timer_op_mode_t;
/**
* @brief TIMER one pulse output channel
*/
typedef enum
{
TIMER_OP_OUTPUT_CHANNEL_1 = 0, /**< One pulse output channal 1 */
TIMER_OP_OUTPUT_CHANNEL_2 = 1, /**< One pulse output channal 2 */
typedef enum {
TIMER_OP_OUTPUT_CHANNEL_1 = 0U, /**< One pulse output channal 1 */
TIMER_OP_OUTPUT_CHANNEL_2 = 1U, /**< One pulse output channal 2 */
} timer_op_output_channel_t;
/**
* @brief TIMER time base configuration structure definition
*/
typedef struct
{
typedef struct {
uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */
timer_cnt_mode_t mode; /**< Specifies the counter mode. */
uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */
@ -155,8 +144,7 @@ typedef struct
/**
* @brief TIMER output compare configuration structure definition
*/
typedef struct
{
typedef struct {
timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */
uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */
timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */
@ -169,38 +157,40 @@ typedef struct
/**
* @brief State structures definition
*/
typedef enum
{
TIMER_STATE_RESET = 0x00, /**< Peripheral not yet initialized or disabled */
TIMER_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
TIMER_STATE_BUSY = 0x02, /**< An internal process is ongoing */
TIMER_STATE_TIMEREOUT = 0x03, /**< Timeout state */
TIMER_STATE_ERROR = 0x04, /**< Reception process is ongoing */
typedef enum {
TIMER_STATE_RESET = 0x00U, /**< Peripheral not yet initialized or disabled */
TIMER_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
TIMER_STATE_BUSY = 0x02U, /**< An internal process is ongoing */
TIMER_STATE_TIMEREOUT = 0x03U, /**< Timeout state */
TIMER_STATE_ERROR = 0x04U, /**< Reception process is ongoing */
} timer_state_t;
/**
* @brief Active channel structures definition
*/
typedef enum
{
TIMER_ACTIVE_CHANNEL_1 = 0x01, /**< The active channel is 1 */
TIMER_ACTIVE_CHANNEL_2 = 0x02, /**< The active channel is 2 */
TIMER_ACTIVE_CHANNEL_3 = 0x04, /**< The active channel is 3 */
TIMER_ACTIVE_CHANNEL_4 = 0x08, /**< The active channel is 4 */
TIMER_ACTIVE_CHANNEL_CLEARED = 0x00, /**< All active channels cleared */
typedef enum {
TIMER_ACTIVE_CHANNEL_1 = 0x01U, /**< The active channel is 1 */
TIMER_ACTIVE_CHANNEL_2 = 0x02U, /**< The active channel is 2 */
TIMER_ACTIVE_CHANNEL_3 = 0x04U, /**< The active channel is 3 */
TIMER_ACTIVE_CHANNEL_4 = 0x08U, /**< The active channel is 4 */
TIMER_ACTIVE_CHANNEL_CLEARED = 0x00U, /**< All active channels cleared */
} timer_active_channel_t;
/**
* @brief TIMER time base handle structure definition
*/
typedef struct timer_handle_s
{
typedef struct timer_handle_s {
TIMER_TypeDef *perh; /**< Register base address */
timer_base_init_t init; /**< TIMER Time Base required parameters */
timer_active_channel_t ch; /**< Active channel */
lock_state_t lock; /**< Locking object */
timer_state_t state; /**< TIMER operation state */
#ifdef ALD_DMA
dma_handle_t hdma1; /**< Timer DMA handle parameters */
dma_handle_t hdma2;
#endif
void (*period_elapse_cbk)(struct timer_handle_s *arg); /**< Period elapse callback */
void (*delay_elapse_cbk)(struct timer_handle_s *arg); /**< Delay_elapse callback */
void (*capture_cbk)(struct timer_handle_s *arg); /**< Capture callback */
@ -215,48 +205,43 @@ typedef struct timer_handle_s
/**
* @brief TIMER encoder mode
*/
typedef enum
{
TIMER_ENC_MODE_TI1 = 1, /**< encoder mode 1 */
TIMER_ENC_MODE_TI2 = 2, /**< encoder mode 2 */
TIMER_ENC_MODE_TI12 = 3, /**< encoder mode 3 */
typedef enum {
TIMER_ENC_MODE_TI1 = 1U, /**< encoder mode 1 */
TIMER_ENC_MODE_TI2 = 2U, /**< encoder mode 2 */
TIMER_ENC_MODE_TI12 = 3U, /**< encoder mode 3 */
} timer_encoder_mode_t;
/**
* @brief TIMER input capture polarity
*/
typedef enum
{
TIMER_IC_POLARITY_RISE = 0, /**< Input capture polarity rising */
TIMER_IC_POLARITY_FALL = 1, /**< Input capture polarity falling */
typedef enum {
TIMER_IC_POLARITY_RISE = 0U, /**< Input capture polarity rising */
TIMER_IC_POLARITY_FALL = 1U, /**< Input capture polarity falling */
} timer_ic_polarity_t;
/**
*@brief TIMER input capture selection
*/
typedef enum
{
TIMER_IC_SEL_DIRECT = 1, /**< IC1 -- TI1 */
TIMER_IC_SEL_INDIRECT = 2, /**< IC1 -- TI2 */
TIMER_IC_SEL_TRC = 3, /**< IC1 -- TRC */
typedef enum {
TIMER_IC_SEL_DIRECT = 1U, /**< IC1 -- TI1 */
TIMER_IC_SEL_INDIRECT = 2U, /**< IC1 -- TI2 */
TIMER_IC_SEL_TRC = 3U, /**< IC1 -- TRC */
} timer_ic_select_t;
/**
* @brief TIMER input capture prescaler
*/
typedef enum
{
TIMER_IC_PSC_DIV1 = 0, /**< Capture performed once every 1 events */
TIMER_IC_PSC_DIV2 = 1, /**< Capture performed once every 2 events */
TIMER_IC_PSC_DIV4 = 2, /**< Capture performed once every 4 events */
TIMER_IC_PSC_DIV8 = 3, /**< Capture performed once every 4 events */
typedef enum {
TIMER_IC_PSC_DIV1 = 0U, /**< Capture performed once every 1 events */
TIMER_IC_PSC_DIV2 = 1U, /**< Capture performed once every 2 events */
TIMER_IC_PSC_DIV4 = 2U, /**< Capture performed once every 4 events */
TIMER_IC_PSC_DIV8 = 3U, /**< Capture performed once every 4 events */
} timer_ic_prescaler_t;
/**
* @brief TIMER encoder configuration structure definition
*/
typedef struct
{
typedef struct {
timer_encoder_mode_t mode; /**< Specifies the encoder mode */
timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */
timer_ic_select_t ic1_sel; /**< Specifies the input */
@ -271,8 +256,7 @@ typedef struct
/**
* @brief TIMER input capture configuration structure definition
*/
typedef struct
{
typedef struct {
timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */
timer_ic_select_t sel; /**< Specifies the input */
timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */
@ -282,8 +266,7 @@ typedef struct
/**
* @brief TIMER one pulse mode configuration structure definition
*/
typedef struct
{
typedef struct {
timer_oc_mode_t mode; /**< Specifies the TIMER mode */
uint16_t pulse; /**< Specifies the pulse value */
timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */
@ -297,35 +280,31 @@ typedef struct
/** @brief TIMER clear input source
*/
typedef enum
{
TIMER_INPUT_NONE = 0, /**< Clear input none */
TIMER_INPUT_ETR = 1, /**< Clear input etr */
typedef enum {
TIMER_INPUT_NONE = 0U, /**< Clear input none */
TIMER_INPUT_ETR = 1U, /**< Clear input etr */
} timer_clear_input_source_t;
/** @brief TIMER clear input polarity
*/
typedef enum
{
TIMER_POLARITY_NO_INV = 0, /**< Polarity for ETRx pin */
TIMER_POLARITY_INV = 1, /**< Polarity for ETRx pin */
typedef enum {
TIMER_POLARITY_NO_INV = 0U, /**< Polarity for ETRx pin */
TIMER_POLARITY_INV = 1U, /**< Polarity for ETRx pin */
} timer_clear_input_polarity_t;
/** @brief TIMER clear input polarity
*/
typedef enum
{
TIMER_ETR_PSC_DIV1 = 0, /**< No prescaler is used */
TIMER_ETR_PSC_DIV2 = 1, /**< ETR input source is divided by 2 */
TIMER_ETR_PSC_DIV4 = 2, /**< ETR input source is divided by 4 */
TIMER_ETR_PSC_DIV8 = 3, /**< ETR input source is divided by 8 */
typedef enum {
TIMER_ETR_PSC_DIV1 = 0U, /**< No prescaler is used */
TIMER_ETR_PSC_DIV2 = 1U, /**< ETR input source is divided by 2 */
TIMER_ETR_PSC_DIV4 = 2U, /**< ETR input source is divided by 4 */
TIMER_ETR_PSC_DIV8 = 3U, /**< ETR input source is divided by 8 */
} timer_etr_psc_t;
/**
* @brief TIMER clear input configuration handle structure definition
*/
typedef struct
{
typedef struct {
type_func_t state; /**< TIMER clear Input state */
timer_clear_input_source_t source; /**< TIMER clear Input sources */
timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */
@ -335,36 +314,33 @@ typedef struct
/** @brief TIMER clock source
*/
typedef enum
{
TIMER_SRC_ETRMODE2 = 0, /**< Clock source is etr mode2 */
TIMER_SRC_INTER = 1, /**< Clock source is etr internal */
TIMER_SRC_ITR0 = 2, /**< Clock source is etr itr0 */
TIMER_SRC_ITR1 = 3, /**< Clock source is etr itr1 */
TIMER_SRC_ITR2 = 4, /**< Clock source is etr itr2 */
TIMER_SRC_ITR3 = 5, /**< Clock source is etr itr3 */
TIMER_SRC_TI1ED = 6, /**< Clock source is etr ti1ed */
TIMER_SRC_TI1 = 7, /**< Clock source is etr ti1 */
TIMER_SRC_TI2 = 8, /**< Clock source is etr ti2 */
TIMER_SRC_ETRMODE1 = 9, /**< Clock source is etr mode1 */
typedef enum {
TIMER_SRC_ETRMODE2 = 0U, /**< Clock source is etr mode2 */
TIMER_SRC_INTER = 1U, /**< Clock source is etr internal */
TIMER_SRC_ITR0 = 2U, /**< Clock source is etr itr0 */
TIMER_SRC_ITR1 = 3U, /**< Clock source is etr itr1 */
TIMER_SRC_ITR2 = 4U, /**< Clock source is etr itr2 */
TIMER_SRC_ITR3 = 5U, /**< Clock source is etr itr3 */
TIMER_SRC_TI1ED = 6U, /**< Clock source is etr ti1ed */
TIMER_SRC_TI1 = 7U, /**< Clock source is etr ti1 */
TIMER_SRC_TI2 = 8U, /**< Clock source is etr ti2 */
TIMER_SRC_ETRMODE1 = 9U, /**< Clock source is etr mode1 */
} timer_clock_source_t;
/** @brief TIMER clock polarity
*/
typedef enum
{
TIMER_CLK_POLARITY_INV = 1, /**< Polarity for ETRx clock sources */
TIMER_CLK_POLARITY_NO_INV = 0, /**< Polarity for ETRx clock sources */
TIMER_CLK_POLARITY_RISE = 0, /**< Polarity for TIx clock sources */
TIMER_CLK_POLARITY_FALL = 1, /**< Polarity for TIx clock sources */
TIMER_CLK_POLARITY_BOTH = 3, /**< Polarity for TIx clock sources */
typedef enum {
TIMER_CLK_POLARITY_INV = 1U, /**< Polarity for ETRx clock sources */
TIMER_CLK_POLARITY_NO_INV = 0U, /**< Polarity for ETRx clock sources */
TIMER_CLK_POLARITY_RISE = 0U, /**< Polarity for TIx clock sources */
TIMER_CLK_POLARITY_FALL = 1U, /**< Polarity for TIx clock sources */
TIMER_CLK_POLARITY_BOTH = 3U, /**< Polarity for TIx clock sources */
} timer_clock_polarity_t;
/**
* @brief TIMER clock config structure definition
*/
typedef struct
{
typedef struct {
timer_clock_source_t source; /**< TIMER clock sources */
timer_clock_polarity_t polarity; /**< TIMER clock polarity */
timer_etr_psc_t psc; /**< TIMER clock prescaler */
@ -374,38 +350,35 @@ typedef struct
/**
* @brief TIMER slave mode
*/
typedef enum
{
TIMER_MODE_DISABLE = 0, /**< Slave mode is disable */
TIMER_MODE_ENC1 = 1, /**< Slave mode is encoder1 */
TIMER_MODE_ENC2 = 2, /**< Slave mode is encoder2 */
TIMER_MODE_ENC3 = 3, /**< Slave mode is encoder3 */
TIMER_MODE_RESET = 4, /**< Slave mode is reset */
TIMER_MODE_GATED = 5, /**< Slave mode is gated */
TIMER_MODE_TRIG = 6, /**< Slave mode is trigger */
TIMER_MODE_EXTERNAL1 = 7, /**< Slave mode is external1 */
typedef enum {
TIMER_MODE_DISABLE = 0U, /**< Slave mode is disable */
TIMER_MODE_ENC1 = 1U, /**< Slave mode is encoder1 */
TIMER_MODE_ENC2 = 2U, /**< Slave mode is encoder2 */
TIMER_MODE_ENC3 = 3U, /**< Slave mode is encoder3 */
TIMER_MODE_RESET = 4U, /**< Slave mode is reset */
TIMER_MODE_GATED = 5U, /**< Slave mode is gated */
TIMER_MODE_TRIG = 6U, /**< Slave mode is trigger */
TIMER_MODE_EXTERNAL1 = 7U, /**< Slave mode is external1 */
} timer_slave_mode_t;
/**
* @brief TIMER ts definition
*/
typedef enum
{
TIMER_TS_ITR0 = 0, /**< ITR0 */
TIMER_TS_ITR1 = 1, /**< ITR1 */
TIMER_TS_ITR2 = 2, /**< ITR2 */
TIMER_TS_ITR3 = 3, /**< ITR3 */
TIMER_TS_TI1F_ED = 4, /**< TI1F_ED */
TIMER_TS_TI1FP1 = 5, /**< TI1FP1 */
TIMER_TS_TI2FP2 = 6, /**< TI2FP2 */
TIMER_TS_ETRF = 7, /**< ETRF */
typedef enum {
TIMER_TS_ITR0 = 0U, /**< ITR0 */
TIMER_TS_ITR1 = 1U, /**< ITR1 */
TIMER_TS_ITR2 = 2U, /**< ITR2 */
TIMER_TS_ITR3 = 3U, /**< ITR3 */
TIMER_TS_TI1F_ED = 4U, /**< TI1F_ED */
TIMER_TS_TI1FP1 = 5U, /**< TI1FP1 */
TIMER_TS_TI2FP2 = 6U, /**< TI2FP2 */
TIMER_TS_ETRF = 7U, /**< ETRF */
} timer_ts_t;
/**
* @brief TIMER slave configuration structure definition
*/
typedef struct
{
typedef struct {
timer_slave_mode_t mode; /**< Slave mode selection */
timer_ts_t input; /**< Input Trigger source */
timer_clock_polarity_t polarity; /**< Input Trigger polarity */
@ -416,8 +389,7 @@ typedef struct
/**
* @brief TIMER hall sensor configuretion structure definition
*/
typedef struct
{
typedef struct {
timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */
timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */
uint32_t filter; /**< Specifies the input capture filter [0x0, 0xF] */
@ -427,28 +399,25 @@ typedef struct
/**
* @brief TIMER lock level
*/
typedef enum
{
TIMER_LOCK_LEVEL_OFF = 0, /**< Lock off */
TIMER_LOCK_LEVEL_1 = 1, /**< Lock level 1 */
TIMER_LOCK_LEVEL_2 = 2, /**< Lock level 2 */
TIMER_LOCK_LEVEL_3 = 3, /**< Lock level 3 */
typedef enum {
TIMER_LOCK_LEVEL_OFF = 0U, /**< Lock off */
TIMER_LOCK_LEVEL_1 = 1U, /**< Lock level 1 */
TIMER_LOCK_LEVEL_2 = 2U, /**< Lock level 2 */
TIMER_LOCK_LEVEL_3 = 3U, /**< Lock level 3 */
} timer_lock_level_t;
/**
* @brief TIMER break polarity
*/
typedef enum
{
TIMER_BREAK_POLARITY_LOW = 0, /**< LOW */
TIMER_BREAK_POLARITY_HIGH = 1, /**< HIGH */
typedef enum {
TIMER_BREAK_POLARITY_LOW = 0U, /**< LOW */
TIMER_BREAK_POLARITY_HIGH = 1U, /**< HIGH */
} timer_break_polarity_t;
/**
* @brief TIMER break and dead time configuretion structure definition
*/
typedef struct
{
typedef struct {
type_func_t off_run; /**< Enalbe/Disable off state in run mode */
type_func_t off_idle; /**< Enalbe/Disable off state in idle mode */
timer_lock_level_t lock_level; /**< Lock level */
@ -461,8 +430,7 @@ typedef struct
/**
* @brief TIMER commutation event channel configuretion structure definition
*/
typedef struct
{
typedef struct {
type_func_t en; /**< Enalbe/Disable the channel */
type_func_t n_en; /**< Enalbe/Disable the complementary channel */
timer_oc_mode_t mode; /**< Mode of the channel */
@ -471,31 +439,28 @@ typedef struct
/**
* @brief TIMER commutation event configuretion structure definition
*/
typedef struct
{
typedef struct {
timer_channel_config_t ch[3]; /**< Configure of channel */
} timer_com_channel_config_t;
/**
* @brief TIMER master mode selection
*/
typedef enum
{
TIMER_TRGO_RESET = 0, /**< RESET */
TIMER_TRGO_ENABLE = 1, /**< ENABLE */
TIMER_TRGO_UPDATE = 2, /**< UPDATE */
TIMER_TRGO_OC1 = 3, /**< OC1 */
TIMER_TRGO_OC1REF = 4, /**< OC1REF */
TIMER_TRGO_OC2REF = 5, /**< OC2REF */
TIMER_TRGO_OC3REF = 6, /**< OC3REF */
TIMER_TRGO_OC4REF = 7, /**< OC4REF */
typedef enum {
TIMER_TRGO_RESET = 0U, /**< RESET */
TIMER_TRGO_ENABLE = 1U, /**< ENABLE */
TIMER_TRGO_UPDATE = 2U, /**< UPDATE */
TIMER_TRGO_OC1 = 3U, /**< OC1 */
TIMER_TRGO_OC1REF = 4U, /**< OC1REF */
TIMER_TRGO_OC2REF = 5U, /**< OC2REF */
TIMER_TRGO_OC3REF = 6U, /**< OC3REF */
TIMER_TRGO_OC4REF = 7U, /**< OC4REF */
} timer_master_mode_sel_t;
/**
* @brief TIMER master configuretion structure definition
*/
typedef struct
{
typedef struct {
timer_master_mode_sel_t sel; /**< Specifies the active edge of the input signal */
type_func_t master_en; /**< Master/Slave mode selection */
} timer_master_config_t;
@ -503,8 +468,7 @@ typedef struct
/**
* @brief Specifies the event source
*/
typedef enum
{
typedef enum {
TIMER_SRC_UPDATE = (1U << 0), /**< Event source is update */
TIMER_SRC_CC1 = (1U << 1), /**< Event source is channel1 */
TIMER_SRC_CC2 = (1U << 2), /**< Event source is channel2 */
@ -518,8 +482,7 @@ typedef enum
/**
* @brief TIMER interrupt definition
*/
typedef enum
{
typedef enum {
TIMER_IT_UPDATE = (1U << 0), /**< Update interrupt bit */
TIMER_IT_CC1 = (1U << 1), /**< Channel1 interrupt bit */
TIMER_IT_CC2 = (1U << 2), /**< Channel2 interrupt bit */
@ -533,8 +496,7 @@ typedef enum
/**
* @brief TIMER DMA request
*/
typedef enum
{
typedef enum {
TIMER_DMA_UPDATE = (1U << 8), /**< DMA request from update */
TIMER_DMA_CC1 = (1U << 9), /**< DMA request from channel1 */
TIMER_DMA_CC2 = (1U << 10), /**< DMA request from channel2 */
@ -547,8 +509,7 @@ typedef enum
/**
* @brief TIMER flag definition
*/
typedef enum
{
typedef enum {
TIMER_FLAG_UPDATE = (1U << 0), /**< Update interrupt flag */
TIMER_FLAG_CC1 = (1U << 1), /**< Channel1 interrupt flag */
TIMER_FLAG_CC2 = (1U << 2), /**< Channel2 interrupt flag */
@ -591,11 +552,11 @@ typedef enum
* @brief Disable the TIMER peripheral.
*/
#define TIMER_DISABLE(hperh) \
do { \
do { \
if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \
&& (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \
CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \
} while (0)
} while (0)
/**
* @brief Disable the TIMER main output.
@ -603,21 +564,21 @@ typedef enum
* all the CCx and CCxN channels have been disabled
*/
#define TIMER_MOE_DISABLE(hperh) \
do { \
do { \
if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \
&& (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \
CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \
} while (0)
} while (0)
/**
* @brief Sets the TIMER autoreload register value on runtime without calling
* another time any Init function.
*/
#define TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \
do { \
do { \
(handle)->perh->AR = (AUTORELOAD); \
(handle)->init.period = (AUTORELOAD); \
} while (0)
} while (0)
/**
* @brief Gets the TIMER autoreload register value on runtime
@ -654,7 +615,7 @@ typedef enum
* TIMER_CHANNEL_4
*/
#define TIMER_CCx_ENABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \
(SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2))))))
(SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2))))))
/**
* @brief Disable channel
@ -666,7 +627,7 @@ typedef enum
* TIMER_CHANNEL_4
*/
#define TIMER_CCx_DISABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \
(CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2))))
(CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2))))
/**
* @brief Enable complementary channel
@ -975,7 +936,7 @@ void ald_timer_base_stop(timer_handle_t *hperh);
void ald_timer_base_start_by_it(timer_handle_t *hperh);
void ald_timer_base_stop_by_it(timer_handle_t *hperh);
#ifdef ALD_DMA
ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma,
ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh,
uint16_t *buf, uint32_t len, uint8_t dma_ch);
void ald_timer_base_stop_by_dma(timer_handle_t *hperh);
#endif
@ -994,7 +955,7 @@ void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
#ifdef ALD_DMA
ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch);
uint16_t *buf, uint32_t len, uint8_t dma_ch);
void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
#endif
/**
@ -1015,7 +976,7 @@ void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t
void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch);
#ifdef ALD_DMA
ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch);
uint16_t *buf, uint32_t len, uint8_t dma_ch);
void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
#endif
/**
@ -1033,7 +994,7 @@ void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
#ifdef ALD_DMA
ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch);
uint16_t *buf, uint32_t len, uint8_t dma_ch);
void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
#endif
/**
@ -1064,8 +1025,8 @@ void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
#ifdef ALD_DMA
ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1,
uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2);
uint16_t *buf1, uint16_t *buf2, uint32_t len,
uint8_t dma_ch1, uint8_t dma_ch2);
void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
#endif
/**
@ -1082,7 +1043,7 @@ void ald_timer_hall_sensor_stop(timer_handle_t *hperh);
void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh);
void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh);
#ifdef ALD_DMA
ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma,
ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh,
uint16_t *buf, uint32_t len, uint8_t dma_ch);
void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh);
#endif
@ -1099,7 +1060,7 @@ void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch);
void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
#ifdef ALD_DMA
ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma,
ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh,
timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch);
void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
#endif
@ -1116,7 +1077,7 @@ void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch);
void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
#ifdef ALD_DMA
ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma,
ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh,
timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch);
void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
#endif
@ -1140,8 +1101,8 @@ void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
* @{
*/
/* Control functions */
ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch);
ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch);
ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch);
ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch);
ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config,
timer_channel_t ch_out, timer_channel_t ch_in);
ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch);

51
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_trng.h
View File

@ -38,34 +38,31 @@ extern "C" {
/**
* @brief Data width
*/
typedef enum
{
TRNG_DSEL_1B = 0x0, /**< 1-bit */
TRNG_DSEL_8B = 0x1, /**< 8-bit */
TRNG_DSEL_16B = 0x2, /**< 16-bit */
TRNG_DSEL_32B = 0x3, /**< 32-bit */
typedef enum {
TRNG_DSEL_1B = 0x0U, /**< 1-bit */
TRNG_DSEL_8B = 0x1U, /**< 8-bit */
TRNG_DSEL_16B = 0x2U, /**< 16-bit */
TRNG_DSEL_32B = 0x3U, /**< 32-bit */
} trng_data_width_t;
/**
* @brief seed type
*/
typedef enum
{
TRNG_SEED_TYPE_0 = 0x0, /**< Using 0 as seed */
TRNG_SEED_TYPE_1 = 0x1, /**< Using 1 as seed */
TRNG_SEED_TYPE_LAST = 0x2, /**< Using last seed */
TRNG_SEED_TYPE_SEED = 0x3, /**< Using value of register */
typedef enum {
TRNG_SEED_TYPE_0 = 0x0U, /**< Using 0 as seed */
TRNG_SEED_TYPE_1 = 0x1U, /**< Using 1 as seed */
TRNG_SEED_TYPE_LAST = 0x2U, /**< Using last seed */
TRNG_SEED_TYPE_SEED = 0x3U, /**< Using value of register */
} trng_seed_type_t;
/**
* @brief TRNG init structure definition
*/
typedef struct
{
typedef struct {
trng_data_width_t data_width; /**< The width of data */
trng_seed_type_t seed_type; /**< The seed type */
uint32_t seed; /**< The value of seed */
uint16_t t_start; /**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */
uint16_t t_start; /**< T(start) = T(trng) * 2 ^ (t_start + 1), T(start) > 1ms */
uint8_t adjc; /**< Adjust parameter */
type_func_t posten; /**< Data back handle function */
} trng_init_t;
@ -73,19 +70,17 @@ typedef struct
/**
* @brief TRNG state structures definition
*/
typedef enum
{
TRNG_STATE_RESET = 0x0, /**< Peripheral is not initialized */
TRNG_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */
TRNG_STATE_BUSY = 0x2, /**< An internal process is ongoing */
TRNG_STATE_ERROR = 0x4, /**< Error */
typedef enum {
TRNG_STATE_RESET = 0x0U, /**< Peripheral is not initialized */
TRNG_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */
TRNG_STATE_BUSY = 0x2U, /**< An internal process is ongoing */
TRNG_STATE_ERROR = 0x4U, /**< Error */
} trng_state_t;
/**
* @brief State type
*/
typedef enum
{
typedef enum {
TRNG_STATUS_START = (1U << 0), /**< Start state */
TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */
TRNG_STATUS_SERR = (1U << 2), /**< Error state */
@ -94,8 +89,7 @@ typedef enum
/**
* @brief Interrupt type
*/
typedef enum
{
typedef enum {
TRNG_IT_START = (1U << 0), /**< Start */
TRNG_IT_DAVLD = (1U << 1), /**< Data valid */
TRNG_IT_SERR = (1U << 2), /**< Error */
@ -104,8 +98,7 @@ typedef enum
/**
* @brief Interrupt flag type
*/
typedef enum
{
typedef enum {
TRNG_IF_START = (1U << 0), /**< Start */
TRNG_IF_DAVLD = (1U << 1), /**< Data valid */
TRNG_IF_SERR = (1U << 2), /**< Error */
@ -114,8 +107,7 @@ typedef enum
/**
* @brief TRNG Handle Structure definition
*/
typedef struct trng_handle_s
{
typedef struct trng_handle_s {
TRNG_TypeDef *perh; /**< Register base address */
trng_init_t init; /**< TRNG required parameters */
uint32_t data; /**< result data */
@ -163,6 +155,7 @@ typedef struct trng_handle_s
((x) == TRNG_IF_DAVLD) || \
((x) == TRNG_IF_SERR))
#define IS_TRNG_ADJC(x) ((x) < 4)
#define IS_TRNG_T_START(x) ((x) < 8)
/**
* @}
*/

110
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_tsense.h
View File

@ -35,74 +35,74 @@ extern "C" {
/** @defgroup TSENSE_Public_Macros TSENSE Public Macros
* @{
*/
#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0))
#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669))
#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U))
#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U))
#define TSENSE_ENABLE() \
do { \
do { \
TSENSE_UNLOCK(); \
SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \
TSENSE_LOCK(); \
} while (0)
} while (0)
#define TSENSE_DISABLE() \
do { \
do { \
TSENSE_UNLOCK(); \
CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \
TSENSE_LOCK(); \
} while (0)
} while (0)
#define TSENSE_REQ_ENABLE() \
do { \
do { \
TSENSE_UNLOCK(); \
SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \
TSENSE_LOCK(); \
} while (0)
} while (0)
#define TSENSE_REQ_DISABLE() \
do { \
do { \
TSENSE_UNLOCK(); \
CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \
TSENSE_LOCK(); \
} while (0)
} while (0)
#define TSENSE_CTN_ENABLE() \
do { \
do { \
TSENSE_UNLOCK(); \
SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \
TSENSE_LOCK(); \
} while (0)
} while (0)
#define TSENSE_CTN_DISABLE() \
do { \
do { \
TSENSE_UNLOCK(); \
CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \
TSENSE_LOCK(); \
} while (0)
} while (0)
#define TSENSE_RESET() \
do { \
do { \
TSENSE_UNLOCK(); \
SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK); \
TSENSE_LOCK(); \
} while (0)
} while (0)
#define TSENSE_LTGR_WR(data) \
do { \
do { \
TSENSE_UNLOCK(); \
WRITE_REG(TSENSE->LTGR, (data)); \
TSENSE_LOCK(); \
} while(0)
} while (0)
#define TSENSE_HTGR_WR(data) \
do { \
do { \
TSENSE_UNLOCK(); \
WRITE_REG(TSENSE->HTGR, (data)); \
TSENSE_LOCK(); \
} while(0)
} while (0)
#define TSENSE_TBDR_WR(data) \
do { \
do { \
TSENSE_UNLOCK(); \
WRITE_REG(TSENSE->TBDR, (data)); \
TSENSE_LOCK(); \
} while(0)
} while (0)
#define TSENSE_TCALBDR_WR(data) \
do { \
do { \
TSENSE_UNLOCK(); \
WRITE_REG(TSENSE->TCALBDR, (data)); \
TSENSE_LOCK(); \
} while(0)
} while (0)
/**
* @}
*/
@ -113,50 +113,34 @@ extern "C" {
/**
* @brief Temperature update time
*/
typedef enum
{
TSENSE_UPDATE_CYCLE_3 = 0x3, /**< 3 Cycles */
TSENSE_UPDATE_CYCLE_4 = 0x4, /**< 4 Cycles */
TSENSE_UPDATE_CYCLE_5 = 0x5, /**< 5 Cycles */
TSENSE_UPDATE_CYCLE_6 = 0x6, /**< 6 Cycles */
TSENSE_UPDATE_CYCLE_7 = 0x7, /**< 7 Cycles */
typedef enum {
TSENSE_UPDATE_CYCLE_3 = 0x3U, /**< 3 Cycles */
TSENSE_UPDATE_CYCLE_4 = 0x4U, /**< 4 Cycles */
TSENSE_UPDATE_CYCLE_5 = 0x5U, /**< 5 Cycles */
TSENSE_UPDATE_CYCLE_6 = 0x6U, /**< 6 Cycles */
TSENSE_UPDATE_CYCLE_7 = 0x7U, /**< 7 Cycles */
} tsense_update_cycle_t;
/**
* @brief Temperature output mode
*/
typedef enum
{
TSENSE_OUTPUT_MODE_200 = 0x0, /**< 200 cycles update one temperature */
TSENSE_OUTPUT_MODE_400 = 0x1, /**< 400 cycles update one temperature */
TSENSE_OUTPUT_MODE_800 = 0x2, /**< 800 cycles update one temperature */
TSENSE_OUTPUT_MODE_1600 = 0x3, /**< 1600 cycles update one temperature */
TSENSE_OUTPUT_MODE_3200 = 0x4, /**< 3200 cycles update one temperature */
typedef enum {
TSENSE_OUTPUT_MODE_200 = 0x0U, /**< 200 cycles update one temperature */
TSENSE_OUTPUT_MODE_400 = 0x1U, /**< 400 cycles update one temperature */
TSENSE_OUTPUT_MODE_800 = 0x2U, /**< 800 cycles update one temperature */
TSENSE_OUTPUT_MODE_1600 = 0x3U, /**< 1600 cycles update one temperature */
TSENSE_OUTPUT_MODE_3200 = 0x4U, /**< 3200 cycles update one temperature */
} tsense_output_mode_t;
/**
* @brief Source select
*/
typedef enum
{
TSENSE_SOURCE_LOSC = 0x0, /**< LOSC */
TSENSE_SOURCE_LRC = 0x1, /**< LRC */
TSENSE_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */
TSENSE_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */
typedef enum {
TSENSE_SOURCE_LOSC = 0x0U, /**< LOSC */
TSENSE_SOURCE_LRC = 0x1U, /**< LRC */
} tsense_source_sel_t;
/**
* @brief TSENSE init structure definition
*/
typedef struct
{
tsense_update_cycle_t cycle; /**< Temperature update time */
tsense_output_mode_t mode; /**< Temperature output mode */
type_func_t ctn; /**< Continue mode */
uint8_t psc; /**< Perscaler */
} tsense_init_t;
/**
* @brief Define callback function type
*/
@ -169,20 +153,8 @@ typedef void (*tsense_cbk)(uint16_t value, ald_status_t status);
* @defgroup TSENSE_Private_Macros TSENSE Private Macros
* @{
*/
#define IS_TSENSE_UPDATE_CYCLE(x) (((x) == TSENSE_UPDATE_CYCLE_3) || \
((x) == TSENSE_UPDATE_CYCLE_4) || \
((x) == TSENSE_UPDATE_CYCLE_5) || \
((x) == TSENSE_UPDATE_CYCLE_6) || \
((x) == TSENSE_UPDATE_CYCLE_7))
#define IS_TSENSE_OUTPUT_MODE(x) (((x) == TSENSE_OUTPUT_MODE_200) || \
((x) == TSENSE_OUTPUT_MODE_400) || \
((x) == TSENSE_OUTPUT_MODE_800) || \
((x) == TSENSE_OUTPUT_MODE_1600) || \
((x) == TSENSE_OUTPUT_MODE_3200))
#define IS_TSENSE_SOURCE_SEL(x) (((x) == TSENSE_SOURCE_LOSC) || \
((x) == TSENSE_SOURCE_LRC) || \
((x) == TSENSE_SOURCE_HRC_DIV_1M ) || \
((x) == TSENSE_SOURCE_HOSC_DIV_1M))
((x) == TSENSE_SOURCE_LRC))
/**
* @}
*/
@ -194,7 +166,7 @@ typedef void (*tsense_cbk)(uint16_t value, ald_status_t status);
* @{
*/
/* Initialization functions */
extern void ald_tsense_init(tsense_init_t *init);
extern void ald_tsense_init(void);
extern void ald_tsense_source_select(tsense_source_sel_t sel);
/**
* @}

145
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_uart.h
View File

@ -74,89 +74,81 @@ extern "C" {
/**
* @brief UART word length
*/
typedef enum
{
UART_WORD_LENGTH_5B = 0x0, /**< 5-bits */
UART_WORD_LENGTH_6B = 0x1, /**< 6-bits */
UART_WORD_LENGTH_7B = 0x2, /**< 7-bits */
UART_WORD_LENGTH_8B = 0x3, /**< 8-bits */
typedef enum {
UART_WORD_LENGTH_5B = 0x0U, /**< 5-bits */
UART_WORD_LENGTH_6B = 0x1U, /**< 6-bits */
UART_WORD_LENGTH_7B = 0x2U, /**< 7-bits */
UART_WORD_LENGTH_8B = 0x3U, /**< 8-bits */
} uart_word_length_t;
/**
* @brief UART stop bits
*/
typedef enum
{
UART_STOP_BITS_1 = 0x0, /**< 1-bits */
UART_STOP_BITS_2 = 0x1, /**< 2-bits */
UART_STOP_BITS_0_5 = 0x0, /**< 0.5-bits, using smartcard mode */
UART_STOP_BITS_1_5 = 0x1, /**< 1.5-bits, using smartcard mode */
typedef enum {
UART_STOP_BITS_1 = 0x0U, /**< 1-bits */
UART_STOP_BITS_2 = 0x1U, /**< 2-bits */
UART_STOP_BITS_0_5 = 0x0U, /**< 0.5-bits, using smartcard mode */
UART_STOP_BITS_1_5 = 0x1U, /**< 1.5-bits, using smartcard mode */
} uart_stop_bits_t;
/**
* @brief UART parity
*/
typedef enum
{
UART_PARITY_NONE = 0x0, /**< Not parity */
UART_PARITY_ODD = 0x1, /**< Odd parity */
UART_PARITY_EVEN = 0x3, /**< Even parity */
typedef enum {
UART_PARITY_NONE = 0x0U, /**< Not parity */
UART_PARITY_ODD = 0x1U, /**< Odd parity */
UART_PARITY_EVEN = 0x3U, /**< Even parity */
} uart_parity_t;
/**
* @brief UART mode
*/
typedef enum
{
UART_MODE_UART = 0x0, /**< UART */
UART_MODE_LIN = 0x1, /**< LIN */
UART_MODE_IrDA = 0x2, /**< IrDA */
UART_MODE_RS485 = 0x3, /**< RS485 */
UART_MODE_HDSEL = 0x4, /**< Single-wire half-duplex */
typedef enum {
UART_MODE_UART = 0x0U, /**< UART */
UART_MODE_LIN = 0x1U, /**< LIN */
UART_MODE_IrDA = 0x2U, /**< IrDA */
UART_MODE_RS485 = 0x3U, /**< RS485 */
UART_MODE_HDSEL = 0x4U, /**< Single-wire half-duplex */
} uart_mode_t;
/**
* @brief UART hardware flow control
*/
typedef enum
{
UART_HW_FLOW_CTL_DISABLE = 0x0, /**< Auto-flow-control disable */
UART_HW_FLOW_CTL_ENABLE = 0x1, /**< Auto-flow-control enable */
typedef enum {
UART_HW_FLOW_CTL_DISABLE = 0x0U, /**< Auto-flow-control disable */
UART_HW_FLOW_CTL_ENABLE = 0x1U, /**< Auto-flow-control enable */
} uart_hw_flow_ctl_t;
/**
* @brief ALD UART state
*/
typedef enum
{
UART_STATE_RESET = 0x00, /**< Peripheral is not initialized */
UART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
UART_STATE_BUSY = 0x02, /**< an internal process is ongoing */
UART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */
UART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */
UART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */
UART_STATE_TIMEOUT = 0x03, /**< Timeout state */
UART_STATE_ERROR = 0x04, /**< Error */
typedef enum {
UART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */
UART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
UART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
UART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */
UART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */
UART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */
UART_STATE_TIMEOUT = 0x03U, /**< Timeout state */
UART_STATE_ERROR = 0x04U, /**< Error */
} uart_state_t;
/**
* @brief UART error codes
*/
typedef enum
{
UART_ERROR_NONE = ((uint32_t)0x00), /**< No error */
UART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */
UART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */
UART_ERROR_FE = ((uint32_t)0x04), /**< frame error */
UART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */
UART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */
typedef enum {
UART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */
UART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */
UART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */
UART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */
UART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */
UART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */
} uart_error_t;
/**
* @brief UART init structure definition
*/
typedef struct
{
typedef struct {
uint32_t baud; /**< Specifies the uart communication baud rate */
uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */
uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */
@ -168,8 +160,7 @@ typedef struct
/**
* @brief UART handle structure definition
*/
typedef struct uart_handle_s
{
typedef struct uart_handle_s {
UART_TypeDef *perh; /**< UART registers base address */
uart_init_t init; /**< UART communication parameters */
uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */
@ -194,8 +185,7 @@ typedef struct uart_handle_s
/**
* @brief UART RS485 configure structure definition
*/
typedef struct
{
typedef struct {
type_func_t normal; /**< Normal mode */
type_func_t dir; /**< Auto-direction mode */
type_func_t invert; /**< Address detection invert */
@ -205,49 +195,44 @@ typedef struct
/**
* @brief LIN detection break length
*/
typedef enum
{
LIN_BREAK_LEN_10B = 0x0, /**< 10-bit break */
LIN_BREAK_LEN_11B = 0x1, /**< 11-bit break */
typedef enum {
LIN_BREAK_LEN_10B = 0x0U, /**< 10-bit break */
LIN_BREAK_LEN_11B = 0x1U, /**< 11-bit break */
} uart_lin_break_len_t;
/**
* @brief UART TXFIFO size
*/
typedef enum
{
UART_TXFIFO_EMPTY = 0x0, /**< Empty */
UART_TXFIFO_2BYTE = 0x1, /**< 2-Bytes */
UART_TXFIFO_4BYTE = 0x2, /**< 4-Bytes */
UART_TXFIFO_8BYTE = 0x3, /**< 8-Bytes */
typedef enum {
UART_TXFIFO_EMPTY = 0x0U, /**< Empty */
UART_TXFIFO_2BYTE = 0x1U, /**< 2-Bytes */
UART_TXFIFO_4BYTE = 0x2U, /**< 4-Bytes */
UART_TXFIFO_8BYTE = 0x3U, /**< 8-Bytes */
} uart_txfifo_t;
/**
* @brief UART RXFIFO size
*/
typedef enum
{
UART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */
UART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */
UART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */
UART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */
typedef enum {
UART_RXFIFO_1BYTE = 0x0U, /**< 1-Byte */
UART_RXFIFO_4BYTE = 0x1U, /**< 4-Bytes */
UART_RXFIFO_8BYTE = 0x2U, /**< 8-Bytes */
UART_RXFIFO_14BYTE = 0x3U, /**< 14-Bytes */
} uart_rxfifo_t;
/**
* @brief UART auto-baud mode
*/
typedef enum
{
UART_ABRMOD_1_TO_0 = 0x0, /**< Detect bit0:1, bit1:0 */
UART_ABRMOD_1 = 0x1, /**< Detect bit0:1 */
UART_ABRMOD_0_TO_1 = 0x2, /**< Detect bit0:0, bit1:1 */
typedef enum {
UART_ABRMOD_1_TO_0 = 0x0U, /**< Detect bit0:1, bit1:0 */
UART_ABRMOD_1 = 0x1U, /**< Detect bit0:1 */
UART_ABRMOD_0_TO_1 = 0x2U, /**< Detect bit0:0, bit1:1 */
} uart_auto_baud_mode_t;
/**
* @brief UART status types
*/
typedef enum
{
typedef enum {
UART_STATUS_DR = (1U << 0), /**< Data ready */
UART_STATUS_OE = (1U << 1), /**< Overrun error */
UART_STATUS_PE = (1U << 2), /**< Parity error */
@ -268,8 +253,7 @@ typedef enum
/**
* @brief UART interrupt types
*/
typedef enum
{
typedef enum {
UART_IT_RXRD = (1U << 0), /**< Receive data available */
UART_IT_TXS = (1U << 1), /**< Tx empty status */
UART_IT_RXS = (1U << 2), /**< Rx line status */
@ -287,8 +271,7 @@ typedef enum
/**
* @brief UART flags types
*/
typedef enum
{
typedef enum {
UART_IF_RXRD = (1U << 0), /**< Receive data available */
UART_IF_TXS = (1U << 1), /**< Tx empty status */
UART_IF_RXS = (1U << 2), /**< Rx line status */
@ -434,8 +417,8 @@ void ald_uart_irq_handler(uart_handle_t *hperh);
/* Peripheral Control functions */
void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state);
void ald_uart_dma_req_config(uart_handle_t *hperh, type_func_t state);
void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level);
void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level);
void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config);
void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config);
void ald_uart_lin_send_break(uart_handle_t *hperh);
void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len);
void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode);

156
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_usart.h
View File

@ -18,7 +18,7 @@
#define __ALD_USART_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@ -40,124 +40,112 @@ extern "C" {
/**
* @brief usart_word_length
*/
typedef enum
{
USART_WORD_LENGTH_8B = 0x0, /**< Word length is 8-bits */
USART_WORD_LENGTH_9B = 0x1, /**< Word length is 9-bits */
typedef enum {
USART_WORD_LENGTH_8B = 0x0U, /**< Word length is 8-bits */
USART_WORD_LENGTH_9B = 0x1U, /**< Word length is 9-bits */
} usart_word_length_t;
/**
* @brief usart_stop_bits
*/
typedef enum
{
USART_STOP_BITS_1 = 0x0, /**< Stop bits is 1-bits */
USART_STOP_BITS_0_5 = 0x1, /**< Stop bits is 0.5-bits */
USART_STOP_BITS_2 = 0x2, /**< Stop bits is 2-bits */
USART_STOP_BITS_1_5 = 0x3, /**< Stop bits is 1.5-bits */
typedef enum {
USART_STOP_BITS_1 = 0x0U, /**< Stop bits is 1-bits */
USART_STOP_BITS_0_5 = 0x1U, /**< Stop bits is 0.5-bits */
USART_STOP_BITS_2 = 0x2U, /**< Stop bits is 2-bits */
USART_STOP_BITS_1_5 = 0x3U, /**< Stop bits is 1.5-bits */
} usart_stop_bits_t;
/**
* @brief usart_parity
*/
typedef enum
{
USART_PARITY_NONE = 0x0, /**< Not parity */
USART_PARITY_EVEN = 0x2, /**< Even parity */
USART_PARITY_ODD = 0x3, /**< Odd parity */
typedef enum {
USART_PARITY_NONE = 0x0U, /**< Not parity */
USART_PARITY_EVEN = 0x2U, /**< Even parity */
USART_PARITY_ODD = 0x3U, /**< Odd parity */
} usart_parity_t;
/**
* @brief usart_mode
*/
typedef enum
{
USART_MODE_RX = 0x1, /**< TX mode */
USART_MODE_TX = 0x2, /**< RX mode */
USART_MODE_TX_RX = 0x3, /**< TX & RX mode */
typedef enum {
USART_MODE_RX = 0x1U, /**< TX mode */
USART_MODE_TX = 0x2U, /**< RX mode */
USART_MODE_TX_RX = 0x3U, /**< TX & RX mode */
} usart_mode_t;
/**
* @brief usart_hardware_flow_control
*/
typedef enum
{
USART_HW_FLOW_CTL_NONE = 0x0, /**< Not flow control */
USART_HW_FLOW_CTL_RTS = 0x1, /**< RTS flow control */
USART_HW_FLOW_CTL_CTS = 0x2, /**< CTS flow control */
USART_HW_FLOW_CTL_RTS_CTS = 0x3, /**< RTS & CTS flow control */
typedef enum {
USART_HW_FLOW_CTL_NONE = 0x0U, /**< Not flow control */
USART_HW_FLOW_CTL_RTS = 0x1U, /**< RTS flow control */
USART_HW_FLOW_CTL_CTS = 0x2U, /**< CTS flow control */
USART_HW_FLOW_CTL_RTS_CTS = 0x3U, /**< RTS & CTS flow control */
} usart_hw_flow_ctl_t;
/**
* @brief usart_clock
*/
typedef enum
{
USART_CLOCK_DISABLE = 0x0, /**< Disable clock output */
USART_CLOCK_ENABLE = 0x1, /**< Enable clock output */
typedef enum {
USART_CLOCK_DISABLE = 0x0U, /**< Disable clock output */
USART_CLOCK_ENABLE = 0x1U, /**< Enable clock output */
} usart_clock_t;
/**
* @brief usart_clock_polarity
*/
typedef enum
{
USART_CPOL_LOW = 0x0, /**< Clock polarity low */
USART_CPOL_HIGH = 0x1, /**< Clock polarity high */
typedef enum {
USART_CPOL_LOW = 0x0U, /**< Clock polarity low */
USART_CPOL_HIGH = 0x1U, /**< Clock polarity high */
} usart_cpol_t;
/**
* @brief usart_clock_phase
*/
typedef enum
{
USART_CPHA_1EDGE = 0x0, /**< Clock phase first edge */
USART_CPHA_2EDGE = 0x1, /**< Clock phase second edge */
typedef enum {
USART_CPHA_1EDGE = 0x0U, /**< Clock phase first edge */
USART_CPHA_2EDGE = 0x1U, /**< Clock phase second edge */
} usart_cpha_t;
/**
* @brief usart_last_bit
*/
typedef enum
{
USART_LAST_BIT_DISABLE = 0x0, /**< Disable last bit clock output */
USART_LAST_BIT_ENABLE = 0x1, /**< Enable last bit clock output */
typedef enum {
USART_LAST_BIT_DISABLE = 0x0U, /**< Disable last bit clock output */
USART_LAST_BIT_ENABLE = 0x1U, /**< Enable last bit clock output */
} usart_last_bit_t;
/**
* @brief usart state structures definition
*/
typedef enum
{
USART_STATE_RESET = 0x00, /**< Peripheral is not initialized */
USART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
USART_STATE_BUSY = 0x02, /**< an internal process is ongoing */
USART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */
USART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */
USART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */
USART_STATE_TIMEOUT = 0x03, /**< Timeout state */
USART_STATE_ERROR = 0x04, /**< Error */
typedef enum {
USART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */
USART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
USART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
USART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */
USART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */
USART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */
USART_STATE_TIMEOUT = 0x03U, /**< Timeout state */
USART_STATE_ERROR = 0x04U, /**< Error */
} usart_state_t;
/**
* @brief usart error codes
*/
typedef enum
{
USART_ERROR_NONE = ((uint32_t)0x00), /**< No error */
USART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */
USART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */
USART_ERROR_FE = ((uint32_t)0x04), /**< frame error */
USART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */
USART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */
typedef enum {
USART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */
USART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */
USART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */
USART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */
USART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */
USART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */
} usart_error_t;
/**
* @brief usart init structure definition
*/
typedef struct
{
typedef struct {
uint32_t baud; /**< This member configures the Usart communication baud rate. */
usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */
usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */
@ -168,14 +156,12 @@ typedef struct
word length is set to 8 data bits). */
usart_mode_t mode; /**< Specifies wether the Receive or Transmit mode is enabled or disabled. */
usart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled. */
type_func_t over_sampling; /**< Specifies whether the Over sampling 8 is enabled or disabled. */
} usart_init_t;
/**
* @brief USART handle structure definition
*/
typedef struct usart_handle_s
{
typedef struct usart_handle_s {
USART_TypeDef *perh; /**< USART registers base address */
usart_init_t init; /**< USART communication parameters */
uint8_t *tx_buf; /**< Pointer to USART Tx transfer buffer */
@ -202,8 +188,7 @@ typedef struct usart_handle_s
/**
* @brief USART clock init structure definition
*/
typedef struct
{
typedef struct {
usart_clock_t clk; /**< Pecifies whether the USART clock is enable or disable. */
usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */
usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made. */
@ -215,8 +200,7 @@ typedef struct
/**
* @brief usart_dma_request
*/
typedef enum
{
typedef enum {
USART_DMA_REQ_TX = (1U << 7), /**< TX dma bit */
USART_DMA_REQ_RX = (1U << 6), /**< RX dma bit */
} usart_dma_req_t;
@ -224,32 +208,29 @@ typedef enum
/**
* @brief usart_wakeup_methods
*/
typedef enum
{
USART_WAKEUP_IDLE = 0x0, /**< Wake up the machine when bus-line is idle */
USART_WAKEUP_ADDR = 0x1, /**< Wake up the machine when match the address */
typedef enum {
USART_WAKEUP_IDLE = 0x0U, /**< Wake up the machine when bus-line is idle */
USART_WAKEUP_ADDR = 0x1U, /**< Wake up the machine when match the address */
} usart_wakeup_t;
/**
* @brief usart_IrDA_low_power
*/
typedef enum
{
USART_IrDA_MODE_NORMAL = 0x0, /**< Normal IrDA mode */
USART_IrDA_MODE_LOW_POWER = 0x1, /**< Low-power IrDA mode */
typedef enum {
USART_IrDA_MODE_NORMAL = 0x0U, /**< Normal IrDA mode */
USART_IrDA_MODE_LOW_POWER = 0x1U, /**< Low-power IrDA mode */
} usart_IrDA_mode_t;
/**
* @brief USART interrupts definition
*/
typedef enum
{
typedef enum {
USART_IT_PE = ((1U << 8) | (1U << 16)), /**< Parity error */
USART_IT_TXE = ((1U << 7) | (1U << 16)), /**< Tx empty */
USART_IT_TC = ((1U << 6) | (1U << 16)), /**< Tx complete */
USART_IT_RXNE = ((1U << 5) | (1U << 16)), /**< Rx not empty */
USART_IT_IDLE = ((1U << 4) | (1U << 16)), /**< Idle */
USART_IT_CTS = ((1U << 10) | (1U << 18)), /**< CTS */
USART_IT_CTS = ((1U << 10)| (1U << 18)), /**< CTS */
USART_IT_ERR = ((1U << 0) | (1U << 18)), /**< Error */
USART_IT_ORE = (1U << 3), /**< Overrun error */
USART_IT_NE = (1U << 2), /**< Noise error */
@ -259,8 +240,7 @@ typedef enum
/**
* @brief USART flags
*/
typedef enum
{
typedef enum {
USART_FLAG_CTS = (1U << 9), /**< CTS */
USART_FLAG_TXE = (1U << 7), /**< Tx empty */
USART_FLAG_TC = (1U << 6), /**< Tx complete */
@ -293,12 +273,12 @@ typedef enum
* @{
*/
#define USART_CLEAR_PEFLAG(handle) \
do { \
do { \
__IO uint32_t tmpreg; \
tmpreg = (handle)->perh->STAT; \
tmpreg = (handle)->perh->DATA; \
UNUSED(tmpreg); \
} while (0)
} while (0)
/**
* @}
*/
@ -383,7 +363,7 @@ typedef enum
* @{
*/
#define USART_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK))
/**
/**
* @}
*/
@ -450,8 +430,8 @@ typedef enum
#define IS_USART_ADDRESS(x) ((x) <= 0xF)
#define IS_USART_DATA(x) ((x) <= 0x1FF)
#define DUMMY_DATA 0xFFFF
#define USART_STATE_TX_MASK (1 << 4)
#define USART_STATE_RX_MASK (1 << 5)
#define USART_STATE_TX_MASK (1U << 4)
#define USART_STATE_RX_MASK (1U << 5)
/**
* @}

19
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_wdt.h
View File

@ -38,12 +38,11 @@ extern "C" {
/**
* @brief Wwdt no dog window
*/
typedef enum
{
WWDT_WIN_25 = 0x0, /**< No dog window size: 25% */
WWDT_WIN_50 = 0x1, /**< No dog window size: 50% */
WWDT_WIN_75 = 0x2, /**< No dog window size: 75% */
WWDT_WIN_00 = 0x3, /**< No dog window size: 0% */
typedef enum {
WWDT_WIN_25 = 0x0U, /**< No dog window size: 25% */
WWDT_WIN_50 = 0x1U, /**< No dog window size: 50% */
WWDT_WIN_75 = 0x2U, /**< No dog window size: 75% */
WWDT_WIN_00 = 0x3U, /**< No dog window size: 0% */
} wwdt_win_t;
/**
@ -54,10 +53,10 @@ typedef enum
* @defgroup WDT_Private_Macros WDT Private Macros
* @{
*/
#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551);}
#define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFF);}
#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551);}
#define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFF);}
#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);}
#define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);}
#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);}
#define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);}
/**
* @}

53
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/type.h
View File

@ -34,41 +34,36 @@ extern "C" {
#define __isr__
typedef enum
{
RESET = 0x0,
SET = 0x1,
typedef enum {
RESET = 0x0U,
SET = 0x1U,
} flag_status_t, it_status_t;
typedef enum
{
BIT_RESET = 0x0,
BIT_SET = 0x1,
typedef enum {
BIT_RESET = 0x0U,
BIT_SET = 0x1U,
} bit_status_t;
typedef enum
{
DISABLE = 0x0,
ENABLE = 0x1,
typedef enum {
DISABLE = 0x0U,
ENABLE = 0x1U,
} type_func_t;
#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE))
typedef enum
{
FALSE = 0x0,
TRUE = 0x1,
typedef enum {
FALSE = 0x0U,
TRUE = 0x1U,
} type_bool_t;
typedef enum
{
UNLOCK = 0x0,
LOCK = 0x1,
typedef enum {
UNLOCK = 0x0U,
LOCK = 0x1U,
} lock_state_t;
#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK))
#define BIT(x) ((1U << (x)))
#define BITS(s, e) ((0xffffffff << (s)) & (0xffffffff >> (31 - (e))))
#define BITS(s, e) ((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e))))
#define SET_BIT(reg, bit) ((reg) |= (bit))
#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit))
#define READ_BIT(reg, bit) ((reg) & (bit))
@ -82,13 +77,13 @@ typedef enum
#ifdef USE_ASSERT
#define assert_param(x) \
do { \
do { \
if (!(x)) { \
__disable_irq(); \
while (1) \
; \
} \
} while (0)
} while (0)
#else
#define assert_param(x)
#endif
@ -112,12 +107,12 @@ __STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val)
}
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
#ifdef __cplusplus

34
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/utils.h
View File

@ -18,7 +18,7 @@
#define __UTILS_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include <stdlib.h>
@ -46,23 +46,21 @@ extern uint32_t __systick_interval;
/**
* @brief ALD Status structures definition
*/
typedef enum
{
OK = 0x0,
ERROR = 0x1,
BUSY = 0x2,
TIMEOUT = 0x3
typedef enum {
OK = 0x0U, /**< Status: OK */
ERROR = 0x1U, /**< Status: ERROR */
BUSY = 0x2U, /**< Status: BUSY */
TIMEOUT = 0x3U, /**< Status: TIMEOUT */
} ald_status_t;
/**
* @brief SysTick interval definition
*/
typedef enum
{
SYSTICK_INTERVAL_1MS = 1000, /**< Interval is 1ms */
SYSTICK_INTERVAL_10MS = 100, /**< Interval is 10ms */
SYSTICK_INTERVAL_100MS = 10, /**< Interval is 100ms */
SYSTICK_INTERVAL_1000MS = 1, /**< Interval is 1s */
typedef enum {
SYSTICK_INTERVAL_1MS = 1000U, /**< Interval is 1ms */
SYSTICK_INTERVAL_10MS = 100U, /**< Interval is 10ms */
SYSTICK_INTERVAL_100MS = 10U, /**< Interval is 100ms */
SYSTICK_INTERVAL_1000MS = 1U, /**< Interval is 1s */
} systick_interval_t;
/**
* @}
@ -71,8 +69,7 @@ typedef enum
/** @defgroup ALD_Public_Macros Public Macros
* @{
*/
#define ALD_MAX_DELAY 0xFFFFFFFF
#define ALD_MAX_DELAY 0xFFFFFFFFU
#define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET)
#define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET)
#define RESET_HANDLE_STATE(x) ((x)->state = 0)
@ -98,6 +95,10 @@ typedef enum
/** @defgroup ALD_Private_Macros Private Macros
* @{
*/
#define MCU_UID0_ADDR 0x000403E0U
#define MCU_UID1_ADDR 0x000403E8U
#define MCU_UID2_ADDR 0x000403F0U
#define MCU_CHIPID_ADDR 0x000403F8U
#define IS_PRIO(x) ((x) < 4)
#define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \
((x) == SYSTICK_INTERVAL_10MS) || \
@ -140,7 +141,8 @@ ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, ui
void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status);
uint32_t ald_mcu_get_tick(void);
uint32_t ald_mcu_get_cpu_id(void);
void ald_mcu_get_uid(uint8_t *buf);
uint32_t ald_mcu_get_chipid(void);
/**
* @}
*/

24
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_acmp.c
View File

@ -83,8 +83,7 @@ ald_status_t ald_acmp_init(acmp_handle_t *hperh)
else
SET_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK);
switch (hperh->init.edge)
{
switch (hperh->init.edge) {
case ACMP_EDGE_NONE:
CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
@ -112,11 +111,8 @@ ald_status_t ald_acmp_init(acmp_handle_t *hperh)
SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK);
tmp = 0;
while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0)
{
if (tmp++ >= 600000)
{
while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) {
if (tmp++ >= 600000) {
__UNLOCK(hperh);
return ERROR;
}
@ -199,8 +195,7 @@ it_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
assert_param(IS_ACMP_TYPE(hperh->perh));
assert_param(IS_ACMP_FLAG_TYPE(flag));
if (hperh->perh->RIF & flag)
{
if (hperh->perh->RIF & flag) {
__UNLOCK(hperh);
return SET;
}
@ -260,8 +255,7 @@ flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status)
assert_param(IS_ACMP_TYPE(hperh->perh));
assert_param(IS_ACMP_STATUS_TYPE(status));
if (hperh->perh->STAT & status)
{
if (hperh->perh->STAT & status) {
__UNLOCK(hperh);
return SET;
}
@ -285,19 +279,15 @@ flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status)
*/
void ald_acmp_irq_handler(acmp_handle_t *hperh)
{
if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_WARMUP) == SET))
{
if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_WARMUP) == SET)) {
if (hperh->acmp_warmup_cplt_cbk)
hperh->acmp_warmup_cplt_cbk(hperh);
ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP);
}
if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_EDGE) == SET))
{
if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_EDGE) == SET)) {
if (hperh->acmp_edge_cplt_cbk)
hperh->acmp_edge_cplt_cbk(hperh);
ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE);
}

836
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_adc.c
View File

File diff suppressed because it is too large Load Diff

28
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_bkpc.c
View File

@ -41,7 +41,7 @@
==============================================================================
[..] This section provides functions allowing to:
(+) ald_bkpc_ldo_config() API can configure LDO in backup field.
(+) ald_bkpc_bor_config() API can configure BOR in backup field.
(+) ald_bkpc_standby_wakeup_config() API can configure STANDBY wakeup.
@endverbatim
* @{
@ -69,26 +69,30 @@ void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state)
}
/**
* @brief Configure bor voltage in backup field
* @param vol: Voltage select.
* @param state: DISABLE/ENABLE.
* @brief Configure standby wakeup in backup field
* @param port: Wakeup port
* @param level: HIGH/LOW.
* @retval None
*/
void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state)
void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
{
assert_param(IS_BKPC_BOR_VOL(vol));
assert_param(IS_FUNC_STATE(state));
assert_param(IS_BKPC_WAKEUP_PORT(port));
assert_param(IS_BKPC_WAKEUP_LEVEL(level));
if (port == PMU_STANDBY_PORT_SEL_NONE) {
BKPC_UNLOCK();
MODIFY_REG(BKPC->PCR, BKPC_PCR_BOREN_MSK, state << BKPC_PCR_BOREN_POS);
if (state)
MODIFY_REG(BKPC->PCR, BKPC_PCR_BORS_MSK, vol << BKPC_PCR_BORS_POSS);
CLEAR_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK);
BKPC_LOCK();
return;
}
BKPC_UNLOCK();
SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK);
MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS);
MODIFY_REG(BKPC->CR, BKPC_CR_WKPOL_MSK, level << BKPC_CR_WKPOL_POS);
BKPC_LOCK();
return;
}
/**
* @}

3
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_calc.c
View File

@ -45,13 +45,12 @@
/**
* @brief Square root operation.
* @param data: The data;
* @param data: The radicand
* @retval The value of square root.
*/
uint32_t ald_calc_sqrt(uint32_t data)
{
WRITE_REG(CALC->RDCND, data);
while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK));
return READ_REG(CALC->SQRTRES);

166
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_cmu.c
View File

@ -125,7 +125,7 @@
* @defgroup CMU_Private_Variables CMU Private Variables
* @{
*/
uint32_t __system_clock = 24000000;
uint32_t __system_clock = 24000000U;
/**
* @}
*/
@ -158,8 +158,7 @@ static void cmu_clock_update(uint32_t clock)
void ald_cmu_irq_handler(void)
{
/* HOSC stop */
if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK))
{
if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) {
SYSCFG_UNLOCK();
SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK);
SYSCFG_LOCK();
@ -168,13 +167,11 @@ void ald_cmu_irq_handler(void)
&& ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1)
|| ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))))
cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000);
ald_cmu_irq_cbk(CMU_HOSC_STOP);
}
/* HOSC start */
if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK))
{
if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) {
SYSCFG_UNLOCK();
SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK);
SYSCFG_LOCK();
@ -182,13 +179,11 @@ void ald_cmu_irq_handler(void)
if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK))
&& ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))
cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000);
ald_cmu_irq_cbk(CMU_HOSC_START);
}
/* LOSC stop */
if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK))
{
if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK)) {
SYSCFG_UNLOCK();
SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK);
SYSCFG_LOCK();
@ -196,8 +191,7 @@ void ald_cmu_irq_handler(void)
}
/* LOSC start */
if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIE_MSK))
{
if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIE_MSK)) {
SYSCFG_UNLOCK();
SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK);
SYSCFG_LOCK();
@ -205,8 +199,7 @@ void ald_cmu_irq_handler(void)
}
/* PLL1 lose */
if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK))
{
if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) {
SYSCFG_UNLOCK();
SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK);
SYSCFG_LOCK();
@ -215,7 +208,6 @@ void ald_cmu_irq_handler(void)
&& ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1)
|| ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))))
cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000);
ald_cmu_irq_cbk(CMU_PLL1_UNLOCK);
}
@ -260,11 +252,9 @@ ald_status_t ald_cmu_clock_config_default(void)
/* Select HRC */
MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS);
while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC)
{
if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) {
SYSCFG_LOCK();
return ERROR;
}
@ -299,17 +289,14 @@ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock)
assert_param(IS_CMU_CLOCK(clk));
SYSCFG_UNLOCK();
switch (clk)
{
switch (clk) {
case CMU_CLOCK_HRC:
assert_param(clock == 24000000 || clock == 2000000);
MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS);
while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC)
{
if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) {
SYSCFG_LOCK();
return ERROR;
}
@ -322,13 +309,9 @@ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock)
SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK);
for (cnt = 4000; cnt; --cnt);
cnt = 4000;
while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt));
cnt = 4000;
while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt));
cmu_clock_update(clock);
@ -339,11 +322,9 @@ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock)
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS);
while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC)
{
if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) {
SYSCFG_LOCK();
return ERROR;
}
@ -351,11 +332,8 @@ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock)
SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);
cnt = 4000;
while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt));
cnt = 4000;
while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt));
cmu_clock_update(32768);
@ -366,11 +344,9 @@ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock)
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS);
while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC)
{
if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) {
SYSCFG_LOCK();
return ERROR;
}
@ -378,11 +354,8 @@ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock)
SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);
cnt = 4000;
while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt));
cnt = 4000;
while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt));
cmu_clock_update(32768);
@ -390,11 +363,9 @@ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock)
case CMU_CLOCK_PLL1:
MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS);
while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1)
{
if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) {
SYSCFG_LOCK();
return ERROR;
}
@ -402,13 +373,9 @@ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock)
SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK);
for (cnt = 4000; cnt; --cnt);
cnt = 4000;
while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt));
cnt = 4000;
while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt));
cmu_clock_update(clock);
@ -418,11 +385,9 @@ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock)
assert_param(clock <= 24000000);
MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS);
while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC)
{
if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) {
SYSCFG_LOCK();
return ERROR;
}
@ -431,13 +396,9 @@ ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock)
MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1);
for (cnt = 4000; cnt; --cnt);
cnt = 4000;
while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt));
cnt = 4000;
while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt));
cmu_clock_update(clock);
@ -470,18 +431,15 @@ void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output)
SYSCFG_UNLOCK();
if (input == CMU_PLL1_INPUT_HRC_6)
{
if (input == CMU_PLL1_INPUT_HRC_6) {
SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK);
}
else if (input == CMU_PLL1_INPUT_PLL2)
{
else if (input == CMU_PLL1_INPUT_PLL2) {
SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);
CLEAR_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2RFS_MSK);
SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK);
}
else
{
else {
SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK);
}
@ -490,9 +448,7 @@ void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output)
SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK);
while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL1LCKN_MSK)) && (--cnt));
cnt = 4000;
while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt));
SYSCFG_LOCK();
@ -534,13 +490,10 @@ int32_t ald_cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_ou
WRITE_REG(CMU->HRCACR, tmp);
while (cnt--);
cnt = 30000;
while ((READ_BIT(CMU->HRCACR, CMU_HRCACR_BUSY_MSK)) && (--cnt));
if (READ_BITS(CMU->HRCACR, CMU_HRCACR_STA_MSK, CMU_HRCACR_STA_POSS) != 1)
{
if (READ_BITS(CMU->HRCACR, CMU_HRCACR_STA_MSK, CMU_HRCACR_STA_POSS) != 1) {
CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK);
SYSCFG_LOCK();
return -1;
@ -591,8 +544,7 @@ void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div)
SYSCFG_UNLOCK();
switch (bus)
{
switch (bus) {
case CMU_HCLK_1:
MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS);
break;
@ -600,13 +552,11 @@ void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div)
case CMU_SYS:
MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS);
if ((__system_clock >> div) <= 1000000)
{
if ((__system_clock >> div) <= 1000000) {
/* Close SysTick interrupt in lower clock */
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
}
else
{
else {
ald_tick_init(TICK_INT_PRIORITY);
}
@ -708,8 +658,7 @@ void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status)
SYSCFG_UNLOCK();
if (status)
{
if (status) {
SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK);
MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clock << CMU_HOSMCR_FRQS_POSS);
SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK);
@ -717,8 +666,7 @@ void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status)
ald_mcu_irq_config(CMU_IRQn, 3, ENABLE);
}
else
{
else {
CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK);
CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK);
@ -740,16 +688,14 @@ void ald_cmu_losc_safe_config(type_func_t status)
assert_param(IS_FUNC_STATE(status));
SYSCFG_UNLOCK();
if (status)
{
if (status) {
SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK);
SET_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK);
SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK);
ald_mcu_irq_config(CMU_IRQn, 3, ENABLE);
}
else
{
else {
CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK);
CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK);
@ -771,8 +717,7 @@ void ald_cmu_pll_safe_config(type_func_t status)
assert_param(IS_FUNC_STATE(status));
SYSCFG_UNLOCK();
if (status)
{
if (status) {
SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK);
MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS);
SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK);
@ -780,8 +725,7 @@ void ald_cmu_pll_safe_config(type_func_t status)
ald_mcu_irq_config(CMU_IRQn, 3, ENABLE);
}
else
{
else {
CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK);
CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK);
@ -793,6 +737,25 @@ void ald_cmu_pll_safe_config(type_func_t status)
return;
}
/**
* @brief Get current clock source.
* @param type: Type of source: HOSC/LOSC/PLL.
* @retval Status:
* - 0: Current clock is HOSC, LOSC or PLL
* - 1: Current clock is HRC, LRC or HRC
*/
uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type)
{
assert_param(IS_CMU_SAFE_CLOCK_TYPE(type));
if (type == CMU_SAFE_CLK_HOSC)
return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK, CMU_HOSMCR_CLKS_POS);
else if (type == CMU_SAFE_CLK_LOSC)
return READ_BITS(CMU->LOSMCR, CMU_LOSMCR_CLKS_MSK, CMU_LOSMCR_CLKS_POS);
else
return READ_BITS(CMU->PULMCR, CMU_PULMCR_CLKS_MSK, CMU_PULMCR_CLKS_POS);
}
/**
* @brief Get clock state.
* @param sr: The state type, see @ref cmu_clock_state_t.
@ -869,14 +832,12 @@ void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel,
SYSCFG_UNLOCK();
if (status)
{
if (status) {
MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS);
MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, div << CMU_CLKOCR_HSCODIV_POSS);
SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK);
}
else
{
else {
CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK);
}
@ -902,13 +863,11 @@ void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t statu
SYSCFG_UNLOCK();
if (status)
{
if (status) {
MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS);
SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK);
}
else
{
else {
CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK);
}
@ -952,14 +911,12 @@ void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status)
SYSCFG_UNLOCK();
if (status)
{
if (status) {
MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS);
MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS);
SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK);
}
else
{
else {
CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK);
}
@ -1060,16 +1017,13 @@ void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status)
SYSCFG_UNLOCK();
if (perh == CMU_PERH_ALL)
{
if (status)
{
if (perh == CMU_PERH_ALL) {
if (status) {
WRITE_REG(CMU->AHB1ENR, ~0);
WRITE_REG(CMU->APB1ENR, ~0);
WRITE_REG(CMU->APB2ENR, ~0);
}
else
{
else {
WRITE_REG(CMU->AHB1ENR, 0);
WRITE_REG(CMU->APB1ENR, 0);
WRITE_REG(CMU->APB2ENR, 0);
@ -1082,10 +1036,8 @@ void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status)
idx = (perh >> 27) & 0x3;
pos = perh & ~(0x3 << 27);
if (status)
{
switch (idx)
{
if (status) {
switch (idx) {
case 0:
SET_BIT(CMU->AHB1ENR, pos);
break;
@ -1102,10 +1054,8 @@ void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status)
break;
}
}
else
{
switch (idx)
{
else {
switch (idx) {
case 0:
CLEAR_BIT(CMU->AHB1ENR, pos);
break;

8
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crc.c
View File

@ -31,8 +31,8 @@
*/
void ald_crc_reset(crc_handle_t *hperh);
#ifdef ALD_DMA
static void crc_dma_calculate_cplt(void *arg);
static void crc_dma_error(void *arg);
static void crc_dma_calculate_cplt(void *arg);
static void crc_dma_error(void *arg);
#endif
/**
* @}
@ -123,7 +123,7 @@ uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size)
hperh->state = CRC_STATE_BUSY;
for (i = 0; i < size; i++)
*((volatile uint8_t *) & (hperh->perh->DATA)) = buf[i];
*((volatile uint8_t *)&(hperh->perh->DATA)) = buf[i];
ret = CRC->CHECKSUM;
hperh->state = CRC_STATE_READY;
@ -155,7 +155,7 @@ uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t
hperh->state = CRC_STATE_BUSY;
for (i = 0; i < size; i++)
*((volatile uint16_t *) & (hperh->perh->DATA)) = buf[i];
*((volatile uint16_t *)&(hperh->perh->DATA)) = buf[i];
ret = CRC->CHECKSUM;
hperh->state = CRC_STATE_READY;

143
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crypt.c
View File

@ -34,8 +34,8 @@
*/
void crypt_reset(crypt_handle_t *hperh);
#ifdef ALD_DMA
static void crypt_dma_crypt_cplt(void *arg);
static void crypt_dma_error(void *arg);
static void crypt_dma_crypt_cplt(void *arg);
static void crypt_dma_error(void *arg);
#endif
/**
* @}
@ -97,11 +97,10 @@ ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key)
uint32_t *temp = key;
uint32_t i;
if (hperh->state == CRYPT_STATE_BUSY)
return BUSY;
if ((hperh == NULL) || (key == NULL))
return ERROR;
if (hperh->state == CRYPT_STATE_BUSY)
return BUSY;
assert_param(IS_CRYPT(hperh->perh));
@ -127,11 +126,10 @@ ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t *key)
{
uint32_t *temp = key;
if (hperh->state == CRYPT_STATE_BUSY)
return BUSY;
if ((hperh == NULL) || (key == NULL))
return ERROR;
if (hperh->state == CRYPT_STATE_BUSY)
return BUSY;
assert_param(IS_CRYPT(hperh->perh));
@ -155,11 +153,10 @@ ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv)
uint32_t *temp = iv;
uint32_t i;
if (hperh->state == CRYPT_STATE_BUSY)
return BUSY;
if ((hperh == NULL) || (iv == NULL))
return ERROR;
if (hperh->state == CRYPT_STATE_BUSY)
return BUSY;
assert_param(IS_CRYPT(hperh->perh));
@ -186,11 +183,10 @@ ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv)
{
uint32_t *temp = iv;
if (hperh->state == CRYPT_STATE_BUSY)
return BUSY;
if ((hperh == NULL) || (iv == NULL))
return ERROR;
if (hperh->state == CRYPT_STATE_BUSY)
return BUSY;
assert_param(IS_CRYPT(hperh->perh));
@ -241,18 +237,15 @@ ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8
CRYPT_SETDIR(hperh, CRYPT_ENCRYPT);
count = size / (4 * hperh->step);
while (count--)
{
for (i = 0; i < hperh->step; i++)
{
while (count--) {
for (i = 0; i < hperh->step; i++) {
CRYPT_WRITE_FIFO(hperh, *plain_buf);
plain_buf++;
}
while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET);
for (i = 0; i < hperh->step; i++)
{
for (i = 0; i < hperh->step; i++) {
*cipher_buf = CRYPT_READ_FIFO(hperh);
cipher_buf++;
}
@ -278,11 +271,10 @@ ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint
{
uint32_t count = 0;
uint32_t i;
uint32_t *plain_buf = (uint32_t *)plain_text;
uint32_t *cipher_buf = (uint32_t *)cipher_text;
uint32_t *plain_buf = (uint32_t*)plain_text;
uint32_t *cipher_buf = (uint32_t*)cipher_text;
if (hperh->init.mode == CRYPT_MODE_CTR)
{
if (hperh->init.mode == CRYPT_MODE_CTR) {
return ald_crypt_encrypt(hperh, cipher_text, plain_text, size);
}
@ -299,18 +291,15 @@ ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint
CRYPT_SETDIR(hperh, CRYPT_DECRYPT);
count = size / (4 * hperh->step);
while (count--)
{
for (i = 0; i < hperh->step; i++)
{
while (count--) {
for (i = 0; i < hperh->step; i++) {
CRYPT_WRITE_FIFO(hperh, *cipher_buf);
cipher_buf++;
}
while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET);
for (i = 0; i < hperh->step; i++)
{
for (i = 0; i < hperh->step; i++) {
*plain_buf = CRYPT_READ_FIFO(hperh);
plain_buf++;
}
@ -370,84 +359,60 @@ ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, u
/* calculate u and v */
u = 128 * ((size % 16) ? (size / 16 + 1) : size / 16) - size * 8;
v = 128 * ((alen % 16) ? (alen / 16 + 1) : alen / 16) - alen * 8;
v = 128 * ((alen % 16) ? (alen / 16 + 1): alen / 16) - alen * 8;
/* get the input of GHASH algorithm,the input:A||0^v||C||0^u||[len(A)]_64||[len(C)]_64 */
for (i = 0; i < alen; i++)
{
for (i = 0; i < alen; i++) {
GCM_HASH_in [i] = * (aadata + i);
}
len += alen;
for (i = 0; i < v / 8; i++)
{
for (i = 0; i < v / 8; i++) {
GCM_HASH_in[i + len] = 0;
}
len += v / 8;
for (i = 0; i < size; i++)
{
for (i = 0; i < size; i++) {
GCM_HASH_in[i + len] = * (cipher_text + i);
}
len += size;
for (i = 0; i < u / 8; i++)
{
for (i = 0; i < u / 8; i++) {
GCM_HASH_in[i + len] = 0;
}
len += u / 8;
for (i = 0; i < 4; i++)
{
for (i = 0; i < 4; i++) {
GCM_HASH_in[i + len] = 0;
}
len += 4;
for (i = 0; i < 4; i++)
{
for (i = 0; i < 4; i++) {
GCM_HASH_in[i + len] = ((alen * 8) >> (8 * i)) & 0xFF;
}
len += 4;
for (i = 0; i < 4; i++)
{
for (i = 0; i < 4; i++) {
GCM_HASH_in[i + len] = 0;
}
len += 4;
for (i = 0; i < 4; i++)
{
for (i = 0; i < 4; i++) {
GCM_HASH_in[i + len] = ((size * 8) >> (8 * i)) & 0xFF;
}
len += 4;
CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS);
CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS);
CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS);
ald_crypt_encrypt(hperh, ecb, ecb, 16);
k = len / 16;
for (i = 0; i < 16; i++)
{
for (i = 0; i < 16; i++) {
tag[i] = 0;
}
cipher_text_temp = (uint32_t *)GCM_HASH_in;
tag_temp = (uint32_t *)tag;
for (i = 0; i < k; i++)
{
for (j = 0; j < 4; j++)
{
for (i = 0; i < k; i++) {
for (j = 0; j < 4; j++) {
x_temp[j] = (*cipher_text_temp) ^ tag_temp[j];
++cipher_text_temp;
}
@ -460,7 +425,7 @@ ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, u
*/
tag_temp = (uint32_t *)tag;
ald_crypt_init(hperh);
CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS);
CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS);
CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS);
ald_crypt_write_key(hperh, hperh->key);
hperh->iv[3] = 1;
@ -480,7 +445,7 @@ ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, u
* @retval Status, see @ref ald_status_t.
* @note the size is multiple of 16(ase)
*/
ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size)
ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t *cipher_text, uint32_t size)
{
uint32_t i;
uint32_t *plain_buf = (uint32_t *)plain_text;
@ -502,8 +467,7 @@ ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text,
hperh->size = size;
ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE);
for (i = 0; i < hperh->step; i++)
{
for (i = 0; i < hperh->step; i++) {
CRYPT_WRITE_FIFO(hperh, *plain_buf);
++plain_buf;
}
@ -525,10 +489,9 @@ ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text,
ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
{
uint32_t i;
uint32_t *cipher_buf = (uint32_t *)cipher_text;
uint32_t *cipher_buf = (uint32_t*)cipher_text;
if (hperh->init.mode == CRYPT_MODE_CTR)
{
if (hperh->init.mode == CRYPT_MODE_CTR) {
return ald_crypt_decrypt_by_it(hperh, cipher_text, plain_text, size);
}
@ -549,8 +512,7 @@ ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text
hperh->size = size;
ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE);
for (i = 0; i < hperh->step; i++)
{
for (i = 0; i < hperh->step; i++) {
CRYPT_WRITE_FIFO(hperh, *cipher_buf);
cipher_buf++;
}
@ -572,7 +534,7 @@ ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text
* @retval Status, see @ref ald_status_t.
* @note the size is multiple of 16(ase)
*/
ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text,
ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t * plain_text,
uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
{
if (hperh->state != CRYPT_STATE_READY)
@ -593,7 +555,6 @@ ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text
if (hperh->hdma_m2p.perh == NULL)
hperh->hdma_m2p.perh = DMA0;
if (hperh->hdma_p2m.perh == NULL)
hperh->hdma_p2m.perh = DMA0;
@ -651,7 +612,7 @@ ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text
* @retval Status, see @ref ald_status_t.
* @note the size is multiple of 16(ase)
*/
ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text,
ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t * cipher_text,
uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
{
if (hperh->init.mode == CRYPT_MODE_CTR)
@ -659,7 +620,6 @@ ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_tex
if (hperh->state != CRYPT_STATE_READY)
return ERROR;
if (plain_text == NULL || cipher_text == NULL || size == 0)
return ERROR;
@ -673,7 +633,6 @@ ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_tex
if (hperh->hdma_m2p.perh == NULL)
hperh->hdma_m2p.perh = DMA0;
if (hperh->hdma_p2m.perh == NULL)
hperh->hdma_p2m.perh = DMA0;
@ -789,19 +748,16 @@ void ald_crypt_irq_handler(crypt_handle_t *hperh)
uint32_t *in_buf;
uint32_t *out_buf;
if (READ_BIT(hperh->perh->CON, CRYPT_CON_ENCS_MSK))
{
if (READ_BIT(hperh->perh->CON, CRYPT_CON_ENCS_MSK)) {
in_buf = (uint32_t *)hperh->plain_text + hperh->count;
out_buf = (uint32_t *)hperh->cipher_text + hperh->count - hperh->step;
}
else
{
else {
in_buf = (uint32_t *)hperh->cipher_text + hperh->count;
out_buf = (uint32_t *)hperh->plain_text + hperh->count - hperh->step;
}
if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET)
{
if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) {
ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF);
}
@ -809,19 +765,15 @@ void ald_crypt_irq_handler(crypt_handle_t *hperh)
*out_buf++ = CRYPT_READ_FIFO(hperh);
hperh->count += hperh->step;
if (hperh->count > (hperh->size / 4))
{
if (hperh->count > (hperh->size / 4)) {
hperh->count = 0;
hperh->state = CRYPT_STATE_READY;
if (hperh->crypt_cplt_cbk)
hperh->crypt_cplt_cbk(hperh);
}
else
{
for (i = 0; i < hperh->step; i++)
{
else {
for (i = 0; i < hperh->step; i++) {
CRYPT_WRITE_FIFO(hperh, *in_buf++);
}
}
@ -851,8 +803,7 @@ void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_
{
assert_param(IS_CRYPT(hperh->perh));
if (it == CRYPT_IT_IT)
{
if (it == CRYPT_IT_IT) {
CLEAR_BIT(CRYPT->CON, CRYPT_CON_IE_MSK);
CRYPT->CON |= (state << CRYPT_CON_IE_POS);
}

337
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_dma.c
View File

@ -73,7 +73,7 @@
/** @defgroup DMA_Private_Variables DMA Private Variables
* @{
*/
dma_descriptor_t dma0_ctrl_base[28] __attribute__((aligned(512)));
dma_descriptor_t dma0_ctrl_base[28] __attribute__ ((aligned(512)));
dma_call_back_t dma0_cbk[6];
/**
* @}
@ -107,7 +107,7 @@ static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config
assert_param(IS_FUNC_STATE(p->primary));
assert_param(IS_FUNC_STATE(p->burst));
assert_param(IS_FUNC_STATE(p->high_prio));
assert_param(IS_FUNC_STATE(p->iterrupt));
assert_param(IS_FUNC_STATE(p->interrupt));
assert_param(IS_DMA_MSEL_TYPE(p->msel));
assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel));
assert_param(IS_DMA_CHANNEL(p->channel));
@ -120,12 +120,12 @@ static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config
if (p->src_inc == DMA_DATA_INC_NONE)
descr->src = p->src;
else
descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << p->data_width));
descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << (uint32_t)p->src_inc));
if (p->dst_inc == DMA_DATA_INC_NONE)
descr->dst = p->dst;
else
descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << p->data_width));
descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << (uint32_t)p->dst_inc));
descr->ctrl.cycle_ctrl = mode;
descr->ctrl.next_useburst = 0;
@ -153,7 +153,7 @@ static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config
else
WRITE_REG(DMAx->CHPRCLR, (1 << p->channel));
if (p->iterrupt)
if (p->interrupt)
SET_BIT(DMAx->IER, (1 << p->channel));
else
CLEAR_BIT(DMAx->IER, (1 << p->channel));
@ -171,10 +171,8 @@ void ald_dma_irq_handler(void)
{
uint32_t i, reg = DMA0->IFLAG;
for (i = 0; i < DMA_CH_COUNT; ++i)
{
if (READ_BIT(reg, (1 << i)))
{
for (i = 0; i < DMA_CH_COUNT; ++i) {
if (READ_BIT(reg, (1 << i))) {
if (dma0_cbk[i].cplt_cbk != NULL)
dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg);
@ -182,12 +180,10 @@ void ald_dma_irq_handler(void)
}
}
if (READ_BIT(reg, (1U << DMA_ERR)))
{
if (READ_BIT(reg, (1U << DMA_ERR))) {
ald_dma_clear_flag_status(DMA0, DMA_ERR);
for (i = 0; i < DMA_CH_COUNT; ++i)
{
for (i = 0; i < DMA_CH_COUNT; ++i) {
if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL))
dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg);
}
@ -230,6 +226,9 @@ void ald_dma_irq_handler(void)
(+) ald_dma_config_struct(): Configure dma_config_t
structure using default parameter.
(+) ald_dma_config_sg_alt_desc(): Configure dma_descriptor_t
structure using specified parameter. This function used
in scatter-gather mode(memory or peripheral).
@endverbatim
* @{
*/
@ -300,7 +299,44 @@ void ald_dma_config_struct(dma_config_t *p)
p->primary = ENABLE;
p->burst = DISABLE;
p->high_prio = DISABLE;
p->iterrupt = ENABLE;
p->interrupt = ENABLE;
return;
}
/**
* @brief Configure dma_descriptor_t structure using specified parameter.
* @note This function used in scatter-gather mode(memory or peripheral).
* @param desc: Address of the alternate descriptor.
* @param config: Pointer to the dma_config_t structure.
* @param memory: Memory or peripheral scatter-gather.
* @retval None
*/
void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory)
{
if ((desc == NULL) || (config == NULL))
return;
if (config->src_inc == DMA_DATA_INC_NONE)
desc->src = config->src;
else
desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width));
if (config->dst_inc == DMA_DATA_INC_NONE)
desc->dst = config->dst;
else
desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width));
desc->ctrl.cycle_ctrl = memory ? DMA_CYCLE_CTRL_MEM_SG_ALTERNATE : DMA_CYCLE_CTRL_PER_SG_ALTERNATE;
desc->ctrl.next_useburst = memory ? 0 : 1;
desc->ctrl.n_minus_1 = config->size - 1;
desc->ctrl.R_power = config->R_power;
desc->ctrl.src_prot_ctrl = 0;
desc->ctrl.dst_prot_ctrl = 0;
desc->ctrl.src_size = config->data_width;
desc->ctrl.src_inc = config->src_inc;
desc->ctrl.dst_size = config->data_width;
desc->ctrl.dst_inc = config->dst_inc;
return;
}
@ -328,6 +364,7 @@ void ald_dma_config_struct(dma_config_t *p)
(++) ald_dma_config_auto_easy(): Configure DMA channel according
to the specified parameter. If you want use the dma easily,
you can invoke this function.
(++) ald_dma_config_sg_mem(): Carry data used scatter-gather mode.
(+) Carry data from peripheral to memory or from memory to peripheral,
this mode APIs are:
(++) ald_dma_config_basic(): Configure DMA channel according to
@ -336,6 +373,8 @@ void ald_dma_config_struct(dma_config_t *p)
(++) ald_dma_config_basic_easy(): Configure DMA channel according
to the specified parameter. If you want use the dma easily,
you can invoke this function.
(++) ald_dma_ping_pong(): Carry data used ping-pong mode.
(++) ald_dma_config_sg_per(): Carry data used scatter-gather mode.
@endverbatim
* @{
@ -383,20 +422,18 @@ void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t si
else
descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel;
if (src)
{
if (src) {
if (hperh->config.src_inc == DMA_DATA_INC_NONE)
descr->src = src;
else
descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width));
descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width));
}
if (dst)
{
if (dst) {
if (hperh->config.dst_inc == DMA_DATA_INC_NONE)
descr->dst = dst;
else
descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width));
descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width));
}
ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
@ -407,8 +444,6 @@ void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t si
return;
}
/**
* @brief Configure DMA channel according to the specified parameter.
* The DMA mode is automatic. This mode is used to carry data
@ -420,7 +455,6 @@ void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t si
* @param size: The total number of DMA transfers that DMA cycle contains
* @param channel: Channel index which will be used.
* @param cbk: DMA complete callback function
*
* @retval None
*/
void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst,
@ -491,20 +525,18 @@ void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t s
else
descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel;
if (src)
{
if (src) {
if (hperh->config.src_inc == DMA_DATA_INC_NONE)
descr->src = src;
else
descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width));
descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width));
}
if (dst)
{
if (dst) {
if (hperh->config.dst_inc == DMA_DATA_INC_NONE)
descr->dst = dst;
else
descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width));
descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width));
}
ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
@ -528,9 +560,7 @@ void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t s
* @param msigsel: Input signal to DMA channel @ref dma_msigsel_t
* @param channel: Channel index which will be used
* @param cbk: DMA complete callback function
*
* @retval None
*
*/
void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel,
dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg))
@ -564,6 +594,214 @@ void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t
return;
}
/**
* @brief Configure DMA channel according to the specified parameter.
* The DMA mode is ping-pong.
* @note The ping-pong mode does not support memory to memory.
* @param DMAx: Pointer to DMA peripheral.
* @param config: Pointer to the dma_config_t structure which contains
* the specified parameters.
* @param first: Whether it is the first transmission. 1-first, 0-not first.
* @param cbk: DMA complete callback function.
* @retval None
*/
void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config,
uint8_t first, void (*cbk)(void *arg))
{
dma_descriptor_t *desc;
assert_param(IS_DMA(DMAx));
assert_param(config->src != NULL);
assert_param(config->dst != NULL);
assert_param(IS_DMA_DATA_SIZE(config->size));
assert_param(IS_DMA_DATASIZE_TYPE(config->data_width));
assert_param(IS_DMA_DATAINC_TYPE(config->src_inc));
assert_param(IS_DMA_DATAINC_TYPE(config->dst_inc));
assert_param(IS_DMA_ARBITERCONFIG_TYPE(config->R_power));
assert_param(IS_FUNC_STATE(config->primary));
assert_param(IS_FUNC_STATE(config->burst));
assert_param(IS_FUNC_STATE(config->high_prio));
assert_param(IS_FUNC_STATE(config->interrupt));
assert_param(IS_DMA_MSEL_TYPE(config->msel));
assert_param(IS_DMA_MSIGSEL_TYPE(config->msigsel));
assert_param(IS_DMA_CHANNEL(config->channel));
dma0_cbk[config->channel].cplt_cbk = cbk;
dma0_cbk[config->channel].err_cbk = NULL;
dma0_cbk[config->channel].cplt_arg = NULL;
dma0_cbk[config->channel].err_arg = NULL;
if (config->primary)
desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + config->channel;
else
desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + config->channel;
if (config->src_inc == DMA_DATA_INC_NONE)
desc->src = config->src;
else
desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width));
if (config->dst_inc == DMA_DATA_INC_NONE)
desc->dst = config->dst;
else
desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width));
desc->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PINGPONG;
desc->ctrl.next_useburst = 0;
desc->ctrl.n_minus_1 = config->size - 1;
desc->ctrl.R_power = config->R_power;
desc->ctrl.src_prot_ctrl = 0,
desc->ctrl.dst_prot_ctrl = 0,
desc->ctrl.src_size = config->data_width;
desc->ctrl.src_inc = config->src_inc;
desc->ctrl.dst_size = config->data_width;
desc->ctrl.dst_inc = config->dst_inc;
if (!first)
return;
if (config->primary)
WRITE_REG(DMAx->CHPRIALTCLR, (1 << config->channel));
else
WRITE_REG(DMAx->CHPRIALTSET, (1 << config->channel));
if (config->burst)
WRITE_REG(DMAx->CHUSEBURSTSET, (1 << config->channel));
else
WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << config->channel));
if (config->high_prio)
WRITE_REG(DMAx->CHPRSET, (1 << config->channel));
else
WRITE_REG(DMAx->CHPRCLR, (1 << config->channel));
if (config->interrupt)
SET_BIT(DMAx->IER, (1 << config->channel));
else
CLEAR_BIT(DMAx->IER, (1 << config->channel));
MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSEL_MSK, config->msel << DMA_CH0_SELCON_MSEL_POSS);
MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSIGSEL_MSK, config->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS);
WRITE_REG(DMAx->ICFR, (1 << config->channel));
WRITE_REG(DMAx->CHENSET, (1 << config->channel));
return;
}
/**
* @brief Configure DMA channel according to the specified parameter.
* The DMA mode is memory scatter-gather.
* @param DMAx: Pointer to DMA peripheral.
* @param desc: Pointer to first alternate descriptor.
* @param nr: Number of the alternate descriptor.
* @param channel: Channel index which will be used.
* @param cbk: DMA complete callback function.
* @retval None
*/
void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr,
uint8_t channel, void (*cbk)(void *arg))
{
dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
assert_param(IS_DMA(DMAx));
assert_param(IS_DMA_CHANNEL(channel));
if ((desc == NULL) || (nr == 0))
return;
dma0_cbk[channel].cplt_cbk = cbk;
dma0_cbk[channel].err_cbk = NULL;
dma0_cbk[channel].cplt_arg = NULL;
dma0_cbk[channel].err_arg = NULL;
tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD));
tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD));
tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_MEM_SG_PRIMARY;
tmp->ctrl.next_useburst = 0;
tmp->ctrl.n_minus_1 = (nr << 2) - 1;
tmp->ctrl.R_power = DMA_R_POWER_4;
tmp->ctrl.src_prot_ctrl = 0,
tmp->ctrl.dst_prot_ctrl = 0,
tmp->ctrl.src_size = DMA_DATA_SIZE_WORD;
tmp->ctrl.src_inc = DMA_DATA_INC_WORD;
tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD;
tmp->ctrl.dst_inc = DMA_DATA_INC_WORD;
desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO;
WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel));
WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << channel));
WRITE_REG(DMAx->CHPRCLR, (1 << channel));
WRITE_REG(DMAx->ICFR, (1 << channel));
SET_BIT(DMAx->IER, (1 << channel));
WRITE_REG(DMAx->CHENSET, (1 << channel));
SET_BIT(DMAx->CHSWREQ, (1 << channel));
return;
}
/**
* @brief Configure DMA channel according to the specified parameter.
* The DMA mode is peripheral scatter-gather.
* @note The size of the first transmission must be 5.
* @param DMAx: Pointer to DMA peripheral.
* @param desc: Pointer to first alternate descriptor.
* @param nr: Number of the alternate descriptor.
* @param burst: 1-Enable burst, 0-Disable burst.
* @param msel: Input source to DMA channel @ref dma_msel_t
* @param msigsel: Input signal to DMA channel @ref dma_msigsel_t
* @param channel: Channel index which will be used.
* @param cbk: DMA complete callback function.
* @retval None
*/
void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst,
dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg))
{
dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
assert_param(IS_DMA(DMAx));
assert_param(IS_DMA_MSEL_TYPE(msel));
assert_param(IS_DMA_MSIGSEL_TYPE(msigsel));
assert_param(IS_DMA_CHANNEL(channel));
if ((desc == NULL) || (nr == 0))
return;
dma0_cbk[channel].cplt_cbk = cbk;
dma0_cbk[channel].err_cbk = NULL;
dma0_cbk[channel].cplt_arg = NULL;
dma0_cbk[channel].err_arg = NULL;
tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD));
tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD));
tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PER_SG_PRIMARY;
tmp->ctrl.next_useburst = 0;
tmp->ctrl.n_minus_1 = (nr << 2) - 1;
tmp->ctrl.R_power = DMA_R_POWER_4;
tmp->ctrl.src_prot_ctrl = 0,
tmp->ctrl.dst_prot_ctrl = 0,
tmp->ctrl.src_size = DMA_DATA_SIZE_WORD;
tmp->ctrl.src_inc = DMA_DATA_INC_WORD;
tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD;
tmp->ctrl.dst_inc = DMA_DATA_INC_WORD;
desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC;
WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel));
burst ? (DMAx->CHUSEBURSTSET = (1 << channel)) : (DMAx->CHUSEBURSTCLR, (1 << channel));
WRITE_REG(DMAx->CHPRCLR, (1 << channel));
MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSEL_MSK, msel << DMA_CH0_SELCON_MSEL_POSS);
MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSIGSEL_MSK, msigsel << DMA_CH0_SELCON_MSIGSEL_POSS);
WRITE_REG(DMAx->ICFR, (1 << channel));
SET_BIT(DMAx->IER, (1 << channel));
WRITE_REG(DMAx->CHENSET, (1 << channel));
return;
}
/**
* @}
*/
@ -614,12 +852,10 @@ void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t stat
descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
alt_descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
if (state)
{
if (state) {
WRITE_REG(DMAx->CHENSET, (1 << channel));
}
else
{
else {
memset(descr, 0x00, sizeof(dma_descriptor_t));
memset(alt_descr, 0x00, sizeof(dma_descriptor_t));
WRITE_REG(DMAx->CH_SELCON[channel], 0x0);
@ -715,6 +951,37 @@ void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
WRITE_REG(DMAx->ICFR, (1 << channel));
return;
}
/**
* @brief Get the completion status of the descriptor
* @param DMAx: Pointer to DMA peripheral
* @param channel: Channel index
* @retval Completion status:
* - DMA_DESCP_CPLT_PRI: Primary descriptor has been completed
* - DMA_DESCP_CPLT_ALT: Alternate descriptor has been completed
* - DMA_DESCP_CPLT_ALL: Both primary and alternate descriptors have been completed
*/
dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel)
{
uint8_t pri, alt;
dma_descriptor_t *desc;
assert_param(IS_DMA(DMAx));
assert_param(IS_DMA_IT_TYPE(channel));
desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
pri = desc->ctrl.cycle_ctrl;
desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
alt = desc->ctrl.cycle_ctrl;
if ((pri == 0) && (alt == 0))
return DMA_DESCP_CPLT_ALL;
if (pri == 0)
return DMA_DESCP_CPLT_PRI;
else
return DMA_DESCP_CPLT_ALT;
}
/**
* @}
*/

38
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash.c
View File

@ -27,9 +27,9 @@
#ifdef ALD_FLASH
#if defined ( __ICCARM__ )
#define __RAMFUNC __ramfunc
#define __RAMFUNC __ramfunc
#else
#define __RAMFUNC
#define __RAMFUNC
#endif
/** @defgroup Flash_Private_Variables Flash Private Variables
@ -61,8 +61,7 @@ __RAMFUNC static ald_status_t flash_unlock(void)
FLASH_IAP_ENABLE();
FLASH_REQ();
for (i = 0; i < 0xFFFF; i++)
{
for (i = 0; i < 0xFFFF; i++) {
if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))
break;
}
@ -82,8 +81,7 @@ __RAMFUNC static ald_status_t flash_lock(void)
FLASH_REG_UNLOCK();
WRITE_REG(MSC->FLASHCR, 0x0);
for (i = 0; i < 0xFFFF; i++)
{
for (i = 0; i < 0xFFFF; i++) {
if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)))
break;
}
@ -104,30 +102,24 @@ __RAMFUNC ald_status_t flash_page_erase(uint32_t addr)
if (flash_unlock() != OK)
goto end;
if (op_cmd == OP_FLASH)
{
if (op_cmd == OP_FLASH) {
CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
}
else
{
else {
SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
}
WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE);
for (i = 0; i < 0xFFFF; i++)
{
for (i = 0; i < 0xFFFF; i++) {
if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
continue;
if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK))
goto end;
if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK))
goto end;
if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK))
break;
}
@ -154,7 +146,7 @@ end:
*/
__RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo)
{
uint16_t i;
uint16_t i = 0;
uint16_t prog_len;
uint32_t *p_data = data;
uint16_t op_cmd = OP_CMD;
@ -170,15 +162,12 @@ __RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_
MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS);
MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS);
for (prog_len = 0; prog_len < len; prog_len++)
{
if (fifo)
{
for (prog_len = 0; prog_len < len; prog_len++) {
if (fifo) {
WRITE_REG(MSC->FLASHFIFO, p_data[0]);
WRITE_REG(MSC->FLASHFIFO, p_data[1]);
}
else
{
else {
WRITE_REG(MSC->FLASHDL, p_data[0]);
WRITE_REG(MSC->FLASHDH, p_data[1]);
WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP);
@ -186,16 +175,13 @@ __RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_
p_data += 2;
for (i = 0; i < 0xFFFF; i++)
{
for (i = 0; i < 0xFFFF; i++) {
if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
continue;
if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK))
break;
}
}
if (i == 0xFFFF)
goto end;

58
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c
View File

@ -84,7 +84,7 @@ static uint8_t write_buf[FLASH_PAGE_SIZE];
*/
static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr)
{
uint8_t *addr_to_read;
uint8_t* addr_to_read;
uint8_t value;
uint32_t index;
@ -99,8 +99,7 @@ static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr)
if (begin_addr > end_addr)
return FALSE;
while (index++ <= end_addr)
{
while (index++ <= end_addr) {
value = *addr_to_read++;
if (value != 0xFF)
@ -146,8 +145,7 @@ ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0))
return ERROR;
for (i = 0; i < len; i++)
{
for (i = 0; i < len; i++) {
ram_addr[i] = ((uint32_t *)addr)[i];
}
@ -181,9 +179,7 @@ ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
len_to_write = len;
__disable_irq();
while (len_to_write > 0)
{
while (len_to_write > 0) {
need_erase_page = FALSE;
for (index = 0; index < FLASH_PAGE_SIZE; index++)
@ -196,17 +192,14 @@ ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
need_erase_page = page_have_writen(FLASH_WORD_ADDR(start_write_addr),
FLASH_WORDEND_ADDR(end_write_addr));
if (need_erase_page)
{
if (need_erase_page) {
if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr),
FLASH_PAGE_SIZE >> 2))
{
FLASH_PAGE_SIZE >> 2)) {
__enable_irq();
return ERROR;
}
if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr)))
{
if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) {
__enable_irq();
return ERROR;
}
@ -220,11 +213,9 @@ ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
index2 = 0;
index = FLASH_PAGE_ADDR(start_write_addr);
para = FLASH_PAGE_ADDR(start_write_addr) + FLASH_PAGE_SIZE;
len_index = FLASH_PAGE_SIZE;
}
else
{
else {
para = end_write_addr & (FLASH_PAGE_SIZE - 1);
index = start_write_addr & (FLASH_PAGE_SIZE - 1);
index2 = len - len_to_write;
@ -239,8 +230,7 @@ ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
len_index = end_word_addr - start_word_addr + 1;
}
if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO))
{
if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) {
__enable_irq();
return ERROR;
}
@ -260,7 +250,7 @@ ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
*/
ald_status_t ald_flash_erase(uint32_t addr, uint16_t len)
{
int32_t index;
uint32_t index;
int32_t para;
int32_t start_erase_addr;
int32_t end_erase_addr;
@ -274,9 +264,7 @@ ald_status_t ald_flash_erase(uint32_t addr, uint16_t len)
len_not_erase = len;
__disable_irq();
while (len_not_erase > 0)
{
while (len_not_erase > 0) {
page_need_save = FALSE;
start_erase_addr = addr + len - len_not_erase;
@ -284,36 +272,29 @@ ald_status_t ald_flash_erase(uint32_t addr, uint16_t len)
end_erase_addr = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr))
? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr);
if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr))
{
if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) {
if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1)))
page_need_save = TRUE;
}
if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr))
{
if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) {
if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr)))
page_need_save = TRUE;
}
if (page_need_save)
{
if (page_need_save) {
if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr),
FLASH_PAGE_SIZE >> 2))
{
FLASH_PAGE_SIZE >> 2)) {
__enable_irq();
return ERROR;
}
}
if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr)))
{
if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) {
__enable_irq();
return ERROR;
}
if (page_need_save)
{
if (page_need_save) {
para = end_erase_addr & (FLASH_PAGE_SIZE - 1);
index = start_erase_addr & (FLASH_PAGE_SIZE - 1);
@ -322,14 +303,11 @@ ald_status_t ald_flash_erase(uint32_t addr, uint16_t len)
index = FLASH_PAGE_ADDR(start_erase_addr);
len_index = FLASH_PAGE_SIZE;
if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO))
{
if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) {
__enable_irq();
return ERROR;
}
}
len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1);
}

68
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_gpio.c
View File

@ -180,8 +180,7 @@ void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init)
assert_param(IS_GPIO_TYPE(init->type));
assert_param(IS_GPIO_FUNC(init->func));
for (i = 0; i < 16; ++i)
{
for (i = 0; i < 16; ++i) {
if (((pin >> i) & 0x1) == 0)
continue;
@ -317,34 +316,29 @@ void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init)
port = 0;
/* Get Pin index */
for (i = 0; i < 16; ++i)
{
for (i = 0; i < 16; ++i) {
if (((pin >> i) & 0x1) == 0x1)
break;
}
/* Select external interrupt line */
if (i <= 7)
{
EXTI->EXTIPSR0 &= ~(0x7 << (i * 4));
if (i <= 7) {
EXTI->EXTIPSR0 &= ~(0x7U << (i * 4));
EXTI->EXTIPSR0 |= (port << (i * 4));
}
else
{
else {
i -= 8;
EXTI->EXTIPSR1 &= ~(0x7 << (i * 4));
EXTI->EXTIPSR1 &= ~(0x7U << (i * 4));
EXTI->EXTIPSR1 |= (port << (i * 4));
}
/* Configure filter parameter */
if (init->filter == ENABLE)
{
if (init->filter == ENABLE) {
SET_BIT(EXTI->EXTIFLTCR, pin);
MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS);
MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS);
}
else
{
else {
CLEAR_BIT(EXTI->EXTIFLTCR, pin);
}
@ -373,8 +367,6 @@ void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init)
* @param GPIOx: Where x can be (A--H) to select the GPIO peripheral.
* @param pin: Specifies the pin to read.
* @retval The input pin value
* - BIT_SET
* - BIT_RESET
*/
uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
{
@ -382,10 +374,9 @@ uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
assert_param(IS_GPIO_PIN(pin));
if (READ_BIT(GPIOx->DIN, pin))
return BIT_SET;
return 1;
else
return BIT_RESET;
return 0;
}
/**
@ -436,8 +427,7 @@ void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin)
assert_param(IS_GPIO_PORT(GPIOx));
assert_param(IS_GPIO_PIN(pin));
for (i = 0; i < 16; ++i)
{
for (i = 0; i < 16; ++i) {
if (((pin >> i) & 0x1) == 0)
continue;
@ -451,12 +441,10 @@ void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin)
if ((value == 2) || (value == 3))
value = 1;
else if (value == 1)
{
else if (value == 1) {
value = 2;
}
else
{
else {
continue; /* do nothing */
}
@ -549,46 +537,36 @@ void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, ty
assert_param(IS_TRIGGER_STYLE(style));
assert_param(IS_FUNC_STATE(status));
if (status == ENABLE)
{
if (style == EXTI_TRIGGER_RISING_EDGE)
{
if (status == ENABLE) {
if (style == EXTI_TRIGGER_RISING_EDGE) {
SET_BIT(EXTI->EXTIRER, pin);
}
else if (style == EXTI_TRIGGER_TRAILING_EDGE)
{
else if (style == EXTI_TRIGGER_TRAILING_EDGE) {
SET_BIT(EXTI->EXTIFER, pin);
}
else if (style == EXTI_TRIGGER_BOTH_EDGE)
{
else if (style == EXTI_TRIGGER_BOTH_EDGE) {
SET_BIT(EXTI->EXTIRER, pin);
SET_BIT(EXTI->EXTIFER, pin);
}
else
{
else {
; /* do nothing */
}
WRITE_REG(EXTI->EXTICFR, 0xffff);
SET_BIT(EXTI->EXTIEN, pin);
}
else
{
if (style == EXTI_TRIGGER_RISING_EDGE)
{
else {
if (style == EXTI_TRIGGER_RISING_EDGE) {
CLEAR_BIT(EXTI->EXTIRER, pin);
}
else if (style == EXTI_TRIGGER_TRAILING_EDGE)
{
else if (style == EXTI_TRIGGER_TRAILING_EDGE) {
CLEAR_BIT(EXTI->EXTIFER, pin);
}
else if (style == EXTI_TRIGGER_BOTH_EDGE)
{
else if (style == EXTI_TRIGGER_BOTH_EDGE) {
CLEAR_BIT(EXTI->EXTIRER, pin);
CLEAR_BIT(EXTI->EXTIFER, pin);
}
else
{
else {
; /* do nothing */
}

846
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_i2c.c
View File

File diff suppressed because it is too large Load Diff

14
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lcd.c
View File

@ -1,4 +1,4 @@
/**
/**
*********************************************************************************
*
* @file ald_lcd.c
@ -70,9 +70,7 @@ ald_status_t ald_lcd_init(lcd_handle_t *hperh)
MODIFY_REG(hperh->perh->FCR, LCD_FCR_WFS_MSK, hperh->init.lcd_wfs << LCD_FCR_WFS_POS);
MODIFY_REG(hperh->perh->FCR, LCD_FCR_PRS_MSK, hperh->init.lcd_prs << LCD_FCR_PRS_POSS);
for (delay = 0; delay < 3000; delay++);
MODIFY_REG(hperh->perh->FCR, LCD_FCR_DIV_MSK, hperh->init.lcd_div << LCD_FCR_DIV_POSS);
MODIFY_REG(hperh->perh->FCR, LCD_FCR_DEAD_MSK, hperh->init.lcd_dead << LCD_FCR_DEAD_POSS);
MODIFY_REG(hperh->perh->FCR, LCD_FCR_PON_MSK, hperh->init.lcd_pon << LCD_FCR_PON_POSS);
@ -139,14 +137,12 @@ ald_status_t ald_lcd_blink_config(lcd_handle_t *hperh, lcd_blink_t blink_mode, l
__LOCK(hperh);
MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLMOD_MSK, blink_mode << LCD_FCR_BLMOD_POSS);
for (delay = 0; delay < 3000; delay++);
MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLFRQ_MSK, blink_freq << LCD_FCR_BLFRQ_POSS);
__UNLOCK(hperh);
return OK;
}
}
/**
* @brief Control segment port enable or disable
@ -318,16 +314,14 @@ ald_status_t ald_lcd_clear_flag_status(lcd_handle_t *hperh, lcd_flag_t flag)
*/
void ald_lcd_irq_handler(lcd_handle_t *hperh)
{
if (ald_lcd_get_flag_status(hperh, LCD_FLAG_UDD))
{
if (ald_lcd_get_flag_status(hperh, LCD_FLAG_UDD)) {
ald_lcd_clear_flag_status(hperh, LCD_FLAG_UDD);
if (hperh->display_cplt_cbk)
hperh->display_cplt_cbk(hperh);
}
if (ald_lcd_get_flag_status(hperh, LCD_FLAG_SOF))
{
if (ald_lcd_get_flag_status(hperh, LCD_FLAG_SOF)) {
ald_lcd_clear_flag_status(hperh, LCD_FLAG_SOF);
if (hperh->frame_start_cbk)

177
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lptim.c
View File

@ -119,7 +119,7 @@ void ald_lptim_trigger_filter_config(lptim_handle_t *hperh, lptim_trgflt_t flt)
void ald_lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt)
{
assert_param(IS_LPTIM(hperh->perh));
assert_param(IS_LPTIM_TRGFLT(flt));
assert_param(IS_LPTIM_CKFLT(flt));
MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKFLT_MSK, flt << LP16T_CON0_CKFLT_POSS);
@ -129,8 +129,134 @@ void ald_lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt)
* @}
*/
/** @defgroup LPTIM_Public_Functions_Group2 LPTIM output toggle functions
* @brief LPTime output toggle functions
/** @defgroup LPTIM_Public_Functions_Group2 LPTIM base functions
* @brief LPTIM base functions
*
* @verbatim
==============================================================================
##### Low Pow Time Base functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize the LPTIM .
(+) Start the LPTIM.
(+) Stop the LPTIM.
(+) Start the LPTIM and enable interrupt.
(+) Stop the LPTIM and disable interrupt.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM according to the specified
* parameters in the tim_handle_t.
* @param hperh: LPTIM handle
* @retval Status, see @ref ald_status_t.
*/
ald_status_t ald_lptim_base_init(lptim_handle_t *hperh)
{
assert_param(IS_LPTIM(hperh->perh));
assert_param(IS_LPTIM_PRESC(hperh->init.psc));
__LOCK(hperh);
hperh->state = LPTIM_STATE_BUSY;
ald_cmu_lptim0_clock_select(hperh->init.clock);
WRITE_REG(hperh->perh->UPDATE, 1);
MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_NONE << LP16T_CON0_WAVE_POSS);
MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS);
WRITE_REG(hperh->perh->ARR, hperh->init.arr);
WRITE_REG(hperh->perh->CMP, hperh->init.cmp);
WRITE_REG(hperh->perh->UPDATE, 0);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK));
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK));
hperh->state = LPTIM_STATE_READY;
__UNLOCK(hperh);
return OK;
}
/**
* @brief Starts the LPTIM.
* @param hperh: LPTIM handle
* @retval None
*/
void ald_lptim_base_start(lptim_handle_t *hperh)
{
assert_param(IS_LPTIM(hperh->perh));
assert_param(IS_LPTIM_MODE(hperh->init.mode));
LPTIM_ENABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
LPTIM_CNTSTART(hperh);
else
LPTIM_SNGSTART(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
}
/**
* @brief Stops the LPTIM.
* @param hperh: LPTIM handle
* @retval None
*/
void ald_lptim_base_stop(lptim_handle_t *hperh)
{
assert_param(IS_LPTIM(hperh->perh));
LPTIM_DISABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
}
/**
* @brief Starts the LPTIM in interrupt mode.
* @param hperh: LPTIM handle
* @retval None
*/
void ald_lptim_base_start_by_it(lptim_handle_t *hperh)
{
assert_param(IS_LPTIM(hperh->perh));
assert_param(IS_LPTIM_MODE(hperh->init.mode));
ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE);
LPTIM_ENABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
LPTIM_CNTSTART(hperh);
else
LPTIM_SNGSTART(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
}
/**
* @brief Stops the LPTIM Output toggle in interrupt mode.
* @param hperh: LPTIM handle
* @retval None
*/
void ald_lptim_base_stop_by_it(lptim_handle_t *hperh)
{
assert_param(IS_LPTIM(hperh->perh));
ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE);
LPTIM_DISABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
}
/**
* @}
*/
/** @defgroup LPTIM_Public_Functions_Group3 LPTIM output toggle functions
* @brief LPTIM output toggle functions
*
* @verbatim
==============================================================================
@ -171,7 +297,6 @@ ald_status_t ald_lptim_toggle_init(lptim_handle_t *hperh)
WRITE_REG(hperh->perh->UPDATE, 0);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK));
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK));
hperh->state = LPTIM_STATE_READY;
@ -190,7 +315,6 @@ void ald_lptim_toggle_start(lptim_handle_t *hperh)
assert_param(IS_LPTIM_MODE(hperh->init.mode));
LPTIM_ENABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
@ -199,7 +323,6 @@ void ald_lptim_toggle_start(lptim_handle_t *hperh)
LPTIM_SNGSTART(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
}
@ -213,9 +336,7 @@ void ald_lptim_toggle_stop(lptim_handle_t *hperh)
assert_param(IS_LPTIM(hperh->perh));
LPTIM_DISABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
}
@ -231,7 +352,6 @@ void ald_lptim_toggle_start_by_it(lptim_handle_t *hperh)
ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE);
LPTIM_ENABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
@ -240,7 +360,6 @@ void ald_lptim_toggle_start_by_it(lptim_handle_t *hperh)
LPTIM_SNGSTART(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
}
@ -255,17 +374,15 @@ void ald_lptim_toggle_stop_by_it(lptim_handle_t *hperh)
ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE);
LPTIM_DISABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
}
/**
* @}
*/
/** @defgroup LPTIM_Public_Functions_Group3 LPTIM output pulse functions
* @brief LPTime output pulse functions
/** @defgroup LPTIM_Public_Functions_Group4 LPTIM output pulse functions
* @brief LPTIM output pulse functions
*
* @verbatim
==============================================================================
@ -305,7 +422,6 @@ ald_status_t ald_lptim_pulse_init(lptim_handle_t *hperh)
WRITE_REG(hperh->perh->UPDATE, 0);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK));
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK));
hperh->state = LPTIM_STATE_READY;
@ -324,7 +440,6 @@ void ald_lptim_pulse_start(lptim_handle_t *hperh)
assert_param(IS_LPTIM_MODE(hperh->init.mode));
LPTIM_ENABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
@ -333,7 +448,6 @@ void ald_lptim_pulse_start(lptim_handle_t *hperh)
LPTIM_SNGSTART(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
}
@ -347,7 +461,6 @@ void ald_lptim_pulse_stop(lptim_handle_t *hperh)
assert_param(IS_LPTIM(hperh->perh));
LPTIM_DISABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
@ -365,7 +478,6 @@ void ald_lptim_pulse_start_by_it(lptim_handle_t *hperh)
ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE);
LPTIM_ENABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
@ -374,7 +486,6 @@ void ald_lptim_pulse_start_by_it(lptim_handle_t *hperh)
LPTIM_SNGSTART(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
}
@ -389,7 +500,6 @@ void ald_lptim_pulse_stop_by_it(lptim_handle_t *hperh)
ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE);
LPTIM_DISABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
@ -398,8 +508,8 @@ void ald_lptim_pulse_stop_by_it(lptim_handle_t *hperh)
* @}
*/
/** @defgroup LPTIM_Public_Functions_Group4 LPTIM output pwm functions
* @brief LPTime output pwm functions
/** @defgroup LPTIM_Public_Functions_Group5 LPTIM output pwm functions
* @brief LPTIM output pwm functions
*
* @verbatim
==============================================================================
@ -438,7 +548,6 @@ ald_status_t ald_lptim_pwm_init(lptim_handle_t *hperh)
WRITE_REG(hperh->perh->UPDATE, 0);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK));
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK));
hperh->state = LPTIM_STATE_READY;
@ -457,7 +566,6 @@ void ald_lptim_pwm_start(lptim_handle_t *hperh)
assert_param(IS_LPTIM_MODE(hperh->init.mode));
LPTIM_ENABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
@ -466,7 +574,6 @@ void ald_lptim_pwm_start(lptim_handle_t *hperh)
LPTIM_SNGSTART(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
}
@ -480,7 +587,6 @@ void ald_lptim_pwm_stop(lptim_handle_t *hperh)
assert_param(IS_LPTIM(hperh->perh));
LPTIM_DISABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
@ -498,7 +604,6 @@ void ald_lptim_pwm_start_by_it(lptim_handle_t *hperh)
ald_lptim_interrupt_config(hperh, LPTIM_IT_CMPMAT, ENABLE);
LPTIM_ENABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
@ -507,7 +612,6 @@ void ald_lptim_pwm_start_by_it(lptim_handle_t *hperh)
LPTIM_SNGSTART(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
}
@ -522,7 +626,6 @@ void ald_lptim_pwm_stop_by_it(lptim_handle_t *hperh)
ald_lptim_interrupt_config(hperh, LPTIM_IT_CMPMAT, DISABLE);
LPTIM_DISABLE(hperh);
while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
return;
@ -532,7 +635,7 @@ void ald_lptim_pwm_stop_by_it(lptim_handle_t *hperh)
*/
/** @defgroup LPTIM_Public_Functions_Group5 Control functions
/** @defgroup LPTIM_Public_Functions_Group6 Control functions
* @brief LPTIM Control functions
*
* @{
@ -548,8 +651,7 @@ void ald_lptim_irq_handler(lptim_handle_t *hperh)
/* Output compare event */
if (((ald_lptim_get_it_status(hperh, LPTIM_IT_CMPMAT)) != RESET) &&
((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_CMPMAT)) != RESET))
{
((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_CMPMAT)) != RESET)) {
ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_CMPMAT);
if (hperh->cmp_cbk)
@ -558,8 +660,7 @@ void ald_lptim_irq_handler(lptim_handle_t *hperh)
/* Output update event */
if (((ald_lptim_get_it_status(hperh, LPTIM_IT_ARRMAT)) != RESET) &&
((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_ARRMAT)) != RESET))
{
((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_ARRMAT)) != RESET)) {
ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_ARRMAT);
if (hperh->update_cbk)
@ -568,8 +669,7 @@ void ald_lptim_irq_handler(lptim_handle_t *hperh)
/* Trigger event */
if (((ald_lptim_get_it_status(hperh, LPTIM_IT_EXTTRIG)) != RESET) &&
((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_EXTTRIG)) != RESET))
{
((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_EXTTRIG)) != RESET)) {
ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_EXTTRIG);
if (hperh->trig_cbk)
@ -600,7 +700,6 @@ void ald_lptim_interrupt_config(lptim_handle_t *hperh, lptim_it_t it, type_func_
SET_BIT(hperh->perh->IER, (uint32_t)it);
else
CLEAR_BIT(hperh->perh->IER, (uint32_t)it);
return;
}
@ -664,7 +763,7 @@ void ald_lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag)
* @}
*/
/** @defgroup LPTIM_Public_Functions_Group6 Peripheral State functions
/** @defgroup LPTIM_Public_Functions_Group7 Peripheral State functions
* @brief Peripheral State functions
*
* @verbatim

106
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lpuart.c
View File

@ -182,8 +182,7 @@ static ald_status_t lpuart_wait_flag(lpuart_handle_t *hperh, lpuart_status_t fla
tick = ald_get_tick();
/* Waiting for flag */
while ((ald_lpuart_get_status(hperh, flag)) != status)
{
while ((ald_lpuart_get_status(hperh, flag)) != status) {
if (((ald_get_tick()) - tick) > timeout)
return TIMEOUT;
}
@ -204,8 +203,7 @@ static ald_status_t __lpuart_send_by_it(lpuart_handle_t *hperh)
WRITE_REG(hperh->perh->TXDR, *hperh->tx_buf++);
if (--hperh->tx_count == 0)
{
if (--hperh->tx_count == 0) {
ald_lpuart_interrupt_config(hperh, LPUART_IT_TBEMP, DISABLE);
ald_lpuart_interrupt_config(hperh, LPUART_IT_TC, ENABLE);
}
@ -239,30 +237,26 @@ static ald_status_t __lpuart_end_send_by_it(lpuart_handle_t *hperh)
*/
static ald_status_t __lpuart_recv_by_it(lpuart_handle_t *hperh)
{
uint8_t tmp;
uint32_t tmp;
uint16_t i;
if ((hperh->state & LPUART_STATE_RX_MASK) == 0x0)
return BUSY;
do
{
do {
i = 10000;
tmp = hperh->perh->STAT & LPUART_STAT_RXPTR_MSK;
*hperh->rx_buf++ = (uint8_t)(hperh->perh->RXDR & 0xFF);
--hperh->rx_count;
while (((hperh->perh->STAT & LPUART_STAT_RXPTR_MSK) != tmp - 1) && (i--));
}
while (hperh->perh->STAT & LPUART_STAT_RXPTR_MSK);
while (((hperh->perh->STAT & LPUART_STAT_RXPTR_MSK) != (uint32_t)(tmp - 1)) && (i--));
} while (hperh->perh->STAT & LPUART_STAT_RXPTR_MSK);
if (hperh->rx_count == 0)
{
if (hperh->rx_count == 0) {
ald_lpuart_interrupt_config(hperh, LPUART_IT_RBR, DISABLE);
CLEAR_BIT(hperh->state, LPUART_STATE_RX_MASK);
if (hperh->state == LPUART_STATE_READY)
{
if (hperh->state == LPUART_STATE_READY) {
ald_lpuart_interrupt_config(hperh, LPUART_IT_PERR, DISABLE);
ald_lpuart_interrupt_config(hperh, LPUART_IT_FERR, DISABLE);
}
@ -493,10 +487,8 @@ ald_status_t ald_lpuart_send(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size
hperh->tx_size = size;
hperh->tx_count = size;
while (hperh->tx_count-- > 0)
{
if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, SET, timeout) != OK)
{
while (hperh->tx_count-- > 0) {
if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = LPUART_STATE_READY;
return TIMEOUT;
@ -504,16 +496,14 @@ ald_status_t ald_lpuart_send(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size
WRITE_REG(hperh->perh->TXDR, *buf++);
if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, RESET, timeout) != OK)
{
if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, RESET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = LPUART_STATE_READY;
return TIMEOUT;
}
}
if (lpuart_wait_flag(hperh, LPUART_STAT_TXIDLE, SET, timeout) != OK)
{
if (lpuart_wait_flag(hperh, LPUART_STAT_TXIDLE, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = LPUART_STATE_READY;
return TIMEOUT;
@ -539,7 +529,7 @@ ald_status_t ald_lpuart_recv(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size
if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
@ -551,10 +541,8 @@ ald_status_t ald_lpuart_recv(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size
hperh->rx_count = size;
/* Check the remain data to be received */
while (hperh->rx_count-- > 0)
{
if (lpuart_wait_flag(hperh, LPUART_STAT_RXEMP, RESET, timeout) != OK)
{
while (hperh->rx_count-- > 0) {
if (lpuart_wait_flag(hperh, LPUART_STAT_RXEMP, RESET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = LPUART_STATE_READY;
return TIMEOUT;
@ -582,7 +570,7 @@ ald_status_t ald_lpuart_send_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_
if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
@ -612,7 +600,7 @@ ald_status_t ald_lpuart_recv_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_
if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
@ -647,7 +635,7 @@ ald_status_t ald_lpuart_send_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16
if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
@ -677,8 +665,7 @@ ald_status_t ald_lpuart_send_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16
hperh->hdmatx.config.msigsel = DMA_MSIGSEL_LPUART_TXEMPTY;
hperh->hdmatx.config.channel = channel;
if (hperh->init.mode == LPUART_MODE_RS485)
{
if (hperh->init.mode == LPUART_MODE_RS485) {
hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD;
hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
}
@ -705,7 +692,7 @@ ald_status_t ald_lpuart_recv_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16
if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
@ -734,8 +721,7 @@ ald_status_t ald_lpuart_recv_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16
hperh->hdmarx.config.msigsel = DMA_MSIGSEL_LPUART_RNR;
hperh->hdmarx.config.channel = channel;
if (hperh->init.mode == LPUART_MODE_RS485)
{
if (hperh->init.mode == LPUART_MODE_RS485) {
hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD;
hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD;
}
@ -757,21 +743,17 @@ ald_status_t ald_lpuart_dma_pause(lpuart_handle_t *hperh)
{
__LOCK(hperh);
if (hperh->state == LPUART_STATE_BUSY_TX)
{
if (hperh->state == LPUART_STATE_BUSY_TX) {
ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE);
}
else if (hperh->state == LPUART_STATE_BUSY_RX)
{
else if (hperh->state == LPUART_STATE_BUSY_RX) {
ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE);
}
else if (hperh->state == LPUART_STATE_BUSY_TX_RX)
{
else if (hperh->state == LPUART_STATE_BUSY_TX_RX) {
ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE);
ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE);
}
else
{
else {
__UNLOCK(hperh);
return ERROR;
}
@ -790,23 +772,19 @@ ald_status_t ald_lpuart_dma_resume(lpuart_handle_t *hperh)
{
__LOCK(hperh);
if (hperh->state == LPUART_STATE_BUSY_TX)
{
if (hperh->state == LPUART_STATE_BUSY_TX) {
ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, ENABLE);
}
else if (hperh->state == LPUART_STATE_BUSY_RX)
{
else if (hperh->state == LPUART_STATE_BUSY_RX) {
ald_lpuart_clear_flag_status(hperh, LPUART_IF_RXOV);
ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, ENABLE);
}
else if (hperh->state == LPUART_STATE_BUSY_TX_RX)
{
else if (hperh->state == LPUART_STATE_BUSY_TX_RX) {
ald_lpuart_clear_flag_status(hperh, LPUART_IF_RXOV);
ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, ENABLE);
ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, ENABLE);
}
else
{
else {
__UNLOCK(hperh);
return ERROR;
}
@ -845,62 +823,53 @@ void ald_lpuart_irq_handler(lpuart_handle_t *hperh)
/* Handle CTS wakeup */
flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_CTSWK);
source = ald_lpuart_get_it_status(hperh, LPUART_IT_CTSWK);
if ((flag != RESET) && (source != RESET))
ald_lpuart_clear_flag_status(hperh, LPUART_IF_CTSWK);
/* Handle DATA wakeup */
flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_DATWK);
source = ald_lpuart_get_it_status(hperh, LPUART_IT_DATWK);
if ((flag != RESET) && (source != RESET))
ald_lpuart_clear_flag_status(hperh, LPUART_IF_DATWK);
/* Handle parity error */
flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_PERR);
source = ald_lpuart_get_it_status(hperh, LPUART_IT_PERR);
if ((flag != RESET) && (source != RESET))
hperh->err_code |= LPUART_ERROR_PE;
/* Handle frame error */
flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_FERR);
source = ald_lpuart_get_it_status(hperh, LPUART_IT_FERR);
if ((flag != RESET) && (source != RESET))
hperh->err_code |= LPUART_ERROR_FE;
/* Handle overflow error */
flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_RXOV);
source = ald_lpuart_get_it_status(hperh, LPUART_IT_RXOV);
if ((flag != RESET) && (source != RESET))
hperh->err_code |= LPUART_ERROR_ORE;
/* Receive */
flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_RBR);
source = ald_lpuart_get_it_status(hperh, LPUART_IT_RBR);
if ((flag != RESET) && (source != RESET))
__lpuart_recv_by_it(hperh);
/* Transmite */
flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_TBEMP);
source = ald_lpuart_get_it_status(hperh, LPUART_IT_TBEMP);
if ((flag != RESET) && (source != RESET))
__lpuart_send_by_it(hperh);
/* End Transmite */
flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_TC);
source = ald_lpuart_get_it_status(hperh, LPUART_IT_TC);
if ((flag != RESET) && (source != RESET))
__lpuart_end_send_by_it(hperh);
/* Handle error state */
if (hperh->err_code != LPUART_ERROR_NONE)
{
if (hperh->err_code != LPUART_ERROR_NONE) {
ald_lpuart_clear_flag_status(hperh, LPUART_IF_PERR);
ald_lpuart_clear_flag_status(hperh, LPUART_IF_FERR);
ald_lpuart_clear_flag_status(hperh, LPUART_IF_RXOV);
@ -996,15 +965,13 @@ void ald_lpuart_dma_req_config(lpuart_handle_t *hperh, lpuart_dma_req_t req, typ
assert_param(IS_LPUART_DMAREQ(req));
assert_param(IS_FUNC_STATE(status));
if (req == LPUART_DMA_REQ_TX)
{
if (req == LPUART_DMA_REQ_TX) {
if (status == ENABLE)
SET_BIT(hperh->perh->CON0, LPUART_CON0_TXDMAE_MSK);
else
CLEAR_BIT(hperh->perh->CON0, LPUART_CON0_TXDMAE_MSK);
}
else
{
else {
if (status == ENABLE)
SET_BIT(hperh->perh->CON0, LPUART_CON0_RXDMAE_MSK);
else
@ -1063,22 +1030,19 @@ ald_status_t ald_lpuart_rs485_send_addr(lpuart_handle_t *hperh, uint16_t addr, u
SET_BIT(hperh->state, LPUART_STATE_TX_MASK);
if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, SET, timeout) != OK)
{
if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, SET, timeout) != OK) {
hperh->state = LPUART_STATE_READY;
return TIMEOUT;
}
WRITE_REG(hperh->perh->TXDR, addr | 0x100);
if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, RESET, timeout) != OK)
{
if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, RESET, timeout) != OK) {
hperh->state = LPUART_STATE_READY;
return TIMEOUT;
}
if (lpuart_wait_flag(hperh, LPUART_STAT_TXIDLE, SET, timeout) != OK)
{
if (lpuart_wait_flag(hperh, LPUART_STAT_TXIDLE, SET, timeout) != OK) {
hperh->state = LPUART_STATE_READY;
return TIMEOUT;
}

37
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pis.c
View File

@ -44,7 +44,6 @@
*/
ald_status_t ald_pis_create(pis_handle_t *hperh)
{
pis_divide_t temp;
uint8_t clock_menu = 0;
if (hperh == NULL)
@ -61,16 +60,14 @@ ald_status_t ald_pis_create(pis_handle_t *hperh)
/* get location of consumer in channel and position of con0/con1
* accord to comsumer_trig information */
temp.HalfWord = (hperh->init.consumer_trig);
hperh->consumer_ch = (pis_ch_t)(temp.ch);
hperh->consumer_con = (pis_con_t)(temp.con);
hperh->consumer_pos = (1 << temp.shift);
hperh->consumer_ch = (pis_ch_t)(hperh->init.consumer_trig & 0x0F);
hperh->consumer_con = (pis_con_t)(((uint32_t)hperh->init.consumer_trig >> 4) & 0x0F);
hperh->consumer_pos = (1U << (uint32_t)(((uint32_t)hperh->init.consumer_trig >> 8) & 0xFF));
/* union producer clock and consumer clock */
clock_menu = (hperh->init.producer_clk << 4) | (hperh->init.consumer_clk);
if (hperh->perh->CH_CON[hperh->consumer_ch] != 0)
{
if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) {
__UNLOCK(hperh);
return BUSY;
}
@ -79,39 +76,32 @@ ald_status_t ald_pis_create(pis_handle_t *hperh)
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS);
/* configure sync clock, judging by producer clock with consumer clock */
switch (clock_menu)
{
switch (clock_menu) {
case 0x00:
case 0x11:
case 0x22:
case 0x33:
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS);
break;
case 0x01:
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS);
break;
case 0x02:
case 0x12:
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS);
break;
case 0x21:
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS);
break;
case 0x30:
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS);
break;
case 0x31:
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS);
break;
case 0x32:
MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS);
break;
default:
break;
}
@ -121,16 +111,13 @@ ald_status_t ald_pis_create(pis_handle_t *hperh)
hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch];
/* enable consumer bit, switch pin of consumer */
switch (hperh->consumer_con)
{
switch (hperh->consumer_con) {
case PIS_CON_0:
PIS->TAR_CON0 |= hperh->consumer_pos;
break;
case PIS_CON_1:
PIS->TAR_CON1 |= hperh->consumer_pos;
break;
default:
break;
}
@ -155,19 +142,16 @@ ald_status_t ald_pis_destroy(pis_handle_t *hperh)
__LOCK(hperh);
CLEAR_BIT(PIS->CH_OER, (1 << hperh->consumer_ch));
CLEAR_BIT(PIS->CH_OER, (1U << (uint32_t)hperh->consumer_ch));
WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0);
switch (hperh->consumer_con)
{
switch (hperh->consumer_con) {
case PIS_CON_0:
PIS->TAR_CON0 &= ~(hperh->consumer_pos);
break;
case PIS_CON_1:
PIS->TAR_CON1 &= ~(hperh->consumer_pos);
break;
default:
break;
}
@ -279,8 +263,7 @@ ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *con
assert_param(IS_PIS_MODU_CHANNEL(config->channel));
__LOCK(hperh);
switch (config->target)
{
switch (config->target) {
case PIS_UART0_TX:
MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);

42
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pmu.c
View File

@ -15,7 +15,6 @@
*/
#include "ald_pmu.h"
#include "ald_bkpc.h"
/** @addtogroup ES32FXXX_ALD
@ -63,6 +62,7 @@ void ald_lvd_irq_handler(void)
[..] This section provides functions allowing to:
(+) Enter stop1 mode.
(+) Enter stop2 mode.
(+) Enter standby mode.
(+) Get wakeup status.
(+) Clear wakeup status.
@ -108,6 +108,29 @@ void ald_pmu_stop2_enter(void)
return;
}
/**
* @brief Enter standby mode
* @param port: The port whick wake up the standby mode.
* @param level: Wakeup level.
* @retval None
*/
void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
{
ald_bkpc_standby_wakeup_config(port, level);
SYSCFG_UNLOCK();
SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);
MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STANDBY << PMU_CR_LPM_POSS);
SYSCFG_LOCK();
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__WFI();
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
return;
}
/**
* @brief Configures low power mode. The system clock must
* be less than 2MHz. Such as: LOSC or LRC.
@ -120,15 +143,13 @@ void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state)
assert_param(IS_FUNC_STATE(state));
SYSCFG_UNLOCK();
if (state)
{
if (state) {
assert_param(IS_PMU_LDO_LPMODE_OUTPUT(vol));
MODIFY_REG(PMU->CR, PMU_CR_LPVS_MSK, vol << PMU_CR_LPVS_POSS);
SET_BIT(PMU->CR, PMU_CR_LPRUN_MSK);
}
else
{
else {
CLEAR_BIT(PMU->CR, PMU_CR_LPRUN_MSK);
}
@ -169,8 +190,6 @@ void ald_pmu_clear_status(pmu_status_t sr)
SYSCFG_LOCK();
return;
}
/**
* @}
*/
@ -202,8 +221,7 @@ void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode,
assert_param(IS_FUNC_STATE(state));
SYSCFG_UNLOCK();
if (state)
{
if (state) {
assert_param(IS_PMU_LVD_VOL_SEL(sel));
assert_param(IS_PMU_LVD_TRIGGER_MODE(mode));
@ -214,8 +232,7 @@ void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode,
SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
}
else
{
else {
SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
@ -227,8 +244,6 @@ void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode,
/**
* @}
*/
/**
* @}
*/
@ -236,7 +251,6 @@ void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode,
/**
* @}
*/
/**
* @}
*/

18
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rmu.c
View File

@ -44,8 +44,7 @@ void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t sta
SYSCFG_UNLOCK();
if (state)
{
if (state) {
assert_param(IS_RMU_BORFLT(flt));
assert_param(IS_RMU_BORVOL(vol));
@ -53,8 +52,7 @@ void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t sta
MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS);
SET_BIT(RMU->CR, RMU_CR_BOREN_MSK);
}
else
{
else {
CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK);
}
@ -65,12 +63,15 @@ void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t sta
/**
* @brief Get specified reset status
* @param state: Speicifies the type of the reset,
* @retval The status: SET/RESET.
* @retval The status.
*/
flag_status_t ald_rmu_get_reset_status(rmu_state_t state)
uint32_t ald_rmu_get_reset_status(rmu_state_t state)
{
assert_param(IS_RMU_STATE(state));
if (state == RMU_RST_ALL)
return RMU->RSTSR;
if (READ_BIT(RMU->RSTSR, state))
return SET;
@ -103,12 +104,11 @@ void ald_rmu_reset_periperal(rmu_peripheral_t perh)
assert_param(IS_RMU_PERH(perh));
idx = (perh >> 27) & 0x7;
idx = ((uint32_t)perh >> 27) & 0x7;
pos = perh & ~(0x7 << 27);
SYSCFG_UNLOCK();
switch (idx)
{
switch (idx) {
case 0:
WRITE_REG(RMU->AHB1RSTR, pos);
break;

134
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rtc.c
View File

@ -170,19 +170,14 @@ static int32_t rtc_consistency_check(rtc_time_t *t_last,
{
if (t_last->second != time->second)
return 0;
if (t_last->minute != time->minute)
return 0;
if (t_last->hour != time->hour)
return 0;
if (d_last->day != date->day)
return 0;
if (d_last->month != date->month)
return 0;
if (d_last->year != date->year)
return 0;
@ -274,16 +269,13 @@ void ald_rtc_source_select(rtc_source_sel_t sel)
BKPC_UNLOCK();
MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, sel << BKPC_PCCR_RTCCS_POSS);
if (sel == RTC_SOURCE_LOSC)
{
if (sel == RTC_SOURCE_LOSC) {
SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);
}
else if (sel == RTC_SOURCE_LRC)
{
else if (sel == RTC_SOURCE_LRC) {
SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);
}
else
{
else {
; /* do nothing */
}
@ -325,8 +317,7 @@ ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format)
assert_param(IS_RTC_FORMAT(format));
if (format == RTC_FORMAT_DEC)
{
if (format == RTC_FORMAT_DEC) {
assert_param(IS_RTC_SECOND(time->second));
assert_param(IS_RTC_MINUTE(time->minute));
assert_param(IS_RTC_HOUR(time->hour));
@ -335,8 +326,7 @@ ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format)
(dec_to_bcd(time->minute) << 8) |
(dec_to_bcd(time->hour) << 16);
}
else
{
else {
assert_param(IS_RTC_SECOND(bcd_to_dec(time->second)));
assert_param(IS_RTC_MINUTE(bcd_to_dec(time->minute)));
assert_param(IS_RTC_HOUR(bcd_to_dec(time->hour)));
@ -346,13 +336,11 @@ ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format)
RTC_UNLOCK();
WRITE_REG(RTC->TIME, tmp);
WRITE_REG(RTC->SSEC, time->sub_sec);
RTC_LOCK();
tmp = ald_get_tick();
while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK))
{
while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) {
if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE)
return TIMEOUT;
}
@ -372,8 +360,7 @@ ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format)
assert_param(IS_RTC_FORMAT(format));
if (format == RTC_FORMAT_DEC)
{
if (format == RTC_FORMAT_DEC) {
assert_param(IS_RTC_DAY(date->day));
assert_param(IS_RTC_MONTH(date->month));
assert_param(IS_RTC_YEAR(date->year));
@ -383,8 +370,7 @@ ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format)
(dec_to_bcd(date->year) << 16) |
(dec_to_bcd(date->week) << 24);
}
else
{
else {
assert_param(IS_RTC_DAY(bcd_to_dec(date->day)));
assert_param(IS_RTC_MONTH(bcd_to_dec(date->month)));
assert_param(IS_RTC_YEAR(bcd_to_dec(date->year)));
@ -399,8 +385,7 @@ ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format)
tmp = ald_get_tick();
while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK))
{
while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) {
if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE)
return TIMEOUT;
}
@ -424,14 +409,12 @@ void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format)
time->sub_sec = RTC->SSEC & 0xFFFF;
tmp = RTC->TIME;
if (format == RTC_FORMAT_DEC)
{
if (format == RTC_FORMAT_DEC) {
time->second = bcd_to_dec(tmp & 0x7F);
time->minute = bcd_to_dec((tmp >> 8) & 0x7F);
time->hour = bcd_to_dec((tmp >> 16) & 0x7F);
}
else
{
else {
time->second = tmp & 0x7F;
time->minute = (tmp >> 8) & 0x7F;
time->hour = (tmp >> 16) & 0x7F;
@ -453,15 +436,13 @@ void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format)
assert_param(date != NULL);
assert_param(IS_RTC_FORMAT(format));
if (format == RTC_FORMAT_DEC)
{
if (format == RTC_FORMAT_DEC) {
date->day = bcd_to_dec(tmp & 0x3F);
date->month = bcd_to_dec((tmp >> 8) & 0x1F);
date->year = bcd_to_dec((tmp >> 16) & 0xFF);
date->week = bcd_to_dec((tmp >> 24) & 0x7);
}
else
{
else {
date->day = tmp & 0x3F;
date->month = (tmp >> 8) & 0x1F;
date->year = (tmp >> 16) & 0xFF;
@ -486,8 +467,7 @@ int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t f
rtc_date_t d_last;
rtc_time_t t_last;
while (nr--)
{
while (nr--) {
ald_rtc_get_time(&t_last, format);
ald_rtc_get_date(&d_last, format);
ald_rtc_get_time(time, format);
@ -535,8 +515,7 @@ void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format)
assert_param(IS_RTC_ALARM_SS_MASK(alarm->ss_mask));
assert_param(IS_RTC_FORMAT(format));
if (format == RTC_FORMAT_DEC)
{
if (format == RTC_FORMAT_DEC) {
assert_param(IS_RTC_SECOND(alarm->time.second));
assert_param(IS_RTC_MINUTE(alarm->time.minute));
assert_param(IS_RTC_HOUR(alarm->time.hour));
@ -546,21 +525,18 @@ void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format)
(dec_to_bcd(alarm->time.hour) << 16) |
alarm->mask;
if (alarm->sel == RTC_SELECT_DAY)
{
if (alarm->sel == RTC_SELECT_DAY) {
assert_param(IS_RTC_DAY(alarm->day));
tmp |= (dec_to_bcd(alarm->day) << 24);
tmp &= 0x7FFFFFFF; /* Reset bit31 */
}
else
{
else {
tmp |= (1 << (alarm->week + 24));
tmp |= 0x80000000; /* Set bit31 */
}
}
else
{
else {
assert_param(IS_RTC_SECOND(bcd_to_dec(alarm->time.second)));
assert_param(IS_RTC_MINUTE(bcd_to_dec(alarm->time.minute)));
assert_param(IS_RTC_HOUR(bcd_to_dec(alarm->time.hour)));
@ -570,15 +546,13 @@ void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format)
(alarm->time.hour << 16) |
alarm->mask;
if (alarm->sel == RTC_SELECT_DAY)
{
if (alarm->sel == RTC_SELECT_DAY) {
assert_param(IS_RTC_DAY(bcd_to_dec(alarm->day)));
tmp |= (alarm->day << 24);
tmp &= 0x7FFFFFFF; /* Reset bit31 */
}
else
{
else {
tmp |= (1 << (alarm->week + 24));
tmp |= 0x80000000; /* Set bit31 */
}
@ -589,14 +563,12 @@ void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format)
RTC_UNLOCK();
if (alarm->idx == RTC_ALARM_A)
{
if (alarm->idx == RTC_ALARM_A) {
WRITE_REG(RTC->ALMA, tmp);
WRITE_REG(RTC->ALMASSEC, ss_tmp);
SET_BIT(RTC->CON, RTC_CON_ALMAEN_MSK);
}
else
{
else {
WRITE_REG(RTC->ALMB, tmp);
WRITE_REG(RTC->ALMBSSEC, ss_tmp);
SET_BIT(RTC->CON, RTC_CON_ALMBEN_MSK);
@ -620,58 +592,46 @@ void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format)
assert_param(alarm != NULL);
assert_param(IS_RTC_FORMAT(format));
if (alarm->idx == RTC_ALARM_A)
{
if (alarm->idx == RTC_ALARM_A) {
tmp = RTC->ALMA;
ss_tmp = RTC->ALMASSEC;
}
else
{
else {
tmp = RTC->ALMB;
ss_tmp = RTC->ALMBSSEC;
}
if ((tmp >> 31) & 0x1)
{
if ((tmp >> 31) & 0x1) {
alarm->sel = RTC_SELECT_WEEK;
week = ((tmp >> 24) & 0x7F);
switch (week)
{
switch (week) {
case 1:
alarm->week = 0;
break;
case 2:
alarm->week = 1;
break;
case 4:
alarm->week = 2;
break;
case 8:
alarm->week = 3;
break;
case 16:
alarm->week = 4;
break;
case 32:
alarm->week = 5;
break;
case 64:
alarm->week = 6;
break;
default:
break;
}
}
else
{
else {
alarm->sel = RTC_SELECT_DAY;
if (format == RTC_FORMAT_DEC)
@ -680,14 +640,12 @@ void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format)
alarm->day = (tmp >> 24) & 0x3F;
}
if (format == RTC_FORMAT_DEC)
{
if (format == RTC_FORMAT_DEC) {
alarm->time.second = bcd_to_dec(tmp & 0x7F);
alarm->time.minute = bcd_to_dec((tmp >> 8) & 0x7F);
alarm->time.hour = bcd_to_dec((tmp >> 16) & 0x3F);
}
else
{
else {
alarm->time.second = tmp & 0x7F;
alarm->time.minute = (tmp >> 8) & 0x7F;
alarm->time.hour = (tmp >> 16) & 0x3F;
@ -779,8 +737,7 @@ void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format
tmp0 = RTC->TSTIME;
tmp1 = RTC->TSDATE;
if (format == RTC_FORMAT_DEC)
{
if (format == RTC_FORMAT_DEC) {
ts_time->second = bcd_to_dec(tmp0 & 0x7F);
ts_time->minute = bcd_to_dec((tmp0 >> 8) & 0x7F);
ts_time->hour = bcd_to_dec((tmp0 >> 16) & 0x3F);
@ -789,8 +746,7 @@ void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format
ts_date->year = bcd_to_dec((tmp1 >> 16) & 0xFF);
ts_date->week = bcd_to_dec((tmp1 >> 24) & 0x7);
}
else
{
else {
ts_time->second = tmp0 & 0x7F;
ts_time->minute = (tmp0 >> 8) & 0x7F;
ts_time->hour = (tmp0 >> 16) & 0x3F;
@ -840,16 +796,14 @@ void ald_rtc_set_tamper(rtc_tamper_t *tamper)
MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPCKS_MSK, tamper->freq << RTC_TAMPCON_TAMPCKS_POSS);
MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPFLT_MSK, tamper->dur << RTC_TAMPCON_TAMPFLT_POSS);
if (tamper->idx == RTC_TAMPER_0)
{
if (tamper->idx == RTC_TAMPER_0) {
MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP0LV_MSK, tamper->trig << RTC_TAMPCON_TAMP0LV_POS);
SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP0EN_MSK);
}
else {
MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP1LV_MSK, tamper->trig << RTC_TAMPCON_TAMP1LV_POS);
SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK);
}
else
{
MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP2LV_MSK, tamper->trig << RTC_TAMPCON_TAMP2LV_POS);
SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK);
}
RTC_LOCK();
return;
@ -869,9 +823,9 @@ void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx)
RTC_UNLOCK();
if (idx == RTC_TAMPER_0)
CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK);
CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP0EN_MSK);
else
CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK);
CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK);
RTC_LOCK();
return;
@ -969,18 +923,13 @@ ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock)
SYSCFG_UNLOCK();
if (clock == RTC_CLOCK_OUTPUT_EXA_1)
{
if (clock == RTC_CLOCK_OUTPUT_EXA_1) {
SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK);
while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2LCKN_MSK)) && (--cnt));
cnt = 4000;
while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL2RDY_MSK))) && (--cnt));
}
else
{
else {
CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK);
}
@ -1102,8 +1051,7 @@ ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss)
tick = ald_get_tick();
while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK))
{
while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK)) {
if ((ald_get_tick() - tick) > RTC_TIMEOUT_VALUE)
return TIMEOUT;
}

62
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_smartcard.c
View File

@ -122,9 +122,9 @@ static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hsmartcard);
static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh);
static void smartcard_set_config(smartcard_handle_t *hperh);
#ifdef ALD_DMA
static void smartcard_dma_send_cplt(void *arg);
static void smartcard_dma_recv_cplt(void *arg);
static void smartcard_dma_error(void *arg);
static void smartcard_dma_send_cplt(void *arg);
static void smartcard_dma_recv_cplt(void *arg);
static void smartcard_dma_error(void *arg);
#endif
static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout);
/**
@ -324,7 +324,6 @@ ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_
{
if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX))
return BUSY;
if ((buf == NULL) || (size == 0))
return ERROR;
@ -335,10 +334,8 @@ ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_
hperh->tx_size = size;
hperh->tx_count = size;
while (hperh->tx_count-- > 0)
{
if (smartcard_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK)
{
while (hperh->tx_count-- > 0) {
if (smartcard_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) {
hperh->state = SMARTCARD_STATE_READY;
__UNLOCK(hperh);
return TIMEOUT;
@ -347,8 +344,7 @@ ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_
WRITE_REG(hperh->perh->DATA, *buf++);
}
if (smartcard_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK)
{
if (smartcard_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) {
hperh->state = SMARTCARD_STATE_READY;
__UNLOCK(hperh);
return TIMEOUT;
@ -373,7 +369,6 @@ ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_
{
if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX))
return BUSY;
if ((buf == NULL) || (size == 0))
return ERROR;
@ -384,10 +379,8 @@ ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_
hperh->rx_size = size;
hperh->rx_count = size;
while (hperh->rx_count-- > 0)
{
if (smartcard_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK)
{
while (hperh->rx_count-- > 0) {
if (smartcard_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) {
hperh->state = SMARTCARD_STATE_READY;
__UNLOCK(hperh);
return TIMEOUT;
@ -414,7 +407,6 @@ ald_status_t ald_smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, u
{
if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX))
return BUSY;
if ((buf == NULL) || (size == 0))
return ERROR;
@ -445,7 +437,6 @@ ald_status_t ald_smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, u
{
if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX))
return BUSY;
if ((buf == NULL) || (size == 0))
return ERROR;
@ -479,7 +470,6 @@ ald_status_t ald_smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf,
{
if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX))
return BUSY;
if ((buf == NULL) || (size == 0))
return ERROR;
@ -531,7 +521,6 @@ ald_status_t ald_smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf,
{
if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX))
return BUSY;
if ((buf == NULL) || (size == 0))
return ERROR;
@ -583,53 +572,45 @@ void ald_smartcard_irq_handler(smartcard_handle_t *hperh)
/* Handle parity error */
flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_PE);
source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_PE);
if ((flag != RESET) && (source != RESET))
hperh->err_code |= SMARTCARD_ERROR_PE;
/* Handle frame error */
flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_FE);
source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_ERR);
if ((flag != RESET) && (source != RESET))
hperh->err_code |= SMARTCARD_ERROR_FE;
/* Handle noise error */
flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_NE);
if ((flag != RESET) && (source != RESET))
hperh->err_code |= SMARTCARD_ERROR_NE;
/* Handle overrun error */
flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_ORE);
if ((flag != RESET) && (source != RESET))
hperh->err_code |= SMARTCARD_ERROR_ORE;
/* Handle receive */
flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_RXNE);
source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_RXNE);
if ((flag != RESET) && (source != RESET))
__smartcard_recv_by_it(hperh);
/* Handle transmit */
flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TXE);
source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TXE);
if ((flag != RESET) && (source != RESET))
__smartcard_send_by_it(hperh);
/* Handle transmit complete */
flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TC);
source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TC);
if ((flag != RESET) && (source != RESET))
__smartcard_end_send_by_it(hperh);
/* Handle error */
if (hperh->err_code != SMARTCARD_ERROR_NONE)
{
if (hperh->err_code != SMARTCARD_ERROR_NONE) {
USART_CLEAR_PEFLAG(hperh);
hperh->state = SMARTCARD_STATE_READY;
@ -704,7 +685,7 @@ uint32_t ald_smartcard_get_error(smartcard_handle_t *hperh)
*/
static void smartcard_dma_send_cplt(void *arg)
{
smartcard_handle_t *hperh = (smartcard_handle_t *)arg;
smartcard_handle_t* hperh = ( smartcard_handle_t *)arg;
hperh->tx_count = 0;
ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE);
@ -721,7 +702,7 @@ static void smartcard_dma_send_cplt(void *arg)
*/
static void smartcard_dma_recv_cplt(void *arg)
{
smartcard_handle_t *hperh = (smartcard_handle_t *)arg;
smartcard_handle_t* hperh = ( smartcard_handle_t* )arg;
hperh->rx_count = 0;
ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE);
@ -741,7 +722,7 @@ static void smartcard_dma_recv_cplt(void *arg)
*/
static void smartcard_dma_error(void *arg)
{
smartcard_handle_t *hperh = (smartcard_handle_t *)arg;
smartcard_handle_t* hperh = ( smartcard_handle_t* )arg;
hperh->rx_count = 0;
hperh->tx_count = 0;
@ -776,10 +757,8 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t
tick = ald_get_tick();
while ((ald_usart_get_flag_status((usart_handle_t *)hperh, flag)) != status)
{
if (((ald_get_tick()) - tick) > timeout)
{
while ((ald_usart_get_flag_status((usart_handle_t *)hperh, flag)) != status) {
if (((ald_get_tick()) - tick) > timeout) {
ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE);
ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE);
ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE);
@ -807,8 +786,7 @@ static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh)
WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++);
if (--hperh->tx_count == 0)
{
if (--hperh->tx_count == 0) {
ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE);
ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE);
}
@ -851,8 +829,7 @@ static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh)
*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
if (--hperh->rx_count == 0)
{
if (--hperh->rx_count == 0) {
ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE);
ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE);
ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE);
@ -911,17 +888,14 @@ static void smartcard_set_config(smartcard_handle_t *hperh)
MODIFY_REG(tmp, USART_CON1_LBCP_MSK, hperh->init.last_bit << USART_CON1_LBCP_POS);
/* Determine the integer part */
if (READ_BIT(hperh->perh->CON0, (1 << 15)))
{
if (READ_BIT(hperh->perh->CON0, (1 << 15))) {
/* Integer part computing in case Oversampling mode is 8 Samples */
integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud)));
}
else
{
else {
/* Integer part computing in case Oversampling mode is 16 Samples */
integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud)));
}
tmp = (integer / 100) << 4;
/* Determine the fractional part */

366
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_spi.c
View File

@ -78,10 +78,10 @@ static void __spi_send_by_it(spi_handle_t *hperh);
static void __spi_recv_by_it(spi_handle_t *hperh);
static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status);
#ifdef ALD_DMA
static void spi_dma_send_cplt(void *arg);
static void spi_dma_recv_cplt(void *arg);
static void spi_dma_send_recv_cplt(void *arg);
static void spi_dma_error(void *arg);
static void spi_dma_send_cplt(void *arg);
static void spi_dma_recv_cplt(void *arg);
static void spi_dma_send_recv_cplt(void *arg);
static void spi_dma_error(void *arg);
#endif
/**
* @}
@ -152,20 +152,20 @@ ald_status_t ald_spi_init(spi_handle_t *hperh)
{
uint32_t tmp = 0;
if (hperh == NULL)
return ERROR;
assert_param(IS_SPI(hperh->perh));
assert_param(IS_SPI_MODE(hperh->init.mode));
assert_param(IS_SPI_DIRECTION(hperh->init.dir));
assert_param(IS_SPI_BAUD(hperh->init.baud));
assert_param(IS_FUNC_STATE(hperh->init.first_bit));
assert_param(IS_SPI_FIRSTBIT(hperh->init.first_bit));
assert_param(IS_FUNC_STATE(hperh->init.ss_en));
assert_param(IS_FUNC_STATE(hperh->init.crc_calc));
assert_param(IS_SPI_DATASIZE(hperh->init.data_size));
assert_param(IS_SPI_CPHA(hperh->init.phase));
assert_param(IS_SPI_CPOL(hperh->init.polarity));
if (hperh == NULL)
return ERROR;
ald_spi_reset(hperh);
tmp = hperh->perh->CON1;
@ -180,18 +180,15 @@ ald_status_t ald_spi_init(spi_handle_t *hperh)
hperh->perh->CON1 = tmp;
if (hperh->init.dir == SPI_DIRECTION_2LINES)
{
if (hperh->init.dir == SPI_DIRECTION_2LINES) {
CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK);
CLEAR_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK);
}
else if (hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY)
{
else if (hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) {
CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK);
SET_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK);
}
else
{
else {
SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK);
}
@ -256,13 +253,9 @@ int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data)
uint16_t cnt = 2000, temp;
hperh->perh->DATA = data;
while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt));
cnt = 2000;
while ((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0 && (--cnt));
temp = hperh->perh->DATA;
UNUSED(temp);
@ -282,7 +275,6 @@ int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data)
uint16_t cnt = 2000;
hperh->perh->DATA = data;
while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt));
return cnt == 0 ? -1 : 0;
@ -297,17 +289,13 @@ uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh)
{
uint16_t cnt = 2000;
if (hperh->init.mode == SPI_MODE_MASTER)
{
if (hperh->init.mode == SPI_MODE_MASTER) {
hperh->perh->DATA = 0xFF;
while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt));
}
cnt = 2000;
while (((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0) && (--cnt));
return (uint8_t)hperh->perh->DATA;
}
@ -325,7 +313,6 @@ ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint
if (hperh->state != SPI_STATE_READY)
return BUSY;
if (buf == NULL || size == 0)
return ERROR;
@ -343,33 +330,26 @@ ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
if (hperh->init.dir == SPI_DIRECTION_1LINE)
SPI_1LINE_TX(hperh);
if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0)
SPI_ENABLE(hperh);
if ((hperh->init.mode == SPI_MODE_SLAVER) || (hperh->tx_count == 1))
{
if (hperh->init.data_size == SPI_DATA_SIZE_8)
{
if ((hperh->init.mode == SPI_MODE_SLAVER) || (hperh->tx_count == 1)) {
if (hperh->init.data_size == SPI_DATA_SIZE_8) {
hperh->perh->DATA = *hperh->tx_buf;
++hperh->tx_buf;
--hperh->tx_count;
}
else
{
else {
hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf);
hperh->tx_buf += 2;
--hperh->tx_count;
}
}
while (hperh->tx_count > 0)
{
if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK)
{
while (hperh->tx_count > 0) {
if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) {
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
@ -378,14 +358,12 @@ ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint
return TIMEOUT;
}
if (hperh->init.data_size == SPI_DATA_SIZE_8)
{
if (hperh->init.data_size == SPI_DATA_SIZE_8) {
hperh->perh->DATA = *hperh->tx_buf;
++hperh->tx_buf;
--hperh->tx_count;
}
else
{
else {
hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf);
hperh->tx_buf += 2;
--hperh->tx_count;
@ -396,8 +374,7 @@ ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint
SPI_CRCNEXT_ENABLE(hperh);
if ((spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK)
|| (spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK))
{
|| (spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) {
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
@ -430,7 +407,6 @@ ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint
if (hperh->state != SPI_STATE_READY)
return BUSY;
if (buf == NULL || size == 0)
return ERROR;
@ -447,12 +423,10 @@ ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
if (hperh->init.dir == SPI_DIRECTION_1LINE_RX)
SPI_1LINE_RX(hperh);
if ((hperh->init.mode == SPI_MODE_MASTER) && (hperh->init.dir == SPI_DIRECTION_2LINES))
{
if ((hperh->init.mode == SPI_MODE_MASTER) && (hperh->init.dir == SPI_DIRECTION_2LINES)) {
__UNLOCK(hperh);
hperh->state = SPI_STATE_READY;
return ald_spi_send_recv(hperh, buf, buf, size, timeout);
@ -461,10 +435,8 @@ ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint
if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX))
SPI_ENABLE(hperh);
while (hperh->rx_count > 1)
{
if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK)
{
while (hperh->rx_count > 1) {
if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) {
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
@ -473,14 +445,12 @@ ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint
return TIMEOUT;
}
if (hperh->init.data_size == SPI_DATA_SIZE_8)
{
if (hperh->init.data_size == SPI_DATA_SIZE_8) {
*hperh->rx_buf = hperh->perh->DATA;
++hperh->rx_buf;
--hperh->rx_count;
}
else
{
else {
*(uint16_t *)hperh->rx_buf = hperh->perh->DATA;
hperh->rx_buf += 2;
--hperh->rx_count;
@ -490,8 +460,7 @@ ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint
if (hperh->init.crc_calc)
SPI_CRCNEXT_ENABLE(hperh);
if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK)
{
if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) {
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
@ -500,23 +469,19 @@ ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint
return TIMEOUT;
}
if (hperh->init.data_size == SPI_DATA_SIZE_8)
{
if (hperh->init.data_size == SPI_DATA_SIZE_8) {
*hperh->rx_buf = hperh->perh->DATA;
++hperh->rx_buf;
--hperh->rx_count;
}
else
{
else {
*(uint16_t *)hperh->rx_buf = hperh->perh->DATA;
hperh->rx_buf += 2;
--hperh->rx_count;
}
if (hperh->init.crc_calc)
{
if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK)
{
if (hperh->init.crc_calc) {
if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) {
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
@ -529,8 +494,7 @@ ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint
UNUSED(temp);
}
if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET))
{
if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) {
hperh->err_code |= SPI_ERROR_CRC;
SPI_CRC_RESET(hperh);
ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
@ -562,10 +526,8 @@ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx
if (hperh->state != SPI_STATE_READY)
return BUSY;
if (hperh->init.dir != SPI_DIRECTION_2LINES)
return ERROR;
if (tx_buf == NULL || rx_buf == NULL || size == 0)
return ERROR;
@ -583,29 +545,24 @@ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
if ((hperh->init.mode == SPI_MODE_SLAVER) || ((hperh->init.mode == SPI_MODE_SLAVER) && (hperh->tx_size == 1)))
{
if (hperh->init.data_size == SPI_DATA_SIZE_8)
{
if ((hperh->init.mode == SPI_MODE_SLAVER) || ((hperh->init.mode == SPI_MODE_SLAVER) && (hperh->tx_size == 1))) {
if (hperh->init.data_size == SPI_DATA_SIZE_8) {
hperh->perh->DATA = *hperh->tx_buf;
++hperh->tx_buf;
--hperh->tx_count;
}
else
{
else {
hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf);
hperh->tx_buf += 2;
--hperh->tx_count;
}
}
if (hperh->tx_buf == 0)
{
if (hperh->tx_count == 0) {
if (hperh->init.crc_calc)
SPI_CRCNEXT_ENABLE(hperh);
if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK)
{
if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) {
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
@ -614,24 +571,20 @@ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx
return TIMEOUT;
}
if (hperh->init.data_size == SPI_DATA_SIZE_8)
{
if (hperh->init.data_size == SPI_DATA_SIZE_8) {
*hperh->rx_buf = hperh->perh->DATA;
++hperh->rx_buf;
--hperh->rx_count;
}
else
{
else {
(*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA;
hperh->rx_buf += 2;
--hperh->rx_count;
}
}
while (hperh->tx_count > 0)
{
if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK)
{
while (hperh->tx_count > 0) {
if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) {
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
@ -640,14 +593,12 @@ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx
return TIMEOUT;
}
if (hperh->init.data_size == SPI_DATA_SIZE_8)
{
if (hperh->init.data_size == SPI_DATA_SIZE_8) {
hperh->perh->DATA = *hperh->tx_buf;
++hperh->tx_buf;
--hperh->tx_count;
}
else
{
else {
hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf);
hperh->tx_buf += 2;
--hperh->tx_count;
@ -656,8 +607,7 @@ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx
if ((hperh->tx_count == 0) && (hperh->init.crc_calc))
SPI_CRCNEXT_ENABLE(hperh);
if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK)
{
if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) {
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
@ -666,14 +616,12 @@ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx
return TIMEOUT;
}
if (hperh->init.data_size == SPI_DATA_SIZE_8)
{
if (hperh->init.data_size == SPI_DATA_SIZE_8) {
*hperh->rx_buf = hperh->perh->DATA;
++hperh->rx_buf;
--hperh->rx_count;
}
else
{
else {
(*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA;
hperh->rx_buf += 2;
@ -681,10 +629,8 @@ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx
}
}
if (hperh->init.mode == SPI_MODE_SLAVER)
{
if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK)
{
if (hperh->init.mode == SPI_MODE_SLAVER) {
if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) {
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
@ -693,14 +639,12 @@ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx
return TIMEOUT;
}
if (hperh->init.data_size == SPI_DATA_SIZE_8)
{
if (hperh->init.data_size == SPI_DATA_SIZE_8) {
*hperh->rx_buf = hperh->perh->DATA;
++hperh->rx_buf;
--hperh->rx_count;
}
else
{
else {
(*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA;
hperh->rx_buf += 2;
@ -708,10 +652,8 @@ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx
}
}
if (hperh->init.crc_calc)
{
if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK)
{
if (hperh->init.crc_calc) {
if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) {
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
@ -724,8 +666,7 @@ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx
UNUSED(temp);
}
if ((spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK))
{
if ((spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) {
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
@ -734,8 +675,7 @@ ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx
return TIMEOUT;
}
if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET))
{
if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) {
hperh->err_code |= SPI_ERROR_CRC;
SPI_CRC_RESET(hperh);
ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
@ -764,7 +704,6 @@ ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size
if (hperh->state != SPI_STATE_READY)
return BUSY;
if (buf == NULL || size == 0)
return ERROR;
@ -786,12 +725,10 @@ ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size
if (hperh->init.dir == SPI_DIRECTION_1LINE)
SPI_1LINE_TX(hperh);
if (hperh->init.dir == SPI_DIRECTION_2LINES)
{
if (hperh->init.dir == SPI_DIRECTION_2LINES) {
ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE);
}
else
{
else {
ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE);
ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE);
}
@ -815,10 +752,8 @@ ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size
if (hperh->state != SPI_STATE_READY)
return BUSY;
if (buf == NULL || size == 0)
return ERROR;
if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER))
return ERROR; /* Please call ald_spi_send_recv_by_it() */
@ -864,7 +799,6 @@ ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8
if (hperh->state != SPI_STATE_READY)
return BUSY;
if (tx_buf == NULL || rx_buf == NULL || size == 0)
return ERROR;
@ -905,7 +839,6 @@ ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t siz
if (hperh->state != SPI_STATE_READY)
return BUSY;
if (buf == NULL || size == 0)
return ERROR;
@ -922,7 +855,6 @@ ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t siz
if (hperh->init.dir == SPI_DIRECTION_1LINE)
SPI_1LINE_TX(hperh);
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
@ -970,7 +902,6 @@ ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t siz
if (hperh->state != SPI_STATE_READY)
return BUSY;
if (buf == NULL || size == 0)
return ERROR;
@ -987,13 +918,10 @@ ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t siz
if (hperh->init.dir == SPI_DIRECTION_1LINE_RX)
SPI_1LINE_RX(hperh);
if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER))
{
if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) {
__UNLOCK(hperh);
return ERROR; /* Please use ald_spi_send_recv_by_dma() */
}
if (hperh->init.crc_calc)
SPI_CRC_RESET(hperh);
@ -1043,7 +971,6 @@ ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint
if (hperh->state != SPI_STATE_READY && hperh->state != SPI_STATE_BUSY_RX)
return BUSY;
if (tx_buf == NULL || rx_buf == NULL || size == 0)
return ERROR;
@ -1060,7 +987,6 @@ ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint
if (hperh->hdmatx.perh == NULL)
hperh->hdmatx.perh = DMA0;
if (hperh->hdmarx.perh == NULL)
hperh->hdmarx.perh = DMA0;
@ -1193,8 +1119,7 @@ ald_status_t ald_spi_dma_stop(spi_handle_t *hperh)
*/
void ald_spi_irq_handler(spi_handle_t *hperh)
{
if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX))
{
if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX)) {
if ((ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET))
__spi_recv_by_it(hperh);
@ -1202,46 +1127,46 @@ void ald_spi_irq_handler(spi_handle_t *hperh)
__spi_send_by_it(hperh);
}
else if (hperh->state == SPI_STATE_BUSY_TX_RX)
{
if (hperh->tx_size == hperh->tx_count)
{
else if (hperh->state == SPI_STATE_BUSY_TX_RX) {
if (hperh->tx_size == hperh->tx_count) {
if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET))
__spi_send_recv_by_it(hperh, SPI_SR_TXBE);
}
else
{
else {
if (hperh->init.mode == SPI_MODE_MASTER) {
if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)
&& (ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET))
__spi_send_recv_by_it(hperh, SPI_SR_TXBE_RXBNE);
}
else {
if ((ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET))
__spi_send_recv_by_it(hperh, SPI_SR_RXBNE);
if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET))
__spi_send_recv_by_it(hperh, SPI_SR_TXBE);
}
if ((ald_spi_get_it_status(hperh, SPI_IT_ERR) != RESET))
{
if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)
{
}
}
if ((ald_spi_get_it_status(hperh, SPI_IT_ERR) != RESET)) {
if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) {
hperh->err_code |= SPI_ERROR_CRC;
ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
}
if (ald_spi_get_flag_status(hperh, SPI_IF_MODF) != RESET)
{
if (ald_spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) {
hperh->err_code |= SPI_ERROR_MODF;
ald_spi_clear_flag_status(hperh, SPI_IF_MODF);
}
if (ald_spi_get_flag_status(hperh, SPI_IF_OVE) != RESET)
{
if (hperh->state != SPI_STATE_BUSY_TX)
{
if (ald_spi_get_flag_status(hperh, SPI_IF_OVE) != RESET) {
if ((hperh->state != SPI_STATE_BUSY_TX) && (hperh->state != SPI_STATE_READY)) {
hperh->err_code |= SPI_ERROR_OVE;
ald_spi_clear_flag_status(hperh, SPI_IF_OVE);
}
}
if (hperh->err_code != SPI_ERROR_NONE)
{
if (hperh->err_code != SPI_ERROR_NONE) {
ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE);
ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE);
ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE);
@ -1293,7 +1218,7 @@ void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed)
assert_param(IS_SPI_BAUD(speed));
tmp = hperh->perh->CON1;
tmp &= ~(0x7 << SPI_CON1_BAUD_POSS);
tmp &= ~(0x7U << SPI_CON1_BAUD_POSS);
tmp |= (speed << SPI_CON1_BAUD_POSS);
hperh->perh->CON1 = tmp;
return;
@ -1315,15 +1240,13 @@ void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t
assert_param(IS_SPI_DMA_REQ(req));
assert_param(IS_FUNC_STATE(state));
if (state == ENABLE)
{
if (state == ENABLE) {
if (req == SPI_DMA_REQ_TX)
SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK);
else
SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK);
}
else
{
else {
if (req == SPI_DMA_REQ_TX)
CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK);
else
@ -1404,22 +1327,17 @@ void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag)
assert_param(IS_SPI(hperh->perh));
assert_param(IS_SPI_IF(flag));
if (flag == SPI_IF_CRCERR)
{
if (flag == SPI_IF_CRCERR) {
SET_BIT(hperh->perh->STAT, SPI_STAT_CRCERR_MSK);
return;
}
if (flag == SPI_IF_OVE)
{
if (flag == SPI_IF_OVE) {
temp = hperh->perh->DATA;
temp = hperh->perh->STAT;
UNUSED(temp);
return;
}
if (flag == SPI_IF_MODF)
{
if (flag == SPI_IF_MODF) {
temp = hperh->perh->STAT;
UNUSED(temp);
hperh->perh->CON1 = hperh->perh->CON1;
@ -1443,10 +1361,8 @@ static ald_status_t spi_wait_flag(spi_handle_t *hperh, spi_flag_t flag, flag_sta
assert_param(timeout > 0);
while ((ald_spi_get_flag_status(hperh, flag)) != status)
{
if (((ald_get_tick()) - tick) > timeout)
{
while ((ald_spi_get_flag_status(hperh, flag)) != status) {
if (((ald_get_tick()) - tick) > timeout) {
ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE);
ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE);
ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE);
@ -1542,16 +1458,15 @@ uint32_t ald_spi_get_error(spi_handle_t *hperh)
*/
static void __spi_send_by_it(spi_handle_t *hperh)
{
if (hperh->tx_count == 0)
{
if (hperh->tx_count == 0) {
ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE);
ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE);
hperh->state = SPI_STATE_READY;
if (hperh->init.dir == SPI_DIRECTION_2LINES)
ald_spi_clear_flag_status(hperh, SPI_IF_OVE);
if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK)
{
if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) {
if (hperh->err_cbk)
hperh->err_cbk(hperh);
@ -1564,21 +1479,17 @@ static void __spi_send_by_it(spi_handle_t *hperh)
return;
}
if (hperh->init.data_size == SPI_DATA_SIZE_8)
{
if (hperh->init.data_size == SPI_DATA_SIZE_8) {
hperh->perh->DATA = *hperh->tx_buf;
++hperh->tx_buf;
}
else
{
else {
hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
hperh->tx_buf += 2;
}
--hperh->tx_count;
if (hperh->tx_count == 0)
{
if (hperh->tx_count == 0) {
if (hperh->init.crc_calc)
SPI_CRCNEXT_ENABLE(hperh);
}
@ -1594,30 +1505,25 @@ static void __spi_send_by_it(spi_handle_t *hperh)
static void __spi_recv_by_it(spi_handle_t *hperh)
{
uint16_t temp;
if (hperh->init.data_size == SPI_DATA_SIZE_8)
{
if (hperh->init.data_size == SPI_DATA_SIZE_8) {
*hperh->rx_buf = hperh->perh->DATA;
++hperh->rx_buf;
}
else
{
else {
*(uint16_t *)hperh->rx_buf = hperh->perh->DATA;
hperh->rx_buf += 2;
}
--hperh->rx_count;
if ((hperh->rx_count == 1) && (hperh->init.crc_calc))
SPI_CRCNEXT_ENABLE(hperh);
if (hperh->rx_count == 0)
{
if (hperh->rx_count == 0) {
ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE);
ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE);
hperh->state = SPI_STATE_READY;
if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET))
{
if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) {
hperh->err_code |= SPI_ERROR_CRC;
ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
@ -1627,8 +1533,7 @@ static void __spi_recv_by_it(spi_handle_t *hperh)
return;
}
if (hperh->init.crc_calc)
{
if (hperh->init.crc_calc) {
temp = hperh->perh->DATA;
UNUSED(temp);
}
@ -1650,17 +1555,13 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status)
{
assert_param(IS_SPI_SR_STATUS(status));
if (hperh->rx_count != 0)
{
if ((status == SPI_SR_RXBNE) || (status == SPI_SR_TXBE_RXBNE))
{
if (hperh->init.data_size == SPI_DATA_SIZE_8)
{
if (hperh->rx_count != 0) {
if ((status == SPI_SR_RXBNE) || (status == SPI_SR_TXBE_RXBNE)) {
if (hperh->init.data_size == SPI_DATA_SIZE_8) {
*hperh->rx_buf = hperh->perh->DATA;
++hperh->rx_buf;
}
else
{
else {
*(uint16_t *)hperh->rx_buf = hperh->perh->DATA;
hperh->rx_buf += 2;
}
@ -1669,19 +1570,14 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status)
}
}
if (hperh->tx_count != 0)
{
if ((status == SPI_SR_TXBE) || (status == SPI_SR_TXBE_RXBNE))
{
if (hperh->tx_count == 1)
{
if (hperh->init.data_size == SPI_DATA_SIZE_8)
{
if (hperh->tx_count != 0) {
if ((status == SPI_SR_TXBE) || (status == SPI_SR_TXBE_RXBNE)) {
if (hperh->tx_count == 1) {
if (hperh->init.data_size == SPI_DATA_SIZE_8) {
hperh->perh->DATA = *hperh->tx_buf;
++hperh->tx_buf;
}
else
{
else {
hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
hperh->tx_buf += 2;
}
@ -1691,39 +1587,32 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status)
if (hperh->init.crc_calc)
SPI_CRCNEXT_ENABLE(hperh);
}
else
{
if (hperh->init.data_size == SPI_DATA_SIZE_8)
{
else {
if (hperh->init.data_size == SPI_DATA_SIZE_8) {
hperh->perh->DATA = *hperh->tx_buf;
++hperh->tx_buf;
}
else
{
else {
hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
hperh->tx_buf += 2;
}
if (--hperh->tx_count == 0)
{
if (--hperh->tx_count == 0) {
if (hperh->init.crc_calc)
SPI_CRCNEXT_ENABLE(hperh);
ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE);
}
}
}
}
if (hperh->rx_count == 0)
{
if (hperh->rx_count == 0) {
ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE);
ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE);
ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE);
hperh->state = SPI_STATE_READY;
if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET))
{
if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) {
hperh->err_code |= SPI_ERROR_CRC;
ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
@ -1740,7 +1629,6 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status)
return;
}
#ifdef ALD_DMA
/**
* @brief DMA SPI transmit process complete callback.
@ -1764,13 +1652,11 @@ static void spi_dma_send_cplt(void *arg)
for (delay = 0; delay < 3000; delay++);
if (hperh->err_code == SPI_ERROR_NONE)
{
if (hperh->err_code == SPI_ERROR_NONE) {
if (hperh->tx_cplt_cbk)
hperh->tx_cplt_cbk(hperh);
}
else
{
else {
if (hperh->err_cbk)
hperh->err_cbk(hperh);
}
@ -1793,29 +1679,25 @@ static void spi_dma_recv_cplt(void *arg)
ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE);
hperh->state = SPI_STATE_READY;
if (hperh->init.crc_calc)
{
if (hperh->init.crc_calc) {
if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK)
hperh->err_code |= SPI_ERROR_FLAG;
tmp = hperh->perh->DATA;
UNUSED(tmp);
if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET)
{
if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) {
SET_BIT(hperh->err_code, SPI_ERROR_CRC);
SPI_CRC_RESET(hperh);
ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
}
}
if (hperh->err_code == SPI_ERROR_NONE)
{
if (hperh->err_code == SPI_ERROR_NONE) {
if (hperh->rx_cplt_cbk)
hperh->rx_cplt_cbk(hperh);
}
else
{
else {
if (hperh->err_cbk)
hperh->err_cbk(hperh);
}
@ -1834,16 +1716,14 @@ static void spi_dma_send_recv_cplt(void *arg)
uint16_t delay;
spi_handle_t *hperh = (spi_handle_t *)arg;
if (hperh->init.crc_calc)
{
if (hperh->init.crc_calc) {
if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK)
hperh->err_code |= SPI_ERROR_FLAG;
tmp = hperh->perh->DATA;
UNUSED(tmp);
if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET)
{
if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) {
SET_BIT(hperh->err_code, SPI_ERROR_CRC);
ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
}
@ -1860,13 +1740,11 @@ static void spi_dma_send_recv_cplt(void *arg)
hperh->rx_count = 0;
hperh->state = SPI_STATE_READY;
if (hperh->err_code == SPI_ERROR_NONE)
{
if (hperh->err_code == SPI_ERROR_NONE) {
if (hperh->tx_rx_cplt_cbk)
hperh->tx_rx_cplt_cbk(hperh);
}
else
{
else {
if (hperh->err_cbk)
hperh->err_cbk(hperh);
}

641
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_timer.c
View File

File diff suppressed because it is too large Load Diff

15
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_trng.c
View File

@ -76,6 +76,8 @@ ald_status_t ald_trng_init(trng_handle_t *hperh)
assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width));
assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type));
assert_param(IS_TRNG_ADJC(hperh->init.adjc));
assert_param(IS_FUNC_STATE(hperh->init.posten));
assert_param(IS_TRNG_T_START(hperh->init.t_start));
__LOCK(hperh);
trng_reset(hperh);
@ -267,32 +269,25 @@ void trng_reset(trng_handle_t *hperh)
*/
void ald_trng_irq_handler(trng_handle_t *hperh)
{
if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET)
{
if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET) {
hperh->state = TRNG_STATE_ERROR;
ald_trng_clear_flag_status(hperh, TRNG_IF_SERR);
if (hperh->err_cplt_cbk)
hperh->err_cplt_cbk(hperh);
return;
}
if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET)
{
if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET) {
hperh->data = hperh->perh->DR;
hperh->state = TRNG_STATE_READY;
ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD);
if (hperh->trng_cplt_cbk)
hperh->trng_cplt_cbk(hperh);
}
if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET)
{
if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET) {
hperh->state = TRNG_STATE_BUSY;
ald_trng_clear_flag_status(hperh, TRNG_IF_START);
if (hperh->init_cplt_cbk)
hperh->init_cplt_cbk(hperh);
}

74
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_tsense.c
View File

@ -61,25 +61,38 @@ tsense_cbk __tsense_cbk;
/**
* @brief Initializes the TSENSE according to the specified
* parameters in the tsense_init_t.
* @param init: Pointer to a tsense_init_t structure that contains
* the configuration information.
* @retval None
*/
void ald_tsense_init(tsense_init_t *init)
void ald_tsense_init(void)
{
assert_param(IS_TSENSE_UPDATE_CYCLE(init->cycle));
assert_param(IS_TSENSE_OUTPUT_MODE(init->mode));
uint16_t tempt, temptinv;
uint32_t tscic, tscicinv;
TSENSE_UNLOCK();
TSENSE->CR = 0;
MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, init->cycle << TSENSE_CR_TSU_POSS);
MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, init->mode << TSENSE_CR_TOM_POSS);
MODIFY_REG(TSENSE->CR, TSENSE_CR_CTN_MSK, init->ctn << TSENSE_CR_CTN_POS);
MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, init->psc << TSENSE_PSR_PRS_POSS);
TSENSE_LOCK();
MODIFY_REG(TSENSE->CR, TSENSE_CR_CTN_MSK, 0x1 << TSENSE_CR_CTN_POS);
MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, 0x4 << TSENSE_CR_TSU_POSS);
MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, 0x3 << TSENSE_CR_TOM_POSS);
MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, 0x1 << TSENSE_PSR_PRS_POSS);
TSENSE->HTGR = 0x88F18;
TSENSE->LTGR = 0x85C39;
tempt = *(volatile uint16_t *)0x40348;
temptinv = *(volatile uint16_t *)0x4034A;
tscic = *(volatile uint32_t *)0x40350;
tscicinv = *(volatile uint32_t *)0x40358;
if ((tempt == (uint16_t)(~temptinv)) && (tscic == (~tscicinv))) {
TSENSE->TBDR = tempt;
TSENSE->TCALBDR = (tscic & 0x1FFFFFF) >> 6;
}
else {
TSENSE->TBDR = 0x1E00;
TSENSE->TCALBDR = 0x1FE70;
}
TSENSE_LOCK();
return;
}
@ -95,16 +108,13 @@ void ald_tsense_source_select(tsense_source_sel_t sel)
BKPC_UNLOCK();
MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS);
if (sel == TSENSE_SOURCE_LOSC)
{
if (sel == TSENSE_SOURCE_LOSC) {
SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);
}
else if (sel == TSENSE_SOURCE_LRC)
{
else if (sel == TSENSE_SOURCE_LRC) {
SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);
}
else
{
else {
; /* do nothing */
}
@ -149,17 +159,30 @@ ald_status_t ald_tsense_get_value(uint16_t *tsense)
while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000));
if (tmp >= 1000000)
if (tmp >= 1000000) {
TSENSE_UNLOCK();
CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
TSENSE_LOCK();
return TIMEOUT;
}
TSENSE_UNLOCK();
SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
TSENSE_LOCK();
if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK))
if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) {
TSENSE_UNLOCK();
CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
TSENSE_LOCK();
return ERROR;
}
*tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS);
TSENSE_UNLOCK();
CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
TSENSE_LOCK();
return OK;
}
@ -191,11 +214,17 @@ void ald_tsense_irq_handler(void)
SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
TSENSE_LOCK();
if (__tsense_cbk == NULL)
if (__tsense_cbk == NULL) {
TSENSE_UNLOCK();
CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
TSENSE_LOCK();
return;
}
if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK))
{
if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) {
TSENSE_UNLOCK();
CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
TSENSE_LOCK();
__tsense_cbk(0, ERROR);
return;
}
@ -204,6 +233,7 @@ void ald_tsense_irq_handler(void)
TSENSE_UNLOCK();
SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
TSENSE_LOCK();
return;
}

78
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_uart.c
View File

@ -183,8 +183,7 @@ static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, fla
tick = ald_get_tick();
/* Waiting for flag */
while ((ald_uart_get_status(hperh, flag)) != status)
{
while ((ald_uart_get_status(hperh, flag)) != status) {
if (((ald_get_tick()) - tick) > timeout)
return TIMEOUT;
}
@ -204,8 +203,7 @@ static ald_status_t __uart_send_by_it(uart_handle_t *hperh)
WRITE_REG(hperh->perh->TBR, (uint8_t)(*hperh->tx_buf++ & 0x00FF));
if (--hperh->tx_count == 0)
{
if (--hperh->tx_count == 0) {
ald_uart_clear_flag_status(hperh, UART_IF_TC);
ald_uart_interrupt_config(hperh, UART_IT_TXS, DISABLE);
ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE);
@ -226,7 +224,6 @@ static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh)
ald_uart_interrupt_config(hperh, UART_IT_TC, DISABLE);
CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
if (hperh->tx_cplt_cbk)
hperh->tx_cplt_cbk(hperh);
@ -245,8 +242,7 @@ static ald_status_t __uart_recv_by_it(uart_handle_t *hperh)
*hperh->rx_buf++ = (uint8_t)(hperh->perh->RBR & 0xFF);
if (--hperh->rx_count == 0)
{
if (--hperh->rx_count == 0) {
ald_uart_interrupt_config(hperh, UART_IT_RXRD, DISABLE);
CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
@ -367,7 +363,6 @@ void ald_uart_init(uart_handle_t *hperh)
if (hperh->init.fctl)
SET_BIT(hperh->perh->MCR, UART_MCR_RTSCTRL_MSK);
if (hperh->init.mode == UART_MODE_IrDA)
SET_BIT(hperh->perh->LCR, UART_LCR_RXINV_MSK);
@ -475,10 +470,8 @@ ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, ui
hperh->tx_size = size;
hperh->tx_count = size;
while (hperh->tx_count-- > 0)
{
if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK)
{
while (hperh->tx_count-- > 0) {
if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = UART_STATE_READY;
return TIMEOUT;
@ -487,8 +480,7 @@ ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, ui
WRITE_REG(hperh->perh->TBR, (*buf++ & 0xFF));
}
if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK)
{
if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = UART_STATE_READY;
return TIMEOUT;
@ -515,7 +507,7 @@ ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, ui
if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
@ -526,10 +518,8 @@ ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, ui
hperh->rx_size = size;
hperh->rx_count = size;
while (hperh->rx_count-- > 0)
{
if (uart_wait_flag(hperh, UART_STATUS_DR, SET, timeout) != OK)
{
while (hperh->rx_count-- > 0) {
if (uart_wait_flag(hperh, UART_STATUS_DR, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = UART_STATE_READY;
return TIMEOUT;
@ -558,7 +548,7 @@ ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t si
if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
@ -571,14 +561,12 @@ ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t si
__UNLOCK(hperh);
if (((ald_uart_get_status(hperh, UART_STATUS_TBEM)) == SET)
&& ((ald_uart_get_flag_status(hperh, UART_IF_TXS)) == RESET))
{
&& ((ald_uart_get_flag_status(hperh, UART_IF_TXS)) == RESET)) {
WRITE_REG(hperh->perh->TBR, (*hperh->tx_buf++ & 0xFF));
--hperh->tx_count;
}
if (hperh->tx_count == 0)
{
if (hperh->tx_count == 0) {
ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE);
return OK;
}
@ -601,7 +589,7 @@ ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t si
if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
@ -631,7 +619,7 @@ ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t s
if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
@ -660,8 +648,7 @@ ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t s
hperh->hdmatx.config.burst = ENABLE;
hperh->hdmatx.config.channel = channel;
if (hperh->init.mode == UART_MODE_RS485)
{
if (hperh->init.mode == UART_MODE_RS485) {
hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD;
hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
}
@ -729,8 +716,7 @@ ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t s
hperh->hdmarx.config.burst = ENABLE;
hperh->hdmarx.config.channel = channel;
if (hperh->init.mode == UART_MODE_RS485)
{
if (hperh->init.mode == UART_MODE_RS485) {
hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD;
hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD;
}
@ -816,29 +802,25 @@ void ald_uart_irq_handler(uart_handle_t *hperh)
hperh->err_code |= UART_ERROR_ORE;
/* Receive */
if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RXRD)) != RESET)
{
ald_uart_clear_flag_status(hperh, UART_IF_RXRD);
if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RXRD)) != RESET) {
__uart_recv_by_it(hperh);
ald_uart_clear_flag_status(hperh, UART_IF_RXRD);
}
/* Transmit */
if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TXS)) != RESET)
{
ald_uart_clear_flag_status(hperh, UART_IF_TXS);
if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TXS)) != RESET) {
__uart_send_by_it(hperh);
ald_uart_clear_flag_status(hperh, UART_IF_TXS);
}
/* End Transmit */
if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TC)) != RESET)
{
ald_uart_clear_flag_status(hperh, UART_IF_TC);
if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TC)) != RESET) {
__uart_end_send_by_it(hperh);
ald_uart_clear_flag_status(hperh, UART_IF_TC);
}
/* Handle error state */
if (hperh->err_code != UART_ERROR_NONE)
{
if (hperh->err_code != UART_ERROR_NONE) {
hperh->state = UART_STATE_READY;
if (hperh->error_cbk)
@ -926,17 +908,15 @@ void ald_uart_dma_req_config(uart_handle_t *hperh, type_func_t state)
* @brief Configure transmit fifo parameters.
* @param hperh: Pointer to a uart_handle_t structure.
* @param config: Transmit fifo trigger level.
* @param level: Transmit fifo level.
* @retval None
*/
void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level)
void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config)
{
assert_param(IS_UART_ALL(hperh->perh));
assert_param(IS_UART_TXFIFO_TYPE(config));
SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK);
MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, config << UART_FCR_TXTL_POSS);
MODIFY_REG(hperh->perh->FCR, UART_FCR_TXFL_MSK, level << UART_FCR_TXFL_POSS);
SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK);
return;
@ -946,17 +926,15 @@ void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t
* @brief Configure receive fifo parameters.
* @param hperh: Pointer to a uart_handle_t structure.
* @param config: Receive fifo trigger level.
* @param level: Receive fifo level.
* @retval None
*/
void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level)
void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config)
{
assert_param(IS_UART_ALL(hperh->perh));
assert_param(IS_UART_RXFIFO_TYPE(config));
SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK);
MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, config << UART_FCR_RXTL_POSS);
MODIFY_REG(hperh->perh->FCR, UART_FCR_RXFL_MSK, level << UART_FCR_RXFL_POSS);
SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK);
return;
@ -1027,16 +1005,14 @@ ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint3
SET_BIT(hperh->state, UART_STATE_TX_MASK);
if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK)
{
if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) {
hperh->state = UART_STATE_READY;
return TIMEOUT;
}
WRITE_REG(hperh->perh->TBR, (addr | 0x100));
if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK)
{
if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) {
hperh->state = UART_STATE_READY;
return TIMEOUT;
}

341
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_usart.c
View File

@ -173,7 +173,7 @@ uint8_t __frame_mode = 0;
/** @addtogroup USART_Private_Functions USART Private Functions
* @{
*/
static void usart_set_config(usart_handle_t *hperh);
static void usart_set_config (usart_handle_t *hperh);
static ald_status_t __usart_send_by_it(usart_handle_t *hperh);
static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh);
static ald_status_t __usart_recv_by_it(usart_handle_t *hperh);
@ -181,9 +181,9 @@ static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh);
static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh);
static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh);
#ifdef ALD_DMA
static void usart_dma_send_cplt(void *arg);
static void usart_dma_recv_cplt(void *arg);
static void usart_dma_error(void *arg);
static void usart_dma_send_cplt(void *arg);
static void usart_dma_recv_cplt(void *arg);
static void usart_dma_error(void *arg);
#endif
static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout);
/**
@ -275,7 +275,6 @@ ald_status_t ald_usart_init(usart_handle_t *hperh)
assert_param(IS_USART(hperh->perh));
assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl));
assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length));
assert_param(IS_FUNC_STATE(hperh->init.over_sampling));
ald_usart_reset(hperh);
hperh->state = USART_STATE_BUSY;
@ -309,7 +308,6 @@ ald_status_t ald_usart_half_duplex_init(usart_handle_t *hperh)
{
assert_param(IS_USART(hperh->perh));
assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length));
assert_param(IS_FUNC_STATE(hperh->init.over_sampling));
ald_usart_reset(hperh);
hperh->state = USART_STATE_BUSY;
@ -349,7 +347,6 @@ ald_status_t ald_usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr,
assert_param(IS_USART_WAKEUP(wakeup));
assert_param(IS_USART_ADDRESS(addr));
assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length));
assert_param(IS_FUNC_STATE(hperh->init.over_sampling));
ald_usart_reset(hperh);
hperh->state = USART_STATE_BUSY;
@ -385,7 +382,6 @@ ald_status_t ald_usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *ini
{
assert_param(IS_USART(hperh->perh));
assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length));
assert_param(IS_FUNC_STATE(hperh->init.over_sampling));
ald_usart_reset(hperh);
hperh->state = USART_STATE_BUSY;
@ -498,35 +494,28 @@ ald_status_t ald_usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size,
hperh->tx_size = size;
hperh->tx_count = size;
while (hperh->tx_count-- > 0)
{
if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK)
{
while (hperh->tx_count-- > 0) {
if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = USART_STATE_READY;
return TIMEOUT;
}
if (hperh->init.word_length == USART_WORD_LENGTH_9B)
{
if (hperh->init.parity == USART_PARITY_NONE)
{
if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
if (hperh->init.parity == USART_PARITY_NONE) {
WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & (uint16_t)0x01FF));
buf += 2;
}
else
{
else {
WRITE_REG(hperh->perh->DATA, *buf++);
}
}
else
{
else {
WRITE_REG(hperh->perh->DATA, *buf++);
}
}
if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK)
{
if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = USART_STATE_READY;
return TIMEOUT;
@ -552,7 +541,7 @@ ald_status_t ald_usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size,
if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
@ -562,30 +551,24 @@ ald_status_t ald_usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size,
hperh->rx_size = size;
hperh->rx_count = size;
while (hperh->rx_count-- > 0)
{
if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK)
{
while (hperh->rx_count-- > 0) {
if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = USART_STATE_READY;
return TIMEOUT;
}
if (hperh->init.word_length == USART_WORD_LENGTH_9B)
{
if (hperh->init.parity == USART_PARITY_NONE)
{
if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
if (hperh->init.parity == USART_PARITY_NONE) {
*(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF);
buf += 2;
}
else
{
else {
*buf = (uint8_t)(hperh->perh->DATA & 0xFF);
buf += 1;
}
}
else
{
else {
if (hperh->init.parity == USART_PARITY_NONE)
*buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
else
@ -612,14 +595,14 @@ ald_status_t ald_usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t
if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
SET_BIT(hperh->state, USART_STATE_TX_MASK);
hperh->tx_buf = buf;
hperh->rx_size = size;
hperh->tx_size = size;
hperh->tx_count = size;
hperh->err_code = USART_ERROR_NONE;
@ -642,7 +625,7 @@ ald_status_t ald_usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t
if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
@ -674,7 +657,7 @@ ald_status_t ald_usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uin
if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
@ -709,7 +692,7 @@ ald_status_t ald_usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t
if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
@ -741,8 +724,7 @@ ald_status_t ald_usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t
hperh->hdmatx.config.channel = channel;
if ((hperh->init.word_length == USART_WORD_LENGTH_9B)
&& (hperh->init.parity == USART_PARITY_NONE))
{
&& (hperh->init.parity == USART_PARITY_NONE)) {
hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD;
hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
}
@ -772,7 +754,7 @@ ald_status_t ald_usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t
if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX))
return BUSY;
if ((buf == NULL) || (size == 0))
if ((buf == NULL ) || (size == 0))
return ERROR;
__LOCK(hperh);
@ -803,8 +785,7 @@ ald_status_t ald_usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t
hperh->hdmarx.config.channel = channel;
if ((hperh->init.word_length == USART_WORD_LENGTH_9B)
&& (hperh->init.parity == USART_PARITY_NONE))
{
&& (hperh->init.parity == USART_PARITY_NONE)) {
hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD;
hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD;
}
@ -903,28 +884,23 @@ ald_status_t ald_usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t s
hperh->err_code = USART_ERROR_NONE;
hperh->state = USART_STATE_BUSY_TX;
while (hperh->tx_count-- > 0)
{
if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK)
{
while (hperh->tx_count-- > 0) {
if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = USART_STATE_READY;
return TIMEOUT;
}
if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE))
{
if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) {
WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & 0x1FF));
buf += 2;
}
else
{
else {
WRITE_REG(hperh->perh->DATA, *buf++);
}
}
if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK)
{
if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = USART_STATE_READY;
return TIMEOUT;
@ -960,42 +936,34 @@ ald_status_t ald_usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t s
hperh->err_code = USART_ERROR_NONE;
hperh->state = USART_STATE_BUSY_RX;
while (hperh->rx_count-- > 0)
{
if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK)
{
while (hperh->rx_count-- > 0) {
if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = USART_STATE_READY;
return TIMEOUT;
}
if (hperh->init.word_length == USART_WORD_LENGTH_9B)
{
if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF));
if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK)
{
if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = USART_STATE_READY;
return TIMEOUT;
}
if (hperh->init.parity == USART_PARITY_NONE)
{
if (hperh->init.parity == USART_PARITY_NONE) {
*(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF);
buf += 2;
}
else
{
else {
*buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
}
}
else
{
else {
WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0xFF));
if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK)
{
if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = USART_STATE_READY;
return TIMEOUT;
@ -1041,52 +1009,42 @@ ald_status_t ald_usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, ui
hperh->err_code = USART_ERROR_NONE;
hperh->state = USART_STATE_BUSY_RX;
while (hperh->tx_count-- > 0)
{
while (hperh->tx_count-- > 0) {
--hperh->rx_count;
if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK)
{
if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = USART_STATE_READY;
return TIMEOUT;
}
if (hperh->init.word_length == USART_WORD_LENGTH_9B)
{
if (hperh->init.parity == USART_PARITY_NONE)
{
if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
if (hperh->init.parity == USART_PARITY_NONE) {
WRITE_REG(hperh->perh->DATA, (*(uint16_t *)tx_buf & 0x1FF));
tx_buf += 2;
}
else
{
else {
WRITE_REG(hperh->perh->DATA, *tx_buf++);
}
if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK)
{
if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = USART_STATE_READY;
return TIMEOUT;
}
if (hperh->init.parity == USART_PARITY_NONE)
{
if (hperh->init.parity == USART_PARITY_NONE) {
*(uint16_t *)rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF);
rx_buf += 2;
}
else
{
else {
*rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
}
}
else
{
else {
WRITE_REG(hperh->perh->DATA, *tx_buf++);
if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK)
{
if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) {
__UNLOCK(hperh);
hperh->state = USART_STATE_READY;
return TIMEOUT;
@ -1262,8 +1220,7 @@ ald_status_t ald_usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uin
hperh->hdmatx.config.channel = channel;
if ((hperh->init.word_length == USART_WORD_LENGTH_9B)
&& (hperh->init.parity == USART_PARITY_NONE))
{
&& (hperh->init.parity == USART_PARITY_NONE)) {
hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD;
hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
}
@ -1308,7 +1265,6 @@ ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uin
if (hperh->hdmatx.perh == NULL)
hperh->hdmatx.perh = DMA0;
if (hperh->hdmarx.perh == NULL)
hperh->hdmarx.perh = DMA0;
@ -1330,8 +1286,7 @@ ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uin
hperh->hdmarx.config.channel = rx_channel;
if ((hperh->init.word_length == USART_WORD_LENGTH_9B)
&& (hperh->init.parity == USART_PARITY_NONE))
{
&& (hperh->init.parity == USART_PARITY_NONE)) {
hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD;
hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD;
}
@ -1353,8 +1308,7 @@ ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uin
hperh->hdmatx.config.channel = tx_channel;
if ((hperh->init.word_length == USART_WORD_LENGTH_9B)
&& (hperh->init.parity == USART_PARITY_NONE))
{
&& (hperh->init.parity == USART_PARITY_NONE)) {
hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD;
hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
}
@ -1401,7 +1355,6 @@ ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_
if (hperh->hdmatx.perh == NULL)
hperh->hdmatx.perh = DMA0;
if (hperh->hdmarx.perh == NULL)
hperh->hdmarx.perh = DMA0;
@ -1427,8 +1380,7 @@ ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_
hperh->hdmarx.config.channel = rx_channel;
if ((hperh->init.word_length == USART_WORD_LENGTH_9B)
&& (hperh->init.parity == USART_PARITY_NONE))
{
&& (hperh->init.parity == USART_PARITY_NONE)) {
hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD;
hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD;
}
@ -1447,8 +1399,7 @@ ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_
hperh->hdmatx.config.channel = tx_channel;
if ((hperh->init.word_length == USART_WORD_LENGTH_9B)
&& (hperh->init.parity == USART_PARITY_NONE))
{
&& (hperh->init.parity == USART_PARITY_NONE)) {
hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD;
hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
}
@ -1483,21 +1434,17 @@ ald_status_t ald_usart_dma_pause(usart_handle_t *hperh)
{
__LOCK(hperh);
if (hperh->state == USART_STATE_BUSY_TX)
{
if (hperh->state == USART_STATE_BUSY_TX) {
CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
}
else if (hperh->state == USART_STATE_BUSY_RX)
{
else if (hperh->state == USART_STATE_BUSY_RX) {
CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK);
}
else if (hperh->state == USART_STATE_BUSY_TX_RX)
{
else if (hperh->state == USART_STATE_BUSY_TX_RX) {
CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK);
}
else
{
else {
__UNLOCK(hperh);
return ERROR;
}
@ -1516,23 +1463,19 @@ ald_status_t ald_usart_dma_resume(usart_handle_t *hperh)
{
__LOCK(hperh);
if (hperh->state == USART_STATE_BUSY_TX)
{
if (hperh->state == USART_STATE_BUSY_TX) {
SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
}
else if (hperh->state == USART_STATE_BUSY_RX)
{
else if (hperh->state == USART_STATE_BUSY_RX) {
USART_CLEAR_OREFLAG(hperh);
SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK);
}
else if (hperh->state == USART_STATE_BUSY_TX_RX)
{
else if (hperh->state == USART_STATE_BUSY_TX_RX) {
USART_CLEAR_OREFLAG(hperh);
SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK);
}
else
{
else {
__UNLOCK(hperh);
return ERROR;
}
@ -1570,61 +1513,50 @@ void ald_usart_irq_handler(usart_handle_t *hperh)
/* Handle parity error */
flag = ald_usart_get_flag_status(hperh, USART_FLAG_PE);
source = ald_usart_get_it_status(hperh, USART_IT_PE);
if ((flag != RESET) && (source != RESET))
hperh->err_code |= USART_ERROR_PE;
/* Handle frame error */
flag = ald_usart_get_flag_status(hperh, USART_FLAG_FE);
source = ald_usart_get_it_status(hperh, USART_IT_ERR);
if ((flag != RESET) && (source != RESET))
hperh->err_code |= USART_ERROR_FE;
/* Handle noise error */
flag = ald_usart_get_flag_status(hperh, USART_FLAG_NE);
if ((flag != RESET) && (source != RESET))
hperh->err_code |= USART_ERROR_NE;
/* Handle overrun error */
flag = ald_usart_get_flag_status(hperh, USART_FLAG_ORE);
if ((flag != RESET) && (source != RESET))
hperh->err_code |= USART_ERROR_ORE;
/* Handle idle error */
flag = ald_usart_get_flag_status(hperh, USART_FLAG_IDLE);
source = ald_usart_get_it_status(hperh, USART_IT_IDLE);
if ((flag != RESET) && (source != RESET))
__usart_recv_frame_cplt(hperh);
/* Handle asynchronous */
if (READ_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK) == 0)
{
if (READ_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK) == 0) {
/* Receiver */
flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE);
source = ald_usart_get_it_status(hperh, USART_IT_RXNE);
if ((flag != RESET) && (source != RESET))
__usart_recv_by_it(hperh);
/* Transmitter */
flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE);
source = ald_usart_get_it_status(hperh, USART_IT_TXE);
if ((flag != RESET) && (source != RESET))
__usart_send_by_it(hperh);
}
else /* Handle synchronous */
{
else { /* Handle synchronous */
/* Receiver */
flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE);
source = ald_usart_get_it_status(hperh, USART_IT_RXNE);
if ((flag != RESET) && (source != RESET))
{
if ((flag != RESET) && (source != RESET)) {
if (hperh->state == USART_STATE_BUSY_RX)
__usart_recv_by_it_sync(hperh);
else
@ -1634,9 +1566,7 @@ void ald_usart_irq_handler(usart_handle_t *hperh)
/* Transmitter */
flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE);
source = ald_usart_get_it_status(hperh, USART_IT_TXE);
if ((flag != RESET) && (source != RESET))
{
if ((flag != RESET) && (source != RESET)) {
if (hperh->state == USART_STATE_BUSY_TX)
__usart_send_by_it(hperh);
else
@ -1647,13 +1577,11 @@ void ald_usart_irq_handler(usart_handle_t *hperh)
/* Handle transmitter end */
flag = ald_usart_get_flag_status(hperh, USART_FLAG_TC);
source = ald_usart_get_it_status(hperh, USART_IT_TC);
if ((flag != RESET) && (source != RESET))
__usart_end_send_by_it(hperh);
/* Handle error */
if (hperh->err_code != USART_ERROR_NONE)
{
if (hperh->err_code != USART_ERROR_NONE) {
USART_CLEAR_PEFLAG(hperh);
hperh->state = USART_STATE_READY;
@ -1827,8 +1755,7 @@ void ald_usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_
idx = (it >> 16) & 0x7;
it &= 0xFFFF;
if (state)
{
if (state) {
if (idx == 1)
SET_BIT(hperh->perh->CON0, it);
else if (idx == 2)
@ -1838,8 +1765,7 @@ void ald_usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_
else
;
}
else
{
else {
if (idx == 1)
CLEAR_BIT(hperh->perh->CON0, it);
else if (idx == 2)
@ -1932,28 +1858,23 @@ it_status_t ald_usart_get_it_status(usart_handle_t *hperh, usart_it_t it)
idx = (it >> 16) & 0x7;
it &= 0xFFFF;
if (idx == 0)
{
if (idx == 0) {
if (READ_BIT(hperh->perh->STAT, it))
status = SET;
}
else if (idx == 1)
{
else if (idx == 1) {
if (READ_BIT(hperh->perh->CON0, it))
status = SET;
}
else if (idx == 2)
{
else if (idx == 2) {
if (READ_BIT(hperh->perh->CON1, it))
status = SET;
}
else if (idx == 4)
{
else if (idx == 4) {
if (READ_BIT(hperh->perh->CON2, it))
status = SET;
}
else
{
else {
/* do nothing */
}
@ -2090,10 +2011,8 @@ static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, fl
tick = ald_get_tick();
while ((ald_usart_get_flag_status(hperh, flag)) != status)
{
if (((ald_get_tick()) - tick) > timeout)
{
while ((ald_usart_get_flag_status(hperh, flag)) != status) {
if (((ald_get_tick()) - tick) > timeout) {
ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE);
ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE);
ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE);
@ -2117,18 +2036,15 @@ static ald_status_t __usart_send_by_it(usart_handle_t *hperh)
if ((hperh->state != USART_STATE_BUSY_TX) && (hperh->state != USART_STATE_BUSY_TX_RX))
return BUSY;
if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE))
{
if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) {
WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & (uint16_t)0x01FF));
hperh->tx_buf += 2;
}
else
{
else {
WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++);
}
if (--hperh->tx_count == 0)
{
if (--hperh->tx_count == 0) {
ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE);
ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE);
}
@ -2165,20 +2081,16 @@ static ald_status_t __usart_recv_by_it(usart_handle_t *hperh)
if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX))
return BUSY;
if (hperh->init.word_length == USART_WORD_LENGTH_9B)
{
if (hperh->init.parity == USART_PARITY_NONE)
{
if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
if (hperh->init.parity == USART_PARITY_NONE) {
*(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & (uint16_t)0x01FF);
hperh->rx_buf += 2;
}
else
{
else {
*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
}
}
else
{
else {
if (hperh->init.parity == USART_PARITY_NONE)
*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
else
@ -2188,14 +2100,12 @@ static ald_status_t __usart_recv_by_it(usart_handle_t *hperh)
if (__frame_mode && ((ald_usart_get_it_status(hperh, USART_IT_IDLE)) == RESET))
ald_usart_interrupt_config(hperh, USART_IT_IDLE, ENABLE);
if (--hperh->rx_count == 0)
{
if (--hperh->rx_count == 0) {
ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE);
CLEAR_BIT(hperh->state, USART_STATE_RX_MASK);
__frame_mode = 0;
if (hperh->state == USART_STATE_READY)
{
if (hperh->state == USART_STATE_READY) {
ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE);
ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE);
}
@ -2225,8 +2135,7 @@ static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh)
__frame_mode = 0;
hperh->rx_size -= hperh->rx_count;
if (hperh->state == USART_STATE_READY)
{
if (hperh->state == USART_STATE_READY) {
ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE);
ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE);
}
@ -2250,24 +2159,20 @@ static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh)
if (hperh->state != USART_STATE_BUSY_RX)
return BUSY;
if (hperh->init.word_length == USART_WORD_LENGTH_9B)
{
if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
if (hperh->init.parity == USART_PARITY_NONE)
{
if (hperh->init.parity == USART_PARITY_NONE) {
*(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF);
hperh->rx_buf += 2;
}
else
{
else {
*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
}
if (--hperh->rx_count != 0x00)
WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF));
}
else
{
else {
if (hperh->init.parity == USART_PARITY_NONE)
*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
else
@ -2277,8 +2182,7 @@ static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh)
hperh->perh->DATA = (DUMMY_DATA & 0xFF);
}
if (hperh->rx_count == 0)
{
if (hperh->rx_count == 0) {
ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE);
ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE);
ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE);
@ -2302,24 +2206,18 @@ static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh)
if (hperh->state != USART_STATE_BUSY_TX_RX)
return BUSY;
if (hperh->tx_count != 0)
{
if (ald_usart_get_flag_status(hperh, USART_FLAG_TXE) != RESET)
{
if (hperh->init.word_length == USART_WORD_LENGTH_9B)
{
if (hperh->init.parity == USART_PARITY_NONE)
{
if (hperh->tx_count != 0) {
if (ald_usart_get_flag_status(hperh, USART_FLAG_TXE) != RESET) {
if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
if (hperh->init.parity == USART_PARITY_NONE) {
WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & 0x1FF));
hperh->tx_buf += 2;
}
else
{
else {
WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++);
}
}
else
{
else {
WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++);
}
@ -2328,24 +2226,18 @@ static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh)
}
}
if (hperh->rx_count != 0)
{
if (ald_usart_get_flag_status(hperh, USART_FLAG_RXNE) != RESET)
{
if (hperh->init.word_length == USART_WORD_LENGTH_9B)
{
if (hperh->init.parity == USART_PARITY_NONE)
{
if (hperh->rx_count != 0) {
if (ald_usart_get_flag_status(hperh, USART_FLAG_RXNE) != RESET) {
if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
if (hperh->init.parity == USART_PARITY_NONE) {
*(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF);
hperh->rx_buf += 2;
}
else
{
else {
*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
}
}
else
{
else {
if (hperh->init.parity == USART_PARITY_NONE)
*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
else
@ -2356,8 +2248,7 @@ static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh)
}
}
if (hperh->rx_count == 0)
{
if (hperh->rx_count == 0) {
ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE);
ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE);
ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE);
@ -2377,7 +2268,7 @@ static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh)
* the configuration information for the specified USART module.
* @retval None
*/
static void usart_set_config(usart_handle_t *hperh)
static void usart_set_config (usart_handle_t *hperh)
{
uint32_t tmp;
uint32_t integer;
@ -2412,44 +2303,24 @@ static void usart_set_config(usart_handle_t *hperh)
MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS);
MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS);
if (hperh->init.over_sampling)
SET_BIT(hperh->perh->CON0, (1 << 15));
/* Determine the integer part */
if (READ_BIT(hperh->perh->CON0, (1 << 15)))
{
/* Integer part computing in case Oversampling mode is 8 Samples */
integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud)));
}
else
{
/* Integer part computing in case Oversampling mode is 16 Samples */
integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud)));
}
tmp = (integer / 100) << 4;
/* Determine the fractional part */
fractional = integer - (100 * (tmp >> 4));
/* Implement the fractional part in the register */
if (READ_BIT(hperh->perh->CON0, (1 << 15)))
tmp |= ((((fractional * 8) + 50) / 100) & ((uint8_t)0x07));
else
tmp |= ((((fractional * 16) + 50) / 100) & ((uint8_t)0x0F));
WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp);
return;
}
/**
* @}
*/
#endif /* ALD_USART */
/**
* @}
*/
/**
* @}
*/

47
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/utils.c
View File

@ -14,6 +14,7 @@
*********************************************************************************
*/
#include <string.h>
#include "utils.h"
#include "ald_dma.h"
#include "ald_cmu.h"
@ -185,6 +186,9 @@ void ald_systick_interval_select(systick_interval_t value)
(+) Configure the interrupt
(+) Provide system tick value
(+) Get CPU ID
(+) Get UID
(+) Get CHIPID
@endverbatim
* @{
*/
@ -253,8 +257,7 @@ __weak void ald_delay_ms(__IO uint32_t delay)
{
uint32_t tick, __delay;
switch (__systick_interval)
{
switch (__systick_interval) {
case SYSTICK_INTERVAL_1MS:
__delay = delay;
break;
@ -336,18 +339,14 @@ ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, ui
assert_param(timeout > 0);
if (status == SET)
{
while (!(IS_BIT_SET(*reg, bit)))
{
if (status == SET) {
while (!(IS_BIT_SET(*reg, bit))) {
if (((ald_get_tick()) - tick) > timeout)
return TIMEOUT;
}
}
else
{
while ((IS_BIT_SET(*reg, bit)))
{
else {
while ((IS_BIT_SET(*reg, bit))) {
if (((ald_get_tick()) - tick) > timeout)
return TIMEOUT;
}
@ -370,13 +369,11 @@ void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status)
assert_param(IS_FUNC_STATE(status));
assert_param(IS_PRIO(prio));
if (status == ENABLE)
{
if (status == ENABLE) {
NVIC_SetPriority(irq, prio);
NVIC_EnableIRQ(irq);
}
else
{
else {
NVIC_DisableIRQ(irq);
}
@ -404,6 +401,28 @@ uint32_t ald_mcu_get_cpu_id(void)
return SCB->CPUID;
}
/**
* @brief Get the UID.
* @param buf: Pointer to UID, len: 12Bytes(96-bits)
* @retval None
*/
void ald_mcu_get_uid(uint8_t *buf)
{
memcpy(&buf[0], (void *)MCU_UID0_ADDR, 4);
memcpy(&buf[4], (void *)MCU_UID1_ADDR, 4);
memcpy(&buf[8], (void *)MCU_UID2_ADDR, 4);
return;
}
/**
* @brief Get the CHIPID
* @retval CHPID
*/
uint32_t ald_mcu_get_chipid(void)
{
return (uint32_t)*(uint32_t *)MCU_CHIPID_ADDR;
}
/**
* @}
*/

968
bsp/essemi/es32f0334/project.uvoptx
View File

@ -73,7 +73,7 @@
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
@ -101,7 +101,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>2</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>3</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -118,7 +120,7 @@
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI</Key>
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0ES32F033x.FLM -FS00 -FL040000 -FP0($$Device:ES32F0334LT$Flash\ES32F033x.FLM)</Name>
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0ES32F033x.FLM -FS00 -FL040000 -FP0($$Device:ES32F0334LT$Flash\ES32F033x.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
@ -170,7 +172,967 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Applications</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>applications\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>cpu</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\libcpu\arm\common\backtrace.c</PathWithFileName>
<FilenameWithoutPath>backtrace.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\libcpu\arm\common\div0.c</PathWithFileName>
<FilenameWithoutPath>div0.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\libcpu\arm\common\showmem.c</PathWithFileName>
<FilenameWithoutPath>showmem.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\libcpu\arm\cortex-m0\cpuport.c</PathWithFileName>
<FilenameWithoutPath>cpuport.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\libcpu\arm\cortex-m0\context_rvds.S</PathWithFileName>
<FilenameWithoutPath>context_rvds.S</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>DeviceDrivers</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\drivers\hwtimer\hwtimer.c</PathWithFileName>
<FilenameWithoutPath>hwtimer.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\drivers\i2c\i2c_core.c</PathWithFileName>
<FilenameWithoutPath>i2c_core.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
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<GroupNumber>7</GroupNumber>
<FileNumber>61</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lpuart.c</PathWithFileName>
<FilenameWithoutPath>ald_lpuart.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>62</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_pis.c</PathWithFileName>
<FilenameWithoutPath>ald_pis.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
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<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_pmu.c</PathWithFileName>
<FilenameWithoutPath>ald_pmu.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
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<GroupNumber>7</GroupNumber>
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<tvExpOptDlg>0</tvExpOptDlg>
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<PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_rmu.c</PathWithFileName>
<FilenameWithoutPath>ald_rmu.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>65</FileNumber>
<FileType>1</FileType>
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<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_rtc.c</PathWithFileName>
<FilenameWithoutPath>ald_rtc.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>66</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_smartcard.c</PathWithFileName>
<FilenameWithoutPath>ald_smartcard.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>67</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_spi.c</PathWithFileName>
<FilenameWithoutPath>ald_spi.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
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<GroupNumber>7</GroupNumber>
<FileNumber>68</FileNumber>
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<PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_timer.c</PathWithFileName>
<FilenameWithoutPath>ald_timer.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
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<RteFlg>0</RteFlg>
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</ProjectOpt>

840
bsp/essemi/es32f0334/project.uvprojx
View File

File diff suppressed because it is too large Load Diff

12
bsp/essemi/es32f0334/rtconfig.h
View File

@ -39,7 +39,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40002
#define RT_VER_NUM 0x40003
/* RT-Thread Components */
@ -76,7 +76,15 @@
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_HWTIMER
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_PIN
#define RT_USING_ADC
#define RT_USING_PWM
#define RT_USING_PM
#define RT_USING_RTC
#define RT_USING_SPI
/* Using USB */
@ -180,6 +188,8 @@
/* Offboard Peripheral Drivers */
/* Peripheral Drivers test example */
#define SOC_ES32F0334LT
#endif

8
bsp/essemi/es32f0334/template.uvoptx
View File

@ -101,7 +101,9 @@
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>2</nTsel>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>3</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -170,6 +172,10 @@
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>

5
bsp/essemi/es32f0334/template.uvprojx
View File

@ -10,11 +10,12 @@
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ES32F0334LT</Device>
<Vendor>Eastsoft</Vendor>
<PackID>Eastsoft.ES32_DFP.1.0.1</PackID>
<PackID>Eastsoft.ES32_DFP.7.2350</PackID>
<PackURL>http://www.essemi.com</PackURL>
<Cpu>IRAM(0x20000000,0x00008000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -182,6 +183,7 @@
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
@ -322,6 +324,7 @@
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>

124
bsp/essemi/es32f0654/.config
View File

@ -9,7 +9,7 @@
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
CONFIG_RT_ALIGN_SIZE=8
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
@ -64,7 +64,7 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
CONFIG_RT_VER_NUM=0x40002
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@ -114,19 +114,31 @@ CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
CONFIG_RT_USING_CAN=y
# CONFIG_RT_CAN_USING_HDR is not set
CONFIG_RT_USING_HWTIMER=y
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_I2C=y
# CONFIG_RT_I2C_DEBUG is not set
CONFIG_RT_USING_I2C_BITOPS=y
# CONFIG_RT_I2C_BITOPS_DEBUG is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_PWM is not set
CONFIG_RT_USING_ADC=y
# CONFIG_RT_USING_DAC is not set
CONFIG_RT_USING_PWM=y
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
CONFIG_RT_USING_PM=y
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
@ -192,10 +204,15 @@ CONFIG_RT_USING_PIN=y
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
@ -222,6 +239,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
@ -234,8 +252,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
@ -249,6 +269,16 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
#
# security packages
@ -256,6 +286,8 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
@ -272,6 +304,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_HELIX is not set
#
# tools packages
@ -286,6 +319,13 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
#
# system packages
@ -296,6 +336,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@ -304,6 +345,15 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_PPOOL is not set
#
# peripheral libraries and drivers
@ -311,6 +361,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
@ -319,6 +370,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
@ -332,9 +387,27 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_LCD_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
#
# miscellaneous packages
@ -369,8 +442,14 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
CONFIG_SOC_ES32F0654LT=y
#
@ -402,6 +481,11 @@ CONFIG_BSP_USING_UART2=y
# CONFIG_BSP_USING_I2C0 is not set
# CONFIG_BSP_USING_I2C1 is not set
#
# CAN Drivers
#
# CONFIG_BSP_USING_CAN is not set
#
# PWM Drivers
#
@ -414,6 +498,7 @@ CONFIG_BSP_USING_UART2=y
# HWtimer Drivers
#
# CONFIG_BSP_USING_HWTIMER0 is not set
# CONFIG_BSP_USING_HWTIMER1 is not set
# CONFIG_BSP_USING_HWTIMER2 is not set
# CONFIG_BSP_USING_HWTIMER3 is not set
@ -440,3 +525,18 @@ CONFIG_BSP_USING_UART2=y
#
# Offboard Peripheral Drivers
#
#
# Peripheral Drivers test example
#
# CONFIG_BSP_USING_EXAMPLE_ADC_VOL is not set
# CONFIG_BSP_USING_EXAMPLE_HWTIMER is not set
# CONFIG_BSP_USING_EXAMPLE_I2C is not set
# CONFIG_BSP_USING_EXAMPLE_LED_BLINK is not set
# CONFIG_BSP_USING_EXAMPLE_PIN_BEEP is not set
# CONFIG_BSP_USING_EXAMPLE_PWM_LED is not set
# CONFIG_BSP_USING_EXAMPLE_RTC is not set
# CONFIG_BSP_USING_EXAMPLE_SPI is not set
# CONFIG_BSP_USING_EXAMPLE_UART is not set
# CONFIG_BSP_USING_EXAMPLE_CAN is not set
# CONFIG_BSP_USING_EXAMPLE_PM is not set

20
bsp/essemi/es32f0654/README.md
View File

@ -90,6 +90,24 @@ msh >
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
a）如果需要使用内核用例，先配置rt-thread内核，如图：
![kernel_config](figures/k_conf.jpg)
然后配置内核用例，如图：
![kernel_sample](figures/k_ex.jpg)
b）如果需要使用驱动用例：先使能驱动，如图：
![driver_config](figures/d_conf.jpg)
然后配置驱动用例，如图：
![driver_sample](figures/d_ex.jpg)
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
@ -98,7 +116,7 @@ msh >
## 4. 联系人信息
- [wangyongquan](https://github.com/wangyq2018)
- [liuhongyan](https://gitee.com/liuhongyan98)
## 5. 参考

49
bsp/essemi/es32f0654/drivers/Kconfig
View File

@ -148,4 +148,53 @@ menu "Hardware Drivers Config"
endmenu
menu "Peripheral Drivers test example"
config BSP_USING_EXAMPLE_ADC_VOL
bool "BSP_USING_EXAMPLE_ADC_VOL"
default n
config BSP_USING_EXAMPLE_HWTIMER
bool "BSP_USING_EXAMPLE_HWTIMER"
default n
config BSP_USING_EXAMPLE_I2C
bool "BSP_USING_EXAMPLE_I2C"
default n
config BSP_USING_EXAMPLE_LED_BLINK
bool "BSP_USING_EXAMPLE_LED_BLINK"
default y
config BSP_USING_EXAMPLE_PIN_BEEP
bool "BSP_USING_EXAMPLE_PIN_BEEP"
default y
config BSP_USING_EXAMPLE_PWM_LED
bool "BSP_USING_EXAMPLE_PWM_LED"
default n
config BSP_USING_EXAMPLE_RTC
bool "BSP_USING_EXAMPLE_RTC"
default n
config BSP_USING_EXAMPLE_SPI
bool "BSP_USING_EXAMPLE_SPI"
default n
config BSP_USING_EXAMPLE_UART
bool "BSP_USING_EXAMPLE_UART"
default y
config BSP_USING_EXAMPLE_CAN
bool "BSP_USING_EXAMPLE_CAN"
default n
config BSP_USING_EXAMPLE_PM
bool "BSP_USING_EXAMPLE_PM"
default n
endmenu
endmenu

46
bsp/essemi/es32f0654/drivers/SConscript
View File

@ -2,6 +2,8 @@ from building import *
cwd = GetCurrentDir()
objs = []
# add the general drivers.
src = Split('''
board.c
@ -53,5 +55,47 @@ if GetDepend(['BSP_USING_ADC']):
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
objs = objs + group
src = []
cwd = GetCurrentDir()
include_path = [cwd]
if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'):
src += ['bsp_driver_example/adc_vol_sample.c']
if GetDepend('BSP_USING_EXAMPLE_HWTIMER'):
src += ['bsp_driver_example/hwtimer_sample.c']
if GetDepend('BSP_USING_EXAMPLE_I2C'):
src += ['bsp_driver_example/i2c_sample.c']
if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'):
src += ['bsp_driver_example/led_blink_sample.c']
if GetDepend('BSP_USING_EXAMPLE_PIN_BEEP'):
src += ['bsp_driver_example/pin_beep_sample.c']
if GetDepend('BSP_USING_EXAMPLE_PWM_LED'):
src += ['bsp_driver_example/pwm_led_sample.c']
if GetDepend('BSP_USING_EXAMPLE_RTC'):
src += ['bsp_driver_example/rtc_sample.c']
if GetDepend('BSP_USING_EXAMPLE_UART'):
src += ['bsp_driver_example/uart_sample.c']
if GetDepend('BSP_USING_EXAMPLE_SPI'):
src += ['bsp_driver_example/spi_sample.c']
if GetDepend('BSP_USING_EXAMPLE_CAN'):
src += ['bsp_driver_example/can_sample.c']
if GetDepend('BSP_USING_EXAMPLE_PM'):
src += ['bsp_driver_example/pm_sample.c']
group = DefineGroup('bsp-drivers-test-samples', src, depend = [''], CPPPATH = include_path)
objs = objs + group
Return('objs')
Return('group')

52
bsp/essemi/es32f0654/drivers/bsp_driver_example/.gitignore vendored Normal file
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@ -0,0 +1,52 @@
# Prerequisites
*.d
# Object files
*.o
*.ko
*.obj
*.elf
# Linker output
*.ilk
*.map
*.exp
# Precompiled Headers
*.gch
*.pch
# Libraries
*.lib
*.a
*.la
*.lo
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
*.i*86
*.x86_64
*.hex
# Debug files
*.dSYM/
*.su
*.idb
*.pdb
# Kernel Module Compile Results
*.mod*
*.cmd
.tmp_versions/
modules.order
Module.symvers
Mkfile.old
dkms.conf

47
bsp/essemi/es32f0654/drivers/bsp_driver_example/README.md Normal file
View File

@ -0,0 +1,47 @@
# 外设驱动测试用例
## 1、介绍
这个软件包包含一些外设设备操作的例程。
### 1.1 例程说明
| 文件 | 说明 |
| ---------------- | ------------------------------- |
| adc_vol_sample.c | 使用 ADC 设备转换电压数据 |
| can_sample.c | 通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。 |
| hwtimer_sample.c | 使用 硬件定时器定时 |
| i2c_sample.c | 使用 i2c 设备进行读写 |
| pm.c | 反复进入不同程度的睡眠。 |
| led_blink_sample.c | 使用 pin 设备控制 LED 闪烁 |
| pin_beep_sample.c | 使用 pin 设备控制蜂鸣器 |
| pwm_led_sample.c | 使用 pwm 设备控制 LED 的亮度 |
| rtc_sample.c | 使用 rtc 设备设置年月日时分秒信息 |
| spi_sample.c | 使用 spi 设备进行读写 |
| uart_sample.c | 使用 serial 设备中断接收及轮询发送模式收发数据 |
### 1.2 依赖
依赖设备管理模块提供的设备驱动。
## 2、如何打开 外设驱动测试用例
使用 外设驱动测试用例 需要在 RT-Thread 的menuconfig中选择它，具体路径如下：
```
Hardware Driver Config --->
Peripheral Driver test example--->
```
## 3、使用 外设驱动测试用例
在打开 Peripheral Driver test example 后，当进行 BSP 编译时，选择的软件包相关源代码会被加入到 BSP 工程中进行编译。
## 4、注意事项
暂无。
## 5、联系方式 & 感谢
* 维护：[misonyo](https://github.com/misonyo)
* 主页：https://github.com/RT-Thread-packages/peripheral-sample

57
bsp/essemi/es32f0654/drivers/bsp_driver_example/adc_vol_sample.c Normal file
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@ -0,0 +1,57 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-29 misonyo first implementation.
*/
/*
* 程序清单： ADC 设备使用例程
* 例程导出了 adc_sample 命令到控制终端
* 命令调用格式：adc_sample
* 程序功能：通过 ADC 设备采样电压值并转换为数值。
* 示例代码参考电压为3.3V,转换位数为12位。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define ADC_DEV_NAME "adc0" /* ADC 设备名称 */
#define ADC_DEV_CHANNEL 5 /* PA1 ADC 通道 */
#define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/
#define CONVERT_BITS (1 << 12) /* 转换位数为12位 */
static int adc_vol_sample(int argc, char *argv[])
{
rt_adc_device_t adc_dev;
rt_uint32_t value, vol;
rt_err_t ret = RT_EOK;
/* 查找设备 */
adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME);
if (adc_dev == RT_NULL)
{
rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME);
return RT_ERROR;
}
/* 使能设备 */
ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
/* 读取采样值 */
value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
rt_kprintf("the value is :%d \n", value);
/* 转换为对应电压值 */
vol = value * REFER_VOLTAGE / CONVERT_BITS;
rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
/* 关闭通道 */
ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
return ret;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample);

144
bsp/essemi/es32f0654/drivers/bsp_driver_example/can_sample.c Normal file
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@ -0,0 +1,144 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-06-25 misonyo first implementation.
*/
/*
* 程序清单：这是一个 CAN 设备使用例程
* 例程导出了 can_sample 命令到控制终端
* 命令调用格式：can_sample can2
* 命令解释：命令第二个参数是要使用的 CAN 设备名称，为空则使用默认的 CAN 设备
* 程序功能：通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。
*/
#include <rtthread.h>
#include "rtdevice.h"
#define CAN_DEV_NAME "can" /* CAN 设备名称 */
static struct rt_semaphore rx_sem; /* 用于接收消息的信号量 */
static rt_device_t can_dev; /* CAN 设备句柄 */
/* 接收数据回调函数 */
static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size)
{
/* CAN 接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */
rt_sem_release(&rx_sem);
return RT_EOK;
}
static void can_rx_thread(void *parameter)
{
int i;
struct rt_can_msg rxmsg = {0};
/* 设置接收回调函数 */
rt_device_set_rx_indicate(can_dev, can_rx_call);
#ifdef RT_CAN_USING_HDR
rt_err_t res;
struct rt_can_filter_item items[5] =
{
RT_CAN_FILTER_ITEM_INIT(0x100, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x100~0x1ff，hdr为-1，设置默认过滤表 */
RT_CAN_FILTER_ITEM_INIT(0x300, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x300~0x3ff，hdr为-1 */
RT_CAN_FILTER_ITEM_INIT(0x211, 0, 0, 0, 0x7ff, RT_NULL, RT_NULL), /* std,match ID:0x211，hdr为-1 */
RT_CAN_FILTER_STD_INIT(0x486, RT_NULL, RT_NULL), /* std,match ID:0x486，hdr为-1 */
{0x555, 0, 0, 0, 0x7ff, 7,} /* std,match ID:0x555，hdr为7，指定设置7号过滤表 */
};
struct rt_can_filter_config cfg = {5, 1, items}; /* 一共有5个过滤表 */
/* 设置硬件过滤表 */
res = rt_device_control(can_dev, RT_CAN_CMD_SET_FILTER, &cfg);
RT_ASSERT(res == RT_EOK);
#endif
while (1)
{
/* hdr值为-1，表示直接从uselist链表读取数据 */
rxmsg.hdr = -1;
/* 阻塞等待接收信号量 */
rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
/* 从CAN读取一帧数据 */
rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg));
/* 打印数据ID及内容 */
rt_kprintf("ID:%x ", rxmsg.id);
for (i = 0; i < 8; i++)
{
rt_kprintf("%2x ", rxmsg.data[i]);
}
rt_kprintf("\n");
}
}
int can_sample(int argc, char *argv[])
{
struct rt_can_msg msg = {0};
rt_err_t res;
rt_size_t size;
rt_thread_t thread;
char can_name[RT_NAME_MAX];
if (argc == 2)
{
rt_strncpy(can_name, argv[1], RT_NAME_MAX);
}
else
{
rt_strncpy(can_name, CAN_DEV_NAME, RT_NAME_MAX);
}
can_dev = rt_device_find(can_name);
if (!can_dev)
{
rt_kprintf("find %s failed!\n", can_name);
return RT_ERROR;
}
/* 初始化CAN接收信号量 */
rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
/* 以中断接收及发送方式打开CAN设备 */
res = rt_device_open(can_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX);
RT_ASSERT(res == RT_EOK);
thread = rt_thread_create("can_rx", can_rx_thread, RT_NULL, 1024, 25, 10);
if (thread != RT_NULL)
{
rt_thread_startup(thread);
}
else
{
rt_kprintf("create can_rx thread failed!\n");
}
msg.id = 0x78; /* ID为0x78 */
msg.ide = RT_CAN_STDID; /* 标准格式 */
msg.rtr = RT_CAN_DTR; /* 数据帧 */
msg.len = 8; /* 数据长度为8 */
/* 待发送的8字节数据 */
msg.data[0] = 0x00;
msg.data[1] = 0x11;
msg.data[2] = 0x22;
msg.data[3] = 0x33;
msg.data[4] = 0x44;
msg.data[5] = 0x55;
msg.data[6] = 0x66;
msg.data[7] = 0x77;
/* 发送一帧CAN数据 */
size = rt_device_write(can_dev, 0, &msg, sizeof(msg));
if (size == 0)
{
rt_kprintf("can dev write data failed!\n");
}
return res;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(can_sample, can device sample);

85
bsp/essemi/es32f0654/drivers/bsp_driver_example/hwtimer_sample.c Normal file
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@ -0,0 +1,85 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-30 misonyo first implementation.
*/
/*
* 程序清单：这是一个 hwtimer 设备使用例程
* 例程导出了 hwtimer_sample 命令到控制终端
* 命令调用格式：hwtimer_sample
* 程序功能：硬件定时器超时回调函数周期性的打印当前tick值，2次tick值之差换算为时间等同于定时时间值。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define HWTIMER_DEV_NAME "timer0" /* 定时器名称 */
/* 定时器超时回调函数 */
static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
{
rt_kprintf("tick is :%d !\n", rt_tick_get());
return 0;
}
static int hwtimer_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
rt_hwtimerval_t timeout_s; /* 定时器超时值 */
rt_device_t hw_dev = RT_NULL; /* 定时器设备句柄 */
rt_hwtimer_mode_t mode; /* 定时器模式 */
/* 查找定时器设备 */
hw_dev = rt_device_find(HWTIMER_DEV_NAME);
if (hw_dev == RT_NULL)
{
rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME);
return RT_ERROR;
}
/* 以读写方式打开设备 */
ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
if (ret != RT_EOK)
{
rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME);
return ret;
}
/* 设置超时回调函数 */
rt_device_set_rx_indicate(hw_dev, timeout_cb);
/* 设置模式为周期性定时器 */
mode = HWTIMER_MODE_PERIOD;
ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode);
if (ret != RT_EOK)
{
rt_kprintf("set mode failed! ret is :%d\n", ret);
return ret;
}
/* 设置定时器超时值为5s并启动定时器 */
timeout_s.sec = 5; /* 秒 */
timeout_s.usec = 0; /* 微秒 */
if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
{
rt_kprintf("set timeout value failed\n");
return RT_ERROR;
}
/* 延时3500ms */
rt_thread_mdelay(3500);
/* 读取定时器当前值 */
rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
return ret;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);

97
bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c Normal file
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@ -0,0 +1,97 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-12-15 liuhy first implementation.
*/
/*
* 程序清单：这是一个 I2C 设备使用例程
* 例程导出了 i2c_io_sample 命令到控制终端
* 命令调用格式：i2c_io_sample
* 命令解释：使用默认的I2C总线设备
* 程序功能：通过 I2C 设备接收数据并打印，然后将接收的字符加1输出。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define I2C_BUS_NAME "i2c1" /* I2C总线设备名称 */
#define SLAVE_ADDR 0x2D /* 从机地址 */
#define STR_LEN 16 /* 接收发送的数据长度 */
static void i2c_io_sample(int argc, char *argv[])
{
struct rt_i2c_bus_device *i2c_bus = RT_NULL; /* I2C总线设备句柄 */
struct rt_i2c_msg temp_msg; /* I2C消息 */
rt_uint8_t buffer[STR_LEN] = { 0U };
rt_uint32_t i,num_msg;
rt_size_t s_stat;
i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(I2C_BUS_NAME); /* 通过名字获取I2C总线设备的句柄 */
if( i2c_bus == RT_NULL)
{
rt_kprintf("can't find i2c device :%s !\n",I2C_BUS_NAME);
return;
}
/*初始化消息*/
temp_msg.addr = SLAVE_ADDR; /* 从机地址 */
temp_msg.len = STR_LEN; /* 传输的数据长度 */
temp_msg.buf = buffer; /* 读写缓存器 */
num_msg = 1; /* 传输一条消息 */
temp_msg.flags = RT_I2C_RD; /* I2C读 */
s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输消息 */
rt_thread_mdelay(400);
if( s_stat == num_msg )
{
rt_kprintf("receive successful. \n receive messege : %s \n:",buffer);
for( i = 0 ; i < STR_LEN ; i++)
rt_kprintf(" %x",(unsigned int)buffer[i]);
rt_kprintf("\n");
}
else
{
rt_kprintf("device s% recieve fail \n buffer : s%\n",I2C_BUS_NAME,buffer);
return;
}
for( i = 0 ; i < STR_LEN ; i++)
buffer[i]++;
temp_msg.flags = RT_I2C_WR; /* I2C写 */
s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输一条 */
rt_thread_mdelay(400);
if( s_stat == num_msg )
{
rt_kprintf(" send successful \n messege : %s \n:",buffer);
for( i = 0 ; i < STR_LEN ; i++)
rt_kprintf(" %x",(unsigned int)buffer[i]);
rt_kprintf("\n");
}
else
{
rt_kprintf("device s% send fail \n",I2C_BUS_NAME);
return;
}
return;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(i2c_io_sample, i2c io sample);

83
bsp/essemi/es32f0654/drivers/bsp_driver_example/led_blink_sample.c Normal file
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@ -0,0 +1,83 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-09-25 misonyo first edition.
*/
/*
* 程序清单：这是一个通过PIN脚控制LED亮灭的使用例程
* 例程导出了 led_sample 命令到控制终端
* 命令调用格式：led_sample 41
* 命令解释：命令第二个参数是要使用的PIN脚编号，为空则使用例程默认的引脚编号。
* 程序功能：程序创建一个led线程，线程每隔1000ms改变PIN脚状态，达到控制led灯
* 亮灭的效果。
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <stdlib.h>
/* PIN脚编号，查看驱动文件drv_gpio.c确定 */
#define LED_PIN_NUM 40 /*PB9*/
static int pin_num;
static void led_entry(void *parameter)
{
int count = 0;
/* 设置PIN脚模式为输出 */
rt_pin_mode(pin_num, PIN_MODE_OUTPUT);
while (1)
{
count++;
rt_kprintf("thread run count : %d\r\n", count);
/* 拉低PIN脚 */
rt_pin_write(pin_num, PIN_LOW);
rt_kprintf("led on!\r\n");
/* 延时1000ms */
rt_thread_mdelay(1000);
/* 拉高PIN脚 */
rt_pin_write(pin_num, PIN_HIGH);
rt_kprintf("led off!\r\n");
rt_thread_mdelay(1000);
}
}
static int led_sample(int argc, char *argv[])
{
rt_thread_t tid;
rt_err_t ret = RT_EOK;
/* 判断命令行参数是否给定了PIN脚编号 */
if (argc == 2)
{
pin_num = atoi(argv[1]);
}
else
{
pin_num = LED_PIN_NUM;
}
tid = rt_thread_create("led",
led_entry,
RT_NULL,
512,
RT_THREAD_PRIORITY_MAX / 3,
20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
ret = RT_ERROR;
}
return ret;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(led_sample, led sample);

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