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[bsp/nuvoton] Support NuMaker-M467HJ BSP and update drivers. (#6416) 

* [bsp/nuvoton] Support NuMaker-M467HJ BSP and update drivers.

* Format files.

Co-authored-by: Wayne Lin <wclin@nuvoton.com>
This commit is contained in:
Wayne 2022-09-12 19:36:11 +08:00 committed by GitHub
parent 4a83592596
commit c9db6ed151
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
387 changed files with 197642 additions and 1240 deletions
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1
bsp/nuvoton/README.md
View File

@ -10,3 +10,4 @@ Current supported BSP shown in below table:
| [nk-rtu980](nk-rtu980) | Nuvoton NK-RTU980 |
| [nk-n9h30](nk-n9h30) | Nuvoton NK-N9H30 |
| [numaker-m032ki](numaker-m032ki) | Nuvoton NuMaker-M032KI |
| [numaker-m467hj](numaker-m467hj) | Nuvoton NuMaker-M467HJ |

1
bsp/nuvoton/docs/LVGL_Notes.md
View File

@ -10,6 +10,7 @@ Current supported LVGL running environment on Nuvoton's boards shown in below ta
| numaker-m2354 | Music | Nu-TFT v1.3 | config_lvgl |
| nk-n9h30 | Music | No | .config |
| numaker-m032ki | Widgets | Nu-TFT v1.3 | config_lvgl |
| numaker-m467hj | Widgets | NuMaker-TFT-LCD43 v1.0 | config_lvgl |
## Download related packages

6
bsp/nuvoton/libraries/m031/Device/Nuvoton/M031/Include/spi_reg.h
View File

@ -488,7 +488,11 @@ typedef struct
__O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */
__I uint32_t RESERVE1[3];
__I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */
__I uint32_t RESERVE2[11];
__I uint32_t RESERVE2[5]; /*!< [0x0034] Reserved */
__IO uint32_t INTERNAL; /*!< [0x0048] SPI Internal Control Register */
__I uint32_t RESERVE3; /*!< [0x004C] Reserved */
__I uint32_t VER_NUM; /*!< [0x0050] SPI Version Number Register */
__I uint32_t RESERVE4[3]; /*!< [0x0054] Reserved */
__IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */
__IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */
__IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */

12
bsp/nuvoton/libraries/m031/rtt_port/drv_crc.c
View File

@ -45,8 +45,10 @@ static rt_uint32_t nu_crc_run(
{
uint32_t u32CalChecksum = 0;
uint32_t i = 0;
rt_err_t result;
rt_mutex_take(&s_CRC_mutex, RT_WAITING_FOREVER);
result = rt_mutex_take(&s_CRC_mutex, RT_WAITING_FOREVER);
RT_ASSERT(result == RT_EOK);
/* Configure CRC controller */
CRC_Open(u32OpMode, u32Attr, u32Seed, CRC_WDATA_8);
@ -86,7 +88,9 @@ static rt_uint32_t nu_crc_run(
/* Get checksum value */
u32CalChecksum = CRC_GetChecksum();
rt_mutex_release(&s_CRC_mutex);
result = rt_mutex_release(&s_CRC_mutex);
RT_ASSERT(result == RT_EOK);
return u32CalChecksum;
}
@ -94,9 +98,7 @@ static rt_uint32_t nu_crc_run(
rt_err_t nu_crc_init(void)
{
SYS_ResetModule(CRC_RST);
rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO);
return RT_EOK;
return rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO);
}
rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)

7
bsp/nuvoton/libraries/m031/rtt_port/drv_pdma.c
View File

@ -201,10 +201,13 @@ static void nu_pdma_init(void)
/* Assign first SG table address as PDMA SG table base address */
PDMA->SCATBA = (uint32_t)&nu_pdma_sgtbl_arr[0];
/* Initializa token pool. */
/* Initialize token pool. */
rt_memset(&nu_pdma_sgtbl_token[0], 0xff, sizeof(nu_pdma_sgtbl_token));
latest = NU_PDMA_SGTBL_POOL_SIZE / 32;
if (NU_PDMA_SGTBL_POOL_SIZE % 32)
{
latest = (NU_PDMA_SGTBL_POOL_SIZE) / 32;
nu_pdma_sgtbl_token[latest] ^= ~((1 << (NU_PDMA_SGTBL_POOL_SIZE % 32)) - 1) ;
}
nu_pdma_inited = 1;
}

90
bsp/nuvoton/libraries/m031/rtt_port/drv_uart.c
View File

@ -288,7 +288,6 @@ static struct nu_uart nu_uart_arr [] =
#endif
},
#endif
{0}
}; /* uart nu_uart */
/* Interrupt Handle Function ----------------------------------------------------*/
@ -378,7 +377,7 @@ void UART57_IRQHandler(void)
static void nu_uart_isr(nu_uart_t serial)
{
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
UART_T *uart_base = serial->uart_base;
/* Get interrupt event */
uint32_t u32IntSts = uart_base->INTSTS;
@ -413,12 +412,15 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
uint32_t uart_stop_bit = 0;
uint32_t uart_parity = 0;
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
RT_ASSERT(serial);
RT_ASSERT(cfg);
/* Check baudrate */
RT_ASSERT(cfg->baud_rate != 0);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
/* Check word len */
switch (cfg->data_bits)
{
@ -439,7 +441,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
break;
default:
rt_kprintf("Unsupported data length");
rt_kprintf("Unsupported data length\n");
ret = RT_EINVAL;
goto exit_nu_uart_configure;
}
@ -456,7 +458,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
break;
default:
rt_kprintf("Unsupported stop bit");
rt_kprintf("Unsupported stop bit\n");
ret = RT_EINVAL;
goto exit_nu_uart_configure;
}
@ -477,7 +479,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
break;
default:
rt_kprintf("Unsupported parity");
rt_kprintf("Unsupported parity\n");
ret = RT_EINVAL;
goto exit_nu_uart_configure;
}
@ -545,13 +547,12 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
rt_size_t transferred_rxbyte = 0;
struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner;
nu_uart_t puart = (nu_uart_t)serial;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = puart->uart_base;
transferred_rxbyte = nu_pdma_transferred_byte_get(puart->pdma_chanid_rx, puart->rxdma_trigger_len);
if (u32Events & (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT))
{
if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)
@ -576,8 +577,10 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
recv_len = transferred_rxbyte - puart->rx_write_offset;
if (recv_len > 0)
{
puart->rx_write_offset = transferred_rxbyte % puart->rxdma_trigger_len;
}
}
if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE))
@ -585,7 +588,7 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
recv_len = puart->rxdma_trigger_len;
}
if (recv_len)
if (recv_len > 0)
{
rt_hw_serial_isr(&puart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
}
@ -594,7 +597,7 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
static rt_err_t nu_pdma_uart_tx_config(struct rt_serial_device *serial)
{
rt_err_t result = RT_EOK;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
result = nu_pdma_callback_register(((nu_uart_t)serial)->pdma_chanid_tx,
nu_pdma_uart_tx_cb,
@ -608,7 +611,7 @@ static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events)
{
nu_uart_t puart = (nu_uart_t)pvOwner;
RT_ASSERT(puart != RT_NULL);
RT_ASSERT(puart);
UART_DISABLE_INT(puart->uart_base, UART_INTEN_TXPDMAEN_Msk);// Stop DMA TX transfer
@ -624,15 +627,16 @@ static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events)
static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
{
rt_err_t result = RT_EOK;
nu_uart_t psNuUart = (nu_uart_t)serial;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(buf != RT_NULL);
RT_ASSERT(serial);
RT_ASSERT(buf);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
UART_T *uart_base = psNuUart->uart_base;
if (direction == RT_SERIAL_DMA_TX)
{
result = nu_pdma_transfer(((nu_uart_t)serial)->pdma_chanid_tx,
result = nu_pdma_transfer(psNuUart->pdma_chanid_tx,
8,
(uint32_t)buf,
(uint32_t)uart_base,
@ -645,8 +649,8 @@ static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
UART_DISABLE_INT(uart_base, UART_INTEN_RXPDMAEN_Msk);
// If config.bufsz = 0, serial will trigger once.
((nu_uart_t)serial)->rxdma_trigger_len = size;
((nu_uart_t)serial)->rx_write_offset = 0;
psNuUart->rxdma_trigger_len = size;
psNuUart->rx_write_offset = 0;
result = nu_pdma_uart_rx_config(serial, buf, size);
}
else
@ -659,7 +663,7 @@ static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_
static int nu_hw_uart_dma_allocate(nu_uart_t pusrt)
{
RT_ASSERT(pusrt != RT_NULL);
RT_ASSERT(pusrt);
/* Allocate UART_TX nu_dma channel */
if (pusrt->pdma_perp_tx != NU_PDMA_UNUSED)
@ -690,30 +694,31 @@ static int nu_hw_uart_dma_allocate(nu_uart_t pusrt)
*/
static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
nu_uart_t psNuUart = (nu_uart_t)serial;
rt_err_t result = RT_EOK;
rt_uint32_t flag;
rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
UART_T *uart_base = psNuUart->uart_base;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */
{
flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
UART_DISABLE_INT(uart_base, flag);
UART_DISABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk);
}
else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */
{
/* Disable Receive Line interrupt & Stop DMA RX transfer. */
#if defined(RT_SERIAL_USING_DMA)
nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
UART_DISABLE_INT(uart_base, UART_INTEN_RXPDMAEN_Msk);
if (psNuUart->dma_flag & RT_DEVICE_FLAG_DMA_RX)
{
nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx);
}
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
#endif
}
break;
@ -721,8 +726,7 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
case RT_DEVICE_CTRL_SET_INT:
if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */
{
flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
UART_ENABLE_INT(uart_base, flag);
UART_ENABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk);
}
break;
@ -731,9 +735,10 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */
{
struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
((nu_uart_t)serial)->rxdma_trigger_len = serial->config.bufsz;
((nu_uart_t)serial)->rx_write_offset = 0;
result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], ((nu_uart_t)serial)->rxdma_trigger_len); // Config & trigger
psNuUart->rxdma_trigger_len = serial->config.bufsz;
psNuUart->rx_write_offset = 0;
result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], psNuUart->rxdma_trigger_len); // Config & trigger
}
else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */
{
@ -744,15 +749,18 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
case RT_DEVICE_CTRL_CLOSE:
/* Disable NVIC interrupt. */
NVIC_DisableIRQ(((nu_uart_t)serial)->uart_irq_n);
NVIC_DisableIRQ(psNuUart->uart_irq_n);
#if defined(RT_SERIAL_USING_DMA)
nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_tx);
nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
#endif
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
UART_DISABLE_INT(uart_base, UART_INTEN_TXPDMAEN_Msk);
/* Reset this module */
SYS_ResetModule(((nu_uart_t)serial)->uart_rst);
if (psNuUart->dma_flag != 0)
{
nu_pdma_channel_terminate(psNuUart->pdma_chanid_tx);
nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx);
}
#endif
/* Close UART port */
UART_Close(uart_base);
@ -772,7 +780,7 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
*/
static int nu_uart_send(struct rt_serial_device *serial, char c)
{
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
@ -791,7 +799,7 @@ static int nu_uart_send(struct rt_serial_device *serial, char c)
*/
static int nu_uart_receive(struct rt_serial_device *serial)
{
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;

5
bsp/nuvoton/libraries/m2354/rtt_port/drv_pdma.c
View File

@ -234,8 +234,11 @@ static void nu_pdma_init(void)
/* Initialize token pool. */
rt_memset(&nu_pdma_sgtbl_token[0], 0xff, sizeof(nu_pdma_sgtbl_token));
latest = NU_PDMA_SGTBL_POOL_SIZE / 32;
if (NU_PDMA_SGTBL_POOL_SIZE % 32)
{
latest = (NU_PDMA_SGTBL_POOL_SIZE) / 32;
nu_pdma_sgtbl_token[latest] ^= ~((1 << (NU_PDMA_SGTBL_POOL_SIZE % 32)) - 1) ;
}
nu_pdma_inited = 1;
}

91
bsp/nuvoton/libraries/m2354/rtt_port/drv_uart.c
View File

@ -238,7 +238,6 @@ static struct nu_uart nu_uart_arr [] =
#endif
},
#endif
{0}
}; /* uart nu_uart */
/* Interrupt Handle Function ----------------------------------------------------*/
@ -332,7 +331,7 @@ void UART5_IRQHandler(void)
static void nu_uart_isr(nu_uart_t serial)
{
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
UART_T *uart_base = serial->uart_base;
/* Get interrupt event */
uint32_t u32IntSts = uart_base->INTSTS;
@ -367,12 +366,15 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
uint32_t uart_stop_bit = 0;
uint32_t uart_parity = 0;
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
RT_ASSERT(serial);
RT_ASSERT(cfg);
/* Check baudrate */
RT_ASSERT(cfg->baud_rate != 0);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
/* Check word len */
switch (cfg->data_bits)
{
@ -393,7 +395,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
break;
default:
rt_kprintf("Unsupported data length");
rt_kprintf("Unsupported data length\n");
ret = RT_EINVAL;
goto exit_nu_uart_configure;
}
@ -410,7 +412,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
break;
default:
rt_kprintf("Unsupported stop bit");
rt_kprintf("Unsupported stop bit\n");
ret = RT_EINVAL;
goto exit_nu_uart_configure;
}
@ -431,7 +433,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
break;
default:
rt_kprintf("Unsupported parity");
rt_kprintf("Unsupported parity\n");
ret = RT_EINVAL;
goto exit_nu_uart_configure;
}
@ -488,7 +490,6 @@ static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t
UART_ENABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
UART_PDMA_ENABLE(uart_base, UART_INTEN_RXPDMAEN_Msk);
exit_nu_pdma_uart_rx_config:
return result;
@ -500,7 +501,7 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
rt_size_t transferred_rxbyte = 0;
struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner;
nu_uart_t puart = (nu_uart_t)serial;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = puart->uart_base;
@ -531,8 +532,10 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
recv_len = transferred_rxbyte - puart->rx_write_offset;
if (recv_len > 0)
{
puart->rx_write_offset = transferred_rxbyte % puart->rxdma_trigger_len;
}
}
if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE))
@ -540,7 +543,7 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
recv_len = puart->rxdma_trigger_len;
}
if (recv_len)
if (recv_len > 0)
{
rt_hw_serial_isr(&puart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
}
@ -563,7 +566,7 @@ static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events)
{
nu_uart_t puart = (nu_uart_t)pvOwner;
RT_ASSERT(puart != RT_NULL);
RT_ASSERT(puart);
UART_PDMA_DISABLE(puart->uart_base, UART_INTEN_TXPDMAEN_Msk);// Stop DMA TX transfer
@ -579,29 +582,31 @@ static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events)
static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
{
rt_err_t result = RT_EOK;
nu_uart_t psNuUart = (nu_uart_t)serial;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(buf != RT_NULL);
RT_ASSERT(serial);
RT_ASSERT(buf);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
UART_T *uart_base = psNuUart->uart_base;
if (direction == RT_SERIAL_DMA_TX)
{
result = nu_pdma_transfer(((nu_uart_t)serial)->pdma_chanid_tx,
result = nu_pdma_transfer(psNuUart->pdma_chanid_tx,
8,
(uint32_t)buf,
(uint32_t)uart_base,
size,
0); // wait-forever
UART_PDMA_ENABLE(uart_base, UART_INTEN_TXPDMAEN_Msk); // Start DMA TX transfer
// Start DMA TX transfer
UART_PDMA_ENABLE(uart_base, UART_INTEN_TXPDMAEN_Msk);
}
else if (direction == RT_SERIAL_DMA_RX)
{
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
UART_PDMA_DISABLE(uart_base, UART_INTEN_RXPDMAEN_Msk);
// If config.bufsz = 0, serial will trigger once.
((nu_uart_t)serial)->rxdma_trigger_len = size;
((nu_uart_t)serial)->rx_write_offset = 0;
psNuUart->rxdma_trigger_len = size;
psNuUart->rx_write_offset = 0;
result = nu_pdma_uart_rx_config(serial, buf, size);
}
else
@ -614,7 +619,7 @@ static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_
static int nu_hw_uart_dma_allocate(nu_uart_t pusrt)
{
RT_ASSERT(pusrt != RT_NULL);
RT_ASSERT(pusrt);
/* Allocate UART_TX nu_dma channel */
if (pusrt->pdma_perp_tx != NU_PDMA_UNUSED)
@ -645,30 +650,31 @@ static int nu_hw_uart_dma_allocate(nu_uart_t pusrt)
*/
static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
nu_uart_t psNuUart = (nu_uart_t)serial;
rt_err_t result = RT_EOK;
rt_uint32_t flag;
rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
UART_T *uart_base = psNuUart->uart_base;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */
{
flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
UART_DISABLE_INT(uart_base, flag);
UART_DISABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk);
}
else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */
{
/* Disable Receive Line interrupt & Stop DMA RX transfer. */
#if defined(RT_SERIAL_USING_DMA)
nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
UART_PDMA_DISABLE(uart_base, UART_INTEN_RXPDMAEN_Msk);
if (psNuUart->dma_flag & RT_DEVICE_FLAG_DMA_RX)
{
nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx);
}
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
#endif
}
break;
@ -676,8 +682,7 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
case RT_DEVICE_CTRL_SET_INT:
if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */
{
flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
UART_ENABLE_INT(uart_base, flag);
UART_ENABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk);
}
break;
@ -686,9 +691,10 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */
{
struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
((nu_uart_t)serial)->rxdma_trigger_len = serial->config.bufsz;
((nu_uart_t)serial)->rx_write_offset = 0;
result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], ((nu_uart_t)serial)->rxdma_trigger_len); // Config & trigger
psNuUart->rxdma_trigger_len = serial->config.bufsz;
psNuUart->rx_write_offset = 0;
result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], psNuUart->rxdma_trigger_len); // Config & trigger
}
else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */
{
@ -699,15 +705,18 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
case RT_DEVICE_CTRL_CLOSE:
/* Disable NVIC interrupt. */
NVIC_DisableIRQ(((nu_uart_t)serial)->uart_irq_n);
NVIC_DisableIRQ(psNuUart->uart_irq_n);
#if defined(RT_SERIAL_USING_DMA)
nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_tx);
nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
#endif
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
UART_DISABLE_INT(uart_base, UART_INTEN_TXPDMAEN_Msk);
/* Reset this module */
SYS_ResetModule(((nu_uart_t)serial)->uart_rst);
if (psNuUart->dma_flag != 0)
{
nu_pdma_channel_terminate(psNuUart->pdma_chanid_tx);
nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx);
}
#endif
/* Close UART port */
UART_Close(uart_base);
@ -727,7 +736,7 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
*/
static int nu_uart_send(struct rt_serial_device *serial, char c)
{
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
@ -746,7 +755,7 @@ static int nu_uart_send(struct rt_serial_device *serial, char c)
*/
static int nu_uart_receive(struct rt_serial_device *serial)
{
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;

121
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@ -0,0 +1,121 @@
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
* Description: Extern declaration for common tables
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

66
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@ -0,0 +1,66 @@
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
* Description: Constant structs that are initialized for user convenience.
* For example, some can be given as arguments to the arm_cfft_f32() function.
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

7257
bsp/nuvoton/libraries/m460/CMSIS/Include/arm_math.h Normal file
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File diff suppressed because it is too large Load Diff

814
bsp/nuvoton/libraries/m460/CMSIS/Include/cmsis_armcc.h Normal file
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@ -0,0 +1,814 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (ARM compiler V5) header file
* @version V5.0.2
* @date 13. February 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return (__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return (__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return (__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return (__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return (__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return (__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return (__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return (__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return (__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return (__regfpscr);
#else
return (0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return (result);
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.2
* @date 13. February 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* ARM Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* ARM Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#include <cmsis_iar.h>
/* CMSIS compiler control architecture macros */
#if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
#ifndef __ARM_ARCH_6M__
#define __ARM_ARCH_6M__ 1
#endif
#elif (__CORE__ == __ARM7M__)
#ifndef __ARM_ARCH_7M__
#define __ARM_ARCH_7M__ 1
#endif
#elif (__CORE__ == __ARM7EM__)
#ifndef __ARM_ARCH_7EM__
#define __ARM_ARCH_7EM__ 1
#endif
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __noreturn
#endif
#ifndef __USED
#define __USED __root
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
__packed struct T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
//#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
//#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
// Workaround for missing __CLZ intrinsic in
// various versions of the IAR compilers.
// __IAR_FEATURE_CLZ__ should be defined by
// the compiler that supports __CLZ internally.
#if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
__STATIC_INLINE uint32_t __CLZ(uint32_t data)
{
if (data == 0u)
{
return 32u;
}
uint32_t count = 0;
uint32_t mask = 0x80000000;
while ((data & mask) == 0)
{
count += 1u;
mask = mask >> 1u;
}
return (count);
}
#endif
/*
* TI ARM Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return ((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return (0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return (0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return ((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for (;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for ARMv7 MPU
* @version V5.0.2
* @date 09. June 2017
******************************************************************************/
/*
* Copyright (c) 2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
#define ARM_MPU_AP_NONE 0u
#define ARM_MPU_AP_PRIV 1u
#define ARM_MPU_AP_URO 2u
#define ARM_MPU_AP_FULL 3u
#define ARM_MPU_AP_PRO 5u
#define ARM_MPU_AP_RO 6u
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) ((BaseAddress & MPU_RBAR_ADDR_Msk) | (Region & MPU_RBAR_REGION_Msk) | (1UL << MPU_RBAR_VALID_Pos))
/**
* MPU Region Attribut and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
((DisableExec << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
((AccessPermission << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
((TypeExtField << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
((IsShareable << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
((IsCacheable << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
((IsBufferable << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
((SubRegionDisable << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
((Size << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
((1UL << MPU_RASR_ENABLE_Pos) & MPU_RASR_ENABLE_Msk)
/**
* Struct for a single MPU Region
*/
typedef struct _ARM_MPU_Region_t
{
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable()
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0u;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0u; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const *table, uint32_t cnt)
{
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt * sizeof(ARM_MPU_Region_t) / 4u);
}
#endif

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/*
* Copyright (c) 2015-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------------
*
* $Date: 21. September 2016
* $Revision: V1.0
*
* Project: TrustZone for ARMv8-M
* Title: Context Management for ARMv8-M TrustZone
*
* Version 1.0
* Initial Release
*---------------------------------------------------------------------------*/
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S(void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S(TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S(TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S(TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S(TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

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import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Split("""
""")
path = [cwd + '/Include',]
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path)
Return('group')

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/**************************************************************************//**
* @file NuMicro.h
* @version V1.00
* @brief NuMicro peripheral access layer header file.
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NUMICRO_H__
#define __NUMICRO_H__
#include "m460.h"
#endif /* __NUMICRO_H__ */

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/**************************************************************************//**
* @file acmp_reg.h
* @version V1.00
* @brief ACMP register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ACMP_REG_H__
#define __ACMP_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Analog Comparator Controller -------------------------*/
/**
@addtogroup ACMP Analog Comparator Controller(ACMP)
Memory Mapped Structure for ACMP Controller
@{ */
typedef struct
{
/**
* @var ACMP_T::CTL0
* Offset: 0x00 Analog Comparator 0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACMPEN |Comparator Enable Bit
* | | |0 = Comparator 0 Disabled.
* | | |1 = Comparator 0 Enabled.
* |[1] |ACMPIE |Comparator Interrupt Enable Bit
* | | |0 = Comparator 0 interrupt Disabled.
* | | |1 = Comparator 0 interrupt Enabled
* | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
* |[2] |HYSEN |Comparator Hysteresis Enable Bit
* | | |0 = Comparator 0 hysteresis Disabled.
* | | |1 = Comparator 0 hysteresis Enabled.
* | | |Note: If HYSEN = 0, user can adjust HYS by HYSSEL.
* | | |Note: If HYSEN = 1, HYSSEL is invalid. The Hysterresis is fixed to 30mV.
* |[3] |ACMPOINV |Comparator Output Inverse
* | | |0 = Comparator 0 output inverse Disabled.
* | | |1 = Comparator 0 output inverse Enabled.
* |[5:4] |NEGSEL |Comparator Negative Input Selection
* | | |00 = ACMP0_N pin.
* | | |01 = Internal comparator reference voltage (CRV0).
* | | |10 = Band-gap voltage.
* | | |11 = DAC0 output.
* | | |Note: NEGSEL must select 2u2019b01 in calibration mode.
* |[7:6] |POSSEL |Comparator Positive Input Selection
* | | |00 = Input from ACMP0_P0.
* | | |01 = Input from ACMP0_P1.
* | | |10 = Input from ACMP0_P2.
* | | |11 = Input from ACMP0_P3.
* |[9:8] |INTPOL |Interrupt Condition Polarity Selection
* | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected.
* | | |00 = Rising edge or falling edge.
* | | |01 = Rising edge.
* | | |10 = Falling edge.
* | | |11 = Reserved.
* |[12] |OUTSEL |Comparator Output Select
* | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output.
* | | |1 = Comparator 0 output to ACMP0_O pin is from filter output.
* |[15:13] |FILTSEL |Comparator Output Filter Count Selection
* | | |000 = Filter function is Disabled.
* | | |001 = ACMP0 output is sampled 1 consecutive PCLK.
* | | |010 = ACMP0 output is sampled 2 consecutive PCLKs.
* | | |011 = ACMP0 output is sampled 4 consecutive PCLKs.
* | | |100 = ACMP0 output is sampled 8 consecutive PCLKs.
* | | |101 = ACMP0 output is sampled 16 consecutive PCLKs.
* | | |110 = ACMP0 output is sampled 32 consecutive PCLKs.
* | | |111 = ACMP0 output is sampled 64 consecutive PCLKs.
* |[16] |WKEN |Power-down Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[17] |WLATEN |Window Latch Mode Enable Bit
* | | |0 = Window Latch Mode Disabled.
* | | |1 = Window Latch Mode Enabled.
* |[18] |WCMPSEL |Window Compare Mode Selection
* | | |0 = Window Compare Mode Disabled.
* | | |1 = Window Compare Mode is Selected.
* |[21:20] |FCLKDIV |Comparator Output Filter Clock Divider
* | | |00 = cComparator output filter clock = PCLK
* | | |01 = cComparator output filter clock = PCLK/2
* | | |10 = cComparator output filter clock = PCLK/4
* | | |11 = Reserved
* | | |Note: uUse FCLKDIV must under the condition fof FILTSEL = 3u2019h7, then set FCLKDIV canto get the effect of filtering 128,256 consecutive PCLKs.
* |[26:24] |HYSSEL |Hysteresis Mode Selection
* | | |000 = Hysteresis is 0mV.
* | | |001 = Hysteresis is 10mV.
* | | |010 = Hysteresis is 20mV.
* | | |011 = Hysteresis is 30mV.
* | | |100 = Hysteresis is 40mV
* | | |101 = Hysteresis is 50mV
* | | |Others = rReserved
* |[29:28] |MODESEL |Comparator Power Mode Selection
* | | |00 = low power mode comparator AVDD current 1uA
* | | |01 = low power mode comparator AVDD current 2uA
* | | |10 = active mode comparator AVDD current 35uA
* | | |11 = active mode comparator AVDD current 70uA
* @var ACMP_T::CTL1
* Offset: 0x04 Analog Comparator 1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACMPEN |Comparator Enable Bit
* | | |0 = Comparator 1 Disabled.
* | | |1 = Comparator 1 Enabled.
* |[1] |ACMPIE |Comparator Interrupt Enable Bit
* | | |0 = Comparator 1 interrupt Disabled.
* | | |1 = Comparator 1 interrupt Enabled
* | | |If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well.
* |[2] |HYSEN |Comparator Hysteresis Enable Bit
* | | |0 = Comparator 1 hysteresis Disabled.
* | | |1 = Comparator 1 hysteresis Enabled.
* | | |Note: If HYSEN = 0, user can adjust HYS by HYSSEL.
* | | |Note: If HYSEN = 1, HYSSEL is invalid. The Hysterresis is fixed to 30mV.
* |[3] |ACMPOINV |Comparator Output Inverse Control
* | | |0 = Comparator 1 output inverse Disabled.
* | | |1 = Comparator 1 output inverse Enabled.
* |[5:4] |NEGSEL |Comparator Negative Input Selection
* | | |00 = ACMP1_N pin.
* | | |01 = Internal comparator reference voltage (CRV1).
* | | |10 = Band-gap voltage.
* | | |11 = DAC0 output.
* | | |Note: NEGSEL must select 2u2019b01 in calibration mode.
* |[7:6] |POSSEL |Comparator Positive Input Selection
* | | |00 = Input from ACMP1_P0.
* | | |01 = Input from ACMP1_P1.
* | | |10 = Input from ACMP1_P2.
* | | |11 = Input from ACMP1_P3.
* |[9:8] |INTPOL |Interrupt Condition Polarity Selection
* | | |ACMPIF1 will be set to 1 when comparator output edge condition is detected.
* | | |00 = Rising edge or falling edge.
* | | |01 = Rising edge.
* | | |10 = Falling edge.
* | | |11 = Reserved.
* |[12] |OUTSEL |Comparator Output Select
* | | |0 = Comparator 1 output to ACMP1_O pin is unfiltered comparator output.
* | | |1 = Comparator 1 output to ACMP1_O pin is from filter output.
* |[15:13] |FILTSEL |Comparator Output Filter Count Selection
* | | |000 = Filter function is Disabled.
* | | |001 = ACMP1 output is sampled 1 consecutive PCLK.
* | | |010 = ACMP1 output is sampled 2 consecutive PCLKs.
* | | |011 = ACMP1 output is sampled 4 consecutive PCLKs.
* | | |100 = ACMP1 output is sampled 8 consecutive PCLKs.
* | | |101 = ACMP1 output is sampled 16 consecutive PCLKs.
* | | |110 = ACMP1 output is sampled 32 consecutive PCLKs.
* | | |111 = ACMP1 output is sampled 64 consecutive PCLKs.
* |[16] |WKEN |Power-down Wakeup Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[17] |WLATEN |Window Latch Mode Enable Bit
* | | |0 = Window Latch Mode Disabled.
* | | |1 = Window Latch Mode Enabled.
* |[18] |WCMPSEL |Window Compare Mode Selection
* | | |0 = Window Compare Mode Disabled.
* | | |1 = Window Compare Mode is Selected.
* |[21:20] |FCLKDIV |Comparator Output Filter Clock Divider
* | | |00 = comparator output filter clock = PCLK
* | | |01 = comparator output filter clock = PCLK/2
* | | |10 = comparator output filter clock = PCLK/4
* | | |11 = Reserved
* |[26:24] |HYSSEL |Hysteresis Mode Selection
* | | |000 = Hysteresis is 0mV.
* | | |001 = Hysteresis is 10mV.
* | | |010 = Hysteresis is 20mV.
* | | |011 = Hysteresis is 30mV.
* | | |100 = Hysteresis is 40mV
* | | |101 = Hysteresis is 50mV
* | | |Others = rReserved00 = Hysteresis is 0mV.
* | | |01 = Hysteresis is 10mV.
* | | |10 = Hysteresis is 20mV.
* | | |11 = Hysteresis is 30mV.
* |[29:28] |MODESEL |Comparator Power Mode Selection
* | | |00 = low power mode comparator AVDD current 1uA
* | | |01 = low power mode comparator AVDD current 2uA
* | | |10 = active mode comparator AVDD current 35uA
* | | |11 = active mode comparator AVDD current 70uA
* @var ACMP_T::STATUS
* Offset: 0x08 Analog Comparator Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output
* | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
* | | |Note: Write 1 to clear this bit to 0.
* |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output
* | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
* | | |Note: Write 1 to clear this bit to 0.
* |[4] |ACMPO0 |Comparator 0 Output
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 0 is disabled, i.e
* | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
* |[5] |ACMPO1 |Comparator 1 Output
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 1 is disabled, i.e
* | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
* |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag
* | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
* | | |0 = No power-down wake-up occurred.
* | | |1 = Power-down wake-up occurred.
* | | |Note: Write 1 to clear this bit to 0.
* |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag
* | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
* | | |0 = No power-down wake-up occurred.
* | | |1 = Power-down wake-up occurred.
* | | |Note: Write 1 to clear this bit to 0.
* |[12] |ACMPS0 |Comparator 0 Status
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 0 is disabled, i.e
* | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
* |[13] |ACMPS1 |Comparator 1 Status
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 1 is disabled, i.e
* | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
* |[16] |ACMPWO |Comparator Window Output
* | | |This bit shows the output status of window compare mode
* | | |0 = The positive input voltage is outside the window.
* | | |1 = The positive input voltage is in the window.
* @var ACMP_T::VREF
* Offset: 0x0C Analog Comparator Reference Voltage Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |CRV0SEL |Comparator0Comparator 0 Reference Voltage Setting
* | | |CRV0 = CRV0 source voltage * (ACMP_VREF01[5:0] )/ 631/6+CRVCTL/24).
* |[6] |CRV0SSEL |CRV0 Source Voltage Selection
* | | |0 = AVDD is selected as CRV0 source voltage.
* | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV0 source voltage.
* |[8] |CRV0EN |CRV0 Enable Bit
* | | |0 = CRV0 is dDisabled.
* | | |1 = CRV0 is eEnabled.
* |[21:16] |CRV1SEL |Comparator1Comparator 1 Reference Voltage Setting
* | | |CRV1 = CRV1 source voltage * (ACMP_VREF01[21:16] )/ 63.
* |[22] |CRV1SSEL |CRV1 Source Voltage Selection
* | | |0 = AVDD is selected as CRV1 source voltage.
* | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV1 source voltage.
* |[24] |CRV1EN |CRV1 Enable Bit
* | | |0 = CRV1 is dDisabled.
* | | |1 = CRV1 Eis enabled.
* |[31] |CLAMPEN |Current Level Control Selection under Speed Up Function
* | | |0 = ACMP run on high SPEED mode with high quiescent current
* | | |1 = ACMP run on low SPEED mode with high quiescent current
* | | |Note: Comparator speed up function only support SPEED[1:0]=2bu201911 & 2bu201910
* @var ACMP_T::CALCTL
* Offset: 0x10 Analog Comparator Calibration Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CALTRG0 |Comparator0Comparator 0 Calibration Trigger Bit
* | | |0 = Calibration is stopped.
* | | |1 = Calibration is triggered.
* | | |Note 1: Before this bit is enabled, ACMPEN(ACMP_CTL0[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.
* | | |Note 2: Hardware will auto clear this bit when the next calibration is triggered by software.
* | | |Note 3: If user must trigger calibration twice or more times, the second trigger haves to wait at least 300us after the previous calibration is done.
* |[1] |CALTRG1 |Comparator1Comparator 1 Calibration Trigger Bit
* | | |0 = Calibration is stopped.
* | | |1 = Calibration is triggered.
* | | |Note 1: Before this bit is enabled, ACMPEN(ACMP_CTL1[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.
* | | |Note 2: Hardware will auto clear this bit when the next calibration is triggered by software.
* | | |Note 3: If user must trigger calibration twice or more times, the second trigger haves to wait at least 300us after the previous calibration is done.
* |[5:4] |CALCLK0 |Comparator0Comparator 0 Calibration Clock Rate Selection
* | | |00 = 1.5 kHz.
* | | |01 = 6 kHz.
* | | |10 = 24kHz.
* | | |11 = 95 kHz.
* |[7:6] |CALCLK1 |Comparator1Comparator 1 Calibration Clock Rate Selection
* | | |00 = 1.5 kHz.
* | | |01 = 6 kHz.
* | | |10 = 24kHz.
* | | |11 = 95 kHz.
* |[8] |OFFSETSEL |Comparator Trim Code Selection
* | | |0 = calibration trim code will not minus 1 when calibrated done.
* | | |1 = calibration trim code will not minus 1 when calibrated done.
* |[17:16] |CALRVS |Calibration Reference Voltage Selection
* | | |00 = option0 (N-pair calibration: 5V - 80mV, P-pair calibration: 80mV)
* | | |01 = option1
* | | |10 = option2 (N-pair calibration: 5V - 160mV, P-pair calibration: 160mV)
* | | |11 = Reserved
* | | |Note: CRV0 and CRV1 must be the same setting in calibration
* | | |Note: The details refer to Analog ACMP SPEC
* @var ACMP_T::CALSTS
* Offset: 0x14 Analog Comparator Calibration Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DONE0 |Comparator 0 Calibration Done Status
* | | |0 = Calibrating.
* | | |1 = Calibration Ddone.
* | | |NOTE: this bit is write 1 clear
* |[4] |DONE1 |Comparator 1 Calibration Done Status
* | | |0 = Calibrating.
* | | |1 = Calibration Ddone.
* | | |NOTE: this bit is write 1 clear
* @var ACMP_T::COFF
* Offset: 0xFF0 Analog Comparator Calibration Offset Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |NCODE0 |Comparator0Comparator 0 Offset of NMOS
* | | |ACMP0 offset canceling trim code of NMOS
* | | |Note: 1. Once ACMP0 is enabled, reading these bits will gets initial value from ROMMAP46[19:16]
* | | |2. write MODESEL ACMP_CTL0[29:28] will decide NCODE0 load from which ROMMAP
* | | | MODESEL = 2u2019b00, NCODE0 load from ROMMAP46[3:0]
* | | | MODESEL = 2u2019b01, NCODE0 load from ROMMAP46[19:16]
* | | | MODESEL = 2u2019b10, NCODE0 load from ROMMAP47[3:0]
* | | | MODESEL = 2u2019b11, NCODE0 load from ROMMAP47[19:16]
* |[7] |NSEL0 |Comparator0Comparator 0 Offset of NMOS
* | | |0 = trim NMOS negative offset
* | | |1 = trim NMOS positive offset
* | | |Note: 1. Once ACMP0 is enabled, reading this bit default will get initial value from ROMMAP46[20]
* | | | 2. write MODESEL ACMP_CTL0[29:28] will decide NSEL0 load from which ROMMAP
* | | | MODESEL = 2u2019b00, NSEL0 load from ROMMAP46[4]
* | | | MODESEL = 2u2019b01, NSEL0 load from ROMMAP46[20]
* | | | MODESEL = 2u2019b10, NSEL0 load from ROMMAP47[4]
* | | | MODESEL = 2u2019b11, NSEL0 load from ROMMAP47[20]
* | | |2
* | | |If ACMP0 is enabled and CALTRG0 (ACMP_CALCTL01[0]]) is set, after calibration done DONE0(ACMP_CALSRTS01[0]) will get NSEL0 value
* |[11:8] |PCODE0 |Comparator0Comparator 0 Offset of PMOS
* | | |ACMP0 offset canceling trim code of PMOS
* | | |Note: 1. Once ACMP0 is enabled, reading these bits default will get initial value from ROMMAP46[27:24]
* | | |2. write MODESEL ACMP_CTL0[29:28] will decide PCODE0 load from which ROMMAP
* | | | MODESEL = 2u2019b00, PCODE0 load from ROMMAP46[11:8]
* | | | MODESEL = 2u2019b01, PCODE0 load from ROMMAP46[27:24]
* | | | MODESEL = 2u2019b10, PCODE0 load from ROMMAP47[11:8]
* | | | MODESEL = 2u2019b11, PCODE0 load from ROMMAP47[27:24]
* |[15] |PSEL0 |Comparator0Comparator 0 Offset of PMOS
* | | |0 = trim PMOS negative offset
* | | |1 = trim PMOS positive offset
* | | |Note: 1. Once ACMP0 is enabled, reading this bit default will get initial value from ROMMAP46[28].
* | | |2. write MODESEL ACMP_CTL0[29:28] will decide PSEL0 load from which ROMMAP
* | | | MODESEL = 2u2019b00, PSEL0 load from ROMMAP46[12]
* | | | MODESEL = 2u2019b01, PSEL0 load from ROMMAP48[28]
* | | | MODESEL = 2u2019b10, PSEL0 load from ROMMAP47[12]
* | | | MODESEL = 2u2019b11, PSEL0 load from ROMMAP47[28]
* | | |3
* | | |If ACMP0 is enabled and CALTRG0 (ACMP_CALCTL01[0]]) is set, after calibration done DONE0(ACMP_CALSACMP_CALSTS01R[0]) will get PSEL0 value
* |[19:16] |NCODE1 |Comparator 1 Offset of NMOS
* | | |ACMP1 offset canceling trim code of PMOS
* | | |Note: 1. Once ACMP1 is enabled, reading these bits default will get initial value from ROMMAP48[19:16]
* | | |2. write MODESEL ACMP_CTL1[29:28] will decide NCODE1 load from which ROMMAP
* | | | MODESEL = 2u2019b00, NCODE1load from ROMMAP48[3:0]
* | | | MODESEL = 2u2019b01, NCODE1 load from ROMMAP48[19:16]
* | | | MODESEL = 2u2019b10, NCODE1 load from ROMMAP49[3:0]
* | | | MODESEL = 2u2019b11, NCODE1 load from ROMMAP49[19:16]
* |[23] |NSEL1 |Comparator 1 Offset of NMOS
* | | |0 = trim NMOS negative offset
* | | |1 = trim NMOS positive offset
* | | |Note: 1. Once ACMP1 is enabled, reading this bit default will get initial value from ROMMAP48[20]
* | | | 2. write MODESEL ACMP_CTL1[29:28] will decide NSEL1 load from which ROMMAP
* | | | MODESEL = 2u2019b00, NSEL1 load from ROMMAP48[4]
* | | | MODESEL = 2u2019b01, NSEL1 load from ROMMAP48[20]
* | | | MODESEL = 2u2019b10, NSEL1 load from ROMMAP49[4]
* | | | MODESEL = 2u2019b11, NSEL1 load from ROMMAP49[20]
* | | |3
* | | |If ACMP1 is enabled and CALTRG1 (ACMP_CALCTL01[1]]) is set, after calibration done DONE1(ACMP_CALSRTS01[4]) will get NSEL1 value
* |[27:24] |PCODE1 |Comparator 1 Offset of PMOS
* | | |ACMP1 offset canceling trim code of PMOS
* | | |Note: 1. Once ACMP1 is enabled, reading these bits default will get initial value from ROMMAP48[27:24]
* | | |2. write MODESEL ACMP_CTL1[29:28] will decide PCODE1 load from which ROMMAP
* | | | MODESEL = 2u2019b00, PCODE1 load from ROMMAP48[11:8]
* | | | MODESEL = 2u2019b01, PCODE1 load from ROMMAP48[27:24]
* | | | MODESEL = 2u2019b10, PCODE1 load from ROMMAP49[11:8]
* | | | MODESEL = 2u2019b11, PCODE1 load from ROMMAP49[27:24]
* |[31] |PSEL1 |Comparator 1 Offset of PMOS
* | | |0 = trim PMOS negative offset
* | | |1 = trim PMOS positive offset
* | | |Note: 1. Once ACMP1 is enabled, reading this bit default will get initial value from ROMMAP48[28]
* | | | 2. write MODESEL ACMP_CTL1[29:28] will decide PSEL1 load from which ROMMAP
* | | | MODESEL = 2u2019b00, PSEL1 load from ROMMAP48[12]
* | | | MODESEL = 2u2019b01, PSEL1 load from ROMMAP48[28]
* | | | MODESEL = 2u2019b10, PSEL1 load from ROMMAP49[12]
* | | | MODESEL = 2u2019b11, PSEL1 load from ROMMAP49[28]
* | | |3
* | | |If ACMP1 is enabled and CALTRG1 (ACMP_CALCTL01[1]]) is set, after calibration done DONE1(ACMP_CALSRTS01[4]) will get PSEL1 value
* @var ACMP_T::TEST
* Offset: 0xFF8 Analog Comparator Test Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CRV0TEST |CRV0 Test Mode Enable Bit (Write Protect)
* | | |0 = No effect.
* | | |1 = CRV voltage output to ACMP0_N pin for voltage measure.
* | | |This bit is designed for Nuvoton Lab use only.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note: NEGSEL (ACMP_CTL0[5:4]) or NEGSEL (ACMP_CTL1[5:4]) must select to 2u2019b01 in CRV test mode
* |[1] |CRV1TEST |CRV1 Test Mode Enable Bit (Write Protect)
* | | |0 = No effect.
* | | |1 = CRV voltage output to ACMP0_N pin for voltage measure.
* | | |This bit is designed for Nuvoton Lab use only.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note: NEGSEL (ACMP_CTL0[5:4]) or NEGSEL (ACMP_CTL1[5:4]) must select to 2u2019b01 in CRV test mode
* |[4] |OUTSEL |Comparator CRV Output Source Selection
* | | |0 = CRV output from resistor string
* | | |1 = CRV output from bandgap voltage
* |[8] |HYSBYPASS |Hysteresis Adjust Function Selection
* | | |0 = Enable adjust function
* | | |1 = Bypass adjust function
* @var ACMP_T::VERSION
* Offset: 0xFFC Analog Comparator RTL Design Version Number
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |MINOR |Comp RTL Design MINOR Version Number
* | | |Minor version number is dependent on module ECO version control.
* |[23:16] |SUB |Comp RTL Design SUB Version Number
* | | |Major version number is correlated to Product Line.
* |[31:24] |MAJOR |Comp RTL Design MAJOR Version Number
* | | |Major version number is correlated to Product Line.
*/
__IO uint32_t CTL[2]; /*!< [0x0000-0x0004] Analog Comparator 0/1 Control Register */
__IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */
__IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */
__IO uint32_t CALCTL; /*!< [0x0010] Analog Comparator Calibration Control Register */
__IO uint32_t CALSTS; /*!< [0x0014] Analog Comparator Calibration Status Register */
__I uint32_t RESERVE0[1014];
__IO uint32_t COFF; /*!< [0x0ff0] Analog Comparator Calibration Offset Register */
__I uint32_t RESERVE1[1];
__IO uint32_t TEST; /*!< [0x0ff8] Analog Comparator Test Control Register */
__I uint32_t VERSION; /*!< [0x0ffc] Analog Comparator RTL Design Version Number */
} ACMP_T;
/**
@addtogroup ACMP_CONST ACMP Bit Field Definition
Constant Definitions for ACMP Controller
@{ */
#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL0: ACMPEN Position */
#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL0: ACMPEN Mask */
#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL0: ACMPIE Position */
#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL0: ACMPIE Mask */
#define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL0: HYSEN Position */
#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL0: HYSEN Mask */
#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL0: ACMPOINV Position */
#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL0: ACMPOINV Mask */
#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL0: NEGSEL Position */
#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL0: NEGSEL Mask */
#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL0: POSSEL Position */
#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL0: POSSEL Mask */
#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL0: INTPOL Position */
#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL0: INTPOL Mask */
#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL0: OUTSEL Position */
#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL0: OUTSEL Mask */
#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL0: FILTSEL Position */
#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL0: FILTSEL Mask */
#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL0: WKEN Position */
#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL0: WKEN Mask */
#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL0: WLATEN Position */
#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL0: WLATEN Mask */
#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL0: WCMPSEL Position */
#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL0: WCMPSEL Mask */
#define ACMP_CTL_FCLKDIV_Pos (20) /*!< ACMP_T::CTL0: FCLKDIV Position */
#define ACMP_CTL_FCLKDIV_Msk (0x3ul << ACMP_CTL_FCLKDIV_Pos) /*!< ACMP_T::CTL0: FCLKDIV Mask */
#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL0: HYSSEL Position */
#define ACMP_CTL_HYSSEL_Msk (0x7ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL0: HYSSEL Mask */
#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL0: MODESEL Position */
#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL0: MODESEL Mask */
#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */
#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */
#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */
#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */
#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */
#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */
#define ACMP_VREF_CRV0SEL_Pos (0) /*!< ACMP_T::VREF: CRV0SEL Position */
#define ACMP_VREF_CRV0SEL_Msk (0x3ful << ACMP_VREF_CRV0SEL_Pos) /*!< ACMP_T::VREF: CRV0SEL Mask */
#define ACMP_VREF_CRV0SSEL_Pos (6) /*!< ACMP_T::VREF: CRV0SSEL Position */
#define ACMP_VREF_CRV0SSEL_Msk (0x1ul << ACMP_VREF_CRV0SSEL_Pos) /*!< ACMP_T::VREF: CRV0SSEL Mask */
#define ACMP_VREF_CRV0EN_Pos (8) /*!< ACMP_T::VREF: CRV0EN Position */
#define ACMP_VREF_CRV0EN_Msk (0x1ul << ACMP_VREF_CRV0EN_Pos) /*!< ACMP_T::VREF: CRV0EN Mask */
#define ACMP_VREF_CRV1SEL_Pos (16) /*!< ACMP_T::VREF: CRV1SEL Position */
#define ACMP_VREF_CRV1SEL_Msk (0x3ful << ACMP_VREF_CRV1SEL_Pos) /*!< ACMP_T::VREF: CRV1SEL Mask */
#define ACMP_VREF_CRV1SSEL_Pos (22) /*!< ACMP_T::VREF: CRV1SSEL Position */
#define ACMP_VREF_CRV1SSEL_Msk (0x1ul << ACMP_VREF_CRV1SSEL_Pos) /*!< ACMP_T::VREF: CRV1SSEL Mask */
#define ACMP_VREF_CRV1EN_Pos (24) /*!< ACMP_T::VREF: CRV1EN Position */
#define ACMP_VREF_CRV1EN_Msk (0x1ul << ACMP_VREF_CRV1EN_Pos) /*!< ACMP_T::VREF: CRV1EN Mask */
#define ACMP_VREF_CLAMPEN_Pos (31) /*!< ACMP_T::VREF: CLAMPEN Position */
#define ACMP_VREF_CLAMPEN_Msk (0x1ul << ACMP_VREF_CLAMPEN_Pos) /*!< ACMP_T::VREF: CLAMPEN Mask */
#define ACMP_CALCTL_CALTRG0_Pos (0) /*!< ACMP_T::CALCTL: CALTRG0 Position */
#define ACMP_CALCTL_CALTRG0_Msk (0x1ul << ACMP_CALCTL_CALTRG0_Pos) /*!< ACMP_T::CALCTL: CALTRG0 Mask */
#define ACMP_CALCTL_CALTRG1_Pos (1) /*!< ACMP_T::CALCTL: CALTRG1 Position */
#define ACMP_CALCTL_CALTRG1_Msk (0x1ul << ACMP_CALCTL_CALTRG1_Pos) /*!< ACMP_T::CALCTL: CALTRG1 Mask */
#define ACMP_CALCTL_CALCLK0_Pos (4) /*!< ACMP_T::CALCTL: CALCLK0 Position */
#define ACMP_CALCTL_CALCLK0_Msk (0x3ul << ACMP_CALCTL_CALCLK0_Pos) /*!< ACMP_T::CALCTL: CALCLK0 Mask */
#define ACMP_CALCTL_CALCLK1_Pos (6) /*!< ACMP_T::CALCTL: CALCLK1 Position */
#define ACMP_CALCTL_CALCLK1_Msk (0x3ul << ACMP_CALCTL_CALCLK1_Pos) /*!< ACMP_T::CALCTL: CALCLK1 Mask */
#define ACMP_CALCTL_OFFSETSEL_Pos (8) /*!< ACMP_T::CALCTL: OFFSETSEL Position */
#define ACMP_CALCTL_OFFSETSEL_Msk (0x1ul << ACMP_CALCTL_OFFSETSEL_Pos) /*!< ACMP_T::CALCTL: OFFSETSEL Mask */
#define ACMP_CALCTL_CALRVS_Pos (16) /*!< ACMP_T::CALCTL: CALRVS Position */
#define ACMP_CALCTL_CALRVS_Msk (0x3ul << ACMP_CALCTL_CALRVS_Pos) /*!< ACMP_T::CALCTL: CALRVS Mask */
#define ACMP_CALSTS_DONE0_Pos (0) /*!< ACMP_T::CALSTS: DONE0 Position */
#define ACMP_CALSTS_DONE0_Msk (0x1ul << ACMP_CALSTS_DONE0_Pos) /*!< ACMP_T::CALSTS: DONE0 Mask */
#define ACMP_CALSTS_DONE1_Pos (4) /*!< ACMP_T::CALSTS: DONE1 Position */
#define ACMP_CALSTS_DONE1_Msk (0x1ul << ACMP_CALSTS_DONE1_Pos) /*!< ACMP_T::CALSTS: DONE1 Mask */
#define ACMP_COFF_NCODE0_Pos (0) /*!< ACMP_T::COFF: NCODE0 Position */
#define ACMP_COFF_NCODE0_Msk (0xful << ACMP_COFF_NCODE0_Pos) /*!< ACMP_T::COFF: NCODE0 Mask */
#define ACMP_COFF_NSEL0_Pos (7) /*!< ACMP_T::COFF: NSEL0 Position */
#define ACMP_COFF_NSEL0_Msk (0x1ul << ACMP_COFF_NSEL0_Pos) /*!< ACMP_T::COFF: NSEL0 Mask */
#define ACMP_COFF_PCODE0_Pos (8) /*!< ACMP_T::COFF: PCODE0 Position */
#define ACMP_COFF_PCODE0_Msk (0xful << ACMP_COFF_PCODE0_Pos) /*!< ACMP_T::COFF: PCODE0 Mask */
#define ACMP_COFF_PSEL0_Pos (15) /*!< ACMP_T::COFF: PSEL0 Position */
#define ACMP_COFF_PSEL0_Msk (0x1ul << ACMP_COFF_PSEL0_Pos) /*!< ACMP_T::COFF: PSEL0 Mask */
#define ACMP_COFF_NCODE1_Pos (16) /*!< ACMP_T::COFF: NCODE1 Position */
#define ACMP_COFF_NCODE1_Msk (0xful << ACMP_COFF_NCODE1_Pos) /*!< ACMP_T::COFF: NCODE1 Mask */
#define ACMP_COFF_NSEL1_Pos (23) /*!< ACMP_T::COFF: NSEL1 Position */
#define ACMP_COFF_NSEL1_Msk (0x1ul << ACMP_COFF_NSEL1_Pos) /*!< ACMP_T::COFF: NSEL1 Mask */
#define ACMP_COFF_PCODE1_Pos (24) /*!< ACMP_T::COFF: PCODE1 Position */
#define ACMP_COFF_PCODE1_Msk (0xful << ACMP_COFF_PCODE1_Pos) /*!< ACMP_T::COFF: PCODE1 Mask */
#define ACMP_COFF_PSEL1_Pos (31) /*!< ACMP_T::COFF: PSEL1 Position */
#define ACMP_COFF_PSEL1_Msk (0x1ul << ACMP_COFF_PSEL1_Pos) /*!< ACMP_T::COFF: PSEL1 Mask */
#define ACMP_TEST_CRV0TEST_Pos (0) /*!< ACMP_T::TEST: CRV0TEST Position */
#define ACMP_TEST_CRV0TEST_Msk (0x1ul << ACMP_TEST_CRV0TEST_Pos) /*!< ACMP_T::TEST: CRV0TEST Mask */
#define ACMP_TEST_CRV1TEST_Pos (1) /*!< ACMP_T::TEST: CRV1TEST Position */
#define ACMP_TEST_CRV1TEST_Msk (0x1ul << ACMP_TEST_CRV1TEST_Pos) /*!< ACMP_T::TEST: CRV1TEST Mask */
#define ACMP_TEST_OUTSEL_Pos (4) /*!< ACMP_T::TEST: OUTSEL Position */
#define ACMP_TEST_OUTSEL_Msk (0x1ul << ACMP_TEST_OUTSEL_Pos) /*!< ACMP_T::TEST: OUTSEL Mask */
#define ACMP_TEST_HYSBYPASS_Pos (8) /*!< ACMP_T::TEST: HYSBYPASS Position */
#define ACMP_TEST_HYSBYPASS_Msk (0x1ul << ACMP_TEST_HYSBYPASS_Pos) /*!< ACMP_T::TEST: HYSBYPASS Mask */
#define ACMP_VERSION_MINOR_Pos (0) /*!< ACMP_T::VERSION: MINOR Position */
#define ACMP_VERSION_MINOR_Msk (0xfffful << ACMP_VERSION_MINOR_Pos) /*!< ACMP_T::VERSION: MINOR Mask */
#define ACMP_VERSION_SUB_Pos (16) /*!< ACMP_T::VERSION: SUB Position */
#define ACMP_VERSION_SUB_Msk (0xfful << ACMP_VERSION_SUB_Pos) /*!< ACMP_T::VERSION: SUB Mask */
#define ACMP_VERSION_MAJOR_Pos (24) /*!< ACMP_T::VERSION: MAJOR Position */
#define ACMP_VERSION_MAJOR_Msk (0xfful << ACMP_VERSION_MAJOR_Pos) /*!< ACMP_T::VERSION: MAJOR Mask */
/**@}*/ /* ACMP_CONST */
/**@}*/ /* end of ACMP register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __ACMP_REG_H__ */

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/**************************************************************************//**
* @file bmc_reg.h
* @version V3.00
* @brief BMC register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __BMC_REG_H__
#define __BMC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup BMC Controller
Memory Mapped Structure for BMC Controller
@{ */
typedef struct
{
/**
* @var BMC_T::CTL
* Offset: 0x00 Biphase Mask Coding Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BMCEN |Biphase Mask Coding Enable
* | | |0 = Biphase Mask Coding function is Disabled. It is cleared after current frame data transfer done.
* | | |1 = Biphase Mask Coding function is Enabled.
* |[1] |BWADJ |Bit Width Adjustment 1.5 Time
* | | |0 = The bit time period of Logic '0' is same as Logic '1'.
* | | |1 = The bit time period of Logic '0' is 1.5 times as Logic '1'.
* | | |Note: When this bit is set, the PDMA
* |[2] |PREAM32 |Preamble Bit Number 32
* | | |0 = The bit number of Preamble is 64 bits.
* | | |1 = The bit number of Preamble is 32 bits.
* |[3] |DUMLVL |Dummy Bit Level
* | | |0 = The logic level of dummy bit is LOW.
* | | |1 = The logic level of dummy bit is HIGH.
* |[4] |DMAEN |PDMA Channel Enable
* | | |0 = PDMA function Disabled.
* | | |1 = PDMA function Enabled.
* |[8] |G0CHEN |BMC Group 0 Channel Enable
* | | |0 = BMC Channel 0~3 Disabled.
* | | |1 = BMC Channel 0~3 Enabled.
* |[9] |G1CHEN |BMC Group 1 Channel Enable
* | | |0 = BMC Channel 4~7 Disabled.
* | | |1 = BMC Channel 4~7 Enabled.
* |[10] |G2CHEN |BMC Group 2 Channel Enable
* | | |0 = BMC Channel 8~11 Disabled.
* | | |1 = BMC Channel 8~11 Enabled.
* |[11] |G3CHEN |BMC Group 3 Channel Enable
* | | |0 = BMC Channel 12~15 Disabled.
* | | |1 = BMC Channel 12~15 Enabled.
* |[12] |G4CHEN |BMC Group 4 Channel Enable
* | | |0 = BMC Channel 16~19 Disabled.
* | | |1 = BMC Channel 16~19 Enabled.
* |[13] |G5CHEN |BMC Group 5 Channel Enable
* | | |0 = BMC Channel 20~23 Disabled.
* | | |1 = BMC Channel 20~23 Enabled.
* |[14] |G6CHEN |BMC Group 6 Channel Enable
* | | |0 = BMC Channel 24~27 Disabled.
* | | |1 = BMC Channel 24~27 Enabled.
* |[15] |G7CHEN |BMC Group 7 Channel Enable
* | | |0 = BMC Channel 28~31 Disabled.
* | | |1 = BMC Channel 28~31 Enabled.
* |[24:16] |BTDIV |Bit Time Divider
* | | |These bit field indicates the half bit time divider for Biphase Mask Coding bit.
* | | |For example, if the HCLK is 200 MHz, the divider can be set as 0x64
* | | |It will generate 2 MHz reference clock and the Biphase Mask Coding transmitting data is sent according the reference divided clock.
* @var BMC_T::DNUM0
* Offset: 0x04 Biphase Mask Coding Dummy Bit Number Channel Group 0~3 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DNUMG0 |Dummy Number for Channel 0~3
* | | |These bit field defines the dummy bit number for the group of channel 0~3
* | | |Each dummy bit equal 8 bit data period.
* |[15:8] |DNUMG1 |Dummy Number for Channel 4~7
* | | |These bit field defines the dummy bit number for the group of channel 4~7
* | | |Each dummy bit equal 8 bit data period.
* |[23:16] |DNUMG2 |Dummy Number for Channel 8~11
* | | |These bit field defines the dummy bit number for the group of channel 8~11
* | | |Each dummy bit equal 8 bit data period.
* |[31:24] |DNUMG3 |Dummy Number for Channel 12~15
* | | |These bit field defines the dummy bit number for the group of channel 12~15
* | | |Each dummy bit equal 8 bit data period.
* @var BMC_T::DNUM1
* Offset: 0x08 Biphase Mask Coding Dummy Bit Number Channel Group 4~7 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DNUMG4 |Dummy Number for Channel 16~19
* | | |These bit field defines the dummy bit number for the group of channel 16~19
* | | |Each dummy bit equal 8 bit data period.
* |[15:8] |DNUMG5 |Dummy Number for Channel 20~23
* | | |These bit field defines the dummy bit number for the group of channel 20~23
* | | |Each dummy bit equal 8 bit data period.
* |[23:16] |DNUMG6 |Dummy Number for Channel 24~27
* | | |These bit field defines the dummy bit number for the group of channel 24~27
* | | |Each dummy bit equal 8 bit data period.
* |[31:24] |DNUMG7 |Dummy Number for Channel 28~31
* | | |These bit field defines the dummy bit number for the group of channel 28~31
* | | |Each dummy bit equal 8 bit data period.
* @var BMC_T::INTEN
* Offset: 0x0C Biphase Mask Coding Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FTXDIEN |Frame Transmit Done Interrupt Enable Bit
* | | |0 = Frame transmit done interrupt Disabled.
* | | |1 = Frame transmit done interrupt Enabled.
* |[1] |TXUNDIEN |Transmit Data Under Run Interrupt Enable Bit
* | | |0 = Transmit data register under run interrupt Disabled.
* | | |1 = Transmit data register under run interrupt Enabled.
* @var BMC_T::INTSTS
* Offset: 0x10 Biphase Mask Coding Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FTXDIF |Frame Transmit Done Interrupt Flag
* | | |0 = No frame transmit done interrupt flag.
* | | |1 = Frame transmit done interrupt flag. Write 1 to clear.
* |[1] |TXUNDIF |Transmit Data Register Under Run Interrupt Flag
* | | |0 = No transmit data register under run interrupt flag.
* | | |1 = Transmit data register under interrupt flag. This bit is the OR function of BMC_INTSTS[15:8].
* |[8] |G0TXUND |Channel 0~3 Transmit Data Under Run
* | | |0 = No Transmit data under run active in one of channel 0~3.
* | | |1 = Transmit data under run active in one of channel 0~3. Write 1 to clear.
* |[9] |G1TXUND |Channel 4~7 Transmit Data Under Run
* | | |0 = No Transmit data under run active in one of channel 4~7.
* | | |1 = Transmit data under run active in one of channel 4~7. Write 1 to clear.
* |[10] |G2TXUND |Channel 8~11 Transmit Data Under Run
* | | |0 = No Transmit data under run active in one of channel 8~11.
* | | |1 = Transmit data under run active in one of channel 8~11. Write 1 to clear.
* |[10] |G3TXUND |Channel 12~15 Transmit Data Under Run
* | | |0 = No Transmit data under run active in one of channel 12~15.
* | | |1 = Transmit data under run active in one of channel 12~15. Write 1 to clear.
* |[12] |G4TXUND |Channel 16~19 Transmit Data Under Run
* | | |0 = No Transmit data under run active in one of channel 16~19.
* | | |1 = Transmit data under run active in one of channel 16~19. Write 1 to clear.
* |[13] |G5TXUND |Channel 20~23 Transmit Data Under Run
* | | |0 = No Transmit data under run active in one of channel 20~23.
* | | |1 = Transmit data under run active in one of channel 20~23. Write 1 to clear.
* |[14] |G6TXUND |Channel 24~27 Transmit Data Under Run
* | | |0 = No Transmit data under run active in one of channel 24~27.
* | | |1 = Transmit data under run active in one of channel 24~27. Write 1 to clear.
* |[15] |G7TXUND |Channel 28~31 Transmit Data Under Run
* | | |0 = No Transmit data under run active in one of channel 28~31.
* | | |1 = Transmit data under run active in one of channel 28~31. Write 1 to clear.
* @var BMC_T::CHEMPTY
* Offset: 0x14 Biphase Mask Coding Channel Done Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CH0EPT |BMC Channel 0 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[1] |CH1EPT |BMC Channel 1 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[2] |CH2EPT |BMC Channel 2 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[3] |CH3EPT |BMC Channel 3 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[4] |CH4EPT |BMC Channel 4 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[5] |CH5EPT |BMC Channel 5 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[6] |CH6EPT |BMC Channel 6 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[7] |CH7EPT |BMC Channel 7 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[8] |CH8EPT |BMC Channel 8 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[9] |CH9EPT |BMC Channel 9 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[10] |CH10EPT |BMC Channel 10 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[11] |CH11EPT |BMC Channel 11 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[12] |CH12EPT |BMC Channel 12 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[13] |CH13EPT |BMC Channel 13 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[14] |CH14EPT |BMC Channel 14 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[15] |CH15EPT |BMC Channel 15 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[16] |CH16EPT |BMC Channel 16 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[17] |CH17EPT |BMC Channel 17 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[18] |CH18EPT |BMC Channel 18 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[19] |CH19EPT |BMC Channel 19 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[20] |CH20EPT |BMC Channel 20 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[21] |CH21EPT |BMC Channel 21 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[22] |CH22EPT |BMC Channel 22 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[23] |CH23EPT |BMC Channel 23 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[24] |CH24EPT |BMC Channel 24 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[25] |CH25EPT |BMC Channel 25 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[26] |CH26EPT |BMC Channel 26 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[27] |CH27EPT |BMC Channel 27 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[28] |CH28EPT |BMC Channel 28 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[29] |CH29EPT |BMC Channel 29 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[30] |CH30EPT |BMC Channel 30 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* |[31] |CH31EPT |BMC Channel 31 Current FIFO Empty
* | | |0 = The current transmitted FIFO no empty.
* | | |1 = The current transmitted FIFO empty.
* | | |Note: This bit be clear automatically by writing the relative channel data (byte).
* @var BMC_T::TXDATG0
* Offset: 0x18 Biphase Mask Coding Transmit Data Group 0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |CH0_TXDAT |Biphase Mask Coding Channel 0 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 0.
* |[12:8] |CH1_TXDAT |Biphase Mask Coding Channel 1 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 1.
* |[20:16] |CH2_TXDAT |Biphase Mask Coding Channel 2 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 2.
* |[28:24] |CH3_TXDAT |Biphase Mask Coding Channel 3 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 3.
* @var BMC_T::TXDATG1
* Offset: 0x1C Biphase Mask Coding Transmit Data Group 1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |CH4_TXDAT |Biphase Mask Coding Channel 4 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 4.
* |[12:8] |CH5_TXDAT |Biphase Mask Coding Channel 5 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 5.
* |[20:16] |CH6_TXDAT |Biphase Mask Coding Channel 6 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 6.
* |[28:24] |CH7_TXDAT |Biphase Mask Coding Channel 7 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 7.
* @var BMC_T::TXDATG2
* Offset: 0x20 Biphase Mask Coding Transmit Data Group 2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |CH8_TXDAT |Biphase Mask Coding Channel 8 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 8.
* |[12:8] |CH9_TXDAT |Biphase Mask Coding Channel 9 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 9.
* |[20:16] |CH10_TXDAT|Biphase Mask Coding Channel 10 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 10.
* |[28:24] |CH11_TXDAT|Biphase Mask Coding Channel 11 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 11.
* @var BMC_T::TXDATG3
* Offset: 0x24 Biphase Mask Coding Transmit Data Group 3 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |CH12_TXDAT|Biphase Mask Coding Channel 12 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 12.
* |[12:8] |CH13_TXDAT|Biphase Mask Coding Channel 13 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 13.
* |[20:16] |CH14_TXDAT|Biphase Mask Coding Channel 14 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 14.
* |[28:24] |CH15_TXDAT|Biphase Mask Coding Channel 15 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 15.
* @var BMC_T::TXDATG4
* Offset: 0x28 Biphase Mask Coding Transmit Data Group 4 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |CH16_TXDAT|Biphase Mask Coding Channel 16 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 16.
* |[12:8] |CH17_TXDAT|Biphase Mask Coding Channel 17 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 17.
* |[20:16] |CH18_TXDAT|Biphase Mask Coding Channel 18 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 18.
* |[28:24] |CH19_TXDAT|Biphase Mask Coding Channel 19 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 19.
* @var BMC_T::TXDATG5
* Offset: 0x2C Biphase Mask Coding Transmit Data Group 5 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |CH20_TXDAT|Biphase Mask Coding Channel 20 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 20.
* |[12:8] |CH21_TXDAT|Biphase Mask Coding Channel 21 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 21.
* |[20:16] |CH22_TXDAT|Biphase Mask Coding Channel 22 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 22.
* |[28:24] |CH23_TXDAT|Biphase Mask Coding Channel 23 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 23.
* @var BMC_T::TXDATG6
* Offset: 0x30 Biphase Mask Coding Transmit Data Group 6 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |CH24_TXDAT|Biphase Mask Coding Channel 24 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 24.
* |[12:8] |CH25_TXDAT|Biphase Mask Coding Channel 25 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 25.
* |[20:16] |CH26_TXDAT|Biphase Mask Coding Channel 26 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 26.
* |[28:24] |CH27_TXDAT|Biphase Mask Coding Channel 27 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 27.
* @var BMC_T::TXDATG7
* Offset: 0x34 Biphase Mask Coding Transmit Data Group 7 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |CH28_TXDAT|Biphase Mask Coding Channel 28 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 28.
* |[12:8] |CH29_TXDAT|Biphase Mask Coding Channel 29 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 29.
* |[20:16] |CH30_TXDAT|Biphase Mask Coding Channel 30 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 30.
* |[28:24] |CH31_TXDAT|Biphase Mask Coding Channel 31 Transmit Data
* | | |The bits field indicates the transmit data buffer for channel 31.
*/
__IO uint32_t CTL; /*!< [0x0000] Biphase Mask Coding Control Register */
__IO uint32_t DNUM0; /*!< [0x0004] Biphase Mask Coding Dummy Bit Number Channel Group 0~3 Register */
__IO uint32_t DNUM1; /*!< [0x0008] Biphase Mask Coding Dummy Bit Number Channel Group 4~7 Register */
__IO uint32_t INTEN; /*!< [0x000c] Biphase Mask Coding Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x0010] Biphase Mask Coding Interrupt Status Register */
__IO uint32_t CHEMPTY; /*!< [0x0014] Biphase Mask Coding Channel Done Status Register */
__O uint32_t TXDATG0; /*!< [0x0018] Biphase Mask Coding Transmit Data Group 0 Register */
__O uint32_t TXDATG1; /*!< [0x001c] Biphase Mask Coding Transmit Data Group 1 Register */
__O uint32_t TXDATG2; /*!< [0x0020] Biphase Mask Coding Transmit Data Group 2 Register */
__O uint32_t TXDATG3; /*!< [0x0024] Biphase Mask Coding Transmit Data Group 3 Register */
__O uint32_t TXDATG4; /*!< [0x0028] Biphase Mask Coding Transmit Data Group 4 Register */
__O uint32_t TXDATG5; /*!< [0x002c] Biphase Mask Coding Transmit Data Group 5 Register */
__O uint32_t TXDATG6; /*!< [0x0030] Biphase Mask Coding Transmit Data Group 6 Register */
__O uint32_t TXDATG7; /*!< [0x0034] Biphase Mask Coding Transmit Data Group 7 Register */
} BMC_T;
/**
@addtogroup BMC_CONST BMC Bit Field Definition
Constant Definitions for BMC Controller
@{ */
#define BMC_CTL_BMCEN_Pos (0) /*!< BMC_T::CTL: BMCEN Position */
#define BMC_CTL_BMCEN_Msk (0x1ul << BMC_CTL_BMCEN_Pos) /*!< BMC_T::CTL: BMCEN Mask */
#define BMC_CTL_BWADJ_Pos (1) /*!< BMC_T::CTL: BWADJ Position */
#define BMC_CTL_BWADJ_Msk (0x1ul << BMC_CTL_BWADJ_Pos) /*!< BMC_T::CTL: BWADJ Mask */
#define BMC_CTL_PREAM32_Pos (2) /*!< BMC_T::CTL: PREAM32 Position */
#define BMC_CTL_PREAM32_Msk (0x1ul << BMC_CTL_PREAM32_Pos) /*!< BMC_T::CTL: PREAM32 Mask */
#define BMC_CTL_DUMLVL_Pos (3) /*!< BMC_T::CTL: DUMLVL Position */
#define BMC_CTL_DUMLVL_Msk (0x1ul << BMC_CTL_DUMLVL_Pos) /*!< BMC_T::CTL: DUMLVL Mask */
#define BMC_CTL_DMAEN_Pos (4) /*!< BMC_T::CTL: DMAEN Position */
#define BMC_CTL_DMAEN_Msk (0x1ul << BMC_CTL_DMAEN_Pos) /*!< BMC_T::CTL: DMAEN Mask */
#define BMC_CTL_G0CHEN_Pos (8) /*!< BMC_T::CTL: G0CHEN Position */
#define BMC_CTL_G0CHEN_Msk (0x1ul << BMC_CTL_G0CHEN_Pos) /*!< BMC_T::CTL: G0CHEN Mask */
#define BMC_CTL_G1CHEN_Pos (9) /*!< BMC_T::CTL: G1CHEN Position */
#define BMC_CTL_G1CHEN_Msk (0x1ul << BMC_CTL_G1CHEN_Pos) /*!< BMC_T::CTL: G1CHEN Mask */
#define BMC_CTL_G2CHEN_Pos (10) /*!< BMC_T::CTL: G2CHEN Position */
#define BMC_CTL_G2CHEN_Msk (0x1ul << BMC_CTL_G2CHEN_Pos) /*!< BMC_T::CTL: G2CHEN Mask */
#define BMC_CTL_G3CHEN_Pos (11) /*!< BMC_T::CTL: G3CHEN Position */
#define BMC_CTL_G3CHEN_Msk (0x1ul << BMC_CTL_G3CHEN_Pos) /*!< BMC_T::CTL: G3CHEN Mask */
#define BMC_CTL_G4CHEN_Pos (12) /*!< BMC_T::CTL: G4CHEN Position */
#define BMC_CTL_G4CHEN_Msk (0x1ul << BMC_CTL_G4CHEN_Pos) /*!< BMC_T::CTL: G4CHEN Mask */
#define BMC_CTL_G5CHEN_Pos (13) /*!< BMC_T::CTL: G5CHEN Position */
#define BMC_CTL_G5CHEN_Msk (0x1ul << BMC_CTL_G5CHEN_Pos) /*!< BMC_T::CTL: G5CHEN Mask */
#define BMC_CTL_G6CHEN_Pos (14) /*!< BMC_T::CTL: G6CHEN Position */
#define BMC_CTL_G6CHEN_Msk (0x1ul << BMC_CTL_G6CHEN_Pos) /*!< BMC_T::CTL: G6CHEN Mask */
#define BMC_CTL_G7CHEN_Pos (15) /*!< BMC_T::CTL: G7CHEN Position */
#define BMC_CTL_G7CHEN_Msk (0x1ul << BMC_CTL_G7CHEN_Pos) /*!< BMC_T::CTL: G7CHEN Mask */
#define BMC_CTL_BTDIV_Pos (16) /*!< BMC_T::CTL: BTDIV Position */
#define BMC_CTL_BTDIV_Msk (0x1fful << BMC_CTL_BTDIV_Pos) /*!< BMC_T::CTL: BTDIV Mask */
#define BMC_DNUM0_DNUMG0_Pos (0) /*!< BMC_T::DNUM0: DNUMG0 Position */
#define BMC_DNUM0_DNUMG0_Msk (0xfful << BMC_DNUM0_DNUMG0_Pos) /*!< BMC_T::DNUM0: DNUMG0 Mask */
#define BMC_DNUM0_DNUMG1_Pos (8) /*!< BMC_T::DNUM0: DNUMG1 Position */
#define BMC_DNUM0_DNUMG1_Msk (0xfful << BMC_DNUM0_DNUMG1_Pos) /*!< BMC_T::DNUM0: DNUMG1 Mask */
#define BMC_DNUM0_DNUMG2_Pos (16) /*!< BMC_T::DNUM0: DNUMG2 Position */
#define BMC_DNUM0_DNUMG2_Msk (0xfful << BMC_DNUM0_DNUMG2_Pos) /*!< BMC_T::DNUM0: DNUMG2 Mask */
#define BMC_DNUM0_DNUMG3_Pos (24) /*!< BMC_T::DNUM0: DNUMG3 Position */
#define BMC_DNUM0_DNUMG3_Msk (0xfful << BMC_DNUM0_DNUMG3_Pos) /*!< BMC_T::DNUM0: DNUMG3 Mask */
#define BMC_DNUM1_DNUMG4_Pos (0) /*!< BMC_T::DNUM1: DNUMG4 Position */
#define BMC_DNUM1_DNUMG4_Msk (0xfful << BMC_DNUM1_DNUMG4_Pos) /*!< BMC_T::DNUM1: DNUMG4 Mask */
#define BMC_DNUM1_DNUMG5_Pos (8) /*!< BMC_T::DNUM1: DNUMG5 Position */
#define BMC_DNUM1_DNUMG5_Msk (0xfful << BMC_DNUM1_DNUMG5_Pos) /*!< BMC_T::DNUM1: DNUMG5 Mask */
#define BMC_DNUM1_DNUMG6_Pos (16) /*!< BMC_T::DNUM1: DNUMG6 Position */
#define BMC_DNUM1_DNUMG6_Msk (0xfful << BMC_DNUM1_DNUMG6_Pos) /*!< BMC_T::DNUM1: DNUMG6 Mask */
#define BMC_DNUM1_DNUMG7_Pos (24) /*!< BMC_T::DNUM1: DNUMG7 Position */
#define BMC_DNUM1_DNUMG7_Msk (0xfful << BMC_DNUM1_DNUMG7_Pos) /*!< BMC_T::DNUM1: DNUMG7 Mask */
#define BMC_INTEN_FTXDIEN_Pos (0) /*!< BMC_T::INTEN: FTXDIEN Position */
#define BMC_INTEN_FTXDIEN_Msk (0x1ul << BMC_INTEN_FTXDIEN_Pos) /*!< BMC_T::INTEN: FTXDIEN Mask */
#define BMC_INTEN_TXUNDIEN_Pos (1) /*!< BMC_T::INTEN: TXUNDIEN Position */
#define BMC_INTEN_TXUNDIEN_Msk (0x1ul << BMC_INTEN_TXUNDIEN_Pos) /*!< BMC_T::INTEN: TXUNDIEN Mask */
#define BMC_INTSTS_FTXDIF_Pos (0) /*!< BMC_T::INTSTS: FTXDIF Position */
#define BMC_INTSTS_FTXDIF_Msk (0x1ul << BMC_INTSTS_FTXDIF_Pos) /*!< BMC_T::INTSTS: FTXDIF Mask */
#define BMC_INTSTS_TXUNDIF_Pos (1) /*!< BMC_T::INTSTS: TXUNDIF Position */
#define BMC_INTSTS_TXUNDIF_Msk (0x1ul << BMC_INTSTS_TXUNDIF_Pos) /*!< BMC_T::INTSTS: TXUNDIF Mask */
#define BMC_INTSTS_G0TXUND_Pos (8) /*!< BMC_T::INTSTS: G0TXUND Position */
#define BMC_INTSTS_G0TXUND_Msk (0x1ul << BMC_INTSTS_G0TXUND_Pos) /*!< BMC_T::INTSTS: G0TXUND Mask */
#define BMC_INTSTS_G1TXUND_Pos (9) /*!< BMC_T::INTSTS: G1TXUND Position */
#define BMC_INTSTS_G1TXUND_Msk (0x1ul << BMC_INTSTS_G1TXUND_Pos) /*!< BMC_T::INTSTS: G1TXUND Mask */
#define BMC_INTSTS_G2TXUND_Pos (10) /*!< BMC_T::INTSTS: G2TXUND Position */
#define BMC_INTSTS_G2TXUND_Msk (0x1ul << BMC_INTSTS_G2TXUND_Pos) /*!< BMC_T::INTSTS: G2TXUND Mask */
#define BMC_INTSTS_G3TXUND_Pos (11) /*!< BMC_T::INTSTS: G3TXUND Position */
#define BMC_INTSTS_G3TXUND_Msk (0x1ul << BMC_INTSTS_G3TXUND_Pos) /*!< BMC_T::INTSTS: G3TXUND Mask */
#define BMC_INTSTS_G4TXUND_Pos (12) /*!< BMC_T::INTSTS: G4TXUND Position */
#define BMC_INTSTS_G4TXUND_Msk (0x1ul << BMC_INTSTS_G4TXUND_Pos) /*!< BMC_T::INTSTS: G4TXUND Mask */
#define BMC_INTSTS_G5TXUND_Pos (13) /*!< BMC_T::INTSTS: G5TXUND Position */
#define BMC_INTSTS_G5TXUND_Msk (0x1ul << BMC_INTSTS_G5TXUND_Pos) /*!< BMC_T::INTSTS: G5TXUND Mask */
#define BMC_INTSTS_G6TXUND_Pos (14) /*!< BMC_T::INTSTS: G6TXUND Position */
#define BMC_INTSTS_G6TXUND_Msk (0x1ul << BMC_INTSTS_G6TXUND_Pos) /*!< BMC_T::INTSTS: G6TXUND Mask */
#define BMC_INTSTS_G7TXUND_Pos (15) /*!< BMC_T::INTSTS: G7TXUND Position */
#define BMC_INTSTS_G7TXUND_Msk (0x1ul << BMC_INTSTS_G7TXUND_Pos) /*!< BMC_T::INTSTS: G7TXUND Mask */
#define BMC_CHEMPTY_CH0EPT_Pos (0) /*!< BMC_T::CHEMPTY: CH0EPT Position */
#define BMC_CHEMPTY_CH0EPT_Msk (0x1ul << BMC_CHEMPTY_CH0EPT_Pos) /*!< BMC_T::CHEMPTY: CH0EPT Mask */
#define BMC_CHEMPTY_CH1EPT_Pos (1) /*!< BMC_T::CHEMPTY: CH1EPT Position */
#define BMC_CHEMPTY_CH1EPT_Msk (0x1ul << BMC_CHEMPTY_CH1EPT_Pos) /*!< BMC_T::CHEMPTY: CH1EPT Mask */
#define BMC_CHEMPTY_CH2EPT_Pos (2) /*!< BMC_T::CHEMPTY: CH2EPT Position */
#define BMC_CHEMPTY_CH2EPT_Msk (0x1ul << BMC_CHEMPTY_CH2EPT_Pos) /*!< BMC_T::CHEMPTY: CH2EPT Mask */
#define BMC_CHEMPTY_CH3EPT_Pos (3) /*!< BMC_T::CHEMPTY: CH3EPT Position */
#define BMC_CHEMPTY_CH3EPT_Msk (0x1ul << BMC_CHEMPTY_CH3EPT_Pos) /*!< BMC_T::CHEMPTY: CH3EPT Mask */
#define BMC_CHEMPTY_CH4EPT_Pos (4) /*!< BMC_T::CHEMPTY: CH4EPT Position */
#define BMC_CHEMPTY_CH4EPT_Msk (0x1ul << BMC_CHEMPTY_CH4EPT_Pos) /*!< BMC_T::CHEMPTY: CH4EPT Mask */
#define BMC_CHEMPTY_CH5EPT_Pos (5) /*!< BMC_T::CHEMPTY: CH5EPT Position */
#define BMC_CHEMPTY_CH5EPT_Msk (0x1ul << BMC_CHEMPTY_CH5EPT_Pos) /*!< BMC_T::CHEMPTY: CH5EPT Mask */
#define BMC_CHEMPTY_CH6EPT_Pos (6) /*!< BMC_T::CHEMPTY: CH6EPT Position */
#define BMC_CHEMPTY_CH6EPT_Msk (0x1ul << BMC_CHEMPTY_CH6EPT_Pos) /*!< BMC_T::CHEMPTY: CH6EPT Mask */
#define BMC_CHEMPTY_CH7EPT_Pos (7) /*!< BMC_T::CHEMPTY: CH7EPT Position */
#define BMC_CHEMPTY_CH7EPT_Msk (0x1ul << BMC_CHEMPTY_CH7EPT_Pos) /*!< BMC_T::CHEMPTY: CH7EPT Mask */
#define BMC_CHEMPTY_CH8EPT_Pos (8) /*!< BMC_T::CHEMPTY: CH8EPT Position */
#define BMC_CHEMPTY_CH8EPT_Msk (0x1ul << BMC_CHEMPTY_CH8EPT_Pos) /*!< BMC_T::CHEMPTY: CH8EPT Mask */
#define BMC_CHEMPTY_CH9EPT_Pos (9) /*!< BMC_T::CHEMPTY: CH9EPT Position */
#define BMC_CHEMPTY_CH9EPT_Msk (0x1ul << BMC_CHEMPTY_CH9EPT_Pos) /*!< BMC_T::CHEMPTY: CH9EPT Mask */
#define BMC_CHEMPTY_CH10EPT_Pos (10) /*!< BMC_T::CHEMPTY: CH10EPT Position */
#define BMC_CHEMPTY_CH10EPT_Msk (0x1ul << BMC_CHEMPTY_CH10EPT_Pos) /*!< BMC_T::CHEMPTY: CH10EPT Mask */
#define BMC_CHEMPTY_CH11EPT_Pos (11) /*!< BMC_T::CHEMPTY: CH11EPT Position */
#define BMC_CHEMPTY_CH11EPT_Msk (0x1ul << BMC_CHEMPTY_CH11EPT_Pos) /*!< BMC_T::CHEMPTY: CH11EPT Mask */
#define BMC_CHEMPTY_CH12EPT_Pos (12) /*!< BMC_T::CHEMPTY: CH12EPT Position */
#define BMC_CHEMPTY_CH12EPT_Msk (0x1ul << BMC_CHEMPTY_CH12EPT_Pos) /*!< BMC_T::CHEMPTY: CH12EPT Mask */
#define BMC_CHEMPTY_CH13EPT_Pos (13) /*!< BMC_T::CHEMPTY: CH13EPT Position */
#define BMC_CHEMPTY_CH13EPT_Msk (0x1ul << BMC_CHEMPTY_CH13EPT_Pos) /*!< BMC_T::CHEMPTY: CH13EPT Mask */
#define BMC_CHEMPTY_CH14EPT_Pos (14) /*!< BMC_T::CHEMPTY: CH14EPT Position */
#define BMC_CHEMPTY_CH14EPT_Msk (0x1ul << BMC_CHEMPTY_CH14EPT_Pos) /*!< BMC_T::CHEMPTY: CH14EPT Mask */
#define BMC_CHEMPTY_CH15EPT_Pos (15) /*!< BMC_T::CHEMPTY: CH15EPT Position */
#define BMC_CHEMPTY_CH15EPT_Msk (0x1ul << BMC_CHEMPTY_CH15EPT_Pos) /*!< BMC_T::CHEMPTY: CH15EPT Mask */
#define BMC_CHEMPTY_CH16EPT_Pos (16) /*!< BMC_T::CHEMPTY: CH16EPT Position */
#define BMC_CHEMPTY_CH16EPT_Msk (0x1ul << BMC_CHEMPTY_CH16EPT_Pos) /*!< BMC_T::CHEMPTY: CH16EPT Mask */
#define BMC_CHEMPTY_CH17EPT_Pos (17) /*!< BMC_T::CHEMPTY: CH17EPT Position */
#define BMC_CHEMPTY_CH17EPT_Msk (0x1ul << BMC_CHEMPTY_CH17EPT_Pos) /*!< BMC_T::CHEMPTY: CH17EPT Mask */
#define BMC_CHEMPTY_CH18EPT_Pos (18) /*!< BMC_T::CHEMPTY: CH18EPT Position */
#define BMC_CHEMPTY_CH18EPT_Msk (0x1ul << BMC_CHEMPTY_CH18EPT_Pos) /*!< BMC_T::CHEMPTY: CH18EPT Mask */
#define BMC_CHEMPTY_CH19EPT_Pos (19) /*!< BMC_T::CHEMPTY: CH19EPT Position */
#define BMC_CHEMPTY_CH19EPT_Msk (0x1ul << BMC_CHEMPTY_CH19EPT_Pos) /*!< BMC_T::CHEMPTY: CH19EPT Mask */
#define BMC_CHEMPTY_CH20EPT_Pos (20) /*!< BMC_T::CHEMPTY: CH20EPT Position */
#define BMC_CHEMPTY_CH20EPT_Msk (0x1ul << BMC_CHEMPTY_CH20EPT_Pos) /*!< BMC_T::CHEMPTY: CH20EPT Mask */
#define BMC_CHEMPTY_CH21EPT_Pos (21) /*!< BMC_T::CHEMPTY: CH21EPT Position */
#define BMC_CHEMPTY_CH21EPT_Msk (0x1ul << BMC_CHEMPTY_CH21EPT_Pos) /*!< BMC_T::CHEMPTY: CH21EPT Mask */
#define BMC_CHEMPTY_CH22EPT_Pos (22) /*!< BMC_T::CHEMPTY: CH22EPT Position */
#define BMC_CHEMPTY_CH22EPT_Msk (0x1ul << BMC_CHEMPTY_CH22EPT_Pos) /*!< BMC_T::CHEMPTY: CH22EPT Mask */
#define BMC_CHEMPTY_CH23EPT_Pos (23) /*!< BMC_T::CHEMPTY: CH23EPT Position */
#define BMC_CHEMPTY_CH23EPT_Msk (0x1ul << BMC_CHEMPTY_CH23EPT_Pos) /*!< BMC_T::CHEMPTY: CH23EPT Mask */
#define BMC_CHEMPTY_CH24EPT_Pos (24) /*!< BMC_T::CHEMPTY: CH24EPT Position */
#define BMC_CHEMPTY_CH24EPT_Msk (0x1ul << BMC_CHEMPTY_CH24EPT_Pos) /*!< BMC_T::CHEMPTY: CH24EPT Mask */
#define BMC_CHEMPTY_CH25EPT_Pos (25) /*!< BMC_T::CHEMPTY: CH25EPT Position */
#define BMC_CHEMPTY_CH25EPT_Msk (0x1ul << BMC_CHEMPTY_CH25EPT_Pos) /*!< BMC_T::CHEMPTY: CH25EPT Mask */
#define BMC_CHEMPTY_CH26EPT_Pos (26) /*!< BMC_T::CHEMPTY: CH26EPT Position */
#define BMC_CHEMPTY_CH26EPT_Msk (0x1ul << BMC_CHEMPTY_CH26EPT_Pos) /*!< BMC_T::CHEMPTY: CH26EPT Mask */
#define BMC_CHEMPTY_CH27EPT_Pos (27) /*!< BMC_T::CHEMPTY: CH27EPT Position */
#define BMC_CHEMPTY_CH27EPT_Msk (0x1ul << BMC_CHEMPTY_CH27EPT_Pos) /*!< BMC_T::CHEMPTY: CH27EPT Mask */
#define BMC_CHEMPTY_CH28EPT_Pos (28) /*!< BMC_T::CHEMPTY: CH28EPT Position */
#define BMC_CHEMPTY_CH28EPT_Msk (0x1ul << BMC_CHEMPTY_CH28EPT_Pos) /*!< BMC_T::CHEMPTY: CH28EPT Mask */
#define BMC_CHEMPTY_CH29EPT_Pos (29) /*!< BMC_T::CHEMPTY: CH29EPT Position */
#define BMC_CHEMPTY_CH29EPT_Msk (0x1ul << BMC_CHEMPTY_CH29EPT_Pos) /*!< BMC_T::CHEMPTY: CH29EPT Mask */
#define BMC_CHEMPTY_CH30EPT_Pos (30) /*!< BMC_T::CHEMPTY: CH30EPT Position */
#define BMC_CHEMPTY_CH30EPT_Msk (0x1ul << BMC_CHEMPTY_CH30EPT_Pos) /*!< BMC_T::CHEMPTY: CH30EPT Mask */
#define BMC_CHEMPTY_CH31EPT_Pos (31) /*!< BMC_T::CHEMPTY: CH31EPT Position */
#define BMC_CHEMPTY_CH31EPT_Msk (0x1ul << BMC_CHEMPTY_CH31EPT_Pos) /*!< BMC_T::CHEMPTY: CH31EPT Mask */
#define BMC_TXDATG0_CH0_TXDAT_Pos (0) /*!< BMC_T::TXDATG0: CH0_TXDAT Position */
#define BMC_TXDATG0_CH0_TXDAT_Msk (0x1ful << BMC_TXDATG0_CH0_TXDAT_Pos) /*!< BMC_T::TXDATG0: CH0_TXDAT Mask */
#define BMC_TXDATG0_CH1_TXDAT_Pos (8) /*!< BMC_T::TXDATG0: CH1_TXDAT Position */
#define BMC_TXDATG0_CH1_TXDAT_Msk (0x1ful << BMC_TXDATG0_CH1_TXDAT_Pos) /*!< BMC_T::TXDATG0: CH1_TXDAT Mask */
#define BMC_TXDATG0_CH2_TXDAT_Pos (16) /*!< BMC_T::TXDATG0: CH2_TXDAT Position */
#define BMC_TXDATG0_CH2_TXDAT_Msk (0x1ful << BMC_TXDATG0_CH2_TXDAT_Pos) /*!< BMC_T::TXDATG0: CH2_TXDAT Mask */
#define BMC_TXDATG0_CH3_TXDAT_Pos (24) /*!< BMC_T::TXDATG0: CH3_TXDAT Position */
#define BMC_TXDATG0_CH3_TXDAT_Msk (0x1ful << BMC_TXDATG0_CH3_TXDAT_Pos) /*!< BMC_T::TXDATG0: CH3_TXDAT Mask */
#define BMC_TXDATG1_CH4_TXDAT_Pos (0) /*!< BMC_T::TXDATG1: CH4_TXDAT Position */
#define BMC_TXDATG1_CH4_TXDAT_Msk (0x1ful << BMC_TXDATG1_CH4_TXDAT_Pos) /*!< BMC_T::TXDATG1: CH4_TXDAT Mask */
#define BMC_TXDATG1_CH5_TXDAT_Pos (8) /*!< BMC_T::TXDATG1: CH5_TXDAT Position */
#define BMC_TXDATG1_CH5_TXDAT_Msk (0x1ful << BMC_TXDATG1_CH5_TXDAT_Pos) /*!< BMC_T::TXDATG1: CH5_TXDAT Mask */
#define BMC_TXDATG1_CH6_TXDAT_Pos (16) /*!< BMC_T::TXDATG1: CH6_TXDAT Position */
#define BMC_TXDATG1_CH6_TXDAT_Msk (0x1ful << BMC_TXDATG1_CH6_TXDAT_Pos) /*!< BMC_T::TXDATG1: CH6_TXDAT Mask */
#define BMC_TXDATG1_CH7_TXDAT_Pos (24) /*!< BMC_T::TXDATG1: CH7_TXDAT Position */
#define BMC_TXDATG1_CH7_TXDAT_Msk (0x1ful << BMC_TXDATG1_CH7_TXDAT_Pos) /*!< BMC_T::TXDATG1: CH7_TXDAT Mask */
#define BMC_TXDATG2_CH8_TXDAT_Pos (0) /*!< BMC_T::TXDATG2: CH8_TXDAT Position */
#define BMC_TXDATG2_CH8_TXDAT_Msk (0x1ful << BMC_TXDATG2_CH8_TXDAT_Pos) /*!< BMC_T::TXDATG2: CH8_TXDAT Mask */
#define BMC_TXDATG2_CH9_TXDAT_Pos (8) /*!< BMC_T::TXDATG2: CH9_TXDAT Position */
#define BMC_TXDATG2_CH9_TXDAT_Msk (0x1ful << BMC_TXDATG2_CH9_TXDAT_Pos) /*!< BMC_T::TXDATG2: CH9_TXDAT Mask */
#define BMC_TXDATG2_CH10_TXDAT_Pos (16) /*!< BMC_T::TXDATG2: CH10_TXDAT Position */
#define BMC_TXDATG2_CH10_TXDAT_Msk (0x1ful << BMC_TXDATG2_CH10_TXDAT_Pos) /*!< BMC_T::TXDATG2: CH10_TXDAT Mask */
#define BMC_TXDATG2_CH11_TXDAT_Pos (24) /*!< BMC_T::TXDATG2: CH11_TXDAT Position */
#define BMC_TXDATG2_CH11_TXDAT_Msk (0x1ful << BMC_TXDATG2_CH11_TXDAT_Pos) /*!< BMC_T::TXDATG2: CH11_TXDAT Mask */
#define BMC_TXDATG3_CH12_TXDAT_Pos (0) /*!< BMC_T::TXDATG3: CH12_TXDAT Position */
#define BMC_TXDATG3_CH12_TXDAT_Msk (0x1ful << BMC_TXDATG3_CH12_TXDAT_Pos) /*!< BMC_T::TXDATG3: CH12_TXDAT Mask */
#define BMC_TXDATG3_CH13_TXDAT_Pos (8) /*!< BMC_T::TXDATG3: CH13_TXDAT Position */
#define BMC_TXDATG3_CH13_TXDAT_Msk (0x1ful << BMC_TXDATG3_CH13_TXDAT_Pos) /*!< BMC_T::TXDATG3: CH13_TXDAT Mask */
#define BMC_TXDATG3_CH14_TXDAT_Pos (16) /*!< BMC_T::TXDATG3: CH14_TXDAT Position */
#define BMC_TXDATG3_CH14_TXDAT_Msk (0x1ful << BMC_TXDATG3_CH14_TXDAT_Pos) /*!< BMC_T::TXDATG3: CH14_TXDAT Mask */
#define BMC_TXDATG3_CH15_TXDAT_Pos (24) /*!< BMC_T::TXDATG3: CH15_TXDAT Position */
#define BMC_TXDATG3_CH15_TXDAT_Msk (0x1ful << BMC_TXDATG3_CH15_TXDAT_Pos) /*!< BMC_T::TXDATG3: CH15_TXDAT Mask */
#define BMC_TXDATG4_CH16_TXDAT_Pos (0) /*!< BMC_T::TXDATG4: CH16_TXDAT Position */
#define BMC_TXDATG4_CH16_TXDAT_Msk (0x1ful << BMC_TXDATG4_CH16_TXDAT_Pos) /*!< BMC_T::TXDATG4: CH16_TXDAT Mask */
#define BMC_TXDATG4_CH17_TXDAT_Pos (8) /*!< BMC_T::TXDATG4: CH17_TXDAT Position */
#define BMC_TXDATG4_CH17_TXDAT_Msk (0x1ful << BMC_TXDATG4_CH17_TXDAT_Pos) /*!< BMC_T::TXDATG4: CH17_TXDAT Mask */
#define BMC_TXDATG4_CH18_TXDAT_Pos (16) /*!< BMC_T::TXDATG4: CH18_TXDAT Position */
#define BMC_TXDATG4_CH18_TXDAT_Msk (0x1ful << BMC_TXDATG4_CH18_TXDAT_Pos) /*!< BMC_T::TXDATG4: CH18_TXDAT Mask */
#define BMC_TXDATG4_CH19_TXDAT_Pos (24) /*!< BMC_T::TXDATG4: CH19_TXDAT Position */
#define BMC_TXDATG4_CH19_TXDAT_Msk (0x1ful << BMC_TXDATG4_CH19_TXDAT_Pos) /*!< BMC_T::TXDATG4: CH19_TXDAT Mask */
#define BMC_TXDATG5_CH20_TXDAT_Pos (0) /*!< BMC_T::TXDATG5: CH20_TXDAT Position */
#define BMC_TXDATG5_CH20_TXDAT_Msk (0x1ful << BMC_TXDATG5_CH20_TXDAT_Pos) /*!< BMC_T::TXDATG5: CH20_TXDAT Mask */
#define BMC_TXDATG5_CH21_TXDAT_Pos (8) /*!< BMC_T::TXDATG5: CH21_TXDAT Position */
#define BMC_TXDATG5_CH21_TXDAT_Msk (0x1ful << BMC_TXDATG5_CH21_TXDAT_Pos) /*!< BMC_T::TXDATG5: CH21_TXDAT Mask */
#define BMC_TXDATG5_CH22_TXDAT_Pos (16) /*!< BMC_T::TXDATG5: CH22_TXDAT Position */
#define BMC_TXDATG5_CH22_TXDAT_Msk (0x1ful << BMC_TXDATG5_CH22_TXDAT_Pos) /*!< BMC_T::TXDATG5: CH22_TXDAT Mask */
#define BMC_TXDATG5_CH23_TXDAT_Pos (24) /*!< BMC_T::TXDATG5: CH23_TXDAT Position */
#define BMC_TXDATG5_CH23_TXDAT_Msk (0x1ful << BMC_TXDATG5_CH23_TXDAT_Pos) /*!< BMC_T::TXDATG5: CH23_TXDAT Mask */
#define BMC_TXDATG6_CH24_TXDAT_Pos (0) /*!< BMC_T::TXDATG6: CH24_TXDAT Position */
#define BMC_TXDATG6_CH24_TXDAT_Msk (0x1ful << BMC_TXDATG6_CH24_TXDAT_Pos) /*!< BMC_T::TXDATG6: CH24_TXDAT Mask */
#define BMC_TXDATG6_CH25_TXDAT_Pos (8) /*!< BMC_T::TXDATG6: CH25_TXDAT Position */
#define BMC_TXDATG6_CH25_TXDAT_Msk (0x1ful << BMC_TXDATG6_CH25_TXDAT_Pos) /*!< BMC_T::TXDATG6: CH25_TXDAT Mask */
#define BMC_TXDATG6_CH26_TXDAT_Pos (16) /*!< BMC_T::TXDATG6: CH26_TXDAT Position */
#define BMC_TXDATG6_CH26_TXDAT_Msk (0x1ful << BMC_TXDATG6_CH26_TXDAT_Pos) /*!< BMC_T::TXDATG6: CH26_TXDAT Mask */
#define BMC_TXDATG6_CH27_TXDAT_Pos (24) /*!< BMC_T::TXDATG6: CH27_TXDAT Position */
#define BMC_TXDATG6_CH27_TXDAT_Msk (0x1ful << BMC_TXDATG6_CH27_TXDAT_Pos) /*!< BMC_T::TXDATG6: CH27_TXDAT Mask */
#define BMC_TXDATG7_CH28_TXDAT_Pos (0) /*!< BMC_T::TXDATG7: CH28_TXDAT Position */
#define BMC_TXDATG7_CH28_TXDAT_Msk (0x1ful << BMC_TXDATG7_CH28_TXDAT_Pos) /*!< BMC_T::TXDATG7: CH28_TXDAT Mask */
#define BMC_TXDATG7_CH29_TXDAT_Pos (8) /*!< BMC_T::TXDATG7: CH29_TXDAT Position */
#define BMC_TXDATG7_CH29_TXDAT_Msk (0x1ful << BMC_TXDATG7_CH29_TXDAT_Pos) /*!< BMC_T::TXDATG7: CH29_TXDAT Mask */
#define BMC_TXDATG7_CH30_TXDAT_Pos (16) /*!< BMC_T::TXDATG7: CH30_TXDAT Position */
#define BMC_TXDATG7_CH30_TXDAT_Msk (0x1ful << BMC_TXDATG7_CH30_TXDAT_Pos) /*!< BMC_T::TXDATG7: CH30_TXDAT Mask */
#define BMC_TXDATG7_CH31_TXDAT_Pos (24) /*!< BMC_T::TXDATG7: CH31_TXDAT Position */
#define BMC_TXDATG7_CH31_TXDAT_Msk (0x1ful << BMC_TXDATG7_CH31_TXDAT_Pos) /*!< BMC_T::TXDATG7: CH31_TXDAT Mask */
/**@}*/ /* BMC_CONST */
/**@}*/ /* end of BMC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __BMC_REG_H__ */

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/**************************************************************************//**
* @file ccap_reg.h
* @version V3.00
* @brief CCAP register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CCAP_REG_H__
#define __CCAP_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup CCAP Camera Capture Interface Controller (CCAP)
Memory Mapped Structure for CCAP Controller
@{ */
typedef struct
{
/**
* @var CCAP_T::CTL
* Offset: 0x00 Camera Capture Interface Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CCAPEN |Camera Capture Interface Enable Bit
* | | |0 = Camera Capture Interface Disabled.
* | | |1 = Camera Capture Interface Enabled.
* |[6] |PKTEN |Packet Output Enable Bit
* | | |0 = Packet output Disabled.
* | | |1 = Packet output Enabled.
* |[7] |MONO |Monochrome CMOS Sensor Select
* | | |0 = Color CMOS Sensor.
* | | |1 = Monochrome CMOS Sensor. The U/V components are ignored when the MONO is enabled.
* |[16] |SHUTTER |Camera Capture Interface Automatically Disable the Capture Interface After a Frame Had Been Captured
* | | |0 = Shutter Disabled.
* | | |1 = Shutter Enabled.
* |[17] |MY4_SWAP |Monochrome CMOS Sensor 4-bit Data Nibble Swap
* | | |0 = The 4-bit data input sequence: 1st Pixel is for 1st Nibble (1st pixel at MSB).
* | | |1 = The 4-bit data input sequence: 1st Pixel is for 2nd Nibble (1st pixel at LSB).
* |[18] |MY8_MY4 |Monochrome CMOS Sensor Data I/O Interface
* | | |0 = Monochrome CMOS sensor is by the 4-bit data I/O interface.
* | | |1 = Monochrome CMOS sensor is by the 8-bit data I/O interface.
* |[19] |Luma_Y_One|Color/Monochrome CMOS Sensor Luminance 8-bit Y to 1-bit Y Conversion
* | | |0 = Color/Monochrome CMOS sensor Luma-Y-One bit Disabled.
* | | |1 = Color/Monochrome CMOS sensor Luma-Y-One bit Enabled.
* | | |Note: Color CMOS sensor U/V components are ignored when the Luma_Y_One is enabled.
* |[20] |UPDATE |Update Register at New Frame
* | | |0 = Update register at new frame Disabled.
* | | |1 = Update register at new frame Enabled (Auto clear to 0 when register updated).
* |[24] |VPRST |Capture Interface Reset
* | | |0 = Capture interface reset Disabled.
* | | |1 = Capture interface reset Enabled.
* @var CCAP_T::PAR
* Offset: 0x04 Camera Capture Interface Parameter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |INFMT |Sensor Input Data Format
* | | |0 = YCbCr422.
* | | |1 = RGB565.
* |[1] |SENTYPE |Sensor Input Type
* | | |0 = CCIR601.
* | | |1 = CCIR656, VSync & Hsync embedded in the data signal.
* |[3:2] |INDATORD |Sensor Input Data Order
* | | |If INFMT (CCAP_PAR[0]) = 0 (YCbCr):
* | | |00 = Sensor input data (Byte 0 1 2 3) is Y0 U0 Y1 V0.
* | | |01 = Sensor input data (Byte 0 1 2 3) is Y0 V0 Y1 U0.
* | | |10 = Sensor input data (Byte 0 1 2 3) is U0 Y0 V0 Y1.
* | | |11 = Sensor input data (Byte 0 1 2 3) is V0 Y0 U0 Y1.
* | | |If INFMT (CCAP_PAR[0]) = 1 (RGB565):
* | | |00 = Sensor input data (Byte 0) is {R[4:0],G[5:3]}. Sensor input data (Byte 1) is {G[2:0], B[4:0]}.
* | | |01 = Sensor input data (Byte 0) is {B[4:0],G[5:3]}. Sensor input data (Byte 1) is {G[2:0], R[4:0]}.
* | | |10 = Sensor input data (Byte 0) is {G[2:0],B[4:0]}. Sensor input data (Byte 1) is {R[4:0], G[5:3]}.
* | | |11 = Sensor input data (Byte 0) is {G[2:0],R[4:0]}. Sensor input data (Byte 1) is {B[4:0], G[5:3]}.
* |[5:4] |OUTFMT |Image Data Format Output to System Memory
* | | |00 = YCbCr422.
* | | |01 = Only output Y. (Select this format when CCAP_CTL "Luma_Y_One" or "MONO" enabled).
* | | |10 = RGB555.
* | | |11 = RGB565.
* |[6] |RANGE |Scale Input YUV CCIR601 Color Range to Full Range
* | | |0 = Default.
* | | |1 = Scale to full range.
* |[8] |PCLKP |Sensor Pixel Clock Polarity
* | | |0 = Input video data and signals are latched by falling edge of Pixel Clock.
* | | |1 = Input video data and signals are latched by rising edge of Pixel Clock.
* |[9] |HSP |Sensor Hsync Polarity
* | | |0 = Sync Low.
* | | |1 = Sync High.
* |[10] |VSP |Sensor Vsync Polarity
* | | |0 = Sync Low.
* | | |1 = Sync High.
* |[18] |FBB |Field by Blank
* | | |Field by Blank (only in ccir-656 mode) means blanking pixel data(0x80108010) have to transfer to system memory or not.
* | | |0 = Field by blank Disabled. (blank pixel data will transfer to system memory).
* | | |1 = Field by blank Enabled. (only active data will transfer to system memory).
* @var CCAP_T::INT
* Offset: 0x08 Camera Capture Interface Interrupt Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VINTF |Video Frame End Interrupt
* | | |0 = Did not receive a frame completely.
* | | |1 = Received a frame completely.
* | | |Note: This bit is cleared by writing 1 to it.
* |[1] |MEINTF |Bus Master Transfer Error Interrupt
* | | |0 = Transfer Error did not occur.
* | | |1 = Transfer Error occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[3] |ADDRMINTF |Memory Address Match Interrupt
* | | |0 = Memory Address Match Interrupt did not occur.
* | | |1 = Memory Address Match Interrupt occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[16] |VIEN |Video Frame End Interrupt Enable Bit
* | | |0 = Video frame end interrupt Disabled.
* | | |1 = Video frame end interrupt Enabled.
* |[17] |MEIEN |Bus Master Transfer Error Interrupt Enable Bit
* | | |0 = Bus Master Transfer error interrupt Disabled.
* | | |1 = Bus Master Transfer error interrupt Enabled.
* |[19] |ADDRMIEN |Memory Address Match Interrupt Enable Bit
* | | |0 = Memory address match interrupt Disabled.
* | | |1 = Memory address match interrupt Enabled.
* @var CCAP_T::CWSP
* Offset: 0x20 Cropping Window Starting Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |CWSADDRH |Cropping Window Horizontal Starting Address
* | | |Specify the value of the cropping window horizontal start address.
* |[26:16] |CWSADDRV |Cropping Window Vertical Starting Address
* | | |Specify the value of the cropping window vertical start address.
* @var CCAP_T::CWS
* Offset: 0x24 Cropping Window Size Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |CWW |Cropping Window Width
* | | |Specify the size of the cropping window width.
* |[26:16] |CWH |Cropping Window Height
* | | |Specify the size of the cropping window height.
* @var CCAP_T::PKTSL
* Offset: 0x28 Packet Scaling Vertical/Horizontal Factor Register (LSB)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PKTSHML |Packet Scaling Horizontal Factor M
* | | |Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor.
* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor.
* | | |The output image width will be equal to the image width * N/M.
* | | |Note: The value of N must be equal to or less than M.
* |[15:8] |PKTSHNL |Packet Scaling Horizontal Factor N
* | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor.
* |[23:16] |PKTSVML |Packet Scaling Vertical Factor M
* | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor.
* | | |The output image width will be equal to the image height * N/M.
* | | |Note: The value of N must be equal to or less than M.
* |[31:24] |PKTSVNL |Packet Scaling Vertical Factor N
* | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor.
* @var CCAP_T::FRCTL
* Offset: 0x30 Scaling Frame Rate Factor Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |FRM |Scaling Frame Rate Factor M
* | | |Specify the denominator part (M) of the frame rate scaling factor.
* | | |The output image frame rate will be equal to input image frame rate * (N/M).
* | | |Note: The value of N must be equal to or less than M.
* |[13:8] |FRN |Scaling Frame Rate Factor N
* | | |Specify the numerator part (N) of the frame rate scaling factor.
* @var CCAP_T::STRIDE
* Offset: 0x34 Frame Output Pixel Stride Width Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |PKTSTRIDE |Packet Frame Output Pixel Stride Width
* | | |The output pixel stride size of packet pipe.
* | | |It is a 32-pixel aligned stride width for the Luma-Y-One bit format or a 4-pixel aligned stride with for the Luma-Y-Eight bit format when color or monochrome CMOS sensors used.
* | | |This means that every new captured line is by word alignment address when color or monochrome CMOS sensors used.
* @var CCAP_T::FIFOTH
* Offset: 0x3C FIFO Threshold Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[28:24] |PKTFTH |Packet FIFO Threshold
* | | |Specify the 5-bit value of the packet FIFO threshold.
* |[31] |OVF |FIFO Overflow Flag
* | | |Indicate the FIFO overflow flag.
* @var CCAP_T::CMPADDR
* Offset: 0x40 Compare Memory Base Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CMPADDR |Compare Memory Base Address
* | | |It is a word alignment address, that is, the address is aligned by ignoring the 2 LSB bits [1:0].
* @var CCAP_T::LUMA_Y1_THD
* Offset: 0x44 Luminance Y8 to Y1 Threshold Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :-----------: | :---- |
* |[7:0] |LUMA_Y1_THRESH |Luminance Y8 to Y1 Threshold Value
* | | |Specify the 8-bit threshold value for the luminance Y bit-8 to the luminance Y 1-bit conversion.
* @var CCAP_T::PKTSM
* Offset: 0x48 Packet Scaling Vertical/Horizontal Factor Register (MSB)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PKTSHMH |Packet Scaling Horizontal Factor M
* | | |Specify the higher 8-bit of denominator part (M) of the horizontal scaling factor.
* | | |Please refer to the register CCAP_PKTSL for the detailed operation.
* |[15:8] |PKTSHNH |Packet Scaling Horizontal Factor N
* | | |Specify the higher 8-bit of numerator part (N) of the horizontal scaling factor.
* | | |Please refer to the register CCAP_PKTSL for the detailed operation.
* |[23:16] |PKTSVMH |Packet Scaling Vertical Factor M
* | | |Specify the higher 8-bit of denominator part (M) of the vertical scaling factor.
* | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers.
* |[31:24] |PKTSVNH |Packet Scaling Vertical Factor N
* | | |Specify the higher 8-bit of numerator part (N) of the vertical scaling factor.
* | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers.
* @var CCAP_T::CURADDRP
* Offset: 0x50 Current Packet System Memory Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CURADDR |Current Packet Output Memory Address
* | | |Specify the 32-bit value of the current packet output memory address.
* @var CCAP_T::PKTBA0
* Offset: 0x60 System Memory Packet Base Address 0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |BASEADDR |System Memory Packet Base Address 0
* | | |It is a word alignment address, that is, the address is aligned by ignoring the 2 LSB bits [1:0].
*/
__IO uint32_t CTL; /*!< [0x0000] Camera Capture Interface Control Register */
__IO uint32_t PAR; /*!< [0x0004] Camera Capture Interface Parameter Register */
__IO uint32_t INT; /*!< [0x0008] Camera Capture Interface Interrupt Register */
__I uint32_t RESERVE0[5];
__IO uint32_t CWSP; /*!< [0x0020] Cropping Window Starting Address Register */
__IO uint32_t CWS; /*!< [0x0024] Cropping Window Size Register */
__IO uint32_t PKTSL; /*!< [0x0028] Packet Scaling Vertical/Horizontal Factor Register (LSB) */
__IO uint32_t PLNSL; /*!< [0x002C] Planar Scaling Vertical/Horizontal Factor Register (LSB) */
__IO uint32_t FRCTL; /*!< [0x0030] Scaling Frame Rate Factor Register */
__IO uint32_t STRIDE; /*!< [0x0034] Frame Output Pixel Stride Width Register */
__I uint32_t RESERVE1[1];
__IO uint32_t FIFOTH; /*!< [0x003C] FIFO Threshold Register */
__IO uint32_t CMPADDR; /*!< [0x0040] Compare Memory Base Address Register */
__IO uint32_t LUMA_Y1_THD; /*!< [0x0044] Luminance Y8 to Y1 Threshold Value Register */
__IO uint32_t PKTSM; /*!< [0x0048] Packet Scaling Vertical/Horizontal Factor Register (MSB) */
__IO uint32_t PLNSM; /*!< [0x004C] Planar Scaling Vertical/Horizontal Factor Register (MSB) */
__I uint32_t CURADDRP; /*!< [0x0050] Current Packet System Memory Address Register */
__I uint32_t CURADDRY; /*!< [0x0054] Current Planar Y System Memory Address Register */
__I uint32_t CURADDRU; /*!< [0x0058] Current Planar U System Memory Address Register */
__I uint32_t CURADDRV; /*!< [0x005C] Current Planar V System Memory Address Register */
__IO uint32_t PKTBA0; /*!< [0x0060] System Memory Packet Base Address 0 Register */
__I uint32_t RESERVE4[7];
__IO uint32_t YBA; /*!< [0x0080] System Memory Planar Y Base Address Register */
__IO uint32_t UBA; /*!< [0x0084] System Memory Planar U Base Address Register */
__IO uint32_t VBA; /*!< [0x0088] System Memory Planar V Base Address Register */
} CCAP_T;
/**
@addtogroup CCAP_CONST CCAP Bit Field Definition
Constant Definitions for CCAP Controller
@{ */
#define CCAP_CTL_CCAPEN_Pos (0) /*!< CCAP_T::CTL: CCAPEN Position */
#define CCAP_CTL_CCAPEN_Msk (0x1ul << CCAP_CTL_CCAPEN_Pos) /*!< CCAP_T::CTL: CCAPEN Mask */
#define CCAP_CTL_PLNEN_Pos (5) /*!< CCAP_T::CTL: PLNEN Position */
#define CCAP_CTL_PLNEN_Msk (0x1ul << CCAP_CTL_PLNEN_Pos) /*!< CCAP_T::CTL: PLNEN Mask */
#define CCAP_CTL_PKTEN_Pos (6) /*!< CCAP_T::CTL: PKTEN Position */
#define CCAP_CTL_PKTEN_Msk (0x1ul << CCAP_CTL_PKTEN_Pos) /*!< CCAP_T::CTL: PKTEN Mask */
#define CCAP_CTL_MONO_Pos (7) /*!< CCAP_T::CTL: MONO Position */
#define CCAP_CTL_MONO_Msk (0x1ul << CCAP_CTL_MONO_Pos) /*!< CCAP_T::CTL: MONO Mask */
#define CCAP_CTL_SHUTTER_Pos (16) /*!< CCAP_T::CTL: SHUTTER Position */
#define CCAP_CTL_SHUTTER_Msk (0x1ul << CCAP_CTL_SHUTTER_Pos) /*!< CCAP_T::CTL: SHUTTER Mask */
#define CCAP_CTL_MY4_SWAP_Pos (17) /*!< CCAP_T::CTL: MY4_SWAP Position */
#define CCAP_CTL_MY4_SWAP_Msk (0x1ul << CCAP_CTL_MY4_SWAP_Pos) /*!< CCAP_T::CTL: MY4_SWAP Mask */
#define CCAP_CTL_MY8_MY4_Pos (18) /*!< CCAP_T::CTL: MY8_MY4 Position */
#define CCAP_CTL_MY8_MY4_Msk (0x1ul << CCAP_CTL_MY8_MY4_Pos) /*!< CCAP_T::CTL: MY8_MY4 Mask */
#define CCAP_CTL_Luma_Y_One_Pos (19) /*!< CCAP_T::CTL: Luma_Y_One Position */
#define CCAP_CTL_Luma_Y_One_Msk (0x1ul << CCAP_CTL_Luma_Y_One_Pos) /*!< CCAP_T::CTL: Luma_Y_One Mask */
#define CCAP_CTL_UPDATE_Pos (20) /*!< CCAP_T::CTL: UPDATE Position */
#define CCAP_CTL_UPDATE_Msk (0x1ul << CCAP_CTL_UPDATE_Pos) /*!< CCAP_T::CTL: UPDATE Mask */
#define CCAP_CTL_VPRST_Pos (24) /*!< CCAP_T::CTL: VPRST Position */
#define CCAP_CTL_VPRST_Msk (0x1ul << CCAP_CTL_VPRST_Pos) /*!< CCAP_T::CTL: VPRST Mask */
#define CCAP_PAR_INFMT_Pos (0) /*!< CCAP_T::PAR: INFMT Position */
#define CCAP_PAR_INFMT_Msk (0x1ul << CCAP_PAR_INFMT_Pos) /*!< CCAP_T::PAR: INFMT Mask */
#define CCAP_PAR_SENTYPE_Pos (1) /*!< CCAP_T::PAR: SENTYPE Position */
#define CCAP_PAR_SENTYPE_Msk (0x1ul << CCAP_PAR_SENTYPE_Pos) /*!< CCAP_T::PAR: SENTYPE Mask */
#define CCAP_PAR_INDATORD_Pos (2) /*!< CCAP_T::PAR: INDATORD Position */
#define CCAP_PAR_INDATORD_Msk (0x3ul << CCAP_PAR_INDATORD_Pos) /*!< CCAP_T::PAR: INDATORD Mask */
#define CCAP_PAR_PLNFMT_Pos (7) /*!< CCAP_T::PAR: OUTFMT Position */
#define CCAP_PAR_PLNFMT_Msk (0x1ul << CCAP_PAR_OUTFMT_Pos) /*!< CCAP_T::PAR: OUTFMT Mask */
#define CCAP_PAR_OUTFMT_Pos (4) /*!< CCAP_T::PAR: OUTFMT Position */
#define CCAP_PAR_OUTFMT_Msk (0x3ul << CCAP_PAR_OUTFMT_Pos) /*!< CCAP_T::PAR: OUTFMT Mask */
#define CCAP_PAR_RANGE_Pos (6) /*!< CCAP_T::PAR: RANGE Position */
#define CCAP_PAR_RANGE_Msk (0x1ul << CCAP_PAR_RANGE_Pos) /*!< CCAP_T::PAR: RANGE Mask */
#define CCAP_PAR_PCLKP_Pos (8) /*!< CCAP_T::PAR: PCLKP Position */
#define CCAP_PAR_PCLKP_Msk (0x1ul << CCAP_PAR_PCLKP_Pos) /*!< CCAP_T::PAR: PCLKP Mask */
#define CCAP_PAR_HSP_Pos (9) /*!< CCAP_T::PAR: HSP Position */
#define CCAP_PAR_HSP_Msk (0x1ul << CCAP_PAR_HSP_Pos) /*!< CCAP_T::PAR: HSP Mask */
#define CCAP_PAR_VSP_Pos (10) /*!< CCAP_T::PAR: VSP Position */
#define CCAP_PAR_VSP_Msk (0x1ul << CCAP_PAR_VSP_Pos) /*!< CCAP_T::PAR: VSP Mask */
#define CCAP_PAR_FBB_Pos (18) /*!< CCAP_T::PAR: FBB Position */
#define CCAP_PAR_FBB_Msk (0x1ul << CCAP_PAR_FBB_Pos) /*!< CCAP_T::PAR: FBB Mask */
#define CCAP_INT_VINTF_Pos (0) /*!< CCAP_T::INT: VINTF Position */
#define CCAP_INT_VINTF_Msk (0x1ul << CCAP_INT_VINTF_Pos) /*!< CCAP_T::INT: VINTF Mask */
#define CCAP_INT_MEINTF_Pos (1) /*!< CCAP_T::INT: MEINTF Position */
#define CCAP_INT_MEINTF_Msk (0x1ul << CCAP_INT_MEINTF_Pos) /*!< CCAP_T::INT: MEINTF Mask */
#define CCAP_INT_ADDRMINTF_Pos (3) /*!< CCAP_T::INT: ADDRMINTF Position */
#define CCAP_INT_ADDRMINTF_Msk (0x1ul << CCAP_INT_ADDRMINTF_Pos) /*!< CCAP_T::INT: ADDRMINTF Mask */
#define CCAP_INT_VIEN_Pos (16) /*!< CCAP_T::INT: VIEN Position */
#define CCAP_INT_VIEN_Msk (0x1ul << CCAP_INT_VIEN_Pos) /*!< CCAP_T::INT: VIEN Mask */
#define CCAP_INT_MEIEN_Pos (17) /*!< CCAP_T::INT: MEIEN Position */
#define CCAP_INT_MEIEN_Msk (0x1ul << CCAP_INT_MEIEN_Pos) /*!< CCAP_T::INT: MEIEN Mask */
#define CCAP_INT_ADDRMIEN_Pos (19) /*!< CCAP_T::INT: ADDRMIEN Position */
#define CCAP_INT_ADDRMIEN_Msk (0x1ul << CCAP_INT_ADDRMIEN_Pos) /*!< CCAP_T::INT: ADDRMIEN Mask */
#define CCAP_CWSP_CWSADDRH_Pos (0) /*!< CCAP_T::CWSP: CWSADDRH Position */
#define CCAP_CWSP_CWSADDRH_Msk (0xffful << CCAP_CWSP_CWSADDRH_Pos) /*!< CCAP_T::CWSP: CWSADDRH Mask */
#define CCAP_CWSP_CWSADDRV_Pos (16) /*!< CCAP_T::CWSP: CWSADDRV Position */
#define CCAP_CWSP_CWSADDRV_Msk (0x7fful << CCAP_CWSP_CWSADDRV_Pos) /*!< CCAP_T::CWSP: CWSADDRV Mask */
#define CCAP_CWS_CWW_Pos (0) /*!< CCAP_T::CWS: CWW Position */
#define CCAP_CWS_CWW_Msk (0xffful << CCAP_CWS_CWW_Pos) /*!< CCAP_T::CWS: CWW Mask */
#define CCAP_CWS_CWH_Pos (16) /*!< CCAP_T::CWS: CIWH Position */
#define CCAP_CWS_CWH_Msk (0x7fful << CCAP_CWS_CWH_Pos) /*!< CCAP_T::CWS: CIWH Mask */
#define CCAP_PKTSL_PKTSHML_Pos (0) /*!< CCAP_T::PKTSL: PKTSHML Position */
#define CCAP_PKTSL_PKTSHML_Msk (0xfful << CCAP_PKTSL_PKTSHML_Pos) /*!< CCAP_T::PKTSL: PKTSHML Mask */
#define CCAP_PKTSL_PKTSHNL_Pos (8) /*!< CCAP_T::PKTSL: PKTSHNL Position */
#define CCAP_PKTSL_PKTSHNL_Msk (0xfful << CCAP_PKTSL_PKTSHNL_Pos) /*!< CCAP_T::PKTSL: PKTSHNL Mask */
#define CCAP_PKTSL_PKTSVML_Pos (16) /*!< CCAP_T::PKTSL: PKTSVML Position */
#define CCAP_PKTSL_PKTSVML_Msk (0xfful << CCAP_PKTSL_PKTSVML_Pos) /*!< CCAP_T::PKTSL: PKTSVML Mask */
#define CCAP_PKTSL_PKTSVNL_Pos (24) /*!< CCAP_T::PKTSL: PKTSVNL Position */
#define CCAP_PKTSL_PKTSVNL_Msk (0xfful << CCAP_PKTSL_PKTSVNL_Pos) /*!< CCAP_T::PKTSL: PKTSVNL Mask */
#define CCAP_PLNSL_PLNSHML_Pos (0) /*!< CCAP_T::PLNSL: PLNSHML Position */
#define CCAP_PLNSL_PLNSHML_Msk (0xfful << CCAP_PLNSL_PLNSHML_Pos) /*!< CCAP_T::PLNSL: PLNSHML Mask */
#define CCAP_PLNSL_PLNSHNL_Pos (8) /*!< CCAP_T::PLNSL: PLNSHNL Position */
#define CCAP_PLNSL_PLNSHNL_Msk (0xfful << CCAP_PLNSL_PLNSHNL_Pos) /*!< CCAP_T::PLNSL: PLNSHNL Mask */
#define CCAP_PLNSL_PLNSVML_Pos (16) /*!< CCAP_T::PLNSL: PLNSVML Position */
#define CCAP_PLNSL_PLNSVML_Msk (0xfful << CCAP_PLNSL_PLNSVML_Pos) /*!< CCAP_T::PLNSL: PLNSVML Mask */
#define CCAP_PLNSL_PLNSVNL_Pos (24) /*!< CCAP_T::PLNSL: PLNSVNL Position */
#define CCAP_PLNSL_PLNSVNL_Msk (0xfful << CCAP_PLNSL_PLNSVNL_Pos) /*!< CCAP_T::PLNSL: PLNSVNL Mask */
#define CCAP_FRCTL_FRM_Pos (0) /*!< CCAP_T::FRCTL: FRM Position */
#define CCAP_FRCTL_FRM_Msk (0x3ful << CCAP_FRCTL_FRM_Pos) /*!< CCAP_T::FRCTL: FRM Mask */
#define CCAP_FRCTL_FRN_Pos (8) /*!< CCAP_T::FRCTL: FRN Position */
#define CCAP_FRCTL_FRN_Msk (0x3ful << CCAP_FRCTL_FRN_Pos) /*!< CCAP_T::FRCTL: FRN Mask */
#define CCAP_STRIDE_PKTSTRIDE_Pos (0) /*!< CCAP_T::STRIDE: PKTSTRIDE Position */
#define CCAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PKTSTRIDE_Pos) /*!< CCAP_T::STRIDE: PKTSTRIDE Mask */
#define CCAP_STRIDE_PLNSTRIDE_Pos (16) /*!< CCAP_T::STRIDE: PLNSTRIDE Position */
#define CCAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PLNSTRIDE_Pos) /*!< CCAP_T::STRIDE: PLNSTRIDE Mask */
#define CCAP_FIFOTH_PKTFTH_Pos (24) /*!< CCAP_T::FIFOTH: PKTFTH Position */
#define CCAP_FIFOTH_PKTFTH_Msk (0x1ful << CCAP_FIFOTH_PKTFTH_Pos) /*!< CCAP_T::FIFOTH: PKTFTH Mask */
#define CCAP_FIFOTH_OVF_Pos (31) /*!< CCAP_T::FIFOTH: OVF Position */
#define CCAP_FIFOTH_OVF_Msk (0x1ul << CCAP_FIFOTH_OVF_Pos) /*!< CCAP_T::FIFOTH: OVF Mask */
#define CCAP_CMPADDR_CMPADDR_Pos (0) /*!< CCAP_T::CMPADDR: CMPADDR Position */
#define CCAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CCAP_CMPADDR_CMPADDR_Pos) /*!< CCAP_T::CMPADDR: CMPADDR Mask */
#define CCAP_PKTSM_PKTSHMH_Pos (0) /*!< CCAP_T::PKTSM: PKTSHMH Position */
#define CCAP_PKTSM_PKTSHMH_Msk (0xfful << CCAP_PKTSM_PKTSHMH_Pos) /*!< CCAP_T::PKTSM: PKTSHMH Mask */
#define CCAP_PKTSM_PKTSHNH_Pos (8) /*!< CCAP_T::PKTSM: PKTSHNH Position */
#define CCAP_PKTSM_PKTSHNH_Msk (0xfful << CCAP_PKTSM_PKTSHNH_Pos) /*!< CCAP_T::PKTSM: PKTSHNH Mask */
#define CCAP_PKTSM_PKTSVMH_Pos (16) /*!< CCAP_T::PKTSM: PKTSVMH Position */
#define CCAP_PKTSM_PKTSVMH_Msk (0xfful << CCAP_PKTSM_PKTSVMH_Pos) /*!< CCAP_T::PKTSM: PKTSVMH Mask */
#define CCAP_PKTSM_PKTSVNH_Pos (24) /*!< CCAP_T::PKTSM: PKTSVNH Position */
#define CCAP_PKTSM_PKTSVNH_Msk (0xfful << CCAP_PKTSM_PKTSVNH_Pos) /*!< CCAP_T::PKTSM: PKTSVNH Mask */
#define CCAP_PLNSM_PLNSHMH_Pos (0) /*!< CCAP_T::PLNSM: PLNSHMH Position */
#define CCAP_PLNSM_PLNSHMH_Msk (0xfful << CCAP_PLNSM_PLNSHMH_Pos) /*!< CCAP_T::PLNSM: PLNSHMH Mask */
#define CCAP_PLNSM_PLNSHNH_Pos (8) /*!< CCAP_T::PLNSM: PLNSHNH Position */
#define CCAP_PLNSM_PLNSHNH_Msk (0xfful << CCAP_PLNSM_PLNSHNH_Pos) /*!< CCAP_T::PLNSM: PLNSHNH Mask */
#define CCAP_PLNSM_PLNSVMH_Pos (16) /*!< CCAP_T::PLNSM: PLNSVMH Position */
#define CCAP_PLNSM_PLNSVMH_Msk (0xfful << CCAP_PLNSM_PLNSVMH_Pos) /*!< CCAP_T::PLNSM: PLNSVMH Mask */
#define CCAP_PLNSM_PLNSVNH_Pos (24) /*!< CCAP_T::PLNSM: PLNSVNH Position */
#define CCAP_PLNSM_PLNSVNH_Msk (0xfful << CCAP_PLNSM_PLNSVNH_Pos) /*!< CCAP_T::PLNSM: PLNSVNH Mask */
#define CCAP_CURADDRP_CURADDR_Pos (0) /*!< CCAP_T::CURADDRP: CURADDR Position */
#define CCAP_CURADDRP_CURADDR_Msk (0xfffffffful << CCAP_CURADDRP_CURADDR_Pos) /*!< CCAP_T::CURADDRP: CURADDR Mask */
#define CCAP_PKTBA0_BASEADDR_Pos (0) /*!< CCAP_T::PKTBA0: BASEADDR Position */
#define CCAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CCAP_PKTBA0_BASEADDR_Pos) /*!< CCAP_T::PKTBA0: BASEADDR Mask */
/**@}*/ /* CCAP_CONST */
/**@}*/ /* end of CCAP register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __CCAP_REG_H__ */

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/**************************************************************************//**
* @file crc_reg.h
* @version V3.00
* @brief CRC register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CRC_REG_H__
#define __CRC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Cyclic Redundancy Check Controller -------------------------*/
/**
@addtogroup CRC Cyclic Redundancy Check Controller(CRC)
Memory Mapped Structure for CRC Controller
@{
*/
typedef struct
{
/**
* @var CRC_T::CTL
* Offset: 0x00 CRC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CRCEN |CRC Channel Enable Bit
* | | |0 = No effect.
* | | |1 = CRC operation Enabled.
* |[1] |CHKSINIT |Checksum Initialization
* | | |0 = No effect.
* | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value.
* | | |Note: This bit will be cleared automatically and written only.
* |[24] |DATREV |Write Data Bit Order Reverse
* | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
* | | |0 = Bit order reversed for CRC write data in Disabled.
* | | |1 = Bit order reversed for CRC write data in Enabled (per byte).
* | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
* |[25] |CHKSREV |Checksum Bit Order Reverse
* | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
* | | |0 = Bit order reverse for CRC checksum Disabled.
* | | |1 = Bit order reverse for CRC checksum Enabled.
* | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
* |[26] |DATFMT |Write Data 1's Complement
* | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
* | | |0 = 1's complement for CRC writes data in Disabled.
* | | |1 = 1's complement for CRC writes data in Enabled.
* |[27] |CHKSFMT |Checksum 1's Complement
* | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
* | | |0 = 1's complement for CRC checksum Disabled.
* | | |0 = 1's complement for CRC checksum Enabled.
* |[29:28] |DATLEN |CPU Write Data Length
* | | |This field indicates the write data length.
* | | |00 = Data length is 8-bit mode.
* | | |01 = Data length is 16-bit mode.
* | | |1x = Data length is 32-bit mode.
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
* |[31:30] |CRCMODE |CRC Polynomial Mode
* | | |This field indicates the CRC operation polynomial mode.
* | | |10 = CRC-16 Polynomial mode.
* | | |01 = CRC-8 Polynomial mode.
* | | |10 = CRC-16 Polynomial mode.
* | | |11 = CRC-32 Polynomial mode.
* | | |Note: User must program the polynomial value in CRC_POLYNOMIAL register to specify the polynomial used for CRC calculation.
* @var CRC_T::DAT
* Offset: 0x04 CRC Write Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATA |CRC Write Data Bits
* | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
* @var CRC_T::SEED
* Offset: 0x08 CRC Seed Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |CRC Seed Value
* | | |This field indicates the CRC seed value.
* | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
* @var CRC_T::CHECKSUM
* Offset: 0x0C CRC Checksum Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CHECKSUM |CRC Checksum Results
* | | |This field indicates the CRC checksum result.
* | | |Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
* @var CRC_T::POLYNOMIAL
* Offset: 0x10 CRC Polynomial Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |POLYNOMIAL |CRC Polynomial Register
* | | |This field indicates the value of CRC polynomial.
*/
__IO uint32_t CTL; /*!< [0x0000] CRC Control Register */
__IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */
__IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */
__I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */
__IO uint32_t POLYNOMIAL; /*!< [0x0010] CRC Polynomial Register */
} CRC_T;
/**
@addtogroup CRC_CONST CRC Bit Field Definition
Constant Definitions for CRC Controller
@{
*/
#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */
#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */
#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
#define CRC_POLYNOMIAL_POLYNOMIAL_Pos (0) /*!< CRC_T::POLYNOMIAL: POLYNOMIAL Position */
#define CRC_POLYNOMIAL_POLYNOMIAL_Msk (0xfffffffful << CRC_POLYNOMIAL_POLYNOMIAL_Pos) /*!< CRC_T::POLYNOMIAL: POLYNOMIAL Mask */
/**@}*/ /* CRC_CONST */
/**@}*/ /* end of CRC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __CRC_REG_H__ */

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/**************************************************************************//**
* @file dac_reg.h
* @version V1.00
* @brief DAC register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __DAC_REG_H__
#define __DAC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup DAC Digital to Analog Converter(DAC)
Memory Mapped Structure for DAC Controller
@{ */
typedef struct
{
/**
* @var DAC_T::CTL
* Offset: 0x00 DAC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DACEN |DAC Enable Bit
* | | |0 = DAC is Disabled.
* | | |1 = DAC is Enabled.
* |[1] |DACIEN |DAC Interrupt Enable Bit
* | | |0 = Interrupt is Disabled.
* | | |1 = Interrupt is Enabled.
* |[2] |DMAEN |DMA Mode Enable Bit
* | | |0 = DMA mode Disabled.
* | | |1 = DMA mode Enabled.
* |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit
* | | |0 = DMA under-run interrupt Disabled.
* | | |1 = DMA under-run interrupt Enabled.
* |[4] |TRGEN |Trigger Mode Enable Bit
* | | |0 = DAC event trigger mode Disabled.
* | | |1 = DAC event trigger mode Enabled.
* |[7:5] |TRGSEL |Trigger Source Selection
* | | |000 = Software trigger.
* | | |001 = External pin DAC0_ST trigger.
* | | |010 = Timer 0 trigger.
* | | |011 = Timer 1 trigger.
* | | |100 = Timer 2 trigger.
* | | |101 = Timer 3 trigger.
* | | |110 = EPWM0 trigger.
* | | |111 = EPWM1 trigger.
* |[8] |BYPASS |Bypass Buffer Mode
* | | |0 = Output voltage buffer Enabled.
* | | |1 = Output voltage buffer Disabled.
* |[10] |LALIGN |DAC Data Left-aligned Enabled Control
* | | |0 = Right alignment.
* | | |1 = Left alignment.
* |[13:12] |ETRGSEL |External Pin Trigger Selection
* | | |00 = Low level trigger.
* | | |01 = High level trigger.
* | | |10 = Falling edge trigger.
* | | |11 = Rising edge trigger.
* |[15:14] |BWSEL |DAC Data Bit-width Selection
* | | |00 = data is 12 bits.
* | | |01 = data is 8 bits.
* | | |Others = reserved.
* |[16] |GRPEN |DAC Group Mode Enable Bit
* | | |0 = DAC0 and DAC1 are not grouped.
* | | |1 = DAC0 and DAC1 are grouped.
* @var DAC_T::SWTRG
* Offset: 0x04 DAC Software Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SWTRG |Software Trigger
* | | |0 = Software trigger Disabled.
* | | |1 = Software trigger Enabled.
* | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
* @var DAC_T::DAT
* Offset: 0x08 DAC Data Holding Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DACDAT |DAC 12-bit Holding Data
* | | |These bits are written by user software which specifies 12-bit conversion data for DAC output
* | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
* | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
* | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
* @var DAC_T::DATOUT
* Offset: 0x0C DAC Data Output Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |DATOUT |DAC 12-bit Output Data
* | | |These bits are current digital data for DAC output conversion.
* | | |It is loaded from DAC_DAT register and user cannot write it directly.
* @var DAC_T::STATUS
* Offset: 0x10 DAC Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FINISH |DAC Conversion Complete Finish Flag
* | | |0 = DAC is in conversion state.
* | | |1 = DAC conversion finish.
* | | |This bit set to 1 when conversion time counter counts to SETTLET
* | | |It is cleared to 0 when DAC starts a new conversion
* | | |User writes 1 to clear this bit to 0.
* |[1] |DMAUDR |DMA Under-run Interrupt Flag
* | | |0 = No DMA under-run error condition occurred.
* | | |1 = DMA under-run error condition occurred.
* | | |User writes 1 to clear this bit.
* |[8] |BUSY |DAC Busy Flag (Read Only)
* | | |0 = DAC is ready for next conversion.
* | | |1 = DAC is busy in conversion.
* | | |This is read only bit.
* @var DAC_T::TCTL
* Offset: 0x14 DAC Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |SETTLET |DAC Output Settling Time
* | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
* | | |For example, DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50.
* | | |SELTTLET = DAC controller clock speed x settling time.
* @var DAC_T::GRPDAT
* Offset: 0x30 DAC Group Mode Data Holding Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DAC0DAT |DAC0 12-bit Holding Data
* | | |These bits are written by user software which specifies 12-bit conversion data for DAC output
* | | |The unused bits (DAC_GRPDAT[3:0] in left-alignment mode and DAC_GRPDAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
* | | |12 bit left alignment: user has to load data into DAC_GRPDAT[15:4] bits.
* | | |12 bit right alignment: user has to load data into DAC_GRPDAT[11:0] bits.
* | | |Note: In group mode, user can write 12-bit conversion data for DAC0 in DAC_GRPDAT[15:0] or DAC0_DAT[15:0]
* | | |The advantage of writing 12-bit conversion data in DAC_GRPDAT[15:0] is that can share one PDMA transfer mechanism.
* | | |Note: Write 12-bit conversion data in DAC0_DAT[15:0] or DAC1_DAT[15:0] have individual PDMA transfer mechanism between two DACs
* |[31:16] |DAC1DAT |DAC1 12-bit Holding Data
* | | |In group mode, user can write these bits for DAC1 12-bit conversion data
* | | |The unused bits (DAC_GRPDAT[3:0] in left-alignment mode and DAC_GRPDAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
* | | |12 bit left alignment: user has to load data into DAC_GRPDAT[15:4] bits.
* | | |12 bit right alignment: user has to load data into DAC_GRPDAT[11:0] bits.
* | | |Note: In group mode, user can write 12-bit conversion data for DAC1 in DAC_GRPDAT[31:16] or DAC1_DAT[15:0]
* | | |The advantage of writing 12-bit conversion data in DAC_GRPDAT[31:16] is that can share one PDMA transfer mechanism.
* | | |Note: Write 12-bit conversion data in DAC0_DAT[15:0] or DAC1_DAT[15:0] have individual PDMA transfer mechanism between two DACs
*/
__IO uint32_t CTL; /*!< [0x0000] DAC Control Register */
__IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */
__IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */
__I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */
__IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */
__IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */
__I uint32_t RESERVE0[6];
__IO uint32_t GRPDAT; /*!< [0x0030] DAC Group Mode Data Holding Register */
} DAC_T;
/**
@addtogroup DAC_CONST DAC Bit Field Definition
Constant Definitions for DAC Controller
@{ */
#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */
#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */
#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */
#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */
#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */
#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */
#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */
#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */
#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */
#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */
#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */
#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */
#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */
#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */
#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */
#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */
#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */
#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */
#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */
#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */
#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */
#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */
#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */
#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */
#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */
#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */
#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */
#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */
#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */
#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */
#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */
#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */
#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */
#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */
#define DAC_GRPDAT_DAC0DAT_Pos (0) /*!< DAC_T::GRPDAT: DAC0DAT Position */
#define DAC_GRPDAT_DAC0DAT_Msk (0xfffful << DAC_GRPDAT_DAC0DAT_Pos) /*!< DAC_T::GRPDAT: DAC0DAT Mask */
#define DAC_GRPDAT_DAC1DAT_Pos (16) /*!< DAC_T::GRPDAT: DAC1DAT Position */
#define DAC_GRPDAT_DAC1DAT_Msk (0xfffful << DAC_GRPDAT_DAC1DAT_Pos) /*!< DAC_T::GRPDAT: DAC1DAT Mask */
/**@}*/ /* DAC_CONST */
/**@}*/ /* end of DAC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __DAC_REG_H__ */

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/**************************************************************************//**
* @file ebi_reg.h
* @version V3.00
* @brief EBI register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __EBI_REG_H__
#define __EBI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- External Bus Interface Controller -------------------------*/
/**
@addtogroup EBI External Bus Interface Controller(EBI)
Memory Mapped Structure for EBI Controller
@{
*/
typedef struct
{
/**
* @var EBI_T::CTL
* Offset: 0x00 External Bus Interface Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EN |EBI Enable Bit
* | | |This bit is the functional enable bit for EBI.
* | | |0 = EBI function Disabled.
* | | |1 = EBI function Enabled.
* |[1] |DW16 |EBI Data Width 16-bit Select
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
* | | |0 = EBI data width is 8-bit.
* | | |1 = EBI data width is 16-bit.
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
* | | |0 = Chip select pin (EBI_nCS) is active low.
* | | |1 = Chip select pin (EBI_nCS) is active high.
* |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
* | | |0 = Address/Data Bus Separating Mode Disabled.
* | | |1 = Address/Data Bus Separating Mode Enabled.
* |[4] |CACCESS |Continuous Data Access Mode
* | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
* | | |0 = Continuous data access mode Disabled.
* | | |1 = Continuous data access mode Enabled.
* |[10:8] |MCLKDIV |External Output Clock Divider
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
* | | |000 = HCLK/1.
* | | |001 = HCLK/2.
* | | |010 = HCLK/4.
* | | |011 = HCLK/8.
* | | |100 = HCLK/16.
* | | |101 = HCLK/32.
* | | |110 = HCLK/64.
* | | |111 = HCLK/128.
* |[18:16] |TALE |Extend Time of ALE
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
* | | |tALE = (TALE+1)*EBI_MCLK.
* | | |Note: This field only available in EBI_CTL0 register
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
* | | |0 = EBI write buffer Disabled.
* | | |1 = EBI write buffer Enabled.
* | | |Note: This bit only available in EBI_CTL0 register
* @var EBI_T::TCTL
* Offset: 0x04 External Bus Interface Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:3] |TACC |EBI Data Access Time
* | | |TACC define data access time (tACC).
* | | |tACC = (TACC+1) * EBI_MCLK.
* |[10:8] |TAHD |EBI Data Access Hold Time
* | | |TAHD define data access hold time (tAHD).
* | | |tAHD = (TAHD+1) * EBI_MCLK.
* |[15:12] |W2X |Idle Cycle After Write
* | | |This field defines the number of W2X idle cycle.
* | | |W2X idle cycle = (W2X * EBI_MCLK).
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
* | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
* | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
* | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
* | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
* |[27:24] |R2R |Idle Cycle Between Read-to-read
* | | |This field defines the number of R2R idle cycle.
* | | |R2R idle cycle = (R2R * EBI_MCLK).
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
*/
__IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
__IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
__I uint32_t RESERVE0[2];
__IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
__IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
__I uint32_t RESERVE1[2];
__IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */
__IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */
} EBI_T;
/**
@addtogroup EBI_CONST EBI Bit Field Definition
Constant Definitions for EBI Controller
@{
*/
#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */
#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */
#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */
#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */
#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */
#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */
#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */
#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */
#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */
#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */
#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */
#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */
#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */
#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */
#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */
#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */
#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */
#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */
#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */
#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */
#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */
#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */
#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */
#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */
#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */
#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */
#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */
#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */
/**@}*/ /* EBI_CONST */
/**@}*/ /* end of EBI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __EBI_REG_H__ */

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/**************************************************************************//**
* @file ecap_reg.h
* @version V1.00
* @brief ECAP register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ECAP_REG_H__
#define __ECAP_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup ECAP Enhanced Input Capture Timer(ECAP)
Memory Mapped Structure for ECAP Controller
@{ */
typedef struct
{
/**
* @var ECAP_T::CNT
* Offset: 0x00 Input Capture Counter (24-bit up counter)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNT |Input Capture Timer/Counter
* | | |The input Capture Timer/Counter is a 24-bit up-counting counter
* | | |The clock source for the counter is from the clock divider
* @var ECAP_T::HLD0
* Offset: 0x04 Input Capture Hold Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::HLD1
* Offset: 0x08 Input Capture Hold Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::HLD2
* Offset: 0x0C Input Capture Hold Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::CNTCMP
* Offset: 0x10 Input Capture Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNTCMP |Input Capture Counter Compare Register
* | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT).
* | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT.
* @var ECAP_T::CTL0
* Offset: 0x14 Input Capture Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
* | | |To determine the sampling frequency of the Noise Filter clock
* | | |000 = CAP_CLK.
* | | |001 = CAP_CLK/2.
* | | |010 = CAP_CLK/4.
* | | |011 = CAP_CLK/16.
* | | |100 = CAP_CLK/32.
* | | |101 = CAP_CLK/64.
* |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control
* | | |0 = Noise filter of Input Capture Enabled.
* | | |1 = Noise filter of Input Capture Disabled (Bypass).
* |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control
* | | |0 = IC0 input to Input Capture Unit Disabled.
* | | |1 = IC0 input to Input Capture Unit Enabled.
* |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control
* | | |0 = IC1 input to Input Capture Unit Disabled.
* | | |1 = IC1 input to Input Capture Unit Enabled.
* |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control
* | | |0 = IC2 input to Input Capture Unit Disabled.
* | | |1 = IC2 input to Input Capture Unit Enabled.
* |[9:8] |CAPSEL0 |CAP0 Input Source Selection
* | | |00 = CAP0 input is from port pin ICAP0.
* | | |01 = Reserved.
* | | |10 = CAP0 input is from signal CHA of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[11:10] |CAPSEL1 |CAP1 Input Source Selection
* | | |00 = CAP1 input is from port pin ICAP1.
* | | |01 = Reserved.
* | | |10 = CAP1 input is from signal CHB of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[13:12] |CAPSEL2 |CAP2 Input Source Selection
* | | |00 = CAP2 input is from port pin ICAP2.
* | | |01 = Reserved.
* | | |10 = CAP2 input is from signal CHX of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control
* | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled.
* |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control
* | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled.
* |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control
* | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled.
* |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control
* | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled.
* |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control
* | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled.
* |[24] |CNTEN |Input Capture Counter Start Counting Control
* | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the .
* | | |0 = ECAP_CNT stop counting.
* | | |1 = ECAP_CNT starts up-counting.
* |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control
* | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs.
* | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled.
* |[28] |CMPEN |Compare Function Enable Control
* | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
* | | |0 = The compare function Disabled.
* | | |1 = The compare function Enabled.
* |[29] |CAPEN |Input Capture Timer/Counter Enable Control
* | | |0 = Input Capture function Disabled.
* | | |1 = Input Capture function Enabled.
* @var ECAP_T::CTL1
* Offset: 0x18 Input Capture Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection
* | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection
* | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection
* | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit
* | | |0 = The reload triggered by Event CAPTE0 Disabled.
* | | |1 = The reload triggered by Event CAPTE0 Enabled.
* |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit
* | | |0 = The reload triggered by Event CAPTE1 Disabled.
* | | |1 = The reload triggered by Event CAPTE1 Enabled.
* |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit
* | | |0 = The reload triggered by Event CAPTE2 Disabled.
* | | |1 = The reload triggered by Event CAPTE2 Enabled.
* |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit
* | | |0 = The reload triggered by CAPOV Disabled.
* | | |1 = The reload triggered by CAPOV Enabled.
* |[14:12] |CLKSEL |Capture Timer Clock Divide Selection
* | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].
* | | |000 = CAP_CLK/1.
* | | |001 = CAP_CLK/4.
* | | |010 = CAP_CLK/16.
* | | |011 = CAP_CLK/32.
* | | |100 = CAP_CLK/64.
* | | |101 = CAP_CLK/96.
* | | |110 = CAP_CLK/112.
* | | |111 = CAP_CLK/128.
* |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection
* | | |Select the capture timer/counter clock source.
* | | |00 = CAP_CLK (default).
* | | |01 = CAP0.
* | | |10 = CAP1.
* | | |11 = CAP2.
* |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control
* | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled.
* |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control
* | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled.
* |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control
* | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled.
* @var ECAP_T::STATUS
* Offset: 0x1C Input Capture Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag
* | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high.
* | | |0 = No valid edge change has been detected at CAP0 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP0 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag
* | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high.
* | | |0 = No valid edge change has been detected at CAP1 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP1 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag
* | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high.
* | | |0 = No valid edge change has been detected at CAP2 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP2 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[4] |CAPCMPF |Input Capture Compare-match Flag
* | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.
* | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear.
* | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[5] |CAPOVF |Input Capture Counter Overflow Flag
* | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
* | | |0 = No overflow event has occurred since last clear.
* | | |1 = Overflow event(s) has/have occurred since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only)
* | | |Reflecting the value of input channel 0, CAP0
* | | |(The bit is read only and write is ignored)
* |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only)
* | | |Reflecting the value of input channel 1, CAP1
* | | |(The bit is read only and write is ignored)
* |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only)
* | | |Reflecting the value of input channel 2, CAP2.
* | | |(The bit is read only and write is ignored)
*/
__IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */
__IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */
__IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */
__IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */
__IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */
__IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */
__IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */
__IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */
} ECAP_T;
/**
@addtogroup ECAP_CONST ECAP Bit Field Definition
Constant Definitions for ECAP Controller
@{ */
#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */
#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */
#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */
#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */
#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */
#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */
#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */
#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */
#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */
#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */
#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */
#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */
#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */
#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */
#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */
#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */
#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */
#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */
#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */
#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */
#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */
#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */
#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */
#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */
#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */
#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */
#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */
#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */
#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */
#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */
#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */
#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */
#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */
#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */
#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */
#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */
#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */
#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */
#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */
#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */
#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */
#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */
#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */
#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */
#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */
#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */
#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */
#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */
#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */
#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */
#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */
#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */
#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */
#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */
#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */
#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */
#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */
#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */
#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */
#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */
#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */
#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */
#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */
#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */
#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */
#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */
#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */
#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */
#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */
#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */
#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */
#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */
#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */
#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */
#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */
#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */
#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */
#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */
#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */
#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */
#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */
#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */
#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */
#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */
/**@}*/ /* ECAP_CONST */
/**@}*/ /* end of ECAP register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __ECAP_REG_H__ */

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/**************************************************************************//**
* @file qei_reg.h
* @version V1.00
* @brief EQEI register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __EQEI_REG_H__
#define __EQEI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup EQEI Quadrature Encoder Interface(EQEI)
Memory Mapped Structure for EQEI Controller
@{ */
typedef struct
{
/**
* @var EQEI_T::CNT
* Offset: 0x00 EQEI Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |Quadrature Encoder Interface Counter
* | | |A 32-bit up/down counter
* | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (EQEI_STATUS[8]) is one or decreased by one if the bit DIRF(EQEI_STATUS[8]) is zero
* | | |This register performs an integrator which count value is proportional to the encoder position
* | | |The pulse counter may be initialized to a predetermined value by one of three events occurs:
* | | |1. Software is written if EQEIEN (EQEI_CTL[29]) = 0.
* | | |2. Compare-match event if EQEIEN(EQEI_CTL[29])=1 and EQEI is in compare-counting mode.
* | | |3. Index signal change if EQEIEN(EQEI_CTL[29])=1 and IDXRLDEN (EQEI_CTL[27])=1.
* @var EQEI_T::CNTHOLD
* Offset: 0x04 EQEI Counter Hold Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold
* | | |When bit HOLDCNT (EQEI_CTL[24]) goes from low to high, the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD (EQEI_CNTHOLD[31:0]) register.
* @var EQEI_T::CNTLATCH
* Offset: 0x08 EQEI Counter Index Latch Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch
* | | |When the IDXF (EQEI_STATUS[0]) bit is set, the CNT(EQEI_CNT[31:0]) is copied into CNTLATCH (EQEI_CNTLATCH[31:0]) register.
* @var EQEI_T::CNTCMP
* Offset: 0x0C EQEI Counter Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare
* | | |If the EQEI controller is in the compare-counting mode CMPEN (EQEI_CTL[28]) =1, when the value of CNT(EQEI_CNT[31:0]) matches CNTCMP(EQEI_CNTCMP[31:0]), CMPF will be set
* | | |This register is software writable.
* @var EQEI_T::CNTMAX
* Offset: 0x14 EQEI Pre-set Maximum Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count
* | | |This register value determined by user stores the maximum value which may be the number of the EQEI counter for the EQEI controller compare-counting mode
* @var EQEI_T::CTL
* Offset: 0x18 EQEI Controller Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
* | | |To determine the sampling frequency of the Noise Filter clock .
* | | |000 = EQEI_CLK.
* | | |001 = EQEI_CLK/2.
* | | |010 = EQEI_CLK/4.
* | | |011 = EQEI_CLK/16.
* | | |100 = EQEI_CLK/32.
* | | |101 = EQEI_CLK/64.
* |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit
* | | |0 = The noise filter of EQEI controller Enabled.
* | | |1 = The noise filter of EQEI controller Disabled.
* |[4] |CHAEN |QEA Input to EQEI Controller Enable Bit
* | | |0 = QEA input to EQEI Controller Disabled.
* | | |1 = QEA input to EQEI Controller Enabled.
* |[5] |CHBEN |QEB Input to EQEI Controller Enable Bit
* | | |0 = QEB input to EQEI Controller Disabled.
* | | |1 = QEB input to EQEI Controller Enabled.
* |[6] |IDXEN |IDX Input to EQEI Controller Enable Bit
* | | |0 = IDX input to EQEI Controller Disabled.
* | | |1 = IDX input to EQEI Controller Enabled.
* |[7] |IDXRSTEN |IDX Reset EQEI Position Counter Enable Bit
* | | |0 = Reset EQEI position counter in every time IDX signal.
* | | |1 = Reset EQEI position counter in first time IDX signal.
* | | |Note: IDXRLDEN(EQEI_CTL[27]) should be set 1.
* |[10:8] |MODE |QEI Counting Mode Selection
* | | |There are seven quadrature encoder pulse counter operation modes.
* | | |000 = X4 Free-counting Mode.
* | | |001 = X2 Free-counting Mode.
* | | |010 = X4 Compare-counting Mode.
* | | |011 = X2 Compare-counting Mode.
* | | |100 = Phase Counting Mode Type 1. (PCMT1).
* | | |101 = Phase Counting Mode Type 2. (PCMT2).
* | | |110 = Directional Counting Mode.
* | | |111 = Reserved.
* | | |Note: User needs to set DIRSRC(EQEI_CTL2[5:4]) when MODE(EQEI_CTL[10:8]) selects to directional counting mode.
* |[12] |CHAINV |Inverse QEA Input Polarity
* | | |0 = Not inverse QEA input polarity.
* | | |1 = QEA input polarity is inversed to EQEI controller.
* |[13] |CHBINV |Inverse QEB Input Polarity
* | | |0 = Not inverse QEB input polarity.
* | | |1 = QEB input polarity is inversed to EQEI controller.
* |[14] |IDXINV |Inverse IDX Input Polarity
* | | |0 = Not inverse IDX input polarity.
* | | |1 = IDX input polarity is inversed to EQEI controller.
* |[15] |IDXRSTEV |IDX Signal Resets Enable Bit in First IDX Reset Event (Write Only)
* | | |0 = The next IDX level high signal reset function is disabled.
* | | |1 = The next IDX level high signal reset function is enabled.
* | | |Note: This bit only effective when IDXRSTEN (EQEI_CTL[7])=1 and IDXRLDEN (EQEI_CTL[27])=1.
* |[16] |OVUNIEN |OVUNF Trigger EQEI Interrupt Enable Bit
* | | |0 = OVUNF can trigger EQEI controller interrupt Disabled.
* | | |1 = OVUNF can trigger EQEI controller interrupt Enabled.
* |[17] |DIRIEN |DIRCHGF Trigger EQEI Interrupt Enable Bit
* | | |0 = DIRCHGF can trigger EQEI controller interrupt Disabled.
* | | |1 = DIRCHGF can trigger EQEI controller interrupt Enabled.
* |[18] |CMPIEN |CMPF Trigger EQEI Interrupt Enable Bit
* | | |0 = CMPF can trigger EQEI controller interrupt Disabled.
* | | |1 = CMPF can trigger EQEI controller interrupt Enabled.
* |[19] |IDXIEN |IDXF Trigger EQEI Interrupt Enable Bit
* | | |0 = The IDXF can trigger EQEI interrupt Disabled.
* | | |1 = The IDXF can trigger EQEI interrupt Enabled.
* |[20] |HOLDTMR0 |Hold EQEI_CNT by Timer 0
* | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1.
* |[21] |HOLDTMR1 |Hold EQEI_CNT by Timer 1
* | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1.
* |[22] |HOLDTMR2 |Hold EQEI_CNT by Timer 2
* | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1.
* |[23] |HOLDTMR3 |Hold EQEI_CNT by Timer 3
* | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1.
* |[24] |HOLDCNT |Hold EQEI_CNT Control
* | | |When this bit is set from low to high, the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD(EQEI_CNTHOLD[31:0])
* | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).
* | | |0 = No operation.
* | | |1 = EQEI_CNT content is captured and stored in CNTHOLD(EQEI_CNTHOLD[31:0]).
* | | |Note: This bit is automatically cleared after EQEI_CNTHOLD holds EQEI_CNT value.
* |[25] |IDXLATEN |Index Latch EQEI_CNT Enable Bit
* | | |If this bit is set to high, the CNT(EQEI_CNT[31:0]) content will be latched into CNTLATCH (EQEI_CNTLATCH[31:0]) at every rising on signal CHX.
* | | |0 = The index signal latch EQEI counter function Disabled.
* | | |1 = The index signal latch EQEI counter function Enabled.
* |[27] |IDXRLDEN |Index Trigger EQEI_CNT Reload Enable Bit
* | | |When this bit is high and a rising edge comes on signal CHX, the CNT(EQEI_CNT[31:0]) will be reset to zero if the counter is in up-counting type (DIRF(EQEI_STATUS[8]) = 1); while the CNT(EQEI_CNT[31:0]) will be reloaded with CNTMAX (EQEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF(EQEI_STATUS[8]) = 0).
* | | |0 = Reload function Disabled.
* | | |1 = EQEI_CNT re-initialized by Index signal Enabled.
* |[28] |CMPEN |The Compare Function Enable Bit
* | | |The compare function in EQEI controller is to compare the dynamic counting EQEI_CNT with the compare register CNTCMP( EQEI_CNTCMP[31:0]), if CNT(EQEI_CNT[31:0]) reaches CNTCMP( EQEI_CNTCMP[31:0]), the flag CMPF will be set.
* | | |0 = Compare function Disabled.
* | | |1 = Compare function Enabled.
* |[29] |EQEIEN |Enhanced Quadrature Encoder Interface Controller Enable Bit
* | | |0 = EQEI controller function Disabled.
* | | |1 = EQEI controller function Enabled.
* @var EQEI_T::CTL2
* Offset: 0x1C EQEI Controller Control Register2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SWAPEN |Swap Function Enable Bit
* | | |0 = EQEI swap function Disabled.
* | | |1 = EQEI swap function Enabled.
* |[2:1] |CRS |Clock Rate Setting without Quadrature Mode
* | | |00 = EQEI counter only counts the falling edge.
* | | |01 = EQEI counter only counts the rising edge.
* | | |10 = EQEI counter counts the rising and falling edge.
* | | |11 = reserved.
* |[5:4] |DIRSRC |Direction Signal Source Select
* | | |00 = Direction signal is determined from EQEI system calculation.
* | | |01 = reserved.
* | | |10 = Direction signal is tied 1 only for direction up count mode.
* | | |11 = Direction signal is tied 0 only for down count mode.
* |[8] |UTEN |Unit Timer Function Enable Bit
* | | |0 = EQEI unit timer function is disable.
* | | |1 = EQEI unit timer function is enable.
* |[9] |UTHOLDEN |Unit Timer Counter Hold Enable Bit
* | | |0 = No operation.
* | | |1 = EQEI_CNT content is captured and stored in CNTHOLD(EQEI_CNTHOLD[31:0]) when UTCNT matches UTCMP(EQEI_UTCMP[31:0]).
* |[10] |UTEVTRST |Enable Bit to Reset EQEI Position Counter by Unit Timer Event
* | | |0 = Disable to reset EQEI position counter feature when unit timer counter event occurs.
* | | |1 = Enable to reset EQEI position counter feature when unit timer counter event occurs.
* |[11] |IDXRSTUTS |IDX Resets Unit Timer Select Bit
* | | |0 = Unit timer will not be reset when IDX reset event happens.
* | | |1 = Resets unit timer or not will follow EQEI_CNT when IDX reset event happens.
* |[16] |PHEIEN |PHEF Trigger EQEI Interrupt Enable Bit
* | | |0 = PHEF can trigger EQEI controller interrupt Disabled.
* | | |1 = PHEF can trigger EQEI controller interrupt Enabled.
* |[17] |UTIEIEN |UTIEF Trigger EQEI Interrupt Enable Bit
* | | |0 = UTIEF can trigger EQEI controller interrupt Disabled.
* | | |1 = UTIEF can trigger EQEI controller interrupt Enabled.
* @var EQEI_T::UTCNT
* Offset: 0x20 EQEI Unit Timer Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |UTCNT |Unit Timer Counter
* | | |A 32-bit unit timer counter which may be reset to an initial value when any of the following events occur:
* | | |1. Software is written if UTEN (EQEI_CTL2[8]) = 0.
* | | |2. UT_EN (EQEI_CTL2[8]) =1, and the unit timer counter value matches UTCMP(EQEI_UTCMP[31:0]).
* | | |3. IDXRLDEN(EQEI_CTL[27]) =1 and IDXRSTUTS(EQEI_CTL2[11]=1, determine the unit timer to be reset or not will follow EQEI_CNT when IDX reset event happens.
* @var EQEI_T::UTCMP
* Offset: 0x24 EQEI Unit Timer Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |UTCMP |Unit Timer Counter Compare
* | | |If the EQEI unit timer is enable (EQEI_CTL2[8]) =1, and the unit timer counter value also matches UTCMP(EQEI_UTCMP[31:0]), then UTIEF (EQEI_STATUS[10]) will be set. This register is software writable.
* @var EQEI_T::STATUS
* Offset: 0x2C EQEI Controller Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IDXF |IDX Detected Flag
* | | |When the EQEI controller detects a rising edge on signal CHX it will set flag IDXF to high.
* | | |0 = No rising edge detected on signal CHX.
* | | |1 = A rising edge occurs on signal CHX.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[1] |CMPF |Compare-match Flag
* | | |If the EQEI compare function is enabled, the flag is set by hardware while EQEI counter up or down counts and reach to the CNTCMP(EQEI_CNTCMP[31:0]).
* | | |0 = EQEI counter does not match with CNTCMP(EQEI_CNTCMP[31:0]).
* | | |1 = EQEI counter counts to the same as CNTCMP(EQEI_CNTCMP[31:0]).
* | | |Note: This bit is only cleared by writing 1 to it.
* |[2] |OVUNF |QEI Counter Overflow or Underflow Flag
* | | |Flag is set by hardware while CNT(EQEI_CNT[31:0]) overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (EQEI_CNTMAX[31:0]) to zero in compare-counting mode
* | | |Similarly, the flag is set while EQEI counter underflows from zero to 0xFFFF_FFFF or CNTMAX (EQEI_CNTMAX[31:0]).
* | | |0 = No overflow or underflow occurs in EQEI counter.
* | | |1 = EQEI counter occurs counting overflow or underflow.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[3] |DIRCHGF |Direction Change Flag
* | | |Flag is set by hardware while EQEI counter counting direction is changed.
* | | |Software can clear this bit by writing 1 to it.
* | | |0 = No change in EQEI counter counting direction.
* | | |1 = EQEI counter counting direction is changed.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[8] |DIRF |QEI Counter Counting Direction Indication
* | | |0 = EQEI Counter is in down-counting.
* | | |1 = EQEI Counter is in up-counting.
* | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
* |[9] |FIDXEF |First IDX Signal Reset Event Flag (Read Only)
* | | |0 = The first IDX reset event has not happened yet.
* | | |1 = The first IDX reset event has happened.
* | | |Note: This bit only effective when IDXRSTEN (EQEI_CTL[7])=1 and IDXRLDEN (EQEI_CTL[27])=1.
* |[16] |PHEF EQEI |Phase Error Flag
* | | |0 = No Phase error occurs in EQEI CHA and CHB.
* | | |1 = Phase error occurs in EQEI CHA and CHB.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[17] |UTIEF |EQEI Unit Timer Event Flag
* | | |0 = No timer event occurs in EQEI unit timer counter.
* | | |1 = Unit timer event occurs in EQEI unit timer counter.
* | | |Note: This bit is only cleared by writing 1 to it.
*/
__IO uint32_t CNT; /*!< [0x0000] EQEI Counter Register */
__IO uint32_t CNTHOLD; /*!< [0x0004] EQEI Counter Hold Register */
__IO uint32_t CNTLATCH; /*!< [0x0008] EQEI Counter Index Latch Register */
__IO uint32_t CNTCMP; /*!< [0x000c] EQEI Counter Compare Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CNTMAX; /*!< [0x0014] EQEI Pre-set Maximum Count Register */
__IO uint32_t CTL; /*!< [0x0018] EQEI Controller Control Register */
__IO uint32_t CTL2; /*!< [0x001C] EQEI Controller Control Register2 */
__IO uint32_t UTCNT; /*!< [0x0020] EQEI Unit Timer Counter Register */
__IO uint32_t UTCMP; /*!< [0x0024] EQEI Unit Timer Compare Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t STATUS; /*!< [0x002c] EQEI Controller Status Register */
} EQEI_T;
/**
@addtogroup EQEI_CONST EQEI Bit Field Definition
Constant Definitions for EQEI Controller
@{ */
#define EQEI_CNT_CNT_Pos (0) /*!< EQEI_T::CNT: CNT Position */
#define EQEI_CNT_CNT_Msk (0xfffffffful << EQEI_CNT_CNT_Pos) /*!< EQEI_T::CNT: CNT Mask */
#define EQEI_CNTHOLD_CNTHOLD_Pos (0) /*!< EQEI_T::CNTHOLD: CNTHOLD Position */
#define EQEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << EQEI_CNTHOLD_CNTHOLD_Pos) /*!< EQEI_T::CNTHOLD: CNTHOLD Mask */
#define EQEI_CNTLATCH_CNTLATCH_Pos (0) /*!< EQEI_T::CNTLATCH: CNTLATCH Position */
#define EQEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << EQEI_CNTLATCH_CNTLATCH_Pos) /*!< EQEI_T::CNTLATCH: CNTLATCH Mask */
#define EQEI_CNTCMP_CNTCMP_Pos (0) /*!< EQEI_T::CNTCMP: CNTCMP Position */
#define EQEI_CNTCMP_CNTCMP_Msk (0xfffffffful << EQEI_CNTCMP_CNTCMP_Pos) /*!< EQEI_T::CNTCMP: CNTCMP Mask */
#define EQEI_CNTMAX_CNTMAX_Pos (0) /*!< EQEI_T::CNTMAX: CNTMAX Position */
#define EQEI_CNTMAX_CNTMAX_Msk (0xfffffffful << EQEI_CNTMAX_CNTMAX_Pos) /*!< EQEI_T::CNTMAX: CNTMAX Mask */
#define EQEI_CTL_NFCLKSEL_Pos (0) /*!< EQEI_T::CTL: NFCLKSEL Position */
#define EQEI_CTL_NFCLKSEL_Msk (0x7ul << EQEI_CTL_NFCLKSEL_Pos) /*!< EQEI_T::CTL: NFCLKSEL Mask */
#define EQEI_CTL_NFDIS_Pos (3) /*!< EQEI_T::CTL: NFDIS Position */
#define EQEI_CTL_NFDIS_Msk (0x1ul << EQEI_CTL_NFDIS_Pos) /*!< EQEI_T::CTL: NFDIS Mask */
#define EQEI_CTL_CHAEN_Pos (4) /*!< EQEI_T::CTL: CHAEN Position */
#define EQEI_CTL_CHAEN_Msk (0x1ul << EQEI_CTL_CHAEN_Pos) /*!< EQEI_T::CTL: CHAEN Mask */
#define EQEI_CTL_CHBEN_Pos (5) /*!< EQEI_T::CTL: CHBEN Position */
#define EQEI_CTL_CHBEN_Msk (0x1ul << EQEI_CTL_CHBEN_Pos) /*!< EQEI_T::CTL: CHBEN Mask */
#define EQEI_CTL_IDXEN_Pos (6) /*!< EQEI_T::CTL: IDXEN Position */
#define EQEI_CTL_IDXEN_Msk (0x1ul << EQEI_CTL_IDXEN_Pos) /*!< EQEI_T::CTL: IDXEN Mask */
#define EQEI_CTL_IDXRSTEN_Pos (7) /*!< EQEI_T::CTL: IDXRSTEN Position */
#define EQEI_CTL_IDXRSTEN_Msk (0x1ul << EQEI_CTL_IDXRSTEN_Pos) /*!< EQEI_T::CTL: IDXRSTEN Mask */
#define EQEI_CTL_MODE_Pos (8) /*!< EQEI_T::CTL: MODE Position */
#define EQEI_CTL_MODE_Msk (0x7ul << EQEI_CTL_MODE_Pos) /*!< EQEI_T::CTL: MODE Mask */
#define EQEI_CTL_CHAINV_Pos (12) /*!< EQEI_T::CTL: CHAINV Position */
#define EQEI_CTL_CHAINV_Msk (0x1ul << EQEI_CTL_CHAINV_Pos) /*!< EQEI_T::CTL: CHAINV Mask */
#define EQEI_CTL_CHBINV_Pos (13) /*!< EQEI_T::CTL: CHBINV Position */
#define EQEI_CTL_CHBINV_Msk (0x1ul << EQEI_CTL_CHBINV_Pos) /*!< EQEI_T::CTL: CHBINV Mask */
#define EQEI_CTL_IDXINV_Pos (14) /*!< EQEI_T::CTL: IDXINV Position */
#define EQEI_CTL_IDXINV_Msk (0x1ul << EQEI_CTL_IDXINV_Pos) /*!< EQEI_T::CTL: IDXINV Mask */
#define EQEI_CTL_IDXRSTEV_Pos (15) /*!< EQEI_T::CTL: IDXRSTEV Position */
#define EQEI_CTL_IDXRSTEV_Msk (0x1ul << EQEI_CTL_IDXRSTEV_Pos) /*!< EQEI_T::CTL: IDXRSTEV Mask */
#define EQEI_CTL_OVUNIEN_Pos (16) /*!< EQEI_T::CTL: OVUNIEN Position */
#define EQEI_CTL_OVUNIEN_Msk (0x1ul << EQEI_CTL_OVUNIEN_Pos) /*!< EQEI_T::CTL: OVUNIEN Mask */
#define EQEI_CTL_DIRIEN_Pos (17) /*!< EQEI_T::CTL: DIRIEN Position */
#define EQEI_CTL_DIRIEN_Msk (0x1ul << EQEI_CTL_DIRIEN_Pos) /*!< EQEI_T::CTL: DIRIEN Mask */
#define EQEI_CTL_CMPIEN_Pos (18) /*!< EQEI_T::CTL: CMPIEN Position */
#define EQEI_CTL_CMPIEN_Msk (0x1ul << EQEI_CTL_CMPIEN_Pos) /*!< EQEI_T::CTL: CMPIEN Mask */
#define EQEI_CTL_IDXIEN_Pos (19) /*!< EQEI_T::CTL: IDXIEN Position */
#define EQEI_CTL_IDXIEN_Msk (0x1ul << EQEI_CTL_IDXIEN_Pos) /*!< EQEI_T::CTL: IDXIEN Mask */
#define EQEI_CTL_HOLDTMR0_Pos (20) /*!< EQEI_T::CTL: HOLDTMR0 Position */
#define EQEI_CTL_HOLDTMR0_Msk (0x1ul << EQEI_CTL_HOLDTMR0_Pos) /*!< EQEI_T::CTL: HOLDTMR0 Mask */
#define EQEI_CTL_HOLDTMR1_Pos (21) /*!< EQEI_T::CTL: HOLDTMR1 Position */
#define EQEI_CTL_HOLDTMR1_Msk (0x1ul << EQEI_CTL_HOLDTMR1_Pos) /*!< EQEI_T::CTL: HOLDTMR1 Mask */
#define EQEI_CTL_HOLDTMR2_Pos (22) /*!< EQEI_T::CTL: HOLDTMR2 Position */
#define EQEI_CTL_HOLDTMR2_Msk (0x1ul << EQEI_CTL_HOLDTMR2_Pos) /*!< EQEI_T::CTL: HOLDTMR2 Mask */
#define EQEI_CTL_HOLDTMR3_Pos (23) /*!< EQEI_T::CTL: HOLDTMR3 Position */
#define EQEI_CTL_HOLDTMR3_Msk (0x1ul << EQEI_CTL_HOLDTMR3_Pos) /*!< EQEI_T::CTL: HOLDTMR3 Mask */
#define EQEI_CTL_HOLDCNT_Pos (24) /*!< EQEI_T::CTL: HOLDCNT Position */
#define EQEI_CTL_HOLDCNT_Msk (0x1ul << EQEI_CTL_HOLDCNT_Pos) /*!< EQEI_T::CTL: HOLDCNT Mask */
#define EQEI_CTL_IDXLATEN_Pos (25) /*!< EQEI_T::CTL: IDXLATEN Position */
#define EQEI_CTL_IDXLATEN_Msk (0x1ul << EQEI_CTL_IDXLATEN_Pos) /*!< EQEI_T::CTL: IDXLATEN Mask */
#define EQEI_CTL_IDXRLDEN_Pos (27) /*!< EQEI_T::CTL: IDXRLDEN Position */
#define EQEI_CTL_IDXRLDEN_Msk (0x1ul << EQEI_CTL_IDXRLDEN_Pos) /*!< EQEI_T::CTL: IDXRLDEN Mask */
#define EQEI_CTL_CMPEN_Pos (28) /*!< EQEI_T::CTL: CMPEN Position */
#define EQEI_CTL_CMPEN_Msk (0x1ul << EQEI_CTL_CMPEN_Pos) /*!< EQEI_T::CTL: CMPEN Mask */
#define EQEI_CTL_QEIEN_Pos (29) /*!< EQEI_T::CTL: EQEIEN Position */
#define EQEI_CTL_QEIEN_Msk (0x1ul << EQEI_CTL_QEIEN_Pos) /*!< EQEI_T::CTL: EQEIEN Mask */
#define EQEI_CTL2_SWAPEN_Pos (0) /*!< EQEI_T::CTL2: SWAPEN Position */
#define EQEI_CTL2_SWAPEN_Msk (0x1ul << EQEI_CTL2_SWAPEN_Pos) /*!< EQEI_T::CTL2: SWAPEN Mask */
#define EQEI_CTL2_CRS_Pos (1) /*!< EQEI_T::CTL2: CRS Position */
#define EQEI_CTL2_CRS_Msk (0x3ul << EQEI_CTL2_CRS_Pos) /*!< EQEI_T::CTL2: CRS Mask */
#define EQEI_CTL2_DIRSRC_Pos (4) /*!< EQEI_T::CTL2: DIRSRC Position */
#define EQEI_CTL2_DIRSRC_Msk (0x3ul << EQEI_CTL2_DIRSRC_Pos) /*!< EQEI_T::CTL2: DIRSRC Mask */
#define EQEI_CTL2_UTEN_Pos (8) /*!< EQEI_T::CTL2: UTEN Position */
#define EQEI_CTL2_UTEN_Msk (0x1ul << EQEI_CTL2_UTEN_Pos) /*!< EQEI_T::CTL2: UTEN Mask */
#define EQEI_CTL2_UTHOLDEN_Pos (9) /*!< EQEI_T::CTL2: UTHOLDEN Position */
#define EQEI_CTL2_UTHOLDEN_Msk (0x1ul << EQEI_CTL2_UTHOLDEN_Pos) /*!< EQEI_T::CTL2: UTHOLDEN Mask */
#define EQEI_CTL2_UTEVTRST_Pos (10) /*!< EQEI_T::CTL2: UTEVTRST Position */
#define EQEI_CTL2_UTEVTRST_Msk (0x1ul << EQEI_CTL2_UTEVTRST_Pos) /*!< EQEI_T::CTL2: UTEVTRST Mask */
#define EQEI_CTL2_IDXRSTUTS_Pos (11) /*!< EQEI_T::CTL2: IDXRSTUTS Position */
#define EQEI_CTL2_IDXRSTUTS_Msk (0x1ul << EQEI_CTL2_IDXRSTUTS_Pos) /*!< EQEI_T::CTL2: IDXRSTUTS Mask */
#define EQEI_CTL2_PHEIEN_Pos (16) /*!< EQEI_T::CTL2: PHEIEN Position */
#define EQEI_CTL2_PHEIEN_Msk (0x1ul << EQEI_CTL2_PHEIEN_Pos) /*!< EQEI_T::CTL2: PHEIEN Mask */
#define EQEI_CTL2_UTIEIEN_Pos (17) /*!< EQEI_T::CTL2: UTIEIEN Position */
#define EQEI_CTL2_UTIEIEN_Msk (0x1ul << EQEI_CTL2_UTIEIEN_Pos) /*!< EQEI_T::CTL2: UTIEIEN Mask */
#define EQEI_UTCNT_UTCNT_Pos (0) /*!< EQEI_T::UTCNT: UTCNT Position */
#define EQEI_UTCNT_UTCNT_Msk (0xfffffffful << EQEI_UTCNT_UTCNT_Pos) /*!< EQEI_T::UTCNT: UTCNT Mask */
#define EQEI_UTCMP_UTCMP_Pos (0) /*!< EQEI_T::UTCMP: UTCMP Position */
#define EQEI_UTCMP_UTCMP_Msk (0xfffffffful << EQEI_UTCMP_UTCMP_Pos) /*!< EQEI_T::UTCMP: UTCMP Mask */
#define EQEI_STATUS_IDXF_Pos (0) /*!< EQEI_T::STATUS: IDXF Position */
#define EQEI_STATUS_IDXF_Msk (0x1ul << EQEI_STATUS_IDXF_Pos) /*!< EQEI_T::STATUS: IDXF Mask */
#define EQEI_STATUS_CMPF_Pos (1) /*!< EQEI_T::STATUS: CMPF Position */
#define EQEI_STATUS_CMPF_Msk (0x1ul << EQEI_STATUS_CMPF_Pos) /*!< EQEI_T::STATUS: CMPF Mask */
#define EQEI_STATUS_OVUNF_Pos (2) /*!< EQEI_T::STATUS: OVUNF Position */
#define EQEI_STATUS_OVUNF_Msk (0x1ul << EQEI_STATUS_OVUNF_Pos) /*!< EQEI_T::STATUS: OVUNF Mask */
#define EQEI_STATUS_DIRCHGF_Pos (3) /*!< EQEI_T::STATUS: DIRCHGF Position */
#define EQEI_STATUS_DIRCHGF_Msk (0x1ul << EQEI_STATUS_DIRCHGF_Pos) /*!< EQEI_T::STATUS: DIRCHGF Mask */
#define EQEI_STATUS_DIRF_Pos (8) /*!< EQEI_T::STATUS: DIRF Position */
#define EQEI_STATUS_DIRF_Msk (0x1ul << EQEI_STATUS_DIRF_Pos) /*!< EQEI_T::STATUS: DIRF Mask */
#define EQEI_STATUS_FIDXEF_Pos (9) /*!< EQEI_T::STATUS: FIDXEF Position */
#define EQEI_STATUS_FIDXEF_Msk (0x1ul << EQEI_STATUS_FIDXEF_Pos) /*!< EQEI_T::STATUS: FIDXEF Mask */
#define EQEI_STATUS_PHEF_Pos (16) /*!< EQEI_T::STATUS: PHEF Position */
#define EQEI_STATUS_PHEF_Msk (0x1ul << EQEI_STATUS_PHEF_Pos) /*!< EQEI_T::STATUS: PHEF Mask */
#define EQEI_STATUS_UTIEF_Pos (17) /*!< EQEI_T::STATUS: UTIEF Position */
#define EQEI_STATUS_UTIEF_Msk (0x1ul << EQEI_STATUS_UTIEF_Pos) /*!< EQEI_T::STATUS: UTIEF Mask */
/**@}*/ /* EQEI_CONST */
/**@}*/ /* end of EQEI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __EQEI_REG_H__ */

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/**************************************************************************//**
* @file fmc_reg.h
* @version V1.00
* @brief FMC register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __FMC_REG_H__
#define __FMC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup FMC Flash Memory Controller(FMC)
Memory Mapped Structure for FMC Controller
@{ */
typedef struct
{
/**
* @var FMC_T::ISPCTL
* Offset: 0x00 ISP Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPEN |ISP Enable Bit (Write Protect)
* | | |ISP function enable bit. Set this bit to enable ISP function.
* | | |0 = ISP function Disabled.
* | | |1 = ISP function Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[1] |BS |Boot Select (Write Protect)
* | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively
* | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from
* | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
* | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
* | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[3] |APUEN |APROM Update Enable Bit (Write Protect)
* | | |0 = APROM cannot be updated when the chip runs in APROM.
* | | |1 = APROM can be updated when the chip runs in APROM.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)
* | | |0 = CONFIG cannot be updated.
* | | |1 = CONFIG can be updated.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)
* | | |LDROM update enable bit.
* | | |0 = LDROM cannot be updated.
* | | |1 = LDROM can be updated.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[6] |ISPFF |ISP Fail Flag (Write Protect)
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |This bit needs to be cleared by writing 1 to it.
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) SPROM is erased/programmed if SPUEN is set to 0
* | | |(5) SPROM is programmed at SPROM secured mode.
* | | |(6) Page Erase command at LOCK mode with ICE connection
* | | |(7) Erase or Program command at brown-out detected
* | | |(8) Destination address is illegal, such as over an available range.
* | | |(9) Invalid ISP commands
* | | |(10) Vector address is mapping to SPROM region
* | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1
* | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1
* | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1
* | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
* | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1
* | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A
* | | |(17) Read any content of boot loader with ICE connection
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[16] |BL |Boot Loader Booting (Write Protect)
* | | |This bit is initiated with the inversed value of MBS (CONFIG0[5])
* | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded
* | | |This bit is used to check chip boot from Boot Loader or not
* | | |User should keep original value of this bit when updating FMC_ISPCTL register.
* | | |0 = Booting from APROM or LDROM.
* | | |1 = Booting from Boot Loader.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::ISPADDR
* Offset: 0x04 ISP Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPADDR |ISP Address
* | | |The NuMicro M480 series is equipped with embedded flash
* | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation
* | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
* | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation.
* | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte)
* | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte).
* @var FMC_T::ISPDAT
* Offset: 0x08 ISP Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT |ISP Data
* | | |Write data to this register before ISP program operation.
* | | |Read data from this register after ISP read operation.
* | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff
* | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 4 Kbytes alignment
* | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result
* | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect
* @var FMC_T::ISPCMD
* Offset: 0x0C ISP Command Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |CMD |ISP Command
* | | |ISP command table is shown below:
* | | |0x00= FLASH Read.
* | | |0x04= Read Unique ID.
* | | |0x08= Read Flash All-One Result.
* | | |0x0B= Read Company ID.
* | | |0x0C= Read Device ID.
* | | |0x0D= Read Checksum.
* | | |0x21= FLASH 32-bit Program.
* | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP.
* | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1.
* | | |0x27= FLASH Multi-Word Program.
* | | |0x28= Run Flash All-One Verification.
* | | |0x2C= Bank Remap.
* | | |0x2D= Run Checksum Calculation.
* | | |0x2E= Vector Remap.
* | | |0x40= FLASH 64-bit Read.
* | | |0x61= FLASH 64-bit Program.
* | | |The other commands are invalid.
* @var FMC_T::ISPTRG
* Offset: 0x10 ISP Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPGO |ISP Start Trigger (Write Protect)
* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
* | | |0 = ISP operation is finished.
* | | |1 = ISP is progressed.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::DFBA
* Offset: 0x14 Data Flash Base Address
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DFBA |Data Flash Base Address
* | | |This register indicates Data Flash start address. It is a read only register.
* | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
* | | |This register is valid when DFEN (CONFIG0[0]) =0 .
* @var FMC_T::ISPSTS
* Offset: 0x40 ISP Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPBUSY |ISP Busy Flag (Read Only)
* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
* | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
* | | |0 = ISP operation is finished.
* | | |1 = ISP is progressed.
* |[2:1] |CBS |Boot Selection of CONFIG (Read Only)
* | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
* | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
* | | |00 = LDROM with IAP mode.
* | | |01 = LDROM without IAP mode.
* | | |10 = APROM with IAP mode.
* | | |11 = APROM without IAP mode.
* |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only)
* | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
* | | |0 = Booting from Boot Loader.
* | | |1 = Booting from LDROM/APROM.(.see CBS bit setting)
* |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only)
* | | |This bit is set if data is mismatched at ISP programming verification
* | | |This bit is clear by performing ISP flash erase or ISP read CID operation
* | | |0 = Flash Program is success.
* | | |1 = Flash Program is fail. Program data is different with data in the flash memory
* |[6] |ISPFF |ISP Fail Flag (Write Protect)
* | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) SPROM is erased/programmed if SPUEN is set to 0
* | | |(5) SPROM is programmed at SPROM secured mode.
* | | |(6) Page Erase command at LOCK mode with ICE connection
* | | |(7) Erase or Program command at brown-out detected
* | | |(8) Destination address is illegal, such as over an available range.
* | | |(9) Invalid ISP commands
* | | |(10) Vector address is mapping to SPROM region.
* | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1
* | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1
* | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1
* | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
* | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1.
* | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A
* | | |(17) Read any content of boot loader with ICE connection
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[7] |ALLONE |Flash All-one Verification Flag
* | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1
* | | |0 = All of flash bits are 1 after "Run Flash All-One Verification" complete.
* | | |1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete.
* |[23:9] |VECMAP |Vector Page Mapping Address (Read Only)
* | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9u2019h000} ~ {VECMAP[14:0], 9u2019h1FF}
* |[24] |INTFLAG |ISP Interrupt Flag
* | | |0 = ISP Not Finished.
* | | |1 = ISP done or ISPFF set.
* | | |Note: This function needs to be enabled by FMC_ISPCTRL[24].
* |[28] |ISPCERR |ISP Conflict Error
* | | |This bit shows when FMC is doing ISP operation. User cannot access FMC_ISP_ADDR,FMC_ISPDAT,FMC_ISPCMD,FMC_ISPTRG. It would cause ISPFF.
* |[30] |FBS |Flash Bank Selection
* | | |This bit indicate which bank is selected to boot.
* | | |0 = Booting from BANK0.
* | | |1 = Booting from BANK1.
* @var FMC_T::CYCCTL
* Offset: 0x4C Flash Access Cycle Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect)
* | | |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;.
* | | |The HCLK working frequency range range is<27MHz
* | | |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;.
* | | | The optimized HCLK working frequency range is 27~54 MHz
* | | |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;.
* | | |The optimized HCLK working frequency range is 54~81MHz
* | | |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;.
* | | | The optimized HCLK working frequency range is81~108MHz
* | | |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;.
* | | |The optimized HCLK working frequency range is 108~135MHz
* | | |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;.
* | | | The optimized HCLK working frequency range is 135~162MHz
* | | |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;.
* | | | The optimized HCLK working frequency range is 162~192MHz
* | | |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;.
* | | |The optimized HCLK working frequency range is >192MHz
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::MPDAT0
* Offset: 0x80 ISP Data0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT0 |ISP Data 0
* | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
* @var FMC_T::MPDAT1
* Offset: 0x84 ISP Data1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT1 |ISP Data 1
* | | |This register is the second 32-bit data for 64-bit/multi-word programming.
* @var FMC_T::MPDAT2
* Offset: 0x88 ISP Data2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT2 |ISP Data 2
* | | |This register is the third 32-bit data for multi-word programming.
* @var FMC_T::MPDAT3
* Offset: 0x8C ISP Data3 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT3 |ISP Data 3
* | | |This register is the fourth 32-bit data for multi-word programming.
* @var FMC_T::MPSTS
* Offset: 0xC0 ISP Multi-Program Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only)
* | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
* | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
* | | |0 = ISP Multi-Word program operation is finished.
* | | |1 = ISP Multi-Word program operation is progressed.
* |[1] |PPGO |ISP Multi-program Status (Read Only)
* | | |0 = ISP multi-word program operation is not active.
* | | |1 = ISP multi-word program operation is in progress.
* |[2] |ISPFF |ISP Fail Flag (Read Only)
* | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) SPROM is erased/programmed if SPUEN is set to 0
* | | |(5) SPROM is programmed at SPROM secured mode.
* | | |(6) Page Erase command at LOCK mode with ICE connection
* | | |(7) Erase or Program command at brown-out detected
* | | |(8) Destination address is illegal, such as over an available range.
* | | |(9) Invalid ISP commands
* | | |(10) Vector address is mapping to SPROM region.
* |[4] |D0 |ISP DATA 0 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
* | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
* |[5] |D1 |ISP DATA 1 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
* | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
* |[6] |D2 |ISP DATA 2 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
* | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
* |[7] |D3 |ISP DATA 3 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
* | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.
* | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
* @var FMC_T::MPADDR
* Offset: 0xC4 ISP Multi-Program Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |MPADDR |ISP Multi-word Program Address
* | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
* | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.
* @var FMC_T::XOMR0STS
* Offset: 0xD0 XOM Region 0 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SIZE |XOM Region 0 Size (Page-aligned)
* | | |SIZE is the page number of XOM Region 0.
* |[31:8] |BASE |XOM Region 0 Base Address (Page-aligned)
* | | |BASE is the base address of XOM Region 0.
* @var FMC_T::XOMR1STS
* Offset: 0xD4 XOM Region 1 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SIZE |XOM Region 1 Size (Page-aligned)
* | | |SIZE is the page number of XOM Region 1.
* |[31:8] |BASE |XOM Region 1 Base Address (Page-aligned)
* | | |BASE is the base address of XOM Region 1.
* @var FMC_T::XOMR2STS
* Offset: 0xD8 XOM Region 2 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SIZE |XOM Region 2 Size (Page-aligned)
* | | |SIZE is the page number of XOM Region 2.
* |[31:8] |BASE |XOM Region 2 Base Address (Page-aligned)
* | | |BASE is the base address of XOM Region 2.
* @var FMC_T::XOMR3STS
* Offset: 0xDC XOM Region 3 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SIZE |XOM Region 3 Size (Page-aligned)
* | | |SIZE is the page number of XOM Region 3.
* |[31:8] |BASE |XOM Region 3 Base Address (Page-aligned)
* | | |BASE is the base address of XOM Region 3.
* @var FMC_T::XOMSTS
* Offset: 0xE0 XOM Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |XOMR0ON |XOM Region 0 On
* | | |XOM Region 0 active status.
* | | |0 = No active.
* | | |1 = XOM region 0 is active.
* |[1] |XOMR1ON |XOM Region 1 On
* | | |XOM Region 1 active status.
* | | |0 = No active.
* | | |1 = XOM region 1 is active.
* |[2] |XOMR2ON |XOM Region 2 On
* | | |XOM Region 2 active status.
* | | |0 = No active.
* | | |1 = XOM region 2 is active.
* |[3] |XOMR3ON |XOM Region 3 On
* | | |XOM Region 3 active status.
* | | |0 = No active.
* | | |1 = XOM region 3 is active.
* |[4] |XOMPEF |XOM Page Erase Function Fail
* | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.
* | | |0 = Success.
* | | |1 = Fail.
* @var FMC_T::APPROT
* Offset: 0x110 APROM Protect Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |APPROENn |APROM Proect enable
* | n=0,1..| |This bit indicates which APROM region is protected.
* | ..31 | |0 = APROM region n is not protected.
* | | |1 = APROM region n is protected.
* | | |Note: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000)
*/
__IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */
__IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */
__IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */
__IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */
__IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */
__I uint32_t DFBA; /*!< [0x0014] Data Flash Base Address */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[10];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[12];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */
__IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */
__IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */
__IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[12];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */
__I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE4[2];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */
__I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */
__I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */
__I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */
__I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */
__I uint32_t RESERVE5[11];
__IO uint32_t APPROT; /*!< [0x0110] XOM Status Register */
} FMC_T;
/**
@addtogroup FMC_CONST FMC Bit Field Definition
Constant Definitions for FMC Controller
@{ */
#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
#define FMC_ISPCTL_SPUEN_Pos (2) /*!< FMC_T::ISPCTL: SPUEN Position */
#define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) /*!< FMC_T::ISPCTL: SPUEN Mask */
#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */
#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */
#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
#define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */
#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */
#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */
#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */
#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */
#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */
#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */
#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
#define FMC_ISPSTS_INTFLAG_Pos (24) /*!< FMC_T::ISPSTS: INTFLAG Position */
#define FMC_ISPSTS_INTFLAG_Msk (0x01ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Position */
#define FMC_ISPSTS_ISPCERR_Pos (28) /*!< FMC_T::ISPSTS: ISPCERR Position */
#define FMC_ISPSTS_ISPCERR_Msk (0x01ul << FMC_ISPSTS_ISPCERR_Pos) /*!< FMC_T::ISPSTS: ISPCERR Position */
#define FMC_ISPSTS_FBS_Pos (30) /*!< FMC_T::ISPSTS: FBS Position */
#define FMC_ISPSTS_FBS_Msk (0x1ul << FMC_ISPSTS_FBS_Pos) /*!< FMC_T::ISPSTS: FBS Msk */
#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */
#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */
#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
#define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */
#define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */
#define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */
#define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */
#define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */
#define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */
#define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */
#define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */
#define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */
#define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */
#define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */
#define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOM20STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */
#define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */
#define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */
#define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */
#define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */
#define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */
#define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */
#define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */
#define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */
#define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */
#define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */
#define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */
#define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */
#define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */
#define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */
#define FMC_APPROT_APPROEN0_Pos (0) /*!< FMC_T::APPROT: APPROEN0 Position */
#define FMC_APPROT_APPROEN0_Msk (0x1ul << FMC_APPROT_APPROEN0_Pos) /*!< FMC_T::APPROT: APPROEN0 Mask */
#define FMC_APPROT_APPROEN1_Pos (1) /*!< FMC_T::APPROT: APPROEN1 Position */
#define FMC_APPROT_APPROEN1_Msk (0x1ul << FMC_APPROT_APPROEN1_Pos) /*!< FMC_T::APPROT: APPROEN1 Mask */
#define FMC_APPROT_APPROEN2_Pos (2) /*!< FMC_T::APPROT: APPROEN2 Position */
#define FMC_APPROT_APPROEN2_Msk (0x1ul << FMC_APPROT_APPROEN2_Pos) /*!< FMC_T::APPROT: APPROEN2 Mask */
#define FMC_APPROT_APPROEN3_Pos (3) /*!< FMC_T::APPROT: APPROEN3 Position */
#define FMC_APPROT_APPROEN3_Msk (0x1ul << FMC_APPROT_APPROEN3_Pos) /*!< FMC_T::APPROT: APPROEN3 Mask */
#define FMC_APPROT_APPROEN4_Pos (4) /*!< FMC_T::APPROT: APPROEN4 Position */
#define FMC_APPROT_APPROEN4_Msk (0x1ul << FMC_APPROT_APPROEN4_Pos) /*!< FMC_T::APPROT: APPROEN4 Mask */
#define FMC_APPROT_APPROEN5_Pos (5) /*!< FMC_T::APPROT: APPROEN5 Position */
#define FMC_APPROT_APPROEN5_Msk (0x1ul << FMC_APPROT_APPROEN5_Pos) /*!< FMC_T::APPROT: APPROEN5 Mask */
#define FMC_APPROT_APPROEN6_Pos (6) /*!< FMC_T::APPROT: APPROEN6 Position */
#define FMC_APPROT_APPROEN6_Msk (0x1ul << FMC_APPROT_APPROEN6_Pos) /*!< FMC_T::APPROT: APPROEN6 Mask */
#define FMC_APPROT_APPROEN7_Pos (7) /*!< FMC_T::APPROT: APPROEN7 Position */
#define FMC_APPROT_APPROEN7_Msk (0x1ul << FMC_APPROT_APPROEN7_Pos) /*!< FMC_T::APPROT: APPROEN7 Mask */
#define FMC_APPROT_APPROEN8_Pos (8) /*!< FMC_T::APPROT: APPROEN8 Position */
#define FMC_APPROT_APPROEN8_Msk (0x1ul << FMC_APPROT_APPROEN8_Pos) /*!< FMC_T::APPROT: APPROEN8 Mask */
#define FMC_APPROT_APPROEN9_Pos (9) /*!< FMC_T::APPROT: APPROEN9 Position */
#define FMC_APPROT_APPROEN9_Msk (0x1ul << FMC_APPROT_APPROEN9_Pos) /*!< FMC_T::APPROT: APPROEN9 Mask */
#define FMC_APPROT_APPROEN10_Pos (10) /*!< FMC_T::APPROT: APPROEN10 Position */
#define FMC_APPROT_APPROEN10_Msk (0x1ul << FMC_APPROT_APPROEN10_Pos) /*!< FMC_T::APPROT: APPROEN10 Mask */
#define FMC_APPROT_APPROEN11_Pos (11) /*!< FMC_T::APPROT: APPROEN11 Position */
#define FMC_APPROT_APPROEN11_Msk (0x1ul << FMC_APPROT_APPROEN11_Pos) /*!< FMC_T::APPROT: APPROEN11 Mask */
#define FMC_APPROT_APPROEN12_Pos (12) /*!< FMC_T::APPROT: APPROEN12 Position */
#define FMC_APPROT_APPROEN12_Msk (0x1ul << FMC_APPROT_APPROEN12_Pos) /*!< FMC_T::APPROT: APPROEN12 Mask */
#define FMC_APPROT_APPROEN13_Pos (13) /*!< FMC_T::APPROT: APPROEN13 Position */
#define FMC_APPROT_APPROEN13_Msk (0x1ul << FMC_APPROT_APPROEN13_Pos) /*!< FMC_T::APPROT: APPROEN13 Mask */
#define FMC_APPROT_APPROEN14_Pos (14) /*!< FMC_T::APPROT: APPROEN14 Position */
#define FMC_APPROT_APPROEN14_Msk (0x1ul << FMC_APPROT_APPROEN14_Pos) /*!< FMC_T::APPROT: APPROEN14 Mask */
#define FMC_APPROT_APPROEN15_Pos (15) /*!< FMC_T::APPROT: APPROEN15 Position */
#define FMC_APPROT_APPROEN15_Msk (0x1ul << FMC_APPROT_APPROEN15_Pos) /*!< FMC_T::APPROT: APPROEN15 Mask */
#define FMC_APPROT_APPROEN16_Pos (16) /*!< FMC_T::APPROT: APPROEN16 Position */
#define FMC_APPROT_APPROEN16_Msk (0x1ul << FMC_APPROT_APPROEN16_Pos) /*!< FMC_T::APPROT: APPROEN16 Mask */
#define FMC_APPROT_APPROEN17_Pos (17) /*!< FMC_T::APPROT: APPROEN17 Position */
#define FMC_APPROT_APPROEN17_Msk (0x1ul << FMC_APPROT_APPROEN17_Pos) /*!< FMC_T::APPROT: APPROEN17 Mask */
#define FMC_APPROT_APPROEN18_Pos (18) /*!< FMC_T::APPROT: APPROEN18 Position */
#define FMC_APPROT_APPROEN18_Msk (0x1ul << FMC_APPROT_APPROEN18_Pos) /*!< FMC_T::APPROT: APPROEN18 Mask */
#define FMC_APPROT_APPROEN19_Pos (19) /*!< FMC_T::APPROT: APPROEN19 Position */
#define FMC_APPROT_APPROEN19_Msk (0x1ul << FMC_APPROT_APPROEN19_Pos) /*!< FMC_T::APPROT: APPROEN19 Mask */
#define FMC_APPROT_APPROEN20_Pos (20) /*!< FMC_T::APPROT: APPROEN20 Position */
#define FMC_APPROT_APPROEN20_Msk (0x1ul << FMC_APPROT_APPROEN20_Pos) /*!< FMC_T::APPROT: APPROEN20 Mask */
#define FMC_APPROT_APPROEN21_Pos (21) /*!< FMC_T::APPROT: APPROEN21 Position */
#define FMC_APPROT_APPROEN21_Msk (0x1ul << FMC_APPROT_APPROEN21_Pos) /*!< FMC_T::APPROT: APPROEN21 Mask */
#define FMC_APPROT_APPROEN22_Pos (22) /*!< FMC_T::APPROT: APPROEN22 Position */
#define FMC_APPROT_APPROEN22_Msk (0x1ul << FMC_APPROT_APPROEN22_Pos) /*!< FMC_T::APPROT: APPROEN22 Mask */
#define FMC_APPROT_APPROEN23_Pos (23) /*!< FMC_T::APPROT: APPROEN23 Position */
#define FMC_APPROT_APPROEN23_Msk (0x1ul << FMC_APPROT_APPROEN23_Pos) /*!< FMC_T::APPROT: APPROEN23 Mask */
#define FMC_APPROT_APPROEN24_Pos (24) /*!< FMC_T::APPROT: APPROEN24 Position */
#define FMC_APPROT_APPROEN24_Msk (0x1ul << FMC_APPROT_APPROEN24_Pos) /*!< FMC_T::APPROT: APPROEN24 Mask */
#define FMC_APPROT_APPROEN25_Pos (25) /*!< FMC_T::APPROT: APPROEN25 Position */
#define FMC_APPROT_APPROEN25_Msk (0x1ul << FMC_APPROT_APPROEN25_Pos) /*!< FMC_T::APPROT: APPROEN25 Mask */
#define FMC_APPROT_APPROEN26_Pos (26) /*!< FMC_T::APPROT: APPROEN26 Position */
#define FMC_APPROT_APPROEN26_Msk (0x1ul << FMC_APPROT_APPROEN26_Pos) /*!< FMC_T::APPROT: APPROEN26 Mask */
#define FMC_APPROT_APPROEN27_Pos (27) /*!< FMC_T::APPROT: APPROEN27 Position */
#define FMC_APPROT_APPROEN27_Msk (0x1ul << FMC_APPROT_APPROEN27_Pos) /*!< FMC_T::APPROT: APPROEN27 Mask */
#define FMC_APPROT_APPROEN28_Pos (28) /*!< FMC_T::APPROT: APPROEN28 Position */
#define FMC_APPROT_APPROEN28_Msk (0x1ul << FMC_APPROT_APPROEN28_Pos) /*!< FMC_T::APPROT: APPROEN28 Mask */
#define FMC_APPROT_APPROEN29_Pos (29) /*!< FMC_T::APPROT: APPROEN29 Position */
#define FMC_APPROT_APPROEN29_Msk (0x1ul << FMC_APPROT_APPROEN29_Pos) /*!< FMC_T::APPROT: APPROEN29 Mask */
#define FMC_APPROT_APPROEN30_Pos (30) /*!< FMC_T::APPROT: APPROEN30 Position */
#define FMC_APPROT_APPROEN30_Msk (0x1ul << FMC_APPROT_APPROEN30_Pos) /*!< FMC_T::APPROT: APPROEN30 Mask */
#define FMC_APPROT_APPROEN31_Pos (31) /*!< FMC_T::APPROT: APPROEN31 Position */
#define FMC_APPROT_APPROEN31_Msk (0x1ul << FMC_APPROT_APPROEN31_Pos) /*!< FMC_T::APPROT: APPROEN31 Mask */
/**@}*/ /* FMC_CONST */
/**@}*/ /* end of FMC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __FMC_REG_H__ */

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/**************************************************************************//**
* @file hbi_reg.h
* @version V1.00
* @brief HBI register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __HBI_REG_H__
#define __HBI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup Hyper Bus Interface Controller (HBI)
Memory Mapped Structure for HBI Controller
@{ */
typedef struct
{
/**
* @var HBI_T::CMD
* Offset: 0x00 HyperBus Command and Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |HYPCMD |HyperBus Command and Status
* | | |Write
* | | |0001 = Reset HyperRAM.
* | | |0010 = Read HyperRAM regsiter (16-Bit, Read Data[15:0].
* | | |0101 = Exit From Hybrid Sleep and deep power down.
* | | |0111 = Write HyperRAM regsiter (16-Bit, Write Data[15:0].
* | | |1000 = Read 1 word (Read Data[15:0]) from HyperRAM.
* | | |1001 = Read 2 word (Read Data[31:0]) from HyperRAM.
* | | |1100 = Write 1 Byte (Write Data[7:0]) to HyperRAM.
* | | |1101 = Write 2 Bytes (Write Data[15:0]) to HyperRAM.
* | | |1110 = Write 3 Byte (Write Data[23:0]) to HyperRAM.
* | | |1111 = Write 4 Byte (Write Data[31:0]) to HyperRAM.
* | | |Other value = reserved.
* | | |Read
* | | |0000 = HyperBus interface is Idle.
* | | |Other value = HyperBus interface is busy.
* | | |Note: When an operation is Done, the read value automatically return to 4'b0000.
* @var HBI_T::CONFIG
* Offset: 0x04 HyperBus Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |CSST |Chip Select Setup Time to Next CK Rising Edge
* | | |This field indicates the setup time between the chip select and the next CK rising edge
* | | |00 = 1.5 HCLK cycles.
* | | |01 = 2.5 HCLK cycles.
* | | |10 = 3.5 HCLK cycles.
* | | |11 = 4.5 HCLK cycles.
* |[5:2] |ACCT |Initial Access Time
* | | |This field indicates the initial access cycles of the Hyper Bus transaction
* | | |0000 = 5 CK cycles.
* | | |0001 = 6 CK cycles.
* | | |0010 = 7 CK cycles.
* | | |1110 = 3 CK cycles.
* | | |1111 = 4 CK cycles.
* | | |Others = Reserved.
* | | |Note: This field must be set to the same value as
* | | |initial Latency in HyperRAM Configuration Register 0.
* |[7:6] |CSH |Chip Select Hold Time After CK Falling Edge
* | | |This field indicates the hold time between the last CK falling edge and chip select
* | | |00 = 0.5 HCLK cycles.
* | | |01 = 1.5 HCLK cycles.
* | | |10 = 2.5 HCLK cycles.
* | | |11 = 3.5 HCLK cycles.
* |[11:8] |CSHI |Chip Select High between Transaction
* | | |This field indicates the inactive period between two Hyper Bus transactions
* | | |0000 = 1 HCLK cycle.
* | | |0001 = 2 HCLK cycles.
* | | |0010 = 3 HCLK cycles.
* | | |0011 = 4 HCLK cycles.
* | | |...
* | | |1111 = 16 HCLK cycles.
* | | |Note : This field must meet the HyperRAM device specification of tCSHI.
* |[13:12] |BGSIZE |Burst Group Size
* | | |This field indicates the burst length on the Hyper Bus transaction
* | | |00 = 128 Bytes.
* | | |01 = 64 Bytes.
* | | |10 = 16 Bytes.
* | | |11 = 32 Bytes.
* | | |Note : This field must be set to the same value as burst Length in HyperRAM Configuration Regsiter 0.
* |[14] |ENDIAN |Endian Condition on the Hyper Bus Data Pipe
* | | |0 = Little-Endian.
* | | | Byte A = Bits[7:0] of a 16-Bit ..........word
* | | | Byte B = Bits[15:8] of a 16-Bit ..........word
* | | |1 = Big-Endia.
* | | | Byte A = Bits[15:8] of a 16-Bit ..........word
* | | | Byte B = Bits[7:0] of a 16-Bit ..........word
* |[15] |CKDIV |Hyper Bus Clock Divider
* | | | 0 = Hyper Bus Clock rate is HCLK/2.
* | | | 1 = Hyper Bus Clock rate is HCLK/4.
* |[26:16] |CSMAXLT |Chip Select Maximum Low Time
* | | | This field indicates the maximum Low period of the chip select (CS#) in one transaction
* | | | 00000000000 = 1 HCLK cycle.
* | | | 00000000001 = 2 HCLK cycles.
* | | | 00000000010 = 3 HCLK cycles.
* | | | 00000000011 = 4 HCLK cycles.
* | | | ...
* | | | 01011101100 = 749 HCLK cycles (3.9us @192 MHz).
* | | | ...
* | | | 11111111110 = 2047 HCLK cycles.
* | | | 11111111111 = 2048 HCLK cycles.
* | | | Note: This field inidcates the timing of HyperRAM Chip Select specification so that it has to relative the frequency of HCLK and the CLKDIV (HBI_CONFIG[15]).
* @var HBI_T::ADR
* Offset: 0x08 HyperBus Byte Address access Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |HBI_ADR |HyperBus Byte Address
* | | |Memory Space Range:
* | | | 0x0000_0000 ~ 0x01FF_FFFF
* | | |Register Space Range:
* | | | 0X0000_0000 = Identification Register 0
* | | | 0X0000_0002 = Identification Register 1
* | | | 0X0000_1000 = Configuration Register 0
* | | | 0X0000_1002 = Configuration Register 1
* | | |Note:
* | | |1. It is "Byte" address, not "word" address
* | | |2. Up to 32M Bytes of memory space is supported.
* @var HBI_T::WDATA
* Offset: 0x0C HyperBus 32-Bits Write Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |WDATA |HyperBus 32-Bits Write Data
* | | |To write 1 Byte to HyperRAM, Byte 0 (Data[7:0]) is used
* | | |To write 2 Bytes to HyperRAM, Byte 1~0 (Data[15:0]) is used
* | | |To write 3 Bytes to HyperRAM, Byte 2~0 (Data[23:0]) is used
* | | |To write 4 Bytes to HyperRAM, Byte 3~ (Data[31:0]) is used
* @var HBI_T::RDATA
* Offset: 0x10 HyperBus 32-Bits Read Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RDATA |HyperBus 32-Bits Read Data
* | | |32-Bits Data for HyperBus Read
* | | |Note: The data order is depened on the ENDIAN (HBI_CONFIG[14]). Refer to 1.1.5.4 for detail information.
* @var HBI_T::INTEN
* Offset: 0x14 HyperBus Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OPINTEN |HyperBus Operation Done Interrupt Enable
* | | |0 = Operation done interrupt is Disab led.
* | | |1 = Operation done interrupt is Enabled.
* @var HBI_T::INTSTS
* Offset: 0x18 HyperBus Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OPDONE |HyperBus Operation Done Interrupt
* | | |0 = HyperBus operation is busy.
* | | |1 = HyperBus operation is done.
*/
__IO uint32_t CMD ; /*!< [0x0000] HyperBus Command and Status Register */
__IO uint32_t CONFIG; /*!< [0x0004] HyperBus Configuration Register */
__IO uint32_t ADR; /*!< [0x0008] HyperBus Byte Address access Register */
__IO uint32_t WDATA; /*!< [0x000C] HyperBus 32-Bits Write Data Register */
__IO uint32_t RDATA; /*!< [0x0010] HyperBus 32-Bits Read Data Register */
__IO uint32_t INTEN; /*!< [0x0014] HyperBus Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x0018] HyperBus Interrupt Status Register */
} HBI_T;
/**
@addtogroup HBI_CONST HBI Bit Field Definition
Constant Definitions for HBI Controller
@{ */
#define HBI_CMD_HYPCMD_Pos (0) /*!< HBI_T::CMD: HYPCMD Position */
#define HBI_CMD_HYPCMD_Msk (0xful << HBI_CMD_HYPCMD_Pos) /*!< HBI_T::CMD: HYPCMD Mask */
#define HBI_CONFIG_CSST_Pos (0) /*!< HBI_T::CONFIG: CSST Position */
#define HBI_CONFIG_CSST_Msk (0x3ul << HBI_CONFIG_CSST_Pos) /*!< HBI_T::CONFIG: CSST Mask */
#define HBI_CONFIG_ACCT_Pos (2) /*!< HBI_T::CONFIG: ACCT Position */
#define HBI_CONFIG_ACCT_Msk (0xful << HBI_CONFIG_ACCT_Pos) /*!< HBI_T::CONFIG: ACCT Mask */
#define HBI_CONFIG_CSH_Pos (6) /*!< HBI_T::CONFIG: CSH Position */
#define HBI_CONFIG_CSH_Msk (0x3ul << HBI_CONFIG_CSH_Pos) /*!< HBI_T::CONFIG: CSH Mask */
#define HBI_CONFIG_CSHI_Pos (8) /*!< HBI_T::CONFIG: CSHI Position */
#define HBI_CONFIG_CSHI_Msk (0xful << HBI_CONFIG_CSHI_Pos) /*!< HBI_T::CONFIG: CSHI Mask */
#define HBI_CONFIG_BGSIZE_Pos (12) /*!< HBI_T::CONFIG: BGSIZE Position */
#define HBI_CONFIG_BGSIZE_Msk (0x3ul << HBI_CONFIG_BGSIZE_Pos) /*!< HBI_T::CONFIG: BGSIZE Mask */
#define HBI_CONFIG_ENDIAN_Pos (14) /*!< HBI_T::CONFIG: ENDIAN Position */
#define HBI_CONFIG_ENDIAN_Msk (0x1ul << HBI_CONFIG_ENDIAN_Pos) /*!< HBI_T::CONFIG: ENDIAN Mask */
#define HBI_CONFIG_CKDIV_Pos (15) /*!< HBI_T::CONFIG: CKDIV Position */
#define HBI_CONFIG_CKDIV_Msk (0x1ul << HBI_CONFIG_CKDIV_Pos) /*!< HBI_T::CONFIG: CKDIV Mask */
#define HBI_CONFIG_CSMAXLT_Pos (16) /*!< HBI_T::CONFIG: CSMAXLT Position */
#define HBI_CONFIG_CSMAXLT_Msk (0x7fful << HBI_CONFIG_CSMAXLT_Pos) /*!< HBI_T::CONFIG: CSMAXLT Mask */
#define HBI_ADR_ADR_Pos (0) /*!< HBI_T::ADR: ADR Position */
#define HBI_ADR_ADR_Msk (0xfffffffful << HBI_ADR_ADR_Pos) /*!< HBI_T::ADR: ADR Mask */
#define HBI_WDATA_WDATA_Pos (0) /*!< HBI_T::WDATA: WDATA Position */
#define HBI_WDATA_WDATA_Msk (0xfffffffful << HBI_WDATA_WDATA_Pos) /*!< HBI_T::WDATA: WDATA Mask */
#define HBI_RDATA_RDATA_Pos (0) /*!< HBI_T::RDATA: RDATA Position */
#define HBI_RDATA_RDATA_Msk (0xfffffffful << HBI_RDATA_RDATA_Pos) /*!< HBI_T::RDATA: RDATA Mask */
#define HBI_INTEN_OPINTEN_Pos (0) /*!< HBI_T::INTEN: OPINTEN Position */
#define HBI_INTEN_OPINTEN_Msk (0x1ul << HBI_INTEN_OPINTEN_Pos) /*!< HBI_T::INTEN: OPINTEN Mask */
#define HBI_INTSTS_OPDONE_Pos (0) /*!< HBI_T::INTSTS: OPDONE Position */
#define HBI_INTSTS_OPDONE_Msk (0x1ul << HBI_INTSTS_OPDONE_Pos) /*!< HBI_T::INTSTS: OPDONE Mask */
/**@}*/ /* HBI_CONST */
/**@}*/ /* end of HBI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __HBI_REG_H__ */

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/**************************************************************************//**
* @file hsotg_reg.h
* @version V3.00
* @brief HSOTG register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __HSOTG_REG_H__
#define __HSOTG_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup HSOTG High Speed USB On-The-Go Controller(HSOTG)
Memory Mapped Structure for HSOTG Controller
@{ */
typedef struct
{
/**
* @var HSOTG_T::CTL
* Offset: 0x00 HSOTG Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VBUSDROP |Drop VBUS Control
* | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS
* | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
* | | |0 = Not drop the VBUS.
* | | |1 = Drop the VBUS.
* |[1] |BUSREQ |OTG Bus Request
* | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection
* | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power
* | | |This bit will be cleared when A-device goes to A_wait_vfall state
* | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
* | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol
* | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification)
* | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
* | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
* | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
* |[2] |HNPREQEN |OTG HNP Request Enable Bit
* | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral
* | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state
* | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host
* | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
* | | |0 = HNP request Disabled.
* | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
* | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
* |[4] |OTGEN |OTG Function Enable Bit
* | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device
* | | |When USB frame not configured as OTG device, this bit is must be low.
* | | |0= OTG function Disabled.
* | | |1 = OTG function Enabled.
* |[5] |WKEN |OTG ID Pin Wake-up Enable Bit
* | | |0 = OTG ID pin status change wake-up function Disabled.
* | | |1 = OTG ID pin status change wake-up function Enabled.
* @var HSOTG_T::PHYCTL
* Offset: 0x04 HSOTG PHY Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OTGPHYEN |OTG PHY Enable
* | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function
* | | |If device is not configured as OTG-device nor ID-dependent, this bit is "don't care".
* | | |0 = OTG PHY Disabled.
* | | |1 = OTG PHY Enabled.
* |[1] |IDDETEN |ID Detection Enable Bit
* | | |0 = Detect ID pin status Disabled.
* | | |1 = Detect ID pin status Enabled.
* |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity
* | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need
* | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
* | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component
* | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
* | | |0 = The off-chip USB VBUS power switch enable is active high.
* | | |1 = The off-chip USB VBUS power switch enable is active low.
* |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity
* | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component
* | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch
* | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
* | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.
* | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.
* @var HSOTG_T::INTEN
* Offset: 0x08 HSOTG Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[1] |VBEIEN |VBUS Error Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
* |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Going to idle state means going to a_idle or b_idle state
* | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
* |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit
* | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
* | | |0 = This device as a peripheral interrupt Disabled.
* | | |1 = This device as a peripheral interrupt Enabled.
* |[7] |HOSTIEN |Act As Host Interrupt Enable Bit
* | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
* | | |0 = This device as a host interrupt Disabled.
* | | |1 = This device as a host interrupt Enabled.
* |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* @var HSOTG_T::INTSTS
* Offset: 0x0C HSOTG Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ROLECHGIF |OTG Role Change Interrupt Status
* | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
* | | |0 = OTG device role not changed.
* | | |1 = OTG device role changed.
* | | |Note: Write 1 to clear this flag.
* |[1] |VBEIF |VBUS Error Interrupt Status
* | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
* | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
* | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
* | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
* |[2] |SRPFIF |SRP Fail Interrupt Status
* | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification
* | | |This flag is set when the OTG B-device does not get VBUS high after this interval.
* | | |0 = OTG B-device gets VBUS high before this interval.
* | | |1 = OTG B-device does not get VBUS high before this interval.
* | | |Note: Write 1 to clear this flag.
* |[3] |HNPFIF |HNP Fail Interrupt Status
* | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
* | | |0 = A-device connects to B-device before specified interval expires.
* | | |1 = A-device does not connect to B-device before specified interval expires.
* | | |Note: Write 1 to clear this flag.
* |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status
* | | |Flag is set if the OTG device transfers from non-idle state to idle state
* | | |The OTG device will be neither a host nor a peripheral.
* | | |0 = OTG device does not go back to idle state (a_idle or b_idle).
* | | |1 = OTG device goes back to idle state(a_idle or b_idle).
* | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.
* | | |Note 2: Write 1 to clear this flag.
* |[5] |IDCHGIF |ID State Change Interrupt Status
* | | |0 = IDSTS (OTG_STATUS[1]) not toggled.
* | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
* | | |Note: Write 1 to clear this flag.
* |[6] |PDEVIF |Act As Peripheral Interrupt Status
* | | |0= This device does not act as a peripheral.
* | | |1 = This device acts as a peripheral.
* | | |Note: Write 1 to clear this flag.
* |[7] |HOSTIF |Act As Host Interrupt Status
* | | |0= This device does not act as a host.
* | | |1 = This device acts as a host.
* | | |Note: Write 1 to clear this flag.
* |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status
* | | |0 = BVLD (OTG_STATUS[3]) is not toggled.
* | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
* | | |Note: Write 1 to clear this status.
* |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status
* | | |0 = AVLD (OTG_STATUS[4]) not toggled.
* | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
* | | |Note: Write 1 to clear this status.
* |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status
* | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
* | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
* | | |Note: Write 1 to clear this status.
* |[11] |SECHGIF |SESSEND State Change Interrupt Status
* | | |0 = SESSEND (OTG_STATUS[2]) not toggled.
* | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
* | | |Note: Write 1 to clear this flag.
* |[13] |SRPDETIF |SRP Detected Interrupt Status
* | | |0 = SRP not detected.
* | | |1 = SRP detected.
* | | |Note: Write 1 to clear this status.
* @var HSOTG_T::STATUS
* Offset: 0x10 HSOTG Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OVERCUR |over Current Condition
* | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
* | | |0 = OTG A-device drives VBUS successfully.
* | | |1 = OTG A-device cannot drives VBUS high in this interval.
* |[1] |IDSTS |USB_ID Pin State of Mini-b/Micro-plug
* | | |0 = Mini-A/Micro-A plug is attached.
* | | |1 = Mini-B/Micro-B plug is attached.
* |[2] |SESSEND |Session End Status
* | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1
* | | |Session end means no meaningful power on VBUS.
* | | |0 = Session is not end.
* | | |1 = Session is end.
* |[3] |BVLD |B-device Session Valid Status
* | | |0 = B-device session is not valid.
* | | |1 = B-device session is valid.
* |[4] |AVLD |A-device Session Valid Status
* | | |0 = A-device session is not valid.
* | | |1 = A-device session is valid.
* |[5] |VBUSVLD |VBUS Valid Status
* | | |When VBUS is larger than 4.7V and A-device drives VBUS , this bit will be set to 1.
* | | |0 = VBUS is not valid.
* | | |1 = VBUS is valid.
* |[6] |ASPERI |As Peripheral Status
* | | |When OTG as peripheral, this bit is set.
* | | |0: OTG not as peripheral
* | | |1: OTG as peripheral
* |[7] |ASHOST |As Host Status
* | | |When OTG as Host, this bit is set.
* | | |0: OTG not as Host
* | | |1: OTG as Host
*/
__IO uint32_t CTL; /*!< [0x0000] HSOTG Control Register */
__IO uint32_t PHYCTL; /*!< [0x0004] HSOTG PHY Control Register */
__IO uint32_t INTEN; /*!< [0x0008] HSOTG Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x000c] HSOTG Interrupt Status Register */
__I uint32_t STATUS; /*!< [0x0010] HSOTG Status Register */
} HSOTG_T;
/**
@addtogroup HSOTG_CONST HSOTG Bit Field Definition
Constant Definitions for HSOTG Controller
@{ */
#define HSOTG_CTL_VBUSDROP_Pos (0) /*!< HSOTG_T::CTL: VBUSDROP Position */
#define HSOTG_CTL_VBUSDROP_Msk (0x1ul << HSOTG_CTL_VBUSDROP_Pos) /*!< HSOTG_T::CTL: VBUSDROP Mask */
#define HSOTG_CTL_BUSREQ_Pos (1) /*!< HSOTG_T::CTL: BUSREQ Position */
#define HSOTG_CTL_BUSREQ_Msk (0x1ul << HSOTG_CTL_BUSREQ_Pos) /*!< HSOTG_T::CTL: BUSREQ Mask */
#define HSOTG_CTL_HNPREQEN_Pos (2) /*!< HSOTG_T::CTL: HNPREQEN Position */
#define HSOTG_CTL_HNPREQEN_Msk (0x1ul << HSOTG_CTL_HNPREQEN_Pos) /*!< HSOTG_T::CTL: HNPREQEN Mask */
#define HSOTG_CTL_OTGEN_Pos (4) /*!< HSOTG_T::CTL: OTGEN Position */
#define HSOTG_CTL_OTGEN_Msk (0x1ul << HSOTG_CTL_OTGEN_Pos) /*!< HSOTG_T::CTL: OTGEN Mask */
#define HSOTG_CTL_WKEN_Pos (5) /*!< HSOTG_T::CTL: WKEN Position */
#define HSOTG_CTL_WKEN_Msk (0x1ul << HSOTG_CTL_WKEN_Pos) /*!< HSOTG_T::CTL: WKEN Mask */
#define HSOTG_PHYCTL_OTGPHYEN_Pos (0) /*!< HSOTG_T::PHYCTL: OTGPHYEN Position */
#define HSOTG_PHYCTL_OTGPHYEN_Msk (0x1ul << HSOTG_PHYCTL_OTGPHYEN_Pos) /*!< HSOTG_T::PHYCTL: OTGPHYEN Mask */
#define HSOTG_PHYCTL_IDDETEN_Pos (1) /*!< HSOTG_T::PHYCTL: IDDETEN Position */
#define HSOTG_PHYCTL_IDDETEN_Msk (0x1ul << HSOTG_PHYCTL_IDDETEN_Pos) /*!< HSOTG_T::PHYCTL: IDDETEN Mask */
#define HSOTG_PHYCTL_VBENPOL_Pos (4) /*!< HSOTG_T::PHYCTL: VBENPOL Position */
#define HSOTG_PHYCTL_VBENPOL_Msk (0x1ul << HSOTG_PHYCTL_VBENPOL_Pos) /*!< HSOTG_T::PHYCTL: VBENPOL Mask */
#define HSOTG_PHYCTL_VBSTSPOL_Pos (5) /*!< HSOTG_T::PHYCTL: VBSTSPOL Position */
#define HSOTG_PHYCTL_VBSTSPOL_Msk (0x1ul << HSOTG_PHYCTL_VBSTSPOL_Pos) /*!< HSOTG_T::PHYCTL: VBSTSPOL Mask */
#define HSOTG_PHYCTL_FSEL_Pos (8) /*!< HSOTG_T::PHYCTL: FSEL Position */
#define HSOTG_PHYCTL_FSEL_Msk (0x7ul << HSOTG_PHYCTL_FSEL_Pos) /*!< HSOTG_T::PHYCTL: FSEL Mask */
#define HSOTG_INTEN_ROLECHGIEN_Pos (0) /*!< HSOTG_T::INTEN: ROLECHGIEN Position */
#define HSOTG_INTEN_ROLECHGIEN_Msk (0x1ul << HSOTG_INTEN_ROLECHGIEN_Pos) /*!< HSOTG_T::INTEN: ROLECHGIEN Mask */
#define HSOTG_INTEN_VBEIEN_Pos (1) /*!< HSOTG_T::INTEN: VBEIEN Position */
#define HSOTG_INTEN_VBEIEN_Msk (0x1ul << HSOTG_INTEN_VBEIEN_Pos) /*!< HSOTG_T::INTEN: VBEIEN Mask */
#define HSOTG_INTEN_SRPFIEN_Pos (2) /*!< HSOTG_T::INTEN: SRPFIEN Position */
#define HSOTG_INTEN_SRPFIEN_Msk (0x1ul << HSOTG_INTEN_SRPFIEN_Pos) /*!< HSOTG_T::INTEN: SRPFIEN Mask */
#define HSOTG_INTEN_HNPFIEN_Pos (3) /*!< HSOTG_T::INTEN: HNPFIEN Position */
#define HSOTG_INTEN_HNPFIEN_Msk (0x1ul << HSOTG_INTEN_HNPFIEN_Pos) /*!< HSOTG_T::INTEN: HNPFIEN Mask */
#define HSOTG_INTEN_GOIDLEIEN_Pos (4) /*!< HSOTG_T::INTEN: GOIDLEIEN Position */
#define HSOTG_INTEN_GOIDLEIEN_Msk (0x1ul << HSOTG_INTEN_GOIDLEIEN_Pos) /*!< HSOTG_T::INTEN: GOIDLEIEN Mask */
#define HSOTG_INTEN_IDCHGIEN_Pos (5) /*!< HSOTG_T::INTEN: IDCHGIEN Position */
#define HSOTG_INTEN_IDCHGIEN_Msk (0x1ul << HSOTG_INTEN_IDCHGIEN_Pos) /*!< HSOTG_T::INTEN: IDCHGIEN Mask */
#define HSOTG_INTEN_PDEVIEN_Pos (6) /*!< HSOTG_T::INTEN: PDEVIEN Position */
#define HSOTG_INTEN_PDEVIEN_Msk (0x1ul << HSOTG_INTEN_PDEVIEN_Pos) /*!< HSOTG_T::INTEN: PDEVIEN Mask */
#define HSOTG_INTEN_HOSTIEN_Pos (7) /*!< HSOTG_T::INTEN: HOSTIEN Position */
#define HSOTG_INTEN_HOSTIEN_Msk (0x1ul << HSOTG_INTEN_HOSTIEN_Pos) /*!< HSOTG_T::INTEN: HOSTIEN Mask */
#define HSOTG_INTEN_BVLDCHGIEN_Pos (8) /*!< HSOTG_T::INTEN: BVLDCHGIEN Position */
#define HSOTG_INTEN_BVLDCHGIEN_Msk (0x1ul << HSOTG_INTEN_BVLDCHGIEN_Pos) /*!< HSOTG_T::INTEN: BVLDCHGIEN Mask */
#define HSOTG_INTEN_AVLDCHGIEN_Pos (9) /*!< HSOTG_T::INTEN: AVLDCHGIEN Position */
#define HSOTG_INTEN_AVLDCHGIEN_Msk (0x1ul << HSOTG_INTEN_AVLDCHGIEN_Pos) /*!< HSOTG_T::INTEN: AVLDCHGIEN Mask */
#define HSOTG_INTEN_VBCHGIEN_Pos (10) /*!< HSOTG_T::INTEN: VBCHGIEN Position */
#define HSOTG_INTEN_VBCHGIEN_Msk (0x1ul << HSOTG_INTEN_VBCHGIEN_Pos) /*!< HSOTG_T::INTEN: VBCHGIEN Mask */
#define HSOTG_INTEN_SECHGIEN_Pos (11) /*!< HSOTG_T::INTEN: SECHGIEN Position */
#define HSOTG_INTEN_SECHGIEN_Msk (0x1ul << HSOTG_INTEN_SECHGIEN_Pos) /*!< HSOTG_T::INTEN: SECHGIEN Mask */
#define HSOTG_INTEN_SRPDETIEN_Pos (13) /*!< HSOTG_T::INTEN: SRPDETIEN Position */
#define HSOTG_INTEN_SRPDETIEN_Msk (0x1ul << HSOTG_INTEN_SRPDETIEN_Pos) /*!< HSOTG_T::INTEN: SRPDETIEN Mask */
#define HSOTG_INTSTS_ROLECHGIF_Pos (0) /*!< HSOTG_T::INTSTS: ROLECHGIF Position */
#define HSOTG_INTSTS_ROLECHGIF_Msk (0x1ul << HSOTG_INTSTS_ROLECHGIF_Pos) /*!< HSOTG_T::INTSTS: ROLECHGIF Mask */
#define HSOTG_INTSTS_VBEIF_Pos (1) /*!< HSOTG_T::INTSTS: VBEIF Position */
#define HSOTG_INTSTS_VBEIF_Msk (0x1ul << HSOTG_INTSTS_VBEIF_Pos) /*!< HSOTG_T::INTSTS: VBEIF Mask */
#define HSOTG_INTSTS_SRPFIF_Pos (2) /*!< HSOTG_T::INTSTS: SRPFIF Position */
#define HSOTG_INTSTS_SRPFIF_Msk (0x1ul << HSOTG_INTSTS_SRPFIF_Pos) /*!< HSOTG_T::INTSTS: SRPFIF Mask */
#define HSOTG_INTSTS_HNPFIF_Pos (3) /*!< HSOTG_T::INTSTS: HNPFIF Position */
#define HSOTG_INTSTS_HNPFIF_Msk (0x1ul << HSOTG_INTSTS_HNPFIF_Pos) /*!< HSOTG_T::INTSTS: HNPFIF Mask */
#define HSOTG_INTSTS_GOIDLEIF_Pos (4) /*!< HSOTG_T::INTSTS: GOIDLEIF Position */
#define HSOTG_INTSTS_GOIDLEIF_Msk (0x1ul << HSOTG_INTSTS_GOIDLEIF_Pos) /*!< HSOTG_T::INTSTS: GOIDLEIF Mask */
#define HSOTG_INTSTS_IDCHGIF_Pos (5) /*!< HSOTG_T::INTSTS: IDCHGIF Position */
#define HSOTG_INTSTS_IDCHGIF_Msk (0x1ul << HSOTG_INTSTS_IDCHGIF_Pos) /*!< HSOTG_T::INTSTS: IDCHGIF Mask */
#define HSOTG_INTSTS_PDEVIF_Pos (6) /*!< HSOTG_T::INTSTS: PDEVIF Position */
#define HSOTG_INTSTS_PDEVIF_Msk (0x1ul << HSOTG_INTSTS_PDEVIF_Pos) /*!< HSOTG_T::INTSTS: PDEVIF Mask */
#define HSOTG_INTSTS_HOSTIF_Pos (7) /*!< HSOTG_T::INTSTS: HOSTIF Position */
#define HSOTG_INTSTS_HOSTIF_Msk (0x1ul << HSOTG_INTSTS_HOSTIF_Pos) /*!< HSOTG_T::INTSTS: HOSTIF Mask */
#define HSOTG_INTSTS_BVLDCHGIF_Pos (8) /*!< HSOTG_T::INTSTS: BVLDCHGIF Position */
#define HSOTG_INTSTS_BVLDCHGIF_Msk (0x1ul << HSOTG_INTSTS_BVLDCHGIF_Pos) /*!< HSOTG_T::INTSTS: BVLDCHGIF Mask */
#define HSOTG_INTSTS_AVLDCHGIF_Pos (9) /*!< HSOTG_T::INTSTS: AVLDCHGIF Position */
#define HSOTG_INTSTS_AVLDCHGIF_Msk (0x1ul << HSOTG_INTSTS_AVLDCHGIF_Pos) /*!< HSOTG_T::INTSTS: AVLDCHGIF Mask */
#define HSOTG_INTSTS_VBCHGIF_Pos (10) /*!< HSOTG_T::INTSTS: VBCHGIF Position */
#define HSOTG_INTSTS_VBCHGIF_Msk (0x1ul << HSOTG_INTSTS_VBCHGIF_Pos) /*!< HSOTG_T::INTSTS: VBCHGIF Mask */
#define HSOTG_INTSTS_SECHGIF_Pos (11) /*!< HSOTG_T::INTSTS: SECHGIF Position */
#define HSOTG_INTSTS_SECHGIF_Msk (0x1ul << HSOTG_INTSTS_SECHGIF_Pos) /*!< HSOTG_T::INTSTS: SECHGIF Mask */
#define HSOTG_INTSTS_SRPDETIF_Pos (13) /*!< HSOTG_T::INTSTS: SRPDETIF Position */
#define HSOTG_INTSTS_SRPDETIF_Msk (0x1ul << HSOTG_INTSTS_SRPDETIF_Pos) /*!< HSOTG_T::INTSTS: SRPDETIF Mask */
#define HSOTG_STATUS_OVERCUR_Pos (0) /*!< HSOTG_T::STATUS: OVERCUR Position */
#define HSOTG_STATUS_OVERCUR_Msk (0x1ul << HSOTG_STATUS_OVERCUR_Pos) /*!< HSOTG_T::STATUS: OVERCUR Mask */
#define HSOTG_STATUS_IDSTS_Pos (1) /*!< HSOTG_T::STATUS: IDSTS Position */
#define HSOTG_STATUS_IDSTS_Msk (0x1ul << HSOTG_STATUS_IDSTS_Pos) /*!< HSOTG_T::STATUS: IDSTS Mask */
#define HSOTG_STATUS_SESSEND_Pos (2) /*!< HSOTG_T::STATUS: SESSEND Position */
#define HSOTG_STATUS_SESSEND_Msk (0x1ul << HSOTG_STATUS_SESSEND_Pos) /*!< HSOTG_T::STATUS: SESSEND Mask */
#define HSOTG_STATUS_BVLD_Pos (3) /*!< HSOTG_T::STATUS: BVLD Position */
#define HSOTG_STATUS_BVLD_Msk (0x1ul << HSOTG_STATUS_BVLD_Pos) /*!< HSOTG_T::STATUS: BVLD Mask */
#define HSOTG_STATUS_AVLD_Pos (4) /*!< HSOTG_T::STATUS: AVLD Position */
#define HSOTG_STATUS_AVLD_Msk (0x1ul << HSOTG_STATUS_AVLD_Pos) /*!< HSOTG_T::STATUS: AVLD Mask */
#define HSOTG_STATUS_VBUSVLD_Pos (5) /*!< HSOTG_T::STATUS: VBUSVLD Position */
#define HSOTG_STATUS_VBUSVLD_Msk (0x1ul << HSOTG_STATUS_VBUSVLD_Pos) /*!< HSOTG_T::STATUS: VBUSVLD Mask */
#define HSOTG_STATUS_ASPERI_Pos (6) /*!< HSOTG_T::STATUS: ASPERI Position */
#define HSOTG_STATUS_ASPERI_Msk (0x1ul << HSOTG_STATUS_ASPERI_Pos) /*!< HSOTG_T::STATUS: ASPERI Mask */
#define HSOTG_STATUS_ASHOST_Pos (7) /*!< HSOTG_T::STATUS: ASHOST Position */
#define HSOTG_STATUS_ASHOST_Msk (0x1ul << HSOTG_STATUS_ASHOST_Pos) /*!< HSOTG_T::STATUS: ASHOST Mask */
/**@}*/ /* HSOTG_CONST */
/**@}*/ /* end of HSOTG register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __HSOTG_REG_H__ */

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/**************************************************************************//**
* @file hsusbh_reg.h
* @version V1.00
* @brief HSUSBH register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __HSUSBH_REG_H__
#define __HSUSBH_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup HSUSBH High Speed USB Host Controller (HSUSBH)
Memory Mapped Structure for HSUSBH Controller
@{ */
typedef struct
{
/**
* @var HSUSBH_T::EHCVNR
* Offset: 0x00 EHCI Version Number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CRLEN |Capability Registers Length
* | | |This register is used as an offset to add to register base to find the beginning of the Operational Register Space.
* |[31:16] |VERSION |Host Controller Interface Version Number
* | | |This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller
* | | |The most significant byte of this register represents a major revision and the least significant byte is the minor revision.
* @var HSUSBH_T::EHCSPR
* Offset: 0x04 EHCI Structural Parameters Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |N_PORTS |Number of Physical Downstream Ports
* | | |This field specifies the number of physical downstream ports implemented on this host controller
* | | |The value of this field determines how many port registers are addressable in the Operational Register Space (see Table 2-8)
* | | |Valid values are in the range of 1H to FH.
* | | |A zero in this field is undefined.
* |[4] |PPC |Port Power Control
* | | |This field indicates whether the host controller implementation includes port power control
* | | |A one in this bit indicates the ports have port power switches
* | | |A zero in this bit indicates the port do not have port power stitches
* | | |The value of this field affects the functionality of the Port Power field in each port status and control register.
* |[11:8] |N_PCC |Number of Ports Per Companion Controller
* | | |This field indicates the number of ports supported per companion host controller
* | | |It is used to indicate the port routing configuration to system software.
* | | |For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3
* | | |The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc
* | | |In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2.
* | | |The number in this field must be consistent with N_PORTS and N_CC.
* |[15:12] |N_CC |Number of Companion Controller
* | | |This field indicates the number of companion controllers associated with this USB 2.0 host controller.
* | | |A zero in this field indicates there are no companion host controllers
* | | |Port-ownership hand-off is not supported
* | | |Only high-speed devices are supported on the host controller root ports.
* | | |A value larger than zero in this field indicates there are companion USB 1.1 host controller(s)
* | | |Port-ownership hand-offs are supported
* | | |High, Full- and Low-speed devices are supported on the host controller root ports.
* @var HSUSBH_T::EHCCPR
* Offset: 0x08 EHCI Capability Parameters Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |AC64 |64-bit Addressing Capability
* | | |0 = Data structure using 32-bit address memory pointers.
* |[1] |PFLF |Programmable Frame List Flag
* | | |0 = System software must use a frame list length of 1024 elements with this EHCI host controller.
* |[2] |ASPC |Asynchronous Schedule Park Capability
* | | |0 = This EHCI host controller doesn't support park feature of high-speed queue heads in the Asynchronous Schedule.
* |[7:4] |IST |Isochronous Scheduling Threshold
* | | |This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule.
* | | |When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state.
* |[15:8] |EECP |EHCI Extended Capabilities Pointer (EECP)
* | | |0 = No extended capabilities are implemented.
* @var HSUSBH_T::UCMDR
* Offset: 0x20 USB Command Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RUN |Run/Stop (R/W)
* | | |When set to a 1, the Host Controller proceeds with execution of the schedule
* | | |The Host Controller continues execution as long as this bit is set to a 1
* | | |When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts
* | | |The Host Controller must halt within 16 micro-frames after software clears the Run bit
* | | |The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state
* | | |Software must not write a one to this field unless the host controller is in the Halted state (i.e.
* | | |HCHalted in the USBSTS register is a one)
* | | |Doing so will yield undefined results.
* | | |0 = Stop.
* | | |1 = Run.
* |[1] |HCRST |Host Controller Reset (HCRESET) (R/W)
* | | |This control bit is used by software to reset the host controller
* | | |The effects of this on Root Hub registers are similar to a Chip Hardware Reset.
* | | |When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc
* | | |to their initial value
* | | |Any transaction currently in progress on USB is immediately terminated
* | | |A USB reset is not driven on downstream ports.
* | | |All operational registers, including port registers and port state machines are set to their initial values
* | | |Port ownership reverts to the companion host controller(s), with the side effects
* | | |Software must reinitialize the host controller in order to return the host controller to an operational state.
* | | |This bit is set to zero by the Host Controller when the reset process is complete
* | | |Software cannot terminate the reset process early by writing a zero to this register.
* | | |Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero
* | | |Attempting to reset an actively running host controller will result in undefined behavior.
* |[3:2] |FLSZ |Frame List Size (R/W or RO)
* | | |This field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one
* | | |This field specifies the size of the frame list
* | | |The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index
* | | |Values mean:
* | | |00 = 1024 elements (4096 bytes) Default value.
* | | |01 = 512 elements (2048 bytes).
* | | |10 = 256 elements (1024 bytes) u2013 for resource-constrained environment.
* | | |11 = Reserved.
* |[4] |PSEN |Periodic Schedule Enable (R/W)
* | | |This bit controls whether the host controller skips processing the Periodic Schedule. Values mean:
* | | |0 = Do not process the Periodic Schedule.
* | | |1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.
* |[5] |ASEN |Asynchronous Schedule Enable (R/W)
* | | |This bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean:
* | | |0 = Do not process the Asynchronous Schedule.
* | | |1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
* |[6] |IAAD |Interrupt on Asynchronous Advance Doorbell (R/W)
* | | |This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule
* | | |Software must write a 1 to this bit to ring the doorbell.
* | | |When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Asynchronous Advance status bit in the USBSTS register
* | | |If the Interrupt on Asynchronous Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold.
* | | |The host controller sets this bit to a zero after it has set the Interrupt on Asynchronous Advance status bit in the USBSTS register to a one.
* | | |Software should not write a one to this bit when the asynchronous schedule is disabled
* | | |Doing so will yield undefined results.
* |[23:16] |ITC |Interrupt Threshold Control (R/W)
* | | |This field is used by system software to select the maximum rate at which the host controller will issue interrupts
* | | |The only valid values are defined below
* | | |If software writes an invalid value to this register, the results are undefined
* | | |Value Maximum Interrupt Interval
* | | |0x00 = Reserved.
* | | |0x01 = 1 micro-frame.
* | | |0x02 = 2 micro-frames.
* | | |0x04 = 4 micro-frames.
* | | |0x08 = 8 micro-frames (default, equates to 1 ms).
* | | |0x10 = 16 micro-frames (2 ms).
* | | |0x20 = 32 micro-frames (4 ms).
* | | |0x40 = 64 micro-frames (8 ms).
* | | |Any other value in this register yields undefined results.
* | | |Software modifications to this bit while HCHalted bit is equal to zero results in undefined behavior.
* @var HSUSBH_T::USTSR
* Offset: 0x24 USB Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |USBINT |USB Interrupt (USBINT) (R/WC)
* | | |The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set.
* | | |The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes).
* |[1] |UERRINT |USB Error Interrupt (USBERRINT) (R/WC)
* | | |The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow)
* | | |If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set.
* |[2] |PCD |Port Change Detect (R/WC)
* | | |The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port
* | | |This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit.
* | | |This bit is allowed to be maintained in the Auxiliary power well
* | | |Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, over-current change, enable/disable change and connect status change).
* |[3] |FLR |Frame List Rollover (R/WC)
* | | |The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero
* | | |The exact value at which the rollover occurs depends on the frame list size
* | | |For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles
* | | |Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles.
* |[4] |HSERR |Host System Error (R/WC)
* | | |The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module.
* |[5] |IAA |Interrupt on Asynchronous Advance (R/WC)
* | | |System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Asynchronous Advance Doorbell bit in the USBCMD register
* | | |This status bit indicates the assertion of that interrupt source.
* |[12] |HCHalted |HCHalted (RO)
* | | |This bit is a zero whenever the Run/Stop bit is a one
* | | |The Host Controller sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g.
* | | |internal error).
* |[13] |RECLA |Reclamation (RO)
* | | |This is a read-only status bit, which is used to detect an empty asynchronous schedule.
* |[14] |PSS |Periodic Schedule Status (RO)
* | | |The bit reports the current real status of the Periodic Schedule
* | | |If this bit is a zero then the status of the Periodic Schedule is disabled
* | | |If this bit is a one then the status of the Periodic Schedule is enabled
* | | |The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register
* | | |When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0).
* |[15] |ASS |Asynchronous Schedule Status (RO)
* | | |The bit reports the current real status of the Asynchronous Schedule
* | | |If this bit is a zero then the status of them Asynchronous Schedule is disabled
* | | |If this bit is a one then the status of the Asynchronous Schedule is enabled
* | | |The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register
* | | |When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0).
* @var HSUSBH_T::UIENR
* Offset: 0x28 USB Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |USBIEN |USB Interrupt Enable or Disable Bit
* | | |When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold
* | | |The interrupt is acknowledged by software clearing the USBINT bit.
* | | |0 = USB interrupt Disabled.
* | | |1 = USB interrupt Enabled.
* |[1] |UERRIEN |USB Error Interrupt Enable or Disable Bit
* | | |When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host t controller will issue an interrupt at the next interrupt threshold
* | | |The interrupt is acknowledged by software clearing the USBERRINT bit.
* | | |0 = USB Error interrupt Disabled.
* | | |1 = USB Error interrupt Enabled.
* |[2] |PCIEN |Port Change Interrupt Enable or Disable Bit
* | | |When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt
* | | |The interrupt is acknowledged by software clearing the Port Change Detect bit.
* | | |0 = Port Change interrupt Disabled.
* | | |1 = Port Change interrupt Enabled.
* |[3] |FLREN |Frame List Rollover Enable or Disable Bit
* | | |When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt
* | | |The interrupt is acknowledged by software clearing the Frame List Rollover bit.
* | | |0 = Frame List Rollover interrupt Disabled.
* | | |1 = Frame List Rollover interrupt Enabled.
* |[4] |HSERREN |Host System Error Enable or Disable Bit
* | | |When this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt
* | | |The interrupt is acknowledged by software clearing the Host System Error bit.
* | | |0 = Host System Error interrupt Disabled.
* | | |1 = Host System Error interrupt Enabled.
* |[5] |IAAEN |Interrupt on Asynchronous Advance Enable or Disable Bit
* | | |When this bit is a one, and the Interrupt on Asynchronous Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold
* | | |The interrupt is acknowledged by software clearing the Interrupt on Asynchronous Advance bit.
* | | |0 = Interrupt on Asynchronous Advance Disabled.
* | | |1 = Interrupt on Asynchronous Advance Enabled.
* @var HSUSBH_T::UFINDR
* Offset: 0x2C USB Frame Index Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |FI |Frame Index
* | | |The value in this register increment at the end of each time frame (e.g.
* | | |micro-frame)
* | | |Bits [N:3] are used for the Frame List current index
* | | |This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index
* | | |The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register.
* | | |FLSZ (UCMDR[3:2] Number Elements N
* | | |0x0 1024 12
* | | |0x1 512 11
* | | |0x2 256 10
* | | |0x3 Reserved
* @var HSUSBH_T::UPFLBAR
* Offset: 0x34 USB Periodic Frame List Base Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |BADDR |Base Address
* | | |These bits correspond to memory address signals [31:12], respectively.
* @var HSUSBH_T::UCALAR
* Offset: 0x38 USB Current Asynchronous List Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:5] |LPL |Link Pointer Low (LPL)
* | | |These bits correspond to memory address signals [31:5], respectively
* | | |This field may only reference a Queue Head (QH).
* @var HSUSBH_T::UASSTR
* Offset: 0x3C USB Asynchronous Schedule Sleep Timer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |ASSTMR |Asynchronous Schedule Sleep Timer
* | | |This field defines the AsyncSchedSleepTime of EHCI spec.
* | | |The asynchronous schedule sleep timer is used to control how often the host controller fetches asynchronous schedule list from system memory while the asynchronous schedule is empty.
* | | |The default value of this timer is 12'hBD6
* | | |Because this timer is implemented in UTMI clock (30MHz) domain, the default sleeping time will be about 100us.
* @var HSUSBH_T::UCFGR
* Offset: 0x60 USB Configure Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CF |Configure Flag (CF)
* | | |Host software sets this bit as the last action in its process of configuring the Host Controller
* | | |This bit controls the default port-routing control logic
* | | |Bit values and side-effects are listed below.
* | | |0 = Port routing control logic default-routes each port to an implementation dependent classic host controller.
* | | |1 = Port routing control logic default-routes all ports to this host controller.
* @var HSUSBH_T::UPSCR[2]
* Offset: 0x64~0x68 USB Port 0~1 Status and Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CCS |Current Connect Status (RO)
* | | |This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.
* | | |This field is zero if Port Power is zero.
* | | |0 = No device is present.
* | | |1 = Device is present on port.
* |[1] |CSC |Connect Status Change (R/W)
* | | |Indicates a change has occurred in the port's Current Connect Status
* | | |The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change
* | | |For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (i.e., the bit will remain set).Software sets this bit to 0 by writing a 1 to it.
* | | |This field is zero if Port Power is zero.
* | | |0 = No change.
* | | |1 = Change in Current Connect Status.
* |[2] |PE |Port Enabled/Disabled (R/W)
* | | |Ports can only be enabled by the host controller as a part of the reset and enable
* | | |Software cannot enable a port by writing a one to this field
* | | |The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device.
* | | |Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software
* | | |Note that the bit status does not change until the port state actually changes
* | | |There may be a delay in disabling or enabling a port due to other host controller and bus events.
* | | |When the port is disabled (0b) downstream propagation of data is blocked on this port, except for reset.
* | | |This field is zero if Port Power is zero.
* | | |0 = Port Disabled.
* | | |1 = Port Enabled.
* |[3] |PEC |Port Enable/Disable Change (R/WC)
* | | |For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error)
* | | |Software clears this bit by writing a 1 to it.
* | | |This field is zero if Port Power is zero.
* | | |0 = No change.
* | | |1 = Port enabled/disabled status has changed.
* |[4] |OCA |Over-current Active (RO)
* | | |This bit will automatically transition from a one to a zero when the over current condition is removed.
* | | |0 = This port does not have an over-current condition.
* | | |1 = This port currently has an over-current condition.
* |[5] |OCC |Over-current Change (R/WC)
* | | |1 = This bit gets set to a one when there is a change to Over-current Active
* | | |Software clears this bit by writing a one to this bit position.
* |[6] |FPR |Force Port Resume (R/W)
* | | |This functionality defined for manipulating this bit depends on the value of the Suspend bit
* | | |For example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined.
* | | |Software sets this bit to a 1 to drive resume signaling
* | | |The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state
* | | |When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one
* | | |If software sets this bit to a one, the host controller must not set the Port Change Detect bit.
* | | |Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0
* | | |The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one
* | | |Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed
* | | |Writing a zero (from one) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle)
* | | |This bit will remain a one until the port has switched to the high-speed idle
* | | |The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero.
* | | |This field is zero if Port Power is zero.
* | | |0 = No resume (K-state) detected/driven on port.
* | | |1 = Resume detected/driven on port.
* |[7] |SUSPEND |Suspend (R/W)
* | | |Port Enabled Bit and Suspend bit of this register define the port states as follows:
* | | |Port enable is 0 and suspend is 0 = Disable.
* | | |Port enable is 0 and suspend is 1 = Disable.
* | | |Port enable is 1 and suspend is 0 = Enable.
* | | |Port enable is 1 and suspend is 1 = Suspend.
* | | |When in suspend state, downstream propagation of data is blocked on this port, except for port reset
* | | |The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1
* | | |In the suspend state, the port is sensitive to resume detection
* | | |Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.
* | | |A write of zero to this bit is ignored by the host controller
* | | |The host controller will unconditionally set this bit to a zero when:
* | | |Software sets the Force Port Resume bit to a zero (from a one).
* | | |Software sets the Port Reset bit to a one (from a zero).
* | | |If host software sets this bit to a one when the port is not enabled (i.e.
* | | |Port enabled bit is a zero) the results are undefined.
* | | |This field is zero if Port Power is zero.
* | | |0 = Port not in suspend state.
* | | |1 = Port in suspend state.
* |[8] |PRST |Port Reset (R/W)
* | | |When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started
* | | |Software writes a zero to this bit to terminate the bus reset sequence
* | | |Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes
* | | |Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit.
* | | |Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero
* | | |The bit status will not read as a zero until after the reset has completed
* | | |If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g.
* | | |set the Port Enable bit to a one)
* | | |A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero
* | | |For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a zero.
* | | |The HCHalted bit in the USBSTS register should be a zero before software attempts to use this bit
* | | |The host controller may hold Port Reset asserted to a one when the HCHalted bit is a one.
* | | |This field is zero if Port Power is zero.
* | | |0 = Port is not in Reset.
* | | |1 = Port is in Reset.
* |[11:10] |LSTS |Line Status (RO)
* | | |These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines
* | | |These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence
* | | |This field is valid only when the port enable bit is zero and the current connect status bit is set to a one.
* | | |The encoding of the bits are:
* | | |Bits[11:10] USB State Interpretation
* | | |00 = SE0 Not Low-speed device, perform EHCI reset.
* | | |01 = K-state Low-speed device, release ownership of port.
* | | |10 = J-state Not Low-speed device, perform EHCI reset.
* | | |11 = Undefined Not Low-speed device, perform EHCI reset.
* | | |This value of this field is undefined if Port Power is zero.
* |[12] |PP |Port Power (PP)
* | | |Host controller has port power control switches
* | | |This bit represents the Current setting of the switch (0 = off, 1 = on)
* | | |When power is not available on a port (i.e.
* | | |PP equals a 0), the port is nonfunctional and will not report attaches, detaches, etc.
* | | |When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port).
* |[13] |PO |Port Owner (R/W)
* | | |This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0 to 1 transition
* | | |This bit unconditionally goes to 1 whenever the Configured bit is zero.
* | | |System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device)
* | | |Software writes a one to this bit when the attached device is not a high-speed device
* | | |A one in this bit means that a companion host controller owns and controls the port.
* |[19:16] |PTC |Port Test Control (R/W)
* | | |When this field is zero, the port is NOT operating in a test mode
* | | |A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value
* | | |The encoding of the test mode bits are (0x6 ~ 0xF are reserved):
* | | |Bits Test Mode
* | | |0x0 = Test mode not enabled.
* | | |0x1 = Test J_STATE.
* | | |0x2 = Test K_STATE.
* | | |0x3 = Test SE0_NAK.
* | | |0x4 = Test Packet.
* | | |0x5 = Test FORCE_ENABLE.
* @var HSUSBH_T::USBPCR0
* Offset: 0xC4 USB PHY 0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8] |SUSPEND |Suspend Assertion
* | | |This bit controls the suspend mode of USB PHY 0.
* | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state.
* | | |This bit is 1'b0 in default
* | | |This means the USB PHY 0 is suspended in default
* | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host.
* | | |0 = USB PHY 0 was suspended.
* | | |1 = USB PHY 0 was not suspended.
* |[11] |CLKVALID |UTMI Clock Valid
* | | |This bit is a flag to indicate if the UTMI clock from USB 2.0 PHY is ready
* | | |S/W program must prevent to write other control registers before this UTMI clock valid flag is active.
* | | |0 = UTMI clock is not valid.
* | | |1 = UTMI clock is valid.
* @var HSUSBH_T::USBPCR1
* Offset: 0xC8 USB PHY 1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8] |SUSPEND |Suspend Assertion
* | | |This bit controls the suspend mode of USB PHY 1.
* | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state.
* | | |This bit is 1'b0 in default
* | | |This means the USB PHY 0 is suspended in default
* | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host.
* | | |0 = USB PHY 1 was suspended.
* | | |1 = USB PHY 1 was not suspended.
*/
__I uint32_t EHCVNR; /*!< [0x0000] EHCI Version Number Register */
__I uint32_t EHCSPR; /*!< [0x0004] EHCI Structural Parameters Register */
__I uint32_t EHCCPR; /*!< [0x0008] EHCI Capability Parameters Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[5];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t UCMDR; /*!< [0x0020] USB Command Register */
__IO uint32_t USTSR; /*!< [0x0024] USB Status Register */
__IO uint32_t UIENR; /*!< [0x0028] USB Interrupt Enable Register */
__IO uint32_t UFINDR; /*!< [0x002c] USB Frame Index Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t UPFLBAR; /*!< [0x0034] USB Periodic Frame List Base Address Register */
__IO uint32_t UCALAR; /*!< [0x0038] USB Current Asynchronous List Address Register */
__IO uint32_t UASSTR; /*!< [0x003c] USB Asynchronous Schedule Sleep Timer Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[8];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t UCFGR; /*!< [0x0060] USB Configure Flag Register */
__IO uint32_t UPSCR[2]; /*!< [0x0064] ~ [0x0068] USB Port 0 & 1 Status and Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[22];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t USBPCR0; /*!< [0x00c4] USB PHY 0 Control Register */
__IO uint32_t USBPCR1; /*!< [0x00c8] USB PHY 1 Control Register */
} HSUSBH_T;
/**
@addtogroup HSUSBH_CONST HSUSBH Bit Field Definition
Constant Definitions for HSUSBH Controller
@{ */
#define HSUSBH_EHCVNR_CRLEN_Pos (0) /*!< HSUSBH_T::EHCVNR: CRLEN Position */
#define HSUSBH_EHCVNR_CRLEN_Msk (0xfful << HSUSBH_EHCVNR_CRLEN_Pos) /*!< HSUSBH_T::EHCVNR: CRLEN Mask */
#define HSUSBH_EHCVNR_VERSION_Pos (16) /*!< HSUSBH_T::EHCVNR: VERSION Position */
#define HSUSBH_EHCVNR_VERSION_Msk (0xfffful << HSUSBH_EHCVNR_VERSION_Pos) /*!< HSUSBH_T::EHCVNR: VERSION Mask */
#define HSUSBH_EHCSPR_N_PORTS_Pos (0) /*!< HSUSBH_T::EHCSPR: N_PORTS Position */
#define HSUSBH_EHCSPR_N_PORTS_Msk (0xful << HSUSBH_EHCSPR_N_PORTS_Pos) /*!< HSUSBH_T::EHCSPR: N_PORTS Mask */
#define HSUSBH_EHCSPR_PPC_Pos (4) /*!< HSUSBH_T::EHCSPR: PPC Position */
#define HSUSBH_EHCSPR_PPC_Msk (0x1ul << HSUSBH_EHCSPR_PPC_Pos) /*!< HSUSBH_T::EHCSPR: PPC Mask */
#define HSUSBH_EHCSPR_N_PCC_Pos (8) /*!< HSUSBH_T::EHCSPR: N_PCC Position */
#define HSUSBH_EHCSPR_N_PCC_Msk (0xful << HSUSBH_EHCSPR_N_PCC_Pos) /*!< HSUSBH_T::EHCSPR: N_PCC Mask */
#define HSUSBH_EHCSPR_N_CC_Pos (12) /*!< HSUSBH_T::EHCSPR: N_CC Position */
#define HSUSBH_EHCSPR_N_CC_Msk (0xful << HSUSBH_EHCSPR_N_CC_Pos) /*!< HSUSBH_T::EHCSPR: N_CC Mask */
#define HSUSBH_EHCCPR_AC64_Pos (0) /*!< HSUSBH_T::EHCCPR: AC64 Position */
#define HSUSBH_EHCCPR_AC64_Msk (0x1ul << HSUSBH_EHCCPR_AC64_Pos) /*!< HSUSBH_T::EHCCPR: AC64 Mask */
#define HSUSBH_EHCCPR_PFLF_Pos (1) /*!< HSUSBH_T::EHCCPR: PFLF Position */
#define HSUSBH_EHCCPR_PFLF_Msk (0x1ul << HSUSBH_EHCCPR_PFLF_Pos) /*!< HSUSBH_T::EHCCPR: PFLF Mask */
#define HSUSBH_EHCCPR_ASPC_Pos (2) /*!< HSUSBH_T::EHCCPR: ASPC Position */
#define HSUSBH_EHCCPR_ASPC_Msk (0x1ul << HSUSBH_EHCCPR_ASPC_Pos) /*!< HSUSBH_T::EHCCPR: ASPC Mask */
#define HSUSBH_EHCCPR_IST_Pos (4) /*!< HSUSBH_T::EHCCPR: IST Position */
#define HSUSBH_EHCCPR_IST_Msk (0xful << HSUSBH_EHCCPR_IST_Pos) /*!< HSUSBH_T::EHCCPR: IST Mask */
#define HSUSBH_EHCCPR_EECP_Pos (8) /*!< HSUSBH_T::EHCCPR: EECP Position */
#define HSUSBH_EHCCPR_EECP_Msk (0xfful << HSUSBH_EHCCPR_EECP_Pos) /*!< HSUSBH_T::EHCCPR: EECP Mask */
#define HSUSBH_UCMDR_RUN_Pos (0) /*!< HSUSBH_T::UCMDR: RUN Position */
#define HSUSBH_UCMDR_RUN_Msk (0x1ul << HSUSBH_UCMDR_RUN_Pos) /*!< HSUSBH_T::UCMDR: RUN Mask */
#define HSUSBH_UCMDR_HCRST_Pos (1) /*!< HSUSBH_T::UCMDR: HCRST Position */
#define HSUSBH_UCMDR_HCRST_Msk (0x1ul << HSUSBH_UCMDR_HCRST_Pos) /*!< HSUSBH_T::UCMDR: HCRST Mask */
#define HSUSBH_UCMDR_FLSZ_Pos (2) /*!< HSUSBH_T::UCMDR: FLSZ Position */
#define HSUSBH_UCMDR_FLSZ_Msk (0x3ul << HSUSBH_UCMDR_FLSZ_Pos) /*!< HSUSBH_T::UCMDR: FLSZ Mask */
#define HSUSBH_UCMDR_PSEN_Pos (4) /*!< HSUSBH_T::UCMDR: PSEN Position */
#define HSUSBH_UCMDR_PSEN_Msk (0x1ul << HSUSBH_UCMDR_PSEN_Pos) /*!< HSUSBH_T::UCMDR: PSEN Mask */
#define HSUSBH_UCMDR_ASEN_Pos (5) /*!< HSUSBH_T::UCMDR: ASEN Position */
#define HSUSBH_UCMDR_ASEN_Msk (0x1ul << HSUSBH_UCMDR_ASEN_Pos) /*!< HSUSBH_T::UCMDR: ASEN Mask */
#define HSUSBH_UCMDR_IAAD_Pos (6) /*!< HSUSBH_T::UCMDR: IAAD Position */
#define HSUSBH_UCMDR_IAAD_Msk (0x1ul << HSUSBH_UCMDR_IAAD_Pos) /*!< HSUSBH_T::UCMDR: IAAD Mask */
#define HSUSBH_UCMDR_ITC_Pos (16) /*!< HSUSBH_T::UCMDR: ITC Position */
#define HSUSBH_UCMDR_ITC_Msk (0xfful << HSUSBH_UCMDR_ITC_Pos) /*!< HSUSBH_T::UCMDR: ITC Mask */
#define HSUSBH_USTSR_USBINT_Pos (0) /*!< HSUSBH_T::USTSR: USBINT Position */
#define HSUSBH_USTSR_USBINT_Msk (0x1ul << HSUSBH_USTSR_USBINT_Pos) /*!< HSUSBH_T::USTSR: USBINT Mask */
#define HSUSBH_USTSR_UERRINT_Pos (1) /*!< HSUSBH_T::USTSR: UERRINT Position */
#define HSUSBH_USTSR_UERRINT_Msk (0x1ul << HSUSBH_USTSR_UERRINT_Pos) /*!< HSUSBH_T::USTSR: UERRINT Mask */
#define HSUSBH_USTSR_PCD_Pos (2) /*!< HSUSBH_T::USTSR: PCD Position */
#define HSUSBH_USTSR_PCD_Msk (0x1ul << HSUSBH_USTSR_PCD_Pos) /*!< HSUSBH_T::USTSR: PCD Mask */
#define HSUSBH_USTSR_FLR_Pos (3) /*!< HSUSBH_T::USTSR: FLR Position */
#define HSUSBH_USTSR_FLR_Msk (0x1ul << HSUSBH_USTSR_FLR_Pos) /*!< HSUSBH_T::USTSR: FLR Mask */
#define HSUSBH_USTSR_HSERR_Pos (4) /*!< HSUSBH_T::USTSR: HSERR Position */
#define HSUSBH_USTSR_HSERR_Msk (0x1ul << HSUSBH_USTSR_HSERR_Pos) /*!< HSUSBH_T::USTSR: HSERR Mask */
#define HSUSBH_USTSR_IAA_Pos (5) /*!< HSUSBH_T::USTSR: IAA Position */
#define HSUSBH_USTSR_IAA_Msk (0x1ul << HSUSBH_USTSR_IAA_Pos) /*!< HSUSBH_T::USTSR: IAA Mask */
#define HSUSBH_USTSR_HCHalted_Pos (12) /*!< HSUSBH_T::USTSR: HCHalted Position */
#define HSUSBH_USTSR_HCHalted_Msk (0x1ul << HSUSBH_USTSR_HCHalted_Pos) /*!< HSUSBH_T::USTSR: HCHalted Mask */
#define HSUSBH_USTSR_RECLA_Pos (13) /*!< HSUSBH_T::USTSR: RECLA Position */
#define HSUSBH_USTSR_RECLA_Msk (0x1ul << HSUSBH_USTSR_RECLA_Pos) /*!< HSUSBH_T::USTSR: RECLA Mask */
#define HSUSBH_USTSR_PSS_Pos (14) /*!< HSUSBH_T::USTSR: PSS Position */
#define HSUSBH_USTSR_PSS_Msk (0x1ul << HSUSBH_USTSR_PSS_Pos) /*!< HSUSBH_T::USTSR: PSS Mask */
#define HSUSBH_USTSR_ASS_Pos (15) /*!< HSUSBH_T::USTSR: ASS Position */
#define HSUSBH_USTSR_ASS_Msk (0x1ul << HSUSBH_USTSR_ASS_Pos) /*!< HSUSBH_T::USTSR: ASS Mask */
#define HSUSBH_UIENR_USBIEN_Pos (0) /*!< HSUSBH_T::UIENR: USBIEN Position */
#define HSUSBH_UIENR_USBIEN_Msk (0x1ul << HSUSBH_UIENR_USBIEN_Pos) /*!< HSUSBH_T::UIENR: USBIEN Mask */
#define HSUSBH_UIENR_UERRIEN_Pos (1) /*!< HSUSBH_T::UIENR: UERRIEN Position */
#define HSUSBH_UIENR_UERRIEN_Msk (0x1ul << HSUSBH_UIENR_UERRIEN_Pos) /*!< HSUSBH_T::UIENR: UERRIEN Mask */
#define HSUSBH_UIENR_PCIEN_Pos (2) /*!< HSUSBH_T::UIENR: PCIEN Position */
#define HSUSBH_UIENR_PCIEN_Msk (0x1ul << HSUSBH_UIENR_PCIEN_Pos) /*!< HSUSBH_T::UIENR: PCIEN Mask */
#define HSUSBH_UIENR_FLREN_Pos (3) /*!< HSUSBH_T::UIENR: FLREN Position */
#define HSUSBH_UIENR_FLREN_Msk (0x1ul << HSUSBH_UIENR_FLREN_Pos) /*!< HSUSBH_T::UIENR: FLREN Mask */
#define HSUSBH_UIENR_HSERREN_Pos (4) /*!< HSUSBH_T::UIENR: HSERREN Position */
#define HSUSBH_UIENR_HSERREN_Msk (0x1ul << HSUSBH_UIENR_HSERREN_Pos) /*!< HSUSBH_T::UIENR: HSERREN Mask */
#define HSUSBH_UIENR_IAAEN_Pos (5) /*!< HSUSBH_T::UIENR: IAAEN Position */
#define HSUSBH_UIENR_IAAEN_Msk (0x1ul << HSUSBH_UIENR_IAAEN_Pos) /*!< HSUSBH_T::UIENR: IAAEN Mask */
#define HSUSBH_UFINDR_FI_Pos (0) /*!< HSUSBH_T::UFINDR: FI Position */
#define HSUSBH_UFINDR_FI_Msk (0x3ffful << HSUSBH_UFINDR_FI_Pos) /*!< HSUSBH_T::UFINDR: FI Mask */
#define HSUSBH_UPFLBAR_BADDR_Pos (12) /*!< HSUSBH_T::UPFLBAR: BADDR Position */
#define HSUSBH_UPFLBAR_BADDR_Msk (0xffffful << HSUSBH_UPFLBAR_BADDR_Pos) /*!< HSUSBH_T::UPFLBAR: BADDR Mask */
#define HSUSBH_UCALAR_LPL_Pos (5) /*!< HSUSBH_T::UCALAR: LPL Position */
#define HSUSBH_UCALAR_LPL_Msk (0x7fffffful << HSUSBH_UCALAR_LPL_Pos) /*!< HSUSBH_T::UCALAR: LPL Mask */
#define HSUSBH_UASSTR_ASSTMR_Pos (0) /*!< HSUSBH_T::UASSTR: ASSTMR Position */
#define HSUSBH_UASSTR_ASSTMR_Msk (0xffful << HSUSBH_UASSTR_ASSTMR_Pos) /*!< HSUSBH_T::UASSTR: ASSTMR Mask */
#define HSUSBH_UCFGR_CF_Pos (0) /*!< HSUSBH_T::UCFGR: CF Position */
#define HSUSBH_UCFGR_CF_Msk (0x1ul << HSUSBH_UCFGR_CF_Pos) /*!< HSUSBH_T::UCFGR: CF Mask */
#define HSUSBH_UPSCR_CCS_Pos (0) /*!< HSUSBH_T::UPSCR[2]: CCS Position */
#define HSUSBH_UPSCR_CCS_Msk (0x1ul << HSUSBH_UPSCR_CCS_Pos) /*!< HSUSBH_T::UPSCR[2]: CCS Mask */
#define HSUSBH_UPSCR_CSC_Pos (1) /*!< HSUSBH_T::UPSCR[2]: CSC Position */
#define HSUSBH_UPSCR_CSC_Msk (0x1ul << HSUSBH_UPSCR_CSC_Pos) /*!< HSUSBH_T::UPSCR[2]: CSC Mask */
#define HSUSBH_UPSCR_PE_Pos (2) /*!< HSUSBH_T::UPSCR[2]: PE Position */
#define HSUSBH_UPSCR_PE_Msk (0x1ul << HSUSBH_UPSCR_PE_Pos) /*!< HSUSBH_T::UPSCR[2]: PE Mask */
#define HSUSBH_UPSCR_PEC_Pos (3) /*!< HSUSBH_T::UPSCR[2]: PEC Position */
#define HSUSBH_UPSCR_PEC_Msk (0x1ul << HSUSBH_UPSCR_PEC_Pos) /*!< HSUSBH_T::UPSCR[2]: PEC Mask */
#define HSUSBH_UPSCR_OCA_Pos (4) /*!< HSUSBH_T::UPSCR[2]: OCA Position */
#define HSUSBH_UPSCR_OCA_Msk (0x1ul << HSUSBH_UPSCR_OCA_Pos) /*!< HSUSBH_T::UPSCR[2]: OCA Mask */
#define HSUSBH_UPSCR_OCC_Pos (5) /*!< HSUSBH_T::UPSCR[2]: OCC Position */
#define HSUSBH_UPSCR_OCC_Msk (0x1ul << HSUSBH_UPSCR_OCC_Pos) /*!< HSUSBH_T::UPSCR[2]: OCC Mask */
#define HSUSBH_UPSCR_FPR_Pos (6) /*!< HSUSBH_T::UPSCR[2]: FPR Position */
#define HSUSBH_UPSCR_FPR_Msk (0x1ul << HSUSBH_UPSCR_FPR_Pos) /*!< HSUSBH_T::UPSCR[2]: FPR Mask */
#define HSUSBH_UPSCR_SUSPEND_Pos (7) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Position */
#define HSUSBH_UPSCR_SUSPEND_Msk (0x1ul << HSUSBH_UPSCR_SUSPEND_Pos) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Mask */
#define HSUSBH_UPSCR_PRST_Pos (8) /*!< HSUSBH_T::UPSCR[2]: PRST Position */
#define HSUSBH_UPSCR_PRST_Msk (0x1ul << HSUSBH_UPSCR_PRST_Pos) /*!< HSUSBH_T::UPSCR[2]: PRST Mask */
#define HSUSBH_UPSCR_LSTS_Pos (10) /*!< HSUSBH_T::UPSCR[2]: LSTS Position */
#define HSUSBH_UPSCR_LSTS_Msk (0x3ul << HSUSBH_UPSCR_LSTS_Pos) /*!< HSUSBH_T::UPSCR[2]: LSTS Mask */
#define HSUSBH_UPSCR_PP_Pos (12) /*!< HSUSBH_T::UPSCR[2]: PP Position */
#define HSUSBH_UPSCR_PP_Msk (0x1ul << HSUSBH_UPSCR_PP_Pos) /*!< HSUSBH_T::UPSCR[2]: PP Mask */
#define HSUSBH_UPSCR_PO_Pos (13) /*!< HSUSBH_T::UPSCR[2]: PO Position */
#define HSUSBH_UPSCR_PO_Msk (0x1ul << HSUSBH_UPSCR_PO_Pos) /*!< HSUSBH_T::UPSCR[2]: PO Mask */
#define HSUSBH_UPSCR_PTC_Pos (16) /*!< HSUSBH_T::UPSCR[2]: PTC Position */
#define HSUSBH_UPSCR_PTC_Msk (0xful << HSUSBH_UPSCR_PTC_Pos) /*!< HSUSBH_T::UPSCR[2]: PTC Mask */
#define HSUSBH_USBPCR0_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR0: SUSPEND Position */
#define HSUSBH_USBPCR0_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR0_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR0: SUSPEND Mask */
#define HSUSBH_USBPCR0_CLKVALID_Pos (11) /*!< HSUSBH_T::USBPCR0: CLKVALID Position */
#define HSUSBH_USBPCR0_CLKVALID_Msk (0x1ul << HSUSBH_USBPCR0_CLKVALID_Pos) /*!< HSUSBH_T::USBPCR0: CLKVALID Mask */
#define HSUSBH_USBPCR1_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR1: SUSPEND Position */
#define HSUSBH_USBPCR1_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR1_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR1: SUSPEND Mask */
/**@}*/ /* HSUSBH_CONST */
/**@}*/ /* end of HSUSBH register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __HSUSBH_REG_H__ */

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/**************************************************************************//**
* @file i2c_reg.h
* @version V1.00
* @brief I2C register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __I2C_REG_H__
#define __I2C_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup I2C Inter-IC Bus Controller(I2C)
Memory Mapped Structure for I2C Controller
@{ */
typedef struct
{
/**
* @var I2C_T::CTL0
* Offset: 0x00 I2C Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2] |AA |Assert Acknowledge Control
* | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
* | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line
* |[3] |SI |I2C Interrupt Flag
* | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware
* | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested
* | | |SI must be cleared by software
* | | |Clear SI by writing 1 to this bit.
* | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
* |[4] |STO |I2C STOP Control
* | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected
* | | |This bit will be cleared by hardware automatically.
* |[5] |STA |I2C START Control
* | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
* |[6] |I2CEN |I2C Controller Enable Bit
* | | |Set to enable I2C serial function controller
* | | |When I2CEN=1 the I2C serial function enable
* | | |The multi-function pin function must set to SDA, and SCL of I2C function first.
* | | |0 = I2C controller Disabled.
* | | |1 = I2C controller Enabled.
* |[7] |INTEN |Enable Interrupt
* | | |0 = I2C interrupt Disabled.
* | | |1 = I2C interrupt Enabled.
* |[9:8] |DPBITSEL |Data Phase Bit Count Select
* | | |00 = DPCIF never set by hardware.
* | | |01 = When I2C is transfer data and bit count equal to 6, DPCIF will be set by hardware.
* | | |10 = When I2C is transfer data and bit count equal to 7, DPCIF will be set by hardware.
* | | |11 = When I2C is transfer data and bit count equal to 8, DPCIF will be set by hardware.
* |[12] |DPCINTEN |Data Phase Count Interrupt Enable Bit
* | | |0 = Data Phase Count Interrupt Disabled.
* | | |1 = Data Phase Count Interrupt Enabled.
* |[13] |SRCINTEN |Slave Read Command Interrupt Enable Bit
* | | |0 = Slave Read Command Interrupt Disabled.
* | | |1 = Slave Read Command Interrupt Enabled.
* |[14] |DPCIF |Data Phase Count Interrupt Flag
* | | |This bit is set by hardware when I2C transfer bit count equal to DPBITSEL setting
* | | |This bit is cleared by write 1 to it.
* |[15] |SARCIF |Slave Address Read Command Interrupt Flag
* | | |This bit is set by hardware when I2C receive address match read command.
* | | |This bit is cleared by write 1 to it.
* @var I2C_T::ADDR0
* Offset: 0x04 I2C Slave Address Register0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* | | |Note: When software set 10'h000, the address can not be used.
* @var I2C_T::DAT
* Offset: 0x08 I2C Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DAT |I2C Data
* | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
* @var I2C_T::STATUS0
* Offset: 0x0C I2C Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |STATUS |I2C Status
* | | |The three least significant bits are always 0
* | | |The five most significant bits contain the status code
* | | |There are 28 possible status codes
* | | |When the content of I2C_STATUS is F8H, no serial interrupt is requested
* | | |Others I2C_STATUS values correspond to defined I2C states
* | | |When each of these states is entered, a status interrupt is requested (SI = 1)
* | | |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software
* | | |In addition, states 00H stands for a Bus Error
* | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
* | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
* @var I2C_T::CLKDIV
* Offset: 0x10 I2C Clock Divided Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |DIVIDER |I2C Clock Divided
* | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
* | | |Note: The minimum value of I2C_CLKDIV is 4.
* |[15:12] |NFCNT |Noise Filter Count
* | | |The register bits control the input filter width.
* | | |0 = filter width 3*PCLK
* | | |1 = filter width 4*PCLK
* | | |N = filter width (3+N)*PCKL
* | | |Note: Filter width Min :3*PCLK, Max : 18*PCLK
* @var I2C_T::TOCTL
* Offset: 0x14 I2C Time-out Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOIF |Time-out Flag
* | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
* | | |Note: Software can write 1 to clear this bit.
* |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4
* | | |When Enabled, The time-out period is extend 4 times.
* | | |0 = Time-out period is extend 4 times Disabled.
* | | |1 = Time-out period is extend 4 times Enabled.
* |[2] |TOCEN |Time-out Counter Enable Bit
* | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear
* | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
* | | |0 = Time-out counter Disabled.
* | | |1 = Time-out counter Enabled.
* @var I2C_T::ADDR1
* Offset: 0x18 I2C Slave Address Register1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* | | |Note: When software set 10'h000, the address can not be used.
* @var I2C_T::ADDR2
* Offset: 0x1C I2C Slave Address Register2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* | | |Note: When software set 10'h000, the address can not be used.
* @var I2C_T::ADDR3
* Offset: 0x20 I2C Slave Address Register3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* | | |Note: When software set 10'h000, the address can not be used.
* @var I2C_T::ADDRMSK0
* Offset: 0x24 I2C Slave Address Mask Register0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::ADDRMSK1
* Offset: 0x28 I2C Slave Address Mask Register1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::ADDRMSK2
* Offset: 0x2C I2C Slave Address Mask Register2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::ADDRMSK3
* Offset: 0x30 I2C Slave Address Mask Register3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::WKCTL
* Offset: 0x3C I2C Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |I2C Wake-up Enable Bit
* | | |0 = I2C wake-up function Disabled.
* | | |1 = I2C wake-up function Enabled.
* |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit
* | | |0 = I2C hold bus after wake-up.
* | | |1 = I2C don't hold bus after wake-up.
* | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received
* | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
* @var I2C_T::WKSTS
* Offset: 0x40 I2C Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKIF |I2C Wake-up Flag
* | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done
* | | |0 = The ACK bit cycle of address match frame isn't done.
* | | |1 = The ACK bit cycle of address match frame is done in power-down.
* | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit.
* |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame
* | | |0 = Write command be record on the address match wakeup frame.
* | | |1 = Read command be record on the address match wakeup frame.
* | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit.
* @var I2C_T::CTL1
* Offset: 0x44 I2C Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |PDMA Transmit Channel Available
* | | |0 = Transmit PDMA function disable.
* | | |1 = Transmit PDMA function enable.
* |[1] |RXPDMAEN |PDMA Receive Channel Available
* | | |0 = Receive PDMA function disable.
* | | |1 = Receive PDMA function enable.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the I2C request to PDMA.
* |[3] |OVRIEN |I2C over Run Interrupt Control Bit
* | | |Setting OVRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received buffer.
* |[4] |UDRIEN |I2C Under Run Interrupt Control Bit
* | | |Setting UDRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted buffer.
* |[5] |TWOBUFEN |Two-level BUFFER Enable Bit
* | | |0 = Two-level buffer Disabled.
* | | |1 = Two-level buffer Enabled.
* | | |Set to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus.
* |[8] |PDMASTR |PDMA Stretch Bit
* | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX)
* | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared
* | | |(only master TX)
* |[9] |ADDR10EN |Address 10-bit Function Enable
* | | |0 = Address match 10-bit function is disabled.
* | | |1 = Address match 10-bit function is enabled.
* |[10] |SWITCHEN |SCL And SDA Pin Switch Enable Bit
* | | |0 = I2C use original pin configuration.
* | | |1 = I2C switch SCL and SDA pin configuration.
* | | |Note: Original pin configuration table is shown in Basic Configuration chapter.
* @var I2C_T::STATUS1
* Offset: 0x48 I2C Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADMAT0 |I2C Address 0 Match Status Register
* | | |When address 0 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[1] |ADMAT1 |I2C Address 1 Match Status Register
* | | |When address 1 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[2] |ADMAT2 |I2C Address 2 Match Status Register
* | | |When address 2 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[3] |ADMAT3 |I2C Address 3 Match Status Register
* | | |When address 3 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[4] |FULL |TWO-LEVEL BUFFER FULL
* | | |This bit indicates two-level buffer TX or RX full or not when the TWOBUFEN = 1.
* | | |This bit is set when POINTER is equal to 2
* | | |Note: This bit is read only.
* |[5] |EMPTY |TWO-LEVEL BUFFER EMPTY
* | | |This bit indicates two-level buffer TX or RX empty or not when the TWOBUFEN = 1.
* | | |This bit is set when POINTER is equal to 0.
* | | |Note: This bit is read only.
* |[6] |OVR |I2C over Run Status Bit
* | | |This bit indicates the received two-level buffer TX or RX is over run when the TWOBUFEN = 1.
* | | |Note: This bit is read only.
* |[7] |UDR |I2C Under Run Status Bit
* | | |This bit indicates the transmitted two-level buffer TX or RX is under run when the TWOBUFEN = 1.
* | | |Note: This bit is read only.
* |[8] |ONBUSY |On Bus Busy
* | | |Indicates that a communication is in progress on the bus
* | | |It is set by hardware when a START condition is detected
* | | |It is cleared by hardware when a STOP condition is detected.
* | | |0 = The bus is IDLE (both SCLK and SDA High).
* | | |1 = The bus is busy.
* | | |Note:This bit is read only.
* @var I2C_T::TMCTL
* Offset: 0x4C I2C Timing Configure Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |STCTL |Setup Time Configure Control Register
* | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
* | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK.
* | | |Note: Setup time setting should not make SCL output less than three PCLKs.
* |[24:16] |HTCTL |Hold Time Configure Control Register
* | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
* | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK.
* @var I2C_T::BUSCTL
* Offset: 0x50 I2C Bus Management Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACKMEN |Acknowledge Control by Manual
* | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
* | | |0 = Slave byte control Disabled.
* | | |1 = Slave byte control Enabled
* | | |The 9th bit can response the ACK or NACK according the received data by user
* | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
* | | |Note: If the BMDEN=1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
* |[1] |PECEN |Packet Error Checking Calculation Enable Bit
* | | |0 = Packet Error Checking Calculation Disabled.
* | | |1 = Packet Error Checking Calculation Enabled.
* | | |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation.
* |[2] |BMDEN |Bus Management Device Default Address Enable Bit
* | | |0 = Device default address Disable
* | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed
* | | |1 = Device default address Enabled
* | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
* |[3] |BMHEN |Bus Management Host Enable Bit
* | | |0 = Host function Disabled.
* | | |1 = Host function Enabled.
* |[4] |ALERTEN |Bus Management Alert Enable Bit
* | | |Device Mode (BMHEN=0).
* | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
* | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
* | | |Host Mode (BMHEN=1).
* | | |0 = BM_ALERT pin not supported.
* | | |1 = BM_ALERT pin supported.
* |[5] |SCTLOSTS |Suspend/Control Data Output Status
* | | |0 = The output of SUSCON pin is low.
* | | |1 = The output of SUSCON pin is high.
* |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit
* | | |0 = The SUSCON pin in input.
* | | |1 = The output enable is active on the SUSCON pin.
* |[7] |BUSEN |BUS Enable Bit
* | | |0 = The system management function is Disabled.
* | | |1 = The system management function is Enable.
* | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
* |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception
* | | |0 = No PEC transfer.
* | | |1 = PEC transmission is requested.
* | | |Note: This bit has no effect in slave mode when ACKMEN=0.
* |[9] |TIDLE |Timer Check in Idle State
* | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle
* | | |This bit is used to define which condition is enabled.
* | | |0 = The BUSTOUT is used to calculate the clock low period in bus active.
* | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
* | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
* |[10] |PECCLR |PEC Clear at Repeat Start
* | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected
* | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
* | | |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled.
* | | |1 = The PEC calculation is cleared by "Repeat Start"" function is Enabled.
* |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt
* | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1.
* | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1.
* |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit
* | | |0 = Indicates the byte count done interrupt is Disabled.
* | | |1 = Indicates the byte count done interrupt is Enabled.
* | | |Note: This bit is used in PECEN=1.
* |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit
* | | |0 = Indicates the PEC transfer done interrupt is Disabled.
* | | |1 = Indicates the PEC transfer done interrupt is Enabled.
* | | |Note: This bit is used in PECEN=1.
* @var I2C_T::BUSTCTL
* Offset: 0x54 I2C Bus Management Timer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSTOEN |Bus Time Out Enable Bit
* | | |0 = Indicates the bus clock low time-out detection is Disabled.
* | | |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1)
* |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit
* | | |0 = Indicates the cumulative clock low time-out detection is Disabled.
* | | |1 = Indicates the cumulative clock low time-out detection is Enabled.
* | | |For Master, it calculates the period from START to ACK
* | | |For Slave, it calculates the period from START to STOP
* |[2] |BUSTOIEN |Time-out Interrupt Enable Bit
* | | |BUSY =1.
* | | |0 = Indicates the SCLK low time-out interrupt is Disabled.
* | | |1 = Indicates the SCLK low time-out interrupt is Enabled.
* | | |BUSY =0.
* | | |0 = Indicates the bus IDLE time-out interrupt is Disabled.
* | | |1 = Indicates the bus IDLE time-out interrupt is Enabled.
* |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit
* | | |0 = Indicates the clock time out interrupt is Disabled.
* | | |1 = Indicates the clock time out interrupt is Enabled.
* |[4] |TORSTEN |Time Out Reset Enable Bit
* | | |0 = Indicates the I2C state machine reset is Disable.
* | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)
* @var I2C_T::BUSSTS
* Offset: 0x58 I2C Bus Management Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Bus Busy
* | | |Indicates that a communication is in progress on the bus
* | | |It is set by hardware when a START condition is detected
* | | |It is cleared by hardware when a STOP condition is detected
* | | |0 = The bus is IDLE (both SCLK and SDA High).
* | | |1 = The bus is busy.
* |[1] |BCDONE |Byte Count Transmission/Receive Done
* | | |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set.
* | | |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set.
* | | |Note: Software can write 1 to clear this bit.
* |[2] |PECERR |PEC Error in Reception
* | | |0 = Indicates the PEC value equal the received PEC data packet.
* | | |1 = Indicates the PEC value doesn't match the receive PEC data packet.
* | | |Note: Software can write 1 to clear this bit.
* |[3] |ALERT |SMBus Alert Status
* | | |Device Mode (BMHEN =0).
* | | |0 = Indicates SMBALERT pin state is low.
* | | |1 = Indicates SMBALERT pin state is high.
* | | |Host Mode (BMHEN =1).
* | | |0 = No SMBALERT event.
* | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
* | | |Note:
* | | |1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system
* | | |2. Software can write 1 to clear this bit.
* |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status
* | | |0 = The input status of SUSCON pin is 0.
* | | |1 = The input status of SUSCON pin is 1.
* |[5] |BUSTO |Bus Time-out Status
* | | |0 = Indicates that there is no any time-out or external clock time-out.
* | | |1 = Indicates that a time-out or external clock time-out occurred.
* | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
* | | |Note: Software can write 1 to clear this bit.
* |[6] |CLKTO |Clock Low Cumulate Time-out Status
* | | |0 = Indicates that the cumulative clock low is no any time-out.
* | | |1 = Indicates that the cumulative clock low time-out occurred.
* | | |Note: Software can write 1 to clear this bit.
* |[7] |PECDONE |PEC Byte Transmission/Receive Done
* | | |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set.
* | | |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set.
* | | |Note: Software can write 1 to clear this bit.
* @var I2C_T::PKTSIZE
* Offset: 0x5C I2C Packet Error Checking Byte Number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |PLDSIZE |Transfer Byte Number
* | | |The transmission or receive byte number in one transaction when the PECEN is set
* | | |The maximum transaction or receive byte is 256 Bytes.
* | | |Notice: The byte number counting includes address, command code, and data frame.
* @var I2C_T::PKTCRC
* Offset: 0x60 I2C Packet Error Checking Byte Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PECCRC |Packet Error Checking Byte Value
* | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1
* | | |It is read only.
* @var I2C_T::BUSTOUT
* Offset: 0x64 I2C Bus Management Timer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |BUSTO |Bus Management Time-out Value
* | | |Indicate the bus time-out value in bus is IDLE or SCLK low.
* | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
* @var I2C_T::CLKTOUT
* Offset: 0x68 I2C Bus Management Clock Low Timer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CLKTO |Bus Clock Low Timer
* | | |The field is used to configure the cumulative clock extension time-out.
* | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.
*/
__IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */
__IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */
__IO uint32_t DAT; /*!< [0x0008] I2C Data Register */
__I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */
__IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */
__IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */
__IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */
__IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */
__IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */
__IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */
__IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */
__IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */
__IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */
__IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */
__IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */
__IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */
__IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */
__IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */
__IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */
__IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */
__I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */
__IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */
__IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */
} I2C_T;
/**
@addtogroup I2C_CONST I2C Bit Field Definition
Constant Definitions for I2C Controller
@{ */
#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL: AA Position */
#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL: AA Mask */
#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL: SI Position */
#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL: SI Mask */
#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL: STO Position */
#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL: STO Mask */
#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL: STA Position */
#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL: STA Mask */
#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL: I2CEN Position */
#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL: I2CEN Mask */
#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL: INTEN Position */
#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL: INTEN Mask */
#define I2C_CTL0_DPBITSEL_Pos (8) /*!< I2C_T::CTL: DPBITSEL Position */
#define I2C_CTL0_DPBITSEL_Msk (0x3ul << I2C_CTL0_DPBITSEL_Pos) /*!< I2C_T::CTL: DPBITSEL Mask */
#define I2C_CTL0_DPCINTEN_Pos (12) /*!< I2C_T::CTL: DPCINTEN Position */
#define I2C_CTL0_DPCINTEN_Msk (0x1ul << I2C_CTL0_DPCINTEN_Pos) /*!< I2C_T::CTL: DPCINTEN Mask */
#define I2C_CTL0_SRCINTEN_Pos (13) /*!< I2C_T::CTL: SRCINTEN Position */
#define I2C_CTL0_SRCINTEN_Msk (0x1ul << I2C_CTL0_SRCINTEN_Pos) /*!< I2C_T::CTL: SRCINTEN Mask */
#define I2C_CTL0_DPCIF_Pos (14) /*!< I2C_T::CTL: DPCIF Position */
#define I2C_CTL0_DPCIF_Msk (0x1ul << I2C_CTL0_DPCIF_Pos) /*!< I2C_T::CTL: DPCIF Mask */
#define I2C_CTL0_SARCIF_Pos (15) /*!< I2C_T::CTL: SARCIF Position */
#define I2C_CTL0_SARCIF_Msk (0x1ul << I2C_CTL0_SARCIF_Pos) /*!< I2C_T::CTL: SARCIF Mask */
#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */
#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */
#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */
#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */
#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */
#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */
#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */
#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS_STATUS0_Pos) /*!< I2C_T::STATUS: STATUS Mask */
#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */
#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */
#define I2C_CLKDIV_NFCNT_Pos (12) /*!< I2C_T::CLKDIV: NFCNT Position */
#define I2C_CLKDIV_NFCNT_Msk (0xful << I2C_CLKDIV_NFCNT_Pos) /*!< I2C_T::CLKDIV: NFCNT Mask */
#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */
#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */
#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */
#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */
#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */
#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */
#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */
#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */
#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */
#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */
#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */
#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */
#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */
#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */
#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */
#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */
#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */
#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */
#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */
#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */
#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */
#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */
#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */
#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */
#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */
#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */
#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */
#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */
#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */
#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */
#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */
#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */
#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */
#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */
#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */
#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */
#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */
#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */
#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */
#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */
#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */
#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */
#define I2C_CTL1_OVRIEN_Pos (3) /*!< I2C_T::CTL1: OVRIEN Position */
#define I2C_CTL1_OVRIEN_Msk (0x1ul << I2C_CTL1_OVRIEN_Pos) /*!< I2C_T::CTL1: OVRIEN Mask */
#define I2C_CTL1_UDRIEN_Pos (4) /*!< I2C_T::CTL1: UDRIEN Position */
#define I2C_CTL1_UDRIEN_Msk (0x1ul << I2C_CTL1_UDRIEN_Pos) /*!< I2C_T::CTL1: UDRIEN Mask */
#define I2C_CTL1_TWOBUFEN_Pos (5) /*!< I2C_T::CTL1: TWOBUFEN Position */
#define I2C_CTL1_TWOBUFEN_Msk (0x1ul << I2C_CTL1_TWOBUFEN_Pos) /*!< I2C_T::CTL1: TWOBUFEN Mask */
#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */
#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */
#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */
#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */
#define I2C_CTL1_SWITCHEN_Pos (10) /*!< I2C_T::CTL1: SWITCHEN Position */
#define I2C_CTL1_SWITCHEN_Msk (0x1ul << I2C_CTL1_SWITCHEN_Pos) /*!< I2C_T::CTL1: SWITCHEN Mask */
#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */
#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */
#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */
#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */
#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */
#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */
#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */
#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */
#define I2C_STATUS1_FULL_Pos (4) /*!< I2C_T::STATUS1: FULL Position */
#define I2C_STATUS1_FULL_Msk (0x1ul << I2C_STATUS1_FULL_Pos) /*!< I2C_T::STATUS1: FULL Mask */
#define I2C_STATUS1_EMPTY_Pos (5) /*!< I2C_T::STATUS1: EMPTY Position */
#define I2C_STATUS1_EMPTY_Msk (0x1ul << I2C_STATUS1_EMPTY_Pos) /*!< I2C_T::STATUS1: EMPTY Mask */
#define I2C_STATUS1_OVR_Pos (6) /*!< I2C_T::STATUS1: OVR Position */
#define I2C_STATUS1_OVR_Msk (0x1ul << I2C_STATUS1_OVR_Pos) /*!< I2C_T::STATUS1: OVR Mask */
#define I2C_STATUS1_UDR_Pos (7) /*!< I2C_T::STATUS1: UDR Position */
#define I2C_STATUS1_UDR_Msk (0x1ul << I2C_STATUS1_UDR_Pos) /*!< I2C_T::STATUS1: UDR Mask */
#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */
#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */
#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */
#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */
#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */
#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */
#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */
#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */
#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */
#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */
#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */
#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */
#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */
#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */
#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */
#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */
#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */
#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */
#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */
#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */
#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */
#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */
#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */
#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */
#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */
#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */
#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */
#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */
#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */
#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */
#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */
#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */
#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */
#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */
#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */
#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */
#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */
#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */
#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */
#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */
#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */
#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */
#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */
#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */
#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */
#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */
#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */
#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */
#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */
#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */
#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */
#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */
#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */
#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */
#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */
#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */
#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */
#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */
#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */
#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */
#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */
#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */
#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */
#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */
#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */
#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */
#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */
#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */
/**@}*/ /* I2C_CONST */
/**@}*/ /* end of I2C register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __I2C_REG_H__ */

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bsp/nuvoton/libraries/m460/Device/Nuvoton/m460/Include/i2s_reg.h Normal file
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/**************************************************************************//**
* @file i2s_reg.h
* @version V3.00
* @brief I2S register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __I2S_REG_H__
#define __I2S_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup I2S I2S Interface Controller(I2S)
Memory Mapped Structure for I2S Controller
@{ */
typedef struct
{
/**
* @var I2S_T::CTL0
* Offset: 0x00 I2S Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SEN |I2S Controller Enable Control
* | | |0 = I2S controller Disabled.
* | | |1 = I2S controller Enabled.
* |[1] |TXEN |Transmit Enable Control
* | | |0 = Data transmission Disabled.
* | | |1 = Data transmission Enabled.
* |[2] |RXEN |Receive Enable Control
* | | |0 = Data receiving Disabled.
* | | |1 = Data receiving Enabled.
* |[3] |MUTE |Transmit Mute Enable Control
* | | |0 = Transmit data is shifted from buffer.
* | | |1 = Send zero on transmit channel.
* |[5:4] |DATWIDTH |Data Width
* | | |This bit field is used to define the bit-width of data word in each audio channel
* | | |00 = The bit-width of data word is 8-bit.
* | | |01 = The bit-width of data word is 16-bit.
* | | |10 = The bit-width of data word is 24-bit.
* | | |11 = The bit-width of data word is 32-bit.
* |[6] |MONO |Monaural Data Control
* | | |0 = Data is stereo format.
* | | |1 = Data is monaural format.
* | | |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected.
* |[7] |ORDER |Stereo Data Order in FIFO
* | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte
* | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries.
* | | |0 = Even channel data at high byte in 8-bit/16-bit data width.
* | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries.
* | | |1 = Even channel data at low byte.
* | | | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries.
* |[8] |SLAVE |Slave Mode Enable Control
* | | |0 = Master mode.
* | | |1 = Slave mode.
* | | |Note: I2S can operate as master or slave
* | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip
* | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
* |[15] |MCLKEN |Master Clock Enable Control
* | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.
* | | |0 = Master clock Disabled.
* | | |1 = Master clock Enabled.
* |[18] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No Effect.
* | | |1 = Clear TX FIFO.
* | | |Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed.
* | | |Note2: This bit is clear by hardware automatically, read it return zero.
* |[19] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No Effect.
* | | |1 = Clear RX FIFO.
* | | |Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.
* | | |Note2: This bit is cleared by hardware automatically, read it return zero.
* |[20] |TXPDMAEN |Transmit PDMA Enable Control
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[21] |RXPDMAEN |Receive PDMA Enable Control
* | | |0 = Receiver PDMA function Disabled.
* | | |1 = Receiver PDMA function Enabled.
* |[23] |RXLCH |Receive Left Channel Enable Control
* | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1.
* | | |0 = Receives channel1 data in MONO mode.
* | | |1 = Receives channel0 data in MONO mode.
* |[26:24] |FORMAT |Data Format Selection
* | | |000 = I2S standard data format.
* | | |001 = I2S with MSB justified.
* | | |010 = I2S with LSB justified.
* | | |011 = Reserved.
* | | |100 = PCM standard data format.
* | | |101 = PCM with MSB justified.
* | | |110 = PCM with LSB justified.
* | | |111 = Reserved.
* |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection
* | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol
* | | |0 = One BCLK period.
* | | |1 = One channel period.
* | | |Note: This bit is only available in master mode
* |[29:28] |CHWIDTH |Channel Width
* | | |This bit fields are used to define the length of audio channel
* | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH.
* | | |00 = The bit-width of each audio channel is 8-bit.
* | | |01 = The bit-width of each audio channel is 16-bit.
* | | |10 = The bit-width of each audio channel is 24-bit.
* | | |11 = The bit-width of each audio channel is 32-bit.
* |[31:30] |TDMCHNUM |TDM Channel Number
* | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1).
* | | |00 = 2 channels in audio frame.
* | | |01 = 4 channels in audio frame.
* | | |10 = 6 channels in audio frame.
* | | |11 = 8 channels in audio frame.
* @var I2S_T::CLKDIV
* Offset: 0x04 I2S Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |MCLKDIV |Master Clock Divider
* | | |If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip
* | | |If MCLKDIV is set to 0, MCLK is the same as external clock input.
* | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1.
* | | |F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ).
* | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ).
* | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK
* |[16:8] |BCLKDIV |Bit Clock Divider
* | | |The I2S controller will generate bit clock in Master mode
* | | |Software can program these bit fields to generate sampling rate clock frequency.
* | | |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)).
* | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK
* @var I2S_T::IEN
* Offset: 0x08 I2S Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1.
* |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1
* |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1
* | | |If RXTHIEN bit is enabled, interrupt occur.
* |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1.
* |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1
* |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]).
* |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross
* | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross
* | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Control
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* @var I2S_T::STATUS0
* Offset: 0x0C I2S Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SINT |I2S Interrupt Flag (Read Only)
* | | |0 = No I2S interrupt.
* | | |1 = I2S interrupt.
* | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits.
* |[1] |I2SRXINT |I2S Receive Interrupt (Read Only)
* | | |0 = No receive interrupt.
* | | |1 = Receive interrupt.
* |[2] |I2STXINT |I2S Transmit Interrupt (Read Only)
* | | |0 = No transmit interrupt.
* | | |1 = Transmit interrupt.
* |[5:3] |DATACH |Transmission Data Channel (Read Only)
* | | |This bit fields are used to indicate which audio channel is current transmit data belong.
* | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode).
* | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode).
* | | |010 = channel2 (available while 4-channel TDM PCM mode).
* | | |011 = channel3 (available while 4-channel TDM PCM mode).
* | | |100 = channel4 (available while 6-channel TDM PCM mode).
* | | |101 = channel5 (available while 6-channel TDM PCM mode).
* | | |110 = channel6 (available while 8-channel TDM PCM mode).
* | | |111 = channel7 (available while 8-channel TDM PCM mode).
* |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag
* | | |0 = No underflow occur.
* | | |1 = Underflow occur.
* | | |Note1: When receive FIFO is empty, and software reads the receive FIFO again
* | | |This bit will be set to 1, and it indicates underflow situation occurs.
* | | |Note2: Write 1 to clear this bit to zero
* |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag
* | | |0 = No overflow occur.
* | | |1 = Overflow occur.
* | | |Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.
* | | |Note2: Write 1 to clear this bit to 0.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = Data word(s) in FIFO is not higher than threshold level.
* | | |1 = Data word(s) in FIFO is higher than threshold level.
* | | |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1
* | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register.
* |[11] |RXFULL |Receive FIFO Full (Read Only)
* | | |0 = Not full.
* | | |1 = Full.
* | | |Note: This bit reflects data words number in receive FIFO is 16.
* |[12] |RXEMPTY |Receive FIFO Empty (Read Only)
* | | |0 = Not empty.
* | | |1 = Empty.
* | | |Note: This bit reflects data words number in receive FIFO is zero
* |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag
* | | |0 = No underflow.
* | | |1 = Underflow.
* | | |Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.
* | | |Note2: Write 1 to clear this bit to 0.
* |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag
* | | |0 = No overflow.
* | | |1 = Overflow.
* | | |Note1: Write data to transmit FIFO when it is full and this bit set to 1
* | | |Note2: Write 1 to clear this bit to 0.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = Data word(s) in FIFO is higher than threshold level.
* | | |1 = Data word(s) in FIFO is equal or lower than threshold level.
* | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1
* | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register.
* |[19] |TXFULL |Transmit FIFO Full (Read Only)
* | | |This bit reflect data word number in transmit FIFO is 16
* | | |0 = Not full.
* | | |1 = Full.
* |[20] |TXEMPTY |Transmit FIFO Empty (Read Only)
* | | |This bit reflect data word number in transmit FIFO is zero
* | | |0 = Not empty.
* | | |1 = Empty.
* |[21] |TXBUSY |Transmit Busy (Read Only)
* | | |0 = Transmit shift buffer is empty.
* | | |1 = Transmit shift buffer is busy.
* | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out
* | | |And set to 1 when 1st data is load to shift buffer
* @var I2S_T::TXFIFO
* Offset: 0x10 I2S Transmit FIFO Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TXFIFO |Transmit FIFO Bits
* | | |I2S contains 16 words (16x32 bit) data buffer for data transmit
* | | |Write data to this register to prepare data for transmit
* | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]).
* @var I2S_T::RXFIFO
* Offset: 0x14 I2S Receive FIFO Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RXFIFO |Receive FIFO Bits
* | | |I2S contains 16 words (16x32 bit) data buffer for data receive
* | | |Read this register to get data in FIFO
* | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]).
* @var I2S_T::CTL1
* Offset: 0x20 I2S Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Control
* | | |0 = channel0 zero-cross detect Disabled.
* | | |1 = channel0 zero-cross detect Enabled.
* | | |Note1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* | | |Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.
* | | |Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute.
* |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Control
* | | |0 = channel1 zero-cross detect Disabled.
* | | |1 = channel1 zero-cross detect Enabled.
* | | |Note1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* | | |Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.
* | | |Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute.
* |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Control
* | | |0 = channel2 zero-cross detect Disabled.
* | | |1 = channel2 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.
* | | |Note3: If CH2ZCIF Flag is set to 1, the channel2 will be mute.
* |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Control
* | | |0 = channel3 zero-cross detect Disabled.
* | | |1 = channel3 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.
* | | |Note3: If CH3ZCIF Flag is set to 1, the channel3 will be mute.
* |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Control
* | | |0 = channel4 zero-cross detect Disabled.
* | | |1 = channel4 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.
* | | |Note3: If CH4ZCIF Flag is set to 1, the channel4 will be mute.
* |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Control
* | | |0 = channel5 zero-cross detect Disabled.
* | | |1 = channel5 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.
* | | |Note3: If CH5ZCIF Flag is set to 1, the channel5 will be mute.
* |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Control
* | | |0 = channel6 zero-cross detect Disabled.
* | | |1 = channel6 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.
* | | |Note3: If CH6ZCIF Flag is set to 1, the channel6 will be mute.
* |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Control
* | | |0 = channel7 zero-cross detect Disabled.
* | | |1 = channel7 zero-cross detect Enabled.
* | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.
* | | |Note3: If CH7ZCIF Flag is set to 1, the channel7 will be mute.
* |[11:8] |TXTH |Transmit FIFO Threshold Level
* | | |0000 = 0 data word in transmit FIFO.
* | | |0001 = 1 data word in transmit FIFO.
* | | |0010 = 2 data words in transmit FIFO.
* | | |...
* | | |1110 = 14 data words in transmit FIFO.
* | | |1111 = 15 data words in transmit FIFO.
* | | |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set.
* |[19:16] |RXTH |Receive FIFO Threshold Level
* | | |0000 = 1 data word in receive FIFO.
* | | |0001 = 2 data words in receive FIFO.
* | | |0010 = 3 data words in receive FIFO.
* | | |...
* | | |1110 = 15 data words in receive FIFO.
* | | |1111 = 16 data words in receive FIFO.
* | | |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set.
* |[24] |PBWIDTH |Peripheral Bus Data Width Selection
* | | |This bit is used to choice the available data width of APB bus
* | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode
* | | |0 = 32 bits data width.
* | | |1 = 16 bits data width.
* | | |Note1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available.
* | | |Note2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations.
* | | |Note3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations.
* |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus
* | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access
* | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries.
* | | |0 = Low 16-bit read/write access first.
* | | |1 = High 16-bit read/write access first.
* | | |Note: This bit is available while PBWIDTH = 1.
* @var I2S_T::STATUS1
* Offset: 0x24 I2S Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag
* | | |It indicates channel0 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel0.
* | | |1 = Channel0 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag
* | | |It indicates channel1 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel1.
* | | |1 = Channel1 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag
* | | |It indicates channel2 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel2.
* | | |1 = Channel2 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag
* | | |It indicates channel3 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel3.
* | | |1 = Channel3 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag
* | | |It indicates channel4 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel4.
* | | |1 = Channel4 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag
* | | |It indicates channel5 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel5.
* | | |1 = Channel5 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag
* | | |It indicates channel6 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel6.
* | | |1 = Channel6 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag
* | | |It indicates channel7 next sample data sign bit is changed or all data bits are zero.
* | | |0 = No zero-cross in channel7.
* | | |1 = Channel7 zero-cross is detected.
* | | |Note1: Write 1 to clear this bit to 0.
* | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[12:8] |TXCNT |Transmit FIFO Level (Read Only)
* | | |These bits indicate the number of available entries in transmit FIFO
* | | |00000 = No data.
* | | |00001 = 1 word in transmit FIFO.
* | | |00010 = 2 words in transmit FIFO.
* | | |...
* | | |01110 = 14 words in transmit FIFO.
* | | |01111 = 15 words in transmit FIFO.
* | | |10000 = 16 words in transmit FIFO.
* | | |Others are reserved.
* |[20:16] |RXCNT |Receive FIFO Level (Read Only)
* | | |These bits indicate the number of available entries in receive FIFO
* | | |00000 = No data.
* | | |00001 = 1 word in receive FIFO.
* | | |00010 = 2 words in receive FIFO.
* | | |...
* | | |01110 = 14 words in receive FIFO.
* | | |01111 = 15 words in receive FIFO.
* | | |10000 = 16 words in receive FIFO.
* | | |Others are reserved.
*/
__IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */
__IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */
__IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */
__IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */
__O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */
__I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */
__IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */
} I2S_T;
/**
@addtogroup I2S_CONST I2S Bit Field Definition
Constant Definitions for I2S Controller
@{ */
#define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */
#define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */
#define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */
#define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */
#define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */
#define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */
#define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */
#define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */
#define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */
#define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */
#define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */
#define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */
#define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */
#define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */
#define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */
#define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */
#define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */
#define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */
#define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */
#define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */
#define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */
#define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */
#define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */
#define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */
#define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */
#define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */
#define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */
#define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */
#define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */
#define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */
#define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */
#define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */
#define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */
#define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */
#define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */
#define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */
#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */
#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */
#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */
#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */
#define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */
#define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */
#define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */
#define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */
#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */
#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */
#define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */
#define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */
#define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */
#define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */
#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */
#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */
#define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */
#define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */
#define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */
#define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */
#define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */
#define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */
#define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */
#define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */
#define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */
#define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */
#define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */
#define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */
#define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */
#define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */
#define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */
#define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */
#define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */
#define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */
#define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */
#define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */
#define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */
#define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */
#define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */
#define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */
#define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */
#define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */
#define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */
#define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */
#define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */
#define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */
#define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */
#define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */
#define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */
#define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */
#define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */
#define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */
#define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */
#define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */
#define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */
#define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */
#define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */
#define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */
#define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */
#define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */
#define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */
#define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */
#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */
#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */
#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */
#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */
#define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */
#define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */
#define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */
#define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */
#define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */
#define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */
#define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */
#define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */
#define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */
#define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */
#define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */
#define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */
#define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */
#define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */
#define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */
#define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */
#define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */
#define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */
#define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */
#define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */
#define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */
#define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */
#define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */
#define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */
#define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */
#define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */
#define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */
#define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */
#define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */
#define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */
#define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */
#define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */
#define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */
#define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */
#define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */
#define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */
#define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */
#define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */
#define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */
#define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */
#define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */
#define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */
#define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */
#define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */
/**@}*/ /* I2S_CONST */
/**@}*/ /* end of I2S register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __I2S_REG_H__ */

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/**************************************************************************//**
* @file keystore_reg.h
* @version V1.00
* @brief Key store register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __KEYSTORE_REG_H__
#define __KEYSTORE_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Key Store -------------------------*/
/**
@addtogroup KS Key Store(KS)
Memory Mapped Structure for KS Controller
@{ */
typedef struct
{
/**
* @var KS_T::CTL
* Offset: 0x00 Key Store Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |START |Key Store Start Control Bit
* | | |0 = No operation.
* | | |1 = Start the operation.
* |[3:1] |OPMODE |Key Store Operation Mode
* | | |000 = Read operation.
* | | |001 = Create operation.
* | | |010 = Erase one key operation (only for key is in SRAM and OTP).
* | | |011 = Erase all keys operation (only for SRAM and Flash).
* | | |100 = Revoke key operation.
* | | |101 = Data Remanence prevention operation (only for SRAM).
* | | |111 = Lock operation (only for OTP).
* | | |Others = reserved.
* |[7] |CONT |Read/Write Key Continue Bit
* | | |0 = Read/Write key operation is not continuous to previous operation.
* | | |1 = Read/Write key operation is continuous to previous operation.
* |[8] |INIT |Key Store Initialization
* | | |User should to check BUSY(KS_STS[2]) is 0, and then write 1 to this bit and START(KS_CTL[0[), the Key Store will start to be initializationed.
* | | |After Key Store is initialized, INIT will be cleared.
* | | |Note: Before executing INIT, user must to checks KS(SYS_SRAMPC1) is 00.
* |[15] |IEN |Key Store Interrupt Enable Bit
* | | |0 = Key Store Interrupt Disabled.
* | | |1 = Key Store Interrupt Enabled.
* @var KS_T::METADATA
* Offset: 0x04 Key Store Metadata Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SEC |Secure Key Selection Bit
* | | |0 = Set key as the non-secure key.
* | | |1 = Set key as the secure key.
* |[1] |PRIV |Privilege Key Selection Bit
* | | |0 = Set key as the non-privilege key.
* | | |1 = Set key as the privilege key.
* |[2] |READABLE |Key Readable Control Bit
* | | |0 = key is un-readable.
* | | |1 = key is readable.
* |[4] |BS |Booting State Selection Bit
* | | |0 = Set key used at all state.
* | | |1 = Set key used at boot loader state 1 (BL1 state).
* |[12:8] |SIZE |Key Size Selection Bits
* | | |00000 = 128 bits.
* | | |00001 = 163 bits.
* | | |00010 = 192 bits.
* | | |00011 = 224 bits.
* | | |00100 = 233 bits.
* | | |00101 = 255 bits.
* | | |00110 = 256 bits.
* | | |00111 = 283 bits.
* | | |01000 = 384 bits.
* | | |01001 = 409 bits.
* | | |01010 = 512 bits.
* | | |01011 = 521 bits.
* | | |01100 = 571 bits.
* | | |10000 = 1024 bits.
* | | |10001 = 1536 bits.
* | | |10010 = 2048 bits.
* | | |10011 = 3072 bits.
* | | |10100 = 4096 bits.
* | | |Others = reserved.
* |[18:16] |OWNER |Key Owner Selection Bits
* | | |000 = AES
* | | |001 = HMAC
* | | |010 = RSA exponent blind key for SCAP(CRYPTO_RSA_CTL[8]) = 1 and CRT(CRYPTO_RSA_CTL[2]) = 0
* | | |011 = RSA middle data, p, q and private key.
* | | |100 = ECC.
* | | |101 = CPU.
* | | |Others = reserved.
* |[25:20] |NUMBER |Key Number
* | | |Before read or erase one key operation starts, user should write the key number to be operated
* | | |When create operation is finished, user can read these bits to get its key number.
* |[31:30] |DST |Key Location Selection Bits
* | | |00 = Key is in SRAM.
* | | |01 = Key is in Flash.
* | | |10 = Key is in OTP.
* | | |Others = reserved.
* @var KS_T::STS
* Offset: 0x08 Key Store Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IF |Key Store Finish Interrupt Flag
* | | |This bit is cleared by writing 1 and it has no effect by writing 0.
* | | |0 = No Key Store interrupt.
* | | |1 = Key Store operation done interrupt.
* |[1] |EIF |Key Store Error Flag
* | | |This bit is cleared by writing 1 and it has no effect by writing 0.
* | | |0 = No Key Store error.
* | | |1 = Key Store error interrupt.
* |[2] |BUSY |Key Store Busy Flag (read only)
* | | |0 = Key Store is idle or finished.
* | | |1 = Key Store is busy.
* |[3] |SRAMFULL |Key Storage at SRAM Full Status Bit (read only)
* | | |0 = Key Storage at SRAM is not full.
* | | |1 = Key Storage at SRAM is full.
* |[4] |FLASHFULL |Key Storage at Flash Full Status Bit (read only)
* | | |0 = Key Storage at Flash is not full.
* | | |1 = Key Storage at Flash is full.
* |[7] |INITDONE |Key Store Initialization Done Status (read only)
* | | |0 = Key Store is un-initialized.
* | | |1 = Key Store is initialized.
* |[8] |RAMINV |Key Store SRAM Invert Status (read only)
* | | |0 = Key Store key in SRAM is normal.
* | | |1 = Key Store key in SRAM is inverted.
* @var KS_T::REMAIN
* Offset: 0x0C Key Store Remaining Space Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[12:0] |RRMNG |Key Store SRAM Remaining Space
* | | |The RRMNG shows the remaining byte count space for SRAM.
* |[28:16] |FRMNG |Key Store Flash Remaining Space
* | | |The FRMNG shows the remaining byte count space for Flash.
* @var KS_T::KEY0
* Offset: 0x20 Key Store Entry Key Word 0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data
* | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::KEY1
* Offset: 0x24 Key Store Entry Key Word 1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data
* | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::KEY2
* Offset: 0x28 Key Store Entry Key Word 2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data
* | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::KEY3
* Offset: 0x2C Key Store Entry Key Word 3 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data
* | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::KEY4
* Offset: 0x30 Key Store Entry Key Word 4 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data
* | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::KEY5
* Offset: 0x34 Key Store Entry Key Word 5 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data
* | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::KEY6
* Offset: 0x38 Key Store Entry Key Word 6 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data
* | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::KEY7
* Offset: 0x3C Key Store Entry Key Word 7 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data
* | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::OTPSTS
* Offset: 0x40 Key Store OTP Keys Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |KEY0 |OTP Key 0 Used Status
* | | |0 = OTP key 0 is unused.
* | | |1 = OTP key 0 is used.
* | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
* |[1] |KEY1 |OTP Key 1 Used Status
* | | |0 = OTP key 1 is unused.
* | | |1 = OTP key 1 is used.
* | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
* |[2] |KEY2 |OTP Key 2 Used Status
* | | |0 = OTP key 2 is unused.
* | | |1 = OTP key 2 is used.
* | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
* |[3] |KEY3 |OTP Key 3 Used Status
* | | |0 = OTP key 3 is unused.
* | | |1 = OTP key 3 is used.
* | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
* |[4] |KEY4 |OTP Key 4 Used Status
* | | |0 = OTP key 4 is unused.
* | | |1 = OTP key 4 is used.
* | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, existing key will be revoked after initialization.
* |[5] |KEY5 |OTP Key 5 Used Status
* | | |0 = OTP key 5 is unused.
* | | |1 = OTP key 5 is used.
* | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
* |[6] |KEY6 |OTP Key 6 Used Status
* | | |0 = OTP key 6 is unused.
* | | |1 = OTP key 6 is used.
* | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
* |[7] |KEY7 |OTP Key 7 Used Status
* | | |0 = OTP key 7 is unused.
* | | |1 = OTP key 7 is used.
* | | |Note: If chip is inchanged to RMA stage, this bit will set to 1 and key is revoked after initialization if key is existedthe existing key will be revoked after initialization.
* @var KS_T::REMKCNT
* Offset: 0x44 Key Store Remaining Key Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |RRMKCNT |Key Store SRAM Remaining Key Count
* | | |The RRMKCNT shows the remaining key count for SRAM.
* |[21:16] |FRMKCNT |Key Store Flash Remaining Key Count
* | | |The FRMKCNT shows the remaining key count for Flash.
* @var KS_T::VERSION
* Offset: 0xFFC Key Store RTL Design Version Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |MINOR |RTL Design Minor Version Number
* | | |Minor version number is dependent on moduleu2019s ECO version control.
* | | |0x0000 (Current Minor Version Number)
* |[23:16] |SUB |RTL Design Sub Version Number
* | | |Sub version number is correlated to moduleu2019s key feature.
* | | |0x01 (Current Sub Version Number)
* |[31:24] |MAJOR |RTL Design Major Version Number
* | | |Major version number is correlated to Product Line.
* | | |0x021 (Current Major Version Number)
*/
__IO uint32_t CTL; /*!< [0x0000] Key Store Control Register */
__IO uint32_t METADATA; /*!< [0x0004] Key Store Metadata Register */
__IO uint32_t STS; /*!< [0x0008] Key Store Status Register */
__I uint32_t REMAIN; /*!< [0x000c] Key Store Remaining Space Register */
__I uint32_t RESERVE0[4];
__IO uint32_t KEY[8]; /*!< [0x0020-0x003c] Key Store Entry Key Word 0 Register */
__I uint32_t OTPSTS; /*!< [0x0040] Key Store OTP Keys Status Register */
__I uint32_t REMKCNT; /*!< [0x0044] Key Store Remaining Key Count Register */
__I uint32_t RESERVE1[1005];
__I uint32_t VERSION; /*!< [0x0ffc] Key Store RTL Design Version Register */
} KS_T;
/**
@addtogroup KS_CONST KS Bit Field Definition
Constant Definitions for KS Controller
@{ */
#define KS_CTL_START_Pos (0) /*!< KS_T::CTL: START Position */
#define KS_CTL_START_Msk (0x1ul << KS_CTL_START_Pos) /*!< KS_T::CTL: START Mask */
#define KS_CTL_OPMODE_Pos (1) /*!< KS_T::CTL: OPMODE Position */
#define KS_CTL_OPMODE_Msk (0x7ul << KS_CTL_OPMODE_Pos) /*!< KS_T::CTL: OPMODE Mask */
#define KS_CTL_CONT_Pos (7) /*!< KS_T::CTL: CONT Position */
#define KS_CTL_CONT_Msk (0x1ul << KS_CTL_CONT_Pos) /*!< KS_T::CTL: CONT Mask */
#define KS_CTL_INIT_Pos (8) /*!< KS_T::CTL: INIT Position */
#define KS_CTL_INIT_Msk (0x1ul << KS_CTL_INIT_Pos) /*!< KS_T::CTL: INIT Mask */
#define KS_CTL_IEN_Pos (15) /*!< KS_T::CTL: IEN Position */
#define KS_CTL_IEN_Msk (0x1ul << KS_CTL_IEN_Pos) /*!< KS_T::CTL: IEN Mask */
#define KS_METADATA_SEC_Pos (0) /*!< KS_T::METADATA: SEC Position */
#define KS_METADATA_SEC_Msk (0x1ul << KS_METADATA_SEC_Pos) /*!< KS_T::METADATA: SEC Mask */
#define KS_METADATA_PRIV_Pos (1) /*!< KS_T::METADATA: PRIV Position */
#define KS_METADATA_PRIV_Msk (0x1ul << KS_METADATA_PRIV_Pos) /*!< KS_T::METADATA: PRIV Mask */
#define KS_METADATA_READABLE_Pos (2) /*!< KS_T::METADATA: READABLE Position */
#define KS_METADATA_READABLE_Msk (0x1ul << KS_METADATA_READABLE_Pos) /*!< KS_T::METADATA: READABLE Mask */
#define KS_METADATA_BS_Pos (4) /*!< KS_T::METADATA: BS Position */
#define KS_METADATA_BS_Msk (0x1ul << KS_METADATA_BS_Pos) /*!< KS_T::METADATA: BS Mask */
#define KS_METADATA_SIZE_Pos (8) /*!< KS_T::METADATA: SIZE Position */
#define KS_METADATA_SIZE_Msk (0x1ful << KS_METADATA_SIZE_Pos) /*!< KS_T::METADATA: SIZE Mask */
#define KS_METADATA_OWNER_Pos (16) /*!< KS_T::METADATA: OWNER Position */
#define KS_METADATA_OWNER_Msk (0x7ul << KS_METADATA_OWNER_Pos) /*!< KS_T::METADATA: OWNER Mask */
#define KS_METADATA_NUMBER_Pos (20) /*!< KS_T::METADATA: NUMBER Position */
#define KS_METADATA_NUMBER_Msk (0x3ful << KS_METADATA_NUMBER_Pos) /*!< KS_T::METADATA: NUMBER Mask */
#define KS_METADATA_DST_Pos (30) /*!< KS_T::METADATA: DST Position */
#define KS_METADATA_DST_Msk (0x3ul << KS_METADATA_DST_Pos) /*!< KS_T::METADATA: DST Mask */
#define KS_STS_IF_Pos (0) /*!< KS_T::STS: IF Position */
#define KS_STS_IF_Msk (0x1ul << KS_STS_IF_Pos) /*!< KS_T::STS: IF Mask */
#define KS_STS_EIF_Pos (1) /*!< KS_T::STS: EIF Position */
#define KS_STS_EIF_Msk (0x1ul << KS_STS_EIF_Pos) /*!< KS_T::STS: EIF Mask */
#define KS_STS_BUSY_Pos (2) /*!< KS_T::STS: BUSY Position */
#define KS_STS_BUSY_Msk (0x1ul << KS_STS_BUSY_Pos) /*!< KS_T::STS: BUSY Mask */
#define KS_STS_SRAMFULL_Pos (3) /*!< KS_T::STS: SRAMFULL Position */
#define KS_STS_SRAMFULL_Msk (0x1ul << KS_STS_SRAMFULL_Pos) /*!< KS_T::STS: SRAMFULL Mask */
#define KS_STS_FLASHFULL_Pos (4) /*!< KS_T::STS: FLASHFULL Position */
#define KS_STS_FLASHFULL_Msk (0x1ul << KS_STS_FLASHFULL_Pos) /*!< KS_T::STS: FLASHFULL Mask */
#define KS_STS_INITDONE_Pos (7) /*!< KS_T::STS: INITDONE Position */
#define KS_STS_INITDONE_Msk (0x1ul << KS_STS_INITDONE_Pos) /*!< KS_T::STS: INITDONE Mask */
#define KS_STS_RAMINV_Pos (8) /*!< KS_T::STS: RAMINV Position */
#define KS_STS_RAMINV_Msk (0x1ul << KS_STS_RAMINV_Pos) /*!< KS_T::STS: RAMINV Mask */
#define KS_STS_KRVKF_Pos (9) /*!< KS_T::STS: KRVKF Position */
#define KS_STS_KRVKF_Msk (0x1ul << KS_STS_KRVKF_Pos) /*!< KS_T::STS: KRVKF Mask */
#define KS_REMAIN_RRMNG_Pos (0) /*!< KS_T::REMAIN: RRMNG Position */
#define KS_REMAIN_RRMNG_Msk (0x1ffful << KS_REMAIN_RRMNG_Pos) /*!< KS_T::REMAIN: RRMNG Mask */
#define KS_REMAIN_FRMNG_Pos (16) /*!< KS_T::REMAIN: FRMNG Position */
#define KS_REMAIN_FRMNG_Msk (0x1ffful << KS_REMAIN_FRMNG_Pos) /*!< KS_T::REMAIN: FRMNG Mask */
#define KS_KEY_KEY_Pos (0) /*!< KS_T::KEY: KEY Position */
#define KS_KEY_KEY_Msk (0xfffffffful << KS_KEY0_KEY_Pos) /*!< KS_T::KEY: KEY Mask */
#define KS_OTPSTS_KEY0_Pos (0) /*!< KS_T::OTPSTS: KEY0 Position */
#define KS_OTPSTS_KEY0_Msk (0x1ul << KS_OTPSTS_KEY0_Pos) /*!< KS_T::OTPSTS: KEY0 Mask */
#define KS_OTPSTS_KEY1_Pos (1) /*!< KS_T::OTPSTS: KEY1 Position */
#define KS_OTPSTS_KEY1_Msk (0x1ul << KS_OTPSTS_KEY1_Pos) /*!< KS_T::OTPSTS: KEY1 Mask */
#define KS_OTPSTS_KEY2_Pos (2) /*!< KS_T::OTPSTS: KEY2 Position */
#define KS_OTPSTS_KEY2_Msk (0x1ul << KS_OTPSTS_KEY2_Pos) /*!< KS_T::OTPSTS: KEY2 Mask */
#define KS_OTPSTS_KEY3_Pos (3) /*!< KS_T::OTPSTS: KEY3 Position */
#define KS_OTPSTS_KEY3_Msk (0x1ul << KS_OTPSTS_KEY3_Pos) /*!< KS_T::OTPSTS: KEY3 Mask */
#define KS_OTPSTS_KEY4_Pos (4) /*!< KS_T::OTPSTS: KEY4 Position */
#define KS_OTPSTS_KEY4_Msk (0x1ul << KS_OTPSTS_KEY4_Pos) /*!< KS_T::OTPSTS: KEY4 Mask */
#define KS_OTPSTS_KEY5_Pos (5) /*!< KS_T::OTPSTS: KEY5 Position */
#define KS_OTPSTS_KEY5_Msk (0x1ul << KS_OTPSTS_KEY5_Pos) /*!< KS_T::OTPSTS: KEY5 Mask */
#define KS_OTPSTS_KEY6_Pos (6) /*!< KS_T::OTPSTS: KEY6 Position */
#define KS_OTPSTS_KEY6_Msk (0x1ul << KS_OTPSTS_KEY6_Pos) /*!< KS_T::OTPSTS: KEY6 Mask */
#define KS_OTPSTS_KEY7_Pos (7) /*!< KS_T::OTPSTS: KEY7 Position */
#define KS_OTPSTS_KEY7_Msk (0x1ul << KS_OTPSTS_KEY7_Pos) /*!< KS_T::OTPSTS: KEY7 Mask */
#define KS_REMKCNT_RRMKCNT_Pos (0) /*!< KS_T::REMKCNT: RRMKCNT Position */
#define KS_REMKCNT_RRMKCNT_Msk (0x3ful << KS_REMKCNT_RRMKCNT_Pos) /*!< KS_T::REMKCNT: RRMKCNT Mask */
#define KS_REMKCNT_FRMKCNT_Pos (16) /*!< KS_T::REMKCNT: FRMKCNT Position */
#define KS_REMKCNT_FRMKCNT_Msk (0x3ful << KS_REMKCNT_FRMKCNT_Pos) /*!< KS_T::REMKCNT: FRMKCNT Mask */
#define KS_VERSION_MINOR_Pos (0) /*!< KS_T::VERSION: MINOR Position */
#define KS_VERSION_MINOR_Msk (0xfffful << KS_VERSION_MINOR_Pos) /*!< KS_T::VERSION: MINOR Mask */
#define KS_VERSION_SUB_Pos (16) /*!< KS_T::VERSION: SUB Position */
#define KS_VERSION_SUB_Msk (0xfful << KS_VERSION_SUB_Pos) /*!< KS_T::VERSION: SUB Mask */
#define KS_VERSION_MAJOR_Pos (24) /*!< KS_T::VERSION: MAJOR Position */
#define KS_VERSION_MAJOR_Msk (0xfful << KS_VERSION_MAJOR_Pos) /*!< KS_T::VERSION: MAJOR Mask */
/**@}*/ /* KS_CONST */
/**@}*/ /* end of KS register group */
/**@}*/ /* end of REGISTER group */
#endif /* __KEYSTORE_REG_H__ */

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/**************************************************************************//**
* @file clk_reg.h
* @version V1.00
* @brief CLK register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __KEYPAD_REG_H__
#define __KEYPAD_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Keypad Control Interface -------------------------*/
/**
@addtogroup KPI Keypad Control Interface (KPI)
Memory Mapped Structure for KPI Controller
@{ */
typedef struct
{
/**
* @var KPI_T::CTL
* Offset: 0x00 Keypad Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |KPEN |Keypad Scan Enable Bit
* | | |Setting this bit high enables the key scan function.
* | | |0 = Keypad scan Disabled.
* | | |1 = Keypad scan Enabled.
* |[1] |KPIEN |Key Press Key Interrupt Enable Bit
* | | |The keypad controller will generate an interrupt when the controller detects any effective key press.
* | | |0 = Keypad press interrupt Disabled.
* | | |1 = Keypad press interrupt Enabled.
* | | |Note: The bit will be reset when KPI reset occurs.
* |[2] |KRIEN |Key Release Key Interrupt Enable Bit
* | | |The keypad controller will generate an interrupt when the controller detects keypad status changes from press to release.
* | | |0 = Keypad release interrupt Disabled.
* | | |1 = Keypad release interrupt Enabled.
* | | |Note: The bit will be reset when KPI reset occurs.
* |[3] |KIEN |Key Interrupt Enable Bit
* | | |0 = Keypad interrupt Disabled.
* | | |1 = Keypad interrupt Enabled.
* | | |Note: The bit will be reset when KPI reset occurs.
* |[5:4] |DBCT |De-bounce Cycle Time
* | | |For keypad debounce, keypad will generate an interrupt when key press, key release or three key reset continued n * key array scan time.
* | | |00 = n=1.
* | | |01 = n=2.
* | | |10 = n=3.
* | | |11 = n=4.
* | | |Note: It would need more time to indicate key press and release event when users selected more debounce cycle time.
* |[15:8] |PSC |Row Scan Cycle Pre-scale Value
* | | |This value is used to pre-scale row scan cycle.
* | | |The pre-scale counter is clocked by the divided crystal clock, xCLOCK.
* | | |The divided number is from 1 to 256.
* | | |E.g.If the crystal clock is 1Mhz then the xCLOCK period is 1us.
* | | |If the keypad matric is 3x3 then
* | | |Each row scan time = xCLOCK x PRESCALE PSC x PrescaleDividerPSCDIV.
* | | |Key array scan time = Each row scan time x ROWS.
* | | |Example scan time for PRESCALE = 0x40, and PrescaleDividerPSCDIV = 0x1F.
* | | |Each row scan time = 1us x 65 x 32 = 2.08ms.
* | | |Scan time = 2.08 x 3 = 6.24ms.
* | | |Note:
* | | |When PRESCALEPSC is determined, De-bounce sampling cycle should not exceed the half of (PRESCALEPSC x PrescaleDividerPSCDIV),
* | | |in the above example, and if scan row delay cycle is 4 xclock
* | | |The maximum DBCLKSEL should be 10244*256 xCLOCK, bouncing time is 1ms.
* |[19:16] |DBCLKSEL |Scan in De-bounce Sampling Cycle Selection
* | | |0000 = Reserved.
* | | |0001 = Reserved.
* | | |0010 = Reserved.
* | | |0011 = Sample interrupt input once per 8 clocks.
* | | |0100 = Sample interrupt input once per 16 clocks.
* | | |0101 = Sample interrupt input once per 32 clocks.
* | | |0110 = Sample interrupt input once per 64 clocks.
* | | |0111 = Sample interrupt input once per 128 clocks.
* | | |1000 = Sample interrupt input once per 256 clocks.
* | | |1001 = Sample interrupt input once per 512 clocks.
* | | |1010 = Sample interrupt input once per 1024 clocks.
* | | |1011 = Sample interrupt input once per 2048 clocks.
* | | |1100 = Sample interrupt input once per 4096 clocks.
* | | |1101 = Sample interrupt input once per 8192 clocks.
* | | |1110 = reserved.
* | | |1111 = reserved.
* | | |Note:
* | | |scan row delay cycle < debounce sampling cycle.
* | | |row scan time > scan row delay cycle + (2 * debounce sampling cycle) + 1 xclock cycle(change row) + 2 xclock cycle(cross clock domain).
* | | |row scan time = xCLOCK x PRESCALEPSC x PrescaleDividerPSCDIVprescale * 32 (xclock).
* | | |xclock = 1 MHz ~32 kHz.
* | | |bouncing time last for 1ms
* | | |For example, if xclock = 1 MHz,.
* | | |debounce sampling cycle choose 1024 xclock,
* | | |and scan row delay cycle choose 8 xclock,
* | | |row scan time should choose larger than (8+2048+3) xclock,
* | | |suppose PrescaleDividerPSCDIV = 0x1F, then prescale = 65 (20562059/32 = 64.2535).
* |[23:22] |ROWDLY |Scan Row Delay
* | | |Setting delay cycle when row change, for avoid KPI from detecting wrong key..
* | | |00 = 4 KPI engine clock cycle.
* | | |01 = 8 KPI engine clock cycle.
* | | |10 = 16 KPI engine clock cycle.
* | | |11 = 32 KPI engine clock cycle.
* | | |Note:
* | | |scan row delay cycle < debounce sampling cycle.
* | | |row scan time > scan row delay cycle + (2 * debounce sampling cycle) + 1 xclock cycle(change row) + 2 xclock cycle(cross clock domain).
* |[26:24] |KCOL |Keypad Matrix COL Number
* | | |The keypad matrix is set by ROW x COL. The COL number can be set 1 to 8.
* | | |000 = 1.
* | | |001 = 2.
* | | |010 = 3.
* | | |011 = 4.
* | | |100 = 5.
* | | |101 = 6.
* | | |110 = 7.
* | | |111 = 8.
* |[30:28] |KROW |Keypad Matrix ROW Number
* | | |The keypad matrix is set by ROW x COL. The ROW number can be set 2 to 6.
* | | |000 = reserved.
* | | |001 = 2.
* | | |010 = 3.
* | | |011 = 4.
* | | |100 = 5.
* | | |101 = 6.
* | | |110 = Reserved.
* | | |111 = Reserved.
* @var KPI_T::STATUS
* Offset: 0x08 Keypad Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TKRIF |3Three-keys Reset Interrupt Flag
* | | |This bit will be set after 3Three-keys reset occurs.
* | | |When READ:
* | | |0 = No reset.
* | | |1 = 3Three -keys reset interrupt occurred.
* | | |When WRITE:
* | | |0 = No operation.
* | | |1 = Clear interrupt flag.
* |[2] |KIF |Key Interrupt Flag
* | | |This bit indicates the key scan interrupt is active when any key press or, key release or three key reset or wake up.
* | | |When READ:
* | | |0 = No reset.
* | | |1 = Key press/Key release/3Three-key reset/wakeup interrupt occurred.
* | | |To clear KIF, software must clear KPIF, KRIF and TKRIF
* | | |(u9019u6BB5WSu81EAu5DF1u731Cu7684uFF0Cu5C0Du55CE?)
* |[3] |KRIF |Release Key Release Interrupt Flag
* | | |This bit indicates that some keys (one or multiple key) have been released.
* | | |When READ:
* | | |0 = No key release.
* | | |1 = At least one key release.
* | | |Note: To clear KRKEYINTIF, software must clear each releasing event flag that are shown on u201Ckey releasing eventu201D
* | | |KPI_KRF0/1 registers.
* | | |C code example:
* | | |DWORD RKE0, RKE1
* | | |PKE0 = reg_read(KPIKRE0); PKE1 = reg_read(KPIKRE1);.
* | | |Reg_write(KPIKRE0, RKE0); Reg_write(KPIKRE1, RKE1)
* |[4] |KPIF |Key Press Key Interrupt Flag
* | | |This bit indicates that some keys (one or multiple key) have been pressed.
* | | |When READ:
* | | |0 = No key press.
* | | |1 = At least one key press.
* | | |Note: To clear KPIFPKEYINT, software must clear each pressing event flag that are shown on u201CKPIKPE1KPI_KPF0/1, KPIKPE0u201D
* | | |registers.
* | | |C code example:
* | | |DWORD PKE0, PKE1
* | | |PKE0 = reg_read(KPIKPE0); PKE1 = reg_read(KPIKPE1);.
* | | |Reg_write(KPIKPE0, PKE0); Reg_write(KPIKPE1, PKE1)
* @var KPI_T::KST0
* Offset: 0x10 Keypad State Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KSTmn |Key State
* | | |KESTm,n: m is row number, n is column number.
* | | |0 = Key m,n is pressing.
* | | |1 = Key m,n is releasing.
* @var KPI_T::KST1
* Offset: 0x14 Keypad State Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |KESTmn |Key State
* | | |KESTm,n: m is row number, n is column number.
* | | |0 = Key m,n is pressing.
* | | |1 = Key m,n is releasing.
* @var KPI_T::KPF0
* Offset: 0x18 Lower 32 Key Press Flag Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KPFmn |Lower 32 Key Press Event Change IndicatorFlag
* | | |m is row number, n is column number.
* | | |KPE mn[X] = 1, m=row, n=column:.
* | | |0 = No key event.
* | | |1 = Corresponding key has a high to low event change.
* | | |Note:
* | | |Hardware will set this bit, and software should clear this bit by writing 1.
* | | |Software can clear PKEYINT KPIF (KPI_STATUS[4]) by writing 1 bit by bit to this register.
* @var KPI_T::KPF1
* Offset: 0x1C Upper 32 Key Press Flag Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |KPEmn |Upper 32 Key Press Event Change IndicatorFlag
* | | |KPE mn[X] = 1, m =is row number, n =is column number.:.
* | | |0 = No key event.
* | | |1 = Corresponding key has a high to low event change.
* | | |Note:
* | | |Hardware will set this bit, and software should clear this bit by writing 1.
* | | |Software can clear PKEYINT (KPISTATUS[4]) by writing 1 bit by bit to this register.
* @var KPI_T::KRF0
* Offset: 0x20 Lower 32 Key Release Flag Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KRFmn |Lower 32 Key Release Event Change IndicatorFlag
* | | |KRE mn[X] = 1, m= is row number, n= is column number.:.
* | | |0 = No key event.
* | | |1 = Corresponding key has a low to high event change.
* | | |Note:
* | | |Hardware will set this bit, and software should clear this bit by writing 1.
* | | |Software can clear RKEYINT (KPISTATUS[3]) by writing 1 bit by bit to this register.
* @var KPI_T::KRF1
* Offset: 0x24 Upper 32 Key Release Flag Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |KRFmn |Upper 32 Key Release Event Change IndicatorFlag
* | | |KRE mn[X] = 1, m =is row number, n =is column number.:.
* | | |0 = No key event.
* | | |1 = Corresponding key has a low to high event change.
* | | |Note:
* | | |Hardware will set this bit, and software should clear this bit by writing 1.
* | | |Software can clear RKEYINT (KPISTATUS[3]) by writing 1 bit by bit to this register.
* @var KPI_T::DLYCTL
* Offset: 0x28 Delay Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PSCDIV |Pre-scale Divider
* | | |This value is used to divide RESCALE that is set in KPICONFKPI_CTL[15:8]
* | | |The prescale divider counter is clocked by the divided crystal clock, xCLOCK
* | | |The number is from 1 to 256.
* | | |E.g. If the crystal clock is 1Mhz then the xCLOCK period is 1us. If the keypad matrix is 3x3. Then,
* | | |each row scan time = xCLOCK x PRESCALEPSC x PrescaleDividerPSCDIV.
* | | |key array scan time = each row scan time x ROWS.
* | | |example scan time for PRESCALEPSC = 0x40, and PrescaleDividerPSCDIV = 0x1F.
* | | |each row scan time = 1us x 65 x 32 = 2.08ms.
* | | |scan time = 2.08 x 3 = 6.24ms.
* | | |Note:
* | | |When PRESCALEPSC (KPICONFKPI_CTL[15:8]) is determined, De-bounce sampling cycle should not exceed the half of (PRESCALEPSC x PrescaleDividerPSCDIV),
* | | |in the above example, and if scan row delay cycle is 4 xclock
* | | |The maximum DBCLKSEL(KPICONFKPI_CTL[19:16]) should be 1024 x clock, bouncing time is 1ms.
* |[17:8] |SCANDLY |Key Array Scan Delay
* | | |This value is used to insert delay cycle between each key array scan.
* | | |The key array scan delay counter is clocked by the divided crystal clock, xCLOCK.
* | | |Key array scan delay time = xCLOCK x KASDSCANDLY.
* | | |The number of key array scan delay cycle is 0 and from 2 to 1024.
* | | |0 = No delay.
* | | |Others = others + 1 cycles.
* | | |Note:
* | | |If the key array scan delay is set to 0, there are no delay between each key array scan.
* | | |There are no delay 1 cycle situation.
*/
__IO uint32_t CTL; /*!< [0x0000] Keypad Control Register */
__IO uint32_t Reserved0; /*!< [0x0004] Reserved */
__IO uint32_t STATUS; /*!< [0x0008] Keypad Status Register */
__IO uint32_t Reserved1; /*!< [0x000c] Reserved */
__I uint32_t KST[2]; /*!< [0x0010-0x0014] Keypad State Register 0 */
__IO uint32_t KPF[2]; /*!< [0x0018-0x001c] Lower 32 Key Press Flag Register 0 */
__IO uint32_t KRF[2]; /*!< [0x0020-0x0024] Lower 32 Key Release Flag Register 0 */
__IO uint32_t DLYCTL; /*!< [0x0028] Delay Control Register */
} KPI_T;
/**
@addtogroup KPI_CONST KPI Bit Field Definition
Constant Definitions for KPI Controller
@{ */
#define KPI_CTL_KPEN_Pos (0) /*!< KPI_T::CTL: KPEN Position */
#define KPI_CTL_KPEN_Msk (0x1ul << KPI_CTL_KPEN_Pos) /*!< KPI_T::CTL: KPEN Mask */
#define KPI_CTL_KPIEN_Pos (1) /*!< KPI_T::CTL: KPIEN Position */
#define KPI_CTL_KPIEN_Msk (0x1ul << KPI_CTL_KPIEN_Pos) /*!< KPI_T::CTL: KPIEN Mask */
#define KPI_CTL_KRIEN_Pos (2) /*!< KPI_T::CTL: KRIEN Position */
#define KPI_CTL_KRIEN_Msk (0x1ul << KPI_CTL_KRIEN_Pos) /*!< KPI_T::CTL: KRIEN Mask */
#define KPI_CTL_KIEN_Pos (3) /*!< KPI_T::CTL: KIEN Position */
#define KPI_CTL_KIEN_Msk (0x1ul << KPI_CTL_KIEN_Pos) /*!< KPI_T::CTL: KIEN Mask */
#define KPI_CTL_DBCT_Pos (4) /*!< KPI_T::CTL: DBCT Position */
#define KPI_CTL_DBCT_Msk (0x3ul << KPI_CTL_DBCT_Pos) /*!< KPI_T::CTL: DBCT Mask */
#define KPI_CTL_PSC_Pos (8) /*!< KPI_T::CTL: PSC Position */
#define KPI_CTL_PSC_Msk (0xfful << KPI_CTL_PSC_Pos) /*!< KPI_T::CTL: PSC Mask */
#define KPI_CTL_DBCLKSEL_Pos (16) /*!< KPI_T::CTL: DBCLKSEL Position */
#define KPI_CTL_DBCLKSEL_Msk (0xful << KPI_CTL_DBCLKSEL_Pos) /*!< KPI_T::CTL: DBCLKSEL Mask */
#define KPI_CTL_ROWDLY_Pos (22) /*!< KPI_T::CTL: ROWDLY Position */
#define KPI_CTL_ROWDLY_Msk (0x3ul << KPI_CTL_ROWDLY_Pos) /*!< KPI_T::CTL: ROWDLY Mask */
#define KPI_CTL_KCOL_Pos (24) /*!< KPI_T::CTL: KCOL Position */
#define KPI_CTL_KCOL_Msk (0x7ul << KPI_CTL_KCOL_Pos) /*!< KPI_T::CTL: KCOL Mask */
#define KPI_CTL_KROW_Pos (28) /*!< KPI_T::CTL: KROW Position */
#define KPI_CTL_KROW_Msk (0x7ul << KPI_CTL_KROW_Pos) /*!< KPI_T::CTL: KROW Mask */
#define KPI_STATUS_TKRIF_Pos (1) /*!< KPI_T::STATUS: TKRIF Position */
#define KPI_STATUS_TKRIF_Msk (0x1ul << KPI_STATUS_TKRIF_Pos) /*!< KPI_T::STATUS: TKRIF Mask */
#define KPI_STATUS_KIF_Pos (2) /*!< KPI_T::STATUS: KIF Position */
#define KPI_STATUS_KIF_Msk (0x1ul << KPI_STATUS_KIF_Pos) /*!< KPI_T::STATUS: KIF Mask */
#define KPI_STATUS_KRIF_Pos (3) /*!< KPI_T::STATUS: KRIF Position */
#define KPI_STATUS_KRIF_Msk (0x1ul << KPI_STATUS_KRIF_Pos) /*!< KPI_T::STATUS: KRIF Mask */
#define KPI_STATUS_KPIF_Pos (4) /*!< KPI_T::STATUS: KPIF Position */
#define KPI_STATUS_KPIF_Msk (0x1ul << KPI_STATUS_KPIF_Pos) /*!< KPI_T::STATUS: KPIF Mask */
#define KPI_KST0_KSTmn_Pos (0) /*!< KPI_T::KST0: KSTmn Position */
#define KPI_KST0_KSTmn_Msk (0xfffffffful << KPI_KST0_KSTmn_Pos) /*!< KPI_T::KST0: KSTmn Mask */
#define KPI_KST1_KESTmn_Pos (0) /*!< KPI_T::KST1: KESTmn Position */
#define KPI_KST1_KESTmn_Msk (0xfffful << KPI_KST1_KESTmn_Pos) /*!< KPI_T::KST1: KESTmn Mask */
#define KPI_KPF0_KPFmn_Pos (0) /*!< KPI_T::KPF0: KPFmn Position */
#define KPI_KPF0_KPFmn_Msk (0xfffffffful << KPI_KPF0_KPFmn_Pos) /*!< KPI_T::KPF0: KPFmn Mask */
#define KPI_KPF1_KPEmn_Pos (0) /*!< KPI_T::KPF1: KPEmn Position */
#define KPI_KPF1_KPEmn_Msk (0xfffful << KPI_KPF1_KPEmn_Pos) /*!< KPI_T::KPF1: KPEmn Mask */
#define KPI_KRF0_KRFmn_Pos (0) /*!< KPI_T::KRF0: KRFmn Position */
#define KPI_KRF0_KRFmn_Msk (0xfffffffful << KPI_KRF0_KRFmn_Pos) /*!< KPI_T::KRF0: KRFmn Mask */
#define KPI_KRF1_KRFmn_Pos (0) /*!< KPI_T::KRF1: KRFmn Position */
#define KPI_KRF1_KRFmn_Msk (0xfffful << KPI_KRF1_KRFmn_Pos) /*!< KPI_T::KRF1: KRFmn Mask */
#define KPI_DLYCTL_PSCDIV_Pos (0) /*!< KPI_T::DLYCTL: PSCDIV Position */
#define KPI_DLYCTL_PSCDIV_Msk (0xfful << KPI_DLYCTL_PSCDIV_Pos) /*!< KPI_T::DLYCTL: PSCDIV Mask */
#define KPI_DLYCTL_SCANDLY_Pos (8) /*!< KPI_T::DLYCTL: SCANDLY Position */
#define KPI_DLYCTL_SCANDLY_Msk (0x3fful << KPI_DLYCTL_SCANDLY_Pos) /*!< KPI_T::DLYCTL: SCANDLY Mask */
/**@}*/ /* KPI_CONST */
/**@}*/ /* end of KPI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __KEYPAD_REG_H__ */

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/**************************************************************************//**
* @file m460.h
* @version V3.00
* @brief M460 peripheral access layer header file.
* This file contains all the peripheral register's definitions,
* bits definitions and memory mapping for NuMicro M460 MCU.
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
/**
\mainpage NuMicro M460 Driver Reference Guide
*
* <b>Introduction</b>
*
* This user manual describes the usage of M460 Series MCU device driver
*
* <b>Disclaimer</b>
*
* The Software is furnished "AS IS", without warranty as to performance or results, and
* the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
* warranties, express, implied or otherwise, with regard to the Software, its use, or
* operation, including without limitation any and all warranties of merchantability, fitness
* for a particular purpose, and non-infringement of intellectual property rights.
*
* <b>Important Notice</b>
*
* Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
* any malfunction or failure of which may cause loss of human life, bodily injury or severe
* property damage. Such applications are deemed, "Insecure Usage".
*
* Insecure usage includes, but is not limited to: equipment for surgical implementation,
* atomic energy control instruments, airplane or spaceship instruments, the control or
* operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
* instruments, all types of safety devices, and other applications intended to support or
* sustain life.
*
* All Insecure Usage shall be made at customer's risk, and in the event that third parties
* lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
* the damages and liabilities thus incurred by Nuvoton.
*
* Please note that all data and specifications are subject to change without notice. All the
* trademarks of products and companies mentioned in this datasheet belong to their respective
* owners.
*
* <b>Copyright Notice</b>
*
* Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*/
#ifndef __M460_H__
#define __M460_H__
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup CMSIS_Device Device CMSIS Definitions
Configuration of the Cortex-M4 Processor and Core Peripherals
@{
*/
/**
* @details Interrupt Number Definition.
*/
typedef enum IRQn
{
/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
/****** M460 Specific Interrupt Numbers ********************************************************/
BOD_IRQn = 0, /*!< Brown Out detection Interrupt */
IRC_IRQn = 1, /*!< Internal RC Interrupt */
PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */
RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */
CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */
ISP_IRQn = 5, /*!< FMC ISP Interrupt */
RTC_IRQn = 6, /*!< Real Time Clock Interrupt */
TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */
WDT_IRQn = 8, /*!< Watchdog timer Interrupt */
WWDT_IRQn = 9, /*!< Window Watchdog timer Interrupt */
EINT0_IRQn = 10, /*!< External Input 0 Interrupt */
EINT1_IRQn = 11, /*!< External Input 1 Interrupt */
EINT2_IRQn = 12, /*!< External Input 2 Interrupt */
EINT3_IRQn = 13, /*!< External Input 3 Interrupt */
EINT4_IRQn = 14, /*!< External Input 4 Interrupt */
EINT5_IRQn = 15, /*!< External Input 5 Interrupt */
GPA_IRQn = 16, /*!< GPIO Port A Interrupt */
GPB_IRQn = 17, /*!< GPIO Port B Interrupt */
GPC_IRQn = 18, /*!< GPIO Port C Interrupt */
GPD_IRQn = 19, /*!< GPIO Port D Interrupt */
GPE_IRQn = 20, /*!< GPIO Port E Interrupt */
GPF_IRQn = 21, /*!< GPIO Port F Interrupt */
QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */
SPI0_IRQn = 23, /*!< SPI0 Interrupt */
BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */
EPWM0P0_IRQn = 25, /*!< EPWM0P0 Interrupt */
EPWM0P1_IRQn = 26, /*!< EPWM0P1 Interrupt */
EPWM0P2_IRQn = 27, /*!< EPWM0P2 Interrupt */
BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */
EPWM1P0_IRQn = 29, /*!< EPWM1P0 Interrupt */
EPWM1P1_IRQn = 30, /*!< EPWM1P1 Interrupt */
EPWM1P2_IRQn = 31, /*!< EPWM1P2 Interrupt */
TMR0_IRQn = 32, /*!< Timer 0 Interrupt */
TMR1_IRQn = 33, /*!< Timer 1 Interrupt */
TMR2_IRQn = 34, /*!< Timer 2 Interrupt */
TMR3_IRQn = 35, /*!< Timer 3 Interrupt */
UART0_IRQn = 36, /*!< UART 0 Interrupt */
UART1_IRQn = 37, /*!< UART 1 Interrupt */
I2C0_IRQn = 38, /*!< I2C 0 Interrupt */
I2C1_IRQn = 39, /*!< I2C 1 Interrupt */
PDMA0_IRQn = 40, /*!< Peripheral DMA 0 Interrupt */
DAC_IRQn = 41, /*!< DAC Interrupt */
EADC00_IRQn = 42, /*!< EADC00 Interrupt */
EADC01_IRQn = 43, /*!< EADC01 Interrupt */
ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */
ACMP23_IRQn = 45, /*!< Analog Comparator 2 and 3 Interrupt */
EADC02_IRQn = 46, /*!< EADC02 Interrupt */
EADC03_IRQn = 47, /*!< EADC03 Interrupt */
UART2_IRQn = 48, /*!< UART2 Interrupt */
UART3_IRQn = 49, /*!< UART3 Interrupt */
QSPI1_IRQn = 50, /*!< QSPI1 Interrupt */
SPI1_IRQn = 51, /*!< SPI1 Interrupt */
SPI2_IRQn = 52, /*!< SPI2 Interrupt */
USBD_IRQn = 53, /*!< USB device Interrupt */
USBH_IRQn = 54, /*!< USB host Interrupt */
USBOTG_IRQn = 55, /*!< USB OTG Interrupt */
BMC_IRQn = 56, /*!< BMC Interrupt */
SPI5_IRQn = 57, /*!< SPI5 Interrupt */
SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */
SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */
SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */
GPJ_IRQn = 61, /*!< GPIO Port J Interrupt */
SPI3_IRQn = 62, /*!< SPI3 Interrupt */
SPI4_IRQn = 63, /*!< SPI4 Interrupt */
EMAC0_TXRX_IRQn = 66, /*!< Ethernet MAC 0 Interrupt */
SDH0_IRQn = 64, /*!< Secure Digital Host Controller 0 Interrupt */
USBD20_IRQn = 65, /*!< High Speed USB device Interrupt */
I2S0_IRQn = 68, /*!< I2S0 Interrupt */
I2S1_IRQn = 69, /*!< I2S1 Interrupt */
SPI6_IRQn = 70, /*!< SPI6 Interrupt */
CRPT_IRQn = 71, /*!< CRPT Interrupt */
GPG_IRQn = 72, /*!< GPIO Port G Interrupt */
EINT6_IRQn = 73, /*!< External Input 6 Interrupt */
UART4_IRQn = 74, /*!< UART4 Interrupt */
UART5_IRQn = 75, /*!< UART5 Interrupt */
USCI0_IRQn = 76, /*!< USCI0 Interrupt */
SPI7_IRQn = 77, /*!< SPI7 Interrupt */
BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */
BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */
SPIM_IRQn = 80, /*!< SPIM Interrupt */
CCAP_IRQn = 81, /*!< CCAP Interrupt */
I2C2_IRQn = 82, /*!< I2C2 Interrupt */
I2C3_IRQn = 83, /*!< I2C3 Interrupt */
EQEI0_IRQn = 84, /*!< EQEI0 Interrupt */
EQEI1_IRQn = 85, /*!< EQEI1 Interrupt */
ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */
ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */
GPH_IRQn = 88, /*!< GPIO Port H Interrupt */
EINT7_IRQn = 89, /*!< External Input 7 Interrupt */
SDH1_IRQn = 90, /*!< Secure Digital Host Controller 1 Interrupt */
PSIO_IRQn = 91, /*!< PSIO Interrupt */
HSUSBH_IRQn = 92, /*!< High speed USB host Interrupt */
USBOTG20_IRQn = 93, /*!< High speed USB OTG Interrupt */
ECAP2_IRQn = 94, /*!< ECAP2 Interrupt */
ECAP3_IRQn = 95, /*!< ECAP3 Interrupt */
KPI_IRQn = 96, /*!< Keypad Interface Interrupt */
HBI_IRQn = 97, /*!< HBI Interrupt */
PDMA1_IRQn = 98, /*!< Peripheral DMA 1 Interrupt */
UART8_IRQn = 99, /*!< UART8 Interrupt */
UART9_IRQn = 100, /*!< UART9 Interrupt */
TRNG_IRQn = 101, /*!< TRNG Interrupt */
UART6_IRQn = 102, /*!< UART6 Interrupt */
UART7_IRQn = 103, /*!< UART7 Interrupt */
EADC10_IRQn = 104, /*!< EADC10 Interrupt */
EADC11_IRQn = 105, /*!< EADC11 Interrupt */
EADC12_IRQn = 106, /*!< EADC12 Interrupt */
EADC13_IRQn = 107, /*!< EADC13 Interrupt */
SPI8_IRQn = 108, /*!< SPI8 Interrupt */
KS_IRQn = 109, /*!< Keystore Interrupt */
GPI_IRQn = 110, /*!< GPIO Port I Interrupt */
SPI9_IRQn = 111, /*!< SPI9 Interrupt */
CANFD00_IRQn = 112, /*!< CANFD00 Interrupt */
CANFD01_IRQn = 113, /*!< CANFD01 Interrupt */
CANFD10_IRQn = 114, /*!< CANFD10 Interrupt */
CANFD11_IRQn = 115, /*!< CANFD11 Interrupt */
EQEI2_IRQn = 116, /*!< EQEI2 Interrupt */
EQEI3_IRQn = 117, /*!< EQEI3 Interrupt */
I2C4_IRQn = 118, /*!< I2C4 Interrupt */
SPI10_IRQn = 119, /*!< SPI10 Interrupt */
CANFD20_IRQn = 120, /*!< CANFD20 Interrupt */
CANFD21_IRQn = 121, /*!< CANFD21 Interrupt */
CANFD30_IRQn = 122, /*!< CANFD30 Interrupt */
CANFD31_IRQn = 123, /*!< CANFD31 Interrupt */
EADC20_IRQn = 124, /*!< EADC20 Interrupt */
EADC21_IRQn = 125, /*!< EADC21 Interrupt */
EADC22_IRQn = 126, /*!< EADC22 Interrupt */
EADC23_IRQn = 127, /*!< EADC23 Interrupt */
}
IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M4 Processor and Core Peripherals */
#define __CM4_REV 0x0201UL /*!< Core Revision r2p1 */
#define __NVIC_PRIO_BITS 4UL /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0UL /*!< Set to 1 if different SysTick Config is used */
#define __MPU_PRESENT 1UL /*!< MPU present or not */
#ifdef __FPU_PRESENT
#undef __FPU_PRESENT
#define __FPU_PRESENT 1UL /*!< FPU present or not */
#else
#define __FPU_PRESENT 1UL /*!< FPU present or not */
#endif
/*@}*/ /* end of group CMSIS_Device */
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_m460.h" /* System include file */
#include <stdint.h>
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************/
/* Register definitions */
/******************************************************************************/
#include "sys_reg.h"
#include "clk_reg.h"
#include "fmc_reg.h"
#include "gpio_reg.h"
#include "pdma_reg.h"
#include "timer_reg.h"
#include "wdt_reg.h"
#include "wwdt_reg.h"
#include "rtc_reg.h"
#include "epwm_reg.h"
#include "bpwm_reg.h"
#include "eqei_reg.h"
#include "ecap_reg.h"
#include "uart_reg.h"
#include "emac_reg.h"
#include "sc_reg.h"
#include "i2s_reg.h"
#include "spi_reg.h"
#include "qspi_reg.h"
#include "spim_reg.h"
#include "i2c_reg.h"
#include "uuart_reg.h"
#include "uspi_reg.h"
#include "ui2c_reg.h"
#include "canfd_reg.h"
#include "sdh_reg.h"
#include "ebi_reg.h"
#include "usbd_reg.h"
#include "hsusbd_reg.h"
#include "usbh_reg.h"
#include "hsusbh_reg.h"
#include "otg_reg.h"
#include "hsotg_reg.h"
#include "crc_reg.h"
#include "crypto_reg.h"
#include "trng_reg.h"
#include "eadc_reg.h"
#include "dac_reg.h"
#include "acmp_reg.h"
#include "ccap_reg.h"
#include "keystore_reg.h"
#include "kpi_reg.h"
#include "psio_reg.h"
#include "hbi_reg.h"
#include "bmc_reg.h"
/** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Base
Memory Mapped Structure for Peripherals
@{
*/
/* Peripheral and SRAM base address */
#define FLASH_BASE ((uint32_t)0x00000000) /*!< Flash base address */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM Base Address */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral Base Address */
#define TCM_BASE (PERIPH_BASE + 0xBE000)
/*!< AHB peripherals */
//HCLK
// CPU,CRC,EBI,EMC,FMC,PDMA,SD0,SD1,CRPT,SPIM,SRAM,HSUSBD, HSUSBH, USBH
#define SYS_BASE (PERIPH_BASE + 0x00000UL)
#define CLK_BASE (PERIPH_BASE + 0x00200UL)
#define NMI_BASE (PERIPH_BASE + 0x00300UL)
#define GPIOA_BASE (PERIPH_BASE + 0x04000UL)
#define GPIOB_BASE (PERIPH_BASE + 0x04040UL)
#define GPIOC_BASE (PERIPH_BASE + 0x04080UL)
#define GPIOD_BASE (PERIPH_BASE + 0x040C0UL)
#define GPIOE_BASE (PERIPH_BASE + 0x04100UL)
#define GPIOF_BASE (PERIPH_BASE + 0x04140UL)
#define GPIOG_BASE (PERIPH_BASE + 0x04180UL)
#define GPIOH_BASE (PERIPH_BASE + 0x041C0UL)
#define GPIOI_BASE (PERIPH_BASE + 0x04200UL)
#define GPIOJ_BASE (PERIPH_BASE + 0x04240UL)
#define GPIO_INT_BASE (PERIPH_BASE + 0x04450UL)
#define GPIO_PIN_DATA_BASE (PERIPH_BASE + 0x04800UL)
#define SPIM_BASE (PERIPH_BASE + 0x07000UL)
#define PDMA0_BASE (PERIPH_BASE + 0x08000UL)
#define PDMA1_BASE (PERIPH_BASE + 0x18000UL)
#define USBH_BASE (PERIPH_BASE + 0x09000UL)
#define HSUSBH_BASE (PERIPH_BASE + 0x1A000UL)
#define EMAC_BASE (PERIPH_BASE + 0x12000UL)
#define FMC_BASE (PERIPH_BASE + 0x0C000UL)
#define SDH0_BASE (PERIPH_BASE + 0x0D000UL)
#define SDH1_BASE (PERIPH_BASE + 0x0E000UL)
#define EBI_BASE (PERIPH_BASE + 0x10000UL)
#define HSUSBD_BASE (PERIPH_BASE + 0x19000UL)
#define CCAP_BASE (PERIPH_BASE + 0x30000UL)
#define CRC_BASE (PERIPH_BASE + 0x31000UL)
#define CRPT_BASE (PERIPH_BASE + 0x32000UL)
#define KS_BASE (PERIPH_BASE + 0x35000UL)
#define TAMPER_BASE (PERIPH_BASE + 0xE1000UL)
#define HBI_BASE (PERIPH_BASE + 0xCE000UL)
#define BMC_BASE (PERIPH_BASE + 0x1B000UL)
//PCLK0
// BPWM0,QSPI0,ECAP2,I2C0/2/4,I2S0,OPA,EPWM0,EQEI0/2,SC0/2,SPI1/3/5/7/9,TMR01,UR0/2/4/6/8,USBD,USCI0,WDT
/*!< APB0 peripherals */
#define WDT_BASE (PERIPH_BASE + 0x40000UL)
#define WWDT_BASE (PERIPH_BASE + 0x40100UL)
#define OPA_BASE (PERIPH_BASE + 0x46000UL)
#define I2S0_BASE (PERIPH_BASE + 0x48000UL)
#define EADC1_BASE (PERIPH_BASE + 0x4B000UL)
#define TIMER0_BASE (PERIPH_BASE + 0x50000UL)
#define TIMER1_BASE (PERIPH_BASE + 0x50100UL)
#define EPWM0_BASE (PERIPH_BASE + 0x58000UL)
#define BPWM0_BASE (PERIPH_BASE + 0x5A000UL)
#define QSPI0_BASE (PERIPH_BASE + 0x60000UL)
#define SPI1_BASE (PERIPH_BASE + 0x62000UL)
#define SPI3_BASE (PERIPH_BASE + 0x64000UL)
#define SPI5_BASE (PERIPH_BASE + 0x66000UL)
#define SPI7_BASE (PERIPH_BASE + 0x68000UL)
#define SPI9_BASE (PERIPH_BASE + 0x6C000UL)
#define UART0_BASE (PERIPH_BASE + 0x70000UL)
#define UART2_BASE (PERIPH_BASE + 0x72000UL)
#define UART4_BASE (PERIPH_BASE + 0x74000UL)
#define UART6_BASE (PERIPH_BASE + 0x76000UL)
#define UART8_BASE (PERIPH_BASE + 0x78000UL)
#define I2C0_BASE (PERIPH_BASE + 0x80000UL)
#define I2C2_BASE (PERIPH_BASE + 0x82000UL)
#define CANFD0_BASE (PERIPH_BASE + 0x20000UL)
#define CANFD2_BASE (PERIPH_BASE + 0x28000UL)
#define EQEI0_BASE (PERIPH_BASE + 0xB0000UL)
#define ECAP0_BASE (PERIPH_BASE + 0xB4000UL)
#define USCI0_BASE (PERIPH_BASE + 0xD0000UL)
//PCLK1
// ACMP01/23,EADC0/1/2,BPWM1,DAC,ECAP1/3,I2C1/3,I2S1,OTG,HSOTG,EPWM1,QEI1/3,RTC,SC1,SPI0/2/4/6/8/10,QSPI1,TMR23,UR1/3/5/7/9,PSIO
/*!< APB1 peripherals */
#define RTC_BASE (PERIPH_BASE + 0x41000UL)
#define EADC0_BASE (PERIPH_BASE + 0x43000UL)
#define ACMP01_BASE (PERIPH_BASE + 0x45000UL)
#define I2S1_BASE (PERIPH_BASE + 0x49000UL)
#define USBD_BASE (PERIPH_BASE + 0xC0000UL)
#define EADC1_BASE (PERIPH_BASE + 0x4B000UL)
#define OTG_BASE (PERIPH_BASE + 0x4D000UL)
#define HSOTG_BASE (PERIPH_BASE + 0x4F000UL)
#define TIMER2_BASE (PERIPH_BASE + 0x51000UL)
#define TIMER3_BASE (PERIPH_BASE + 0x51100UL)
#define EADC2_BASE (PERIPH_BASE + 0x97000UL)
#define EPWM1_BASE (PERIPH_BASE + 0x59000UL)
#define BPWM1_BASE (PERIPH_BASE + 0x5B000UL)
#define SPI0_BASE (PERIPH_BASE + 0x61000UL)
#define SPI2_BASE (PERIPH_BASE + 0x63000UL)
#define SPI4_BASE (PERIPH_BASE + 0x65000UL)
#define SPI6_BASE (PERIPH_BASE + 0x67000UL)
#define QSPI1_BASE (PERIPH_BASE + 0x69000UL)
#define SPI8_BASE (PERIPH_BASE + 0x6B000UL)
#define SPI10_BASE (PERIPH_BASE + 0x6D000UL)
#define UART1_BASE (PERIPH_BASE + 0x71000UL)
#define UART3_BASE (PERIPH_BASE + 0x73000UL)
#define UART5_BASE (PERIPH_BASE + 0x75000UL)
#define UART7_BASE (PERIPH_BASE + 0x77000UL)
#define UART9_BASE (PERIPH_BASE + 0x79000UL)
#define I2C1_BASE (PERIPH_BASE + 0x81000UL)
#define CANFD1_BASE (PERIPH_BASE + 0x24000UL)
#define CANFD3_BASE (PERIPH_BASE + 0x2C000UL)
#define EQEI1_BASE (PERIPH_BASE + 0xB1000UL)
#define ECAP1_BASE (PERIPH_BASE + 0xB5000UL)
#define TRNG_BASE (PERIPH_BASE + 0xB9000UL)
#define ECAP2_BASE (PERIPH_BASE + 0xB6000UL)
#define ECAP3_BASE (PERIPH_BASE + 0xB7000UL)
#define EQEI2_BASE (PERIPH_BASE + 0xB2000UL)
#define EQEI3_BASE (PERIPH_BASE + 0xB3000UL)
#define I2C3_BASE (PERIPH_BASE + 0x83000UL)
#define I2C4_BASE (PERIPH_BASE + 0x84000UL)
#define SC0_BASE (PERIPH_BASE + 0x90000UL)
#define SC1_BASE (PERIPH_BASE + 0x91000UL)
#define SC2_BASE (PERIPH_BASE + 0x92000UL)
#define DAC0_BASE (PERIPH_BASE + 0x47000UL)
#define DAC1_BASE (PERIPH_BASE + 0x47040UL)
#define DACDBG_BASE (PERIPH_BASE + 0x47FECUL)
#define OPA0_BASE (PERIPH_BASE + 0x46000UL)
#define KPI_BASE (PERIPH_BASE + 0x0C2000UL)
#define PSIO_BASE (PERIPH_BASE + 0x0C3000UL)
#define ACMP23_BASE (PERIPH_BASE + 0x0C9000UL)
/*@}*/ /* end of group PERIPHERAL_MEM_MAP */
/** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer
The Declaration of Peripherals
@{
*/
#define TCM ((TCM_T *) TCM_BASE)
#define SYS ((SYS_T *) SYS_BASE)
#define CLK ((CLK_T *) CLK_BASE)
#define NMI ((NMI_T *) NMI_BASE)
#define PA ((GPIO_T *) GPIOA_BASE)
#define PB ((GPIO_T *) GPIOB_BASE)
#define PC ((GPIO_T *) GPIOC_BASE)
#define PD ((GPIO_T *) GPIOD_BASE)
#define PE ((GPIO_T *) GPIOE_BASE)
#define PF ((GPIO_T *) GPIOF_BASE)
#define PG ((GPIO_T *) GPIOG_BASE)
#define PH ((GPIO_T *) GPIOH_BASE)
#define PI ((GPIO_T *) GPIOI_BASE)
#define PJ ((GPIO_T *) GPIOJ_BASE)
#define GPA ((GPIO_T *) GPIOA_BASE)
#define GPB ((GPIO_T *) GPIOB_BASE)
#define GPC ((GPIO_T *) GPIOC_BASE)
#define GPD ((GPIO_T *) GPIOD_BASE)
#define GPE ((GPIO_T *) GPIOE_BASE)
#define GPF ((GPIO_T *) GPIOF_BASE)
#define GPG ((GPIO_T *) GPIOG_BASE)
#define GPH ((GPIO_T *) GPIOH_BASE)
#define GPI ((GPIO_T *) GPIOI_BASE)
#define GPJ ((GPIO_T *) GPIOJ_BASE)
#define GPIO ((GPIO_INT_T *) GPIO_INT_BASE)
#define PDMA0 ((PDMA_T *) PDMA0_BASE)
#define PDMA1 ((PDMA_T *) PDMA1_BASE)
#define USBH ((USBH_T *) USBH_BASE)
#define HSUSBH ((HSUSBH_T *) HSUSBH_BASE)
#define EMAC ((EMAC_T *) EMAC_BASE)
#define FMC ((FMC_T *) FMC_BASE)
#define SDH0 ((SDH_T *) SDH0_BASE)
#define SDH1 ((SDH_T *) SDH1_BASE)
#define EBI ((EBI_T *) EBI_BASE)
#define CRC ((CRC_T *) CRC_BASE)
#define TAMPER ((TAMPER_T *) TAMPER_BASE)
#define KS ((KS_T *) KS_BASE)
#define HBI ((HBI_T *) HBI_BASE)
#define WDT ((WDT_T *) WDT_BASE)
#define WWDT ((WWDT_T *) WWDT_BASE)
#define RTC ((RTC_T *) RTC_BASE)
#define EADC0 ((EADC_T *) EADC0_BASE)
#define EADC1 ((EADC_T *) EADC1_BASE)
#define EADC2 ((EADC_T *) EADC2_BASE)
#define ACMP01 ((ACMP_T *) ACMP01_BASE)
#define ACMP23 ((ACMP_T *) ACMP23_BASE)
#define KPI ((KPI_T *) KPI_BASE)
#define I2S0 ((I2S_T *) I2S0_BASE)
#define I2S1 ((I2S_T *) I2S1_BASE)
#define USBD ((USBD_T *) USBD_BASE)
#define OTG ((OTG_T *) OTG_BASE)
#define HSUSBD ((HSUSBD_T *)HSUSBD_BASE)
#define HSOTG ((HSOTG_T *) HSOTG_BASE)
#define TIMER0 ((TIMER_T *) TIMER0_BASE)
#define TIMER1 ((TIMER_T *) TIMER1_BASE)
#define TIMER2 ((TIMER_T *) TIMER2_BASE)
#define TIMER3 ((TIMER_T *) TIMER3_BASE)
#define EPWM0 ((EPWM_T *) EPWM0_BASE)
#define EPWM1 ((EPWM_T *) EPWM1_BASE)
#define BPWM0 ((BPWM_T *) BPWM0_BASE)
#define BPWM1 ((BPWM_T *) BPWM1_BASE)
#define ECAP0 ((ECAP_T *) ECAP0_BASE)
#define ECAP1 ((ECAP_T *) ECAP1_BASE)
#define ECAP2 ((ECAP_T *) ECAP2_BASE)
#define ECAP3 ((ECAP_T *) ECAP3_BASE)
#define EQEI0 ((EQEI_T *) EQEI0_BASE)
#define EQEI1 ((EQEI_T *) EQEI1_BASE)
#define EQEI2 ((EQEI_T *) EQEI2_BASE)
#define EQEI3 ((EQEI_T *) EQEI3_BASE)
#define QSPI0 ((QSPI_T *) QSPI0_BASE)
#define QSPI1 ((QSPI_T *) QSPI1_BASE)
#define SPI0 ((SPI_T *) SPI0_BASE)
#define SPI1 ((SPI_T *) SPI1_BASE)
#define SPI2 ((SPI_T *) SPI2_BASE)
#define SPI3 ((SPI_T *) SPI3_BASE)
#define SPI4 ((SPI_T *) SPI4_BASE)
#define SPI5 ((SPI_T *) SPI5_BASE)
#define SPI6 ((SPI_T *) SPI6_BASE)
#define SPI7 ((SPI_T *) SPI7_BASE)
#define SPI8 ((SPI_T *) SPI8_BASE)
#define SPI9 ((SPI_T *) SPI9_BASE)
#define SPI10 ((SPI_T *) SPI10_BASE)
#define UART0 ((UART_T *) UART0_BASE)
#define UART1 ((UART_T *) UART1_BASE)
#define UART2 ((UART_T *) UART2_BASE)
#define UART3 ((UART_T *) UART3_BASE)
#define UART4 ((UART_T *) UART4_BASE)
#define UART5 ((UART_T *) UART5_BASE)
#define UART6 ((UART_T *) UART6_BASE)
#define UART7 ((UART_T *) UART7_BASE)
#define UART8 ((UART_T *) UART8_BASE)
#define UART9 ((UART_T *) UART9_BASE)
#define I2C0 ((I2C_T *) I2C0_BASE)
#define I2C1 ((I2C_T *) I2C1_BASE)
#define I2C2 ((I2C_T *) I2C2_BASE)
#define I2C3 ((I2C_T *) I2C3_BASE)
#define I2C4 ((I2C_T *) I2C4_BASE)
#define SC0 ((SC_T *) SC0_BASE)
#define SC1 ((SC_T *) SC1_BASE)
#define SC2 ((SC_T *) SC2_BASE)
#define CANFD0 ((CANFD_T *) CANFD0_BASE)
#define CANFD1 ((CANFD_T *) CANFD1_BASE)
#define CANFD2 ((CANFD_T *) CANFD2_BASE)
#define CANFD3 ((CANFD_T *) CANFD3_BASE)
#define CRPT ((CRPT_T *) CRPT_BASE)
#define TRNG ((TRNG_T *) TRNG_BASE)
#define SPIM ((volatile SPIM_T *) SPIM_BASE)
#define DAC0 ((DAC_T *) DAC0_BASE)
#define DAC1 ((DAC_T *) DAC1_BASE)
#define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Configuration Struct */
#define OPA ((OPA_T *) OPA_BASE)
#define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Configuration Struct */
#define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Configuration Struct */
#define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Configuration Struct */
#define CCAP ((CCAP_T *) CCAP_BASE)
#define PSIO ((PSIO_T *) PSIO_BASE)
#define BMC ((BMC_T *) BMC_BASE)
/*@}*/ /* end of group ERIPHERAL_DECLARATION */
/** @addtogroup IO_ROUTINE I/O Routines
The Declaration of I/O Routines
@{
*/
typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type
typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type
typedef volatile unsigned int vu32; ///< Define 32-bit unsigned volatile data type
/**
* @brief Get a 8-bit unsigned value from specified address
* @param[in] addr Address to get 8-bit data from
* @return 8-bit unsigned value stored in specified address
*/
#define M8(addr) (*((vu8 *) (addr)))
/**
* @brief Get a 16-bit unsigned value from specified address
* @param[in] addr Address to get 16-bit data from
* @return 16-bit unsigned value stored in specified address
* @note The input address must be 16-bit aligned
*/
#define M16(addr) (*((vu16 *) (addr)))
/**
* @brief Get a 32-bit unsigned value from specified address
* @param[in] addr Address to get 32-bit data from
* @return 32-bit unsigned value stored in specified address
* @note The input address must be 32-bit aligned
*/
#define M32(addr) (*((vu32 *) (addr)))
/**
* @brief Set a 32-bit unsigned value to specified I/O port
* @param[in] port Port address to set 32-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 32-bit aligned
*/
#define outpw(port,value) *((volatile unsigned int *)(port)) = (value)
/**
* @brief Get a 32-bit unsigned value from specified I/O port
* @param[in] port Port address to get 32-bit data from
* @return 32-bit unsigned value stored in specified I/O port
* @note The input port must be 32-bit aligned
*/
#define inpw(port) (*((volatile unsigned int *)(port)))
/**
* @brief Set a 16-bit unsigned value to specified I/O port
* @param[in] port Port address to set 16-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 16-bit aligned
*/
#define outps(port,value) *((volatile unsigned short *)(port)) = (value)
/**
* @brief Get a 16-bit unsigned value from specified I/O port
* @param[in] port Port address to get 16-bit data from
* @return 16-bit unsigned value stored in specified I/O port
* @note The input port must be 16-bit aligned
*/
#define inps(port) (*((volatile unsigned short *)(port)))
/**
* @brief Set a 8-bit unsigned value to specified I/O port
* @param[in] port Port address to set 8-bit data
* @param[in] value Value to write to I/O port
* @return None
*/
#define outpb(port,value) *((volatile unsigned char *)(port)) = (value)
/**
* @brief Get a 8-bit unsigned value from specified I/O port
* @param[in] port Port address to get 8-bit data from
* @return 8-bit unsigned value stored in specified I/O port
*/
#define inpb(port) (*((volatile unsigned char *)(port)))
/**
* @brief Set a 32-bit unsigned value to specified I/O port
* @param[in] port Port address to set 32-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 32-bit aligned
*/
#define outp32(port,value) *((volatile unsigned int *)(port)) = (value)
/**
* @brief Get a 32-bit unsigned value from specified I/O port
* @param[in] port Port address to get 32-bit data from
* @return 32-bit unsigned value stored in specified I/O port
* @note The input port must be 32-bit aligned
*/
#define inp32(port) (*((volatile unsigned int *)(port)))
/**
* @brief Set a 16-bit unsigned value to specified I/O port
* @param[in] port Port address to set 16-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 16-bit aligned
*/
#define outp16(port,value) *((volatile unsigned short *)(port)) = (value)
/**
* @brief Get a 16-bit unsigned value from specified I/O port
* @param[in] port Port address to get 16-bit data from
* @return 16-bit unsigned value stored in specified I/O port
* @note The input port must be 16-bit aligned
*/
#define inp16(port) (*((volatile unsigned short *)(port)))
/**
* @brief Set a 8-bit unsigned value to specified I/O port
* @param[in] port Port address to set 8-bit data
* @param[in] value Value to write to I/O port
* @return None
*/
#define outp8(port,value) *((volatile unsigned char *)(port)) = (value)
/**
* @brief Get a 8-bit unsigned value from specified I/O port
* @param[in] port Port address to get 8-bit data from
* @return 8-bit unsigned value stored in specified I/O port
*/
#define inp8(port) (*((volatile unsigned char *)(port)))
/*@}*/ /* end of group IO_ROUTINE */
/******************************************************************************/
/* Legacy Constants */
/******************************************************************************/
/** @addtogroup Legacy_Constants Legacy Constants
Legacy Constants
@{
*/
#ifndef NULL
#define NULL (0) ///< NULL pointer
#endif
#define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value
#define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value
#define ENABLE (1UL) ///< Enable, define to use in API parameters
#define DISABLE (0UL) ///< Disable, define to use in API parameters
/* Define one bit mask */
#define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer
#define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer
#define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer
#define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer
#define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer
#define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer
#define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer
#define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer
#define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer
#define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer
#define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer
#define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer
#define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer
#define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer
#define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer
#define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer
#define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer
#define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer
#define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer
#define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer
#define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer
#define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer
#define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer
#define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer
#define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer
#define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer
#define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer
#define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer
#define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer
#define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer
#define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer
#define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer
/* Byte Mask Definitions */
#define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer
#define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer
#define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer
#define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer
#define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
#define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
#define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
#define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
/*@}*/ /* end of group Legacy_Constants */
/******************************************************************************/
/* Peripheral header files */
/******************************************************************************/
#include "nu_sys.h"
#include "nu_clk.h"
#include "nu_kpi.h"
#include "nu_rng.h"
#include "nu_keystore.h"
#include "nu_acmp.h"
#include "nu_dac.h"
#include "nu_uart.h"
#include "nu_usci_spi.h"
#include "nu_gpio.h"
#include "nu_ccap.h"
#include "nu_ecap.h"
#include "nu_hbi.h"
#include "nu_eqei.h"
#include "nu_timer.h"
#include "nu_timer_pwm.h"
#include "nu_pdma.h"
#include "nu_crypto.h"
#include "nu_trng.h"
#include "nu_fmc.h"
#include "nu_spim.h"
#include "nu_i2c.h"
#include "nu_i2s.h"
#include "nu_epwm.h"
#include "nu_eadc.h"
#include "nu_bpwm.h"
#include "nu_wdt.h"
#include "nu_wwdt.h"
#include "nu_crc.h"
#include "nu_ebi.h"
#include "nu_usci_i2c.h"
#include "nu_scuart.h"
#include "nu_sc.h"
#include "nu_spi.h"
#include "nu_qspi.h"
#include "nu_canfd.h"
#include "nu_rtc.h"
#include "nu_usci_uart.h"
#include "nu_sdh.h"
#include "nu_usbd.h"
#include "nu_hsusbd.h"
#include "nu_otg.h"
#include "nu_hsotg.h"
#include "nu_psio.h"
#include "nu_bmc.h"
#ifdef __cplusplus
}
#endif
#endif /* __M460_H__ */

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/**************************************************************************//**
* @file opa_reg.h
* @version V1.00
* @brief OPA register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __OPA_REG_H__
#define __OPA_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup OPA OP Amplifier(OPA)
Memory Mapped Structure for OPA Controller
@{ */
typedef struct
{
/**
* @var OPA_T::CTL
* Offset: 0x00 OP Amplifier Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OPEN0 |OP Amplifier 0 Enable Bit
* | | |0 = OP amplifier0 Disabled.
* | | |1 = OP amplifier0 Enabled.
* | | |Note: OP Amplifier 0 output needs wait stable 20u03BCs after OPEN0 is set.
* |[1] |OPEN1 |OP Amplifier 1 Enable Bit
* | | |0 = OP amplifier1 Disabled.
* | | |1 = OP amplifier1 Enabled.
* | | |Note: OP Amplifier 1 output needs wait stable 20u03BCs after OPEN1 is set.
* |[2] |OPEN2 |OP Amplifier 2 Enable Bit
* | | |0 = OP amplifier2 Disabled.
* | | |1 = OP amplifier2 Enabled.
* | | |Note: OP Amplifier 2 output needs wait stable 20u03BCs after OPEN2 is set.
* |[4] |OPDOEN0 |OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit
* | | |0 = OP amplifier0 Schmitt Trigger non-invert buffer Disabled.
* | | |1 = OP amplifier0 Schmitt Trigger non-invert buffer Enabled.
* |[5] |OPDOEN1 |OP Amplifier 1 Schmitt Trigger Non-inverting Buffer Enable Bit
* | | |0 = OP amplifier1 Schmitt Trigger non-invert buffer Disabled.
* | | |1 = OP amplifier1 Schmitt Trigger non-invert buffer Enabled.
* |[6] |OPDOEN2 |OP Amplifier 2 Schmitt Trigger Non-inverting Buffer Enable Bit
* | | |0 = OP amplifier2 Schmitt Trigger non-invert buffer Disabled.
* | | |1 = OP amplifier2 Schmitt Trigger non-invert buffer Enabled.
* |[8] |OPDOIEN0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit
* | | |0 = OP Amplifier 0 digital output interrupt function Disabled.
* | | |1 = OP Amplifier 0 digital output interrupt function Enabled.
* | | |The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN0 is set to 1, a comparator interrupt request is generated.
* |[9] |OPDOIEN1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit
* | | |0 = OP Amplifier 1 digital output interrupt function Disabled.
* | | |1 = OP Amplifier 1 digital output interrupt function Enabled.
* | | |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN1 is set to 1, a comparator interrupt request is generated.
* |[10] |OPDOIEN2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Enable Bit
* | | |0 = OP Amplifier 2 digital output interrupt function Disabled.
* | | |1 = OP Amplifier 2 digital output interrupt function Enabled.
* | | |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN2 is set to 1, a comparator interrupt request is generated.
* @var OPA_T::STATUS
* Offset: 0x04 OP Amplifier Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OPDO0 |OP Amplifier 0 Digital Output
* | | |Synchronized to the APB clock to allow reading by software
* | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN0 = 0)
* |[1] |OPDO1 |OP Amplifier 1 Digital Output
* | | |Synchronized to the APB clock to allow reading by software
* | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN1 = 0)
* |[2] |OPDO2 |OP Amplifier 2 Digital Output
* | | |Synchronized to the APB clock to allow reading by software
* | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN2 = 0)
* |[4] |OPDOIF0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag
* | | |OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state
* | | |This bit is cleared by writing 1 to it.
* |[5] |OPDOIF1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag
* | | |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt Trigger non-inverting buffer digital output changes state
* | | |This bit is cleared by writing 1 to it.
* |[6] |OPDOIF2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Flag
* | | |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state
* | | |This bit is cleared by writing 1 to it.
* @var OPA_T::CALCTL
* Offset: 0x08 OP Amplifier Calibration Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CALTRG0 |OP Amplifier 0 Calibration Trigger Bit
* | | |0 = Stop, hardware auto clear.
* | | |1 = Start. Note: Before enable this bit, it should set OPEN0 in advance.
* |[1] |CALTRG1 |OP Amplifier 1 Calibration Trigger Bit
* | | |0 = Stop, hardware auto clear.
* | | |1 = Start. Note: Before enable this bit, it should set OPEN1 in advance.
* |[2] |CALTRG2 |OP Amplifier 2 Calibration Trigger Bit
* | | |0 = Stop, hardware auto clear.
* | | |1 = Start. Note: Before enable this bit, it should set OPEN2 in advance.
* |[16] |CALRVS0 |OPA0 Calibration Reference Voltage Selection
* | | |0 = VREF is AVDD.
* | | |1 = VREF from high vcm to low vcm.
* |[17] |CALRVS1 |OPA1 Calibration Reference Voltage Selection
* | | |0 = VREF is AVDD.
* | | |1 = VREF from high vcm to low vcm.
* |[18] |CALRVS2 |OPA2 Calibration Reference Voltage Selection
* | | |0 = VREF is AVDD.
* | | |1 = VREF from high vcm to low vcm.
* @var OPA_T::CALST
* Offset: 0x0C OP Amplifier Calibration Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DONE0 |OP Amplifier 0 Calibration Done Status
* | | |0 = Calibrating.
* | | |1 = Calibration Done.
* |[1] |CALNS0 |OP Amplifier 0 Calibration Result Status for NMOS
* | | |0 = Pass.
* | | |1 = Fail.
* |[2] |CALPS0 |OP Amplifier 0 Calibration Result Status for PMOS
* | | |0 = Pass.
* | | |1 = Fail.
* |[4] |DONE1 |OP Amplifier 1 Calibration Done Status
* | | |0 = Calibrating.
* | | |1 = Calibration Done.
* |[5] |CALNS1 |OP Amplifier 1 Calibration Result Status for NMOS
* | | |0 = Pass.
* | | |1 = Fail.
* |[6] |CALPS1 |OP Amplifier 1 Calibration Result Status for PMOS
* | | |0 = Pass.
* | | |1 = Fail.
* |[8] |DONE2 |OP Amplifier 2 Calibration Done Status
* | | |0 = Calibrating.
* | | |1 = Calibration Done.
* |[9] |CALNS2 |OP Amplifier 2 Calibration Result Status for NMOS
* | | |0 = Pass.
* | | |1 = Fail.
* |[10] |CALPS2 |OP Amplifier 2 Calibration Result Status for PMOS
* | | |0 = Pass.
* | | |1 = Fail.
*/
__IO uint32_t CTL; /*!< [0x0000] OP Amplifier Control Register */
__IO uint32_t STATUS; /*!< [0x0004] OP Amplifier Status Register */
__IO uint32_t CALCTL; /*!< [0x0008] OP Amplifier Calibration Control Register */
__I uint32_t CALST; /*!< [0x000c] OP Amplifier Calibration Status Register */
} OPA_T;
/**
@addtogroup OPA_CONST OPA Bit Field Definition
Constant Definitions for OPA Controller
@{ */
#define OPA_CTL_OPEN0_Pos (0) /*!< OPA_T::CTL: OPEN0 Position */
#define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) /*!< OPA_T::CTL: OPEN0 Mask */
#define OPA_CTL_OPEN1_Pos (1) /*!< OPA_T::CTL: OPEN1 Position */
#define OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos) /*!< OPA_T::CTL: OPEN1 Mask */
#define OPA_CTL_OPEN2_Pos (2) /*!< OPA_T::CTL: OPEN2 Position */
#define OPA_CTL_OPEN2_Msk (0x1ul << OPA_CTL_OPEN2_Pos) /*!< OPA_T::CTL: OPEN2 Mask */
#define OPA_CTL_OPDOEN0_Pos (4) /*!< OPA_T::CTL: OPDOEN0 Position */
#define OPA_CTL_OPDOEN0_Msk (0x1ul << OPA_CTL_OPDOEN0_Pos) /*!< OPA_T::CTL: OPDOEN0 Mask */
#define OPA_CTL_OPDOEN1_Pos (5) /*!< OPA_T::CTL: OPDOEN1 Position */
#define OPA_CTL_OPDOEN1_Msk (0x1ul << OPA_CTL_OPDOEN1_Pos) /*!< OPA_T::CTL: OPDOEN1 Mask */
#define OPA_CTL_OPDOEN2_Pos (6) /*!< OPA_T::CTL: OPDOEN2 Position */
#define OPA_CTL_OPDOEN2_Msk (0x1ul << OPA_CTL_OPDOEN2_Pos) /*!< OPA_T::CTL: OPDOEN2 Mask */
#define OPA_CTL_OPDOIEN0_Pos (8) /*!< OPA_T::CTL: OPDOIEN0 Position */
#define OPA_CTL_OPDOIEN0_Msk (0x1ul << OPA_CTL_OPDOIEN0_Pos) /*!< OPA_T::CTL: OPDOIEN0 Mask */
#define OPA_CTL_OPDOIEN1_Pos (9) /*!< OPA_T::CTL: OPDOIEN1 Position */
#define OPA_CTL_OPDOIEN1_Msk (0x1ul << OPA_CTL_OPDOIEN1_Pos) /*!< OPA_T::CTL: OPDOIEN1 Mask */
#define OPA_CTL_OPDOIEN2_Pos (10) /*!< OPA_T::CTL: OPDOIEN2 Position */
#define OPA_CTL_OPDOIEN2_Msk (0x1ul << OPA_CTL_OPDOIEN2_Pos) /*!< OPA_T::CTL: OPDOIEN2 Mask */
#define OPA_STATUS_OPDO0_Pos (0) /*!< OPA_T::STATUS: OPDO0 Position */
#define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) /*!< OPA_T::STATUS: OPDO0 Mask */
#define OPA_STATUS_OPDO1_Pos (1) /*!< OPA_T::STATUS: OPDO1 Position */
#define OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos) /*!< OPA_T::STATUS: OPDO1 Mask */
#define OPA_STATUS_OPDO2_Pos (2) /*!< OPA_T::STATUS: OPDO2 Position */
#define OPA_STATUS_OPDO2_Msk (0x1ul << OPA_STATUS_OPDO2_Pos) /*!< OPA_T::STATUS: OPDO2 Mask */
#define OPA_STATUS_OPDOIF0_Pos (4) /*!< OPA_T::STATUS: OPDOIF0 Position */
#define OPA_STATUS_OPDOIF0_Msk (0x1ul << OPA_STATUS_OPDOIF0_Pos) /*!< OPA_T::STATUS: OPDOIF0 Mask */
#define OPA_STATUS_OPDOIF1_Pos (5) /*!< OPA_T::STATUS: OPDOIF1 Position */
#define OPA_STATUS_OPDOIF1_Msk (0x1ul << OPA_STATUS_OPDOIF1_Pos) /*!< OPA_T::STATUS: OPDOIF1 Mask */
#define OPA_STATUS_OPDOIF2_Pos (6) /*!< OPA_T::STATUS: OPDOIF2 Position */
#define OPA_STATUS_OPDOIF2_Msk (0x1ul << OPA_STATUS_OPDOIF2_Pos) /*!< OPA_T::STATUS: OPDOIF2 Mask */
#define OPA_CALCTL_CALTRG0_Pos (0) /*!< OPA_T::CALCTL: CALTRG0 Position */
#define OPA_CALCTL_CALTRG0_Msk (0x1ul << OPA_CALCTL_CALTRG0_Pos) /*!< OPA_T::CALCTL: CALTRG0 Mask */
#define OPA_CALCTL_CALTRG1_Pos (1) /*!< OPA_T::CALCTL: CALTRG1 Position */
#define OPA_CALCTL_CALTRG1_Msk (0x1ul << OPA_CALCTL_CALTRG1_Pos) /*!< OPA_T::CALCTL: CALTRG1 Mask */
#define OPA_CALCTL_CALTRG2_Pos (2) /*!< OPA_T::CALCTL: CALTRG2 Position */
#define OPA_CALCTL_CALTRG2_Msk (0x1ul << OPA_CALCTL_CALTRG2_Pos) /*!< OPA_T::CALCTL: CALTRG2 Mask */
#define OPA_CALCTL_CALCLK0_Pos (4) /*!< OPA_T::CALCTL: CALCLK0 Position */
#define OPA_CALCTL_CALCLK0_Msk (0x3ul << OPA_CALCTL_CALCLK0_Pos) /*!< OPA_T::CALCTL: CALCLK0 Mask */
#define OPA_CALCTL_CALCLK1_Pos (6) /*!< OPA_T::CALCTL: CALCLK1 Position */
#define OPA_CALCTL_CALCLK1_Msk (0x3ul << OPA_CALCTL_CALCLK1_Pos) /*!< OPA_T::CALCTL: CALCLK1 Mask */
#define OPA_CALCTL_CALCLK2_Pos (8) /*!< OPA_T::CALCTL: CALCLK2 Position */
#define OPA_CALCTL_CALCLK2_Msk (0x3ul << OPA_CALCTL_CALCLK2_Pos) /*!< OPA_T::CALCTL: CALCLK2 Mask */
#define OPA_CALCTL_CALRVS0_Pos (16) /*!< OPA_T::CALCTL: CALRVS0 Position */
#define OPA_CALCTL_CALRVS0_Msk (0x1ul << OPA_CALCTL_CALRVS0_Pos) /*!< OPA_T::CALCTL: CALRVS0 Mask */
#define OPA_CALCTL_CALRVS1_Pos (17) /*!< OPA_T::CALCTL: CALRVS1 Position */
#define OPA_CALCTL_CALRVS1_Msk (0x1ul << OPA_CALCTL_CALRVS1_Pos) /*!< OPA_T::CALCTL: CALRVS1 Mask */
#define OPA_CALCTL_CALRVS2_Pos (18) /*!< OPA_T::CALCTL: CALRVS2 Position */
#define OPA_CALCTL_CALRVS2_Msk (0x1ul << OPA_CALCTL_CALRVS2_Pos) /*!< OPA_T::CALCTL: CALRVS2 Mask */
#define OPA_CALST_DONE0_Pos (0) /*!< OPA_T::CALST: DONE0 Position */
#define OPA_CALST_DONE0_Msk (0x1ul << OPA_CALST_DONE0_Pos) /*!< OPA_T::CALST: DONE0 Mask */
#define OPA_CALST_CALNS0_Pos (1) /*!< OPA_T::CALST: CALNS0 Position */
#define OPA_CALST_CALNS0_Msk (0x1ul << OPA_CALST_CALNS0_Pos) /*!< OPA_T::CALST: CALNS0 Mask */
#define OPA_CALST_CALPS0_Pos (2) /*!< OPA_T::CALST: CALPS0 Position */
#define OPA_CALST_CALPS0_Msk (0x1ul << OPA_CALST_CALPS0_Pos) /*!< OPA_T::CALST: CALPS0 Mask */
#define OPA_CALST_DONE1_Pos (4) /*!< OPA_T::CALST: DONE1 Position */
#define OPA_CALST_DONE1_Msk (0x1ul << OPA_CALST_DONE1_Pos) /*!< OPA_T::CALST: DONE1 Mask */
#define OPA_CALST_CALNS1_Pos (5) /*!< OPA_T::CALST: CALNS1 Position */
#define OPA_CALST_CALNS1_Msk (0x1ul << OPA_CALST_CALNS1_Pos) /*!< OPA_T::CALST: CALNS1 Mask */
#define OPA_CALST_CALPS1_Pos (6) /*!< OPA_T::CALST: CALPS1 Position */
#define OPA_CALST_CALPS1_Msk (0x1ul << OPA_CALST_CALPS1_Pos) /*!< OPA_T::CALST: CALPS1 Mask */
#define OPA_CALST_DONE2_Pos (8) /*!< OPA_T::CALST: DONE2 Position */
#define OPA_CALST_DONE2_Msk (0x1ul << OPA_CALST_DONE2_Pos) /*!< OPA_T::CALST: DONE2 Mask */
#define OPA_CALST_CALNS2_Pos (9) /*!< OPA_T::CALST: CALNS2 Position */
#define OPA_CALST_CALNS2_Msk (0x1ul << OPA_CALST_CALNS2_Pos) /*!< OPA_T::CALST: CALNS2 Mask */
#define OPA_CALST_CALPS2_Pos (10) /*!< OPA_T::CALST: CALPS2 Position */
#define OPA_CALST_CALPS2_Msk (0x1ul << OPA_CALST_CALPS2_Pos) /*!< OPA_T::CALST: CALPS2 Mask */
/**@}*/ /* OPA_CONST */
/**@}*/ /* end of OPA register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __OPA_REG_H__ */

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/**************************************************************************//**
* @file otg_reg.h
* @version V3.00
* @brief OTG register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __OTG_REG_H__
#define __OTG_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup OTG USB On-The-Go Controller(OTG)
Memory Mapped Structure for OTG Controller
@{ */
typedef struct
{
/**
* @var OTG_T::CTL
* Offset: 0x00 OTG Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VBUSDROP |Drop VBUS Control
* | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS
* | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
* | | |0 = Not drop the VBUS.
* | | |1 = Drop the VBUS.
* |[1] |BUSREQ |OTG Bus Request
* | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection
* | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power
* | | |This bit will be cleared when A-device goes to A_wait_vfall state
* | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
* | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol
* | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification)
* | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
* | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
* | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
* |[2] |HNPREQEN |OTG HNP Request Enable Bit
* | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral
* | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state
* | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host
* | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
* | | |0 = HNP request Disabled.
* | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
* | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
* |[4] |OTGEN |OTG Function Enable Bit
* | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device
* | | |When USB frame not configured as OTG device, this bit is must be low.
* | | |0= OTG function Disabled.
* | | |1 = OTG function Enabled.
* |[5] |WKEN |OTG ID Pin Wake-up Enable Bit
* | | |0 = OTG ID pin status change wake-up function Disabled.
* | | |1 = OTG ID pin status change wake-up function Enabled.
* @var OTG_T::PHYCTL
* Offset: 0x04 OTG PHY Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OTGPHYEN |OTG PHY Enable
* | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function
* | | |If device is not configured as OTG-device nor ID-dependent , this bit is "don't care".
* | | |0 = OTG PHY Disabled.
* | | |1 = OTG PHY Enabled.
* |[1] |IDDETEN |ID Detection Enable Bit
* | | |0 = Detect ID pin status Disabled.
* | | |1 = Detect ID pin status Enabled.
* |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity
* | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need
* | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
* | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component
* | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
* | | |0 = The off-chip USB VBUS power switch enable is active high.
* | | |1 = The off-chip USB VBUS power switch enable is active low.
* |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity
* | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component
* | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch
* | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
* | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.
* | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.
* @var OTG_T::INTEN
* Offset: 0x08 OTG Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[1] |VBEIEN |VBUS Error Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
* |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Going to idle state means going to a_idle or b_idle state
* | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
* |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit
* | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
* | | |0 = This device as a peripheral interrupt Disabled.
* | | |1 = This device as a peripheral interrupt Enabled.
* |[7] |HOSTIEN |Act As Host Interrupt Enable Bit
* | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
* | | |0 = This device as a host interrupt Disabled.
* | | |1 = This device as a host interrupt Enabled.
* |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit
* | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* @var OTG_T::INTSTS
* Offset: 0x0C OTG Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ROLECHGIF |OTG Role Change Interrupt Status
* | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
* | | |0 = OTG device role not changed.
* | | |1 = OTG device role changed.
* | | |Note: Write 1 to clear this flag.
* |[1] |VBEIF |VBUS Error Interrupt Status
* | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
* | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
* | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
* | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
* |[2] |SRPFIF |SRP Fail Interrupt Status
* | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification
* | | |This flag is set when the OTG B-device does not get VBUS high after this interval.
* | | |0 = OTG B-device gets VBUS high before this interval.
* | | |1 = OTG B-device does not get VBUS high before this interval.
* | | |Note: Write 1 to clear this flag.
* |[3] |HNPFIF |HNP Fail Interrupt Status
* | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
* | | |0 = A-device connects to B-device before specified interval expires.
* | | |1 = A-device does not connect to B-device before specified interval expires.
* | | |Note: Write 1 to clear this flag.
* |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status
* | | |Flag is set if the OTG device transfers from non-idle state to idle state
* | | |The OTG device will be neither a host nor a peripheral.
* | | |0 = OTG device does not go back to idle state (a_idle or b_idle).
* | | |1 = OTG device goes back to idle state(a_idle or b_idle).
* | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.
* | | |Note 2: Write 1 to clear this flag.
* |[5] |IDCHGIF |ID State Change Interrupt Status
* | | |0 = IDSTS (OTG_STATUS[1]) not toggled.
* | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
* | | |Note: Write 1 to clear this flag.
* |[6] |PDEVIF |Act As Peripheral Interrupt Status
* | | |0= This device does not act as a peripheral.
* | | |1 = This device acts as a peripheral.
* | | |Note: Write 1 to clear this flag.
* |[7] |HOSTIF |Act As Host Interrupt Status
* | | |0= This device does not act as a host.
* | | |1 = This device acts as a host.
* | | |Note: Write 1 to clear this flag.
* |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status
* | | |0 = BVLD (OTG_STATUS[3]) is not toggled.
* | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
* | | |Note: Write 1 to clear this status.
* |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status
* | | |0 = AVLD (OTG_STATUS[4]) not toggled.
* | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
* | | |Note: Write 1 to clear this status.
* |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status
* | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
* | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
* | | |Note: Write 1 to clear this status.
* |[11] |SECHGIF |SESSEND State Change Interrupt Status
* | | |0 = SESSEND (OTG_STATUS[2]) not toggled.
* | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
* | | |Note: Write 1 to clear this flag.
* |[13] |SRPDETIF |SRP Detected Interrupt Status
* | | |0 = SRP not detected.
* | | |1 = SRP detected.
* | | |Note: Write 1 to clear this status.
* @var OTG_T::STATUS
* Offset: 0x10 OTG Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OVERCUR |over Current Condition
* | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
* | | |0 = OTG A-device drives VBUS successfully.
* | | |1 = OTG A-device cannot drives VBUS high in this interval.
* |[1] |IDSTS |USB_ID Pin State of Mini-b/Micro-plug
* | | |0 = Mini-A/Micro-A plug is attached.
* | | |1 = Mini-B/Micro-B plug is attached.
* |[2] |SESSEND |Session End Status
* | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1
* | | |Session end means no meaningful power on VBUS.
* | | |0 = Session is not end.
* | | |1 = Session is end.
* |[3] |BVLD |B-device Session Valid Status
* | | |0 = B-device session is not valid.
* | | |1 = B-device session is valid.
* |[4] |AVLD |A-device Session Valid Status
* | | |0 = A-device session is not valid.
* | | |1 = A-device session is valid.
* |[5] |VBUSVLD |VBUS Valid Status
* | | |When VBUS is larger than 4.7V, this bit will be set to 1.
* | | |0 = VBUS is not valid.
* | | |1 = VBUS is valid.
* |[6] |ASPERI |As Peripheral Status
* | | |When OTG as peripheral, this bit is set.
* | | |0: OTG not as peripheral
* | | |1: OTG as peripheral
* |[7] |ASHOST |As Host Status
* | | |When OTG as Host, this bit is set.
* | | |0: OTG not as Host
* | | |1: OTG as Host
*/
__IO uint32_t CTL; /*!< [0x0000] OTG Control Register */
__IO uint32_t PHYCTL; /*!< [0x0004] OTG PHY Control Register */
__IO uint32_t INTEN; /*!< [0x0008] OTG Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x000c] OTG Interrupt Status Register */
__I uint32_t STATUS; /*!< [0x0010] OTG Status Register */
} OTG_T;
/**
@addtogroup OTG_CONST OTG Bit Field Definition
Constant Definitions for OTG Controller
@{ */
#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */
#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */
#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */
#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */
#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */
#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */
#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */
#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */
#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */
#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */
#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */
#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */
#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */
#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */
#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */
#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */
#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */
#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */
#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */
#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */
#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */
#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */
#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */
#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */
#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */
#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */
#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */
#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */
#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */
#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */
#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */
#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */
#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */
#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */
#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */
#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */
#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */
#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */
#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */
#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */
#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */
#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */
#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */
#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */
#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */
#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */
#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */
#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */
#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */
#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */
#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */
#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */
#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */
#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */
#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */
#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */
#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */
#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */
#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */
#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */
#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */
#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */
#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */
#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */
#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */
#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */
#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */
#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */
#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */
#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */
#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */
#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */
#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */
#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */
#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */
#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */
#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */
#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */
#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */
#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */
#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */
#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */
#define OTG_STATUS_ASPERI_Pos (6) /*!< OTG_T::STATUS: ASPERI Position */
#define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) /*!< OTG_T::STATUS: ASPERI Mask */
#define OTG_STATUS_ASHOST_Pos (7) /*!< OTG_T::STATUS: ASHOST Position */
#define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) /*!< OTG_T::STATUS: ASHOST Mask */
/**@}*/ /* OTG_CONST */
/**@}*/ /* end of OTG register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __OTG_REG_H__ */

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/**************************************************************************//**
* @file qspi_reg.h
* @version V3.00
* @brief QSPI register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __QSPI_REG_H__
#define __QSPI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup QSPI Serial Peripheral Interface Controller(QSPI)
Memory Mapped Structure for QSPI Controller
@{ */
typedef struct
{
/**
* @var QSPI_T::CTL
* Offset: 0x00 QSPI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SPIEN |QSPI Transfer Control Enable Bit
* | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
* | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
* | | |0 = Transfer control Disabled.
* | | |1 = Transfer control Enabled.
* | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0.
* |[1] |RXNEG |Receive on Negative Edge
* | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock.
* | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock.
* |[2] |TXNEG |Transmit on Negative Edge
* | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock.
* | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock.
* |[3] |CLKPOL |Clock Polarity
* | | |0 = QSPI bus clock is idle low.
* | | |1 = QSPI bus clock is idle high.
* |[7:4] |SUSPITV |Suspend Interval (Master Only)
* | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
* | | |The default value is 0x3
* | | |The period of the suspend interval is obtained according to the following equation.
* | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle
* | | |Example:
* | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle.
* | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle.
* | | |.....
* | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle.
* | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle.
* |[12:8] |DWIDTH |Data Width
* | | |This field specifies how many bits can be transmitted / received in one transaction
* | | |The minimum bit length is 8 bits and can up to 32 bits.
* | | |DWIDTH = 0x08 .... 8 bits.
* | | |DWIDTH = 0x09 .... 9 bits.
* | | |.....
* | | |DWIDTH = 0x1F .... 31 bits.
* | | |DWIDTH = 0x00 .... 32 bits.
* |[13] |LSB |Send LSB First
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX).
* |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit
* | | |This bit is used to select full-duplex or half-duplex for QSPI transfer
* | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
* | | |0 = QSPI operates in full-duplex transfer.
* | | |1 = QSPI operates in half-duplex transfer.
* |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only)
* | | |This bit field is only available in Master mode
* | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status.
* | | |0 = Receive-only mode Disabled.
* | | |1 = Receive-only mode Enabled.
* |[16] |TWOBIT |2-bit Transfer Mode Enable Bit
* | | |0 = 2-Bit Transfer mode Disabled.
* | | |1 = 2-Bit Transfer mode Enabled.
* | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data
* | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
* | | |0 = QSPI unit transfer interrupt Disabled.
* | | |1 = QSPI unit transfer interrupt Enabled.
* |[18] |SLAVE |Slave Mode Control
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[19] |REORDER |Byte Reorder Function Enable Bit
* | | |0 = Byte Reorder function Disabled.
* | | |1 = Byte Reorder function Enabled
* | | |A byte suspend interval will be inserted among each byte
* | | |The period of the byte suspend interval depends on the setting of SUSPITV.
* | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
* |[20] |DATDIR |Data Port Direction Control
* | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
* | | |0 = QSPI data is input direction.
* | | |1 = QSPI data is output direction.
* |[21] |DUALIOEN |Dual I/O Mode Enable Bit
* | | |0 = Dual I/O mode Disabled.
* | | |1 = Dual I/O mode Enabled.
* |[22] |QUADIOEN |Quad I/O Mode Enable Bit
* | | |0 = Quad I/O mode Disabled.
* | | |1 = Quad I/O mode Enabled.
* |[23] |TXDTREN |Transmit Double Transfer Rate Mode Enable Bit
* | | |0 = TX DTR mode Disabled.
* | | |1 = TX DTR mode Enabled.
* | | |Note: QSPI Master mode supports TXDTR (Transmit Double Transfer Rate) mode, and QSPI Slave mode does not support this mode.
* @var QSPI_T::CLKDIV
* Offset: 0x04 QSPI Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |DIVIDER |Clock Divider
* | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master
* | | |The frequency is obtained according to the following equation.
* | | |where
* | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
* @var QSPI_T::SSCTL
* Offset: 0x08 QSPI Slave Select Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SS |Slave Selection Control (Master Only)
* | | |If AUTOSS bit is cleared to 0,
* | | |0 = Set the QSPIx_SS line to inactive state.
* | | |1 = Set the QSPIx_SS line to active state.
* | | |If the AUTOSS bit is set to 1,
* | | |0 = Keep the QSPIx_SS line at inactive state.
* | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
* | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]).
* |[2] |SSACTPOL |Slave Selection Active Polarity
* | | |This bit defines the active polarity of slave selection signal (QSPIx_SS).
* | | |0 = The slave selection signal QSPIx_SS is active low.
* | | |1 = The slave selection signal QSPIx_SS is active high.
* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
* | | |0 = Automatic slave selection function Disabled
* | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]).
* | | |1 = Automatic slave selection function Enabled.
* |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit
* | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins.
* | | |0 = 4-wire bi-direction interface.
* | | |1 = 3-wire bi-direction interface.
* |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit
* | | |0 = Slave mode time-out interrupt Disabled.
* | | |1 = Slave mode time-out interrupt Enabled.
* |[6] |SLVTORST |Slave Mode Time-out Reset Control
* | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
* | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
* |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
* | | |0 = Slave mode bit count error interrupt Disabled.
* | | |1 = Slave mode bit count error interrupt Enabled.
* |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
* | | |0 = Slave mode TX under run interrupt Disabled.
* | | |1 = Slave mode TX under run interrupt Enabled.
* |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
* | | |0 = Slave select active interrupt Disabled.
* | | |1 = Slave select active interrupt Enabled.
* |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
* | | |0 = Slave select inactive interrupt Disabled.
* | | |1 = Slave select inactive interrupt Enabled.
* |[31:16] |SLVTOCNT |Slave Mode Time-out Period
* | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active
* | | |The clock source of the time-out counter is Slave peripheral clock
* | | |If the value is 0, it indicates the slave mode time-out function is disabled.
* @var QSPI_T::PDMACTL
* Offset: 0x0C QSPI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
* | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
* |[1] |RXPDMAEN |Receive PDMA Enable Bit
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0.
* @var QSPI_T::FIFOCTL
* Offset: 0x10 QSPI FIFO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset receive FIFO pointer and receive circuit
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
* |[1] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset transmit FIFO pointer and transmit circuit
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
* | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state.
* |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
* | | |0 = RX FIFO threshold interrupt Disabled.
* | | |1 = RX FIFO threshold interrupt Enabled.
* |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
* | | |0 = TX FIFO threshold interrupt Disabled.
* | | |1 = TX FIFO threshold interrupt Enabled.
* |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit
* | | |0 = Receive time-out interrupt Disabled.
* | | |1 = Receive time-out interrupt Enabled.
* |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
* | | |0 = Receive FIFO overrun interrupt Disabled.
* | | |1 = Receive FIFO overrun interrupt Enabled.
* |[6] |TXUFPOL |TX Underflow Data Polarity
* | | |0 = The QSPI data out is keep 0 if there is TX underflow event in Slave mode.
* | | |1 = The QSPI data out is keep 1 if there is TX underflow event in Slave mode.
* | | |Note:
* | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
* | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
* | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame.
* |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
* | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1
* | | |This bit is used to enable the TX underflow interrupt.
* | | |0 = Slave TX underflow interrupt Disabled.
* | | |1 = Slave TX underflow interrupt Enabled.
* |[8] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear receive FIFO pointer
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The RX shift register will not be cleared.
* |[9] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear transmit FIFO pointer
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The TX shift register will not be cleared.
* |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error
* | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in QSPI Slave mode.
* | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in QSPI Slave mode
* | | |User can read SLVBENUM (QSPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened.
* | | |Note: Slave mode only.
* |[26:24] |RXTH |Receive FIFO Threshold
* | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
* |[30:28] |TXTH |Transmit FIFO Threshold
* | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
* @var QSPI_T::STATUS
* Offset: 0x14 QSPI Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Busy Status (Read Only)
* | | |0 = QSPI controller is in idle state.
* | | |1 = QSPI controller is in busy state.
* | | |The following listing are the bus busy conditions:
* | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0.
* | | |b
* | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
* | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1.
* | | |d
* | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active.
* | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
* |[1] |UNITIF |Unit Transfer Interrupt Flag
* | | |0 = No transaction has been finished since this bit was cleared to 0.
* | | |1 = QSPI controller has finished one unit transfer.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[2] |SSACTIF |Slave Select Active Interrupt Flag
* | | |0 = Slave select active interrupt was cleared or not occurred.
* | | |1 = Slave select active interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
* | | |0 = Slave select inactive interrupt was cleared or not occurred.
* | | |1 = Slave select inactive interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
* | | |0 = The slave select line status is 0.
* | | |1 = The slave select line status is 1.
* | | |Note: This bit is only available in Slave mode
* | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status.
* |[5] |SLVTOIF |Slave Time-out Interrupt Flag
* | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in QSPI controller logic will be started
* | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
* | | |0 = Slave time-out is not active.
* | | |1 = Slave time-out is active.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
* | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
* | | |0 = No Slave mode bit count error event.
* | | |1 = Slave mode bit count error event occurs.
* | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
* | | |This bit will be cleared by writing 1 to it.
* |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
* | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
* | | |0 = No Slave TX under run event.
* | | |1 = Slave TX under run event occurs.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |0 = No FIFO is overrun.
* | | |1 = Receive FIFO is overrun.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |SPIENSTS |QSPI Enable Status (Read Only)
* | | |0 = The QSPI controller is disabled.
* | | |1 = The QSPI controller is enabled.
* | | |Note: The QSPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* |[19] |TXUFIF |TX Underflow Interrupt Flag
* | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
* | | |0 = No effect.
* | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
* | | |Note 1: This bit will be cleared by writing 1 to it.
* | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
* @var QSPI_T::STATUS2
* Offset: 0x18 QSPI Status2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX Data
* | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (QSPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in QSPI Slave mode
* | | |This status register will be fixed to 0x0 when SLVBERX (QSPIx_FIFOCTL[10]) is disabled.
* | | |Note 1: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (QSPIx_STATUS[6]).
* | | |Note 2: Slave mode only.
* @var QSPI_T::TX
* Offset: 0x20 QSPI Data Transmit Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TX |Data Transmit Register
* | | |The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers
* | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in SPI mode.
* | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted
* | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer.
* | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
* @var QSPI_T::RX
* Offset: 0x30 QSPI Data Receive Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RX |Data Receive Register
* | | |There are 8-level FIFO buffers in this controller
* | | |The data receive register holds the data received from QSPI data input pin
* | | |This is a read only register.
*/
__IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */
__IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */
__IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */
__IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */
__IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */
__IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */
__I uint32_t STATUS2; /*!< [0x0018] QSPI Status2 Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[3];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */
} QSPI_T;
/**
@addtogroup QSPI_CONST QSPI Bit Field Definition
Constant Definitions for QSPI Controller
@{ */
#define QSPI_CTL_SPIEN_Pos (0) /*!< QSPI_T::CTL: SPIEN Position */
#define QSPI_CTL_SPIEN_Msk (0x1ul << QSPI_CTL_SPIEN_Pos) /*!< QSPI_T::CTL: SPIEN Mask */
#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */
#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */
#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */
#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */
#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */
#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */
#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */
#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */
#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */
#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */
#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */
#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */
#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */
#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */
#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */
#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */
#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */
#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */
#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */
#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */
#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */
#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */
#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */
#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */
#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */
#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */
#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */
#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */
#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */
#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */
#define QSPI_CTL_TXDTREN_Pos (23) /*!< QSPI_T::CTL: TXDTREN Position */
#define QSPI_CTL_TXDTREN_Msk (0x1ul << QSPI_CTL_TXDTREN_Pos) /*!< QSPI_T::CTL: TXDTREN Mask */
#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */
#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */
#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */
#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */
#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */
#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */
#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */
#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */
#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */
#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */
#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */
#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */
#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */
#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */
#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */
#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */
#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */
#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */
#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */
#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */
#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */
#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */
#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */
#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */
#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */
#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */
#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */
#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */
#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */
#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */
#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */
#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */
#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */
#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */
#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */
#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */
#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */
#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */
#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */
#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */
#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */
#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */
#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */
#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */
#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */
#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */
#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */
#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */
#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */
#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */
#define QSPI_FIFOCTL_SLVBERX_Pos (10) /*!< QSPI_T::FIFOCTL: SLVBERX Position */
#define QSPI_FIFOCTL_SLVBERX_Msk (0x1ul << QSPI_FIFOCTL_SLVBERX_Pos) /*!< QSPI_T::FIFOCTL: SLVBERX Mask */
#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */
#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */
#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */
#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */
#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */
#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */
#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */
#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */
#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */
#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */
#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */
#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */
#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */
#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */
#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */
#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */
#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */
#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */
#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */
#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */
#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */
#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */
#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */
#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */
#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */
#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */
#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */
#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */
#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */
#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */
#define QSPI_STATUS_SPIENSTS_Pos (15) /*!< QSPI_T::STATUS: SPIENSTS Position */
#define QSPI_STATUS_SPIENSTS_Msk (0x1ul << QSPI_STATUS_SPIENSTS_Pos) /*!< QSPI_T::STATUS: SPIENSTS Mask */
#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */
#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */
#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */
#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */
#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */
#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */
#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */
#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */
#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */
#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */
#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */
#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */
#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */
#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */
#define QSPI_STATUS2_SLVBENUM_Pos (24) /*!< QSPI_T::STATUS2: SLVBENUM Position */
#define QSPI_STATUS2_SLVBENUM_Msk (0x3ful << QSPI_STATUS2_SLVBENUM_Pos) /*!< QSPI_T::STATUS2: SLVBENUM Mask */
#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */
#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */
#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */
#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */
/**@}*/ /* QSPI_CONST */
/**@}*/ /* end of QSPI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __QSPI_REG_H__ */

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/**************************************************************************//**
* @file sdh_reg.h
* @version V1.00
* @brief SDH register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SDH_REG_H__
#define __SDH_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup SDH SD Card Host Interface(SDH)
Memory Mapped Structure for SDH Controller
@{ */
typedef struct
{
/**
* @var SDH_T::FB
* Offset: 0x00~0x7C Shared Buffer (FIFO)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |BUFFER |Shared Buffer
* | | |Buffer for DMA transfer
* @var SDH_T::DMACTL
* Offset: 0x400 DMA Control and Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DMAEN |DMA Engine Enable Bit
* | | |0 = DMA Disabled.
* | | |1 = DMA Enabled.
* | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
* | | |Note: If target abort is occurred, DMAEN will be cleared.
* |[1] |DMARST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset internal state machine and pointers
* | | |The contents of control register will not be cleared
* | | |This bit will auto be cleared after few clock cycles.
* | | |Note: The software reset DMA related registers.
* |[3] |SGEN |Scatter-gather Function Enable Bit
* | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory).
* | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table
* | | |The format of these Pads' will be described later).
* |[9] |DMABUSY |DMA Transfer Is in Progress
* | | |This bit indicates if SD Host is granted and doing DMA transfer or not.
* | | |0 = DMA transfer is not in progress.
* | | |1 = DMA transfer is in progress.
* @var SDH_T::DMASA
* Offset: 0x408 DMA Transfer Starting Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ORDER |Determined to the PAD Table Fetching Is in Order or Out of Order
* | | |0 = PAD table is fetched in order.
* | | |1 = PAD table is fetched out of order.
* | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1.
* |[31:1] |DMASA |DMA Transfer Starting Address
* | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.
* | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.
* | | |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004.
* @var SDH_T::DMABCNT
* Offset: 0x40C DMA Transfer Byte Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[25:0] |BCNT |DMA Transfer Byte Count (Read Only)
* | | |This field indicates the remained byte count of DMA transfer
* | | |The value of this field is valid only when DMA is busy; otherwise, it is 0.
* @var SDH_T::DMAINTEN
* Offset: 0x410 DMA Interrupt Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Bit
* | | |0 = Target abort interrupt generation Disabled during DMA transfer.
* | | |1 = Target abort interrupt generation Enabled during DMA transfer.
* |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Bit
* | | |0 = Interrupt generation Disabled when wrong EOT is encountered.
* | | |1 = Interrupt generation Enabled when wrong EOT is encountered.
* @var SDH_T::DMAINTSTS
* Offset: 0x414 DMA Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag
* | | |0 = No bus ERROR response received.
* | | |1 = Bus ERROR response received.
* | | |Note1: This bit is read only, but can be cleared by writing '1' to it.
* | | |Note2: When DMA's bus master received ERROR response, it means that target abort is happened
* | | |DMA will stop transfer and respond this event and then go to IDLE state
* | | |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again.
* |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag
* | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.
* | | |0 = No EOT encountered before DMA transfer finished.
* | | |1 = EOT encountered before DMA transfer finished.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* @var SDH_T::GCTL
* Offset: 0x800 Global Control and Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GCTLRST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset SD host
* | | |The contents of control register will not be cleared
* | | |This bit will auto cleared after reset complete.
* |[1] |SDEN |Secure Digital Functionality Enable Bit
* | | |0 = SD functionality disabled.
* | | |1 = SD functionality enabled.
* @var SDH_T::GINTEN
* Offset: 0x804 Global Interrupt Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Bit
* | | |0 = DMA READ/WRITE target abort interrupt generation disabled.
* | | |1 = DMA READ/WRITE target abort interrupt generation enabled.
* @var SDH_T::GINTSTS
* Offset: 0x808 Global Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
* | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation
* | | |When Target Abort is occurred, please reset all engine.
* | | |0 = No bus ERROR response received.
* | | |1 = Bus ERROR response received.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* @var SDH_T::CTL
* Offset: 0x820 SD Control and Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |COEN |Command Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will output a command to SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[1] |RIEN |Response Input Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will wait to receive a response from SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[2] |DIEN |Data Input Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[3] |DOEN |Data Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[4] |R2EN |Response R2 Input Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7).
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will output 74 clock cycles to SD card.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Bit
* | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
* | | |1 = Enabled, SD host will output 8 clock cycles.
* | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
* |[7] |CLKKEEP |SD Clock Enable Control
* | | |0 = SD host decided when to output clock and when to disable clock output automatically.
* | | |1 = SD clock always keeps free running.
* |[13:8] |CMDCODE |SD Command Code
* | | |This register contains the SD command code (0x00 - 0x3F).
* |[14] |CTLRST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset the internal state machine and counters
* | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2_EN will be cleared)
* | | |This bit will be auto cleared after few clock cycles.
* |[15] |DBW |SD Data Bus Width (for 1-bit / 4-bit Selection)
* | | |0 = Data bus width is 1-bit.
* | | |1 = Data bus width is 4-bit.
* |[23:16] |BLKCNT |Block Counts to Be Transferred or Received
* | | |This field contains the block counts for data-in and data-out transfer
* | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance
* | | |Don't fill 0x0 to this field.
* | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
* |[27:24] |SDNWR |NWR Parameter for Block Write Operation
* | | |This value indicates the NWR parameter for data block write operation in SD clock counts
* | | |The actual clock cycle will be SDNWR+1.
* @var SDH_T::CMDARG
* Offset: 0x824 SD Command Argument Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ARGUMENT |SD Command Argument
* | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card
* | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.
* @var SDH_T::INTEN
* Offset: 0x828 SD Interrupt Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Bit
* | | |0 = BLKDIF (SDH_INTEN[0]) trigger interrupt Disable.
* | | |1 = BLKDIF (SDH_INTEN[0]) trigger interrupt Enabled.
* |[1] |CRCIEN |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit
* | | |0 = CRCIF (SDH_INTEN[1]) trigger interrupt Disable.
* | | |1 = CRCIF (SDH_INTEN[1]) trigger interrupt Enabled.
* |[8] |CDIEN |SD Card Detection Interrupt Enable Bit
* | | |Enable/Disable interrupts generation of SD controller when card is inserted or removed.
* | | |0 = CDIF (SDH_INTEN[8]) trigger interrupt Disable.
* | | |1 = CDIF (SDH_INTEN[8]) trigger interrupt Enabled.
* |[12] |RTOIEN |Response Time-out Interrupt Enable Bit
* | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out
* | | |Time-out value is specified at TOUT register.
* | | |0 = RTOIF (SDH_INTEN[12]) trigger interrupt Disabled.
* | | |1 = RTOIF (SDH_INTEN[12]) trigger interrupt Enabled.
* |[13] |DITOIEN |Data Input Time-out Interrupt Enable Bit
* | | |Enable/Disable interrupts generation of SD controller when data input time-out
* | | |Time-out value is specified at TOUT register.
* | | |0 = DITOIF (SDH_INTEN[13]) trigger interrupt Disabled.
* | | |1 = DITOIF (SDH_INTEN[13]) trigger interrupt Enabled.
* |[14] |WKIEN |Wake-up Signal Generating Enable Bit
* | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.
* | | |0 = SD Card interrupt to wake-up chip Disabled.
* | | |1 = SD Card interrupt to wake-up chip Enabled.
* |[30] |CDSRC |SD Card Detect Source Selection
* | | |0 = From SD card's DAT3 pin.
* | | |Host need clock to got data on pin DAT3
* | | |Please make sure CLKKEEP (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin.
* | | |1 = From GPIO pin.
* @var SDH_T::INTSTS
* Offset: 0x82C SD Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only)
* | | |This bit indicates that SD host has finished all data-in or data-out block transfer
* | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.
* | | |0 = Not finished yet.
* | | |1 = Done.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only)
* | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer
* | | |When CRC error is occurred, software should reset SD engine
* | | |Some response (ex
* | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag
* | | |In this condition, software should ignore CRC error and clears this bit manually.
* | | |0 = No CRC error is occurred.
* | | |1 = CRC error is occurred.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[2] |CRC7 |CRC7 Check Status (Read Only)
* | | |SD host will check CRC7 correctness during each response in
* | | |If that response does not contain CRC7 information (ex
* | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.
* | | |0 = Fault.
* | | |1 = OK.
* |[3] |CRC16 |CRC16 Check Status of Data-in Transfer (Read Only)
* | | |SD host will check CRC16 correctness after data-in transfer.
* | | |0 = Fault.
* | | |1 = OK.
* |[6:4] |CRCSTS |CRC Status Value of Data-out Transfer (Read Only)
* | | |SD host will record CRC status of data-out transfer
* | | |Software could use this value to identify what type of error is during data-out transfer.
* | | |010 = Positive CRC status.
* | | |101 = Negative CRC status.
* | | |111 = SD card programming error occurs.
* |[7] |DAT0STS |DAT0 Pin Status of Current Selected SD Port (Read Only)
* | | |This bit is the DAT0 pin status of current selected SD port.
* |[8] |CDIF |SD Card Detection Interrupt Flag (Read Only)
* | | |This bit indicates that SD card is inserted or removed
* | | |Only when CDIEN (SDH_INTEN[8]) is set to 1, this bit is active.
* | | |0 = No card is inserted or removed.
* | | |1 = There is a card inserted in or removed from SD.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[12] |RTOIF |Response Time-out Interrupt Flag (Read Only)
* | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).
* | | |0 = Not time-out.
* | | |1 = Response time-out.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[13] |DITOIF |Data Input Time-out Interrupt Flag (Read Only)
* | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit).
* | | |0 = Not time-out.
* | | |1 = Data input time-out.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[16] |CDSTS |Card Detect Status of SD (Read Only)
* | | |This bit indicates the card detect pin status of SD, and is used for card detection
* | | |When there is a card inserted in or removed from SD, software should check this bit to confirm if there is really a card insertion or removal.
* | | |If CDSRC (SDH_INTEN[30]) = 0, to select DAT3 for card detection:.
* | | |0 = Card removed.
* | | |1 = Card inserted.
* | | |If CDSRC (SDH_INTEN[30]) = 1, to select GPIO for card detection:.
* | | |0 = Card inserted.
* | | |1 = Card removed.
* |[18] |DAT1STS |DAT1 Pin Status of SD Port (Read Only)
* | | |This bit indicates the DAT1 pin status of SD port.
* @var SDH_T::RESP0
* Offset: 0x830 SD Receiving Response Token Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RESPTK0 |SD Receiving Response Token 0
* | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
* | | |This field contains response bit 47-16 of the response token.
* @var SDH_T::RESP1
* Offset: 0x834 SD Receiving Response Token Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |RESPTK1 |SD Receiving Response Token 1
* | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
* | | |This register contains the bit 15-8 of the response token.
* @var SDH_T::BLEN
* Offset: 0x838 SD Block Length Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:0] |BLKLEN |SD BLOCK LENGTH in Byte Unit
* | | |An 11-bit value specifies the SD transfer byte count of a block
* | | |The actual byte count is equal to BLKLEN+1.
* | | |Note: The default SD block length is 512 bytes
* @var SDH_T::TOUT
* Offset: 0x83C SD Response/Data-in Time-out Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |TOUT |SD Response/Data-in Time-out Value
* | | |A 24-bit value specifies the time-out counts of response and data input
* | | |SD host controller will wait start bit of response or data-in until this value reached
* | | |The time period depends on SD engine clock frequency
* | | |Do not write a small number into this field, or you may never get response or data due to time-out.
* | | |Note: Filling 0x0 into this field will disable hardware time-out function.
*/
__IO uint32_t FB[32]; /*!< Shared Buffer (FIFO) */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[224];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t DMACTL; /*!< [0x0400] DMA Control and Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t DMASA; /*!< [0x0408] DMA Transfer Starting Address Register */
__I uint32_t DMABCNT; /*!< [0x040c] DMA Transfer Byte Count Register */
__IO uint32_t DMAINTEN; /*!< [0x0410] DMA Interrupt Enable Control Register */
__IO uint32_t DMAINTSTS; /*!< [0x0414] DMA Interrupt Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[250];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t GCTL; /*!< [0x0800] Global Control and Status Register */
__IO uint32_t GINTEN; /*!< [0x0804] Global Interrupt Control Register */
__IO uint32_t GINTSTS; /*!< [0x0808] Global Interrupt Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[5];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CTL; /*!< [0x0820] SD Control and Status Register */
__IO uint32_t CMDARG; /*!< [0x0824] SD Command Argument Register */
__IO uint32_t INTEN; /*!< [0x0828] SD Interrupt Control Register */
__IO uint32_t INTSTS; /*!< [0x082c] SD Interrupt Status Register */
__I uint32_t RESP0; /*!< [0x0830] SD Receiving Response Token Register 0 */
__I uint32_t RESP1; /*!< [0x0834] SD Receiving Response Token Register 1 */
__IO uint32_t BLEN; /*!< [0x0838] SD Block Length Register */
__IO uint32_t TOUT; /*!< [0x083c] SD Response/Data-in Time-out Register */
} SDH_T;
/**
@addtogroup SDH_CONST SDH Bit Field Definition
Constant Definitions for SDH Controller
@{ */
#define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH_T::DMACTL: DMAEN Position */
#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH_T::DMACTL: DMAEN Mask */
#define SDH_DMACTL_DMARST_Pos (1) /*!< SDH_T::DMACTL: DMARST Position */
#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH_T::DMACTL: DMARST Mask */
#define SDH_DMACTL_SGEN_Pos (3) /*!< SDH_T::DMACTL: SGEN Position */
#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH_T::DMACTL: SGEN Mask */
#define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH_T::DMACTL: DMABUSY Position */
#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH_T::DMACTL: DMABUSY Mask */
#define SDH_DMASA_ORDER_Pos (0) /*!< SDH_T::DMASA: ORDER Position */
#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH_T::DMASA: ORDER Mask */
#define SDH_DMASA_DMASA_Pos (1) /*!< SDH_T::DMASA: DMASA Position */
#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH_T::DMASA: DMASA Mask */
#define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH_T::DMABCNT: BCNT Position */
#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH_T::DMABCNT: BCNT Mask */
#define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH_T::DMAINTEN: ABORTIEN Position */
#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH_T::DMAINTEN: ABORTIEN Mask */
#define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH_T::DMAINTEN: WEOTIEN Position */
#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH_T::DMAINTEN: WEOTIEN Mask */
#define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH_T::DMAINTSTS: ABORTIF Position */
#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH_T::DMAINTSTS: ABORTIF Mask */
#define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH_T::DMAINTSTS: WEOTIF Position */
#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH_T::DMAINTSTS: WEOTIF Mask */
#define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH_T::GCTL: GCTLRST Position */
#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH_T::GCTL: GCTLRST Mask */
#define SDH_GCTL_SDEN_Pos (1) /*!< SDH_T::GCTL: SDEN Position */
#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH_T::GCTL: SDEN Mask */
#define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH_T::GINTEN: DTAIEN Position */
#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH_T::GINTEN: DTAIEN Mask */
#define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH_T::GINTSTS: DTAIF Position */
#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH_T::GINTSTS: DTAIF Mask */
#define SDH_CTL_COEN_Pos (0) /*!< SDH_T::CTL: COEN Position */
#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH_T::CTL: COEN Mask */
#define SDH_CTL_RIEN_Pos (1) /*!< SDH_T::CTL: RIEN Position */
#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH_T::CTL: RIEN Mask */
#define SDH_CTL_DIEN_Pos (2) /*!< SDH_T::CTL: DIEN Position */
#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH_T::CTL: DIEN Mask */
#define SDH_CTL_DOEN_Pos (3) /*!< SDH_T::CTL: DOEN Position */
#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH_T::CTL: DOEN Mask */
#define SDH_CTL_R2EN_Pos (4) /*!< SDH_T::CTL: R2EN Position */
#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH_T::CTL: R2EN Mask */
#define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH_T::CTL: CLK74OEN Position */
#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH_T::CTL: CLK74OEN Mask */
#define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH_T::CTL: CLK8OEN Position */
#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH_T::CTL: CLK8OEN Mask */
#define SDH_CTL_CLKKEEP_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */
#define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */
#define SDH_CTL_CMDCODE_Pos (8) /*!< SDH_T::CTL: CMDCODE Position */
#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH_T::CTL: CMDCODE Mask */
#define SDH_CTL_CTLRST_Pos (14) /*!< SDH_T::CTL: CTLRST Position */
#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH_T::CTL: CTLRST Mask */
#define SDH_CTL_DBW_Pos (15) /*!< SDH_T::CTL: DBW Position */
#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH_T::CTL: DBW Mask */
#define SDH_CTL_BLKCNT_Pos (16) /*!< SDH_T::CTL: BLKCNT Position */
#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH_T::CTL: BLKCNT Mask */
#define SDH_CTL_SDNWR_Pos (24) /*!< SDH_T::CTL: SDNWR Position */
#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH_T::CTL: SDNWR Mask */
#define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH_T::CMDARG: ARGUMENT Position */
#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH_T::CMDARG: ARGUMENT Mask */
#define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH_T::INTEN: BLKDIEN Position */
#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH_T::INTEN: BLKDIEN Mask */
#define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH_T::INTEN: CRCIEN Position */
#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH_T::INTEN: CRCIEN Mask */
#define SDH_INTEN_CDIEN_Pos (8) /*!< SDH_T::INTEN: CDIEN Position */
#define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos) /*!< SDH_T::INTEN: CDIEN Mask */
#define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH_T::INTEN: RTOIEN Position */
#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH_T::INTEN: RTOIEN Mask */
#define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH_T::INTEN: DITOIEN Position */
#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH_T::INTEN: DITOIEN Mask */
#define SDH_INTEN_WKIEN_Pos (14) /*!< SDH_T::INTEN: WKIEN Position */
#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH_T::INTEN: WKIEN Mask */
#define SDH_INTEN_CDSRC_Pos (30) /*!< SDH_T::INTEN: CDSRC Position */
#define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos) /*!< SDH_T::INTEN: CDSRC Mask */
#define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH_T::INTSTS: BLKDIF Position */
#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH_T::INTSTS: BLKDIF Mask */
#define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH_T::INTSTS: CRCIF Position */
#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH_T::INTSTS: CRCIF Mask */
#define SDH_INTSTS_CRC7_Pos (2) /*!< SDH_T::INTSTS: CRC7 Position */
#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH_T::INTSTS: CRC7 Mask */
#define SDH_INTSTS_CRC16_Pos (3) /*!< SDH_T::INTSTS: CRC16 Position */
#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH_T::INTSTS: CRC16 Mask */
#define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH_T::INTSTS: CRCSTS Position */
#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH_T::INTSTS: CRCSTS Mask */
#define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH_T::INTSTS: DAT0STS Position */
#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH_T::INTSTS: DAT0STS Mask */
#define SDH_INTSTS_CDIF_Pos (8) /*!< SDH_T::INTSTS: CDIF Position */
#define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos) /*!< SDH_T::INTSTS: CDIF Mask */
#define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH_T::INTSTS: RTOIF Position */
#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH_T::INTSTS: RTOIF Mask */
#define SDH_INTSTS_DITOIF_Pos (13) /*!< SDH_T::INTSTS: DITOIF Position */
#define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos) /*!< SDH_T::INTSTS: DITOIF Mask */
#define SDH_INTSTS_CDSTS_Pos (16) /*!< SDH_T::INTSTS: CDSTS Position */
#define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos) /*!< SDH_T::INTSTS: CDSTS Mask */
#define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH_T::INTSTS: DAT1STS Position */
#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH_T::INTSTS: DAT1STS Mask */
#define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH_T::RESP0: RESPTK0 Position */
#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH_T::RESP0: RESPTK0 Mask */
#define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH_T::RESP1: RESPTK1 Position */
#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH_T::RESP1: RESPTK1 Mask */
#define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH_T::BLEN: BLKLEN Position */
#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH_T::BLEN: BLKLEN Mask */
#define SDH_TOUT_TOUT_Pos (0) /*!< SDH_T::TOUT: TOUT Position */
#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH_T::TOUT: TOUT Mask */
/**@}*/ /* SDH_CONST */
/**@}*/ /* end of SDH register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __SDH_REG_H__ */

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bsp/nuvoton/libraries/m460/Device/Nuvoton/m460/Include/spi_reg.h Normal file
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@ -0,0 +1,861 @@
/**************************************************************************//**
* @file spi_reg.h
* @version V3.00
* @brief SPI register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SPI_REG_H__
#define __SPI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup SPI Serial Peripheral Interface Controller(SPI)
Memory Mapped Structure for SPI Controller
@{ */
typedef struct
{
/**
* @var SPI_T::CTL
* Offset: 0x00 SPI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SPIEN |SPI Transfer Control Enable Bit
* | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
* | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
* | | |0 = Transfer control Disabled.
* | | |1 = Transfer control Enabled.
* | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
* |[1] |RXNEG |Receive on Negative Edge
* | | |0 = Received data input signal is latched on the rising edge of SPI bus clock.
* | | |1 = Received data input signal is latched on the falling edge of SPI bus clock.
* |[2] |TXNEG |Transmit on Negative Edge
* | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
* | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock.
* |[3] |CLKPOL |Clock Polarity
* | | |0 = SPI bus clock is idle low.
* | | |1 = SPI bus clock is idle high.
* |[7:4] |SUSPITV |Suspend Interval (Master Only)
* | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
* | | |The default value is 0x3
* | | |The period of the suspend interval is obtained according to the following equation.
* | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
* | | |Example:
* | | |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle.
* | | |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle.
* | | |.....
* | | |SUSPITV = 0xE .... 14.5 SPICLK clock cycle.
* | | |SUSPITV = 0xF .... 15.5 SPICLK clock cycle.
* |[12:8] |DWIDTH |Data Width
* | | |This field specifies how many bits can be transmitted / received in one transaction
* | | |The minimum bit length is 4 bits and can up to 32 bits.
* | | |DWIDTH = 0x04 .... 4 bits.
* | | |DWIDTH = 0x05 .... 5 bits.
* | | |DWIDTH = 0x06 .... 6 bits.
* | | |DWIDTH = 0x07 .... 7 bits.
* | | |DWIDTH = 0x08 .... 8 bits.
* | | |DWIDTH = 0x09 .... 9 bits.
* | | |.....
* | | |DWIDTH = 0x1F .... 31 bits.
* | | |DWIDTH = 0x00 .... 32 bits.
* | | |Note: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode
* | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically.
* |[13] |LSB |Send LSB First
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
* |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit
* | | |This bit is used to select full-duplex or half-duplex for SPI transfer
* | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
* | | |0 = SPI operates in full-duplex transfer.
* | | |1 = SPI operates in half-duplex transfer.
* |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only)
* | | |This bit field is only available in Master mode
* | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
* | | |0 = Receive-only mode Disabled.
* | | |1 = Receive-only mode Enabled.
* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
* | | |0 = SPI unit transfer interrupt Disabled.
* | | |1 = SPI unit transfer interrupt Enabled.
* |[18] |SLAVE |Slave Mode Control
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[19] |REORDER |Byte Reorder Function Enable Bit
* | | |0 = Byte Reorder function Disabled.
* | | |1 = Byte Reorder function Enabled
* | | |A byte suspend interval will be inserted among each byte
* | | |The period of the byte suspend interval depends on the setting of SUSPITV.
* | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
* |[20] |DATDIR |Data Port Direction Control
* | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
* | | |0 = SPI data is input direction.
* | | |1 = SPI data is output direction.
* @var SPI_T::CLKDIV
* Offset: 0x04 SPI Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |DIVIDER |Clock Divider
* | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master
* | | |The frequency is obtained according to the following equation.
* | | |where
* | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
* | | |Note: Not supported in I2S mode.
* @var SPI_T::SSCTL
* Offset: 0x08 SPI Slave Select Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SS |Slave Selection Control (Master Only)
* | | |If AUTOSS bit is cleared to 0,
* | | |0 = set the SPIx_SS line to inactive state.
* | | |1 = set the SPIx_SS line to active state.
* | | |If the AUTOSS bit is set to 1,
* | | |0 = Keep the SPIx_SS line at inactive state.
* | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
* | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]).
* |[2] |SSACTPOL |Slave Selection Active Polarity
* | | |This bit defines the active polarity of slave selection signal (SPIx_SS).
* | | |0 = The slave selection signal SPIx_SS is active low.
* | | |1 = The slave selection signal SPIx_SS is active high.
* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
* | | |0 = Automatic slave selection function Disabled
* | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]).
* | | |1 = Automatic slave selection function Enabled.
* |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit
* | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIx_CLK, SPIx_MISO and SPIx_MOSI pins.
* | | |0 = 4-wire bi-direction interface.
* | | |1 = 3-wire bi-direction interface.
* | | |Note: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S mode is enabled.
* |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
* | | |0 = Slave mode bit count error interrupt Disabled.
* | | |1 = Slave mode bit count error interrupt Enabled.
* |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
* | | |0 = Slave mode TX under run interrupt Disabled.
* | | |1 = Slave mode TX under run interrupt Enabled.
* |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
* | | |0 = Slave select active interrupt Disabled.
* | | |1 = Slave select active interrupt Enabled.
* |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
* | | |0 = Slave select inactive interrupt Disabled.
* | | |1 = Slave select inactive interrupt Enabled.
* @var SPI_T::PDMACTL
* Offset: 0x0C SPI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
* | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
* |[1] |RXPDMAEN |Receive PDMA Enable Bit
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
* @var SPI_T::FIFOCTL
* Offset: 0x10 SPI FIFO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset receive FIFO pointer and receive circuit
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
* |[1] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset transmit FIFO pointer and transmit circuit
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
* | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
* |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
* | | |0 = RX FIFO threshold interrupt Disabled.
* | | |1 = RX FIFO threshold interrupt Enabled.
* |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
* | | |0 = TX FIFO threshold interrupt Disabled.
* | | |1 = TX FIFO threshold interrupt Enabled.
* |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit
* | | |0 = Receive time-out interrupt Disabled.
* | | |1 = Receive time-out interrupt Enabled.
* |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
* | | |0 = Receive FIFO overrun interrupt Disabled.
* | | |1 = Receive FIFO overrun interrupt Enabled.
* |[6] |TXUFPOL |TX Underflow Data Polarity
* | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
* | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
* | | |Note:
* | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
* | | |2. This bit should be set as 0 in I2S mode.
* | | |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
* | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
* |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
* | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1
* | | |This bit is used to enable the TX underflow interrupt.
* | | |0 = Slave TX underflow interrupt Disabled.
* | | |1 = Slave TX underflow interrupt Enabled.
* |[8] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear receive FIFO pointer
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The RX shift register will not be cleared.
* |[9] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear transmit FIFO pointer
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The TX shift register will not be cleared.
* |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error
* | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in SPI Slave mode.
* | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in SPI Slave mode
* | | |User can read SLVBENUM (SPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened.
* | | |Note: Slave mode only.
* |[26:24] |RXTH |Receive FIFO Threshold
* | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
* | | |The MSB of this bit field is only meaningful while SPI mode 4~16 bits of data length.
* |[30:28] |TXTH |Transmit FIFO Threshold
* | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
* | | |The MSB of this bit field is only meaningful while SPI mode 4~16 bits of data length
* @var SPI_T::STATUS
* Offset: 0x14 SPI Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Busy Status (Read Only)
* | | |0 = SPI controller is in idle state.
* | | |1 = SPI controller is in busy state.
* | | |The following listing are the bus busy conditions:
* | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0.
* | | |b
* | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
* | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1.
* | | |d
* | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
* | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
* |[1] |UNITIF |Unit Transfer Interrupt Flag
* | | |0 = No transaction has been finished since this bit was cleared to 0.
* | | |1 = SPI controller has finished one unit transfer.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[2] |SSACTIF |Slave Select Active Interrupt Flag
* | | |0 = Slave select active interrupt was cleared or not occurred.
* | | |1 = Slave select active interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
* | | |0 = Slave select inactive interrupt was cleared or not occurred.
* | | |1 = Slave select inactive interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
* | | |0 = The slave select line status is 0.
* | | |1 = The slave select line status is 1.
* | | |Note: This bit is only available in Slave mode
* | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
* |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
* | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
* | | |0 = No Slave mode bit count error event.
* | | |1 = Slave mode bit count error event occurs.
* | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
* | | |This bit will be cleared by writing 1 to it.
* |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
* | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
* | | |0 = No Slave TX under run event.
* | | |1 = Slave TX under run event occurs.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |0 = No FIFO is overrun.
* | | |1 = Receive FIFO is overrun.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |SPIENSTS |SPI Enable Status (Read Only)
* | | |0 = The SPI controller is disabled.
* | | |1 = The SPI controller is enabled.
* | | |Note: The SPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* |[19] |TXUFIF |TX Underflow Interrupt Flag
* | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
* | | |0 = No effect.
* | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
* | | |Note 1: This bit will be cleared by writing 1 to it.
* | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
* @var SPI_T::STATUS2
* Offset: 0x18 SPI Status2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX Data
* | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode
* | | |This status register will be fixed to 0x0 when SLVBERX (SPIx_FIFOCTL[10]) is disabled.
* | | |Note 1: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (SPIx_STATUS[6]).
* | | |Note 2: Slave mode only.
* @var SPI_T::TX
* Offset: 0x20 SPI Data Transmit Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TX |Data Transmit Register
* | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers
* | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.
* | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted
* | | |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer.
* | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]
* | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section
* | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
* @var SPI_T::RX
* Offset: 0x30 SPI Data Receive Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RX |Data Receive Register
* | | |There are 4-level FIFO buffers in this controller
* | | |The data receive register holds the data received from SPI data input pin
* | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register
* | | |This is a read only register.
* @var SPI_T::I2SCTL
* Offset: 0x60 I2S Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SEN |I2S Controller Enable Bit
* | | |0 = Disabled I2S mode.
* | | |1 = Enabled I2S mode.
* | | |Note:
* | | |1. If enable this bit, I2Sx_BCLK will start to output in Master mode.
* | | |2
* | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
* |[1] |TXEN |Transmit Enable Bit
* | | |0 = Data transmit Disabled.
* | | |1 = Data transmit Enabled.
* |[2] |RXEN |Receive Enable Bit
* | | |0 = Data receive Disabled.
* | | |1 = Data receive Enabled.
* |[3] |MUTE |Transmit Mute Enable Bit
* | | |0 = Transmit data is shifted from buffer.
* | | |1 = Transmit channel zero.
* |[5:4] |WDWIDTH |Word Width
* | | |00 = data size is 8-bit.
* | | |01 = data size is 16-bit.
* | | |10 = data size is 24-bit.
* | | |11 = data size is 32-bit.
* |[6] |MONO |Monaural Data
* | | |0 = Data is stereo format.
* | | |1 = Data is monaural format.
* |[7] |ORDER |Stereo Data Order in FIFO
* | | |0 = Left channel data at high byte.
* | | |1 = Left channel data at low byte.
* |[8] |SLAVE |Slave Mode
* | | |I2S can operate as master or slave
* | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip
* | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[15] |MCLKEN |Master Clock Enable Bit
* | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
* | | |0 = Master clock Disabled.
* | | |1 = Master clock Enabled.
* |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit
* | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1
* | | |This function is only available in transmit operation.
* | | |0 = Right channel zero cross detection Disabled.
* | | |1 = Right channel zero cross detection Enabled.
* |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit
* | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1
* | | |This function is only available in transmit operation.
* | | |0 = Left channel zero cross detection Disabled.
* | | |1 = Left channel zero cross detection Enabled.
* |[23] |RXLCH |Receive Left Channel Enable Bit
* | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
* | | |0 = Receive right channel data in Mono mode.
* | | |1 = Receive left channel data in Mono mode.
* |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit
* | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit
* | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[29:28] |FORMAT |Data Format Selection
* | | |00 = I2S data format.
* | | |01 = MSB justified data format.
* | | |10 = PCM mode A.
* | | |11 = PCM mode B.
* |[31] |SLVERRIEN |Bit Clock Loss Interrupt Enable Bit for Slave Mode
* | | |Interrupt occurs if this bit is set to 1 and bit clock loss event occurs.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* @var SPI_T::I2SCLK
* Offset: 0x64 I2S Clock Divider Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |MCLKDIV |Master Clock Divider
* | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices
* | | |The frequency of master clock, fMCLK, is determined by the following expressions:
* | | |If MCLKDIV >= 1,.
* | | |If MCLKDIV = 0,.
* | | |where
* | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2
* | | |In general, the master clock rate is 256 times sampling clock rate.
* |[17:8] |BCLKDIV |Bit Clock Divider
* | | |The I2S controller will generate bit clock in Master mode
* | | |The clock frequency of bit clock , fBCLK, is determined by the following expression:
* | | |where
* | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
* | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by .
* | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.
* |[24] |I2SMODE |I2S Clock Divider Number Selection for I2S Mode and SPI Mode
* | | |User sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set.
* | | |User needs to set I2SMODE before I2SEN (SPIx_I2SCTL[0]) or SPIEN (SPIx_CTL[0]) is enabled.
* | | |0 = The frequency of peripheral clock is set to SPI mode.
* | | |1 = The frequency of peripheral clock is set to I2S mode.
* |[25] |I2SSLAVE |I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode
* | | |User sets I2SSLAVE to set frequency of peripheral clock of I2S master mode and I2S slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.
* | | |I2SSLAVE needs to set before I2SEN (SPIx_I2SCTL[0]) is enabled.
* | | |0 = The frequency of peripheral clock is set to I2S Master mode.
* | | |1 = The frequency of peripheral clock is set to I2S Slave mode.
* @var SPI_T::I2SSTS
* Offset: 0x68 I2S Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4] |RIGHT |Right Channel (Read Only)
* | | |This bit indicates the current transmit data is belong to which channel.
* | | |0 = Left channel.
* | | |1 = Right channel.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |I2SENSTS |I2S Enable Status (Read Only)
* | | |0 = The SPI/I2S control logic is disabled.
* | | |1 = The SPI/I2S control logic is enabled.
* | | |Note: The SPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
* |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag
* | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag
* | | |0 = No zero cross event occurred on right channel.
* | | |1 = Zero cross event occurred on right channel.
* |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag
* | | |0 = No zero cross event occurred on left channel.
* | | |1 = Zero cross event occurred on left channel.
* |[22] |SLVERRIF |Bit Clock Loss Interrupt Flag for Slave Mode
* | | |0 = No bit clock loss event occurred.
* | | |1 = Bit clock loss event occurred.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[26:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
*/
__IO uint32_t CTL; /*!< [0x0000] SPI Control Register */
__IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */
__IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */
__IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */
__IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */
__IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */
__I uint32_t STATUS2; /*!< [0x0018] SPI Status2 Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[3];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[11];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */
__IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */
__IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */
} SPI_T;
/**
@addtogroup SPI_CONST SPI Bit Field Definition
Constant Definitions for SPI Controller
@{ */
#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */
#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */
#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */
#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */
#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */
#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */
#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */
#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */
#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */
#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */
#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */
#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */
#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */
#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */
#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */
#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */
#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */
#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */
#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */
#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */
#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */
#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */
#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */
#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */
#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */
#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */
#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */
#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */
#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */
#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */
#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */
#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */
#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */
#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */
#define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI_T::SSCTL: SLV3WIRE Position */
#define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI_T::SSCTL: SLV3WIRE Mask */
#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */
#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */
#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */
#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */
#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */
#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */
#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */
#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */
#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */
#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */
#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */
#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */
#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */
#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */
#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */
#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */
#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */
#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */
#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */
#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */
#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */
#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */
#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */
#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */
#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */
#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */
#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */
#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */
#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */
#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */
#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */
#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */
#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */
#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */
#define SPI_FIFOCTL_SLVBERX_Pos (10) /*!< SPI_T::FIFOCTL: SLVBERX Position */
#define SPI_FIFOCTL_SLVBERX_Msk (0x1ul << SPI_FIFOCTL_SLVBERX_Pos) /*!< SPI_T::FIFOCTL: SLVBERX Mask */
#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */
#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */
#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */
#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */
#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */
#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */
#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */
#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */
#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */
#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */
#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */
#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */
#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */
#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */
#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */
#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */
#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */
#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */
#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */
#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */
#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */
#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */
#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */
#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */
#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */
#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */
#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */
#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */
#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */
#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */
#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */
#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */
#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */
#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */
#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */
#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */
#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */
#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */
#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */
#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */
#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */
#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */
#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */
#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */
#define SPI_STATUS2_SLVBENUM_Pos (24) /*!< SPI_T::STATUS2: SLVBENUM Position */
#define SPI_STATUS2_SLVBENUM_Msk (0x3ful << SPI_STATUS2_SLVBENUM_Pos) /*!< SPI_T::STATUS2: SLVBENUM Mask */
#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */
#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */
#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */
#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */
#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */
#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */
#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */
#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */
#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */
#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */
#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */
#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */
#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */
#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */
#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */
#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */
#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */
#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */
#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */
#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */
#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */
#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */
#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */
#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */
#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */
#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */
#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */
#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */
#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */
#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */
#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */
#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */
#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */
#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */
#define SPI_I2SCTL_SLVERRIEN_Pos (31) /*!< SPI_T::I2SCTL: SLVERRIEN Position */
#define SPI_I2SCTL_SLVERRIEN_Msk (0x1ul << SPI_I2SCTL_SLVERRIEN_Pos) /*!< SPI_T::I2SCTL: SLVERRIEN Mask */
#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */
#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */
#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */
#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */
#define SPI_I2SCLK_I2SMODE_Pos (24) /*!< SPI_T::I2SCLK: I2SMODE Position */
#define SPI_I2SCLK_I2SMODE_Msk (0x1ul << SPI_I2SCLK_I2SMODE_Pos) /*!< SPI_T::I2SCLK: I2SMODE Mask */
#define SPI_I2SCLK_I2SSLAVE_Pos (25) /*!< SPI_T::I2SCLK: I2SSLAVE Position */
#define SPI_I2SCLK_I2SSLAVE_Msk (0x1ul << SPI_I2SCLK_I2SSLAVE_Pos) /*!< SPI_T::I2SCLK: I2SSLAVE Mask */
#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */
#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */
#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */
#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */
#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */
#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */
#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */
#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */
#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */
#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */
#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */
#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */
#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */
#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */
#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */
#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */
#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */
#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */
#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */
#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */
#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */
#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */
#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */
#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */
#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */
#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */
#define SPI_I2SSTS_SLVERRIF_Pos (22) /*!< SPI_T::I2SSTS: SLVERRIF Position */
#define SPI_I2SSTS_SLVERRIF_Msk (0x1ul << SPI_I2SSTS_SLVERRIF_Pos) /*!< SPI_T::I2SSTS: SLVERRIF Mask */
#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */
#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */
#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */
#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */
#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */
#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */
/**@}*/ /* SPI_CONST */
/**@}*/ /* end of SPI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __SPI_REG_H__ */

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bsp/nuvoton/libraries/m460/Device/Nuvoton/m460/Include/spim_reg.h Normal file
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/**************************************************************************//**
* @file spim_reg.h
* @version V1.00
* @brief SPIM register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SPIM_REG_H__
#define __SPIM_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup SPIM Serial Peripheral Interface Controller Master Mode (SPIM)
Memory Mapped Structure for SPIM Controller
@{ */
typedef struct
{
/**
* @var SPIM_T::CTL0
* Offset: 0x00 Control and Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CIPHOFF |Cipher Disable Control
* | | |0 = Cipher function Enabled.
* | | |1 = Cipher function Disabled.
* | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically.
* | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e.
* | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled.
* | | |Note3 : When cipher encryption/decryption is enabled, please set DESELTIM (SPIM_DMMCTL[20:16]) >= 0x10.
* | | |When cipher encryption/decryption is disabled, please set DESELTIM(SPIM_DMMCTL[20:16]) >= 0x8.
* |[2] |BALEN |Balance the AHB Control Time Between Cipher Enable and Disable Control
* | | |When cipher is enabled, the AHB control signal will delay some time caused by the encoding or decoding calculation
* | | |Therefore, if set BALEN to 1, it will make the AHB signal processing time with cipher disabled be equal to that with cipher enabled.
* | | |Note: Only useful when cipher is disabled.
* |[5] |B4ADDREN |4-byte Address Mode Enable Control
* | | |0 = 4-byte address mode is disabled, and 3-byte address mode is enabled.
* | | |1 = 4-byte address mode is enabled.
* | | |Note: Used for DMA write mode, DMA read mode, and DMM mode.
* |[6] |IEN |Interrupt Enable Control
* | | |0 = SPIM Interrupt Disabled.
* | | |1 = SPIM Interrupt Enabled.
* |[7] |IF |Interrupt Flag
* | | |(1) Write Operation :
* | | |0 = No effect.
* | | |1 = Write 1 to clear.
* | | |(2) Read Operation :
* | | |0 = The transfer has not finished yet.
* | | |1 = The transfer has done.
* |[12:8] |DWIDTH |Transmit/Receive Bit Length
* | | |This specifies how many bits are transmitted/received in one transmit/receive transaction.
* | | |0x7 = 8 bits.
* | | |0xF = 16 bits.
* | | |0x17 = 24 bits.
* | | |0x1F = 32 bits.
* | | |Others = Incorrect transfer result.
* | | |Note1: Only used for normal I/O mode.
* | | |Note2: Only 8, 16, 24, and 32 bits are allowed. Other bit length will result in incorrect transfer.
* |[14:13] |BURSTNUM |Transmit/Receive Burst Number
* | | |This field specifies how many transmit/receive transactions should be executed continuously in one transfer.
* | | |0x0 = Only one transmit/receive transaction will be executed in one transfer.
* | | |0x1 = Two successive transmit/receive transactions will be executed in one transfer.
* | | |0x2 = Three successive transmit/receive transactions will be executed in one transfer.
* | | |0x3 = Four successive transmit/receive transactions will be executed in one transfer.
* | | |Note: Only used for normal I/O Mode.
* |[15] |QDIODIR |SPI Interface Direction Select for Quad/Dual Mode
* | | |0 = Interface signals are input.
* | | |1 = Interface signals are output.
* | | |Note: Only used for normal I/O mode.
* |[19:16] |SUSPITV |Suspend Interval
* | | |These four bits provide the configuration of suspend interval between two successive transmit/receive transactions in a transfer
* | | |The default value is 0x00
* | | |When BURSTNUM = 00, setting this field has no effect on transfer
* | | |The desired interval is obtained according to the following equation (from the last falling edge of current SPI clock to the first rising edge of next SPI clock):
* | | | (SUSPITV+2)*period of AHB clock
* | | | 0x0 = 2 AHB clock cycles.
* | | | 0x1 = 3 AHB clock cycles.
* | | | ......
* | | | 0xE = 16 AHB clock cycles.
* | | | 0xF = 17 AHB clock cycles.
* | | | Note: Only used for normal I/O mode.
* |[21:20] |BITMODE |SPI Interface Bit Mode
* | | |0x0 = Standard mode.
* | | |0x1 = Dual mode.
* | | |0x2 = Quad mode.
* | | |0x3 = Reserved.
* | | |Note: Only used for normal I/O mode.
* |[23:22] |OPMODE |SPI Function Operation Mode
* | | |0x0 = Normal I/O mode. (Note1) (Note3)
* | | |0x1 = DMA write mode. (Note2) (Note3)
* | | |0x2 = DMA read mode. (Note3)
* | | |0x3 = Direct Memory Mapping mode (DMM mode) (Default). (Note4)
* | | |Note1 : After user uses Normal I/O mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
* | | |Note2 : In DMA write mode, hardware will send just one page program command per operation
* | | |Users must take care of cross-page cases
* | | |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
* | | |Note3 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x00000000 to 0x01FFFFFF when user uses Normal I/O mode, DMA write mode, and DMA read mode to write/read external SPI flash data
* | | |Please user check size of used SPI flash component to know access address range of external SPI flash.
* | | |Note4 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x08000000 to 0x09FFFFFF when user uses Direct Memory mapping mode (DMM mode) to read external SPI flash data
* | | |Please user check size of used SPI flash component to know access address range of external SPI flash.
* |[31:24] |CMDCODE |Page Program Command Code (Note4)
* | | |(1) 0x02 = Page program (Used for DMA Write mode).
* | | |(2) 0x32 = Quad page program with TYPE_1 program flow (Used for DMA Write mode). (Note3)
* | | |(3) 0x38 = Quad page program with TYPE_2 program flow (Used for DMA Write mode). (Note3)
* | | |(4) 0x40 = Quad page program with TYPE_3 program flow (Used for DMA Write mode). (Note3)
* | | |The Others = Reserved.
* | | |Read Command Code :
* | | |(1) 0x03 = Standard Read (Used for DMA Read/DMM mode).
* | | |(2) 0x0B = Fast Read (Used for DMA Read/DMM mode).
* | | |The fast read command code "0x0B" is similar to command code of standard read "0x03" except it can operate at highest possible frequency
* | | |(Note2)
* | | |(3) 0x3B = Fast Read Dual Output (Used for DMA Read/DMM mode).
* | | |(4) 0xBB = Fast Read Dual I/O (Used for DMA Read/DMM mode).
* | | |The fast read dual I/O command code "0xBB" is similar to command code of fast read dual output "0x3B" but with capability to input the address bits two bits per clock
* | | |(Note2)
* | | |(5) 0xEB = Fast quad read (Used for DMA Read/DMM mode).
* | | |(6) 0xE7 = Word quad read (Used for DMA Read/DMM mode).
* | | |The command code of word quad read "0xE7" is similar to command code of fast quad read "0xEB" except that the lowest address bit must equal to 0 and the number of dummy cycles is less than fast quad read
* | | |(Note2)
* | | |(7) 0x0D = DTR/DDR Fast read (Used for DMA Read/DMM mode).
* | | |(8) 0xBD = DTR/DDR dual read (Used for DMA Read/DMM mode).
* | | |(9) 0xED = DTR/DDR quad read (Used for DMA Read/DMM mode).
* | | |The Others command codes are Reserved.
* | | |The DTR/DDR read commands "0x0D,0xBD,0xED" improves throughput by transferring address and data on both the falling and rising edge of SPI flash clock (SPIM_CLK)
* | | |It is similar to those commands "0x0B, 0xBB, 0xEB" but allows transfer of address and data on rising edge and falling edge of SPI flash output clock
* | | |(Note2)
* | | |Note1: Quad mode of SPI Flash must be enabled first by normal I/O mode before using quad page program/quad read commands.
* | | |Note2: See SPI flash specifications for support items.
* | | |Note3: For TYPE_1, TYPE_2, and TYPE_3 of page program command code, refer to Figure 7.19-3, Figure 7.19-4, and Figure 7.19-5.
* | | |Note4: Please disable "continuous read mode" and "burst wrap mode" before DMA write mode of SPI flash controller is used to program data of external SPI flash
* | | |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
* @var SPIM_T::CTL1
* Offset: 0x04 Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SPIMEN |Go and Busy Status
* | | |(1) Write Operation :
* | | |0 = No effect.
* | | |1 = Start the transfer
* | | |This bit remains set during the transfer and is automatically cleared after transfer finished.
* | | |(2) Read Operation :
* | | |0 = The transfer has done.
* | | |1 = The transfer has not finished yet.
* | | |Note: All registers should be set before writing 1 to the SPIMEN bit
* | | |When a transfer is in progress, you should not write to any register of this peripheral.
* |[1] |CACHEOFF |Cache Memory Function Disable Control
* | | |0 = Cache memory function enable. (Default value)
* | | |1 = Cache memory function disable.
* | | |Note: When CCM mode is enabled, the cache function will be disable by hardware automatically
* | | |When CCM mode is disabled, the cache function can be enable or disable by user.
* |[2] |CCMEN |CCM (Core Coupled Memory) Mode Enable Control
* | | |0 = CCM mode disable. (Default value)
* | | |1 = CCM mode enable.
* | | |Note1: When CCM mode is enabled, the cache function will be disable by hardware automatically
* | | |When CCM mode is disabled, the cache function can be enabled or disabled by user.
* | | |Note2: When CCM mode is disabled, user accesses the core coupled memory by bus master
* | | |In this case, the SPI flash controller will send error response via HRESP bus signal to bus master.
* | | |Note3: When CCM mode needs to be enabled, user sets CCMEN to 1 and needs to read this register to show the current hardware status
* | | |When reading data of CCMEN is 1, MCU can start to read data from CCM memory space or write data to CCM memory space.
* |[3] |CDINVAL |Cache Data Invalid Enable Control
* | | |(1) Write Operation:
* | | |0 = No effect.
* | | |1 = Set all cache data to be invalid. This bit is cleared by hardware automatically.
* | | |(2) Read Operation : No effect
* | | |Note: When SPI flash memory is page erasing or whole flash erasing, please set CDINVAL to 0x1
* | | |After user uses normal I/O mode or DMA write mode of SPI flash controller to program or erase the content of external SPI flash, please set CDINVAL to 0x1.
* |[4] |SS |Slave Select Active Enable Control
* | | |0 = SPIM_SS is in active level.
* | | |1 = SPIM_SS is in inactive level (Default).
* | | |Note: This interface can only drive one device/slave at a given time
* | | |Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer
* | | |Functional description of SSACTPOL(SPIM_CTL1[5]) and SS is shown in Table 2.
* |[5] |SSACTPOL |Slave Select Active Level
* | | |It defines the active level of device/slave select signal (SPIM_SS), and we show in Table 2.
* | | |0 = The SPIM_SS slave select signal is active low.
* | | |1 = The SPIM_SS slave select signal is active high.
* |[11:8] |IDLETIME |Idle Time Interval
* | | |In DMM mode, IDLETIME is set to control the minimum idle time between two SPI Flash accesses.
* | | |Minimum idle time = (IDLETIME + 1) * AHB clock cycle time.
* | | |Note1: Only used for DMM mode.
* | | |Note2 : AHB clock cycle time = 1/AHB clock frequency.
* |[31:16] |DIVIDER |Clock Divider Register
* | | |The value in this field is the frequency divider of the AHB clock (HCLK) to generate the serial SPI output clock "SCLK" on the output SPIM_CLK pin
* | | |The desired frequency is obtained according to the following equation:
* | | |Note1: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of HCLK.
* | | |Note2: SCLK is serial SPI output clock.
* | | |Note3: Please check the specification of the used SPI flash component to decide the frequency of SPI flash clock.
* | | |Note4: For DTR/DDR read commands "0x0D, 0xBD, 0xED", the setting values of DIVIDER are only 1,2,4,8,16,32,..., where n = 0,1,2,3,4, ...
* @var SPIM_T::RXCLKDLY
* Offset: 0x0C RX Clock Delay Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DWDELSEL |SPI flash deselect time interval of DMA write mode
* | | |For DMA write mode only
* | | |This register sets the deselect time interval of SPI flash (i.e.
* | | |time interval of inactive level of SPIM_SS) when SPI flash controller operates on DMA write mode
* | | |(Note1)
* | | |Deselect time interval of DMA write mode = (DWDELSEL + 1) * AHB clock cycle time (Note2).
* | | |Note1: Please user check the used external SPI flash component to set this register value
* | | |In general case, the deselect time interval of SPI flash is greater than 50 ns when SPI flash performs the program operation.
* | | |Note2: AHB clock cycle time = 1/AHB clock frequency.
* |[18:16] |RDDLYSEL |Sampling Clock Delay Selection for Received Data
* | | |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode
* | | |Determine the number of inserted delay cycles
* | | |Used to adjust the sampling clock of received data to latch the correct data.
* | | |0x0 : No delay. (Default Value)
* | | |0x1 : Delay 1 SPI flash clock.
* | | |0x2 : Delay 2 SPI flash clocks.
* | | |0x3 : Delay 3 SPI flash clocks.
* | | |...
* | | |0x7 : Delay 7 SPI flash clocks
* | | |Note : We can use manufacturer id or device id of external SPI flash component to determine the correct setting value of RDDLYSEL, and we give example as follows.
* | | |For example, manufacturer id and device id of external SPI flash for some vendor are 0xEF and 0x1234 separately
* | | |Firstly, we set RDDLYSEL to 0x0, and use read manufacturer id/device id command to read the manufacturer id of external SPI flash by using normal I/O mode (the manufacturer id is 0xEF (1110_1111) in this example).
* | | |If manufacturer id which reads from external SPI flash is 0xF7 (1111_0111), it denotes that manufacturer id is shifted the right by 1 bit and most significant bit (MSB) of manufacturer id is assigned to 1
* | | |According to manufacturer id reads from external SPI flash, we need to set RDDLYSEL to 0x1 to receive SPI flash data correctly.
* |[20] |RDEDGE |Sampling Clock Edge Selection for Received Data
* | | |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode
* | | |0 : Use SPI input clock rising edge to sample received data. (Default Value)
* | | |1 : Use SPI input clock falling edge to sample received data.
* @var SPIM_T::RX[4]
* Offset: 0x10 ~ 0x1C Data Receive Register 0 ~ 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RXDAT |Data Receive Register
* | | |The Data Receive Registers hold the received data of the last executed transfer.
* | | |Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM]
* | | |If BURSTNUM > 0, received data are held in the most significant RXDAT register first.
* | | |Number of valid-bit is specified in SPIM_CTL0[DWIDTH]
* | | |If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RXDAT register first.
* | | |In a byte, received data are held in the most significant bit of RXDAT register first.
* | | |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, received data will be held in the order SPIM_RX3[23:0], SPIM_RX2[23:0], SPIM_RX1[23:0], SPIM_RX0[23:0].
* | | |Example 2: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, received data will be held in the order SPIM_RX0[7:0], SPIM_RX0[15:8], SPIM_RX0[23:16].
* | | |Example 3: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, received data will be held in the order SPIM_RX0[7], SPIM_RX0[6], ...,
* | | |SPIM_RX0[0].
* @var SPIM_T::TX[4]
* Offset: 0x20 ~ 0x2C Data Transmit Register 0 ~ 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TXDAT |Data Transmit Register
* | | |The Data Transmit Registers hold the data to be transmitted in next transfer.
* | | |Number of valid TXDAT registers is specified in SPIM_CTL0[BURSTNUM]
* | | |If BURSTNUM > 0, data are transmitted in the most significant TXDAT register first.
* | | |Number of valid-bit is specified in SPIM_CTL0[DWIDTH]
* | | |If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TXDAT register first.
* | | |In a byte, data are transmitted in the most significant bit of TXDAT register first.
* | | |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX3[23:0], SPIM_TX2[23:0], SPIM_TX1[23:0], SPIM_TX0[23:0] in next transfer.
* | | |Example 2: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX0[7:0], SPIM_TX0[15:8], SPIM_TX0[23:16] in next transfer.
* | | |Example 3: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, data will be transmitted in the order SPIM_TX0[7], SPIM_TX0[6], ...,
* | | |SPIM_TX0[0] in next transfer.
* @var SPIM_T::SRAMADDR
* Offset: 0x30 SRAM Memory Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ADDR |SRAM Memory Address
* | | |For DMA Read mode, this is the destination address for DMA transfer.
* | | |For DMA Write mode, this is the source address for DMA transfer.
* | | |Note: This address must be word-aligned.
* @var SPIM_T::DMACNT
* Offset: 0x34 DMA Transfer Byte Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |DMACNT |DMA Transfer Byte Count Register
* | | |It indicates the transfer length for DMA process.
* | | |Note1: The unit for counting is byte.
* | | |Note2: The number must be the multiple of 4.
* | | |Note3: Please check specification of used SPI flash to know maximum byte length of page program.
* @var SPIM_T::FADDR
* Offset: 0x38 SPI Flash Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ADDR |SPI Flash Address Register
* | | |For DMA Read mode, this is the source address for DMA transfer.
* | | |For DMA Write mode, this is the destination address for DMA transfer.
* | | |Note 1 : This address must be word-aligned.
* | | |Note 2 : For external SPI flash with 32 MB, the value of this SPI flash address register "ADDR" is from 0x00000000 to 0x01FFFFFF when user uses DMA write mode and DMA read mode to write/read external SPI flash data
* | | |Please user check size of used SPI flash component to know access address range of external SPI flash.
* @var SPIM_T::KEY1
* Offset: 0x3C Cipher Key1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY1 |Cipher Key1 Register
* | | |This is the KEY1 data for cipher function.
* | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically.
* | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e.
* | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled.
* @var SPIM_T::KEY2
* Offset: 0x40 Cipher Key2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY2 |Cipher Key2 Register
* | | |This is the KEY2 data for cipher function.
* | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically.
* | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e.
* | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled.
* @var SPIM_T::DMMCTL
* Offset: 0x44 Direct Memory Mapping Mode Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:8] |CRMDAT |Mode bits data for Continuous Read Mode (or performance enhance mode) (Default value = 0)
* | | |Only for direct memory mapping mode
* | | |Set the mode bits data for continuous read mode (or performance enhance mode).
* | | |When we set this mode bits currently (Note1) and set CREN(SPIM_DMMCTL[25]), this reduces the command phase by eight clocks and allows the read address to be immediately entered after SPIM_SS asserted to active
* | | |(Note1)
* | | |Note1 : Please check the used SPI flash specification to know the setting value of this mode bits data, and different SPI flash vendor may use different setting values.
* | | |Note2 : CRMDAT needs to used with CREN(SPIM_DMMCTL[25]).
* |[20:16] |DESELTIM |SPI Flash Deselect Time
* | | |Only for direct memory mapping mode
* | | |Set the minimum time width of SPI flash deselect time (i.e.
* | | |Minimum SPIM_SS deselect time), and we show in Figure 7.19-8.
* | | |(1) Cache function disable :
* | | |Minimum time width of SPIM_SS deselect time = (DESELTIM + 1) * AHB clock cycle time.
* | | |(2) Cache function enable :
* | | |Minimum time width of SPIM_SS deselect time = (DESELTIM + 4) * AHB clock cycle time.
* | | |Note1 : AHB clock cycle time = 1/AHB clock frequency.
* | | |Note2 : When cipher encryption/decryption is enabled, please set this register value >= 0x10
* | | |When cipher encryption/decryption is disabled, please set this register value >= 0x8.
* | | |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values.
* |[24] |BWEN |16 bytes Burst Wrap Mode Enable Control Register (Default value = 0)
* | | |Only for WINBOND SPI flash, direct memory mapping mode, Cache enable, and read command code "0xEB, and 0xE7"
* | | |0 = Burst Wrap Mode Disable. (Default)
* | | |1 = Burst Wrap Mode Enable.
* | | |In direct memory mapping mode, both of quad read commands "0xEB" and "0xE7" support burst wrap mode for cache application and performance enhance
* | | |For cache application, the burst wrap mode can be used to fill the cache line quickly (In this SPI flash controller, we use cache data line with 16 bytes size)
* | | |For performance enhance with direct memory mapping mode and cache enable, when cache data is miss, the burst wrap mode can let MCU get the required SPI flash data quickly.
* |[25] |CREN |Continuous Read Mode Enable Control
* | | |Only for direct memory mapping mode, read command codes 0xBB, 0xEB, 0xE7, 0x0D, 0xBD, 0xED (Note2)
* | | |0 = Continuous Read Mode Disable. (Default)
* | | |1 = Continuous Read Mode Enable.
* | | |For read operations of SPI flash, commands of fast read quad I/O (0xEB), word read quad I/O (0xE7 in Winbond SPI flash), fast read dual I/O (0xBB), DTR/DDR fast read (0x0D), DTR/DDR fast read dual I/O (0xBD), and DTR/DDR fast read quad I/O (0xED) can further reduce command overhead through setting the "continuous read mode" bits (8 bits) after the input address data.
* | | |Note: When user uses function of continuous read mode and sets USETEN (SPIM_CTL2[16]) to 1, CRMDAT(SPIM_DMMCTL[15:8]) must be set by used SPI flash specifications
* | | |When user uses function of continuous read mode and sets USETEN(SPIM_CTL2[16]) to 0, CRMDAT(SPIM_DMMCTL[15:8]) is set by default value of WINBOND SPI flash.
* |[26] |UACTSCLK |User Sets SPI Flash Active SCLK Time
* | | |Only for direct memory mapping mode, DMA write mode, and DMA read mode
* | | |0 = According to DIVIDER(SPIM_CTL1[31:16]), ACTSCLKT(SPIM_DMMCTL[31:28]) is set by hardware automatically
* | | |(Default value)
* | | |1 = Set ACTSCLKT(SPIM_DMMCTL[31:28]) by user manually.
* | | |When user wants to set ACTSCLKT(SPIM_DMMCTL[31:28]) manually, please set UACTSCLK to 1.
* |[31:28] |ACTSCLKT |SPI Flash Active SCLK Time
* | | |Only for direct memory mapping mode, DMA write mode, and DMA read mode
* | | |This register sets time interval between SPIM SS active edge and the position edge of the first serial SPI output clock, and we show in Figure 7.19-8.
* | | |(1) ACTSCLKT = 0 (function disable) :.
* | | |Time interval = 1 AHB clock cycle time.
* | | |(2) ACTSCLKT != 0 (function enable) :
* | | |Time interval = (ACTSCLKT + 3) * AHB clock cycle time.
* | | |Note1 : AHB clock cycle time = 1/AHB clock frequency.
* | | |Note2 : SCLK is SPI output clock
* | | |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values.
* @var SPIM_T::CTL2
* Offset: 0x48 Control Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[16] |USETEN |User Set Value Enable Control
* | | |Only for direct memory mapping mode and DMA read mode with read commands 0x03,0x0B,0x3B,0xBB,0xEB,0xE7
* | | |0 = Hardware circuit of SPI flash controller will use the following default values of DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations automatically.
* | | |Dummy cycle number (DCNUM) :
* | | |Dummy cycle number for read command 0x03 : 0x0
* | | |Dummy cycle number for read command 0x0B : 0x8
* | | |Dummy cycle number for read command 0x3B : 0x8
* | | |Dummy cycle number for read command 0xBB : 0x0
* | | |Dummy cycle number for read command 0xEB : 0x4
* | | |Dummy cycle number for read command 0xE7 : 0x2
* | | |Mode bits data for continuous read mode (CRMDAT) : 0x20
* | | |1 = If DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) are not set as above default values, user must set USETEN to 0x1, DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations manually.
* | | |For DTR/DDR command codes 0x0D, 0xBD, and 0xED, please set USETEN to 0x1.
* |[20] |DTRMPOFF |Mode Phase OFF for DTR/DDR Command Codes 0x0D, 0xBD, and 0xED
* | | |Only for direct memory mapping mode and DMA read mode (Note1)
* | | |0 = mode cycle number (or performance enhance cycle number) does not equal to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED.
* | | |1 = mode cycle number (or performance enhance cycle number) equals to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED.
* | | |Note1 : Please check the used SPI flash specification to know the mode cycle number (or performance enhance cycle number) for DTR/DDR command codes 0x0D, 0xBD, and 0xED.
* |[28:24] |DCNUM |Dummy Cycle Number
* | | |Only for direct memory mapping mode and DMA read mode (Note1)
* | | |Set number of dummy cycles
* | | |(1) For non-DTR/non-DDR command codes 0x03, 0x0B, 0x3B, 0xBB, 0xEB, and 0xE7 :
* | | |When read command code do not need any dummy cycles (i.e.
* | | |dummy cycle number = 0x0), user must set DCNUM to 0x0.
* | | |For command code 0xBB, if both mode cycle number (or performance enhance cycle number) and dummy cycle number do not equal to 0x0 simultaneously, user must set DCNUM to "mode cycle number + dummy cycle number" by used SPI flash specification.
* | | |For command code 0xBB, if there is only dummy cycle number (i.e.
* | | |dummy cycle number != 0x0 and mode cycle number = 0x0 (or performance enhance cycle number = 0x0)), user set DCNUM to dummy cycle number by used SPI flash specification.
* | | |For command codes 0x0B, 0x3B, 0xEB, and 0xE7, user only set DCNUM to dummy cycle number by used SPI flash specification.
* | | |(2) For DTR/DDR command codes 0x0D, 0xBD, and 0xED :
* | | |user sets DCNUM to dummy cycle number and DTRMPOFF(SPIM_CTL2[20]) by used SPI flash specification.
* | | |Note1 : Number of dummy cycles depends on the frequency of SPI output clock, SPI flash vendor, and read command types
* | | |Please check the used SPI flash specification to know the setting value of this number of dummy cycles.
*/
__IO uint32_t CTL0; /*!< [0x0000] Control and Status Register 0 */
__IO uint32_t CTL1; /*!< [0x0004] Control Register 1 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t RXCLKDLY; /*!< [0x000c] RX Clock Delay Control Register */
__I uint32_t RX[4]; /*!< [0x0010] ~ [0x001C] Data Receive Register 0~3 */
__IO uint32_t TX[4]; /*!< [0x0020] ~ [0x002C] Data Transmit Register 0~3 */
__IO uint32_t SRAMADDR; /*!< [0x0030] SRAM Memory Address Register */
__IO uint32_t DMACNT; /*!< [0x0034] DMA Transfer Byte Count Register */
__IO uint32_t FADDR; /*!< [0x0038] SPI Flash Address Register */
__O uint32_t KEY1; /*!< [0x003c] Cipher Key1 Register */
__O uint32_t KEY2; /*!< [0x0040] Cipher Key2 Register */
__IO uint32_t DMMCTL; /*!< [0x0044] Direct Memory Mapping Mode Control Register */
__IO uint32_t CTL2; /*!< [0x0048] Control Register 2 */
} SPIM_T;
/**
@addtogroup SPIM_CONST SPIM Bit Field Definition
Constant Definitions for SPIM Controller
@{ */
#define SPIM_CTL0_CIPHOFF_Pos (0) /*!< SPIM_T::CTL0: CIPHOFF Position */
#define SPIM_CTL0_CIPHOFF_Msk (0x1ul << SPIM_CTL0_CIPHOFF_Pos) /*!< SPIM_T::CTL0: CIPHOFF Mask */
#define SPIM_CTL0_BALEN_Pos (2) /*!< SPIM_T::CTL0: BALEN Position */
#define SPIM_CTL0_BALEN_Msk (0x1ul << SPIM_CTL0_BALEN_Pos) /*!< SPIM_T::CTL0: BALEN Mask */
#define SPIM_CTL0_B4ADDREN_Pos (5) /*!< SPIM_T::CTL0: B4ADDREN Position */
#define SPIM_CTL0_B4ADDREN_Msk (0x1ul << SPIM_CTL0_B4ADDREN_Pos) /*!< SPIM_T::CTL0: B4ADDREN Mask */
#define SPIM_CTL0_IEN_Pos (6) /*!< SPIM_T::CTL0: IEN Position */
#define SPIM_CTL0_IEN_Msk (0x1ul << SPIM_CTL0_IEN_Pos) /*!< SPIM_T::CTL0: IEN Mask */
#define SPIM_CTL0_IF_Pos (7) /*!< SPIM_T::CTL0: IF Position */
#define SPIM_CTL0_IF_Msk (0x1ul << SPIM_CTL0_IF_Pos) /*!< SPIM_T::CTL0: IF Mask */
#define SPIM_CTL0_DWIDTH_Pos (8) /*!< SPIM_T::CTL0: DWIDTH Position */
#define SPIM_CTL0_DWIDTH_Msk (0x1ful << SPIM_CTL0_DWIDTH_Pos) /*!< SPIM_T::CTL0: DWIDTH Mask */
#define SPIM_CTL0_BURSTNUM_Pos (13) /*!< SPIM_T::CTL0: BURSTNUM Position */
#define SPIM_CTL0_BURSTNUM_Msk (0x3ul << SPIM_CTL0_BURSTNUM_Pos) /*!< SPIM_T::CTL0: BURSTNUM Mask */
#define SPIM_CTL0_QDIODIR_Pos (15) /*!< SPIM_T::CTL0: QDIODIR Position */
#define SPIM_CTL0_QDIODIR_Msk (0x1ul << SPIM_CTL0_QDIODIR_Pos) /*!< SPIM_T::CTL0: QDIODIR Mask */
#define SPIM_CTL0_SUSPITV_Pos (16) /*!< SPIM_T::CTL0: SUSPITV Position */
#define SPIM_CTL0_SUSPITV_Msk (0xful << SPIM_CTL0_SUSPITV_Pos) /*!< SPIM_T::CTL0: SUSPITV Mask */
#define SPIM_CTL0_BITMODE_Pos (20) /*!< SPIM_T::CTL0: BITMODE Position */
#define SPIM_CTL0_BITMODE_Msk (0x3ul << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_T::CTL0: BITMODE Mask */
#define SPIM_CTL0_OPMODE_Pos (22) /*!< SPIM_T::CTL0: OPMODE Position */
#define SPIM_CTL0_OPMODE_Msk (0x3ul << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_T::CTL0: OPMODE Mask */
#define SPIM_CTL0_CMDCODE_Pos (24) /*!< SPIM_T::CTL0: CMDCODE Position */
#define SPIM_CTL0_CMDCODE_Msk (0xfful << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_T::CTL0: CMDCODE Mask */
#define SPIM_CTL1_SPIMEN_Pos (0) /*!< SPIM_T::CTL1: SPIMEN Position */
#define SPIM_CTL1_SPIMEN_Msk (0x1ul << SPIM_CTL1_SPIMEN_Pos) /*!< SPIM_T::CTL1: SPIMEN Mask */
#define SPIM_CTL1_CACHEOFF_Pos (1) /*!< SPIM_T::CTL1: CACHEOFF Position */
#define SPIM_CTL1_CACHEOFF_Msk (0x1ul << SPIM_CTL1_CACHEOFF_Pos) /*!< SPIM_T::CTL1: CACHEOFF Mask */
#define SPIM_CTL1_CCMEN_Pos (2) /*!< SPIM_T::CTL1: CCMEN Position */
#define SPIM_CTL1_CCMEN_Msk (0x1ul << SPIM_CTL1_CCMEN_Pos) /*!< SPIM_T::CTL1: CCMEN Mask */
#define SPIM_CTL1_CDINVAL_Pos (3) /*!< SPIM_T::CTL1: CDINVAL Position */
#define SPIM_CTL1_CDINVAL_Msk (0x1ul << SPIM_CTL1_CDINVAL_Pos) /*!< SPIM_T::CTL1: CDINVAL Mask */
#define SPIM_CTL1_SS_Pos (4) /*!< SPIM_T::CTL1: SS Position */
#define SPIM_CTL1_SS_Msk (0x1ul << SPIM_CTL1_SS_Pos) /*!< SPIM_T::CTL1: SS Mask */
#define SPIM_CTL1_SSACTPOL_Pos (5) /*!< SPIM_T::CTL1: SSACTPOL Position */
#define SPIM_CTL1_SSACTPOL_Msk (0x1ul << SPIM_CTL1_SSACTPOL_Pos) /*!< SPIM_T::CTL1: SSACTPOL Mask */
#define SPIM_CTL1_IDLETIME_Pos (8) /*!< SPIM_T::CTL1: IDLETIME Position */
#define SPIM_CTL1_IDLETIME_Msk (0xful << SPIM_CTL1_IDLETIME_Pos) /*!< SPIM_T::CTL1: IDLETIME Mask */
#define SPIM_CTL1_DIVIDER_Pos (16) /*!< SPIM_T::CTL1: DIVIDER Position */
#define SPIM_CTL1_DIVIDER_Msk (0xfffful << SPIM_CTL1_DIVIDER_Pos) /*!< SPIM_T::CTL1: DIVIDER Mask */
#define SPIM_RXCLKDLY_DWDELSEL_Pos (0) /*!< SPIM_T::RXCLKDLY: DWDELSEL Position */
#define SPIM_RXCLKDLY_DWDELSEL_Msk (0xfful << SPIM_RXCLKDLY_DWDELSEL_Pos) /*!< SPIM_T::RXCLKDLY: DWDELSEL Mask */
#define SPIM_RXCLKDLY_RDDLYSEL_Pos (16) /*!< SPIM_T::RXCLKDLY: RDDLYSEL Position */
#define SPIM_RXCLKDLY_RDDLYSEL_Msk (0x7ul << SPIM_RXCLKDLY_RDDLYSEL_Pos) /*!< SPIM_T::RXCLKDLY: RDDLYSEL Mask */
#define SPIM_RXCLKDLY_RDEDGE_Pos (20) /*!< SPIM_T::RXCLKDLY: RDEDGE Position */
#define SPIM_RXCLKDLY_RDEDGE_Msk (0x1ul << SPIM_RXCLKDLY_RDEDGE_Pos) /*!< SPIM_T::RXCLKDLY: RDEDGE Mask */
#define SPIM_RX_RXDAT_Pos (0) /*!< SPIM_T::RX[4]: RXDAT Position */
#define SPIM_RX_RXDAT_Msk (0xfffffffful << SPIM_RX_RXDAT_Pos) /*!< SPIM_T::RX[4]: RXDAT Mask */
#define SPIM_TX_TXDAT_Pos (0) /*!< SPIM_T::TX[4]: TXDAT Position */
#define SPIM_TX_TXDAT_Msk (0xfffffffful << SPIM_TX_TXDAT_Pos) /*!< SPIM_T::TX[4]: TXDAT Mask */
#define SPIM_SRAMADDR_ADDR_Pos (0) /*!< SPIM_T::SRAMADDR: ADDR Position */
#define SPIM_SRAMADDR_ADDR_Msk (0xfffffffful << SPIM_SRAMADDR_ADDR_Pos) /*!< SPIM_T::SRAMADDR: ADDR Mask */
#define SPIM_DMACNT_DMACNT_Pos (0) /*!< SPIM_T::DMACNT: DMACNT Position */
#define SPIM_DMACNT_DMACNT_Msk (0xfffffful << SPIM_DMACNT_DMACNT_Pos) /*!< SPIM_T::DMACNT: DMACNT Mask */
#define SPIM_FADDR_ADDR_Pos (0) /*!< SPIM_T::FADDR: ADDR Position */
#define SPIM_FADDR_ADDR_Msk (0xfffffffful << SPIM_FADDR_ADDR_Pos) /*!< SPIM_T::FADDR: ADDR Mask */
#define SPIM_KEY1_KEY1_Pos (0) /*!< SPIM_T::KEY1: KEY1 Position */
#define SPIM_KEY1_KEY1_Msk (0xfffffffful << SPIM_KEY1_KEY1_Pos) /*!< SPIM_T::KEY1: KEY1 Mask */
#define SPIM_KEY2_KEY2_Pos (0) /*!< SPIM_T::KEY2: KEY2 Position */
#define SPIM_KEY2_KEY2_Msk (0xfffffffful << SPIM_KEY2_KEY2_Pos) /*!< SPIM_T::KEY2: KEY2 Mask */
#define SPIM_DMMCTL_CRMDAT_Pos (8) /*!< SPIM_T::DMMCTL: CRMDAT Position */
#define SPIM_DMMCTL_CRMDAT_Msk (0xfful << SPIM_DMMCTL_CRMDAT_Pos) /*!< SPIM_T::DMMCTL: CRMDAT Mask */
#define SPIM_DMMCTL_DESELTIM_Pos (16) /*!< SPIM_T::DMMCTL: DESELTIM Position */
#define SPIM_DMMCTL_DESELTIM_Msk (0x1ful << SPIM_DMMCTL_DESELTIM_Pos) /*!< SPIM_T::DMMCTL: DESELTIM Mask */
#define SPIM_DMMCTL_BWEN_Pos (24) /*!< SPIM_T::DMMCTL: BWEN Position */
#define SPIM_DMMCTL_BWEN_Msk (0x1ul << SPIM_DMMCTL_BWEN_Pos) /*!< SPIM_T::DMMCTL: BWEN Mask */
#define SPIM_DMMCTL_CREN_Pos (25) /*!< SPIM_T::DMMCTL: CREN Position */
#define SPIM_DMMCTL_CREN_Msk (0x1ul << SPIM_DMMCTL_CREN_Pos) /*!< SPIM_T::DMMCTL: CREN Mask */
#define SPIM_DMMCTL_UACTSCLK_Pos (26) /*!< SPIM_T::DMMCTL: UACTSCLK Position */
#define SPIM_DMMCTL_UACTSCLK_Msk (0x1ul << SPIM_DMMCTL_UACTSCLK_Pos) /*!< SPIM_T::DMMCTL: UACTSCLK Mask */
#define SPIM_DMMCTL_ACTSCLKT_Pos (28) /*!< SPIM_T::DMMCTL: ACTSCLKT Position */
#define SPIM_DMMCTL_ACTSCLKT_Msk (0xful << SPIM_DMMCTL_ACTSCLKT_Pos) /*!< SPIM_T::DMMCTL: ACTSCLKT Mask */
#define SPIM_CTL2_USETEN_Pos (16) /*!< SPIM_T::CTL2: USETEN Position */
#define SPIM_CTL2_USETEN_Msk (0x1ul << SPIM_CTL2_USETEN_Pos) /*!< SPIM_T::CTL2: USETEN Mask */
#define SPIM_CTL2_DTRMPOFF_Pos (20) /*!< SPIM_T::CTL2: DTRMPOFF Position */
#define SPIM_CTL2_DTRMPOFF_Msk (0x1ul << SPIM_CTL2_DTRMPOFF_Pos) /*!< SPIM_T::CTL2: DTRMPOFF Mask */
#define SPIM_CTL2_DCNUM_Pos (24) /*!< SPIM_T::CTL2: DCNUM Position */
#define SPIM_CTL2_DCNUM_Msk (0x1ful << SPIM_CTL2_DCNUM_Pos) /*!< SPIM_T::CTL2: DCNUM Mask */
/**@}*/ /* SPIM_CONST */
/**@}*/ /* end of SPIM register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __SPIM_REG_H__ */

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/**************************************************************************//**
* @file system_m460.h
* @version V3.00
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M460
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SYSTEM_M460_H__
#define __SYSTEM_M460_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#ifndef __HSI
#define __HSI (12000000UL) /*!< PLL default output is 50MHz */
#endif
#ifndef __HXT
#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */
#endif
#ifndef __LXT
#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
#endif
#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */
#define __HIRC48M (48000000UL) /*!< Internal 48M RC Oscillator Frequency */
#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */
#define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */
#define __SYSTEM_CLOCK (1UL*__HXT)
#ifndef DEBUG_PORT
#define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the micro controller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit(void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_M460_H__ */

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/**************************************************************************//**
* @file tcm_reg.h
* @version V1.00
* @brief Tight Couple Memory Controller
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __TCM_REG_H__
#define __TCM_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Tight Couple Memory Controller -------------------------*/
/**
@addtogroup TCM Tight Couple Memory Controller(TCM)
Memory Mapped Structure for TCM Controller
@{ */
typedef struct
{
/**
* @var TCM_T::GCTL
* Offset: 0x00 Tight Couple Memory Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |WAYNUM |Number of TCM ways configured (Read Only)
* | | |00 = 1 way, NUM_WAY == 1
* | | |01 = 2 way, NUM_WAY == 2
* | | |10 = 3 way, NUM_WAY == 3
* | | |11 = 4 way, NUM_WAY == 4
* |[3:2] |WAYSIZE |Size of each TCM ways (Read Only)
* | | |00 = 1 Kbyte (WAY_SIZE == 0)
* | | |01 = 2 Kbyte (WAY_SIZE == 1)
* | | |10 = 4 Kbyte (WAY_SIZE == 2)
* | | |11 = 8 Kbyte (WAY_SIZE == 3)
* |[4] |CACHECFG |Cache Configuration Bit
* | | |(default: 0) When a TCM way is configured as a cache-way, setting this bit to 1 enables the write-back/write-allocate cache management policy
* | | |Otherwise, a 0 in this bit enables the write-through/no-write-allocate policy
* | | |This bit can be modified only when none of the TCM ways is enabled as a cache-way.
* |[5] |FIXAZERO |Fix Auto Zero (Read Only)
* | | |(default: 0) Asserting this bit to 1 to prohibit update of the AutoZero bits in the TCM way configuration registers by the core
* | | |The default 0 setting allows them to be modified
* | | |This bit itself is not modifiable by the core
* | | |Its value can only be changed during the chip configuration stage when the PORESETn input is HIGH and the SYSRESETn input is LOW
* |[8] |WAY0EN |TCM way0 Enable Contorl
* | | |0 = TCM way0 Disabled.
* | | |1 = TCM way0 Enabled.
* | | |When this bit toggles, the corresponding TCM way is enabled/disabled according to the CacheMode bit in the TCM_WayX_Config_Registers
* | | |Note that a TCM way is not fully enabled until the pre-/post-condition is met
* | | |Specifically, when CacheMode bit is 0, the TCM way is not fully enabled until the PreLoading bit is 0
* | | |It is not fully disabled until both AutoFlushing and AutoZeroing bits are 0
* | | |When CacheMode bit is 1, the TCM way is not fully enabled until the Invalidating bit is 0, and not fully disabled until the AutoZeroing bit is 0.
* |[9] |WAY1EN |TCM way1 Enable Contorl
* | | |0 = TCM way1 Disabled.
* | | |1 = TCM way1 Enabled.
* |[10] |WAY2EN |TCM way2 Enable Contorl
* | | |0 = TCM way2 Disabled.
* | | |1 = TCM way2 Enabled.
* |[11] |WAY3EN |TCM way3 Enable Contorl
* | | |0 = TCM way3 Disabled.
* | | |1 = TCM way3 Enabled.
* @var TCM_T::W0CTL
* Offset: 0x10 Tight Couple Memory Way0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CACHEMD |Cache Mode Enable Bit
* | | |0 = TCM as Local Memory Block (LMB)
* | | |1 = TCM as Cache
* | | |Note: This bit can be modified only when the corresponding WAYxEN bit is clear
* |[1] |PRELD |Pre-load the TCM way
* | | |When CacheMode bit is clear, setting this bit to 1 instructs TCM control to pre-load the TCM way according to the size/addr setting in the corresponding DMA register
* | | |The TCM way is not enabled as a LMB until the preloading operation is completed
* | | |When CacheMode is set, this bit has no meaning
* | | |This bit can be modified only when the corresponding WayEnable bit is clear.
* |[2] |PRELDST |Pre-loading Status
* | | |This is a status bit that returns 1 when the pre-loading of the TCM way (as a LMB) is on-going
* | | |Until this bit is clear, the TCM way is not fully enabled to serve I-/D-bus requests as a LMB
* | | |An access request to the would-be-mapped address range will be wait-stated to avoid the multi-caching scenario that can happens when another TCM way is enabled as a cache-way and the requested target can become cached there because the I-/D-bus request is not blocked.
* |[3] |INVALST |Invalidation Status
* | | |This is a status bit that returns 1 when the pre-enabling invalidation of the TCM way (as a cache-way) is on-going
* | | |Until this bit is clear, the TCM way is not fully enabled to serve I-/D-bus requests as a cache-way
* | | |However, since no multi-caching scenario can occur, no any incoming request is blocked due the on-going invalidation.
* |[4] |AFLUSH |auto-flush the data array
* | | |When CacheMode is clear, setting this bit to 1 instructs TCM control to auto-flush the data array according to the size/addr setting in the corresponding DMA register
* | | |When CacheMode is set, this bit has no meaning
* | | |The data array is always fully flushed when a TCM way is disabled from a write-back/write-allocate cache way
* | | |The TCM way is not fully disabled until the flushing operation is completed
* | | |This bit can be modified only when the corresponding WayEnable bit is clear.
* |[5] |AFLUSHST |This is a status bit that returns 1 when auto-flushing of the TCM way is on-going. The auto-flushing is triggered when the TCM way is disabled as a LMB with the AutoFlush bit set, or when the TCM way is disabled as a cache-way and the cache is configured with write-back/write-allocate. Until this bit is clear, a TCM way is not fully disabled. While it is set, accesses to targets residing in the TCM way are wait-stated. This can occur when the TCM way is configured as a LMB and the target falls in the mapped address range, or when the TCM way is configured as a cache-way in general. The blocking is to avoid memory consistency issue when a late arrival write access, whose target data has been flushed out to the memory.
* |[6] |AZERO |Setting this bit to 1 instructs TCM control to auto-zero a TCM way when it is to be disabled as either a LMB or a cache-way. Auto-zeroing of a LMB is not controlled by the size/addr setting in DMA_control register. The whole TCM way is zerou2019ed out. This bit is reset-configurable like FixAutoZero bit when PORESETn is high and SYSRESETn is low. After that, it is modifiable by the core only if the FixAutoZero bit is clear and the corresponding WayEnable bit is also clear.
* |[7] |AZEROST |Auto-zeroing Status
* | | |This is a status bit that returns 1 when auto-zeroing is on-going
* | | |Similar to AutoFlushing bit
* | | |Accesses with target potentially residing in the TCM way are all wait-stated.
* |[8] |XOMERROR |XOM Error Flag
* | | |This is a status bit that returns 1 when the TCM way is configured as a LMB and is currently mapping a XOM region
* | | |This bit is read-only by the core
* | | |It is set/cleared automatically by the TCM logic.
* |[9] |ERROR |Operating Error Flag
* | | |0 = No error is recored
* | | |1 = An AHB error occurred during the last pre-loading (for LMB) or auto-flushing operation (for LMB or cache-way).
* | | |An AHB error occurred during the last pre-loading (for LMB) or auto-flushing operation (for LMB or cache-way)
* | | |The operation didnu2019t complete successfully
* | | |No error can occur to invalidation or zeroing operation
* | | |This bit is set by TCM logic and can only be cleared by the core.
* |[23:13] |LMBTAG |LMB TAG Base Address
* | | |When TCM way configure as LMB used, these bits define the base address of the mapped region
* | | |This tag is compared against the incoming address to determine if the address hits in the LMB.
* | | |Note: This field can be modified only when the corresponding WAYxEN bit is clear.
* | | |(default: 0) When CacheMode is clear, these bits store the base address of the mapped region
* | | |This tag is compared against the incoming address to determine if the address hits in the LMB
* | | |Depending on LMBSize setting, some of the bits are ignored.
* | | |LMBSize == 1K : all bits used
* | | |LMBSize == 2K : bit 10 ignored
* | | |LMBSize == 4K : bit 11:10 ignored
* | | |LMBSize == 8K : bit 12:10 ignored
* @var TCM_T::W1CTL
* Offset: 0x14 Tight Couple Memory Way1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CACHEMD |Cache Mode Enable Bit
* | | |0 = TCM as Local Memory Block (LMB)
* | | |1 = TCM as Cache
* | | |Note: This bit can be modified only when the corresponding WAYxEN bit is clear
* |[1] |PRELD |Pre-load the TCM way
* | | |When CacheMode bit is clear, setting this bit to 1 instructs TCM control to pre-load the TCM way according to the size/addr setting in the corresponding DMA register
* | | |The TCM way is not enabled as a LMB until the preloading operation is completed
* | | |When CacheMode is set, this bit has no meaning
* | | |This bit can be modified only when the corresponding WayEnable bit is clear.
* |[2] |PRELDST |Pre-loading Status
* | | |This is a status bit that returns 1 when the pre-loading of the TCM way (as a LMB) is on-going
* | | |Until this bit is clear, the TCM way is not fully enabled to serve I-/D-bus requests as a LMB
* | | |An access request to the would-be-mapped address range will be wait-stated to avoid the multi-caching scenario that can happens when another TCM way is enabled as a cache-way and the requested target can become cached there because the I-/D-bus request is not blocked.
* |[3] |INVALST |Invalidation Status
* | | |This is a status bit that returns 1 when the pre-enabling invalidation of the TCM way (as a cache-way) is on-going
* | | |Until this bit is clear, the TCM way is not fully enabled to serve I-/D-bus requests as a cache-way
* | | |However, since no multi-caching scenario can occur, no any incoming request is blocked due the on-going invalidation.
* |[4] |AFLUSH |auto-flush the data array
* | | |When CacheMode is clear, setting this bit to 1 instructs TCM control to auto-flush the data array according to the size/addr setting in the corresponding DMA register
* | | |When CacheMode is set, this bit has no meaning
* | | |The data array is always fully flushed when a TCM way is disabled from a write-back/write-allocate cache way
* | | |The TCM way is not fully disabled until the flushing operation is completed
* | | |This bit can be modified only when the corresponding WayEnable bit is clear.
* |[5] |AFLUSHST |This is a status bit that returns 1 when auto-flushing of the TCM way is on-going. The auto-flushing is triggered when the TCM way is disabled as a LMB with the AutoFlush bit set, or when the TCM way is disabled as a cache-way and the cache is configured with write-back/write-allocate. Until this bit is clear, a TCM way is not fully disabled. While it is set, accesses to targets residing in the TCM way are wait-stated. This can occur when the TCM way is configured as a LMB and the target falls in the mapped address range, or when the TCM way is configured as a cache-way in general. The blocking is to avoid memory consistency issue when a late arrival write access, whose target data has been flushed out to the memory.
* |[6] |AZERO |Setting this bit to 1 instructs TCM control to auto-zero a TCM way when it is to be disabled as either a LMB or a cache-way. Auto-zeroing of a LMB is not controlled by the size/addr setting in DMA_control register. The whole TCM way is zerou2019ed out. This bit is reset-configurable like FixAutoZero bit when PORESETn is high and SYSRESETn is low. After that, it is modifiable by the core only if the FixAutoZero bit is clear and the corresponding WayEnable bit is also clear.
* |[7] |AZEROST |Auto-zeroing Status
* | | |This is a status bit that returns 1 when auto-zeroing is on-going
* | | |Similar to AutoFlushing bit
* | | |Accesses with target potentially residing in the TCM way are all wait-stated.
* |[8] |XOMERROR |XOM Error Flag
* | | |This is a status bit that returns 1 when the TCM way is configured as a LMB and is currently mapping a XOM region
* | | |This bit is read-only by the core
* | | |It is set/cleared automatically by the TCM logic.
* |[9] |ERROR |Operating Error Flag
* | | |0 = No error is recored
* | | |1 = An AHB error occurred during the last pre-loading (for LMB) or auto-flushing operation (for LMB or cache-way).
* | | |An AHB error occurred during the last pre-loading (for LMB) or auto-flushing operation (for LMB or cache-way)
* | | |The operation didnu2019t complete successfully
* | | |No error can occur to invalidation or zeroing operation
* | | |This bit is set by TCM logic and can only be cleared by the core.
* |[23:13] |LMBTAG |LMB TAG Base Address
* | | |When TCM way configure as LMB used, these bits define the base address of the mapped region
* | | |This tag is compared against the incoming address to determine if the address hits in the LMB.
* | | |Note: This field can be modified only when the corresponding WAYxEN bit is clear.
* | | |(default: 0) When CacheMode is clear, these bits store the base address of the mapped region
* | | |This tag is compared against the incoming address to determine if the address hits in the LMB
* | | |Depending on LMBSize setting, some of the bits are ignored.
* | | |LMBSize == 1K : all bits used
* | | |LMBSize == 2K : bit 10 ignored
* | | |LMBSize == 4K : bit 11:10 ignored
* | | |LMBSize == 8K : bit 12:10 ignored
* @var TCM_T::W2CTL
* Offset: 0x18 Tight Couple Memory Way2 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CACHEMD |Cache Mode Enable Bit
* | | |0 = TCM as Local Memory Block (LMB)
* | | |1 = TCM as Cache
* | | |Note: This bit can be modified only when the corresponding WAYxEN bit is clear
* |[1] |PRELD |Pre-load the TCM way
* | | |When CacheMode bit is clear, setting this bit to 1 instructs TCM control to pre-load the TCM way according to the size/addr setting in the corresponding DMA register
* | | |The TCM way is not enabled as a LMB until the preloading operation is completed
* | | |When CacheMode is set, this bit has no meaning
* | | |This bit can be modified only when the corresponding WayEnable bit is clear.
* |[2] |PRELDST |Pre-loading Status
* | | |This is a status bit that returns 1 when the pre-loading of the TCM way (as a LMB) is on-going
* | | |Until this bit is clear, the TCM way is not fully enabled to serve I-/D-bus requests as a LMB
* | | |An access request to the would-be-mapped address range will be wait-stated to avoid the multi-caching scenario that can happens when another TCM way is enabled as a cache-way and the requested target can become cached there because the I-/D-bus request is not blocked.
* |[3] |INVALST |Invalidation Status
* | | |This is a status bit that returns 1 when the pre-enabling invalidation of the TCM way (as a cache-way) is on-going
* | | |Until this bit is clear, the TCM way is not fully enabled to serve I-/D-bus requests as a cache-way
* | | |However, since no multi-caching scenario can occur, no any incoming request is blocked due the on-going invalidation.
* |[4] |AFLUSH |auto-flush the data array
* | | |When CacheMode is clear, setting this bit to 1 instructs TCM control to auto-flush the data array according to the size/addr setting in the corresponding DMA register
* | | |When CacheMode is set, this bit has no meaning
* | | |The data array is always fully flushed when a TCM way is disabled from a write-back/write-allocate cache way
* | | |The TCM way is not fully disabled until the flushing operation is completed
* | | |This bit can be modified only when the corresponding WayEnable bit is clear.
* |[5] |AFLUSHST |This is a status bit that returns 1 when auto-flushing of the TCM way is on-going. The auto-flushing is triggered when the TCM way is disabled as a LMB with the AutoFlush bit set, or when the TCM way is disabled as a cache-way and the cache is configured with write-back/write-allocate. Until this bit is clear, a TCM way is not fully disabled. While it is set, accesses to targets residing in the TCM way are wait-stated. This can occur when the TCM way is configured as a LMB and the target falls in the mapped address range, or when the TCM way is configured as a cache-way in general. The blocking is to avoid memory consistency issue when a late arrival write access, whose target data has been flushed out to the memory.
* |[6] |AZERO |Setting this bit to 1 instructs TCM control to auto-zero a TCM way when it is to be disabled as either a LMB or a cache-way. Auto-zeroing of a LMB is not controlled by the size/addr setting in DMA_control register. The whole TCM way is zerou2019ed out. This bit is reset-configurable like FixAutoZero bit when PORESETn is high and SYSRESETn is low. After that, it is modifiable by the core only if the FixAutoZero bit is clear and the corresponding WayEnable bit is also clear.
* |[7] |AZEROST |Auto-zeroing Status
* | | |This is a status bit that returns 1 when auto-zeroing is on-going
* | | |Similar to AutoFlushing bit
* | | |Accesses with target potentially residing in the TCM way are all wait-stated.
* |[8] |XOMERROR |XOM Error Flag
* | | |This is a status bit that returns 1 when the TCM way is configured as a LMB and is currently mapping a XOM region
* | | |This bit is read-only by the core
* | | |It is set/cleared automatically by the TCM logic.
* |[9] |ERROR |Operating Error Flag
* | | |0 = No error is recored
* | | |1 = An AHB error occurred during the last pre-loading (for LMB) or auto-flushing operation (for LMB or cache-way).
* | | |An AHB error occurred during the last pre-loading (for LMB) or auto-flushing operation (for LMB or cache-way)
* | | |The operation didnu2019t complete successfully
* | | |No error can occur to invalidation or zeroing operation
* | | |This bit is set by TCM logic and can only be cleared by the core.
* |[23:13] |LMBTAG |LMB TAG Base Address
* | | |When TCM way configure as LMB used, these bits define the base address of the mapped region
* | | |This tag is compared against the incoming address to determine if the address hits in the LMB.
* | | |Note: This field can be modified only when the corresponding WAYxEN bit is clear.
* | | |(default: 0) When CacheMode is clear, these bits store the base address of the mapped region
* | | |This tag is compared against the incoming address to determine if the address hits in the LMB
* | | |Depending on LMBSize setting, some of the bits are ignored.
* | | |LMBSize == 1K : all bits used
* | | |LMBSize == 2K : bit 10 ignored
* | | |LMBSize == 4K : bit 11:10 ignored
* | | |LMBSize == 8K : bit 12:10 ignored
* @var TCM_T::W3CTL
* Offset: 0x1C Tight Couple Memory Way3 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CACHEMD |Cache Mode Enable Bit
* | | |0 = TCM as Local Memory Block (LMB)
* | | |1 = TCM as Cache
* | | |Note: This bit can be modified only when the corresponding WAYxEN bit is clear
* |[1] |PRELD |Pre-load the TCM way
* | | |When CacheMode bit is clear, setting this bit to 1 instructs TCM control to pre-load the TCM way according to the size/addr setting in the corresponding DMA register
* | | |The TCM way is not enabled as a LMB until the preloading operation is completed
* | | |When CacheMode is set, this bit has no meaning
* | | |This bit can be modified only when the corresponding WayEnable bit is clear.
* |[2] |PRELDST |Pre-loading Status
* | | |This is a status bit that returns 1 when the pre-loading of the TCM way (as a LMB) is on-going
* | | |Until this bit is clear, the TCM way is not fully enabled to serve I-/D-bus requests as a LMB
* | | |An access request to the would-be-mapped address range will be wait-stated to avoid the multi-caching scenario that can happens when another TCM way is enabled as a cache-way and the requested target can become cached there because the I-/D-bus request is not blocked.
* |[3] |INVALST |Invalidation Status
* | | |This is a status bit that returns 1 when the pre-enabling invalidation of the TCM way (as a cache-way) is on-going
* | | |Until this bit is clear, the TCM way is not fully enabled to serve I-/D-bus requests as a cache-way
* | | |However, since no multi-caching scenario can occur, no any incoming request is blocked due the on-going invalidation.
* |[4] |AFLUSH |auto-flush the data array
* | | |When CacheMode is clear, setting this bit to 1 instructs TCM control to auto-flush the data array according to the size/addr setting in the corresponding DMA register
* | | |When CacheMode is set, this bit has no meaning
* | | |The data array is always fully flushed when a TCM way is disabled from a write-back/write-allocate cache way
* | | |The TCM way is not fully disabled until the flushing operation is completed
* | | |This bit can be modified only when the corresponding WayEnable bit is clear.
* |[5] |AFLUSHST |This is a status bit that returns 1 when auto-flushing of the TCM way is on-going. The auto-flushing is triggered when the TCM way is disabled as a LMB with the AutoFlush bit set, or when the TCM way is disabled as a cache-way and the cache is configured with write-back/write-allocate. Until this bit is clear, a TCM way is not fully disabled. While it is set, accesses to targets residing in the TCM way are wait-stated. This can occur when the TCM way is configured as a LMB and the target falls in the mapped address range, or when the TCM way is configured as a cache-way in general. The blocking is to avoid memory consistency issue when a late arrival write access, whose target data has been flushed out to the memory.
* |[6] |AZERO |Setting this bit to 1 instructs TCM control to auto-zero a TCM way when it is to be disabled as either a LMB or a cache-way. Auto-zeroing of a LMB is not controlled by the size/addr setting in DMA_control register. The whole TCM way is zerou2019ed out. This bit is reset-configurable like FixAutoZero bit when PORESETn is high and SYSRESETn is low. After that, it is modifiable by the core only if the FixAutoZero bit is clear and the corresponding WayEnable bit is also clear.
* |[7] |AZEROST |Auto-zeroing Status
* | | |This is a status bit that returns 1 when auto-zeroing is on-going
* | | |Similar to AutoFlushing bit
* | | |Accesses with target potentially residing in the TCM way are all wait-stated.
* |[8] |XOMERROR |XOM Error Flag
* | | |This is a status bit that returns 1 when the TCM way is configured as a LMB and is currently mapping a XOM region
* | | |This bit is read-only by the core
* | | |It is set/cleared automatically by the TCM logic.
* |[9] |ERROR |Operating Error Flag
* | | |0 = No error is recored
* | | |1 = An AHB error occurred during the last pre-loading (for LMB) or auto-flushing operation (for LMB or cache-way).
* | | |An AHB error occurred during the last pre-loading (for LMB) or auto-flushing operation (for LMB or cache-way)
* | | |The operation didnu2019t complete successfully
* | | |No error can occur to invalidation or zeroing operation
* | | |This bit is set by TCM logic and can only be cleared by the core.
* |[23:13] |LMBTAG |LMB TAG Base Address
* | | |When TCM way configure as LMB used, these bits define the base address of the mapped region
* | | |This tag is compared against the incoming address to determine if the address hits in the LMB.
* | | |Note: This field can be modified only when the corresponding WAYxEN bit is clear.
* | | |(default: 0) When CacheMode is clear, these bits store the base address of the mapped region
* | | |This tag is compared against the incoming address to determine if the address hits in the LMB
* | | |Depending on LMBSize setting, some of the bits are ignored.
* | | |LMBSize == 1K : all bits used
* | | |LMBSize == 2K : bit 10 ignored
* | | |LMBSize == 4K : bit 11:10 ignored
* | | |LMBSize == 8K : bit 12:10 ignored
* @var TCM_T::W0DMACTL
* Offset: 0x20 Tight Couple Memory Way0 DMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DMASIZE |DMA Size Selection Bit
* | | |This field indicate and size of moving external memory to LMB after DMA is trigged.
* | | |000 = Full TCM way
* | | |001 = 1/2 TCM way
* | | |010 = 1/4 TCM way
* | | |011 = 1/8 TCM way
* | | |100 = 1/16 TCM way
* | | |101 = 1/32 TCM way
* | | |110 = 1/64 TCM way
* | | |111 = 1/128 TCM way
* | | |Note: This bit can be modified only when the corresponding WAYxEN bit is clear
* | | |(default: 0) When the embedded DMA engine is triggered for either LMB preloading or auto-flushing, this field defines the size of the operation according to the following table
* | | |While a DMA operation is on-going, this field cannot be modified.
* |[23:4] |DMAADDR |DMA starting RAM address
* | | |When a LMB-related DMA operation is triggered, this field provides the starting RAM address of the operation
* | | |Depending on the setting of the WaySize and DMASize, not all bits are used
* | | |The following table lists the DMAAddr bits used to construct the base of the starting RAM address according to WaySize
* | | |While a DMA operation is on-going, this field cannot be modified.
* | | |WaySize / RAMBase 8K / {[23:13], 13u2019b0} 4K / {[23:12], 12u2019b0} 2K / {[23:11], 11u2019b0} 1K / {[23:10], 10u2019b0}
* | | |The following table lists the DMAAddr bits used as the offset for the RAM starting address
* | | |Note that the minimal DMA operation size is 16-byte (or 4-word).
* | | |Offset WaySize
* | | |DMASize 8K 4K 2K 1K
* | | |0 - - - -
* | | |1 [12] [11] [10] [9]
* | | |2 [12:11] [11:10] [10:9] [9:8]
* | | |3 [12:10] [11:9] [10:8] [9:7]
* | | |4 [12:9] [11:8] [10:7] [9:6]
* | | |5 [12:8] [11:7] [10:6] [9:5]
* | | |6 [12:7] [11:6] [10:5] [9:4]
* | | |7 [12:6] [11:5] [10:4] -
* |[30] |DMAFLUSH |Flushing DMA
* | | |When CacheMode bit is 0 (WayEnable bit 0 is OK), writing a 1 into this bit triggers a flushing DMA operation according to the setting in the DMASize and DMAAddr fields
* | | |This bit cannot be written 0 by M4
* | | |It is self-clearing when the DMA operation completes
* | | |While a preloading DMA is on-going, this bit is not modifiable.
* |[31] |DMAPRELD |Preloading DMA
* | | |When CacheMode bit is 0 (WayEnable bit 0 is OK), writing a 1 into this bit triggers a preloading DMA operation according to the setting in the DMASize and DMAAddr fields
* | | |This bit cannot be written 0 by M4
* | | |It is self-clearing when the DMA operation completes
* | | |While a flushing DMA is on-going, this bit is not modifiable.
* @var TCM_T::W1DMACTL
* Offset: 0x24 Tight Couple Memory Way1 DMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DMASIZE |DMA Size Selection Bit
* | | |This field indicate and size of moving external memory to LMB after DMA is trigged.
* | | |000 = Full TCM way
* | | |001 = 1/2 TCM way
* | | |010 = 1/4 TCM way
* | | |011 = 1/8 TCM way
* | | |100 = 1/16 TCM way
* | | |101 = 1/32 TCM way
* | | |110 = 1/64 TCM way
* | | |111 = 1/128 TCM way
* | | |Note: This bit can be modified only when the corresponding WAYxEN bit is clear
* | | |(default: 0) When the embedded DMA engine is triggered for either LMB preloading or auto-flushing, this field defines the size of the operation according to the following table
* | | |While a DMA operation is on-going, this field cannot be modified.
* |[23:4] |DMAADDR |DMA starting RAM address
* | | |When a LMB-related DMA operation is triggered, this field provides the starting RAM address of the operation
* | | |Depending on the setting of the WaySize and DMASize, not all bits are used
* | | |The following table lists the DMAAddr bits used to construct the base of the starting RAM address according to WaySize
* | | |While a DMA operation is on-going, this field cannot be modified.
* | | |WaySize / RAMBase 8K / {[23:13], 13u2019b0} 4K / {[23:12], 12u2019b0} 2K / {[23:11], 11u2019b0} 1K / {[23:10], 10u2019b0}
* | | |The following table lists the DMAAddr bits used as the offset for the RAM starting address
* | | |Note that the minimal DMA operation size is 16-byte (or 4-word).
* | | |Offset WaySize
* | | |DMASize 8K 4K 2K 1K
* | | |0 - - - -
* | | |1 [12] [11] [10] [9]
* | | |2 [12:11] [11:10] [10:9] [9:8]
* | | |3 [12:10] [11:9] [10:8] [9:7]
* | | |4 [12:9] [11:8] [10:7] [9:6]
* | | |5 [12:8] [11:7] [10:6] [9:5]
* | | |6 [12:7] [11:6] [10:5] [9:4]
* | | |7 [12:6] [11:5] [10:4] -
* |[30] |DMAFLUSH |Flushing DMA
* | | |When CacheMode bit is 0 (WayEnable bit 0 is OK), writing a 1 into this bit triggers a flushing DMA operation according to the setting in the DMASize and DMAAddr fields
* | | |This bit cannot be written 0 by M4
* | | |It is self-clearing when the DMA operation completes
* | | |While a preloading DMA is on-going, this bit is not modifiable.
* |[31] |DMAPRELD |Preloading DMA
* | | |When CacheMode bit is 0 (WayEnable bit 0 is OK), writing a 1 into this bit triggers a preloading DMA operation according to the setting in the DMASize and DMAAddr fields
* | | |This bit cannot be written 0 by M4
* | | |It is self-clearing when the DMA operation completes
* | | |While a flushing DMA is on-going, this bit is not modifiable.
* @var TCM_T::W2DMACTL
* Offset: 0x28 Tight Couple Memory Way2 DMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DMASIZE |DMA Size Selection Bit
* | | |This field indicate and size of moving external memory to LMB after DMA is trigged.
* | | |000 = Full TCM way
* | | |001 = 1/2 TCM way
* | | |010 = 1/4 TCM way
* | | |011 = 1/8 TCM way
* | | |100 = 1/16 TCM way
* | | |101 = 1/32 TCM way
* | | |110 = 1/64 TCM way
* | | |111 = 1/128 TCM way
* | | |Note: This bit can be modified only when the corresponding WAYxEN bit is clear
* | | |(default: 0) When the embedded DMA engine is triggered for either LMB preloading or auto-flushing, this field defines the size of the operation according to the following table
* | | |While a DMA operation is on-going, this field cannot be modified.
* |[23:4] |DMAADDR |DMA starting RAM address
* | | |When a LMB-related DMA operation is triggered, this field provides the starting RAM address of the operation
* | | |Depending on the setting of the WaySize and DMASize, not all bits are used
* | | |The following table lists the DMAAddr bits used to construct the base of the starting RAM address according to WaySize
* | | |While a DMA operation is on-going, this field cannot be modified.
* | | |WaySize / RAMBase 8K / {[23:13], 13u2019b0} 4K / {[23:12], 12u2019b0} 2K / {[23:11], 11u2019b0} 1K / {[23:10], 10u2019b0}
* | | |The following table lists the DMAAddr bits used as the offset for the RAM starting address
* | | |Note that the minimal DMA operation size is 16-byte (or 4-word).
* | | |Offset WaySize
* | | |DMASize 8K 4K 2K 1K
* | | |0 - - - -
* | | |1 [12] [11] [10] [9]
* | | |2 [12:11] [11:10] [10:9] [9:8]
* | | |3 [12:10] [11:9] [10:8] [9:7]
* | | |4 [12:9] [11:8] [10:7] [9:6]
* | | |5 [12:8] [11:7] [10:6] [9:5]
* | | |6 [12:7] [11:6] [10:5] [9:4]
* | | |7 [12:6] [11:5] [10:4] -
* |[30] |DMAFLUSH |Flushing DMA
* | | |When CacheMode bit is 0 (WayEnable bit 0 is OK), writing a 1 into this bit triggers a flushing DMA operation according to the setting in the DMASize and DMAAddr fields
* | | |This bit cannot be written 0 by M4
* | | |It is self-clearing when the DMA operation completes
* | | |While a preloading DMA is on-going, this bit is not modifiable.
* |[31] |DMAPRELD |Preloading DMA
* | | |When CacheMode bit is 0 (WayEnable bit 0 is OK), writing a 1 into this bit triggers a preloading DMA operation according to the setting in the DMASize and DMAAddr fields
* | | |This bit cannot be written 0 by M4
* | | |It is self-clearing when the DMA operation completes
* | | |While a flushing DMA is on-going, this bit is not modifiable.
* @var TCM_T::W3DMACTL
* Offset: 0x2C Tight Couple Memory Way3 DMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DMASIZE |DMA Size Selection Bit
* | | |This field indicate and size of moving external memory to LMB after DMA is trigged.
* | | |000 = Full TCM way
* | | |001 = 1/2 TCM way
* | | |010 = 1/4 TCM way
* | | |011 = 1/8 TCM way
* | | |100 = 1/16 TCM way
* | | |101 = 1/32 TCM way
* | | |110 = 1/64 TCM way
* | | |111 = 1/128 TCM way
* | | |Note: This bit can be modified only when the corresponding WAYxEN bit is clear
* | | |(default: 0) When the embedded DMA engine is triggered for either LMB preloading or auto-flushing, this field defines the size of the operation according to the following table
* | | |While a DMA operation is on-going, this field cannot be modified.
* |[23:4] |DMAADDR |DMA starting RAM address
* | | |When a LMB-related DMA operation is triggered, this field provides the starting RAM address of the operation
* | | |Depending on the setting of the WaySize and DMASize, not all bits are used
* | | |The following table lists the DMAAddr bits used to construct the base of the starting RAM address according to WaySize
* | | |While a DMA operation is on-going, this field cannot be modified.
* | | |WaySize / RAMBase 8K / {[23:13], 13u2019b0} 4K / {[23:12], 12u2019b0} 2K / {[23:11], 11u2019b0} 1K / {[23:10], 10u2019b0}
* | | |The following table lists the DMAAddr bits used as the offset for the RAM starting address
* | | |Note that the minimal DMA operation size is 16-byte (or 4-word).
* | | |Offset WaySize
* | | |DMASize 8K 4K 2K 1K
* | | |0 - - - -
* | | |1 [12] [11] [10] [9]
* | | |2 [12:11] [11:10] [10:9] [9:8]
* | | |3 [12:10] [11:9] [10:8] [9:7]
* | | |4 [12:9] [11:8] [10:7] [9:6]
* | | |5 [12:8] [11:7] [10:6] [9:5]
* | | |6 [12:7] [11:6] [10:5] [9:4]
* | | |7 [12:6] [11:5] [10:4] -
* |[30] |DMAFLUSH |Flushing DMA
* | | |When CacheMode bit is 0 (WayEnable bit 0 is OK), writing a 1 into this bit triggers a flushing DMA operation according to the setting in the DMASize and DMAAddr fields
* | | |This bit cannot be written 0 by M4
* | | |It is self-clearing when the DMA operation completes
* | | |While a preloading DMA is on-going, this bit is not modifiable.
* |[31] |DMAPRELD |Preloading DMA
* | | |When CacheMode bit is 0 (WayEnable bit 0 is OK), writing a 1 into this bit triggers a preloading DMA operation according to the setting in the DMASize and DMAAddr fields
* | | |This bit cannot be written 0 by M4
* | | |It is self-clearing when the DMA operation completes
* | | |While a flushing DMA is on-going, this bit is not modifiable.
*/
__IO uint32_t GCTL; /*!< [0x0000] Tight Couple Memory Control Register */
__I uint32_t RESERVE0[3];
__IO uint32_t WAYCTL[4]; /*!< [0x10-0x1c] Tight Couple Memory Way0 Control Register */
__IO uint32_t WDMACTL[4]; /*!< [0x20-0x2c] Tight Couple Memory Way0 DMA Control Register */
} TCM_T;
/**
@addtogroup TCM_CONST TCM Bit Field Definition
Constant Definitions for TCM Controller
@{ */
#define TCM_GCTL_WAYNUM_Pos (0) /*!< TCM_T::GCTL: WAYNUM Position */
#define TCM_GCTL_WAYNUM_Msk (0x3ul << TCM_GCTL_WAYNUM_Pos) /*!< TCM_T::GCTL: WAYNUM Mask */
#define TCM_GCTL_WAYSIZE_Pos (2) /*!< TCM_T::GCTL: WAYSIZE Position */
#define TCM_GCTL_WAYSIZE_Msk (0x3ul << TCM_GCTL_WAYSIZE_Pos) /*!< TCM_T::GCTL: WAYSIZE Mask */
#define TCM_GCTL_CACHECFG_Pos (4) /*!< TCM_T::GCTL: CACHECFG Position */
#define TCM_GCTL_CACHECFG_Msk (0x1ul << TCM_GCTL_CACHECFG_Pos) /*!< TCM_T::GCTL: CACHECFG Mask */
#define TCM_GCTL_FIXAZERO_Pos (5) /*!< TCM_T::GCTL: FIXAZERO Position */
#define TCM_GCTL_FIXAZERO_Msk (0x1ul << TCM_GCTL_FIXAZERO_Pos) /*!< TCM_T::GCTL: FIXAZERO Mask */
#define TCM_GCTL_WAY0EN_Pos (8) /*!< TCM_T::GCTL: WAY0EN Position */
#define TCM_GCTL_WAY0EN_Msk (0x1ul << TCM_GCTL_WAY0EN_Pos) /*!< TCM_T::GCTL: WAY0EN Mask */
#define TCM_GCTL_WAY1EN_Pos (9) /*!< TCM_T::GCTL: WAY1EN Position */
#define TCM_GCTL_WAY1EN_Msk (0x1ul << TCM_GCTL_WAY1EN_Pos) /*!< TCM_T::GCTL: WAY1EN Mask */
#define TCM_GCTL_WAY2EN_Pos (10) /*!< TCM_T::GCTL: WAY2EN Position */
#define TCM_GCTL_WAY2EN_Msk (0x1ul << TCM_GCTL_WAY2EN_Pos) /*!< TCM_T::GCTL: WAY2EN Mask */
#define TCM_GCTL_WAY3EN_Pos (11) /*!< TCM_T::GCTL: WAY3EN Position */
#define TCM_GCTL_WAY3EN_Msk (0x1ul << TCM_GCTL_WAY3EN_Pos) /*!< TCM_T::GCTL: WAY3EN Mask */
#define TCM_W0CTL_CACHEMD_Pos (0) /*!< TCM_T::W0CTL: CACHEMD Position */
#define TCM_W0CTL_CACHEMD_Msk (0x1ul << TCM_W0CTL_CACHEMD_Pos) /*!< TCM_T::W0CTL: CACHEMD Mask */
#define TCM_W0CTL_PRELD_Pos (1) /*!< TCM_T::W0CTL: PRELD Position */
#define TCM_W0CTL_PRELD_Msk (0x1ul << TCM_W0CTL_PRELD_Pos) /*!< TCM_T::W0CTL: PRELD Mask */
#define TCM_W0CTL_PRELDST_Pos (2) /*!< TCM_T::W0CTL: PRELDST Position */
#define TCM_W0CTL_PRELDST_Msk (0x1ul << TCM_W0CTL_PRELDST_Pos) /*!< TCM_T::W0CTL: PRELDST Mask */
#define TCM_W0CTL_INVALST_Pos (3) /*!< TCM_T::W0CTL: INVALST Position */
#define TCM_W0CTL_INVALST_Msk (0x1ul << TCM_W0CTL_INVALST_Pos) /*!< TCM_T::W0CTL: INVALST Mask */
#define TCM_W0CTL_AFLUSH_Pos (4) /*!< TCM_T::W0CTL: AFLUSH Position */
#define TCM_W0CTL_AFLUSH_Msk (0x1ul << TCM_W0CTL_AFLUSH_Pos) /*!< TCM_T::W0CTL: AFLUSH Mask */
#define TCM_W0CTL_AFLUSHST_Pos (5) /*!< TCM_T::W0CTL: AFLUSHST Position */
#define TCM_W0CTL_AFLUSHST_Msk (0x1ul << TCM_W0CTL_AFLUSHST_Pos) /*!< TCM_T::W0CTL: AFLUSHST Mask */
#define TCM_W0CTL_AZERO_Pos (6) /*!< TCM_T::W0CTL: AZERO Position */
#define TCM_W0CTL_AZERO_Msk (0x1ul << TCM_W0CTL_AZERO_Pos) /*!< TCM_T::W0CTL: AZERO Mask */
#define TCM_W0CTL_AZEROST_Pos (7) /*!< TCM_T::W0CTL: AZEROST Position */
#define TCM_W0CTL_AZEROST_Msk (0x1ul << TCM_W0CTL_AZEROST_Pos) /*!< TCM_T::W0CTL: AZEROST Mask */
#define TCM_W0CTL_XOMERROR_Pos (8) /*!< TCM_T::W0CTL: XOMERROR Position */
#define TCM_W0CTL_XOMERROR_Msk (0x1ul << TCM_W0CTL_XOMERROR_Pos) /*!< TCM_T::W0CTL: XOMERROR Mask */
#define TCM_W0CTL_ERROR_Pos (9) /*!< TCM_T::W0CTL: ERROR Position */
#define TCM_W0CTL_ERROR_Msk (0x1ul << TCM_W0CTL_ERROR_Pos) /*!< TCM_T::W0CTL: ERROR Mask */
#define TCM_W0CTL_LMBTAG_Pos (13) /*!< TCM_T::W0CTL: LMBTAG Position */
#define TCM_W0CTL_LMBTAG_Msk (0x7fful << TCM_W0CTL_LMBTAG_Pos) /*!< TCM_T::W0CTL: LMBTAG Mask */
#define TCM_W1CTL_CACHEMD_Pos (0) /*!< TCM_T::W1CTL: CACHEMD Position */
#define TCM_W1CTL_CACHEMD_Msk (0x1ul << TCM_W1CTL_CACHEMD_Pos) /*!< TCM_T::W1CTL: CACHEMD Mask */
#define TCM_W1CTL_PRELD_Pos (1) /*!< TCM_T::W1CTL: PRELD Position */
#define TCM_W1CTL_PRELD_Msk (0x1ul << TCM_W1CTL_PRELD_Pos) /*!< TCM_T::W1CTL: PRELD Mask */
#define TCM_W1CTL_PRELDST_Pos (2) /*!< TCM_T::W1CTL: PRELDST Position */
#define TCM_W1CTL_PRELDST_Msk (0x1ul << TCM_W1CTL_PRELDST_Pos) /*!< TCM_T::W1CTL: PRELDST Mask */
#define TCM_W1CTL_INVALST_Pos (3) /*!< TCM_T::W1CTL: INVALST Position */
#define TCM_W1CTL_INVALST_Msk (0x1ul << TCM_W1CTL_INVALST_Pos) /*!< TCM_T::W1CTL: INVALST Mask */
#define TCM_W1CTL_AFLUSH_Pos (4) /*!< TCM_T::W1CTL: AFLUSH Position */
#define TCM_W1CTL_AFLUSH_Msk (0x1ul << TCM_W1CTL_AFLUSH_Pos) /*!< TCM_T::W1CTL: AFLUSH Mask */
#define TCM_W1CTL_AFLUSHST_Pos (5) /*!< TCM_T::W1CTL: AFLUSHST Position */
#define TCM_W1CTL_AFLUSHST_Msk (0x1ul << TCM_W1CTL_AFLUSHST_Pos) /*!< TCM_T::W1CTL: AFLUSHST Mask */
#define TCM_W1CTL_AZERO_Pos (6) /*!< TCM_T::W1CTL: AZERO Position */
#define TCM_W1CTL_AZERO_Msk (0x1ul << TCM_W1CTL_AZERO_Pos) /*!< TCM_T::W1CTL: AZERO Mask */
#define TCM_W1CTL_AZEROST_Pos (7) /*!< TCM_T::W1CTL: AZEROST Position */
#define TCM_W1CTL_AZEROST_Msk (0x1ul << TCM_W1CTL_AZEROST_Pos) /*!< TCM_T::W1CTL: AZEROST Mask */
#define TCM_W1CTL_XOMERROR_Pos (8) /*!< TCM_T::W1CTL: XOMERROR Position */
#define TCM_W1CTL_XOMERROR_Msk (0x1ul << TCM_W1CTL_XOMERROR_Pos) /*!< TCM_T::W1CTL: XOMERROR Mask */
#define TCM_W1CTL_ERROR_Pos (9) /*!< TCM_T::W1CTL: ERROR Position */
#define TCM_W1CTL_ERROR_Msk (0x1ul << TCM_W1CTL_ERROR_Pos) /*!< TCM_T::W1CTL: ERROR Mask */
#define TCM_W1CTL_LMBTAG_Pos (13) /*!< TCM_T::W1CTL: LMBTAG Position */
#define TCM_W1CTL_LMBTAG_Msk (0x7fful << TCM_W1CTL_LMBTAG_Pos) /*!< TCM_T::W1CTL: LMBTAG Mask */
#define TCM_W2CTL_CACHEMD_Pos (0) /*!< TCM_T::W2CTL: CACHEMD Position */
#define TCM_W2CTL_CACHEMD_Msk (0x1ul << TCM_W2CTL_CACHEMD_Pos) /*!< TCM_T::W2CTL: CACHEMD Mask */
#define TCM_W2CTL_PRELD_Pos (1) /*!< TCM_T::W2CTL: PRELD Position */
#define TCM_W2CTL_PRELD_Msk (0x1ul << TCM_W2CTL_PRELD_Pos) /*!< TCM_T::W2CTL: PRELD Mask */
#define TCM_W2CTL_PRELDST_Pos (2) /*!< TCM_T::W2CTL: PRELDST Position */
#define TCM_W2CTL_PRELDST_Msk (0x1ul << TCM_W2CTL_PRELDST_Pos) /*!< TCM_T::W2CTL: PRELDST Mask */
#define TCM_W2CTL_INVALST_Pos (3) /*!< TCM_T::W2CTL: INVALST Position */
#define TCM_W2CTL_INVALST_Msk (0x1ul << TCM_W2CTL_INVALST_Pos) /*!< TCM_T::W2CTL: INVALST Mask */
#define TCM_W2CTL_AFLUSH_Pos (4) /*!< TCM_T::W2CTL: AFLUSH Position */
#define TCM_W2CTL_AFLUSH_Msk (0x1ul << TCM_W2CTL_AFLUSH_Pos) /*!< TCM_T::W2CTL: AFLUSH Mask */
#define TCM_W2CTL_AFLUSHST_Pos (5) /*!< TCM_T::W2CTL: AFLUSHST Position */
#define TCM_W2CTL_AFLUSHST_Msk (0x1ul << TCM_W2CTL_AFLUSHST_Pos) /*!< TCM_T::W2CTL: AFLUSHST Mask */
#define TCM_W2CTL_AZERO_Pos (6) /*!< TCM_T::W2CTL: AZERO Position */
#define TCM_W2CTL_AZERO_Msk (0x1ul << TCM_W2CTL_AZERO_Pos) /*!< TCM_T::W2CTL: AZERO Mask */
#define TCM_W2CTL_AZEROST_Pos (7) /*!< TCM_T::W2CTL: AZEROST Position */
#define TCM_W2CTL_AZEROST_Msk (0x1ul << TCM_W2CTL_AZEROST_Pos) /*!< TCM_T::W2CTL: AZEROST Mask */
#define TCM_W2CTL_XOMERROR_Pos (8) /*!< TCM_T::W2CTL: XOMERROR Position */
#define TCM_W2CTL_XOMERROR_Msk (0x1ul << TCM_W2CTL_XOMERROR_Pos) /*!< TCM_T::W2CTL: XOMERROR Mask */
#define TCM_W2CTL_ERROR_Pos (9) /*!< TCM_T::W2CTL: ERROR Position */
#define TCM_W2CTL_ERROR_Msk (0x1ul << TCM_W2CTL_ERROR_Pos) /*!< TCM_T::W2CTL: ERROR Mask */
#define TCM_W2CTL_LMBTAG_Pos (13) /*!< TCM_T::W2CTL: LMBTAG Position */
#define TCM_W2CTL_LMBTAG_Msk (0x7fful << TCM_W2CTL_LMBTAG_Pos) /*!< TCM_T::W2CTL: LMBTAG Mask */
#define TCM_W3CTL_CACHEMD_Pos (0) /*!< TCM_T::W3CTL: CACHEMD Position */
#define TCM_W3CTL_CACHEMD_Msk (0x1ul << TCM_W3CTL_CACHEMD_Pos) /*!< TCM_T::W3CTL: CACHEMD Mask */
#define TCM_W3CTL_PRELD_Pos (1) /*!< TCM_T::W3CTL: PRELD Position */
#define TCM_W3CTL_PRELD_Msk (0x1ul << TCM_W3CTL_PRELD_Pos) /*!< TCM_T::W3CTL: PRELD Mask */
#define TCM_W3CTL_PRELDST_Pos (2) /*!< TCM_T::W3CTL: PRELDST Position */
#define TCM_W3CTL_PRELDST_Msk (0x1ul << TCM_W3CTL_PRELDST_Pos) /*!< TCM_T::W3CTL: PRELDST Mask */
#define TCM_W3CTL_INVALST_Pos (3) /*!< TCM_T::W3CTL: INVALST Position */
#define TCM_W3CTL_INVALST_Msk (0x1ul << TCM_W3CTL_INVALST_Pos) /*!< TCM_T::W3CTL: INVALST Mask */
#define TCM_W3CTL_AFLUSH_Pos (4) /*!< TCM_T::W3CTL: AFLUSH Position */
#define TCM_W3CTL_AFLUSH_Msk (0x1ul << TCM_W3CTL_AFLUSH_Pos) /*!< TCM_T::W3CTL: AFLUSH Mask */
#define TCM_W3CTL_AFLUSHST_Pos (5) /*!< TCM_T::W3CTL: AFLUSHST Position */
#define TCM_W3CTL_AFLUSHST_Msk (0x1ul << TCM_W3CTL_AFLUSHST_Pos) /*!< TCM_T::W3CTL: AFLUSHST Mask */
#define TCM_W3CTL_AZERO_Pos (6) /*!< TCM_T::W3CTL: AZERO Position */
#define TCM_W3CTL_AZERO_Msk (0x1ul << TCM_W3CTL_AZERO_Pos) /*!< TCM_T::W3CTL: AZERO Mask */
#define TCM_W3CTL_AZEROST_Pos (7) /*!< TCM_T::W3CTL: AZEROST Position */
#define TCM_W3CTL_AZEROST_Msk (0x1ul << TCM_W3CTL_AZEROST_Pos) /*!< TCM_T::W3CTL: AZEROST Mask */
#define TCM_W3CTL_XOMERROR_Pos (8) /*!< TCM_T::W3CTL: XOMERROR Position */
#define TCM_W3CTL_XOMERROR_Msk (0x1ul << TCM_W3CTL_XOMERROR_Pos) /*!< TCM_T::W3CTL: XOMERROR Mask */
#define TCM_W3CTL_ERROR_Pos (9) /*!< TCM_T::W3CTL: ERROR Position */
#define TCM_W3CTL_ERROR_Msk (0x1ul << TCM_W3CTL_ERROR_Pos) /*!< TCM_T::W3CTL: ERROR Mask */
#define TCM_W3CTL_LMBTAG_Pos (13) /*!< TCM_T::W3CTL: LMBTAG Position */
#define TCM_W3CTL_LMBTAG_Msk (0x7fful << TCM_W3CTL_LMBTAG_Pos) /*!< TCM_T::W3CTL: LMBTAG Mask */
#define TCM_W0DMACTL_DMASIZE_Pos (0) /*!< TCM_T::W0DMACTL: DMASIZE Position */
#define TCM_W0DMACTL_DMASIZE_Msk (0x1ul << TCM_W0DMACTL_DMASIZE_Pos) /*!< TCM_T::W0DMACTL: DMASIZE Mask */
#define TCM_W0DMACTL_DMAADDR_Pos (4) /*!< TCM_T::W0DMACTL: DMAADDR Position */
#define TCM_W0DMACTL_DMAADDR_Msk (0xffffful << TCM_W0DMACTL_DMAADDR_Pos) /*!< TCM_T::W0DMACTL: DMAADDR Mask */
#define TCM_W0DMACTL_DMAFLUSH_Pos (30) /*!< TCM_T::W0DMACTL: DMAFLUSH Position */
#define TCM_W0DMACTL_DMAFLUSH_Msk (0x1ul << TCM_W0DMACTL_DMAFLUSH_Pos) /*!< TCM_T::W0DMACTL: DMAFLUSH Mask */
#define TCM_W0DMACTL_DMAPRELD_Pos (31) /*!< TCM_T::W0DMACTL: DMAPRELD Position */
#define TCM_W0DMACTL_DMAPRELD_Msk (0x1ul << TCM_W0DMACTL_DMAPRELD_Pos) /*!< TCM_T::W0DMACTL: DMAPRELD Mask */
#define TCM_W1DMACTL_DMASIZE_Pos (0) /*!< TCM_T::W1DMACTL: DMASIZE Position */
#define TCM_W1DMACTL_DMASIZE_Msk (0x1ul << TCM_W1DMACTL_DMASIZE_Pos) /*!< TCM_T::W1DMACTL: DMASIZE Mask */
#define TCM_W1DMACTL_DMAADDR_Pos (4) /*!< TCM_T::W1DMACTL: DMAADDR Position */
#define TCM_W1DMACTL_DMAADDR_Msk (0xffffful << TCM_W1DMACTL_DMAADDR_Pos) /*!< TCM_T::W1DMACTL: DMAADDR Mask */
#define TCM_W1DMACTL_DMAFLUSH_Pos (30) /*!< TCM_T::W1DMACTL: DMAFLUSH Position */
#define TCM_W1DMACTL_DMAFLUSH_Msk (0x1ul << TCM_W1DMACTL_DMAFLUSH_Pos) /*!< TCM_T::W1DMACTL: DMAFLUSH Mask */
#define TCM_W1DMACTL_DMAPRELD_Pos (31) /*!< TCM_T::W1DMACTL: DMAPRELD Position */
#define TCM_W1DMACTL_DMAPRELD_Msk (0x1ul << TCM_W1DMACTL_DMAPRELD_Pos) /*!< TCM_T::W1DMACTL: DMAPRELD Mask */
#define TCM_W2DMACTL_DMASIZE_Pos (0) /*!< TCM_T::W2DMACTL: DMASIZE Position */
#define TCM_W2DMACTL_DMASIZE_Msk (0x1ul << TCM_W2DMACTL_DMASIZE_Pos) /*!< TCM_T::W2DMACTL: DMASIZE Mask */
#define TCM_W2DMACTL_DMAADDR_Pos (4) /*!< TCM_T::W2DMACTL: DMAADDR Position */
#define TCM_W2DMACTL_DMAADDR_Msk (0xffffful << TCM_W2DMACTL_DMAADDR_Pos) /*!< TCM_T::W2DMACTL: DMAADDR Mask */
#define TCM_W2DMACTL_DMAFLUSH_Pos (30) /*!< TCM_T::W2DMACTL: DMAFLUSH Position */
#define TCM_W2DMACTL_DMAFLUSH_Msk (0x1ul << TCM_W2DMACTL_DMAFLUSH_Pos) /*!< TCM_T::W2DMACTL: DMAFLUSH Mask */
#define TCM_W2DMACTL_DMAPRELD_Pos (31) /*!< TCM_T::W2DMACTL: DMAPRELD Position */
#define TCM_W2DMACTL_DMAPRELD_Msk (0x1ul << TCM_W2DMACTL_DMAPRELD_Pos) /*!< TCM_T::W2DMACTL: DMAPRELD Mask */
#define TCM_W3DMACTL_DMASIZE_Pos (0) /*!< TCM_T::W3DMACTL: DMASIZE Position */
#define TCM_W3DMACTL_DMASIZE_Msk (0x1ul << TCM_W3DMACTL_DMASIZE_Pos) /*!< TCM_T::W3DMACTL: DMASIZE Mask */
#define TCM_W3DMACTL_DMAADDR_Pos (4) /*!< TCM_T::W3DMACTL: DMAADDR Position */
#define TCM_W3DMACTL_DMAADDR_Msk (0xffffful << TCM_W3DMACTL_DMAADDR_Pos) /*!< TCM_T::W3DMACTL: DMAADDR Mask */
#define TCM_W3DMACTL_DMAFLUSH_Pos (30) /*!< TCM_T::W3DMACTL: DMAFLUSH Position */
#define TCM_W3DMACTL_DMAFLUSH_Msk (0x1ul << TCM_W3DMACTL_DMAFLUSH_Pos) /*!< TCM_T::W3DMACTL: DMAFLUSH Mask */
#define TCM_W3DMACTL_DMAPRELD_Pos (31) /*!< TCM_T::W3DMACTL: DMAPRELD Position */
#define TCM_W3DMACTL_DMAPRELD_Msk (0x1ul << TCM_W3DMACTL_DMAPRELD_Pos) /*!< TCM_T::W3DMACTL: DMAPRELD Mask */
/**@}*/ /* TCM_CONST */
/**@}*/ /* end of TCM register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __ACMP_REG_H__ */

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/**************************************************************************//**
* @file trng_reg.h
* @version V1.00
* @brief TRNG register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __TRNG_REG_H__
#define __TRNG_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- True Random Number Generator -------------------------*/
/**
@addtogroup TRNG True Random Number Generator(TRNG)
Memory Mapped Structure for TRNG Controller
@{ */
typedef struct
{
/**
* @var TRNG_T::CTL
* Offset: 0x00 TRNG Control Register and Status
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TRNGEN |Random Number Generator Enable Bit
* | | |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became 1.
* | | |0 = TRNG disabled.
* | | |1 = TRNG enabled.
* | | |Note: TRNGEN is an enable bit of digital part
* | | |When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption.
* |[1] |DVIF |Data Valid (Read Only)
* | | |0 = Data is not valid. Reading from RNGD returns 0x00000000.
* | | |1 = Data is valid. A valid random number can be read form RNGD.
* | | |This bit is cleared to u20180u2019 by read TRNG_DATA.
* |[5:2] |CLKP |Clock Prescaler
* | | |The CLKP is the peripheral clock frequency range for the selected value , the CLKP must higher than or equal to the actual peripheral clock frequency (for correct random bit generation)
* | | |To change the CLKP contents, first set TRNGEN bit to 0 and then change CLKP; finally, set TRNGEN bit to 1 to re-enable the TRNG module.
* | | |0000 = 80 ~ 100 MHz.
* | | |0001 = 60 ~ 80 MHz.
* | | |0010 = 50 ~60 MHz.
* | | |0011 = 40 ~50 MHz.
* | | |0100 = 30 ~40 MHz.
* | | |0101 = 25 ~30 MHz.
* | | |0110 = 20 ~25 MHz.
* | | |0111 = 15 ~20 MHz.
* | | |1000 = 12 ~15 MHz.
* | | |1001 = 9 ~12 MHz.
* | | |1010 = 7 ~9 MHz.
* | | |1011 = 6 ~7 MHz.
* | | |1100 = 5 ~6 MHz.
* | | |1101 = 4 ~5 MHz.
* | | |1111 = Reserved.
* |[6] |DVIEN |Data Valid Interrupt Enable Bit
* | | |0 = Interrupt disabled..
* | | |1 = Interrupt enabled.
* |[7] |READY |Random Number Generator Ready (Read Only)
* | | |After ACT (TRNG_ACT[7]) bit is set, the READY bit become to 1 after a delay of 90us~120us.
* | | |0 = RNG is not ready or was not activated.
* | | |1 = RNG is ready to be enabled..
* |[31:8] |Reversed |Reversed
* @var TRNG_T::DATA
* Offset: 0x04 TRNG Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DATA |Random Number Generator Data (Read Only)
* | | |The DATA store the random number generated by TRNG and can be read only once.
* @var TRNG_T::ACT
* Offset: 0x0C TRNG Activation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |VER |TRNG Version
* | | |TRNG version number is dependent on TRNG module.
* | | |0x02:(Current Version Number)
* |[7] |ACT |Random Number Generator Activation
* | | |After enable the ACT bit, it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1.
* | | |0 = TRNG inactive.
* | | |1 = TRNG active.
* | | |Note: ACT is an enable bit of analog part
* | | |When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption.
*/
__IO uint32_t CTL; /*!< [0x0000] TRNG Control Register and Status */
__I uint32_t DATA; /*!< [0x0004] TRNG Data Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t ACT; /*!< [0x000c] TRNG Activation Register */
} TRNG_T;
/**
@addtogroup TRNG_CONST TRNG Bit Field Definition
Constant Definitions for TRNG Controller
@{ */
#define TRNG_CTL_TRNGEN_Pos (0) /*!< TRNG_T::CTL: TRNGEN Position */
#define TRNG_CTL_TRNGEN_Msk (0x1ul << TRNG_CTL_TRNGEN_Pos) /*!< TRNG_T::CTL: TRNGEN Mask */
#define TRNG_CTL_DVIF_Pos (1) /*!< TRNG_T::CTL: DVIF Position */
#define TRNG_CTL_DVIF_Msk (0x1ul << TRNG_CTL_DVIF_Pos) /*!< TRNG_T::CTL: DVIF Mask */
#define TRNG_CTL_CLKPSC_Pos (2) /*!< TRNG_T::CTL: CLKPSC Position */
#define TRNG_CTL_CLKPSC_Msk (0xful << TRNG_CTL_CLKP_Pos) /*!< TRNG_T::CTL: CLKPSC Mask */
#define TRNG_CTL_DVIEN_Pos (6) /*!< TRNG_T::CTL: DVIEN Position */
#define TRNG_CTL_DVIEN_Msk (0x1ul << TRNG_CTL_DVIEN_Pos) /*!< TRNG_T::CTL: DVIEN Mask */
#define TRNG_CTL_READY_Pos (7) /*!< TRNG_T::CTL: READY Position */
#define TRNG_CTL_READY_Msk (0x1ul << TRNG_CTL_READY_Pos) /*!< TRNG_T::CTL: READY Mask */
#define TRNG_CTL_Reversed_Pos (8) /*!< TRNG_T::CTL: Reversed Position */
#define TRNG_CTL_Reversed_Msk (0xfffffful << TRNG_CTL_Reversed_Pos) /*!< TRNG_T::CTL: Reversed Mask */
#define TRNG_DATA_DATA_Pos (0) /*!< TRNG_T::DATA: DATA Position */
#define TRNG_DATA_DATA_Msk (0xfful << TRNG_DATA_DATA_Pos) /*!< TRNG_T::DATA: DATA Mask */
#define TRNG_ACT_VER_Pos (0) /*!< TRNG_T::ACT: VER Position */
#define TRNG_ACT_VER_Msk (0x7ful << TRNG_ACT_VER_Pos) /*!< TRNG_T::ACT: VER Mask */
#define TRNG_ACT_ACT_Pos (7) /*!< TRNG_T::ACT: ACT Position */
#define TRNG_ACT_ACT_Msk (0x1ul << TRNG_ACT_ACT_Pos) /*!< TRNG_T::ACT: ACT Mask */
/**@}*/ /* TRNG_CONST */
/**@}*/ /* end of TRNG register group */
/**@}*/ /* end of REGISTER group */
#endif /* __TRNG_REG_H__ */

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/**************************************************************************//**
* @file ui2c_reg.h
* @version V1.00
* @brief UI2C register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __UI2C_REG_H__
#define __UI2C_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup UI2C I2C Mode of USCI Controller(UI2C)
Memory Mapped Structure for UI2C Controller
@{ */
typedef struct
{
/**
* @var UI2C_T::CTL
* Offset: 0x00 USCI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |FUNMODE |Function Mode
* | | |This bit field selects the protocol for this USCI controller
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
* | | |001 = The SPI protocol is selected.
* | | |010 = The UART protocol is selected.
* | | |100 = The I2C protocol is selected.
* | | |Note: Other bit combinations are reserved.
* @var UI2C_T::BRGEN
* Offset: 0x08 USCI Baud Rate Generator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RCLKSEL |Reference Clock Source Selection
* | | |This bit selects the source signal of reference clock (fREF_CLK).
* | | |0 = Peripheral device clock fPCLK.
* | | |1 = Reserved.
* |[1] |PTCLKSEL |Protocol Clock Source Selection
* | | |This bit selects the source signal of protocol clock (fPROT_CLK).
* | | |0 = Reference clock fREF_CLK.
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
* | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
* | | |00 = fSAMP_CLK = fDIV_CLK.
* | | |01 = fSAMP_CLK = fPROT_CLK.
* | | |10 = fSAMP_CLK = fSCLK.
* | | |11 = fSAMP_CLK = fREF_CLK.
* |[4] |TMCNTEN |Time Measurement Counter Enable Bit
* | | |This bit enables the 10-bit timing measurement counter.
* | | |0 = Time measurement counter is Disabled.
* | | |1 = Time measurement counter is Enabled.
* |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection
* | | |0 = Time measurement counter with fPROT_CLK.
* | | |1 = Time measurement counter with fDIV_CLK.
* |[9:8] |PDSCNT |Pre-divider for Sample Counter
* | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK
* | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
* |[14:10] |DSCNT |Denominator for Sample Counter
* | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
* | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
* | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value
* |[25:16] |CLKDIV |Clock Divider
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
* | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled
* | | |The revised value is the average bit time between bit 5 and bit 6
* | | |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate.
* @var UI2C_T::LINECTL
* Offset: 0x2C USCI Line Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LSB |LSB First Transmission Selection
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
* |[11:8] |DWIDTH |Word Length of Transmission
* | | |This bit field defines the data word length (amount of bits) for reception and transmission
* | | |The data word is always right-aligned in the data buffer
* | | |USCI support word length from 4 to 16 bits.
* | | |0x0: The data word contains 16 bits located at bit positions [15:0].
* | | |0x1: Reserved.
* | | |0x2: Reserved.
* | | |0x3: Reserved.
* | | |0x4: The data word contains 4 bits located at bit positions [3:0].
* | | |0x5: The data word contains 5 bits located at bit positions [4:0].
* | | |...
* | | |0xF: The data word contains 15 bits located at bit positions [14:0].
* | | |Note: In UART protocol, the length can be configured as 6~13 bits
* | | |And in I2C protocol, the length fixed as 8 bits.
* @var UI2C_T::TXDAT
* Offset: 0x30 USCI Transmit Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXDAT |Transmit Data
* | | |Software can use this bit field to write 16-bit transmit data for transmission.
* @var UI2C_T::RXDAT
* Offset: 0x34 USCI Receive Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RXDAT |Received Data
* | | |This bit field monitors the received data which stored in receive data buffer.
* | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
* | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]).
* @var UI2C_T::DEVADDR0
* Offset: 0x44 USCI Device Address Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |DEVADDR |Device Address
* | | |In I2C protocol, this bit field contains the programmed slave address
* | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
* | | |Then the second address byte is also compared to DEVADDR[7:0].
* | | |Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
* | | |Note 2: When software set 10'h000, the address can not be used.
* @var UI2C_T::DEVADDR1
* Offset: 0x48 USCI Device Address Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |DEVADDR |Device Address
* | | |In I2C protocol, this bit field contains the programmed slave address
* | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
* | | |Then the second address byte is also compared to DEVADDR[7:0].
* | | |Note 1: The DEVADDR [9:7] must be set 3'000 when I2C operating in 7-bit address mode.
* | | |Note 2: When software set 10'h000, the address can not be used.
* @var UI2C_T::ADDRMSK0
* Offset: 0x4C USCI Device Address Mask Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |ADDRMSK |USCI Device Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |USCI support multiple address recognition with two address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var UI2C_T::ADDRMSK1
* Offset: 0x50 USCI Device Address Mask Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |ADDRMSK |USCI Device Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |USCI support multiple address recognition with two address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var UI2C_T::WKCTL
* Offset: 0x54 USCI Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[1] |WKADDREN |Wake-up Address Match Enable Bit
* | | |0 = The chip is woken up according data toggle.
* | | |1 = The chip is woken up according address match.
* @var UI2C_T::WKSTS
* Offset: 0x58 USCI Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKF |Wake-up Flag
* | | |When chip is woken up from Power-down mode, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* @var UI2C_T::PROTCTL
* Offset: 0x5C USCI Protocol Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GCFUNC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[1] |AA |Assert Acknowledge Control
* | | |When AA=1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
* | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
* |[2] |STO |I2C STOP Control
* | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically
* | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode when bus error (USCI_PROTSTS.ERRIF = 1).
* |[3] |STA |I2C START Control
* | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
* |[4] |ADDR10EN |Address 10-bit Function Enable Bit
* | | |0 = Address match 10 bit function is disabled.
* | | |1 = Address match 10 bit function is enabled.
* |[5] |PTRG |I2C Protocol Trigger (Write Only)
* | | |When a new state is present in the USCI_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested
* | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
* | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead.
* | | |1 = I2C's stretch active.
* |[8] |SCLOUTEN |SCL Output Enable Bit
* | | |This bit enables monitor pulling SCL to low
* | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
* | | |0 = SCL output will be forced high due to open drain mechanism.
* | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt.
* |[9] |MONEN |Monitor Mode Enable Bit
* | | |This bit enables monitor mode
* | | |In monitor mode the SDA output will be put in high impedance mode
* | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.
* | | |0 = The monitor mode is disabled.
* | | |1 = The monitor mode is enabled.
* | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
* |[25:16] |TOCNT |Time-out Clock Cycle
* | | |This bit field indicates how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) when each interrupt flags are clear
* | | |The time-out is enable when TOCNT bigger than 0.
* | | |Note: The TMCNTSRC (USCI_BRGEN [5]) must be set zero on I2C mode.
* |[31] |PROTEN |I2C Protocol Enable Bit
* | | |0 = I2C Protocol disable.
* | | |1 = I2C Protocol enable.
* @var UI2C_T::PROTIEN
* Offset: 0x60 USCI Protocol Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOIEN |Time-out Interrupt Enable Control
* | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event.
* | | |0 = The time-out interrupt is disabled.
* | | |1 = The time-out interrupt is enabled.
* |[1] |STARIEN |Start Condition Received Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if a start condition is detected.
* | | |0 = The start condition interrupt is disabled.
* | | |1 = The start condition interrupt is enabled.
* |[2] |STORIEN |Stop Condition Received Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if a stop condition is detected.
* | | |0 = The stop condition interrupt is disabled.
* | | |1 = The stop condition interrupt is enabled.
* |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.
* | | |0 = The non - acknowledge interrupt is disabled.
* | | |1 = The non - acknowledge interrupt is enabled.
* |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
* | | |0 = The arbitration lost interrupt is disabled.
* | | |1 = The arbitration lost interrupt is enabled.
* |[5] |ERRIEN |Error Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (USCI_PROTSTS [16])).
* | | |0 = The error interrupt is disabled.
* | | |1 = The error interrupt is enabled.
* |[6] |ACKIEN |Acknowledge Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
* | | |0 = The acknowledge interrupt is disabled.
* | | |1 = The acknowledge interrupt is enabled.
* @var UI2C_T::PROTSTS
* Offset: 0x64 USCI Protocol Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5] |TOIF |Time-out Interrupt Flag
* | | |0 = A time-out interrupt status has not occurred.
* | | |1 = A time-out interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit
* |[6] |ONBUSY |On Bus Busy
* | | |Indicates that a communication is in progress on the bus
* | | |It is set by hardware when a START condition is detected
* | | |It is cleared by hardware when a STOP condition is detected
* | | |0 = The bus is IDLE (both SCLK and SDA High).
* | | |1 = The bus is busy.
* |[8] |STARIF |Start Condition Received Interrupt Flag
* | | |This bit indicates that a start condition or repeated start condition has been detected on master mode
* | | |However, this bit also indicates that a repeated start condition has been detected on slave mode.
* | | |A protocol interrupt can be generated if USCI_PROTCTL.STARIEN = 1.
* | | |0 = A start condition has not yet been detected.
* | | |1 = A start condition has been detected.
* | | |It is cleared by software writing one into this bit
* |[9] |STORIF |Stop Condition Received Interrupt Flag
* | | |This bit indicates that a stop condition has been detected on the I2C bus lines
* | | |A protocol interrupt can be generated if USCI_PROTCTL.STORIEN = 1.
* | | |0 = A stop condition has not yet been detected.
* | | |1 = A stop condition has been detected.
* | | |It is cleared by software writing one into this bit
* | | |Note: This bit is set when slave RX mode.
* |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag
* | | |This bit indicates that a non - acknowledge has been received in master mode
* | | |A protocol interrupt can be generated if USCI_PROTCTL.NACKIEN = 1.
* | | |0 = A non - acknowledge has not been received.
* | | |1 = A non - acknowledge has been received.
* | | |It is cleared by software writing one into this bit
* |[11] |ARBLOIF |Arbitration Lost Interrupt Flag
* | | |This bit indicates that an arbitration has been lost
* | | |A protocol interrupt can be generated if USCI_PROTCTL.ARBLOIEN = 1.
* | | |0 = An arbitration has not been lost.
* | | |1 = An arbitration has been lost.
* | | |It is cleared by software writing one into this bit
* |[12] |ERRIF |Error Interrupt Flag
* | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
* | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit
* | | |A protocol interrupt can be generated if USCI_PROTCTL.ERRIEN = 1.
* | | |0 = An I2C error has not been detected.
* | | |1 = An I2C error has been detected.
* | | |It is cleared by software writing one into this bit
* | | |Note: This bit is set when slave mode, user must write one into STO register to the defined "not addressed" slave mode.
* |[13] |ACKIF |Acknowledge Received Interrupt Flag
* | | |This bit indicates that an acknowledge has been received in master mode
* | | |A protocol interrupt can be generated if USCI_PROTCTL.ACKIEN = 1.
* | | |0 = An acknowledge has not been received.
* | | |1 = An acknowledge has been received.
* | | |It is cleared by software writing one into this bit
* |[14] |SLASEL |Slave Select Status
* | | |This bit indicates that this device has been selected as slave.
* | | |0 = The device is not selected as slave.
* | | |1 = The device is selected as slave.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
* |[15] |SLAREAD |Slave Read Request Status
* | | |This bit indicates that a slave read request has been detected.
* | | |0 = A slave R/W bit is 1 has not been detected.
* | | |1 = A slave R/W bit is 1 has been detected.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
* |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done
* | | |0 = The ACK bit cycle of address match frame isn't done.
* | | |1 = The ACK bit cycle of address match frame is done in power-down.
* | | |Note: This bit can't release when WKUPIF is set.
* |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame
* | | |0 = Write command be record on the address match wakeup frame.
* | | |1 = Read command be record on the address match wakeup frame.
* |[18] |BUSHANG |Bus Hang-up
* | | |This bit indicates bus hang-up status
* | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK
* | | |The hang-up counter will count to overflow and set this bit when SDA is low
* | | |The counter will be reset by falling edge of SCL signal.
* | | |0 = The bus is normal status for transmission.
* | | |1 = The bus is hang-up status for transmission.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
* |[19] |ERRARBLO |Error Arbitration Lost
* | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor
* | | |The I2C can send start condition when ERRARBLO is set
* | | |Thus this bit doesn't be cared on slave mode.
* | | |0 = The bus is normal status for transmission.
* | | |1 = The bus is error arbitration lost status for transmission.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
* @var UI2C_T::ADMAT
* Offset: 0x88 I2C Slave Match Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADMAT0 |USCI Address 0 Match Status Register
* | | |When address 0 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[1] |ADMAT1 |USCI Address 1 Match Status Register
* | | |When address 1 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* @var UI2C_T::TMCTL
* Offset: 0x8C I2C Timing Configure Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |STCTL |Setup Time Configure Control Register
* | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.
* | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK.
* |[24:16] |HTCTL |Hold Time Configure Control Register
* | | |This field is used to generate the delay timing between SCL falling edge SDA edge in
* | | |transmission mode.
* | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK.
*/
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[8];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
__O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
__I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[3];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */
__IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */
__IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */
__IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[8];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */
__IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */
} UI2C_T;
/**
@addtogroup UI2C_CONST UI2C Bit Field Definition
Constant Definitions for UI2C Controller
@{ */
#define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */
#define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */
#define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */
#define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */
#define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */
#define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */
#define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */
#define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */
#define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */
#define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */
#define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */
#define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */
#define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */
#define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */
#define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */
#define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */
#define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */
#define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */
#define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */
#define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */
#define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */
#define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */
#define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */
#define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */
#define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */
#define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */
#define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */
#define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */
#define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */
#define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */
#define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */
#define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */
#define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */
#define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */
#define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */
#define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */
#define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */
#define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */
#define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */
#define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */
#define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */
#define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */
#define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */
#define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */
#define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */
#define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */
#define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */
#define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */
#define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */
#define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */
#define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */
#define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */
#define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */
#define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */
#define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */
#define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */
#define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */
#define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */
#define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */
#define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */
#define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */
#define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */
#define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */
#define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */
#define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */
#define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */
#define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */
#define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */
#define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */
#define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */
#define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */
#define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */
#define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */
#define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */
#define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */
#define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */
#define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */
#define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */
#define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */
#define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */
#define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */
#define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */
#define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */
#define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */
#define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */
#define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */
#define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */
#define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */
#define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */
#define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */
#define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */
#define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */
#define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */
#define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */
#define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */
#define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */
#define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */
#define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */
#define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */
#define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */
#define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */
#define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */
#define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */
#define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */
#define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */
#define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */
#define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */
#define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */
#define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */
#define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */
/**@}*/ /* UI2C_CONST */
/**@}*/ /* end of UI2C register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __UI2C_REG_H__ */

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/**************************************************************************//**
* @file usbd_reg.h
* @version V3.00
* @brief USBD register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __USBD_REG_H__
#define __USBD_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup USBD USB Device Controller(USBD)
Memory Mapped Structure for USBD Controller
@{ */
typedef struct
{
/**
* @var USBD_EP_T::BUFSEG
* Offset: 0x000 Endpoint n Buffer Segmentation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:3] |BUFSEG |Endpoint Buffer Segmentation
* | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
* | | |USBD_SRAM address + { BUFSEG, 3'b000}
* | | |Where the USBD_SRAM address = USBD_BA+0x100h.
* | | |Refer to the section 7.29.5.7 for the endpoint SRAM structure and its description.
* @var USBD_EP_T::MXPLD
* Offset: 0x004 Endpoint n Maximal Payload Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |MXPLD |Maximal Payload
* | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)
* | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
* | | |(1) When the register is written by CPU,
* | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
* | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
* | | |(2) When the register is read by CPU,
* | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
* | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
* | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
* @var USBD_EP_T::CFG
* Offset: 0x008 Endpoint n Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |EPNUM |Endpoint Number
* | | |These bits are used to define the endpoint number of the current endpoint
* |[4] |ISOCH |Isochronous Endpoint
* | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
* | | |0 = No Isochronous endpoint.
* | | |1 = Isochronous endpoint.
* |[6:5] |STATE |Endpoint STATE
* | | |00 = Endpoint is Disabled.
* | | |01 = Out endpoint.
* | | |10 = IN endpoint.
* | | |11 = Undefined.
* |[7] |DSQSYNC |Data Sequence Synchronization
* | | |0 = DATA0 PID.
* | | |1 = DATA1 PID.
* | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction
* | | |hardware will toggle automatically in IN token base on the bit.
* |[9] |CSTALL |Clear STALL Response
* | | |0 = Disable the device to clear the STALL handshake in setup stage.
* | | |1 = Clear the device to response STALL handshake in setup stage.
* @var USBD_EP_T::CFGP
* Offset: 0x00C Endpoint n Set Stall and Clear In/Out Ready Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CLRRDY |Clear Ready
* | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data
* | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
* | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
* | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
* | | |This bit is write 1 only and is always 0 when it is read back.
* |[1] |SSTALL |Set STALL
* | | |0 = Disable the device to response STALL.
* | | |1 = Set the device to respond STALL automatically.
*/
__IO uint32_t BUFSEG; /*!< [0x0000] Endpoint n Buffer Segmentation Register */
__IO uint32_t MXPLD; /*!< [0x0004] Endpoint n Maximal Payload Register */
__IO uint32_t CFG; /*!< [0x0008] Endpoint n Configuration Register */
__IO uint32_t CFGP; /*!< [0x000c] Endpoint n Set Stall and Clear In/Out Ready Control Register */
} USBD_EP_T;
typedef struct
{
/**
* @var USBD_T::INTEN
* Offset: 0x00 USB Device Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSIEN |Bus Event Interrupt Enable Bit
* | | |0 = BUS event interrupt Disabled.
* | | |1 = BUS event interrupt Enabled.
* |[1] |USBIEN |USB Event Interrupt Enable Bit
* | | |0 = USB event interrupt Disabled.
* | | |1 = USB event interrupt Enabled.
* |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit
* | | |0 = VBUS detection Interrupt Disabled.
* | | |1 = VBUS detection Interrupt Enabled.
* |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit
* | | |0 = No-event-wake-up Interrupt Disabled.
* | | |1 = No-event-wake-up Interrupt Enabled.
* |[4] |SOFIEN |Start of Frame Interrupt Enable Bit
* | | |0 = SOF Interrupt Disabled.
* | | |1 = SOF Interrupt Enabled.
* |[8] |WKEN |Wake-up Function Enable Bit
* | | |0 = USB wake-up function Disabled.
* | | |1 = USB wake-up function Enabled.
* |[15] |INNAKEN |Active NAK Function and Its Status in IN Token
* | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted.
* | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token.
* @var USBD_T::INTSTS
* Offset: 0x04 USB Device Interrupt Event Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSIF |BUS Interrupt Status
* | | |The BUS event means that there is one of the suspense or the resume function in the bus.
* | | |0 = No BUS event occurred.
* | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0].
* |[1] |USBIF |USB Event Interrupt Status
* | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
* | | |0 = No USB event occurred.
* | | |1 = USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]).
* |[2] |VBDETIF |VBUS Detection Interrupt Status
* | | |0 = There is not attached/detached event in the USB.
* | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2].
* |[3] |NEVWKIF |No-event-wake-up Interrupt Status
* | | |0 = NEVWK event does not occur.
* | | |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3].
* |[4] |SOFIF |Start of Frame Interrupt Status
* | | |0 = SOF event does not occur.
* | | |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4].
* |[16] |EPEVT0 |Endpoint 0's USB Event Status
* | | |0 = No event occurred in endpoint 0.
* | | |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1].
* |[17] |EPEVT1 |Endpoint 1's USB Event Status
* | | |0 = No event occurred in endpoint 1.
* | | |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1].
* |[18] |EPEVT2 |Endpoint 2's USB Event Status
* | | |0 = No event occurred in endpoint 2.
* | | |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1].
* |[19] |EPEVT3 |Endpoint 3's USB Event Status
* | | |0 = No event occurred in endpoint 3.
* | | |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1].
* |[20] |EPEVT4 |Endpoint 4's USB Event Status
* | | |0 = No event occurred in endpoint 4.
* | | |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1].
* |[21] |EPEVT5 |Endpoint 5's USB Event Status
* | | |0 = No event occurred in endpoint 5.
* | | |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1].
* |[22] |EPEVT6 |Endpoint 6's USB Event Status
* | | |0 = No event occurred in endpoint 6.
* | | |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1].
* |[23] |EPEVT7 |Endpoint 7's USB Event Status
* | | |0 = No event occurred in endpoint 7.
* | | |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1].
* |[24] |EPEVT8 |Endpoint 8's USB Event Status
* | | |0 = No event occurred in endpoint 8.
* | | |1 = USB event occurred on Endpoint 8, check USBD_EPSTS1[3 :0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1].
* |[25] |EPEVT9 |Endpoint 9's USB Event Status
* | | |0 = No event occurred in endpoint 9.
* | | |1 = USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1].
* |[26] |EPEVT10 |Endpoint 10's USB Event Status
* | | |0 = No event occurred in endpoint 10.
* | | |1 = USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1].
* |[27] |EPEVT11 |Endpoint 11's USB Event Status
* | | |0 = No event occurred in endpoint 11.
* | | |1 = USB event occurred on Endpoint 11, check USBD_EPSTS1[ 15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1].
* |[31] |SETUP |Setup Event Status
* | | |0 = No Setup event.
* | | |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31].
* @var USBD_T::FADDR
* Offset: 0x08 USB Device Function Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |FADDR |USB Device Function Address
* @var USBD_T::EPSTS
* Offset: 0x0C USB Device Endpoint Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7] |OV |Overrun
* | | |It indicates that the received data is over the maximum payload number or not.
* | | |0 = No overrun.
* | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
* @var USBD_T::ATTR
* Offset: 0x10 USB Device Bus Status and Attribution Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |USBRST |USB Reset Status
* | | |0 = Bus no reset.
* | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us.
* | | |Note: This bit is read only.
* |[1] |SUSPEND |Suspend Status
* | | |0 = Bus no suspend.
* | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
* | | |Note: This bit is read only.
* |[2] |RESUME |Resume Status
* | | |0 = No bus resume.
* | | |1 = Resume from suspend.
* | | |Note: This bit is read only.
* |[3] |TOUT |Time-out Status
* | | |0 = No time-out.
* | | |1 = No Bus response more than 18 bits time.
* | | |Note: This bit is read only.
* |[4] |PHYEN |PHY Transceiver Function Enable Bit
* | | |0 = PHY transceiver function Disabled.
* | | |1 = PHY transceiver function Enabled.
* |[5] |RWAKEUP |Remote Wake-up
* | | |0 = Release the USB bus from K state.
* | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up.
* |[7] |USBEN |USB Controller Enable Bit
* | | |0 = USB Controller Disabled.
* | | |1 = USB Controller Enabled.
* |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit
* | | |0 = Pull-up resistor in USB_D+ bus Disabled.
* | | |1 = Pull-up resistor in USB_D+ bus Active.
* |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection
* | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
* | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
* |[11] |LPMACK |LPM Token Acknowledge Enable Bit
* | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively.
* | | |0= the valid LPM Token will be NYET.
* | | |1= the valid LPM Token will be ACK.
* |[12] |L1SUSPEND |LPM L1 Suspend
* | | |0 = Bus no L1 state suspend.
* | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged.
* | | |Note: This bit is read only.
* |[13] |L1RESUME |LPM L1 Resume
* | | |0 = Bus no LPM L1 state resume.
* | | |1 = LPM L1 state Resume from LPM L1 state suspend.
* | | |Note: This bit is read only.
* @var USBD_T::VBUSDET
* Offset: 0x14 USB Device VBUS Detection Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VBUSDET |Device VBUS Detection
* | | |0 = Controller is not attached to the USB host.
* | | |1 = Controller is attached to the USB host.
* @var USBD_T::STBUFSEG
* Offset: 0x18 SETUP Token Buffer Segmentation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation
* | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
* | | |USBD_SRAM address + {STBUFSEG, 3'b000}
* | | |Where the USBD_SRAM address = USBD_BA+0x100h.
* | | |Note: It is used for SETUP token only.
* @var USBD_T::EPSTS0
* Offset: 0x20 USB Device Endpoint Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[03:00] |EPSTS0 |Endpoint 0 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[07:04] |EPSTS1 |Endpoint 1 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[11:08] |EPSTS2 |Endpoint 2 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[15:12] |EPSTS3 |Endpoint 3 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[19:16] |EPSTS4 |Endpoint 4 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[23:20] |EPSTS5 |Endpoint 5 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[27:24] |EPSTS6 |Endpoint 6 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[31:28] |EPSTS7 |Endpoint 7 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* @var USBD_T::EPSTS1
* Offset: 0x24 USB Device Endpoint Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |EPSTS8 |Endpoint 8 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[7:4] |EPSTS9 |Endpoint 9 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[11:8] |EPSTS10 |Endpoint 10 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[15:12] |EPSTS11 |Endpoint 11 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* @var USBD_T::LPMATTR
* Offset: 0x88 USB LPM Attribution Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |LPMLINKSTS|LPM Link State
* | | |These bits contain the bLinkState received with last ACK LPM Token
* |[7:4] |LPMBESL |LPM Best Effort Service Latency
* | | |These bits contain the BESL value received with last ACK LPM Token
* |[8] |LPMRWAKUP |LPM Remote Wakeup
* | | |This bit contains the bRemoteWake value received with last ACK LPM Token
* @var USBD_T::FN
* Offset: 0x8C USB Frame number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:0] |FN |Frame Number
* | | |These bits contain the 11-bits frame number in the last received SOF packet.
* @var USBD_T::SE0
* Offset: 0x90 USB Device Drive SE0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SE0 |Drive Single Ended Zero in USB Bus
* | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
* | | |0 = Normal operation.
* | | |1 = Force USB PHY transceiver to drive SE0.
*/
__IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */
__IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */
__I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */
__IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */
__I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */
__IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */
__I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */
__I uint32_t EPSTS2; /*!< [0x0028] USB Device Endpoint Status Register 2 */
__I uint32_t EPSTS3; /*!< [0x002c] USB Device Endpoint Status Register 3 */
__IO uint32_t EPINTSTS; /*!< [0x0030] USB Device Endpoint Interrupt Event Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[21];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */
__I uint32_t FN; /*!< [0x008c] USB Frame number Register */
__IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[283];
/// @endcond //HIDDEN_SYMBOLS
USBD_EP_T EP[25]; /*!< [0x500~0x68c] USB End Point 0 ~ 24 Configuration Register */
} USBD_T;
/**
@addtogroup USBD_CONST USBD Bit Field Definition
Constant Definitions for USBD Controller
@{ */
#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */
#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */
#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */
#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */
#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */
#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */
#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */
#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */
#define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */
#define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */
#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */
#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */
#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */
#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */
#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */
#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */
#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */
#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */
#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */
#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */
#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */
#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */
#define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */
#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */
#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */
#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */
#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */
#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */
#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */
#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */
#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */
#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */
#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */
#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */
#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */
#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */
#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */
#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */
#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */
#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */
#define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */
#define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */
#define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */
#define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */
#define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */
#define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */
#define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */
#define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */
#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */
#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */
#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */
#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */
#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */
#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */
#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */
#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */
#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */
#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */
#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */
#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */
#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */
#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */
#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */
#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */
#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */
#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */
#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */
#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */
#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */
#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */
#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */
#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */
#define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */
#define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */
#define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */
#define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */
#define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */
#define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */
#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */
#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */
#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */
#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */
#define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */
#define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */
#define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */
#define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */
#define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */
#define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */
#define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */
#define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */
#define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */
#define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */
#define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */
#define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */
#define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */
#define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */
#define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */
#define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */
#define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */
#define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */
#define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */
#define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */
#define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */
#define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */
#define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */
#define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */
#define USBD_EPSTS1_EPSTS12_Pos (16) /*!< USBD_T::EPSTS1: EPSTS12 Position */
#define USBD_EPSTS1_EPSTS12_Msk (0xful << USBD_EPSTS1_EPSTS12_Pos) /*!< USBD_T::EPSTS1: EPSTS12 Mask */
#define USBD_EPSTS1_EPSTS13_Pos (20) /*!< USBD_T::EPSTS1: EPSTS13 Position */
#define USBD_EPSTS1_EPSTS13_Msk (0xful << USBD_EPSTS1_EPSTS13_Pos) /*!< USBD_T::EPSTS1: EPSTS13 Mask */
#define USBD_EPSTS1_EPSTS14_Pos (24) /*!< USBD_T::EPSTS1: EPSTS14 Position */
#define USBD_EPSTS1_EPSTS14_Msk (0xful << USBD_EPSTS1_EPSTS14_Pos) /*!< USBD_T::EPSTS1: EPSTS14 Mask */
#define USBD_EPSTS1_EPSTS15_Pos (28) /*!< USBD_T::EPSTS1: EPSTS15 Position */
#define USBD_EPSTS1_EPSTS15_Msk (0xful << USBD_EPSTS1_EPSTS15_Pos) /*!< USBD_T::EPSTS1: EPSTS15 Mask */
#define USBD_EPSTS2_EPSTS16_Pos (0) /*!< USBD_T::EPSTS2: EPSTS16 Position */
#define USBD_EPSTS2_EPSTS16_Msk (0xful << USBD_EPSTS2_EPSTS16_Pos) /*!< USBD_T::EPSTS2: EPSTS16 Mask */
#define USBD_EPSTS2_EPSTS17_Pos (4) /*!< USBD_T::EPSTS2: EPSTS17 Position */
#define USBD_EPSTS2_EPSTS17_Msk (0xful << USBD_EPSTS2_EPSTS17_Pos) /*!< USBD_T::EPSTS2: EPSTS17 Mask */
#define USBD_EPSTS2_EPSTS18_Pos (8) /*!< USBD_T::EPSTS2: EPSTS18 Position */
#define USBD_EPSTS2_EPSTS18_Msk (0xful << USBD_EPSTS2_EPSTS18_Pos) /*!< USBD_T::EPSTS2: EPSTS18 Mask */
#define USBD_EPSTS2_EPSTS19_Pos (12) /*!< USBD_T::EPSTS2: EPSTS19 Position */
#define USBD_EPSTS2_EPSTS19_Msk (0xful << USBD_EPSTS2_EPSTS19_Pos) /*!< USBD_T::EPSTS2: EPSTS19 Mask */
#define USBD_EPSTS2_EPSTS20_Pos (16) /*!< USBD_T::EPSTS2: EPSTS20 Position */
#define USBD_EPSTS2_EPSTS20_Msk (0xful << USBD_EPSTS2_EPSTS20_Pos) /*!< USBD_T::EPSTS2: EPSTS20 Mask */
#define USBD_EPSTS2_EPSTS21_Pos (20) /*!< USBD_T::EPSTS2: EPSTS21 Position */
#define USBD_EPSTS2_EPSTS21_Msk (0xful << USBD_EPSTS2_EPSTS21_Pos) /*!< USBD_T::EPSTS2: EPSTS21 Mask */
#define USBD_EPSTS2_EPSTS22_Pos (24) /*!< USBD_T::EPSTS2: EPSTS22 Position */
#define USBD_EPSTS2_EPSTS22_Msk (0xful << USBD_EPSTS2_EPSTS22_Pos) /*!< USBD_T::EPSTS2: EPSTS22 Mask */
#define USBD_EPSTS2_EPSTS23_Pos (28) /*!< USBD_T::EPSTS2: EPSTS23 Position */
#define USBD_EPSTS2_EPSTS23_Msk (0xful << USBD_EPSTS2_EPSTS23_Pos) /*!< USBD_T::EPSTS2: EPSTS23 Mask */
#define USBD_EPSTS3_EPSTS24_Pos (0) /*!< USBD_T::EPSTS3: EPSTS24 Position */
#define USBD_EPSTS3_EPSTS24_Msk (0xful << USBD_EPSTS3_EPSTS24_Pos) /*!< USBD_T::EPSTS3: EPSTS24 Mask */
#define USBD_EPINTSTS_EPEVT0_Pos (0) /*!< USBD_T::EPINTSTS: EPEVT0 Position */
#define USBD_EPINTSTS_EPEVT0_Msk (0x1ul << USBD_EPINTSTS_EPEVT0_Pos) /*!< USBD_T::EPINTSTS: EPEVT0 Mask */
#define USBD_EPINTSTS_EPEVT1_Pos (1) /*!< USBD_T::EPINTSTS: EPEVT1 Position */
#define USBD_EPINTSTS_EPEVT1_Msk (0x1ul << USBD_EPINTSTS_EPEVT1_Pos) /*!< USBD_T::EPINTSTS: EPEVT1 Mask */
#define USBD_EPINTSTS_EPEVT2_Pos (2) /*!< USBD_T::EPINTSTS: EPEVT2 Position */
#define USBD_EPINTSTS_EPEVT2_Msk (0x1ul << USBD_EPINTSTS_EPEVT2_Pos) /*!< USBD_T::EPINTSTS: EPEVT2 Mask */
#define USBD_EPINTSTS_EPEVT3_Pos (3) /*!< USBD_T::EPINTSTS: EPEVT3 Position */
#define USBD_EPINTSTS_EPEVT3_Msk (0x1ul << USBD_EPINTSTS_EPEVT3_Pos) /*!< USBD_T::EPINTSTS: EPEVT3 Mask */
#define USBD_EPINTSTS_EPEVT4_Pos (4) /*!< USBD_T::EPINTSTS: EPEVT4 Position */
#define USBD_EPINTSTS_EPEVT4_Msk (0x1ul << USBD_EPINTSTS_EPEVT4_Pos) /*!< USBD_T::EPINTSTS: EPEVT4 Mask */
#define USBD_EPINTSTS_EPEVT5_Pos (5) /*!< USBD_T::EPINTSTS: EPEVT5 Position */
#define USBD_EPINTSTS_EPEVT5_Msk (0x1ul << USBD_EPINTSTS_EPEVT5_Pos) /*!< USBD_T::EPINTSTS: EPEVT5 Mask */
#define USBD_EPINTSTS_EPEVT6_Pos (6) /*!< USBD_T::EPINTSTS: EPEVT6 Position */
#define USBD_EPINTSTS_EPEVT6_Msk (0x1ul << USBD_EPINTSTS_EPEVT6_Pos) /*!< USBD_T::EPINTSTS: EPEVT6 Mask */
#define USBD_EPINTSTS_EPEVT7_Pos (7) /*!< USBD_T::EPINTSTS: EPEVT7 Position */
#define USBD_EPINTSTS_EPEVT7_Msk (0x1ul << USBD_EPINTSTS_EPEVT7_Pos) /*!< USBD_T::EPINTSTS: EPEVT7 Mask */
#define USBD_EPINTSTS_EPEVT8_Pos (8) /*!< USBD_T::EPINTSTS: EPEVT8 Position */
#define USBD_EPINTSTS_EPEVT8_Msk (0x1ul << USBD_EPINTSTS_EPEVT8_Pos) /*!< USBD_T::EPINTSTS: EPEVT8 Mask */
#define USBD_EPINTSTS_EPEVT9_Pos (9) /*!< USBD_T::EPINTSTS: EPEVT9 Position */
#define USBD_EPINTSTS_EPEVT9_Msk (0x1ul << USBD_EPINTSTS_EPEVT9_Pos) /*!< USBD_T::EPINTSTS: EPEVT9 Mask */
#define USBD_EPINTSTS_EPEVT10_Pos (10) /*!< USBD_T::EPINTSTS: EPEVT10 Position */
#define USBD_EPINTSTS_EPEVT10_Msk (0x1ul << USBD_EPINTSTS_EPEVT10_Pos) /*!< USBD_T::EPINTSTS: EPEVT10 Mask */
#define USBD_EPINTSTS_EPEVT11_Pos (11) /*!< USBD_T::EPINTSTS: EPEVT11 Position */
#define USBD_EPINTSTS_EPEVT11_Msk (0x1ul << USBD_EPINTSTS_EPEVT11_Pos) /*!< USBD_T::EPINTSTS: EPEVT11 Mask */
#define USBD_EPINTSTS_EPEVT12_Pos (12) /*!< USBD_T::EPINTSTS: EPEVT12 Position */
#define USBD_EPINTSTS_EPEVT12_Msk (0x1ul << USBD_EPINTSTS_EPEVT12_Pos) /*!< USBD_T::EPINTSTS: EPEVT12 Mask */
#define USBD_EPINTSTS_EPEVT13_Pos (13) /*!< USBD_T::EPINTSTS: EPEVT13 Position */
#define USBD_EPINTSTS_EPEVT13_Msk (0x1ul << USBD_EPINTSTS_EPEVT13_Pos) /*!< USBD_T::EPINTSTS: EPEVT13 Mask */
#define USBD_EPINTSTS_EPEVT14_Pos (14) /*!< USBD_T::EPINTSTS: EPEVT14 Position */
#define USBD_EPINTSTS_EPEVT14_Msk (0x1ul << USBD_EPINTSTS_EPEVT14_Pos) /*!< USBD_T::EPINTSTS: EPEVT14 Mask */
#define USBD_EPINTSTS_EPEVT15_Pos (15) /*!< USBD_T::EPINTSTS: EPEVT15 Position */
#define USBD_EPINTSTS_EPEVT15_Msk (0x1ul << USBD_EPINTSTS_EPEVT15_Pos) /*!< USBD_T::EPINTSTS: EPEVT15 Mask */
#define USBD_EPINTSTS_EPEVT16_Pos (16) /*!< USBD_T::EPINTSTS: EPEVT16 Position */
#define USBD_EPINTSTS_EPEVT16_Msk (0x1ul << USBD_EPINTSTS_EPEVT16_Pos) /*!< USBD_T::EPINTSTS: EPEVT16 Mask */
#define USBD_EPINTSTS_EPEVT17_Pos (17) /*!< USBD_T::EPINTSTS: EPEVT17 Position */
#define USBD_EPINTSTS_EPEVT17_Msk (0x1ul << USBD_EPINTSTS_EPEVT17_Pos) /*!< USBD_T::EPINTSTS: EPEVT17 Mask */
#define USBD_EPINTSTS_EPEVT18_Pos (18) /*!< USBD_T::EPINTSTS: EPEVT18 Position */
#define USBD_EPINTSTS_EPEVT18_Msk (0x1ul << USBD_EPINTSTS_EPEVT18_Pos) /*!< USBD_T::EPINTSTS: EPEVT18 Mask */
#define USBD_EPINTSTS_EPEVT19_Pos (19) /*!< USBD_T::EPINTSTS: EPEVT19 Position */
#define USBD_EPINTSTS_EPEVT19_Msk (0x1ul << USBD_EPINTSTS_EPEVT19_Pos) /*!< USBD_T::EPINTSTS: EPEVT19 Mask */
#define USBD_EPINTSTS_EPEVT20_Pos (20) /*!< USBD_T::EPINTSTS: EPEVT20 Position */
#define USBD_EPINTSTS_EPEVT20_Msk (0x1ul << USBD_EPINTSTS_EPEVT20_Pos) /*!< USBD_T::EPINTSTS: EPEVT20 Mask */
#define USBD_EPINTSTS_EPEVT21_Pos (21) /*!< USBD_T::EPINTSTS: EPEVT21 Position */
#define USBD_EPINTSTS_EPEVT21_Msk (0x1ul << USBD_EPINTSTS_EPEVT21_Pos) /*!< USBD_T::EPINTSTS: EPEVT21 Mask */
#define USBD_EPINTSTS_EPEVT22_Pos (22) /*!< USBD_T::EPINTSTS: EPEVT22 Position */
#define USBD_EPINTSTS_EPEVT22_Msk (0x1ul << USBD_EPINTSTS_EPEVT22_Pos) /*!< USBD_T::EPINTSTS: EPEVT22 Mask */
#define USBD_EPINTSTS_EPEVT23_Pos (23) /*!< USBD_T::EPINTSTS: EPEVT23 Position */
#define USBD_EPINTSTS_EPEVT23_Msk (0x1ul << USBD_EPINTSTS_EPEVT23_Pos) /*!< USBD_T::EPINTSTS: EPEVT23 Mask */
#define USBD_EPINTSTS_EPEVT24_Pos (24) /*!< USBD_T::EPINTSTS: EPEVT24 Position */
#define USBD_EPINTSTS_EPEVT24_Msk (0x1ul << USBD_EPINTSTS_EPEVT24_Pos) /*!< USBD_T::EPINTSTS: EPEVT24 Mask */
#define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */
#define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */
#define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */
#define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */
#define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */
#define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */
#define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */
#define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */
#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */
#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */
#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */
#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */
#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */
#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */
#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */
#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */
#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */
#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */
#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */
#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */
#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */
#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */
#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */
#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */
#define USBD_CFG_DBTGACTIVE_Pos (10) /*!< USBD_EP_T::CFG: DBTGACTIVE Position */
#define USBD_CFG_DBTGACTIVE_Msk (0x1ul << USBD_CFG_DBTGACTIVE_Pos) /*!< USBD_EP_T::CFG: DBTGACTIVE Mask */
#define USBD_CFG_DBEN_Pos (11) /*!< USBD_EP_T::CFG: DBEN Position */
#define USBD_CFG_DBEN_Msk (0x1ul << USBD_CFG_DBEN_Pos) /*!< USBD_EP_T::CFG: DBEN Mask */
#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */
#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */
#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */
#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */
/**@}*/ /* USBD_CONST */
/**@}*/ /* end of USBD register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __USBD_REG_H__ */

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/**************************************************************************//**
* @file usbh_reg.h
* @version V1.00
* @brief USBH register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __USBH_REG_H__
#define __USBH_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup USBH USB Host Controller(USBH)
Memory Mapped Structure for USBH Controller
@{ */
typedef struct
{
/**
* @var USBH_T::HcRevision
* Offset: 0x00 Host Controller Revision Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |REV |Revision Number
* | | |Indicates the Open HCI Specification revision number implemented by the Hardware
* | | |Host Controller supports 1.1 specification.
* | | |(X.Y = XYh).
* @var USBH_T::HcControl
* Offset: 0x04 Host Controller Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |CBSR |Control Bulk Service Ratio
* | | |This specifies the service ratio between Control and Bulk EDs
* | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs
* | | |The internal count will be retained when crossing the frame boundary
* | | |In case of reset, HCD is responsible for restoring this
* | | |Value.
* | | |00 = Number of Control EDs over Bulk EDs served is 1:1.
* | | |01 = Number of Control EDs over Bulk EDs served is 2:1.
* | | |10 = Number of Control EDs over Bulk EDs served is 3:1.
* | | |11 = Number of Control EDs over Bulk EDs served is 4:1.
* |[2] |PLE |Periodic List Enable Bit
* | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list
* | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
* | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled.
* | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
* |[3] |IE |Isochronous List Enable Bit
* | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list
* | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
* | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too.
* |[4] |CLE |Control List Enable Bit
* | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Control list in the next frame Enabled.
* |[5] |BLE |Bulk List Enable Bit
* | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Bulk list in the next frame Enabled.
* |[7:6] |HCFS |Host Controller Functional State
* | | |This field sets the Host Controller state
* | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port
* | | |States are:
* | | |00 = USBSUSPEND.
* | | |01 = USBOPERATIONAL.
* | | |10 = USBRESUME.
* | | |11 = USBRESET.
* @var USBH_T::HcCommandStatus
* Offset: 0x08 Host Controller Command Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |HCR |Host Controller Reset
* | | |This bit is set to initiate the software reset of Host Controller
* | | |This bit is cleared by the Host Controller, upon completed of the reset operation.
* | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
* | | |0 = Host Controller is not in software reset state.
* | | |1 = Host Controller is in software reset state.
* |[1] |CLF |Control List Filled
* | | |Set high to indicate there is an active TD on the Control List
* | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
* | | |0 = No active TD found or Host Controller begins to process the head of the Control list.
* | | |1 = An active TD added or found on the Control list.
* |[2] |BLF |Bulk List Filled
* | | |Set high to indicate there is an active TD on the Bulk list
* | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
* | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list.
* | | |1 = An active TD added or found on the Bulk list.
* |[17:16] |SOC |Schedule Overrun Count
* | | |These bits are incremented on each scheduling overrun error
* | | |It is initialized to 00b and wraps around at 11b
* | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set.
* @var USBH_T::HcInterruptStatus
* Offset: 0x0C Host Controller Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SO |Scheduling Overrun
* | | |Set when the List Processor determines a Schedule Overrun has occurred.
* | | |0 = Schedule Overrun didn't occur.
* | | |1 = Schedule Overrun has occurred.
* |[1] |WDH |Write Back Done Head
* | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead
* | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared.
* | | |0 =.Host Controller didn't update HccaDoneHead.
* | | |1 =.Host Controller has written HcDoneHead to HccaDoneHead.
* |[2] |SF |Start of Frame
* | | |Set when the Frame Management functional block signals a 'Start of Frame' event
* | | |Host Control generates a SOF token at the same time.
* | | |0 =.Not the start of a frame.
* | | |1 =.Indicate the start of a frame and Host Controller generates a SOF token.
* |[3] |RD |Resume Detected
* | | |Set when Host Controller detects resume signaling on a downstream port.
* | | |0 = No resume signaling detected on a downstream port.
* | | |1 = Resume signaling detected on a downstream port.
* |[5] |FNO |Frame Number Overflow
* | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
* | | |0 = The bit 15 of Frame Number didn't change.
* | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
* |[6] |RHSC |Root Hub Status Change
* | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed.
* | | |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change.
* | | |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed.
* @var USBH_T::HcInterruptEnable
* Offset: 0x10 Host Controller Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SO |Scheduling Overrun Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
* |[1] |WDH |Write Back Done Head Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
* |[2] |SF |Start of Frame Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
* |[3] |RD |Resume Detected Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
* |[5] |FNO |Frame Number Overflow Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
* |[6] |RHSC |Root Hub Status Change Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
* |[31] |MIE |Master Interrupt Enable Bit
* | | |This bit is a global interrupt enable
* | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
* @var USBH_T::HcInterruptDisable
* Offset: 0x14 Host Controller Interrupt Disable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SO |Scheduling Overrun Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
* |[1] |WDH |Write Back Done Head Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
* |[2] |SF |Start of Frame Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
* |[3] |RD |Resume Detected Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
* |[5] |FNO |Frame Number Overflow Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
* |[6] |RHSC |Root Hub Status Change Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
* |[31] |MIE |Master Interrupt Disable Bit
* | | |Global interrupt disable. Writing '1' to disable all interrupts.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
* @var USBH_T::HcHCCA
* Offset: 0x18 Host Controller Communication Area Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:8] |HCCA |Host Controller Communication Area
* | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA).
* @var USBH_T::HcPeriodCurrentED
* Offset: 0x1C Host Controller Period Current ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |PCED |Periodic Current ED
* | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
* @var USBH_T::HcControlHeadED
* Offset: 0x20 Host Controller Control Head ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |CHED |Control Head ED
* | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.
* @var USBH_T::HcControlCurrentED
* Offset: 0x24 Host Controller Control Current ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |CCED |Control Current Head ED
* | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
* @var USBH_T::HcBulkHeadED
* Offset: 0x28 Host Controller Bulk Head ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |BHED |Bulk Head ED
* | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
* @var USBH_T::HcBulkCurrentED
* Offset: 0x2C Host Controller Bulk Current ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |BCED |Bulk Current Head ED
* | | |Pointer to indicate the physical address of the current endpoint of the Bulk list.
* @var USBH_T::HcDoneHead
* Offset: 0x30 Host Controller Done Head Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |DH |Done Head
* | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
* @var USBH_T::HcFmInterval
* Offset: 0x34 Host Controller Frame Interval Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |FI |Frame Interval
* | | |This field specifies the length of a frame as (bit times - 1)
* | | |For 12,000 bit times in a frame, a value of 11,999 is stored here.
* |[30:16] |FSMPS |FS Largest Data Packet
* | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
* |[31] |FIT |Frame Interval Toggle
* | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).
* | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]).
* | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]).
* @var USBH_T::HcFmRemaining
* Offset: 0x38 Host Controller Frame Remaining Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |FR |Frame Remaining
* | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period
* | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval
* | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
* |[31] |FRT |Frame Remaining Toggle
* | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0.
* @var USBH_T::HcFmNumber
* Offset: 0x3C Host Controller Frame Number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FN |Frame Number
* | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0])
* | | |The count rolls over from 'FFFFh' to '0h.'
* @var USBH_T::HcPeriodicStart
* Offset: 0x40 Host Controller Periodic Start Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |PS |Periodic Start
* | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
* @var USBH_T::HcLSThreshold
* Offset: 0x44 Host Controller Low-speed Threshold Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |LST |Low-speed Threshold
* | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction
* | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field
* | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
* @var USBH_T::HcRhDescriptorA
* Offset: 0x48 Host Controller Root Hub Descriptor A Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |NDP |Number Downstream Ports
* | | |USB host control supports two downstream ports and only one port is available in this series of chip.
* |[8] |PSM |Power Switching Mode
* | | |This bit is used to specify how the power switching of the Root Hub ports is controlled.
* | | |0 = Global Switching.
* | | |1 = Individual Switching.
* |[11] |OCPM |over Current Protection Mode
* | | |This bit describes how the over current status for the Root Hub ports reported
* | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared.
* | | |0 = Global Over current.
* | | |1 = Individual Over current.
* |[12] |NOCP |No over Current Protection
* | | |This bit describes how the over current status for the Root Hub ports reported.
* | | |0 = Over current status is reported.
* | | |1 = Over current status is not reported.
* @var USBH_T::HcRhDescriptorB
* Offset: 0x4C Host Controller Root Hub Descriptor B Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:16] |PPCM |Port Power Control Mask
* | | |Global power switching
* | | |This field is only valid if PowerSwitchingMode is set (individual port switching)
* | | |When set, the port only responds to individual port power switching commands (Set/ClearPortPower)
* | | |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).
* | | |0 = Port power controlled by global power switching.
* | | |1 = Port power controlled by port power switching.
* | | |Note: PPCM[15:2] and PPCM[0] are reserved.
* @var USBH_T::HcRhStatus
* Offset: 0x50 Host Controller Root Hub Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LPS |Clear Global Power
* | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power.
* | | |This bit always read as zero.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear global power.
* |[1] |OCI |over Current Indicator
* | | |This bit reflects the state of the over current status pin
* | | |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
* | | |0 = No over current condition.
* | | |1 = Over current condition.
* |[15] |DRWE |Device Remote Wakeup Enable Bit
* | | |This bit controls if port's Connect Status Change as a remote wake-up event.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Connect Status Change as a remote wake-up event Enabled.
* | | |Read Operation:
* | | |0 = Connect Status Change as a remote wake-up event Disabled.
* | | |1 = Connect Status Change as a remote wake-up event Enabled.
* |[16] |LPSC |Set Global Power
* | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports.
* | | |This bit always read as zero.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set global power.
* |[17] |OCIC |over Current Indicator Change
* | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).
* | | |Write 1 to clear this bit to zero.
* | | |0 = OCI (HcRhStatus[1]) didn't change.
* | | |1 = OCI (HcRhStatus[1]) change.
* |[31] |CRWE |Clear Remote Wake-up Enable Bit
* | | |This bit is use to clear DRWE (HcRhStatus[15]).
* | | |This bit always read as zero.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear DRWE (HcRhStatus[15]).
* @var USBH_T::HcRhPortStatus[2]
* Offset: 0x54 Host Controller Root Hub Port Status
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CCS |CurrentConnectStatus (Read) or ClearPortEnable Bit (Write)
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear port enable.
* | | |Read Operation:
* | | |0 = No device connected.
* | | |1 = Device connected.
* |[1] |PES |Port Enable Status
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set port enable.
* | | |Read Operation:
* | | |0 = Port Disabled.
* | | |1 = Port Enabled.
* |[2] |PSS |Port Suspend Status
* | | |This bit indicates the port is suspended
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set port suspend.
* | | |Read Operation:
* | | |0 = Port is not suspended.
* | | |1 = Port is selectively suspended.
* |[3] |POCI |Port over Current Indicator (Read) or Clear Port Suspend (Write)
* | | |This bit reflects the state of the over current status pin dedicated to this port
* | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.
* | | |This bit is also used to initiate the selective result sequence for the port.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear port suspend.
* | | |Read Operation:
* | | |0 = No over current condition.
* | | |1 = Over current condition.
* |[4] |PRS |Port Reset Status
* | | |This bit reflects the reset state of the port.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set port reset.
* | | |Read Operation
* | | |0 = Port reset signal is not active.
* | | |1 = Port reset signal is active.
* |[8] |PPS |Port Power Status
* | | |This bit reflects the power state of the port regardless of the power switching mode.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Port Power Enabled.
* | | |Read Operation:
* | | |0 = Port power is Disabled.
* | | |1 = Port power is Enabled.
* |[9] |LSDA |Low Speed Device Attached (Read) or Clear Port Power (Write)
* | | |This bit defines the speed (and bud idle) of the attached device
* | | |It is only valid when CCS (HcRhPortStatus1[0]) is set.
* | | |This bit is also used to clear port power.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear PPS (HcRhPortStatus1[8]).
* | | |Read Operation:
* | | |0 = Full Speed device.
* | | |1 = Low-speed device.
* |[16] |CSC |Connect Status Change
* | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).
* | | |Write 1 to clear this bit to zero.
* | | |0 = No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change).
* | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed).
* |[17] |PESC |Port Enable Status Change
* | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.
* | | |Write 1 to clear this bit to zero.
* | | |0 = PES (HcRhPortStatus1[1]) didn't change.
* | | |1 = PES (HcRhPortStatus1[1]) changed.
* |[18] |PSSC |Port Suspend Status Change
* | | |This bit indicates the completion of the selective resume sequence for the port.
* | | |Write 1 to clear this bit to zero.
* | | |0 = Port resume is not completed.
* | | |1 = Port resume completed.
* |[19] |OCIC |Port over Current Indicator Change
* | | |This bit is set when POCI (HcRhPortStatus1[3]) changes.
* | | |Write 1 to clear this bit to zero.
* | | |0 = POCI (HcRhPortStatus1[3]) didn't change.
* | | |1 = POCI (HcRhPortStatus1[3]) changes.
* |[20] |PRSC |Port Reset Status Change
* | | |This bit indicates that the port reset signal has completed.
* | | |Write 1 to clear this bit to zero.
* | | |0 = Port reset is not complete.
* | | |1 = Port reset is complete.
* @var USBH_T::HcPhyControl
* Offset: 0x200 Host Controller PHY Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[27] |STBYEN |USB Transceiver Standby Enable Bit
* | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
* | | |0 = The USB transceiver would never enter the standby mode.
* | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).
* @var USBH_T::HcMiscControl
* Offset: 0x204 Host Controller Miscellaneous Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |ABORT |AHB Bus ERROR Response
* | | |This bit indicates there is an ERROR response received in AHB bus.
* | | |0 = No ERROR response received.
* | | |1 = ERROR response received.
* |[3] |OCAL |over Current Active Low
* | | |This bit controls the polarity of over current flag from external power IC.
* | | |0 = Over current flag is high active.
* | | |1 = Over current flag is low active.
* |[16] |DPRT1 |Disable Port 1
* | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled
* | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
* | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
* | | |0 = The connection between USB host controller and transceiver of port 1 Enabled.
* | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode.
*/
__I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */
__IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */
__IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */
__IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */
__IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */
__IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */
__IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */
__IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */
__IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */
__IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */
__IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */
__IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */
__IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */
__IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */
__I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */
__I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */
__IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */
__IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */
__IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */
__IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */
__IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */
__IO uint32_t HcRhPortStatus[2]; /*!< [0x0054] Host Controller Root Hub Port Status [1] */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[105];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */
__IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */
} USBH_T;
/**
@addtogroup USBH_CONST USBH Bit Field Definition
Constant Definitions for USBH Controller
@{ */
#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */
#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */
#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */
#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */
#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */
#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */
#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */
#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */
#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */
#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */
#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */
#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */
#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */
#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */
#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */
#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */
#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */
#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */
#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */
#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */
#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */
#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */
#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */
#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */
#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/
#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */
#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */
#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */
#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */
#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */
#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/
#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */
#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/
#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */
#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */
#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */
#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/
#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */
#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */
#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */
#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */
#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */
#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/
#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */
#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/
#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */
#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/
#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */
#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/
#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */
#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/
#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */
#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/
#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */
#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/
#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */
#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/
#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */
#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/
#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */
#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/
#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */
#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */
#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */
#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/
#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */
#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */
#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */
#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/
#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */
#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */
#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */
#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */
#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */
#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */
#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */
#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */
#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */
#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */
#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */
#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */
#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */
#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */
#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */
#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */
#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */
#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */
#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */
#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */
#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */
#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */
#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */
#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */
#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */
#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */
#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */
#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */
#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */
#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */
#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */
#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */
#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */
#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */
#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */
#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */
#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */
#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */
#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */
#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */
#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */
#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */
#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */
#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */
#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */
#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus1: CCS Position */
#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus1: CCS Mask */
#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus1: PES Position */
#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus1: PES Mask */
#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus1: PSS Position */
#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus1: PSS Mask */
#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus1: POCI Position */
#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus1: POCI Mask */
#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus1: PRS Position */
#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus1: PRS Mask */
#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus1: PPS Position */
#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus1: PPS Mask */
#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus1: LSDA Position */
#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus1: LSDA Mask */
#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus1: CSC Position */
#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus1: CSC Mask */
#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus1: PESC Position */
#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus1: PESC Mask */
#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus1: PSSC Position */
#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus1: PSSC Mask */
#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus1: OCIC Position */
#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus1: OCIC Mask */
#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus1: PRSC Position */
#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus1: PRSC Mask */
#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */
#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */
#define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */
#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */
#define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */
#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */
#define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */
#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */
/**@}*/ /* USBH_CONST */
/**@}*/ /* end of USBH register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __USBH_REG_H__ */

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/**************************************************************************//**
* @file uspi_reg.h
* @version V1.00
* @brief USPI register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __USPI_REG_H__
#define __USPI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup USPI SPI Mode of USCI Controller(USPI)
Memory Mapped Structure for USPI Controller
@{ */
typedef struct
{
/**
* @var USPI_T::CTL
* Offset: 0x00 USCI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |FUNMODE |Function Mode
* | | |This bit field selects the protocol for this USCI controller
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
* | | |001 = The SPI protocol is selected.
* | | |010 = The UART protocol is selected.
* | | |100 = The I2C protocol is selected.
* | | |Note: Other bit combinations are reserved.
* @var USPI_T::INTEN
* Offset: 0x04 USCI Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit start event.
* | | |0 = The transmit start interrupt is disabled.
* | | |1 = The transmit start interrupt is enabled.
* |[2] |TXENDIEN |Transmit End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit finish event.
* | | |0 = The transmit finish interrupt is disabled.
* | | |1 = The transmit finish interrupt is enabled.
* |[3] |RXSTIEN |Receive Start Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a receive start event.
* | | |0 = The receive start interrupt is disabled.
* | | |1 = The receive start interrupt is enabled.
* |[4] |RXENDIEN |Receive End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a receive finish event.
* | | |0 = The receive end interrupt is disabled.
* | | |1 = The receive end interrupt is enabled.
* @var USPI_T::BRGEN
* Offset: 0x08 USCI Baud Rate Generator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RCLKSEL |Reference Clock Source Selection
* | | |This bit selects the source of reference clock (fREF_CLK).
* | | |0 = Peripheral device clock fPCLK.
* | | |1 = Reserved.
* |[1] |PTCLKSEL |Protocol Clock Source Selection
* | | |This bit selects the source of protocol clock (fPROT_CLK).
* | | |0 = Reference clock fREF_CLK.
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
* | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
* | | |00 = fDIV_CLK.
* | | |01 = fPROT_CLK.
* | | |10 = fSCLK.
* | | |11 = fREF_CLK.
* |[4] |TMCNTEN |Time Measurement Counter Enable Bit
* | | |This bit enables the 10-bit timing measurement counter.
* | | |0 = Time measurement counter is Disabled.
* | | |1 = Time measurement counter is Enabled.
* |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection
* | | |0 = Time measurement counter with fPROT_CLK.
* | | |1 = Time measurement counter with fDIV_CLK.
* |[25:16] |CLKDIV |Clock Divider
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
* | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled
* | | |The revised value is the average bit time between bit 5 and bit 6
* | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate.
* @var USPI_T::DATIN0
* Offset: 0x10 USCI Input Data Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Signal Synchronization Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* @var USPI_T::CTLIN0
* Offset: 0x20 USCI Input Control Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* @var USPI_T::CLKIN
* Offset: 0x28 USCI Input Clock Signal Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* @var USPI_T::LINECTL
* Offset: 0x2C USCI Line Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LSB |LSB First Transmission Selection
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
* |[5] |DATOINV |Data Output Inverse Selection
* | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.
* | | |0 = Data output level is not inverted.
* | | |1 = Data output level is inverted.
* |[7] |CTLOINV |Control Signal Output Inverse Selection
* | | |This bit defines the relation between the internal control signal and the output control signal.
* | | |0 = No effect.
* | | |1 = The control signal will be inverted before its output.
* | | |Note: The control signal has different definitions in different protocol
* | | |In SPI protocol, the control signal means slave select signal
* |[11:8] |DWIDTH |Word Length of Transmission
* | | |This bit field defines the data word length (amount of bits) for reception and transmission
* | | |The data word is always right-aligned in the data buffer
* | | |USCI support word length from 4 to 16 bits.
* | | |0x0: The data word contains 16 bits located at bit positions [15:0].
* | | |0x1: Reserved.
* | | |0x2: Reserved.
* | | |0x3: Reserved.
* | | |0x4: The data word contains 4 bits located at bit positions [3:0].
* | | |0x5: The data word contains 5 bits located at bit positions [4:0].
* | | |...
* | | |0xF: The data word contains 15 bits located at bit positions [14:0].
* @var USPI_T::TXDAT
* Offset: 0x30 USCI Transmit Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXDAT |Transmit Data
* | | |Software can use this bit field to write 16-bit transmit data for transmission
* | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
* |[16] |PORTDIR |Port Direction Control
* | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer
* | | |It is used to define the direction of the data port pin
* | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously.
* | | |0 = The data pin is configured as output mode.
* | | |1 = The data pin is configured as input mode.
* @var USPI_T::RXDAT
* Offset: 0x34 USCI Receive Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RXDAT |Received Data
* | | |This bit field monitors the received data which stored in receive data buffer.
* @var USPI_T::BUFCTL
* Offset: 0x38 USCI Transmit/Receive Buffer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6] |TXUDRIEN |Slave Transmit Under Run Interrupt Enable Bit
* | | |0 = Transmit under-run interrupt Disabled.
* | | |1 = Transmit under-run interrupt Enabled.
* |[7] |TXCLR |Clear Transmit Buffer
* | | |0 = No effect.
* | | |1 = The transmit buffer is cleared
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit
* | | |0 = Receive overrun interrupt Disabled.
* | | |1 = Receive overrun interrupt Enabled.
* |[15] |RXCLR |Clear Receive Buffer
* | | |0 = No effect.
* | | |1 = The receive buffer is cleared
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[16] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[17] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
* | | |Note: It is cleared automatically after one PCLK cycle.
* @var USPI_T::BUFSTS
* Offset: 0x3C USCI Transmit/Receive Buffer Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXEMPTY |Receive Buffer Empty Indicator
* | | |0 = Receive buffer is not empty.
* | | |1 = Receive buffer is empty.
* |[1] |RXFULL |Receive Buffer Full Indicator
* | | |0 = Receive buffer is not full.
* | | |1 = Receive buffer is full.
* |[3] |RXOVIF |Receive Buffer Over-run Interrupt Status
* | | |This bit indicates that a receive buffer overrun event has been detected
* | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated
* | | |It is cleared by software writes 1 to this bit.
* | | |0 = A receive buffer overrun event has not been detected.
* | | |1 = A receive buffer overrun event has been detected.
* |[8] |TXEMPTY |Transmit Buffer Empty Indicator
* | | |0 = Transmit buffer is not empty.
* | | |1 = Transmit buffer is empty and available for the next transmission datum.
* |[9] |TXFULL |Transmit Buffer Full Indicator
* | | |0 = Transmit buffer is not full.
* | | |1 = Transmit buffer is full.
* |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status
* | | |This bit indicates that a transmit buffer under-run event has been detected
* | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated
* | | |It is cleared by software writes 1 to this bit
* | | |0 = A transmit buffer under-run event has not been detected.
* | | |1 = A transmit buffer under-run event has been detected.
* @var USPI_T::PDMACTL
* Offset: 0x40 USCI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
* |[1] |TXPDMAEN |PDMA Transmit Channel Available
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[2] |RXPDMAEN |PDMA Receive Channel Available
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[3] |PDMAEN |PDMA Mode Enable Bit
* | | |0 = PDMA function Disabled.
* | | |1 = PDMA function Enabled.
* | | |Notice: The I2C is not supporting PDMA function.
* @var USPI_T::WKCTL
* Offset: 0x54 USCI Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[1] |WKADDREN |Wake-up Address Match Enable Bit
* | | |0 = The chip is woken up according data toggle.
* | | |1 = The chip is woken up according address match.
* |[2] |PDBOPT |Power Down Blocking Option
* | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
* | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
* @var USPI_T::WKSTS
* Offset: 0x58 USCI Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKF |Wake-up Flag
* | | |When chip is woken up from Power-down mode, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* @var USPI_T::PROTCTL
* Offset: 0x5C USCI Protocol Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SLAVE |Slave Mode Selection
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only)
* | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
* | | |0 = 4-wire bi-direction interface.
* | | |1 = 3-wire bi-direction interface.
* |[2] |SS |Slave Select Control (Master Only)
* | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.
* | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal.
* | | |Note: In SPI protocol, the internal slave select signal is active high.
* |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only)
* | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit.
* | | |1 = Slave select signal will be generated automatically
* | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.
* |[7:6] |SCLKMODE |Serial Bus Clock Mode
* | | |This bit field defines the SCLK idle status, data transmit, and data receive edge.
* | | |MODE0 = The idle state of SPI clock is low level
* | | |Data is transmitted with falling edge and received with rising edge.
* | | |MODE1 = The idle state of SPI clock is low level
* | | |Data is transmitted with rising edge and received with falling edge.
* | | |MODE2 = The idle state of SPI clock is high level
* | | |Data is transmitted with rising edge and received with falling edge.
* | | |MODE3 = The idle state of SPI clock is high level
* | | |Data is transmitted with falling edge and received with rising edge.
* |[11:8] |SUSPITV |Suspend Interval (Master Only)
* | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
* | | |The default value is 0x3
* | | |The period of the suspend interval is obtained according to the following equation.
* | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle
* | | |Example:
* | | |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle.
* | | |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle.
* | | |.....
* | | |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle.
* | | |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle.
* |[14:12] |TSMSEL |Transmit Data Mode Selection
* | | |This bit field describes how receive and transmit data is shifted in and out.
* | | |TSMSEL = 000b: Full-duplex SPI.
* | | |TSMSEL = 100b: Half-duplex SPI.
* | | |Other values are reserved.
* | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
* |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only)
* | | |In Slave mode, this bit field is used for Slave time-out period
* | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event
* | | |Writing 0x0 into this bit field will disable the Slave time-out function.
* | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
* |[28] |TXUDRPOL |Transmit Under-run Data Polarity (for Slave)
* | | |This bit defines the transmitting data level when no data is available for transferring.
* | | |0 = The output data level is 0 if TX under run event occurs.
* | | |1 = The output data level is 1 if TX under run event occurs.
* |[31] |PROTEN |SPI Protocol Enable Bit
* | | |0 = SPI Protocol Disabled.
* | | |1 = SPI Protocol Enabled.
* @var USPI_T::PROTIEN
* Offset: 0x60 USCI Protocol Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Control
* | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
* | | |0 = Slave select inactive interrupt generation Disabled.
* | | |1 = Slave select inactive interrupt generation Enabled.
* |[1] |SSACTIEN |Slave Select Active Interrupt Enable Control
* | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
* | | |0 = Slave select active interrupt generation Disabled.
* | | |1 = Slave select active interrupt generation Enabled.
* |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Control
* | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
* | | |0 = The Slave time-out interrupt Disabled.
* | | |1 = The Slave time-out interrupt Enabled.
* |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Control
* | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8])
* | | |Bit count error event occurs.
* | | |0 = The Slave mode bit count error interrupt Disabled.
* | | |1 = The Slave mode bit count error interrupt Enabled.
* @var USPI_T::PROTSTS
* Offset: 0x64 USCI Protocol Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIF |Transmit Start Interrupt Flag
* | | |0 = Transmit start event does not occur.
* | | |1 = Transmit start event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[2] |TXENDIF |Transmit End Interrupt Flag
* | | |0 = Transmit end event does not occur.
* | | |1 = Transmit end event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[3] |RXSTIF |Receive Start Interrupt Flag
* | | |0 = Receive start event does not occur.
* | | |1 = Receive start event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[4] |RXENDIF |Receive End Interrupt Flag
* | | |0 = Receive end event does not occur.
* | | |1 = Receive end event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[5] |SLVTOIF |Slave Time-out Interrupt Flag (for Slave Only)
* | | |0 = Slave time-out event does not occur.
* | | |1 = Slave time-out event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (for Slave Only)
* | | |0 = Slave bit count error event does not occur.
* | | |1 = Slave bit count error event occurs.
* | | |Note: It is cleared by software writes 1 to this bit.
* |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (for Slave Only)
* | | |This bit indicates that the internal slave select signal has changed to inactive
* | | |It is cleared by software writes 1 to this bit
* | | |0 = The slave select signal has not changed to inactive.
* | | |1 = The slave select signal has changed to inactive.
* | | |Note: The internal slave select signal is active high.
* |[9] |SSACTIF |Slave Select Active Interrupt Flag (for Slave Only)
* | | |This bit indicates that the internal slave select signal has changed to active
* | | |It is cleared by software writes one to this bit
* | | |0 = The slave select signal has not changed to active.
* | | |1 = The slave select signal has changed to active.
* | | |Note: The internal slave select signal is active high.
* |[16] |SSLINE |Slave Select Line Bus Status (Read Only)
* | | |This bit is only available in Slave mode
* | | |It used to monitor the current status of the input slave select signal on the bus.
* | | |0 = The slave select line status is 0.
* | | |1 = The slave select line status is 1.
* |[17] |BUSY |Busy Status (Read Only)
* | | |0 = SPI is in idle state.
* | | |1 = SPI is in busy state.
* | | |The following listing are the bus busy conditions:
* | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0.
* | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
* | | |c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active.
* | | |d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
* |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only)
* | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1
* | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
* | | |0 = Slave transmit under-run event does not occur.
* | | |1 = Slave transmit under-run event occurs.
*/
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
__IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[3];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
__O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
__I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
__IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */
__IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */
__IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[4];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
} USPI_T;
/**
@addtogroup USPI_CONST USPI Bit Field Definition
Constant Definitions for USPI Controller
@{ */
#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */
#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */
#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */
#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */
#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */
#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */
#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */
#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */
#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */
#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */
#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */
#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */
#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */
#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */
#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */
#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */
#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */
#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */
#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */
#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */
#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */
#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */
#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */
#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */
#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */
#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */
#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */
#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */
#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */
#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */
#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */
#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */
#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */
#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */
#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */
#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */
#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */
#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */
#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */
#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */
#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */
#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */
#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */
#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */
#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */
#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */
#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */
#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */
#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */
#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */
#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */
#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */
#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */
#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */
#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */
#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */
#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */
#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */
#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */
#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */
#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */
#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */
#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */
#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */
#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */
#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */
#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */
#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */
#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */
#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */
#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */
#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */
#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */
#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */
#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */
#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */
#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */
#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */
#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */
#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */
#define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */
#define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */
#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */
#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */
#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */
#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */
#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */
#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */
#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */
#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */
#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */
#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */
#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */
#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */
#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */
#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */
#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */
#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */
#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */
#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */
#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */
#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */
#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */
#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */
#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */
#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */
#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */
#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */
#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */
#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */
#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */
#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */
#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */
#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */
#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */
#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */
#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */
#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */
#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */
#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */
#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */
#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */
#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */
#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */
#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */
#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */
#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */
#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */
#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */
#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */
#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */
#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */
#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */
#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */
#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */
#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */
/**@}*/ /* USPI_CONST */
/**@}*/ /* end of USPI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __USPI_REG_H__ */

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/**************************************************************************//**
* @file uuart_reg.h
* @version V3.00
* @brief UUART register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __UUART_REG_H__
#define __UUART_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup UUART UART Mode of USCI Controller(UUART)
Memory Mapped Structure for UUART Controller
@{ */
typedef struct
{
/**
* @var UUART_T::CTL
* Offset: 0x00 USCI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |FUNMODE |Function Mode
* | | |This bit field selects the protocol for this USCI controller.
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI.
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol.
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
* | | |001 = The SPI protocol is selected.
* | | |010 = The UART protocol is selected.
* | | |100 = The I2C protocol is selected.
* | | |Others = Reserved.
* @var UUART_T::INTEN
* Offset: 0x04 USCI Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit start event.
* | | |0 = The transmit start interrupt is disabled.
* | | |1 = The transmit start interrupt is enabled.
* |[2] |TXENDIEN |Transmit End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit finish event.
* | | |0 = The transmit finish interrupt is disabled.
* | | |1 = The transmit finish interrupt is enabled.
* |[3] |RXSTIEN |Receive Start Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a receive start event.
* | | |0 = The receive start interrupt is disabled.
* | | |1 = The receive start interrupt is enabled.
* |[4] |RXENDIEN |Receive End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a receive finish event.
* | | |0 = The receive end interrupt is disabled.
* | | |1 = The receive end interrupt is enabled.
* @var UUART_T::BRGEN
* Offset: 0x08 USCI Baud Rate Generator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RCLKSEL |Reference Clock Source Selection
* | | |This bit selects the source signal of reference clock (fREF_CLK).
* | | |0 = Peripheral device clock fPCLK.
* | | |1 = Reserved.
* |[1] |PTCLKSEL |Protocol Clock Source Selection
* | | |This bit selects the source signal of protocol clock (fPROT_CLK).
* | | |0 = Reference clock fREF_CLK.
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
* | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
* | | |00 = fSAMP_CLK is selected to fDIV_CLK.
* | | |01 = fSAMP_CLK is selected to fPROT_CLK.
* | | |10 = fSAMP_CLK is selected to fSCLK.
* | | |11 = fSAMP_CLK is selected to fREF_CLK.
* |[4] |TMCNTEN |Timing Measurement Counter Enable Bit
* | | |This bit enables the 10-bit timing measurement counter.
* | | |0 = Timing measurement counter is Disabled.
* | | |1 = Timing measurement counter is Enabled.
* |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection
* | | |0 = Timing measurement counter with fPROT_CLK.
* | | |1 = Timing measurement counter with fDIV_CLK.
* |[9:8] |PDSCNT |Pre-divider for Sample Counter
* | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK.
* | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
* |[14:10] |DSCNT |Denominator for Sample Counter
* | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
* | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
* | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
* |[25:16] |CLKDIV |Clock Divider
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
* | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled.
* | | |The revised value is the average bit time between bit 5 and bit 6.
* | | |The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.
* @var UUART_T::DATIN0
* Offset: 0x10 USCI Input Data Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Signal Synchronization Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* |[4:3] |EDGEDET |Input Signal Edge Detection Mode
* | | |This bit field selects which edge actives the trigger event of input data signal.
* | | |00 = The trigger event activation is disabled.
* | | |01 = A rising edge activates the trigger event of input data signal.
* | | |10 = A falling edge activates the trigger event of input data signal.
* | | |11 = Both edges activate the trigger event of input data signal.
* | | |Note: In UART function mode, it is suggested to set this bit field as 0x2.
* @var UUART_T::CTLIN0
* Offset: 0x20 USCI Input Control Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* @var UUART_T::CLKIN
* Offset: 0x28 USCI Input Clock Signal Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* @var UUART_T::LINECTL
* Offset: 0x2C USCI Line Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LSB |LSB First Transmission Selection
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
* |[5] |DATOINV |Data Output Inverse Selection
* | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
* | | |0 = The value of USCIx_DAT1 is equal to the data shift register.
* | | |1 = The value of USCIx_DAT1 is the inversion of data shift register.
* |[7] |CTLOINV |Control Signal Output Inverse Selection
* | | |This bit defines the relation between the internal control signal and the output control signal.
* | | |0 = No effect.
* | | |1 = The control signal will be inverted before its output.
* | | |Note: In UART protocol, the control signal means nRTS signal.
* |[11:8] |DWIDTH |Word Length of Transmission
* | | |This bit field defines the data word length (amount of bits) for reception and transmission.
* | | |The data word is always right-aligned in the data buffer.
* | | |USCI support word length from 4 to 16 bits.
* | | |0000 = The data word contains 16 bits located at bit positions [15:0].
* | | |0001 = Reserved.
* | | |0010 = Reserved.
* | | |0011 = Reserved.
* | | |0100 = The data word contains 4 bits located at bit positions [3:0].
* | | |0101 = The data word contains 5 bits located at bit positions [4:0].
* | | |0110 = The data word contains 6 bits located at bit positions [5:0].
* | | |0111 = The data word contains 7 bits located at bit positions [6:0].
* | | |1000 = The data word contains 8 bits located at bit positions [7:0].
* | | |1001 = The data word contains 9 bits located at bit positions [8:0].
* | | |1010 = The data word contains 10 bits located at bit positions [9:0].
* | | |1011 = The data word contains 11 bits located at bit positions [10:0].
* | | |1100 = The data word contains 12 bits located at bit positions [11:0].
* | | |1101 = The data word contains 13 bits located at bit positions [12:0].
* | | |1110 = The data word contains 14 bits located at bit positions [13:0].
* | | |1111 = The data word contains 15 bits located at bit positions [14:0].
* | | |Note: In UART protocol, the length can be configured as 6~13 bits.
* @var UUART_T::TXDAT
* Offset: 0x30 USCI Transmit Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXDAT |Transmit Data
* | | |Software can use this bit field to write 16-bit transmit data for transmission.
* @var UUART_T::RXDAT
* Offset: 0x34 USCI Receive Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RXDAT |Received Data
* | | |This bit field monitors the received data which stored in receive data buffer.
* | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]).
* @var UUART_T::BUFCTL
* Offset: 0x38 USCI Transmit/Receive Buffer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7] |TXCLR |Clear Transmit Buffer
* | | |0 = No effect.
* | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value).
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control
* | | |0 = Receive overrun interrupt Disabled.
* | | |1 = Receive overrun interrupt Enabled.
* |[15] |RXCLR |Clear Receive Buffer
* | | |0 = No effect.
* | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value).
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[16] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[17] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
* | | |Note 1: It is cleared automatically after one PCLK cycle.
* | | |Note 2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.
* @var UUART_T::BUFSTS
* Offset: 0x3C USCI Transmit/Receive Buffer Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXEMPTY |Receive Buffer Empty Indicator
* | | |0 = Receive buffer is not empty.
* | | |1 = Receive buffer is empty.
* |[1] |RXFULL |Receive Buffer Full Indicator
* | | |0 = Receive buffer is not full.
* | | |1 = Receive buffer is full.
* |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status
* | | |This bit indicates that a receive buffer overrun error event has been detected.
* | | |If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated.
* | | |It is cleared by software writes 1 to this bit.
* | | |0 = A receive buffer overrun error event has not been detected.
* | | |1 = A receive buffer overrun error event has been detected.
* |[8] |TXEMPTY |Transmit Buffer Empty Indicator
* | | |0 = Transmit buffer is not empty.
* | | |1 = Transmit buffer is empty.
* |[9] |TXFULL |Transmit Buffer Full Indicator
* | | |0 = Transmit buffer is not full.
* | | |1 = Transmit buffer is full.
* @var UUART_T::PDMACTL
* Offset: 0x40 USCI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
* |[1] |TXPDMAEN |PDMA Transmit Channel Available
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[2] |RXPDMAEN |PDMA Receive Channel Available
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[3] |PDMAEN |PDMA Mode Enable Bit
* | | |0 = PDMA function Disabled.
* | | |1 = PDMA function Enabled.
* @var UUART_T::WKCTL
* Offset: 0x54 USCI Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[2] |PDBOPT |Power Down Blocking Option
* | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
* | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
* @var UUART_T::WKSTS
* Offset: 0x58 USCI Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKF |Wake-up Flag
* | | |When chip is woken up from Power-down mode, this bit is set to 1.
* | | |Software can write 1 to clear this bit.
* @var UUART_T::PROTCTL
* Offset: 0x5C USCI Protocol Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |STOPB |Stop Bits
* | | |This bit defines the number of stop bits in an UART frame.
* | | |0 = The number of stop bits is 1.
* | | |1 = The number of stop bits is 2.
* |[1] |PARITYEN |Parity Enable Bit
* | | |This bit defines the parity bit is enabled in an UART frame.
* | | |0 = The parity bit Disabled.
* | | |1 = The parity bit Enabled.
* |[2] |EVENPARITY|Even Parity Enable Bit
* | | |0 = Odd number of logic 1's is transmitted and checked in each word.
* | | |1 = Even number of logic 1's is transmitted and checked in each word.
* | | |Note: This bit has effect only when PARITYEN is set.
* |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit
* | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (UUART_BUFSTS[1] = 1)), the UART will de-assert nRTS signal.
* | | |0 = nRTS auto-flow control Disabled.
* | | |1 = nRTS auto-flow control Enabled.
* | | |Note: This bit has effect only when the RTSAUDIREN is not set.
* |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit
* | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
* | | |0 = nCTS auto-flow control Disabled.
* | | |1 = nCTS auto-flow control Enabled.
* |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit
* | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically.
* | | |0 = nRTS auto direction control Disabled.
* | | |1 = nRTS auto direction control Enabled.
* | | |Note 1: This bit is used for nRTS auto direction control for RS485.
* | | |Note 2: This bit has effect only when the RTSAUTOEN is not set.
* |[6] |ABREN |Auto-baud Rate Detect Enable Bit
* | | |0 = Auto-baud rate detect function Disabled.
* | | |1 = Auto-baud rate detect function Enabled.
* | | |Note: When the auto-baud rate detect operation finishes, hardware will clear this bit.
* | | |The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
* |[9] |DATWKEN |Data Wake-up Mode Enable Bit
* | | |0 = Data wake-up mode Disabled.
* | | |1 = Data wake-up mode Enabled.
* |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit
* | | |0 = nCTS wake-up mode Disabled.
* | | |1 = nCTS wake-up mode Enabled.
* |[14:11] |WAKECNT |Wake-up Counter
* | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode.
* |[24:16] |BRDETITV |Baud Rate Detection Interval
* | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits.
* | | |The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55).
* | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.
* | | |Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV.
* |[26] |STICKEN |Stick Parity Enable Bit
* | | |0 = Stick parity Disabled.
* | | |1 = Stick parity Enabled.
* | | |Note: Refer to RS-485 Support section for detail information.
* |[29] |BCEN |Transmit Break Control Enable Bit
* | | |0 = Transmit Break Control Disabled.
* | | |1 = Transmit Break Control Enabled.
* | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
* | | |This bit acts only on TX line and has no effect on the transmitter logic.
* |[30] |DGE |Deglitch Enable Bit
* | | |0 = Deglitch Disabled.
* | | |1 = Deglitch Enabled.
* | | |Note 1: When this bit is set to logic 1, any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX).
* | | |This bit acts only on RX line and has no effect on the transmitter logic.
* | | |Note 2: It is recommended to set this bit only when operating at baud rate under 2.5 Mbps.
* |[31] |PROTEN |UART Protocol Enable Bit
* | | |0 = UART Protocol Disabled.
* | | |1 = UART Protocol Enabled.
* @var UUART_T::PROTIEN
* Offset: 0x60 USCI Protocol Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit
* | | |0 = Auto-baud rate interrupt Disabled.
* | | |1 = Auto-baud rate interrupt Enabled.
* |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit
* | | |0 = Receive line status interrupt Disabled.
* | | |1 = Receive line status interrupt Enabled.
* | | |Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
* @var UUART_T::PROTSTS
* Offset: 0x64 USCI Protocol Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIF |Transmit Start Interrupt Flag
* | | |0 = A transmit start interrupt status has not occurred.
* | | |1 = A transmit start interrupt status has occurred.
* | | |Note 1: It is cleared by software writing one into this bit.
* | | |Note 2: Used for user to load next transmit data when there is no data in transmit buffer.
* |[2] |TXENDIF |Transmit End Interrupt Flag
* | | |0 = A transmit end interrupt status has not occurred.
* | | |1 = A transmit end interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit.
* |[3] |RXSTIF |Receive Start Interrupt Flag
* | | |0 = A receive start interrupt status has not occurred.
* | | |1 = A receive start interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit.
* |[4] |RXENDIF |Receive End Interrupt Flag
* | | |0 = A receive finish interrupt status has not occurred.
* | | |1 = A receive finish interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit.
* |[5] |PARITYERR |Parity Error Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.
* | | |0 = No parity error is generated.
* | | |1 = Parity error is generated.
* | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
* |[6] |FRMERR |Framing Error Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit'(that is, the stop bit following the last data bit or parity bit is detected as logic 0).
* | | |0 = No framing error is generated.
* | | |1 = Framing error is generated.
* | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
* |[7] |BREAK |Break Flag
* | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state'
* | | |(logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
* | | |0 = No Break is generated.
* | | |1 = Break is generated in the receiver bus.
* | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits.
* |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag
* | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data.
* | | |If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated.
* | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.
* | | |0 = Auto-baud rate detect function is not done.
* | | |1 = One Bit auto-baud rate detect function is done.
* | | |Note: This bit can be cleared by writing '1' to it.
* |[10] |RXBUSY |RX Bus Status Flag (Read Only)
* | | |This bit indicates the busy status of the receiver.
* | | |0 = The receiver is Idle.
* | | |1 = The receiver is BUSY.
* |[11] |ABERRSTS |Auto-baud Rate Error Status
* | | |This bit is set when auto-baud rate detection counter overrun
* | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.
* | | |0 = Auto-baud rate detect counter is not overrun.
* | | |1 = Auto-baud rate detect counter is overrun.
* | | |Note 1: This bit is set at the same time of ABRDETIF.
* | | |Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS.
* |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only)
* | | |This bit used to indicate the current status of the internal synchronized nCTS signal.
* | | |0 = The internal synchronized nCTS is low.
* | | |1 = The internal synchronized nCTS is high.
* |[17] |CTSLV |nCTS Pin Status (Read Only)
* | | |This bit used to monitor the current status of nCTS pin input.
* | | |0 = nCTS pin input is low level voltage logic state.
* | | |1 = nCTS pin input is high level voltage logic state.
*/
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
__IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[3];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
__IO uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
__IO uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
__IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */
__IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */
__IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE3[4];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
} UUART_T;
/**
@addtogroup UUART_CONST UUART Bit Field Definition
Constant Definitions for UUART Controller
@{ */
#define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */
#define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */
#define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */
#define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */
#define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */
#define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */
#define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */
#define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */
#define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */
#define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */
#define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */
#define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */
#define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */
#define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */
#define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */
#define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */
#define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */
#define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */
#define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */
#define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */
#define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */
#define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */
#define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */
#define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */
#define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */
#define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */
#define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */
#define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */
#define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */
#define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */
#define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */
#define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */
#define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */
#define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */
#define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */
#define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */
#define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */
#define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */
#define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */
#define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */
#define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */
#define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */
#define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */
#define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */
#define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */
#define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */
#define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */
#define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */
#define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */
#define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */
#define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */
#define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */
#define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */
#define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */
#define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */
#define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */
#define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */
#define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */
#define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */
#define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */
#define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */
#define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */
#define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */
#define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */
#define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */
#define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */
#define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */
#define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */
#define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */
#define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */
#define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */
#define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */
#define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */
#define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */
#define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */
#define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */
#define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */
#define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */
#define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */
#define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */
#define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */
#define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */
#define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */
#define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */
#define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */
#define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */
#define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */
#define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */
#define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */
#define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */
#define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */
#define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */
#define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */
#define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */
#define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */
#define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */
#define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */
#define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */
#define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */
#define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */
#define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */
#define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */
#define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */
#define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */
#define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */
#define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */
#define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */
#define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */
#define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */
#define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */
#define UUART_PROTCTL_DGE_Pos (30) /*!< UUART_T::PROTCTL: DGE Position */
#define UUART_PROTCTL_DGE_Msk (0x1ul << UUART_PROTCTL_DGE_Pos) /*!< UUART_T::PROTCTL: DGE Mask */
#define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */
#define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */
#define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */
#define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */
#define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */
#define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */
#define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */
#define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */
#define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */
#define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */
#define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */
#define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */
#define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */
#define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */
#define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */
#define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */
#define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */
#define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */
#define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */
#define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */
#define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */
#define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */
#define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */
#define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */
#define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */
#define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */
#define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */
#define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */
#define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */
#define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */
/**@}*/ /* UUART_CONST */
/**@}*/ /* end of UUART register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __UUART_REG_H__ */

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@ -0,0 +1,176 @@
/**************************************************************************//**
* @file wdt_reg.h
* @version V3.00
* @brief WDT register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WDT_REG_H__
#define __WDT_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Watch Dog Timer Controller -------------------------*/
/**
@addtogroup WDT Watch Dog Timer Controller(WDT)
Memory Mapped Structure for WDT Controller
@{
*/
typedef struct
{
/**
* @var WDT_T::CTL
* Offset: 0x00 WDT Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect)
* | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
* | | |0 = WDT time-out reset function Disabled.
* | | |1 = WDT time-out reset function Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[2] |RSTF |WDT Time-out Reset Flag
* | | |This bit indicates the system has been reset by WDT time-out reset or not.
* | | |0 = WDT time-out reset did not occur.
* | | |1 = WDT time-out reset occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[3] |IF |WDT Time-out Interrupt Flag
* | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
* | | |0 = WDT time-out interrupt did not occur.
* | | |1 = WDT time-out interrupt occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect)
* | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
* | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
* | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT.
* |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect)
* | | |This bit indicates the interrupt wake-up flag status of WDT
* | | |0 = WDT does not cause chip wake-up.
* | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
* | | |Note: This bit is cleared by writing 1 to it.
* |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect)
* | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
* | | |0 = WDT time-out interrupt Disabled.
* | | |1 = WDT time-out interrupt Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[7] |WDTEN |WDT Enable Bit (Write Protect)
* | | |0 = WDT Disabled (This action will reset the internal up counter value).
* | | |1 = WDT Enabled.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
* |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect)
* | | |These three bits select the time-out interval period for the WDT.
* | | |000 = 2^4 * WDT_CLK.
* | | |001 = 2^6 * WDT_CLK.
* | | |010 = 2^8 * WDT_CLK.
* | | |011 = 2^10 * WDT_CLK.
* | | |100 = 2^12 * WDT_CLK.
* | | |101 = 2^14 * WDT_CLK.
* | | |110 = 2^16 * WDT_CLK.
* | | |111 = 2^18 * WDT_CLK.
* | | |111 = 2^20 * WDT_CLK.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only)
* | | |If user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.
* | | |0 = Setting WDTEN bit is completed and WDT is ready.
* | | |1 = Setting WDTEN bit is synchronizing and not become active yet.
* | | |Note: Perform enable or disable WDTEN bit needs 4 * WDT_CLK period to become active.
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
* | | |0 = ICE debug mode acknowledgement affects WDT counting.
* | | |WDT up counter will be held while CPU is held by ICE.
* | | |1 = ICE debug mode acknowledgement Disabled.
* | | |WDT up counter will keep going no matter CPU is held by ICE or not.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var WDT_T::ALTCTL
* Offset: 0x04 WDT Alternative Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect)
* | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by programming 0x5AA5 to prevent WDT time-out reset happened.
* | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
* | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
* | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
* | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
* | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: This register will be reset to 0 if WDT time-out reset happened.
* @var WDT_T::RSTCNT
* Offset: 0x08 WDT Reset Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RSTCNT |WDT Reset Counter Register
* | | |Writing 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0.
* | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
*/
__IO uint32_t CTL; /*!< [0x0000] WDT Control Register */
__IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */
__O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */
} WDT_T;
/**
@addtogroup WDT_CONST WDT Bit Field Definition
Constant Definitions for WDT Controller
@{
*/
#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
#define WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */
#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */
#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */
#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */
/**@}*/ /* WDT_CONST */
/**@}*/ /* end of WDT register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __WDT_REG_H__ */

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/**************************************************************************//**
* @file wwdt_reg.h
* @version V3.00
* @brief WWDT register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WWDT_REG_H__
#define __WWDT_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Window Watchdog Timer -------------------------*/
/**
@addtogroup WWDT Window Watchdog Timer(WWDT)
Memory Mapped Structure for WWDT Controller
@{
*/
typedef struct
{
/**
* @var WWDT_T::RLDCNT
* Offset: 0x00 WWDT Reload Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RLDCNT |WWDT Reload Counter Register
* | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]).
* | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately.
* @var WWDT_T::CTL
* Offset: 0x04 WWDT Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WWDTEN |WWDT Enable Bit
* | | |0 = Indicates WWDT counter is stopped.
* | | |1 = Enable WWDT counter starts counting.
* |[1] |INTEN |WWDT Interrupt Enable Bit
* | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
* | | |0 = WWDT counter compare match interrupt Disabled.
* | | |1 = WWDT counter compare match interrupt Enabled.
* |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
* | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
* | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
* | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
* | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
* | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
* | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
* | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
* | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
* | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
* | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
* | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
* | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
* | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
* | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
* | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
* | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
* |[21:16] |CMPDAT |WWDT Window Compare
* | | |Set this register to adjust the valid reload window.
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
* | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit
* | | |0 = ICE debug mode acknowledgement effects WWDT counting.
* | | |WWDT down counter will be held while CPU is held by ICE.
* | | |1 = ICE debug mode acknowledgement Disabled.
* | | |WWDT down counter will keep going no matter CPU is held by ICE or not.
* @var WWDT_T::STATUS
* Offset: 0x08 WWDT Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
* | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
* | | |0 = No effect.
* | | |1 = WWDT counter value matches CMPDAT.
* | | |Note: This bit is cleared by writing 1 to it.
* |[1] |WWDTRF |WWDT Timer-out Reset Flag
* | | |This bit indicates the system has been reset by WWDT time-out reset or not.
* | | |0 = WWDT time-out reset did not occur.
* | | |1 = WWDT time-out reset occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* @var WWDT_T::CNT
* Offset: 0x0C WWDT Counter Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |CNTDAT |WWDT Counter Value
* | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
*/
__O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */
__IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */
__IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */
__I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */
} WWDT_T;
/**
@addtogroup WWDT_CONST WWDT Bit Field Definition
Constant Definitions for WWDT Controller
@{
*/
#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */
#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */
#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */
#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */
#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */
#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */
#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */
#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */
#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */
#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */
#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */
#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */
#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */
#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */
#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */
#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */
#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */
#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */
/**@}*/ /* WWDT_CONST */
/**@}*/ /* end of WWDT register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __WWDT_REG_H__ */

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;/******************************************************************************
; * @file startup_m460.s
; * @version V3.00
; * @brief CMSIS Cortex-M4 Core Device Startup File for M460
; *
; * @copyright SPDX-License-Identifier: Apache-2.0
; * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
;*****************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :LNOT: :DEF: Stack_Size
Stack_Size EQU 0x00000800
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :LNOT: :DEF: Heap_Size
Heap_Size EQU 0x00000100
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD BOD_IRQHandler ; 0: Brown Out detection
DCD IRC_IRQHandler ; 1: Internal RC
DCD PWRWU_IRQHandler ; 2: Power down wake up
DCD RAMPE_IRQHandler ; 3: RAM parity error
DCD CKFAIL_IRQHandler ; 4: Clock detection fail
DCD ISP_IRQHandler ; 5: ISP
DCD RTC_IRQHandler ; 6: Real Time Clock
DCD TAMPER_IRQHandler ; 7: Tamper detection
DCD WDT_IRQHandler ; 8: Watchdog timer
DCD WWDT_IRQHandler ; 9: Window watchdog timer
DCD EINT0_IRQHandler ; 10: External Input 0
DCD EINT1_IRQHandler ; 11: External Input 1
DCD EINT2_IRQHandler ; 12: External Input 2
DCD EINT3_IRQHandler ; 13: External Input 3
DCD EINT4_IRQHandler ; 14: External Input 4
DCD EINT5_IRQHandler ; 15: External Input 5
DCD GPA_IRQHandler ; 16: GPIO Port A
DCD GPB_IRQHandler ; 17: GPIO Port B
DCD GPC_IRQHandler ; 18: GPIO Port C
DCD GPD_IRQHandler ; 19: GPIO Port D
DCD GPE_IRQHandler ; 20: GPIO Port E
DCD GPF_IRQHandler ; 21: GPIO Port F
DCD QSPI0_IRQHandler ; 22: QSPI0
DCD SPI0_IRQHandler ; 23: SPI0
DCD BRAKE0_IRQHandler ; 24: EPWM0 brake
DCD EPWM0P0_IRQHandler ; 25: EPWM0 pair 0
DCD EPWM0P1_IRQHandler ; 26: EPWM0 pair 1
DCD EPWM0P2_IRQHandler ; 27: EPWM0 pair 2
DCD BRAKE1_IRQHandler ; 28: EPWM1 brake
DCD EPWM1P0_IRQHandler ; 29: EPWM1 pair 0
DCD EPWM1P1_IRQHandler ; 30: EPWM1 pair 1
DCD EPWM1P2_IRQHandler ; 31: EPWM1 pair 2
DCD TMR0_IRQHandler ; 32: Timer 0
DCD TMR1_IRQHandler ; 33: Timer 1
DCD TMR2_IRQHandler ; 34: Timer 2
DCD TMR3_IRQHandler ; 35: Timer 3
DCD UART0_IRQHandler ; 36: UART0
DCD UART1_IRQHandler ; 37: UART1
DCD I2C0_IRQHandler ; 38: I2C0
DCD I2C1_IRQHandler ; 39: I2C1
DCD PDMA0_IRQHandler ; 40: Peripheral DMA 0
DCD DAC_IRQHandler ; 41: DAC
DCD EADC00_IRQHandler ; 42: EADC0 interrupt source 0
DCD EADC01_IRQHandler ; 43: EADC0 interrupt source 1
DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1
DCD ACMP23_IRQHandler ; 45: ACMP2 and ACMP3
DCD EADC02_IRQHandler ; 46: EADC0 interrupt source 2
DCD EADC03_IRQHandler ; 47: EADC0 interrupt source 3
DCD UART2_IRQHandler ; 48: UART2
DCD UART3_IRQHandler ; 49: UART3
DCD QSPI1_IRQHandler ; 50: QSPI1
DCD SPI1_IRQHandler ; 51: SPI1
DCD SPI2_IRQHandler ; 52: SPI2
DCD USBD_IRQHandler ; 53: USB device
DCD OHCI_IRQHandler ; 54: OHCI
DCD USBOTG_IRQHandler ; 55: USB OTG
DCD BMC_IRQHandler ; 56: BMC
DCD SPI5_IRQHandler ; 57: SPI5
DCD SC0_IRQHandler ; 58: SC0
DCD SC1_IRQHandler ; 59: SC1
DCD SC2_IRQHandler ; 60: SC2
DCD GPJ_IRQHandler ; 61: GPIO Port J
DCD SPI3_IRQHandler ; 62: SPI3
DCD SPI4_IRQHandler ; 63: SPI4
DCD SDH0_IRQHandler ; 64: SDH0
DCD USBD20_IRQHandler ; 65: USBD20
DCD EMAC0_IRQHandler ; 66: EMAC0
DCD Default_Handler ; 67:
DCD I2S0_IRQHandler ; 68: I2S0
DCD I2S1_IRQHandler ; 69: I2S1
DCD SPI6_IRQHandler ; 70: SPI6
DCD CRPT_IRQHandler ; 71: CRYPTO
DCD GPG_IRQHandler ; 72: GPIO Port G
DCD EINT6_IRQHandler ; 73: External Input 6
DCD UART4_IRQHandler ; 74: UART4
DCD UART5_IRQHandler ; 75: UART5
DCD USCI0_IRQHandler ; 76: USCI0
DCD SPI7_IRQHandler ; 77: SPI7
DCD BPWM0_IRQHandler ; 78: BPWM0
DCD BPWM1_IRQHandler ; 79: BPWM1
DCD SPIM_IRQHandler ; 80: SPIM
DCD CCAP_IRQHandler ; 81: CCAP
DCD I2C2_IRQHandler ; 82: I2C2
DCD I2C3_IRQHandler ; 83: I2C3
DCD EQEI0_IRQHandler ; 84: EQEI0
DCD EQEI1_IRQHandler ; 85: EQEI1
DCD ECAP0_IRQHandler ; 86: ECAP0
DCD ECAP1_IRQHandler ; 87: ECAP1
DCD GPH_IRQHandler ; 88: GPIO Port H
DCD EINT7_IRQHandler ; 89: External Input 7
DCD SDH1_IRQHandler ; 90: SDH1
DCD PSIO_IRQHandler ; 91: PSIO
DCD EHCI_IRQHandler ; 92: EHCI
DCD USBOTG20_IRQHandler ; 93: HSOTG
DCD ECAP2_IRQHandler ; 94: ECAP2
DCD ECAP3_IRQHandler ; 95: ECAP3
DCD KPI_IRQHandler ; 96: KPI
DCD HBI_IRQHandler ; 97: HBI
DCD PDMA1_IRQHandler ; 98: Peripheral DMA 1
DCD UART8_IRQHandler ; 99: UART8
DCD UART9_IRQHandler ; 100: UART9
DCD TRNG_IRQHandler ; 101: TRNG
DCD UART6_IRQHandler ; 102: UART6
DCD UART7_IRQHandler ; 103: UART7
DCD EADC10_IRQHandler ; 104: EADC1 interrupt source 0
DCD EADC11_IRQHandler ; 105: EADC1 interrupt source 1
DCD EADC12_IRQHandler ; 106: EADC1 interrupt source 2
DCD EADC13_IRQHandler ; 107: EADC1 interrupt source 3
DCD SPI8_IRQHandler ; 108: SPI8
DCD KS_IRQHandler ; 109: Key Store
DCD GPI_IRQHandler ; 110: GPIO Port I
DCD SPI9_IRQHandler ; 111: SPI9
DCD CANFD00_IRQHandler ; 112: CANFD0 interrupt source 0
DCD CANFD01_IRQHandler ; 113: CANFD0 interrupt source 1
DCD CANFD10_IRQHandler ; 114: CANFD1 interrupt source 0
DCD CANFD11_IRQHandler ; 115: CANFD1 interrupt source 1
DCD EQEI2_IRQHandler ; 116: EQEI2
DCD EQEI3_IRQHandler ; 117: EQEI3
DCD I2C4_IRQHandler ; 118: I2C4
DCD SPI10_IRQHandler ; 119: SPI10
DCD CANFD20_IRQHandler ; 120: CANFD2 interrupt source 0
DCD CANFD21_IRQHandler ; 121: CANFD2 interrupt source 1
DCD CANFD30_IRQHandler ; 122: CANFD3 interrupt source 0
DCD CANFD31_IRQHandler ; 123: CANFD3 interrupt source 1
DCD EADC20_IRQHandler ; 124: EADC2 interrupt source 0
DCD EADC21_IRQHandler ; 125: EADC2 interrupt source 1
DCD EADC22_IRQHandler ; 126: EADC2 interrupt source 2
DCD EADC23_IRQHandler ; 127: EADC2 interrupt source 3
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
; Unlock Register
LDR R0, =0x40000100
LDR R1, =0x59
STR R1, [R0]
LDR R1, =0x16
STR R1, [R0]
LDR R1, =0x88
STR R1, [R0]
IF :LNOT: :DEF: ENABLE_SPIM_CACHE
LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
ORR R1, R1, #0x4000
STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;
LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
LDR R1, [R0,#4] ; R1 = SPIM->CTL1
ORR R1, R1,#2 ; R1 |= SPIM_CTL1_CACHEOFF_Msk
STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE()
LDR R1, [R0,#4] ; R1 = SPIM->CTL1
ORR R1, R1, #4 ; R1 |= SPIM_CTL1_CCMEN_Msk
STR R1, [R0,#4] ; _SPIM_ENABLE_CCM()
ENDIF
LDR R0, =SystemInit
BLX R0
; Lock
LDR R0, =0x40000100
LDR R1, =0
STR R1, [R0]
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BOD_IRQHandler [WEAK]
EXPORT IRC_IRQHandler [WEAK]
EXPORT PWRWU_IRQHandler [WEAK]
EXPORT RAMPE_IRQHandler [WEAK]
EXPORT CKFAIL_IRQHandler [WEAK]
EXPORT ISP_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT WWDT_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT EINT4_IRQHandler [WEAK]
EXPORT EINT5_IRQHandler [WEAK]
EXPORT GPA_IRQHandler [WEAK]
EXPORT GPB_IRQHandler [WEAK]
EXPORT GPC_IRQHandler [WEAK]
EXPORT GPD_IRQHandler [WEAK]
EXPORT GPE_IRQHandler [WEAK]
EXPORT GPF_IRQHandler [WEAK]
EXPORT QSPI0_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT BRAKE0_IRQHandler [WEAK]
EXPORT EPWM0P0_IRQHandler [WEAK]
EXPORT EPWM0P1_IRQHandler [WEAK]
EXPORT EPWM0P2_IRQHandler [WEAK]
EXPORT BRAKE1_IRQHandler [WEAK]
EXPORT EPWM1P0_IRQHandler [WEAK]
EXPORT EPWM1P1_IRQHandler [WEAK]
EXPORT EPWM1P2_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT PDMA0_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT EADC00_IRQHandler [WEAK]
EXPORT EADC01_IRQHandler [WEAK]
EXPORT ACMP01_IRQHandler [WEAK]
EXPORT ACMP23_IRQHandler [WEAK]
EXPORT EADC02_IRQHandler [WEAK]
EXPORT EADC03_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT QSPI1_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USBD_IRQHandler [WEAK]
EXPORT OHCI_IRQHandler [WEAK]
EXPORT USBOTG_IRQHandler [WEAK]
EXPORT BMC_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SC0_IRQHandler [WEAK]
EXPORT SC1_IRQHandler [WEAK]
EXPORT SC2_IRQHandler [WEAK]
EXPORT GPJ_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SDH0_IRQHandler [WEAK]
EXPORT USBD20_IRQHandler [WEAK]
EXPORT EMAC0_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT CRPT_IRQHandler [WEAK]
EXPORT GPG_IRQHandler [WEAK]
EXPORT EINT6_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT USCI0_IRQHandler [WEAK]
EXPORT SPI7_IRQHandler [WEAK]
EXPORT BPWM0_IRQHandler [WEAK]
EXPORT BPWM1_IRQHandler [WEAK]
EXPORT SPIM_IRQHandler [WEAK]
EXPORT CCAP_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT I2C3_IRQHandler [WEAK]
EXPORT EQEI0_IRQHandler [WEAK]
EXPORT EQEI1_IRQHandler [WEAK]
EXPORT ECAP0_IRQHandler [WEAK]
EXPORT ECAP1_IRQHandler [WEAK]
EXPORT GPH_IRQHandler [WEAK]
EXPORT EINT7_IRQHandler [WEAK]
EXPORT SDH1_IRQHandler [WEAK]
EXPORT PSIO_IRQHandler [WEAK]
EXPORT EHCI_IRQHandler [WEAK]
EXPORT USBOTG20_IRQHandler [WEAK]
EXPORT ECAP2_IRQHandler [WEAK]
EXPORT ECAP3_IRQHandler [WEAK]
EXPORT KPI_IRQHandler [WEAK]
EXPORT HBI_IRQHandler [WEAK]
EXPORT PDMA1_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT UART9_IRQHandler [WEAK]
EXPORT TRNG_IRQHandler [WEAK]
EXPORT UART6_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT EADC10_IRQHandler [WEAK]
EXPORT EADC11_IRQHandler [WEAK]
EXPORT EADC12_IRQHandler [WEAK]
EXPORT EADC13_IRQHandler [WEAK]
EXPORT SPI8_IRQHandler [WEAK]
EXPORT KS_IRQHandler [WEAK]
EXPORT GPI_IRQHandler [WEAK]
EXPORT SPI9_IRQHandler [WEAK]
EXPORT CANFD00_IRQHandler [WEAK]
EXPORT CANFD01_IRQHandler [WEAK]
EXPORT CANFD10_IRQHandler [WEAK]
EXPORT CANFD11_IRQHandler [WEAK]
EXPORT EQEI2_IRQHandler [WEAK]
EXPORT EQEI3_IRQHandler [WEAK]
EXPORT I2C4_IRQHandler [WEAK]
EXPORT SPI10_IRQHandler [WEAK]
EXPORT CANFD20_IRQHandler [WEAK]
EXPORT CANFD21_IRQHandler [WEAK]
EXPORT CANFD30_IRQHandler [WEAK]
EXPORT CANFD31_IRQHandler [WEAK]
EXPORT EADC20_IRQHandler [WEAK]
EXPORT EADC21_IRQHandler [WEAK]
EXPORT EADC22_IRQHandler [WEAK]
EXPORT EADC23_IRQHandler [WEAK]
Default__IRQHandler
BOD_IRQHandler
IRC_IRQHandler
PWRWU_IRQHandler
RAMPE_IRQHandler
CKFAIL_IRQHandler
ISP_IRQHandler
RTC_IRQHandler
TAMPER_IRQHandler
WDT_IRQHandler
WWDT_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
EINT5_IRQHandler
GPA_IRQHandler
GPB_IRQHandler
GPC_IRQHandler
GPD_IRQHandler
GPE_IRQHandler
GPF_IRQHandler
QSPI0_IRQHandler
SPI0_IRQHandler
BRAKE0_IRQHandler
EPWM0P0_IRQHandler
EPWM0P1_IRQHandler
EPWM0P2_IRQHandler
BRAKE1_IRQHandler
EPWM1P0_IRQHandler
EPWM1P1_IRQHandler
EPWM1P2_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
PDMA0_IRQHandler
DAC_IRQHandler
EADC00_IRQHandler
EADC01_IRQHandler
ACMP01_IRQHandler
ACMP23_IRQHandler
EADC02_IRQHandler
EADC03_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
QSPI1_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USBD_IRQHandler
OHCI_IRQHandler
USBOTG_IRQHandler
BMC_IRQHandler
SPI5_IRQHandler
SC0_IRQHandler
SC1_IRQHandler
SC2_IRQHandler
GPJ_IRQHandler
SPI3_IRQHandler
SPI4_IRQHandler
SDH0_IRQHandler
USBD20_IRQHandler
EMAC0_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPI6_IRQHandler
CRPT_IRQHandler
GPG_IRQHandler
EINT6_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
USCI0_IRQHandler
SPI7_IRQHandler
BPWM0_IRQHandler
BPWM1_IRQHandler
SPIM_IRQHandler
CCAP_IRQHandler
I2C2_IRQHandler
I2C3_IRQHandler
EQEI0_IRQHandler
EQEI1_IRQHandler
ECAP0_IRQHandler
ECAP1_IRQHandler
GPH_IRQHandler
EINT7_IRQHandler
SDH1_IRQHandler
PSIO_IRQHandler
EHCI_IRQHandler
USBOTG20_IRQHandler
ECAP2_IRQHandler
ECAP3_IRQHandler
KPI_IRQHandler
HBI_IRQHandler
PDMA1_IRQHandler
UART8_IRQHandler
UART9_IRQHandler
TRNG_IRQHandler
UART6_IRQHandler
UART7_IRQHandler
EADC10_IRQHandler
EADC11_IRQHandler
EADC12_IRQHandler
EADC13_IRQHandler
SPI8_IRQHandler
KS_IRQHandler
GPI_IRQHandler
SPI9_IRQHandler
CANFD00_IRQHandler
CANFD01_IRQHandler
CANFD10_IRQHandler
CANFD11_IRQHandler
EQEI2_IRQHandler
EQEI3_IRQHandler
I2C4_IRQHandler
SPI10_IRQHandler
CANFD20_IRQHandler
CANFD21_IRQHandler
CANFD30_IRQHandler
CANFD31_IRQHandler
EADC20_IRQHandler
EADC21_IRQHandler
EADC22_IRQHandler
EADC23_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

428
bsp/nuvoton/libraries/m460/Device/Nuvoton/m460/Source/GCC/startup_M460.S Normal file
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@ -0,0 +1,428 @@
/****************************************************************************//**
* @file startup_M460.S
* @version V3.00
* @brief CMSIS Cortex-M4 Core Device Startup File for M460
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
// Unlock Register
ldr r0, =0x40000100
ldr r1, =0x59
str r1, [r0]
ldr r1, =0x16
str r1, [r0]
ldr r1, =0x88
str r1, [r0]
#ifndef ENABLE_SPIM_CACHE
ldr r0, =0x40000200 // R0 = Clock Controller Register Base Address
ldr r1, [r0,#0x4] // R1 = 0x40000204 (AHBCLK)
orr r1, r1, #0x4000
str r1, [r0,#0x4] // CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk//
ldr r0, =0x40007000 // R0 = SPIM Register Base Address
ldr r1, [r0,#4] // R1 = SPIM->CTL1
orr r1, r1,#2 // R1 |= SPIM_CTL1_CACHEOFF_Msk
str r1, [r0,#4] // _SPIM_DISABLE_CACHE()
ldr r1, [r0,#4] // R1 = SPIM->CTL1
orr r1, r1, #4 // R1 |= SPIM_CTL1_CCMEN_Msk
str r1, [r0,#4] // _SPIM_ENABLE_CCM()
#endif
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
// Lock
ldr r0, =0x40000100
ldr r1, =0
str r1, [r0]
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the application's entry point.*/
bl entry
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.long _estack /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long BOD_IRQHandler /* 0: BOD */
.long IRC_IRQHandler /* 1: IRC */
.long PWRWU_IRQHandler /* 2: PWRWU */
.long RAMPE_IRQHandler /* 3: RAMPE */
.long CKFAIL_IRQHandler /* 4: CKFAIL */
.long ISP_IRQHandler /* 5: ISP */
.long RTC_IRQHandler /* 6: RTC */
.long TAMPER_IRQHandler /* 7: TAMPER */
.long WDT_IRQHandler /* 8: WDT */
.long WWDT_IRQHandler /* 9: WWDT */
.long EINT0_IRQHandler /* 10: EINT0 */
.long EINT1_IRQHandler /* 11: EINT1 */
.long EINT2_IRQHandler /* 12: EINT2 */
.long EINT3_IRQHandler /* 13: EINT3 */
.long EINT4_IRQHandler /* 14: EINT4 */
.long EINT5_IRQHandler /* 15: EINT5 */
.long GPA_IRQHandler /* 16: GPA */
.long GPB_IRQHandler /* 17: GPB */
.long GPC_IRQHandler /* 18: GPC */
.long GPD_IRQHandler /* 19: GPD */
.long GPE_IRQHandler /* 20: GPE */
.long GPF_IRQHandler /* 21: GPF */
.long QSPI0_IRQHandler /* 22: QSPI0 */
.long SPI0_IRQHandler /* 23: SPI0 */
.long BRAKE0_IRQHandler /* 24: BRAKE0 */
.long EPWM0P0_IRQHandler /* 25: EPWM0P0 */
.long EPWM0P1_IRQHandler /* 26: EPWM0P1 */
.long EPWM0P2_IRQHandler /* 27: EPWM0P2 */
.long BRAKE1_IRQHandler /* 28: BRAKE1 */
.long EPWM1P0_IRQHandler /* 29: EPWM1P0 */
.long EPWM1P1_IRQHandler /* 30: EPWM1P1 */
.long EPWM1P2_IRQHandler /* 31: EPWM1P2 */
.long TMR0_IRQHandler /* 32: TIMER0 */
.long TMR1_IRQHandler /* 33: TIMER1 */
.long TMR2_IRQHandler /* 34: TIMER2 */
.long TMR3_IRQHandler /* 35: TIMER3 */
.long UART0_IRQHandler /* 36: UART0 */
.long UART1_IRQHandler /* 37: UART1 */
.long I2C0_IRQHandler /* 38: I2C0 */
.long I2C1_IRQHandler /* 39: I2C1 */
.long PDMA0_IRQHandler /* 40: PDMA0 */
.long DAC_IRQHandler /* 41: DAC */
.long EADC00_IRQHandler /* 42: EADC00 */
.long EADC01_IRQHandler /* 43: EADC01 */
.long ACMP01_IRQHandler /* 44: ACMP01 */
.long ACMP23_IRQHandler /* 45: ACMP23 */
.long EADC02_IRQHandler /* 46: EADC02 */
.long EADC03_IRQHandler /* 47: EADC03 */
.long UART2_IRQHandler /* 48: UART2 */
.long UART3_IRQHandler /* 49: UART3 */
.long QSPI1_IRQHandler /* 50: QSPI1 */
.long SPI1_IRQHandler /* 51: SPI1 */
.long SPI2_IRQHandler /* 52: SPI2 */
.long USBD_IRQHandler /* 53: USBD */
.long OHCI_IRQHandler /* 54: OHCI */
.long USBOTG_IRQHandler /* 55: OTG */
.long BMC_Handler /* 56: BMC */
.long SPI5_IRQHandler /* 57: SPI5 */
.long SC0_IRQHandler /* 58: SC0 */
.long SC1_IRQHandler /* 59: SC1 */
.long SC2_IRQHandler /* 60: SC2 */
.long GPJ_IRQHandler /* 61: GPJ */
.long SPI3_IRQHandler /* 62: SPI3 */
.long SPI4_IRQHandler /* 63: SPI4 */
.long SDH0_IRQHandler /* 64: SDH0 */
.long USBD20_IRQHandler /* 65: HSUSBD */
.long EMAC0_IRQHandler /* 66: EMAC0 */
.long 0 /* 67: Reserved */
.long I2S0_IRQHandler /* 68: I2S0 */
.long I2S1_IRQHandler /* 69: I2S1 */
.long SPI6_IRQHandler /* 70: SPI6 */
.long CRPT_IRQHandler /* 71: CRPT */
.long GPG_IRQHandler /* 72: GPG */
.long EINT6_IRQHandler /* 73: EINT6 */
.long UART4_IRQHandler /* 74: UART4 */
.long UART5_IRQHandler /* 75: UART5 */
.long USCI0_IRQHandler /* 76: USCI0 */
.long SPI7_IRQHandler /* 77: SPI7 */
.long BPWM0_IRQHandler /* 78: BPWM0 */
.long BPWM1_IRQHandler /* 79: BPWM1 */
.long SPIM_IRQHandler /* 80: SPIM */
.long CCAP_IRQHandler /* 81: CCAP */
.long I2C2_IRQHandler /* 82: I2C2 */
.long I2C3_IRQHandler /* 83: I2C3 */
.long EQEI0_IRQHandler /* 84: EQEI0 */
.long EQEI1_IRQHandler /* 85: EQEI1 */
.long ECAP0_IRQHandler /* 86: ECAP0 */
.long ECAP1_IRQHandler /* 87: ECAP1 */
.long GPH_IRQHandler /* 88: GPH */
.long EINT7_IRQHandler /* 89: EINT7 */
.long SDH1_IRQHandler /* 90: SDH1 */
.long PSIO_IRQHandler /* 91: PSIO */
.long EHCI_IRQHandler /* 92: EHCI */
.long USBOTG20_IRQHandler /* 93: HSOTG */
.long ECAP2_IRQHandler /* 94: ECAP2 */
.long ECAP3_IRQHandler /* 95: ECAP3 */
.long KPI_IRQHandler /* 96: KPI */
.long HBI_IRQHandler /* 97: HBI */
.long PDMA1_IRQHandler /* 98: PDMA1 */
.long UART8_IRQHandler /* 99: UART8 */
.long UART9_IRQHandler /* 100: UART9 */
.long TRNG_IRQHandler /* 101: TRNG */
.long UART6_IRQHandler /* 102: UART6 */
.long UART7_IRQHandler /* 103: UART7 */
.long EADC10_IRQHandler /* 104: EADC10 */
.long EADC11_IRQHandler /* 105: EADC11 */
.long EADC12_IRQHandler /* 106: EADC12 */
.long EADC13_IRQHandler /* 107: EADC13 */
.long SPI8_IRQHandler /* 108: SPI8 */
.long KS_IRQHandler /* 109: KS */
.long GPI_IRQHandler /* 110: GPI */
.long SPI9_IRQHandler /* 111: SPI9 */
.long CANFD00_IRQHandler /* 112: CANFD00 */
.long CANFD01_IRQHandler /* 113: CANFD01 */
.long CANFD10_IRQHandler /* 114: CANFD10 */
.long CANFD10_IRQHandler /* 115: CANFD10 */
.long EQEI2_IRQHandler /* 116: EQEI2 */
.long EQEI3_IRQHandler /* 117: EQEI3 */
.long I2C4_IRQHandler /* 118: I2C4 */
.long SPI10_IRQHandler /* 119: SPI10 */
.long CANFD20_IRQHandler /* 120: CANFD20 */
.long CANFD21_IRQHandler /* 121: CANFD21 */
.long CANFD30_IRQHandler /* 122: CANFD30 */
.long CANFD30_IRQHandler /* 123: CANFD30 */
.long EADC20_IRQHandler /* 124: EADC20 */
.long EADC21_IRQHandler /* 125: EADC21 */
.long EADC22_IRQHandler /* 126: EADC22 */
.long EADC23_IRQHandler /* 127: EADC23 */
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler BOD_IRQHandler
def_irq_handler IRC_IRQHandler
def_irq_handler PWRWU_IRQHandler
def_irq_handler RAMPE_IRQHandler
def_irq_handler CKFAIL_IRQHandler
def_irq_handler ISP_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler TAMPER_IRQHandler
def_irq_handler WDT_IRQHandler
def_irq_handler WWDT_IRQHandler
def_irq_handler EINT0_IRQHandler
def_irq_handler EINT1_IRQHandler
def_irq_handler EINT2_IRQHandler
def_irq_handler EINT3_IRQHandler
def_irq_handler EINT4_IRQHandler
def_irq_handler EINT5_IRQHandler
def_irq_handler GPA_IRQHandler
def_irq_handler GPB_IRQHandler
def_irq_handler GPC_IRQHandler
def_irq_handler GPD_IRQHandler
def_irq_handler GPE_IRQHandler
def_irq_handler GPF_IRQHandler
def_irq_handler QSPI0_IRQHandler
def_irq_handler SPI0_IRQHandler
def_irq_handler BRAKE0_IRQHandler
def_irq_handler EPWM0P0_IRQHandler
def_irq_handler EPWM0P1_IRQHandler
def_irq_handler EPWM0P2_IRQHandler
def_irq_handler BRAKE1_IRQHandler
def_irq_handler EPWM1P0_IRQHandler
def_irq_handler EPWM1P1_IRQHandler
def_irq_handler EPWM1P2_IRQHandler
def_irq_handler TMR0_IRQHandler
def_irq_handler TMR1_IRQHandler
def_irq_handler TMR2_IRQHandler
def_irq_handler TMR3_IRQHandler
def_irq_handler UART0_IRQHandler
def_irq_handler UART1_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler PDMA0_IRQHandler
def_irq_handler DAC_IRQHandler
def_irq_handler EADC00_IRQHandler
def_irq_handler EADC01_IRQHandler
def_irq_handler ACMP01_IRQHandler
def_irq_handler ACMP23_IRQHandler
def_irq_handler EADC02_IRQHandler
def_irq_handler EADC03_IRQHandler
def_irq_handler UART2_IRQHandler
def_irq_handler UART3_IRQHandler
def_irq_handler QSPI1_IRQHandler
def_irq_handler SPI1_IRQHandler
def_irq_handler SPI2_IRQHandler
def_irq_handler USBD_IRQHandler
def_irq_handler OHCI_IRQHandler
def_irq_handler USBOTG_IRQHandler
def_irq_handler BMC_Handler
def_irq_handler SPI5_IRQHandler
def_irq_handler SC0_IRQHandler
def_irq_handler SC1_IRQHandler
def_irq_handler SC2_IRQHandler
def_irq_handler GPJ_IRQHandler
def_irq_handler SPI3_IRQHandler
def_irq_handler SPI4_IRQHandler
def_irq_handler SDH0_IRQHandler
def_irq_handler USBD20_IRQHandler
def_irq_handler EMAC0_IRQHandler
def_irq_handler I2S0_IRQHandler
def_irq_handler I2S1_IRQHandler
def_irq_handler SPI6_IRQHandler
def_irq_handler CRPT_IRQHandler
def_irq_handler GPG_IRQHandler
def_irq_handler EINT6_IRQHandler
def_irq_handler UART4_IRQHandler
def_irq_handler UART5_IRQHandler
def_irq_handler USCI0_IRQHandler
def_irq_handler SPI7_IRQHandler
def_irq_handler BPWM0_IRQHandler
def_irq_handler BPWM1_IRQHandler
def_irq_handler SPIM_IRQHandler
def_irq_handler CCAP_IRQHandler
def_irq_handler I2C2_IRQHandler
def_irq_handler I2C3_IRQHandler
def_irq_handler EQEI0_IRQHandler
def_irq_handler EQEI1_IRQHandler
def_irq_handler ECAP0_IRQHandler
def_irq_handler ECAP1_IRQHandler
def_irq_handler GPH_IRQHandler
def_irq_handler EINT7_IRQHandler
def_irq_handler SDH1_IRQHandler
def_irq_handler PSIO_IRQHandler
def_irq_handler EHCI_IRQHandler
def_irq_handler USBOTG20_IRQHandler
def_irq_handler ECAP2_IRQHandler
def_irq_handler ECAP3_IRQHandler
def_irq_handler KPI_IRQHandler
def_irq_handler HBI_IRQHandler
def_irq_handler PDMA1_IRQHandler
def_irq_handler UART8_IRQHandler
def_irq_handler UART9_IRQHandler
def_irq_handler TRNG_IRQHandler
def_irq_handler UART6_IRQHandler
def_irq_handler UART7_IRQHandler
def_irq_handler EADC10_IRQHandler
def_irq_handler EADC11_IRQHandler
def_irq_handler EADC12_IRQHandler
def_irq_handler EADC13_IRQHandler
def_irq_handler SPI8_IRQHandler
def_irq_handler KS_IRQHandler
def_irq_handler GPI_IRQHandler
def_irq_handler SPI9_IRQHandler
def_irq_handler CANFD00_IRQHandler
def_irq_handler CANFD01_IRQHandler
def_irq_handler CANFD10_IRQHandler
def_irq_handler CANFD11_IRQHandler
def_irq_handler EQEI2_IRQHandler
def_irq_handler EQEI3_IRQHandler
def_irq_handler I2C4_IRQHandler
def_irq_handler SPI10_IRQHandler
def_irq_handler CANFD20_IRQHandler
def_irq_handler CANFD21_IRQHandler
def_irq_handler CANFD30_IRQHandler
def_irq_handler CANFD31_IRQHandler
def_irq_handler EADC20_IRQHandler
def_irq_handler EADC21_IRQHandler
def_irq_handler EADC22_IRQHandler
def_irq_handler EADC23_IRQHandler
.end

499
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;/******************************************************************************
; * @file startup_M460.s
; * @version V3.00
; * @brief CMSIS Cortex-M4 Core Device Startup File for M460
; *
; * @copyright SPDX-License-Identifier: Apache-2.0
; * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
;*****************************************************************************/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN HardFault_Handler
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD BOD_IRQHandler ; 0: Brown Out detection
DCD IRC_IRQHandler ; 1: Internal RC
DCD PWRWU_IRQHandler ; 2: Power down wake up
DCD RAMPE_IRQHandler ; 3: RAM parity error
DCD CKFAIL_IRQHandler ; 4: Clock detection fail
DCD ISP_IRQHandler ; 5: ISP
DCD RTC_IRQHandler ; 6: Real Time Clock
DCD TAMPER_IRQHandler ; 7: Tamper detection
DCD WDT_IRQHandler ; 8: Watchdog timer
DCD WWDT_IRQHandler ; 9: Window watchdog timer
DCD EINT0_IRQHandler ; 10: External Input 0
DCD EINT1_IRQHandler ; 11: External Input 1
DCD EINT2_IRQHandler ; 12: External Input 2
DCD EINT3_IRQHandler ; 13: External Input 3
DCD EINT4_IRQHandler ; 14: External Input 4
DCD EINT5_IRQHandler ; 15: External Input 5
DCD GPA_IRQHandler ; 16: GPIO Port A
DCD GPB_IRQHandler ; 17: GPIO Port B
DCD GPC_IRQHandler ; 18: GPIO Port C
DCD GPD_IRQHandler ; 19: GPIO Port D
DCD GPE_IRQHandler ; 20: GPIO Port E
DCD GPF_IRQHandler ; 21: GPIO Port F
DCD QSPI0_IRQHandler ; 22: QSPI0
DCD SPI0_IRQHandler ; 23: SPI0
DCD BRAKE0_IRQHandler ; 24: EPWM0 brake
DCD EPWM0P0_IRQHandler ; 25: EPWM0 pair 0
DCD EPWM0P1_IRQHandler ; 26: EPWM0 pair 1
DCD EPWM0P2_IRQHandler ; 27: EPWM0 pair 2
DCD BRAKE1_IRQHandler ; 28: EPWM1 brake
DCD EPWM1P0_IRQHandler ; 29: EPWM1 pair 0
DCD EPWM1P1_IRQHandler ; 30: EPWM1 pair 1
DCD EPWM1P2_IRQHandler ; 31: EPWM1 pair 2
DCD TMR0_IRQHandler ; 32: Timer 0
DCD TMR1_IRQHandler ; 33: Timer 1
DCD TMR2_IRQHandler ; 34: Timer 2
DCD TMR3_IRQHandler ; 35: Timer 3
DCD UART0_IRQHandler ; 36: UART0
DCD UART1_IRQHandler ; 37: UART1
DCD I2C0_IRQHandler ; 38: I2C0
DCD I2C1_IRQHandler ; 39: I2C1
DCD PDMA0_IRQHandler ; 40: Peripheral DMA 0
DCD DAC_IRQHandler ; 41: DAC
DCD EADC00_IRQHandler ; 42: EADC0 interrupt source 0
DCD EADC01_IRQHandler ; 43: EADC0 interrupt source 1
DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1
DCD ACMP23_IRQHandler ; 45: ACMP2 and ACMP3
DCD EADC02_IRQHandler ; 46: EADC0 interrupt source 2
DCD EADC03_IRQHandler ; 47: EADC0 interrupt source 3
DCD UART2_IRQHandler ; 48: UART2
DCD UART3_IRQHandler ; 49: UART3
DCD QSPI1_IRQHandler ; 50: QSPI1
DCD SPI1_IRQHandler ; 51: SPI1
DCD SPI2_IRQHandler ; 52: SPI2
DCD USBD_IRQHandler ; 53: USB device
DCD OHCI_IRQHandler ; 54: OHCI
DCD USBOTG_IRQHandler ; 55: USB OTG
DCD BMC_Handler ; 56: BMC
DCD SPI5_IRQHandler ; 57: SPI5
DCD SC0_IRQHandler ; 58: SC0
DCD SC1_IRQHandler ; 59: SC1
DCD SC2_IRQHandler ; 60: SC2
DCD GPJ_IRQHandler ; 61: GPIO Port J
DCD SPI3_IRQHandler ; 62: SPI3
DCD Default_Handler ; 63:
DCD SDH0_IRQHandler ; 64: SDH0
DCD USBD20_IRQHandler ; 65: USBD20
DCD EMAC0_IRQHandler ; 66: EMAC0
DCD Default_Handler ; 67:
DCD I2S0_IRQHandler ; 68: I2S0
DCD I2S1_IRQHandler ; 69: I2S1
DCD SPI6_IRQHandler ; 70: SPI6
DCD CRPT_IRQHandler ; 71: CRYPTO
DCD GPG_IRQHandler ; 72: GPIO Port G
DCD EINT6_IRQHandler ; 73: External Input 6
DCD UART4_IRQHandler ; 74: UART4
DCD UART5_IRQHandler ; 75: UART5
DCD USCI0_IRQHandler ; 76: USCI0
DCD SPI7_IRQHandler ; 77: SPI7
DCD BPWM0_IRQHandler ; 78: BPWM0
DCD BPWM1_IRQHandler ; 79: BPWM1
DCD SPIM_IRQHandler ; 80: SPIM
DCD CCAP_IRQHandler ; 81: CCAP
DCD I2C2_IRQHandler ; 82: I2C2
DCD I2C3_IRQHandler ; 83: I2C3
DCD EQEI0_IRQHandler ; 84: QEI0
DCD EQEI1_IRQHandler ; 85: QEI1
DCD ECAP0_IRQHandler ; 86: ECAP0
DCD ECAP1_IRQHandler ; 87: ECAP1
DCD GPH_IRQHandler ; 88: GPIO Port H
DCD EINT7_IRQHandler ; 89: External Input 7
DCD SDH1_IRQHandler ; 90: SDH1
DCD PSIO_IRQHandler ; 91: PSIO
DCD EHCI_IRQHandler ; 92: EHCI
DCD USBOTG20_IRQHandler ; 93: HSOTG
DCD ECAP2_IRQHandler ; 94: ECAP2
DCD ECAP3_IRQHandler ; 95: ECAP3
DCD KPI_IRQHandler ; 96: KPI
DCD HBI_IRQHandler ; 97: HBI
DCD PDMA1_IRQHandler ; 98: Peripheral DMA 1
DCD UART8_IRQHandler ; 99: UART8
DCD UART9_IRQHandler ; 100: UART9
DCD TRNG_IRQHandler ; 101: TRNG
DCD UART6_IRQHandler ; 102: UART6
DCD UART7_IRQHandler ; 103: UART7
DCD EADC10_IRQHandler ; 104: EADC1 interrupt source 0
DCD EADC11_IRQHandler ; 105: EADC1 interrupt source 1
DCD EADC12_IRQHandler ; 106: EADC1 interrupt source 2
DCD EADC13_IRQHandler ; 107: EADC1 interrupt source 3
DCD SPI8_IRQHandler ; 108: SPI8
DCD KS_IRQHandler ; 109: Key Store
DCD GPI_IRQHandler ; 110: GPIO Port I
DCD SPI9_IRQHandler ; 111: SPI9
DCD CANFD00_IRQHandler ; 112: CANFD0 interrupt source 0
DCD CANFD01_IRQHandler ; 113: CANFD0 interrupt source 1
DCD CANFD10_IRQHandler ; 114: CANFD1 interrupt source 0
DCD CANFD11_IRQHandler ; 115: CANFD1 interrupt source 1
DCD EQEI2_IRQHandler ; 116: EQEI2
DCD EQEI3_IRQHandler ; 117: EQEI3
DCD I2C4_IRQHandler ; 118: I2C4
DCD SPI10_IRQHandler ; 119: SPI10
DCD CANFD20_IRQHandler ; 112: CANFD2 interrupt source 0
DCD CANFD21_IRQHandler ; 113: CANFD2 interrupt source 1
DCD CANFD30_IRQHandler ; 114: CANFD3 interrupt source 0
DCD CANFD31_IRQHandler ; 115: CANFD4 interrupt source 1
DCD EADC20_IRQHandler ; 104: EADC2 interrupt source 0
DCD EADC21_IRQHandler ; 105: EADC2 interrupt source 1
DCD EADC22_IRQHandler ; 106: EADC2 interrupt source 2
DCD EADC23_IRQHandler ; 107: EADC2 interrupt source 3
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK BOD_IRQHandler
PUBWEAK IRC_IRQHandler
PUBWEAK PWRWU_IRQHandler
PUBWEAK RAMPE_IRQHandler
PUBWEAK CKFAIL_IRQHandler
PUBWEAK ISP_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK TAMPER_IRQHandler
PUBWEAK WDT_IRQHandler
PUBWEAK WWDT_IRQHandler
PUBWEAK EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
PUBWEAK EINT4_IRQHandler
PUBWEAK EINT5_IRQHandler
PUBWEAK GPA_IRQHandler
PUBWEAK GPB_IRQHandler
PUBWEAK GPC_IRQHandler
PUBWEAK GPD_IRQHandler
PUBWEAK GPE_IRQHandler
PUBWEAK GPF_IRQHandler
PUBWEAK QSPI0_IRQHandler
PUBWEAK SPI0_IRQHandler
PUBWEAK BRAKE0_IRQHandler
PUBWEAK EPWM0P0_IRQHandler
PUBWEAK EPWM0P1_IRQHandler
PUBWEAK EPWM0P2_IRQHandler
PUBWEAK BRAKE1_IRQHandler
PUBWEAK EPWM1P0_IRQHandler
PUBWEAK EPWM1P1_IRQHandler
PUBWEAK EPWM1P2_IRQHandler
PUBWEAK TMR0_IRQHandler
PUBWEAK TMR1_IRQHandler
PUBWEAK TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
PUBWEAK UART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK PDMA0_IRQHandler
PUBWEAK DAC_IRQHandler
PUBWEAK EADC00_IRQHandler
PUBWEAK EADC01_IRQHandler
PUBWEAK ACMP01_IRQHandler
PUBWEAK ACMP23_IRQHandler
PUBWEAK EADC02_IRQHandler
PUBWEAK EADC03_IRQHandler
PUBWEAK UART2_IRQHandler
PUBWEAK UART3_IRQHandler
PUBWEAK QSPI1_IRQHandler
PUBWEAK SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
PUBWEAK USBD_IRQHandler
PUBWEAK OHCI_IRQHandler
PUBWEAK USBOTG_IRQHandler
PUBWEAK BMC_Handler
PUBWEAK SPI5_IRQHandler
PUBWEAK SC0_IRQHandler
PUBWEAK SC1_IRQHandler
PUBWEAK SC2_IRQHandler
PUBWEAK GPJ_IRQHandler
PUBWEAK SPI3_IRQHandler
PUBWEAK SPI4_IRQHandler
PUBWEAK SDH0_IRQHandler
PUBWEAK USBD20_IRQHandler
PUBWEAK EMAC0_IRQHandler
PUBWEAK I2S0_IRQHandler
PUBWEAK I2S1_IRQHandler
PUBWEAK SPI6_IRQHandler
PUBWEAK CRPT_IRQHandler
PUBWEAK GPG_IRQHandler
PUBWEAK EINT6_IRQHandler
PUBWEAK UART4_IRQHandler
PUBWEAK UART5_IRQHandler
PUBWEAK USCI0_IRQHandler
PUBWEAK SPI7_IRQHandler
PUBWEAK BPWM0_IRQHandler
PUBWEAK BPWM1_IRQHandler
PUBWEAK SPIM_IRQHandler
PUBWEAK CCAP_IRQHandler
PUBWEAK I2C2_IRQHandler
PUBWEAK I2C3_IRQHandler
PUBWEAK EQEI0_IRQHandler
PUBWEAK EQEI1_IRQHandler
PUBWEAK ECAP0_IRQHandler
PUBWEAK ECAP1_IRQHandler
PUBWEAK GPH_IRQHandler
PUBWEAK EINT7_IRQHandler
PUBWEAK SDH1_IRQHandler
PUBWEAK PSIO_IRQHandler
PUBWEAK EHCI_IRQHandler
PUBWEAK USBOTG20_IRQHandler
PUBWEAK ECAP2_IRQHandler
PUBWEAK ECAP3_IRQHandler
PUBWEAK KPI_IRQHandler
PUBWEAK HBI_IRQHandler
PUBWEAK PDMA1_IRQHandler
PUBWEAK UART8_IRQHandler
PUBWEAK UART9_IRQHandler
PUBWEAK TRNG_IRQHandler
PUBWEAK UART6_IRQHandler
PUBWEAK UART7_IRQHandler
PUBWEAK EADC10_IRQHandler
PUBWEAK EADC11_IRQHandler
PUBWEAK EADC12_IRQHandler
PUBWEAK EADC13_IRQHandler
PUBWEAK SPI8_IRQHandler
PUBWEAK GPI_IRQHandler
PUBWEAK SPI9_IRQHandler
PUBWEAK CANFD00_IRQHandler
PUBWEAK CANFD01_IRQHandler
PUBWEAK CANFD10_IRQHandler
PUBWEAK CANFD11_IRQHandler
PUBWEAK EQEI2_IRQHandler
PUBWEAK EQEI3_IRQHandler
PUBWEAK I2C4_IRQHandler
PUBWEAK SPI10_IRQHandler
PUBWEAK CANFD20_IRQHandler
PUBWEAK CANFD21_IRQHandler
PUBWEAK CANFD30_IRQHandler
PUBWEAK CANFD31_IRQHandler
PUBWEAK EADC20_IRQHandler
PUBWEAK EADC21_IRQHandler
PUBWEAK EADC22_IRQHandler
PUBWEAK EADC23_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
BOD_IRQHandler
IRC_IRQHandler
PWRWU_IRQHandler
RAMPE_IRQHandler
CKFAIL_IRQHandler
ISP_IRQHandler
RTC_IRQHandler
TAMPER_IRQHandler
WDT_IRQHandler
WWDT_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
EINT5_IRQHandler
GPA_IRQHandler
GPB_IRQHandler
GPC_IRQHandler
GPD_IRQHandler
GPE_IRQHandler
GPF_IRQHandler
QSPI0_IRQHandler
SPI0_IRQHandler
BRAKE0_IRQHandler
EPWM0P0_IRQHandler
EPWM0P1_IRQHandler
EPWM0P2_IRQHandler
BRAKE1_IRQHandler
EPWM1P0_IRQHandler
EPWM1P1_IRQHandler
EPWM1P2_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
PDMA0_IRQHandler
DAC_IRQHandler
EADC00_IRQHandler
EADC01_IRQHandler
ACMP01_IRQHandler
ACMP23_IRQHandler
EADC02_IRQHandler
EADC03_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
QSPI1_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USBD_IRQHandler
OHCI_IRQHandler
USBOTG_IRQHandler
BMC_Handler
SPI5_IRQHandler
SC0_IRQHandler
SC1_IRQHandler
SC2_IRQHandler
GPJ_IRQHandler
SPI3_IRQHandler
SPI4_IRQHandler
SDH0_IRQHandler
USBD20_IRQHandler
EMAC0_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPI6_IRQHandler
CRPT_IRQHandler
GPG_IRQHandler
EINT6_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
USCI0_IRQHandler
SPI7_IRQHandler
BPWM0_IRQHandler
BPWM1_IRQHandler
SPIM_IRQHandler
CCAP_IRQHandler
I2C2_IRQHandler
I2C3_IRQHandler
EQEI0_IRQHandler
EQEI1_IRQHandler
ECAP0_IRQHandler
ECAP1_IRQHandler
GPH_IRQHandler
EINT7_IRQHandler
SDH1_IRQHandler
PSIO_IRQHandler
EHCI_IRQHandler
USBOTG20_IRQHandler
ECAP2_IRQHandler
ECAP3_IRQHandler
KPI_IRQHandler
HBI_IRQHandler
PDMA1_IRQHandler
UART8_IRQHandler
UART9_IRQHandler
TRNG_IRQHandler
UART6_IRQHandler
UART7_IRQHandler
EADC10_IRQHandler
EADC11_IRQHandler
EADC12_IRQHandler
EADC13_IRQHandler
SPI8_IRQHandler
KS_IRQHandler
GPI_IRQHandler
SPI9_IRQHandler
CANFD00_IRQHandler
CANFD01_IRQHandler
CANFD10_IRQHandler
CANFD11_IRQHandler
EQEI2_IRQHandler
EQEI3_IRQHandler
I2C4_IRQHandler
SPI10_IRQHandler
CANFD20_IRQHandler
CANFD21_IRQHandler
CANFD30_IRQHandler
CANFD31_IRQHandler
EADC20_IRQHandler
EADC21_IRQHandler
EADC22_IRQHandler
EADC23_IRQHandler
Default_Handler
B Default_Handler
END

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/**************************************************************************//**
* @file system_m460.c
* @version V3.000
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M460
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */
uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, 0UL, 0UL, __HIRC};
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
{
uint32_t u32Freq, u32ClkSrc;
uint32_t u32HclkDiv;
/* Update PLL Clock */
PllClock = CLK_GetPLLClockFreq();
u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
if (u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
{
/* Use PLL clock */
u32Freq = PllClock;
}
else
{
/* Use the clock sources directly */
u32Freq = gau32ClkSrcTbl[u32ClkSrc];
}
u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL;
/* Update System Core Clock */
SystemCoreClock = u32Freq / u32HclkDiv;
//if(SystemCoreClock == 0)
// __BKPT(0);
CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
}
/**
* @brief Initialize the System
*
* @param none
* @return none
*/
void SystemInit(void)
{
/* Add your system initialize code here.
Do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
(3UL << 11 * 2)); /* set CP11 Full Access */
#endif
/* Unlock protected registers */
SYS_UnlockReg();
/* Set HCLK switch to be reset by HRESET reset sources */
outpw(0x40000014, inpw(0x40000014) | BIT7);
/* Set HXT crystal as INV type */
CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
/* Lock protected registers */
SYS_LockReg();
}

25
bsp/nuvoton/libraries/m460/Device/SConscript Normal file
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import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Split("""
Nuvoton/m460/Source/system_m460.c
""")
# add for startup script
if rtconfig.PLATFORM in ['gcc']:
src = src + ['Nuvoton/m460/Source/GCC/startup_M460.S']
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
src = src + ['Nuvoton/m460/Source/ARM/startup_m460.s']
elif rtconfig.PLATFORM in ['iccarm']:
src = src + ['Nuvoton/m460/Source/IAR/startup_M460.s']
path = [cwd + '/Nuvoton/m460/Include',]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

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bsp/nuvoton/libraries/m460/README.md Normal file
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# M460 Series
## Supported drivers
| Peripheral | rt_device_class_type | Device name |
| ------ | ---- | :------: |
| BPWM | RT_Device_Class_Miscellaneous (PWM) | ***bpwm[0-1]*** |
| BPWM (Capture function)| RT_Device_Class_Miscellaneous (Input capture) | ***bpwm[0-1]i[0-5]*** |
| CANFD | RT_Device_Class_CAN | ***canfd[0-3]*** |
| CCAP | RT_Device_Class_Miscellaneous | ***ccap0*** |
| CRC | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** |
| CRYPTO | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** |
| DAC | RT_Device_Class_Miscellaneous (DAC) | ***dac[0-1]*** |
| EADC | RT_Device_Class_Miscellaneous (ADC) | ***eadc[0-1]*** |
| EBI | N/A | ***N/A*** |
| ECAP | RT_Device_Class_Miscellaneous (Input capture) | ***ecap[0-1]i[0-2]*** |
| EMAC | RT_Device_Class_NetIf | ***e0*** |
| EPWM | RT_Device_Class_Miscellaneous (PWM) | ***epwm[0-1]*** |
| EPWM (Capture function) | RT_Device_Class_Miscellaneous (Input capture) | ***epwm[0-1]i[0-5]*** |
| EQEI | RT_Device_Class_Miscellaneous (Pulse encoder) | ***eqei[0-3]*** |
| FMC | FAL | ***N/A*** |
| GPIO | RT_Device_Class_Miscellaneous (Pin) | ***gpio*** |
| GPIO | RT_Device_Class_I2CBUS | ***softi2c0[0-1]*** |
| HSOTG | RT_Device_Class_USBHost/RT_Device_Class_USBDevice | ***N/A*** |
| HSUSBD | RT_Device_Class_USBDevice | ***usbd*** |
| I2C | RT_Device_Class_I2CBUS | ***i2c[0-4]*** |
| I2S | RT_Device_Class_Sound/RT_Device_Class_Pipe | ***sound[0, 1]*** |
| PDMA | N/A | ***N/A*** |
| QSPI | RT_Device_Class_SPIBUS | ***qspi[0-1]*** |
| RTC | RT_Device_Class_RTC | ***rtc*** |
| SC (UART function) | RT_Device_Class_Char | ***scuart[0-2]*** |
| SDH | RT_Device_Class_Block | ***sdh[0-1]*** |
| SDIO | RT_Device_Class_Sdio | ***sdio[0-1]*** |
| SPI | RT_Device_Class_SPIBUS | ***spi[0-10]*** |
| SPI (I2S function) | RT_Device_Class_Sound/RT_Device_Class_Pipe | ***spii2s[0-10]*** |
| TIMER | RT_Device_Class_Timer | ***timer[0-3]*** |
| TIMER (PWM function) | RT_Device_Class_Miscellaneous (PWM) | ***tpwm[0-3]*** |
| TRNG | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** |
| UART | RT_Device_Class_Char | ***uart[0-7]*** |
| USBD | RT_Device_Class_USBDevice | ***usbd*** |
| USBH, HSUSBH | RT_Device_Class_USBHost | ***usbh*** |
| USCI (I2C function) | RT_Device_Class_I2CBUS | ***ui2c[0-1]*** |
| USCI (SPI function) | RT_Device_Class_SPIBUS | ***uspi[0-1]*** |
| USCI (UART function) | RT_Device_Class_Char | ***uuart[0-1]*** |
| WDT | RT_Device_Class_Miscellaneous (Watchdog) | ***wdt*** |
## Resources
* [Download M460 TRM][1]
[1]: https://www.nuvoton.com/resource-download.jsp?tp_GUID=DA05-M460

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# RT-Thread building script for bridge
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

28
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# RT-Thread building script for component
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
libs = []
src = Glob('*src/*.c') + Glob('src/*.cpp')
cpppath = [cwd + '/inc']
libpath = [cwd + '/lib']
if not GetDepend('BSP_USE_STDDRIVER_SOURCE'):
if rtconfig.CROSS_TOOL == 'keil':
if GetOption('target') == 'mdk5' and os.path.isfile('./lib/libstddriver_keil.lib'):
libs += ['libstddriver_keil']
elif GetOption('target') == 'mdk4' and os.path.isfile('./lib/libstddriver_keil4.lib'):
libs += ['libstddriver_keil4']
elif rtconfig.CROSS_TOOL == 'gcc' and os.path.isfile('./lib/libstddriver_gcc.a'):
libs += ['libstddriver_gcc']
elif os.path.isfile('./lib/libstddriver_iar.a'):
libs += ['libstddriver_iar']
if not libs:
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath)
else:
src = []
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath, LIBS = libs, LIBPATH = libpath)
Return('group')

455
bsp/nuvoton/libraries/m460/StdDriver/inc/nu_acmp.h Normal file
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@ -0,0 +1,455 @@
/**************************************************************************//**
* @file ACMP.h
* @version V1.00
* @brief M480 Series ACMP Driver Header File
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __NU_ACMP_H__
#define __NU_ACMP_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup ACMP_Driver ACMP Driver
@{
*/
/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* ACMP_CTL constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ACMP_CTL_FILTSEL_OFF (0UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for filter function disabled. \hideinitializer */
#define ACMP_CTL_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 1 PCLK filter count. \hideinitializer */
#define ACMP_CTL_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 2 PCLK filter count. \hideinitializer */
#define ACMP_CTL_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 4 PCLK filter count. \hideinitializer */
#define ACMP_CTL_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 8 PCLK filter count. \hideinitializer */
#define ACMP_CTL_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 16 PCLK filter count. \hideinitializer */
#define ACMP_CTL_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 32 PCLK filter count. \hideinitializer */
#define ACMP_CTL_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 64 PCLK filter count. \hideinitializer */
#define ACMP_CTL_INTPOL_RF (0UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. \hideinitializer */
#define ACMP_CTL_INTPOL_R (1UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. \hideinitializer */
#define ACMP_CTL_INTPOL_F (2UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. \hideinitializer */
#define ACMP_CTL_POSSEL_P0 (0UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. \hideinitializer */
#define ACMP_CTL_POSSEL_P1 (1UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. \hideinitializer */
#define ACMP_CTL_POSSEL_P2 (2UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. \hideinitializer */
#define ACMP_CTL_POSSEL_P3 (3UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. \hideinitializer */
#define ACMP_CTL_NEGSEL_PIN (0UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. \hideinitializer */
#define ACMP_CTL_NEGSEL_CRV (1UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. \hideinitializer */
#define ACMP_CTL_NEGSEL_VBG (2UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. \hideinitializer */
#define ACMP_CTL_NEGSEL_DAC (3UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. \hideinitializer */
#define ACMP_CTL_HYSTERESIS_30MV (3UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. \hideinitializer */
#define ACMP_CTL_HYSTERESIS_20MV (2UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. \hideinitializer */
#define ACMP_CTL_HYSTERESIS_10MV (1UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. \hideinitializer */
#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for disabling the hysteresis function. \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* ACMP_VREF constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ACMP_VREF_CRV0SSEL_VDDA (0UL << ACMP_VREF_CRV0SSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV0 source voltage \hideinitializer */
#define ACMP_VREF_CRV0SSEL_INTVREF (1UL << ACMP_VREF_CRV0SSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV0 source voltage \hideinitializer */
#define ACMP_VREF_CRV1SSEL_VDDA (0UL << ACMP_VREF_CRV1SSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV1 source voltage \hideinitializer */
#define ACMP_VREF_CRV1SSEL_INTVREF (1UL << ACMP_VREF_CRV1SSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV1 source voltage \hideinitializer */
#define ACMP_VREF_CRV2SSEL_VDDA (0UL << ACMP_VREF_CRV2SSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV2 source voltage \hideinitializer */
#define ACMP_VREF_CRV2SSEL_INTVREF (1UL << ACMP_VREF_CRV2SSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV2 source voltage \hideinitializer */
#define ACMP_VREF_CRV3SSEL_VDDA (0UL << ACMP_VREF_CRV3SSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV3 source voltage \hideinitializer */
#define ACMP_VREF_CRV3SSEL_INTVREF (1UL << ACMP_VREF_CRV3SSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV3 source voltage \hideinitializer */
/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */
/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Define Macros and functions */
/*---------------------------------------------------------------------------------------------------------*/
/**
* @brief This macro is used to enable output inverse function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function.
* \hideinitializer
*/
#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk)
/**
* @brief This macro is used to disable output inverse function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function.
* \hideinitializer
*/
#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk)
/**
* @brief This macro is used to select ACMP negative input source
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @param[in] u32Src is comparator negative input selection. Including:
* - \ref ACMP_CTL_NEGSEL_PIN
* - \ref ACMP_CTL_NEGSEL_CRV
* - \ref ACMP_CTL_NEGSEL_VBG
* - \ref ACMP_CTL_NEGSEL_DAC
* @return None
* @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input.
* \hideinitializer
*/
#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src))
/**
* @brief This macro is used to enable hysteresis function and set hysteresis to 30mV
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* \hideinitializer
*/
#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV)
/**
* @brief This macro is used to disable hysteresis function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear HYSEL bits of ACMP_CTL register to disable hysteresis function.
* \hideinitializer
*/
#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk)
/**
* @brief This macro is used to select hysteresis level
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @param[in] u32HysSel The hysteresis function option. Including:
* - \ref ACMP_CTL_HYSTERESIS_30MV
* - \ref ACMP_CTL_HYSTERESIS_20MV
* - \ref ACMP_CTL_HYSTERESIS_10MV
* - \ref ACMP_CTL_HYSTERESIS_DISABLE
* \hideinitializer
* @return None
*/
#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel))
/**
* @brief This macro is used to enable interrupt
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function.
* If wake-up function is enabled, the wake-up interrupt will be enabled as well.
* \hideinitializer
*/
#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk)
/**
* @brief This macro is used to disable interrupt
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function.
* \hideinitializer
*/
#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk)
/**
* @brief This macro is used to enable ACMP
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator.
* \hideinitializer
*/
#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk)
/**
* @brief This macro is used to disable ACMP
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
* \hideinitializer
*/
#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk)
/**
* @brief This macro is used to get ACMP output value
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return ACMP output value
* @details This macro will return the ACMP output value.
* \hideinitializer
*/
#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0)
/**
* @brief This macro is used to get ACMP interrupt flag
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return ACMP interrupt occurred (1) or not (0)
* @details This macro will return the ACMP interrupt flag.
* \hideinitializer
*/
#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0)
/**
* @brief This macro is used to clear ACMP interrupt flag
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag.
* \hideinitializer
*/
#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))
/**
* @brief This macro is used to clear ACMP wake-up interrupt flag
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag.
* \hideinitializer
*/
#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum))))
/**
* @brief This macro is used to enable ACMP wake-up function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function.
* \hideinitializer
*/
#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk)
/**
* @brief This macro is used to disable ACMP wake-up function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function.
* \hideinitializer
*/
#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk)
/**
* @brief This macro is used to select ACMP positive input pin
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @param[in] u32Pin Comparator positive pin selection. Including:
* - \ref ACMP_CTL_POSSEL_P0
* - \ref ACMP_CTL_POSSEL_P1
* - \ref ACMP_CTL_POSSEL_P2
* - \ref ACMP_CTL_POSSEL_P3
* @return None
* @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin.
* \hideinitializer
*/
#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
/**
* @brief This macro is used to enable ACMP filter function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function.
* \hideinitializer
*/
#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk)
/**
* @brief This macro is used to disable ACMP filter function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function.
* \hideinitializer
*/
#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk)
/**
* @brief This macro is used to set ACMP filter function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @param[in] u32Cnt is comparator filter count setting.
* - \ref ACMP_CTL_FILTSEL_OFF
* - \ref ACMP_CTL_FILTSEL_1PCLK
* - \ref ACMP_CTL_FILTSEL_2PCLK
* - \ref ACMP_CTL_FILTSEL_4PCLK
* - \ref ACMP_CTL_FILTSEL_8PCLK
* - \ref ACMP_CTL_FILTSEL_16PCLK
* - \ref ACMP_CTL_FILTSEL_32PCLK
* - \ref ACMP_CTL_FILTSEL_64PCLK
* @return None
* @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]).
* \hideinitializer
*/
#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))
/**
* @brief This macro is used to select comparator reference voltage
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32Level The comparator reference voltage setting.
* The formula is:
* comparator reference voltage = CRV source voltage x (1/6 + u32Level/24)
* The range of u32Level is 0 ~ 15.
* @return None
* @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]).
* \hideinitializer
*/
#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRV0SEL_Msk) | ((u32Level)<<ACMP_VREF_CRV0SEL_Pos))
#define ACMP_CRV0_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRV0SEL_Msk) | ((u32Level)<<ACMP_VREF_CRV0SEL_Pos))
#define ACMP_CRV1_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRV1SEL_Msk) | ((u32Level)<<ACMP_VREF_CRV1SEL_Pos))
/**
* @brief This macro is used to enable comparator reference voltage
* @param[in] acmp The pointer of the specified ACMP module
* @return None
* @details CRV must be enabled before using it.
* \hideinitializer
*/
#define ACMP_ENABLE_CRV0(acmp) ((acmp)->VREF |= ACMP_VREF_CRV0EN_Msk)
#define ACMP_ENABLE_CRV1(acmp) ((acmp)->VREF |= ACMP_VREF_CRV1EN_Msk)
/**
* @brief This macro is used to disable comparator reference voltage
* @param[in] acmp The pointer of the specified ACMP module
* @return None
* @details Disable CRV.
* \hideinitializer
*/
#define ACMP_DISABLE_CRV0(acmp) ((acmp)->VREF &= ~ACMP_VREF_CRV0EN_Msk)
#define ACMP_DISABLE_CRV1(acmp) ((acmp)->VREF &= ~ACMP_VREF_CRV1EN_Msk)
/**
* @brief This macro is used to select the source of CRV
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32Src is the source of CRV. Including:
* - \ref ACMP_VREF_CRV0SSEL_VDDA
* - \ref ACMP_VREF_CRV0SSEL_INTVREF
* - \ref ACMP_VREF_CRV1SSEL_VDDA
* - \ref ACMP_VREF_CRV1SSEL_INTVREF
* - \ref ACMP_VREF_CRV2SSEL_VDDA
* - \ref ACMP_VREF_CRV2SSEL_INTVREF
* - \ref ACMP_VREF_CRV3SSEL_VDDA
* - \ref ACMP_VREF_CRV3SSEL_INTVREF
* @return None
* @details The source of CRV can be VDDA or internal reference voltage. The internal reference voltage level is determined by SYS_VREFCTL register.
* \hideinitializer
*/
#define ACMP_SELECT_CRV_SRC(acmp, u32Src) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRV0SSEL_Msk) | (u32Src))
#define ACMP_SELECT_CRV0_SRC(acmp, u32Src) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRV0SSEL_Msk) | (u32Src))
#define ACMP_SELECT_CRV1_SRC(acmp, u32Src) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRV1SSEL_Msk) | (u32Src))
#define ACMP_SELECT_CRV2_SRC(acmp, u32Src) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRV0SSEL_Msk) | (u32Src))
#define ACMP_SELECT_CRV3_SRC(acmp, u32Src) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRV1SSEL_Msk) | (u32Src))
/**
* @brief This macro is used to select ACMP interrupt condition
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @param[in] u32Cond Comparator interrupt condition selection. Including:
* - \ref ACMP_CTL_INTPOL_RF
* - \ref ACMP_CTL_INTPOL_R
* - \ref ACMP_CTL_INTPOL_F
* @return None
* @details The ACMP output interrupt condition can be rising edge, falling edge or any edge.
* \hideinitializer
*/
#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond))
/**
* @brief This macro is used to enable ACMP window latch mode
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode.
* When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch
* block; when ACMP0/1_WLAT pin is at low level, the output of window latch block,
* WLATOUT, is frozen.
* \hideinitializer
*/
#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk)
/**
* @brief This macro is used to disable ACMP window latch mode
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode.
* \hideinitializer
*/
#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk)
/**
* @brief This macro is used to enable ACMP window compare mode
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode.
* When window compare mode is enabled, user can connect the specific analog voltage
* source to either the positive inputs of both comparators or the negative inputs of
* both comparators. The upper bound and lower bound of the designated range are
* determined by the voltages applied to the other inputs of both comparators. If the
* output of a comparator is low and the other comparator outputs high, which means two
* comparators implies the upper and lower bound. User can directly monitor a specific
* analog voltage source via ACMPWO (ACMP_STATUS[16]).
* \hideinitializer
*/
#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk)
/**
* @brief This macro is used to disable ACMP window compare mode
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode.
* \hideinitializer
*/
#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk)
/* Function prototype declaration */
void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel);
void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum);
/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group ACMP_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_ACMP_H__ */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

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bsp/nuvoton/libraries/m460/StdDriver/inc/nu_bmc.h Normal file
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@ -0,0 +1,228 @@
/**************************************************************************//**
* @file nu_bmc.h
* @version V1.00
* @brief M460 series BMC driver header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_BMC_H__
#define __NU_BMC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup BMC_Driver BMC Driver
@{
*/
/** @addtogroup BMC_EXPORTED_CONSTANTS BMC Exported Constants
@{
*/
#define BMC_BITWIDTH_1 (0UL) /*!< The bit time period of logic 0 is same as logic 1 \hideinitializer */
#define BMC_BITWIDTH_15 (BMC_CTL_BWADJ_Msk) /*!< The bit time period of logic 0 is 1.5 times logic 1 \hideinitializer */
#define BMC_PREAMBLE_64 (0UL) /*!< BMC preamble is 64 bits \hideinitializer */
#define BMC_PREAMBLE_32 (BMC_CTL_PREAM32_Msk) /*!< BMC preamble is 32 bits \hideinitializer */
#define BMC_DUM_LVL_LOW (0UL) /*!< BMC dummy level is low \hideinitializer */
#define BMC_DUM_LVL_HIGH (BMC_CTL_DUMLVL_Msk) /*!< BMC dummy level is high \hideinitializer */
#define BMC_GROUP_0 (0UL) /*!< BMC group 0 mask \hideinitializer */
#define BMC_GROUP_1 (4UL) /*!< BMC group 1 mask \hideinitializer */
#define BMC_GROUP_2 (8UL) /*!< BMC group 2 mask \hideinitializer */
#define BMC_GROUP_3 (12UL) /*!< BMC group 3 mask \hideinitializer */
#define BMC_GROUP_4 (16UL) /*!< BMC group 4 mask \hideinitializer */
#define BMC_GROUP_5 (20UL) /*!< BMC group 5 mask \hideinitializer */
#define BMC_GROUP_6 (24UL) /*!< BMC group 6 mask \hideinitializer */
#define BMC_GROUP_7 (28UL) /*!< BMC group 7 mask \hideinitializer */
#define BMC_CHANNEL_NUM (32UL) /*!< BMC total channel number \hideinitializer */
#define BMC_FTXD_INT_MASK (0x1UL) /*!< Frame transmit done interrupt mask \hideinitializer */
#define BMC_TXUND_INT_MASK (0x2UL) /*!< Transmit data under run interrupt mask \hideinitializer */
#define BMC_G0TXUND_MASK (0x01UL) /*!< BMC group 0 transmit data under run mask \hideinitializer */
#define BMC_G1TXUND_MASK (0x02UL) /*!< BMC group 1 transmit data under run mask \hideinitializer */
#define BMC_G2TXUND_MASK (0x04UL) /*!< BMC group 2 transmit data under run mask \hideinitializer */
#define BMC_G3TXUND_MASK (0x08UL) /*!< BMC group 3 transmit data under run mask \hideinitializer */
#define BMC_G4TXUND_MASK (0x10UL) /*!< BMC group 4 transmit data under run mask \hideinitializer */
#define BMC_G5TXUND_MASK (0x20UL) /*!< BMC group 5 transmit data under run mask \hideinitializer */
#define BMC_G6TXUND_MASK (0x40UL) /*!< BMC group 6 transmit data under run mask \hideinitializer */
#define BMC_G7TXUND_MASK (0x80UL) /*!< BMC group 7 transmit data under run mask \hideinitializer */
/*@}*/ /* end of group BMC_EXPORTED_CONSTANTS */
/** @addtogroup BMC_EXPORTED_FUNCTIONS BMC Exported Functions
@{
*/
/**
* @brief Enable BMC controller
* @return None
* @details This macro is used to enable Biphase Mask Coding function.
* \hideinitializer
*/
#define BMC_ENABLE() (BMC->CTL |= BMC_CTL_BMCEN_Msk)
/**
* @brief Disable BMC controller
* @return None
* @details This macro is used to disable Biphase Mask Coding function.
* \hideinitializer
*/
#define BMC_DISABLE() (BMC->CTL &= ~BMC_CTL_BMCEN_Msk)
/**
* @brief Set the bit width adjustment
* @param[in] u32BitAdj BMC bit time period adjustment selection, valid values are:
* - \ref BMC_BITWIDTH_1
* - \ref BMC_BITWIDTH_15
* @return None
* @details This macro is used to set bit width adjustment.
* \hideinitializer
*/
#define BMC_BITWIDTH_ADJUST(u32BitAdj) (BMC->CTL = (BMC->CTL & ~BMC_CTL_BWADJ_Msk) | (u32BitAdj))
/**
* @brief Set the bit number of preamble
* @param[in] u32PreamBit BMC preamble bit number selection, valid values are:
* - \ref BMC_PREAMBLE_64
* - \ref BMC_PREAMBLE_32
* @return None
* @details This macro is used to set the bit number of preamble.
* \hideinitializer
*/
#define BMC_PREAMBLE_BIT(u32PreamBit) (BMC->CTL = (BMC->CTL & ~BMC_CTL_PREAM32_Msk) | (u32PreamBit))
/**
* @brief Set the dummy bit level
* @param[in] u32DumLvl BMC dummy bit level selection, valid values are:
* - \ref BMC_DUM_LVL_LOW
* - \ref BMC_DUM_LVL_HIGH
* @return None
* @details This macro is used to set dummy bit level.
* \hideinitializer
*/
#define BMC_DUMMY_LEVEL(u32DumLvl) (BMC->CTL = (BMC->CTL & ~BMC_CTL_DUMLVL_Msk) | (u32DumLvl))
/**
* @brief Enable PDMA function
* @return None
* @details This macro is used to enable PDMA function.
* \hideinitializer
*/
#define BMC_ENABLE_DMA() (BMC->CTL |= BMC_CTL_DMAEN_Msk)
/**
* @brief Disable PDMA function
* @return None
* @details This macro is used to disable PDMA function.
* \hideinitializer
*/
#define BMC_DISABLE_DMA() (BMC->CTL &= ~BMC_CTL_DMAEN_Msk)
/**
* @brief Enable BMC group 0 channels
* @return None
* @details This macro is used to enable BMC channel 0~3.
* \hideinitializer
*/
#define BMC_ENABLE_GROUP0() (BMC->CTL |= BMC_CTL_G0CHEN_Msk)
/**
* @brief Enable BMC group 1 channels
* @return None
* @details This macro is used to enable BMC channel 4~7.
* \hideinitializer
*/
#define BMC_ENABLE_GROUP1() (BMC->CTL |= BMC_CTL_G1CHEN_Msk)
/**
* @brief Enable BMC group 2 channels
* @return None
* @details This macro is used to enable BMC channel 8~11.
* \hideinitializer
*/
#define BMC_ENABLE_GROUP2() (BMC->CTL |= BMC_CTL_G2CHEN_Msk)
/**
* @brief Enable BMC group 3 channels
* @return None
* @details This macro is used to enable BMC channel 12~15.
* \hideinitializer
*/
#define BMC_ENABLE_GROUP3() (BMC->CTL |= BMC_CTL_G3CHEN_Msk)
/**
* @brief Enable BMC group 4 channels
* @return None
* @details This macro is used to enable BMC channel 16~19.
* \hideinitializer
*/
#define BMC_ENABLE_GROUP4() (BMC->CTL |= BMC_CTL_G4CHEN_Msk)
/**
* @brief Enable BMC group 5 channels
* @return None
* @details This macro is used to enable BMC channel 20~23.
* \hideinitializer
*/
#define BMC_ENABLE_GROUP5() (BMC->CTL |= BMC_CTL_G5CHEN_Msk)
/**
* @brief Enable BMC group 6 channels
* @return None
* @details This macro is used to enable BMC channel 24~27.
* \hideinitializer
*/
#define BMC_ENABLE_GROUP6() (BMC->CTL |= BMC_CTL_G6CHEN_Msk)
/**
* @brief Enable BMC group 7 channels
* @return None
* @details This macro is used to enable BMC channel 28~31.
* \hideinitializer
*/
#define BMC_ENABLE_GROUP7() (BMC->CTL |= BMC_CTL_G7CHEN_Msk)
/**
* @brief Get channel's FIFO empty flag
* @return Which channel's FIFO is empty
* @details This macro will return which channel's FIFO is empty.
* \hideinitializer
*/
#define BMC_GET_CH_EMPTY_FLAG() (BMC->CHEMPTY)
uint32_t BMC_SetBitClock(uint32_t u32BitClock);
uint32_t BMC_GetBitClock(void);
uint32_t BMC_SetDummyDelayPeriod(uint32_t u32ChGroup, uint32_t u32DumDelay);
void BMC_EnableInt(uint32_t u32Mask);
void BMC_DisableInt(uint32_t u32Mask);
uint32_t BMC_GetIntFlag(uint32_t u32Mask);
void BMC_ClearIntFlag(uint32_t u32Mask);
uint32_t BMC_GetStatus(uint32_t u32Mask);
void BMC_ClearStatus(uint32_t u32Mask);
/*@}*/ /* end of group BMC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group BMC_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_BMC_H__ */

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/**************************************************************************//**
* @file nu_bpwm.h
* @version V1.00
* @brief BPWM driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_BPWM_H__
#define __NU_BPWM_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup BPWM_Driver BPWM Driver
@{
*/
/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants
@{
*/
#define BPWM_CHANNEL_NUM (6UL) /*!< BPWM channel number */
#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask \hideinitializer */
#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask \hideinitializer */
#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask \hideinitializer */
#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask \hideinitializer */
#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask \hideinitializer */
#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Counter Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_UP_COUNTER (0UL) /*!< Up counter type \hideinitializer */
#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type \hideinitializer */
#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Aligned Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) \hideinitializer */
#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Output Level Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing \hideinitializer */
#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low \hideinitializer */
#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high \hideinitializer */
#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Synchronous Start Function Control Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_SSCTL_SSRC_PWM0 (0UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM0 */
#define BPWM_SSCTL_SSRC_PWM1 (1UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM1 */
#define BPWM_SSCTL_SSRC_BPWM0 (2UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM0 */
#define BPWM_SSCTL_SSRC_BPWM1 (3UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM1 */
/*---------------------------------------------------------------------------------------------------------*/
/* Trigger Source Select Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< BPWM trigger ADC while counter of even channel matches zero point \hideinitializer */
#define BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< BPWM trigger ADC while counter of even channel matches period point \hideinitializer */
#define BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< BPWM trigger ADC while counter of even channel matches zero or period point \hideinitializer */
#define BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT (3UL) /*!< BPWM trigger ADC while counter of even channel matches up count to comparator point \hideinitializer */
#define BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT (4UL) /*!< BPWM trigger ADC while counter of even channel matches down count to comparator point \hideinitializer */
#define BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT (8UL) /*!< BPWM trigger ADC while counter of odd channel matches up count to comparator point \hideinitializer */
#define BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT (9UL) /*!< BPWM trigger ADC while counter of odd channel matches down count to comparator point \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Capture Control Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< BPWM capture interrupt if channel has rising transition \hideinitializer */
#define BPWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< BPWM capture interrupt if channel has falling transition \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Duty Interrupt Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (1 << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM duty interrupt triggered if down count match comparator \hideinitializer */
#define BPWM_DUTY_INT_UP_COUNT_MATCH_CMP (1 << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM duty interrupt triggered if up down match comparator \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Load Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_LOAD_MODE_IMMEDIATE (1 << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM immediately load mode \hideinitializer */
#define BPWM_LOAD_MODE_CENTER (1 << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM center load mode \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Clock Source Select Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_CLKSRC_BPWM_CLK (0UL) /*!< BPWM Clock source selects to BPWM0_CLK or BPWM1_CLK \hideinitializer */
#define BPWM_CLKSRC_TIMER0 (1UL) /*!< BPWM Clock source selects to TIMER0 overflow \hideinitializer */
#define BPWM_CLKSRC_TIMER1 (2UL) /*!< BPWM Clock source selects to TIMER1 overflow \hideinitializer */
#define BPWM_CLKSRC_TIMER2 (3UL) /*!< BPWM Clock source selects to TIMER2 overflow \hideinitializer */
#define BPWM_CLKSRC_TIMER3 (4UL) /*!< BPWM Clock source selects to TIMER3 overflow \hideinitializer */
/*@}*/ /* end of group BPWM_EXPORTED_CONSTANTS */
/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions
@{
*/
/**
* @brief Enable timer synchronous start counting function of specified channel(s)
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
* @param[in] u32SyncSrc Synchronous start source selection, valid values are:
* - \ref BPWM_SSCTL_SSRC_PWM0
* - \ref BPWM_SSCTL_SSRC_PWM1
* - \ref BPWM_SSCTL_SSRC_BPWM0
* - \ref BPWM_SSCTL_SSRC_BPWM1
* @return None
* @details This macro is used to enable timer synchronous start counting function of specified channel(s).
* @note All channels share channel 0's setting.
* \hideinitializer
*/
#define BPWM_ENABLE_TIMER_SYNC(bpwm, u32ChannelMask, u32SyncSrc) ((bpwm)->SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk)
/**
* @brief Disable timer synchronous start counting function of specified channel(s)
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
* @return None
* @details This macro is used to disable timer synchronous start counting function of specified channel(s).
* @note All channels share channel 0's setting.
* \hideinitializer
*/
#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk)
/**
* @brief This macro enable BPWM counter synchronous start counting function.
* @param[in] bpwm The pointer of the specified BPWM module
* @return None
* @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time.
* To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC().
* \hideinitializer
*/
#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk)
/**
* @brief This macro enable output inverter of specified channel(s)
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @return None
* \hideinitializer
*/
#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask))
/**
* @brief This macro get captured rising data
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @return None
* \hideinitializer
*/
#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT)
/**
* @brief This macro get captured falling data
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @return None
* \hideinitializer
*/
#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT)
/**
* @brief This macro mask output logic to high or low
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @param[in] u32LevelMask Output logic to high or low
* @return None
* @details This macro is used to mask output logic to high or low of specified channel(s).
* @note If u32ChannelMask parameter is 0, then mask function will be disabled.
* \hideinitializer
*/
#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \
{ \
(bpwm)->MSKEN = (u32ChannelMask); \
(bpwm)->MSK = (u32LevelMask); \
}
/**
* @brief This macro set the prescaler of all channels
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF
* @return None
* \hideinitializer
*/
#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler))
/**
* @brief This macro set the duty of the selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
* @return None
* @note This new setting will take effect on next BPWM period
* \hideinitializer
*/
#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
/**
* @brief This macro get the duty of the selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @return None
* \hideinitializer
*/
#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)])
/**
* @brief This macro set the period of all channels
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
* @return None
* @note This new setting will take effect on next BPWM period
* @note BPWM counter will stop if period length set to 0
* \hideinitializer
*/
#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR))
/**
* @brief This macro get the period of all channels
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @return None
* \hideinitializer
*/
#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD)
/**
* @brief This macro set the BPWM aligned type
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
* @param[in] u32AlignedType BPWM aligned type, valid values are:
* - \ref BPWM_EDGE_ALIGNED
* - \ref BPWM_CENTER_ALIGNED
* @return None
* @note All channels share channel 0's setting.
* \hideinitializer
*/
#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType))
/**
* @brief Clear counter of channel 0
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
* @return None
* @details This macro is used to clear counter of channel 0
* \hideinitializer
*/
#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk))
/**
* @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @param[in] u32ZeroLevel output level at zero point, valid values are:
* - \ref BPWM_OUTPUT_NOTHING
* - \ref BPWM_OUTPUT_LOW
* - \ref BPWM_OUTPUT_HIGH
* - \ref BPWM_OUTPUT_TOGGLE
* @param[in] u32CmpUpLevel output level at compare up point, valid values are:
* - \ref BPWM_OUTPUT_NOTHING
* - \ref BPWM_OUTPUT_LOW
* - \ref BPWM_OUTPUT_HIGH
* - \ref BPWM_OUTPUT_TOGGLE
* @param[in] u32PeriodLevel output level at period(center) point, valid values are:
* - \ref BPWM_OUTPUT_NOTHING
* - \ref BPWM_OUTPUT_LOW
* - \ref BPWM_OUTPUT_HIGH
* - \ref BPWM_OUTPUT_TOGGLE
* @param[in] u32CmpDownLevel output level at compare down point, valid values are:
* - \ref BPWM_OUTPUT_NOTHING
* - \ref BPWM_OUTPUT_LOW
* - \ref BPWM_OUTPUT_HIGH
* - \ref BPWM_OUTPUT_TOGGLE
* @return None
* @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s)
* \hideinitializer
*/
#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
do{ \
uint32_t i; \
for(i = 0UL; i < 6UL; i++) { \
if((u32ChannelMask) & (1UL << i)) { \
(bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \
(bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \
(bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \
(bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \
} \
} \
}while(0)
/*---------------------------------------------------------------------------------------------------------*/
/* Define BPWM functions prototype */
/*---------------------------------------------------------------------------------------------------------*/
uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask);
void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask);
void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask);
void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group BPWM_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_BPWM_H__ */

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/****************************************************************************
* @file nu_canfd.h
* @version V1.00
* @brief CAN FD driver source file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_CANFD_H__
#define __NU_CANFD_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
#include "NuMicro.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CANFD_Driver CAN_FD Driver
@{
*/
/** @addtogroup CANFD_EXPORTED_CONSTANTS CAN_FD Exported Constants
@{
*/
#define CANFD_OP_CAN_MODE 0
#define CANFD_OP_CAN_FD_MODE 1
/* Reserved number of elements in Message RAM - used for calculation of start addresses within RAM Configuration
some element_numbers set to less than max, to stay altogether below 256 words of Message RAM requirement*/
#define CANFD_MAX_11_BIT_FTR_ELEMS 128ul /*!< maximum is 128 11-bit Filter */
#define CANFD_MAX_29_BIT_FTR_ELEMS 64ul /*!< maximum is 64 29-bit Filter */
#define CANFD_MAX_RX_FIFO0_ELEMS 64ul /*!< maximum is 64 Rx FIFO 0 elements */
#define CANFD_MAX_RX_FIFO1_ELEMS 64ul /*!< maximum is 64 Rx FIFO 1 elements */
#define CANFD_MAX_RX_BUF_ELEMS 64ul /*!< maximum is 64 Rx Buffers */
#define CANFD_MAX_TX_BUF_ELEMS 32ul /*!< maximum is 32 Tx Buffers */
#define CANFD_MAX_TX_EVNT_FIFO_ELEMS 32ul /*!< maximum is 32 Tx Event FIFO elements */
/* CAN FD sram size */
#define CANFD_SRAM_SIZE 0x1800ul
#define CANFD_SRAM_OFFSET 0x200ul
/* CAN FD sram address */
#define CANFD_SRAM_BASE_ADDR(psCanfd) ((uint32_t)psCanfd + CANFD_SRAM_OFFSET)
/* CAN FD Mask all interrupt */
#define CANFD_INT_ALL_SIGNALS 0x3FFFFFFFul
/* Maximum size of a CAN FD frame. Must be a valid CAN FD value */
#define CANFD_MAX_MESSAGE_BYTES 64
/* Maximum size of a CAN FD frame. Must be a valid CAN FD value */
#define CANFD_MAX_MESSAGE_WORDS (CANFD_MAX_MESSAGE_BYTES/4)
/* Receive message buffer helper macro */
#define CANFD_RX_BUFFER_STD(id, mbIdx) ((7UL << 27) | ((id & 0x7FF) << 16) | (mbIdx & 0x3F))
/* Receive message buffer extended helper macro - low */
#define CANFD_RX_BUFFER_EXT_LOW(id, mbIdx) ((7UL << 29) | (id & 0x1FFFFFFFUL))
/* Receive message buffer extended helper macro - high */
#define CANFD_RX_BUFFER_EXT_HIGH(id, mbIdx) (mbIdx & 0x3FUL)
/* CAN FD Rx FIFO 0 Mask helper macro. */
#define CANFD_RX_FIFO0_STD_MASK(match, mask) ((2UL << 30) | (1UL << 27) | ((match & 0x7FF) << 16) | (mask & 0x7FF))
/* CAN FD Rx FIFO 0 extended Mask helper macro - low. */
#define CANFD_RX_FIFO0_EXT_MASK_LOW(match) ((1UL << 29) | (match & 0x1FFFFFFF))
/* CAN FD Rx FIFO 0 extended Mask helper macro - high. */
#define CANFD_RX_FIFO0_EXT_MASK_HIGH(mask) ((2UL << 30) | (mask & 0x1FFFFFFF))
/* CAN FD Rx FIFO 1 Mask helper macro. */
#define CANFD_RX_FIFO1_STD_MASK(match, mask) ((2UL << 30) | (2UL << 27) | ((match & 0x7FF) << 16) | (mask & 0x7FF))
/* CANFD Rx FIFO 1 extended Mask helper macro - low. */
#define CANFD_RX_FIFO1_EXT_MASK_LOW(match) ((2UL << 29) | (match & 0x1FFFFFFF))
/* CANFD Rx FIFO 1 extended Mask helper macro - high. */
#define CANFD_RX_FIFO1_EXT_MASK_HIGH(mask) ((2UL << 30) | (mask & 0x1FFFFFFF))
/**
* @brief Get the CAN Communication State Flag
*
* @param[in] canfd The pointer of the specified CANFD module
*
* @retval 0 Synchronizing - node is synchronizing on CANFD communication.
* @retval 1 Idle - node is neither receiver nor transmitter.
* @retval 2 Receiver - node is operating as receiver.
* @retval 3 Transmitter - node is operating as transmitter.
*
* @details This macro gets the CANFD communication state.
* \hideinitializer
*/
#define CANFD_GET_COMMUNICATION_STATE(canfd) (((canfd)->PSR & CANFD_PSR_ACT_Msk) >> CANFD_PSR_ACT_Pos)
/* CAN FD frame data field size. */
typedef enum
{
eCANFD_BYTE8 = 0, /*!< 8 byte data field. */
eCANFD_BYTE12 = 1, /*!< 12 byte data field. */
eCANFD_BYTE16 = 2, /*!< 16 byte data field. */
eCANFD_BYTE20 = 3, /*!< 20 byte data field. */
eCANFD_BYTE24 = 4, /*!< 24 byte data field. */
eCANFD_BYTE32 = 5, /*!< 32 byte data field. */
eCANFD_BYTE48 = 6, /*!< 48 byte data field. */
eCANFD_BYTE64 = 7 /*!< 64 byte data field. */
} E_CANFD_DATA_FIELD_SIZE;
/* CAN FD Tx FIFO/Queue Mode. */
typedef enum
{
eCANFD_QUEUE_MODE = 0, /*!< Tx FIFO operation. */
eCANFD_FIFO_MODE = 1 /*!< Tx Queue operation. */
} E_CANFD_MODE;
/* CAN FD Test & Bus monitor Mode. */
typedef enum
{
eCANFD_NORMAL = 0, /*!< None, Normal mode. */
/*
Support:
(1) to receive data frames
(2) to receive remote frames
(3) to give acknowledge to valid frames
Not support:
(1) data frames sending
(2) remote frames sending
(3) active error frames or overload frames sending
*/
eCANFD_RESTRICTED_OPERATION, /*!< Receive external RX frame and always keep recessive state or send dominate bit on ACK bit on TX pin. */
/*
Support:
(1) to receive valid data frames
(2) to receive valid remote frames
Not support:
(1) transmission start
(2) acknowledge to valid frames
*/
eCANFD_BUS_MONITOR, /*!< Receive external RX frame and always keep recessive state on TX pin. */
/*
Support:
(1) Loopback
(2) Also send out frames
Not support:
(1) to receive external frame
*/
eCANFD_LOOPBACK_EXTERNAL, /*!< Won't receive external RX frame. */
/*
Support:
(1) Loopback
Not support:
(1) to receive external frame
(2) transmission start
*/
eCANFD_LOOPBACK_INTERNAL /*!< Won't receive external RX frame and always keep recessive state on TX pin */
} E_CANFD_TEST_MODE;
/* TX Buffer Configuration Parameters */
typedef struct
{
E_CANFD_DATA_FIELD_SIZE eDataFieldSize; /*!< TX Buffer Data Field Size (8byte .. 64byte) */
E_CANFD_MODE eModeSel; /*!< select: CANFD_QUEUE_MODE/CANFD_FIFO_MODE */
uint32_t u32ElemCnt; /*!< Elements in FIFO/Queue */
uint32_t u32DBufNumber; /*!< Number of dedicated TX buffers */
} CANFD_TX_BUF_CONFIG_T;
/* Nominal Bit Timing Parameters */
typedef struct
{
uint32_t u32BitRate; /*!< Transceiver baud rate in bps */
uint16_t u16TDCOffset; /*!< Transceiver Delay Compensation Offset */
uint16_t u16TDCFltrWin; /*!< Transceiver Delay Compensation Filter Window Length */
uint8_t u8TDC; /*!< Transceiver Delay Compensation (1:Yes, 0:No) */
} CANFD_NBT_CONFIG_T;
/* Data Bit Timing Parameters */
typedef struct
{
uint32_t u32BitRate; /*!< Transceiver baud rate in bps */
uint16_t u16TDCOffset; /*!< Transceiver Delay Compensation Offset */
uint16_t u16TDCFltrWin; /*!< Transceiver Delay Compensation Filter Window Length */
uint8_t u8TDC; /*!< Transceiver Delay Compensation (1:Yes, 0:No) */
} CANFD_DBT_CONFIG_T;
/*! CAN FD protocol timing characteristic configuration structure. */
typedef struct
{
uint8_t u8PreDivider; /*!< Global Clock Division Factor. */
uint16_t u16NominalPrescaler; /*!< Nominal clock prescaler. */
uint8_t u8NominalRJumpwidth; /*!< Nominal Re-sync Jump Width. */
uint8_t u8NominalPhaseSeg1; /*!< Nominal Phase Segment 1. */
uint8_t u8NominalPhaseSeg2; /*!< Nominal Phase Segment 2. */
uint8_t u8NominalPropSeg; /*!< Nominal Propagation Segment. */
uint8_t u8DataPrescaler; /*!< Data clock prescaler. */
uint8_t u8DataRJumpwidth; /*!< Data Re-sync Jump Width. */
uint8_t u8DataPhaseSeg1; /*!< Data Phase Segment 1. */
uint8_t u8DataPhaseSeg2; /*!< Data Phase Segment 2. */
uint8_t u8DataPropSeg; /*!< Data Propagation Segment. */
} CANFD_TIMEING_CONFIG_T;
/* CAN FD module configuration structure. */
typedef struct
{
CANFD_NBT_CONFIG_T sNormBitRate; /*!< Normal bit rate. */
CANFD_DBT_CONFIG_T sDataBitRate; /*!< Data bit rate. */
CANFD_TIMEING_CONFIG_T sConfigBitTing; /*!< Bit timing config*/
uint8_t bFDEn; /*!< 1 == FD Operation enabled. */
uint8_t bBitRateSwitch; /*!< 1 == Bit Rate Switch enabled (only evaluated in HW, if FD operation enabled). */
E_CANFD_TEST_MODE evTestMode; /*!< See E_CANFD_TEST_MODE declaration. */
} CANFD_FD_BT_CONFIG_T;
/* CAN FD Message RAM Partitioning - i.e. Start Addresses (BYTE) */
typedef struct
{
uint32_t u32SIDFC_FLSSA; /*!<Standard ID Filter Configuration */
uint32_t u32XIDFC_FLESA; /*!<Extended ID Filter Configuration */
uint32_t u32RXF0C_F0SA; /*!< RX FIFO 0 Start Address */
uint32_t u32RXF1C_F1SA; /*!< RX FIFO 1 Start Address */
uint32_t u32RXBC_RBSA; /*!< Rx Buffer Configuration */
uint32_t u32TXEFC_EFSA; /*!< Tx Event FIFO Configuration */
uint32_t u32TXBC_TBSA; /*!< Tx Buffer Configuration */
} CANFD_RAM_PART_T;
/*CAN FD element size structure */
typedef struct
{
uint32_t u32SIDFC; /*!< Standard Message ID Filter element size in words */
uint32_t u32XIDFC; /*!< Extended Message ID Filter element size in words */
uint32_t u32RxFifo0; /*!< Rx FIFO0 element size in words */
uint32_t u32RxFifo1; /*!< Rx FIFO1 element size in words */
uint32_t u32RxBuf; /*!< Rx Buffer element size in words */
uint32_t u32TxBuf; /*!< Tx Buffer element size in words */
uint32_t u32TxEventFifo; /*!< Tx Event FIFO element size in words */
} CANFD_ELEM_SIZE_T;
/* CAN FD Message frame structure */
typedef struct
{
CANFD_FD_BT_CONFIG_T sBtConfig; /*!< Bit Timing Configuration */
CANFD_RAM_PART_T sMRamStartAddr; /*!< Absolute Byte Start Addresses for Element Types in Message RAM */
CANFD_ELEM_SIZE_T sElemSize; /*!< Size of Elements in Message RAM (RX Elem. in FIFO0, in FIFO1, TX Buffer) given in words */
CANFD_TX_BUF_CONFIG_T sTxConfig; /*!< TX Buffer Configuration */
uint32_t u32MRamSize; /*!< Size of the Message RAM: number of words */
} CANFD_FD_T;
/* CAN FD Message ID Type */
typedef enum
{
eCANFD_SID = 0, /*!< Standard frame format attribute. */
eCANFD_XID = 1 /*!< Extend frame format attribute. */
} E_CANFD_ID_TYPE;
/* CAN FD Rx Message Type */
typedef enum
{
eCANFD_RX_FIFO_0 = 0,
eCANFD_RX_FIFO_1 = 1,
eCANFD_RX_DBUF = 2
} E_CANFD_RX_BUF_TYPE;
/* CAN FD communication state.*/
typedef enum
{
eCANFD_SYNC = 0,
eCANFD_IDLE = 1,
eCANFD_RECEIVER = 2,
eCANFD_TRANSMITTER = 3
} E_CANFD_COMMUNICATION_STATE;
/* CAN FD Message receive Information: via which RX Buffers, etc. */
typedef struct
{
E_CANFD_RX_BUF_TYPE eRxBuf; /*!< Type of RX Buffer */
uint32_t u32BufIdx; /*!< RX Buffer: buffer index, if RX FIFO: GetIndex */
} CANFD_RX_INFO_T;
/* CAN FD frame type. */
typedef enum
{
eCANFD_DATA_FRM = 0, /*!< Data frame type attribute. */
eCANFD_REMOTE_FRM = 1 /*!< Remote frame type attribute. */
} E_CANFD_FRM_TYPE;
/* CAN FD Message Struct */
typedef struct
{
E_CANFD_ID_TYPE eIdType; /*! Standard ID or Extended ID */
CANFD_RX_INFO_T sRxInfo; /*! Information regarding the reception of the frame */
E_CANFD_FRM_TYPE eFrmType; /*! eCANFD_DATA_FRM/eCANFD_REMOTE_FRM */
uint32_t u32Id; /*! Standard ID (11bits) or Extended ID (29bits) */
uint32_t u32DLC; /*! Data Length */
union
{
uint32_t au32Data[CANFD_MAX_MESSAGE_WORDS]; /*!< Word access to buffer data. */
uint8_t au8Data[CANFD_MAX_MESSAGE_BYTES]; /*!< Byte access to buffer data. */
};
uint8_t u8MsgMarker; /*! Message marker (will be copied to TX Event FIFO element) */
uint8_t bFDFormat; /*! FD Format (1 = FD Format) */
uint8_t bBitRateSwitch; /*! Bit Rate Switch (1 = with Bit Rate Switch) */
uint8_t bErrStaInd; /*! Error State Indicator */
uint8_t bEvntFifoCon; /*! Event FIFO Control (1 = Store TX Event FIFO element after transmission)*/
} CANFD_FD_MSG_T;
/* Transmit and Receive message element structure. */
typedef struct
{
uint32_t u32Id; /*!< Message identifier and associated flags. */
uint32_t u32Config; /*!< Buffer configuration. */
union
{
uint32_t au32Data[CANFD_MAX_MESSAGE_WORDS]; /*!< Word access to buffer data. */
uint8_t au8Data[CANFD_MAX_MESSAGE_BYTES]; /*!< Byte access to buffer data. */
};
} CANFD_BUF_T;
/* Standard ID message filter element structure.*/
typedef struct
{
union
{
struct
{
uint32_t SFID2 : 11; /*!<Standard Filter ID 2. */
uint32_t reserved1 : 5;
uint32_t SFID1 : 11; /*!<Standard Filter ID 1. */
uint32_t SFEC : 3; /*!<Standard Filter Element Configuration */
uint32_t SFT : 2; /*!<Standard Filter Type */
};
struct
{
uint32_t VALUE; /*!< Access to filter as a word. */
};
};
} CANFD_STD_FILTER_T;
/* Extended ID message filter element structure.*/
typedef struct
{
union
{
struct
{
uint32_t EFID1 : 29; /*!< Extended Filter ID 1. */
uint32_t EFEC : 3; /*!< Extended Filter Element Configuration. */
uint32_t EFID2 : 29; /*!< Extended Filter ID 2. */
uint32_t reserved1 : 1;
uint32_t EFT : 2; /*!< Extended Filter Type. */
};
struct
{
uint32_t LOWVALUE; /*!< Access to filter low word. */
uint32_t HIGHVALUE; /*!< Access to filter high word. */
};
};
} CANFD_EXT_FILTER_T;
/* Accept Non-matching Frames (GFC Register) */
typedef enum
{
eCANFD_ACC_NON_MATCH_FRM_RX_FIFO0 = 0x0, /*!< Accept Non-Masking Frames in Rx FIFO 0. */
eCANFD_ACC_NON_MATCH_FRM_RX_FIFO1 = 0x1, /*!< Accept Non-Masking Frames in Rx FIFO 1. */
eCANFD_REJ_NON_MATCH_FRM = 0x3 /*!< Reject Non-Matching Frames. */
} E_CANFD_ACC_NON_MATCH_FRM;
/* Standard ID Filter Element Type */
typedef enum
{
eCANFD_SID_FLTR_TYPE_RANGE = 0x0, /*!< Range filter from SFID1 to SFID2. */
eCANFD_SID_FLTR_TYPE_DUAL = 0x1, /*!< Dual ID filter for SFID1 or SFID2. */
eCANFD_SID_FLTR_TYPE_CLASSIC = 0x2, /*!< Classic filter: SFID1 = filter, SFID2 = mask. */
eCANFD_SID_FLTR_TYPE_DIS = 0x3 /*!< Filter element disabled */
} E_CANFD_SID_FLTR_ELEM_TYPE;
/* Extended ID Filter Element Type */
typedef enum
{
eCANFD_XID_FLTR_TYPE_RANGE = 0x0, /*!< Range filter from EFID1 to EFID2. */
eCANFD_XID_FLTR_TYPE_DUAL = 0x1, /*!< Dual ID filter for EFID1 or EFID2. */
eCANFD_XID_FLTR_TYPE_CLASSIC = 0x2, /*!< Classic filter: EFID1=filter, EFID2=mask */
eCANFD_XID_FLTR_TYPE_RANGE_XIDAM_NOT_APP = 0x3 /*!< XID range filter from EFID1 to EFID2(EFID2 > EFID1), XIDAM not applied */
} E_CANFD_XID_FLTR_ELEM_TYPE;
/* Filter Element Configuration - Can be used for SFEC(Standard Id filter configuration) and EFEC(Extended Id filter configuration) */
typedef enum
{
eCANFD_FLTR_ELEM_DIS = 0x0, /*!< Filter Element Disable */
eCANFD_FLTR_ELEM_STO_FIFO0 = 0x1, /*!< Filter Element Store In Fifo0 */
eCANFD_FLTR_ELEM_STO_FIFO1 = 0x2, /*!< Filter Element Store In Fifo1 */
eCANFD_FLTR_ELEM_REJ_ID = 0x3, /*!< Filter Element RejectId */
eCANFD_FLTR_ELEM_SET_PRI = 0x4, /*!< Filter Element Set Priority */
eCANFD_FLTR_ELEM_SET_PRI_STO_FIFO0 = 0x5, /*!< Filter Element Set Priority And Store In Fifo0 */
eCANFD_FLTR_ELEM_SET_PRI_STO_FIFO1 = 0x6, /*!< Filter Element Set Priority And Store In Fifo1 */
eCANFD_FLTR_ELEM_STO_RX_BUF_OR_DBG_MSG = 0x7 /*!< Filter Element Store In Rx Buf Or Debug Msg */
} E_CANFD_FLTR_CONFIG;
/* TX Event FIFO Element Struct */
typedef struct
{
E_CANFD_ID_TYPE eIdType; /*!< Standard ID or Extended ID */
uint32_t u32Id; /*!< Standard ID (11bits) or Extended ID (29bits) */
uint32_t u32DLC; /*!< Data Length Code used in the frame on the bus */
uint32_t u32TxTs; /*!< Tx Timestamp */
uint32_t u32MsgMarker; /*!< Message marker */
uint8_t bErrStaInd; /*!< Error State Indicator */
uint8_t bRemote; /*!< Remote transmission request */
uint8_t bFDFormat; /*!< FD Format */
uint8_t bBitRateSwitch; /*!< Bit Rate Switch */
} CANFD_TX_EVNT_ELEM_T;
#define CANFD_TIMEOUT SystemCoreClock /*!< CANFD time-out counter (1 second time-out) */
#define CANFD_OK ( 0L) /*!< CANFD operation OK */
#define CANFD_ERR_FAIL (-1L) /*!< CANFD operation failed */
#define CANFD_ERR_TIMEOUT (-2L) /*!< CANFD operation abort due to timeout error */
#define CANFD_READ_REG_TIMEOUT (48UL) /*!< CANFD read register time-out count */
void CANFD_Open(CANFD_T *canfd, CANFD_FD_T *psCanfdStr);
void CANFD_Close(CANFD_T *canfd);
void CANFD_EnableInt(CANFD_T *canfd, uint32_t u32IntLine0, uint32_t u32IntLine1, uint32_t u32TXBTIE, uint32_t u32TXBCIE);
void CANFD_DisableInt(CANFD_T *canfd, uint32_t u32IntLine0, uint32_t u32IntLine1, uint32_t u32TXBTIE, uint32_t u32TXBCIE);
uint32_t CANFD_TransmitTxMsg(CANFD_T *canfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg);
uint32_t CANFD_TransmitDMsg(CANFD_T *canfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg);
void CANFD_SetGFC(CANFD_T *canfd, E_CANFD_ACC_NON_MATCH_FRM eNMStdFrm, E_CANFD_ACC_NON_MATCH_FRM eEMExtFrm, uint32_t u32RejRmtStdFrm, uint32_t u32RejRmtExtFrm);
void CANFD_SetSIDFltr(CANFD_T *canfd, uint32_t u32FltrIdx, uint32_t u32Filter);
void CANFD_SetXIDFltr(CANFD_T *canfd, uint32_t u32FltrIdx, uint32_t u32FilterLow, uint32_t u32FilterHigh);
uint32_t CANFD_ReadRxBufMsg(CANFD_T *canfd, uint8_t u8MbIdx, CANFD_FD_MSG_T *psMsgBuf);
uint32_t CANFD_ReadRxFifoMsg(CANFD_T *canfd, uint8_t u8FifoIdx, CANFD_FD_MSG_T *psMsgBuf);
void CANFD_CopyDBufToMsgBuf(CANFD_BUF_T *psRxBuffer, CANFD_FD_MSG_T *psMsgBuf);
void CANFD_CopyRxFifoToMsgBuf(CANFD_BUF_T *psRxBuf, CANFD_FD_MSG_T *psMsgBuf);
uint32_t CANFD_GetRxFifoWaterLvl(CANFD_T *canfd, uint32_t u32RxFifoNum);
void CANFD_TxBufCancelReq(CANFD_T *canfd, uint32_t u32TxBufIdx);
uint32_t CANFD_IsTxBufCancelFin(CANFD_T *canfd, uint32_t u32TxBufIdx);
uint32_t CANFD_IsTxBufTransmitOccur(CANFD_T *canfd, uint32_t u32TxBufIdx);
uint32_t CANFD_GetTxEvntFifoWaterLvl(CANFD_T *canfd);
void CANFD_CopyTxEvntFifoToUsrBuf(CANFD_T *canfd, uint32_t u32TxEvntNum, CANFD_TX_EVNT_ELEM_T *psTxEvntElem);
void CANFD_GetBusErrCount(CANFD_T *canfd, uint8_t *pu8TxErrBuf, uint8_t *pu8RxErrBuf);
int32_t CANFD_RunToNormal(CANFD_T *canfd, uint8_t u8Enable);
void CANFD_GetDefaultConfig(CANFD_FD_T *psConfig, uint8_t u8OpMode);
void CANFD_ClearStatusFlag(CANFD_T *canfd, uint32_t u32InterruptFlag);
uint32_t CANFD_GetStatusFlag(CANFD_T *canfd, uint32_t u32IntTypeFlag);
uint32_t CANFD_ReadReg(__I uint32_t* pu32RegAddr);
/*@}*/ /* end of group CANFD_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CANFD_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __NU_CANFD_H__ */

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/**************************************************************************//**
* @file nu_ccap.h
* @version V3.00
* @brief M460 Series CCAP Driver Header File
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __NU_CCAP_H__
#define __NU_CCAP_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CCAP_Driver CCAP Driver
@{
*/
/** @addtogroup CCAP_EXPORTED_CONSTANTS CCAP Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* CTL constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CCAP_CTL_CCAPEN (1ul<<CCAP_CTL_CCAPEN_Pos) /*!< CCAP CTL setting for enabling Camera Capture Interface \hideinitializer */
#define CCAP_CTL_PKTEN (1ul<<CCAP_CTL_PKTEN_Pos) /*!< CCAP CTL setting for enabling packet output mode \hideinitializer */
#define CCAP_CTL_PLNEN (1ul<<CCAP_CTL_PLNEN_Pos) /*!< CCAP CTL setting for enabling planar output mode \hideinitializer */
#define CCAP_CTL_SHUTTER (1ul<<CCAP_CTL_SHUTTER_Pos) /*!< CCAP CTL setting for enabling shutter mode \hideinitializer */
#define CCAP_CTL_UPDATE (1ul<<CCAP_CTL_UPDATE_Pos) /*!< CCAP CTL setting for enabling update register at new frame \hideinitializer */
#define CCAP_CTL_RESET (1ul<<CCAP_CTL_VPRST_Pos) /*!< CCAP CTL setting for capture reset \hideinitializer */
#define CCAP_CTL_MY8_MY4 (0ul<<CCAP_CTL_MY8_MY4_Pos) /*!< CCAP CTL setting for 4-bit data I/O interface with Mono \hideinitializer */
#define CCAP_CTL_MY8_MY8 (1ul<<CCAP_CTL_MY8_MY4_Pos) /*!< CCAP CTL setting for 8-bit data I/O interface with Mono \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* PAR constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CCAP_PAR_INFMT_YUV422 (0ul<<CCAP_PAR_INFMT_Pos) /*!< CCAP PAR setting for Sensor Input Data YUV422 Format \hideinitializer */
#define CCAP_PAR_INFMT_RGB565 (1ul<<CCAP_PAR_INFMT_Pos) /*!< CCAP PAR setting for Sensor Input Data RGB565 Format \hideinitializer */
#define CCAP_PAR_SENTYPE_CCIR601 (0ul<<CCAP_PAR_SENTYPE_Pos) /*!< CCAP PAR setting for Sensor Input CCIR601 Type \hideinitializer */
#define CCAP_PAR_SENTYPE_CCIR656 (1ul<<CCAP_PAR_SENTYPE_Pos) /*!< CCAP PAR setting for Sensor Input CCIR656 Type \hideinitializer */
#define CCAP_PAR_INDATORD_YUYV (0x0ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, YUYV \hideinitializer */
#define CCAP_PAR_INDATORD_YVYU (0x1ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, YVYU \hideinitializer */
#define CCAP_PAR_INDATORD_UYVY (0x2ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, UYVY \hideinitializer */
#define CCAP_PAR_INDATORD_VYUY (0x3ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, VYUY \hideinitializer */
#define CCAP_PAR_INDATORD_RGGB (0x0ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, 0byte: R[0:4] G[5:8], 1byte G[0:2] R[3:8] \hideinitializer */
#define CCAP_PAR_INDATORD_BGGR (0x1ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, 0byte: b[0:4] G[5:8], 1byte G[0:2] R[3:8] \hideinitializer */
#define CCAP_PAR_INDATORD_GBRG (0x2ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, 0byte: G[0:3] G[4:8], 1byte G[0:4] G[5:8] \hideinitializer */
#define CCAP_PAR_INDATORD_GRBG (0x3ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, 0byte: G[0:3] G[4:8], 1byte G[0:4] G[5:8] \hideinitializer */
#define CCAP_PAR_PLNFMT_YUV422 (0x0ul<<CCAP_PAR_PLNFMT_Pos) /*!< CCAP PAR setting for Image Data YUV422P Format Output to System Memory \hideinitializer */
#define CCAP_PAR_PLNFMT_YUV420 (0x1ul<<CCAP_PAR_PLNFMT_Pos) /*!< CCAP PAR setting for Image Data YUV420P Format Output to System Memory \hideinitializer */
#define CCAP_PAR_OUTFMT_YUV422 (0x0ul<<CCAP_PAR_OUTFMT_Pos) /*!< CCAP PAR setting for Image Data YUV422 Format Output to System Memory \hideinitializer */
#define CCAP_PAR_OUTFMT_ONLY_Y (0x1ul<<CCAP_PAR_OUTFMT_Pos) /*!< CCAP PAR setting for Image Data ONLY_Y Format Output to System Memory \hideinitializer */
#define CCAP_PAR_OUTFMT_RGB555 (0x2ul<<CCAP_PAR_OUTFMT_Pos) /*!< CCAP PAR setting for Image Data RGB555 Format Output to System Memory \hideinitializer */
#define CCAP_PAR_OUTFMT_RGB565 (0x3ul<<CCAP_PAR_OUTFMT_Pos) /*!< CCAP PAR setting for Image Data RGB565 Format Output to System Memory \hideinitializer */
#define CCAP_PAR_VSP_LOW (0x0ul<<CCAP_PAR_VSP_Pos) /*!< CCAP PAR setting for Sensor Vsync Polarity \hideinitializer */
#define CCAP_PAR_VSP_HIGH (0x1ul<<CCAP_PAR_VSP_Pos) /*!< CCAP PAR setting for Sensor Vsync Polarity \hideinitializer */
#define CCAP_PAR_HSP_LOW (0x0ul<<CCAP_PAR_HSP_Pos) /*!< CCAP PAR setting for Sensor Hsync Polarity \hideinitializer */
#define CCAP_PAR_HSP_HIGH (0x1ul<<CCAP_PAR_HSP_Pos) /*!< CCAP PAR setting for Sensor Hsync Polarity \hideinitializer */
#define CCAP_PAR_PCLKP_LOW (0x0ul<<CCAP_PAR_PCLKP_Pos) /*!< CCAP PAR setting for Sensor Pixel Clock Polarity \hideinitializer */
#define CCAP_PAR_PCLKP_HIGH (0x1ul<<CCAP_PAR_PCLKP_Pos) /*!< CCAP PAR setting for Sensor Pixel Clock Polarity \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* INT constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CCAP_INT_VIEN_ENABLE (0x1ul<<CCAP_INT_VIEN_Pos) /*!< VININT setting for Video Frame End Interrupt enable \hideinitializer */
#define CCAP_INT_MEIEN_ENABLE (0x1ul<<CCAP_INT_MEIEN_Pos) /*!< VININT setting for Bus Master Transfer Error Interrupt enable \hideinitializer */
#define CCAP_INT_ADDRMIEN_ENABLE (0x1ul<<CCAP_INT_ADDRMIEN_Pos) /*!< VININT setting for Memory Address Match Interrupt enable \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Define Error Code */
/*---------------------------------------------------------------------------------------------------------*/
#define CCAP_INVALID_INT ((int32_t)(0xFFFFFFFF-1))
#define CCAP_INVALID_BUF ((int32_t)(0xFFFFFFFF-2))
#define CCAP_INVALID_PIPE ((int32_t)(0xFFFFFFFF-3))
#define CCAP_TIMEOUT_ERR (-1) /*!< CCAP operation abort due to timeout error \hideinitializer */
/*@}*/ /* end of group CCAP_EXPORTED_CONSTANTS */
extern int32_t g_CCAP_i32ErrCode;
/** @addtogroup CCAP_EXPORTED_FUNCTIONS CCAP Exported Functions
@{
*/
/**
* @brief Is CCAP module stopped
*
* @param None
*
* @retval 0 CCAP module is enabled
* @retval 1 CCAP module is disabled(stopped)
*
* @details Check Camera Capture Interface module Enable or Disable(stopped)
* \hideinitializer
*/
#define CCAP_IS_STOPPED(ccap) ((ccap->CTL & CCAP_CTL_CCAPEN_Msk)?0:1)
/**
* @brief Clear CCAP flag
*
* @param[in] u32IntMask interrupt flags settings. It could be
* - \ref CCAP_INT_VINTF_Msk
* - \ref CCAP_INT_MEINTF_Msk
* - \ref CCAP_INT_ADDRMINTF_Msk
* - \ref CCAP_INT_MDINTF_Msk
*
* @return None
*
* @details Clear Camera Capture Interface interrupt flag
* \hideinitializer
*/
#define CCAP_CLR_INT_FLAG(ccap, u32IntMask) (ccap->INT |= (u32IntMask))
/**
* @brief Get CCAP Interrupt status
*
* @param None
*
* @return CCAP Interrupt Register
*
* @details Get Camera Capture Interface interrupt status.
* \hideinitializer
*/
#define CCAP_GET_INT_STS(ccap) (ccap->INT)
void CCAP_Open(CCAP_T *ccap, uint32_t u32InFormat, uint32_t u32OutFormat);
void CCAP_SetCroppingWindow(CCAP_T *ccap, uint32_t u32VStart, uint32_t u32HStart, uint32_t u32Height, uint32_t u32Width);
void CCAP_SetPacketBuf(CCAP_T *ccap, uint32_t u32Address);
void CCAP_Close(CCAP_T *ccap);
void CCAP_EnableInt(CCAP_T *ccap, uint32_t u32IntMask);
void CCAP_DisableInt(CCAP_T *ccap, uint32_t u32IntMask);
void CCAP_Start(CCAP_T *ccap);
void CCAP_Stop(CCAP_T *ccap, uint32_t u32FrameComplete);
void CCAP_SetPacketScaling(CCAP_T *ccap, uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator);
void CCAP_SetPacketStride(CCAP_T *ccap, uint32_t u32Stride);
void CCAP_EnableMono(CCAP_T *ccap, uint32_t u32Interface);
void CCAP_DisableMono(CCAP_T *ccap);
void CCAP_EnableLumaYOne(CCAP_T *ccap, uint32_t u32th);
void CCAP_DisableLumaYOne(CCAP_T *ccap);
void CCAP_SetPlanarYBuf(CCAP_T *ccap, uint32_t u32Address);
void CCAP_SetPlanarUBuf(CCAP_T *ccap, uint32_t u32Address);
void CCAP_SetPlanarVBuf(CCAP_T *ccap, uint32_t u32Address);
void CCAP_SetPlanarScaling(CCAP_T *ccap, uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator);
void CCAP_SetPlanarStride(CCAP_T *ccap, uint32_t u32Stride);
/*@}*/ /* end of group CCAP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CCAP_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif //__NU_CCAP_H__

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/**************************************************************************//**
* @file nu_crc.h
* @version V3.00
* @brief Cyclic Redundancy Check(CRC) driver header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_CRC_H__
#define __NU_CRC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CRC_Driver CRC Driver
@{
*/
/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* CRC Polynomial Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CRC_CCITT (0UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CCITT \hideinitializer */
#define CRC_8 (1UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC8 \hideinitializer */
#define CRC_16 (2UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC16 \hideinitializer */
#define CRC_32 (3UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC32 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Checksum, Write data Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CRC_CHECKSUM_COM (CRC_CTL_CHKSFMT_Msk) /*!<CRC Checksum Complement \hideinitializer */
#define CRC_CHECKSUM_RVS (CRC_CTL_CHKSREV_Msk) /*!<CRC Checksum Reverse \hideinitializer */
#define CRC_WDATA_COM (CRC_CTL_DATFMT_Msk) /*!<CRC Write Data Complement \hideinitializer */
#define CRC_WDATA_RVS (CRC_CTL_DATREV_Msk) /*!<CRC Write Data Reverse \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* CPU Write Data Length Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CRC_CPU_WDATA_8 (0UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 8-bit \hideinitializer */
#define CRC_CPU_WDATA_16 (1UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 16-bit \hideinitializer */
#define CRC_CPU_WDATA_32 (2UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 32-bit \hideinitializer */
/**@}*/ /* end of group CRC_EXPORTED_CONSTANTS */
/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
@{
*/
/**
* @brief Set CRC Seed Value
*
* @param[in] u32Seed Seed value
*
* @return None
*
* @details This macro is used to set CRC seed value.
*
* @note User must to perform CRC_CHKSINIT(CRC_CTL[1] CRC Engine Reset) to reload the new seed value
* to CRC controller.
* \hideinitializer
*/
#define CRC_SET_SEED(u32Seed) do{ CRC->SEED = (u32Seed); CRC->CTL |= CRC_CTL_CHKSINIT_Msk; }while(0)
/**
* @brief Get CRC Seed Value
*
* @param None
*
* @return CRC seed value
*
* @details This macro gets the current CRC seed value.
* \hideinitializer
*/
#define CRC_GET_SEED() (CRC->SEED)
/**
* @brief CRC Write Data
*
* @param[in] u32Data Write data
*
* @return None
*
* @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation.
* \hideinitializer
*/
#define CRC_WRITE_DATA(u32Data) (CRC->DAT = (u32Data))
void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
uint32_t CRC_GetChecksum(void);
/**@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
/**@}*/ /* end of group CRC_Driver */
/**@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_CRC_H__ */

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/**************************************************************************//**
* @file nu_crypto.h
* @version V3.00
* @brief Cryptographic Accelerator driver header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __NU_CRYPTO_H__
#define __NU_CRYPTO_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CRYPTO_Driver CRYPTO Driver
@{
*/
/** @addtogroup CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants
@{
*/
#define PRNG_KEY_SIZE_128 ( 0UL) /*!< Select to generate 128-bit random key \hideinitializer */
#define PRNG_KEY_SIZE_163 ( 1UL) /*!< Select to generate 163-bit random key \hideinitializer */
#define PRNG_KEY_SIZE_192 ( 2UL) /*!< Select to generate 192-bit random key \hideinitializer */
#define PRNG_KEY_SIZE_224 ( 3UL) /*!< Select to generate 224-bit random key \hideinitializer */
#define PRNG_KEY_SIZE_255 ( 4UL) /*!< Select to generate 255-bit random key \hideinitializer */
#define PRNG_KEY_SIZE_256 ( 6UL) /*!< Select to generate 256-bit random key \hideinitializer */
#define PRNG_KEY_SIZE_283 ( 7UL) /*!< Select to generate 283-bit random key (Key Store Only) \hideinitializer */
#define PRNG_KEY_SIZE_384 ( 8UL) /*!< Select to generate 384-bit random key (Key Store Only) \hideinitializer */
#define PRNG_KEY_SIZE_409 ( 9UL) /*!< Select to generate 409-bit random key (Key Store Only) \hideinitializer */
#define PRNG_KEY_SIZE_512 (10UL) /*!< Select to generate 512-bit random key (Key Store Only) \hideinitializer */
#define PRNG_KEY_SIZE_521 (11UL) /*!< Select to generate 521-bit random key (Key Store Only) \hideinitializer */
#define PRNG_KEY_SIZE_571 (12UL) /*!< Select to generate 571-bit random key (Key Store Only) \hideinitializer */
#define PRNG_SEED_CONT (0UL) /*!< PRNG using current seed \hideinitializer */
#define PRNG_SEED_RELOAD (1UL) /*!< PRNG reload new seed \hideinitializer */
#define PRNG_CTL_SEEDSRC_TRNG (0UL) /*!< PRNG seed from TRNG \hideinitializer */
#define PRNG_CTL_SEEDSRC_SEEDREG (CRPT_PRNG_CTL_SEEDSRC_Msk) /*!< PRNG seed from PRNG seed register \hideinitializer */
#define AES_KEY_SIZE_128 (0UL) /*!< AES select 128-bit key length \hideinitializer */
#define AES_KEY_SIZE_192 (1UL) /*!< AES select 192-bit key length \hideinitializer */
#define AES_KEY_SIZE_256 (2UL) /*!< AES select 256-bit key length \hideinitializer */
#define AES_MODE_ECB (0UL) /*!< AES select ECB mode \hideinitializer */
#define AES_MODE_CBC (1UL) /*!< AES select CBC mode \hideinitializer */
#define AES_MODE_CFB (2UL) /*!< AES select CFB mode \hideinitializer */
#define AES_MODE_OFB (3UL) /*!< AES select OFB mode \hideinitializer */
#define AES_MODE_CTR (4UL) /*!< AES select CTR mode \hideinitializer */
#define AES_MODE_CBC_CS1 (0x10UL) /*!< AES select CBC CS1 mode \hideinitializer */
#define AES_MODE_CBC_CS2 (0x11UL) /*!< AES select CBC CS2 mode \hideinitializer */
#define AES_MODE_CBC_CS3 (0x12UL) /*!< AES select CBC CS3 mode \hideinitializer */
#define AES_MODE_GCM (0x20UL)
#define AES_MODE_GHASH (0x21UL)
#define AES_MODE_CCM (0x22UL)
#define SM4_MODE_ECB (0x200UL) /*!< SM4 select ECB mode \hideinitializer */
#define SM4_MODE_CBC (0x201UL) /*!< SM4 select CBC mode \hideinitializer */
#define SM4_MODE_CFB (0x202UL) /*!< SM4 select CFB mode \hideinitializer */
#define SM4_MODE_OFB (0x203UL) /*!< SM4 select OFB mode \hideinitializer */
#define SM4_MODE_CTR (0x204UL) /*!< SM4 select CTR mode \hideinitializer */
#define SM4_MODE_CBC_CS1 (0x210UL) /*!< SM4 select CBC CS1 mode \hideinitializer */
#define SM4_MODE_CBC_CS2 (0x211UL) /*!< SM4 select CBC CS2 mode \hideinitializer */
#define SM4_MODE_CBC_CS3 (0x212UL) /*!< SM4 select CBC CS3 mode \hideinitializer */
#define SM4_MODE_GCM (0x220UL)
#define SM4_MODE_GHASH (0x221UL)
#define SM4_MODE_CCM (0x222UL)
#define AES_NO_SWAP (0UL) /*!< AES do not swap input and output data \hideinitializer */
#define AES_OUT_SWAP (1UL) /*!< AES swap output data \hideinitializer */
#define AES_IN_SWAP (2UL) /*!< AES swap input data \hideinitializer */
#define AES_IN_OUT_SWAP (3UL) /*!< AES swap both input and output data \hideinitializer */
#define DES_MODE_ECB (0x000UL) /*!< DES select ECB mode \hideinitializer */
#define DES_MODE_CBC (0x100UL) /*!< DES select CBC mode \hideinitializer */
#define DES_MODE_CFB (0x200UL) /*!< DES select CFB mode \hideinitializer */
#define DES_MODE_OFB (0x300UL) /*!< DES select OFB mode \hideinitializer */
#define DES_MODE_CTR (0x400UL) /*!< DES select CTR mode \hideinitializer */
#define TDES_MODE_ECB (0x004UL) /*!< TDES select ECB mode \hideinitializer */
#define TDES_MODE_CBC (0x104UL) /*!< TDES select CBC mode \hideinitializer */
#define TDES_MODE_CFB (0x204UL) /*!< TDES select CFB mode \hideinitializer */
#define TDES_MODE_OFB (0x304UL) /*!< TDES select OFB mode \hideinitializer */
#define TDES_MODE_CTR (0x404UL) /*!< TDES select CTR mode \hideinitializer */
#define TDES_NO_SWAP (0UL) /*!< TDES do not swap data \hideinitializer */
#define TDES_WHL_SWAP (1UL) /*!< TDES swap high-low word \hideinitializer */
#define TDES_OUT_SWAP (2UL) /*!< TDES swap output data \hideinitializer */
#define TDES_OUT_WHL_SWAP (3UL) /*!< TDES swap output data and high-low word \hideinitializer */
#define TDES_IN_SWAP (4UL) /*!< TDES swap input data \hideinitializer */
#define TDES_IN_WHL_SWAP (5UL) /*!< TDES swap input data and high-low word \hideinitializer */
#define TDES_IN_OUT_SWAP (6UL) /*!< TDES swap both input and output data \hideinitializer */
#define TDES_IN_OUT_WHL_SWAP (7UL) /*!< TDES swap input, output and high-low word \hideinitializer */
#define SHA_MODE_SHA1 (0UL) /*!< SHA select SHA-1 160-bit \hideinitializer */
#define SHA_MODE_SHA224 (5UL) /*!< SHA select SHA-224 224-bit \hideinitializer */
#define SHA_MODE_SHA256 (4UL) /*!< SHA select SHA-256 256-bit \hideinitializer */
#define SHA_MODE_SHA384 (7UL) /*!< SHA select SHA-384 384-bit \hideinitializer */
#define SHA_MODE_SHA512 (6UL) /*!< SHA select SHA-512 512-bit \hideinitializer */
#define HMAC_MODE_SHA1 (8UL) /*!< HMAC select SHA-1 160-bit \hideinitializer */
#define HMAC_MODE_SHA224 (13UL) /*!< HMAC select SHA-224 224-bit \hideinitializer */
#define HMAC_MODE_SHA256 (12UL) /*!< HMAC select SHA-256 256-bit \hideinitializer */
#define HMAC_MODE_SHA384 (15UL) /*!< HMAC select SHA-384 384-bit \hideinitializer */
#define HMAC_MODE_SHA512 (14UL) /*!< HMAC select SHA-512 512-bit \hideinitializer */
#define SHA_NO_SWAP (0UL) /*!< SHA do not swap input and output data \hideinitializer */
#define SHA_OUT_SWAP (1UL) /*!< SHA swap output data \hideinitializer */
#define SHA_IN_SWAP (2UL) /*!< SHA swap input data \hideinitializer */
#define SHA_IN_OUT_SWAP (3UL) /*!< SHA swap both input and output data \hideinitializer */
#define CRYPTO_DMA_FIRST (0x4UL) /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */
#define CRYPTO_DMA_ONE_SHOT (0x5UL) /*!< Do one shot encrypt/decrypt with DMA \hideinitializer */
#define CRYPTO_DMA_CONTINUE (0x6UL) /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */
#define CRYPTO_DMA_LAST (0x7UL) /*!< Do last encrypt/decrypt in DMA cascade \hideinitializer */
//---------------------------------------------------
#define RSA_MAX_KLEN (4096)
#define RSA_KBUF_HLEN (RSA_MAX_KLEN/4 + 8)
#define RSA_KBUF_BLEN (RSA_MAX_KLEN + 32)
#define RSA_KEY_SIZE_1024 (0UL) /*!< RSA select 1024-bit key length \hideinitializer */
#define RSA_KEY_SIZE_2048 (1UL) /*!< RSA select 2048-bit key length \hideinitializer */
#define RSA_KEY_SIZE_3072 (2UL) /*!< RSA select 3072-bit key length \hideinitializer */
#define RSA_KEY_SIZE_4096 (3UL) /*!< RSA select 4096-bit key length \hideinitializer */
#define RSA_MODE_NORMAL (0x000UL) /*!< RSA select normal mode \hideinitializer */
#define RSA_MODE_CRT (0x004UL) /*!< RSA select CRT mode \hideinitializer */
#define RSA_MODE_CRTBYPASS (0x00CUL) /*!< RSA select CRT bypass mode \hideinitializer */
#define RSA_MODE_SCAP (0x100UL) /*!< RSA select SCAP mode \hideinitializer */
#define RSA_MODE_CRT_SCAP (0x104UL) /*!< RSA select CRT SCAP mode \hideinitializer */
#define RSA_MODE_CRTBYPASS_SCAP (0x10CUL) /*!< RSA select CRT bypass SCAP mode \hideinitializer */
typedef enum
{
/*!< ECC curve \hideinitializer */
CURVE_P_192, /*!< ECC curve P-192 \hideinitializer */
CURVE_P_224, /*!< ECC curve P-224 \hideinitializer */
CURVE_P_256, /*!< ECC curve P-256 \hideinitializer */
CURVE_P_384, /*!< ECC curve P-384 \hideinitializer */
CURVE_P_521, /*!< ECC curve P-521 \hideinitializer */
CURVE_K_163, /*!< ECC curve K-163 \hideinitializer */
CURVE_K_233, /*!< ECC curve K-233 \hideinitializer */
CURVE_K_283, /*!< ECC curve K-283 \hideinitializer */
CURVE_K_409, /*!< ECC curve K-409 \hideinitializer */
CURVE_K_571, /*!< ECC curve K-571 \hideinitializer */
CURVE_B_163, /*!< ECC curve B-163 \hideinitializer */
CURVE_B_233, /*!< ECC curve B-233 \hideinitializer */
CURVE_B_283, /*!< ECC curve B-283 \hideinitializer */
CURVE_B_409, /*!< ECC curve B-409 \hideinitializer */
CURVE_B_571, /*!< ECC curve K-571 \hideinitializer */
CURVE_KO_192, /*!< ECC 192-bits "Koblitz" curve \hideinitializer */
CURVE_KO_224, /*!< ECC 224-bits "Koblitz" curve \hideinitializer */
CURVE_KO_256, /*!< ECC 256-bits "Koblitz" curve \hideinitializer */
CURVE_BP_256, /*!< ECC Brainpool 256-bits curve \hideinitializer */
CURVE_BP_384, /*!< ECC Brainpool 256-bits curve \hideinitializer */
CURVE_BP_512, /*!< ECC Brainpool 256-bits curve \hideinitializer */
CURVE_25519, /*!< ECC curve-25519 \hideinitializer */
CURVE_SM2_256, /*!< SM2 \hideinitializer */
CURVE_UNDEF = -0x7fffffff, /*!< Invalid curve \hideinitializer */
}
E_ECC_CURVE;
typedef struct e_curve_t
{
E_ECC_CURVE curve_id;
int32_t Echar;
char Ea[144];
char Eb[144];
char Px[144];
char Py[144];
int32_t Epl;
char Pp[176];
int32_t Eol;
char Eorder[176];
int32_t key_len;
int32_t irreducible_k1;
int32_t irreducible_k2;
int32_t irreducible_k3;
int32_t GF;
} ECC_CURVE;
/* RSA working buffer for normal mode */
typedef struct
{
uint32_t au32RsaOutput[128]; /* The RSA answer. */
uint32_t au32RsaN[128]; /* The base of modulus operation word. */
uint32_t au32RsaM[128]; /* The base of exponentiation words. */
uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */
} RSA_BUF_NORMAL_T;
/* RSA working buffer for CRT ( + CRT bypass) mode */
typedef struct
{
uint32_t au32RsaOutput[128]; /* The RSA answer. */
uint32_t au32RsaN[128]; /* The base of modulus operation word. */
uint32_t au32RsaM[128]; /* The base of exponentiation words. */
uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */
uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */
uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */
uint32_t au32RsaTmpCp[128]; /* The Temporary Value(Cp) of RSA CRT. */
uint32_t au32RsaTmpCq[128]; /* The Temporary Value(Cq) of RSA CRT. */
uint32_t au32RsaTmpDp[128]; /* The Temporary Value(Dp) of RSA CRT. */
uint32_t au32RsaTmpDq[128]; /* The Temporary Value(Dq) of RSA CRT. */
uint32_t au32RsaTmpRp[128]; /* The Temporary Value(Rp) of RSA CRT. */
uint32_t au32RsaTmpRq[128]; /* The Temporary Value(Rq) of RSA CRT. */
} RSA_BUF_CRT_T;
/* RSA working buffer for SCAP mode */
typedef struct
{
uint32_t au32RsaOutput[128]; /* The RSA answer. */
uint32_t au32RsaN[128]; /* The base of modulus operation word. */
uint32_t au32RsaM[128]; /* The base of exponentiation words. */
uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */
uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */
uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */
uint32_t au32RsaTmpBlindKey[128]; /* The Temporary Value(blind key) of RSA SCAP. */
} RSA_BUF_SCAP_T;
/* RSA working buffer for CRT ( + CRT bypass ) + SCAP mode */
typedef struct
{
uint32_t au32RsaOutput[128]; /* The RSA answer. */
uint32_t au32RsaN[128]; /* The base of modulus operation word. */
uint32_t au32RsaM[128]; /* The base of exponentiation words. */
uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */
uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */
uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */
uint32_t au32RsaTmpCp[128]; /* The Temporary Value(Cp) of RSA CRT. */
uint32_t au32RsaTmpCq[128]; /* The Temporary Value(Cq) of RSA CRT. */
uint32_t au32RsaTmpDp[128]; /* The Temporary Value(Dp) of RSA CRT. */
uint32_t au32RsaTmpDq[128]; /* The Temporary Value(Dq) of RSA CRT. */
uint32_t au32RsaTmpRp[128]; /* The Temporary Value(Rp) of RSA CRT. */
uint32_t au32RsaTmpRq[128]; /* The Temporary Value(Rq) of RSA CRT. */
uint32_t au32RsaTmpBlindKey[128]; /* The Temporary Value(blind key) of RSA SCAP. */
} RSA_BUF_CRT_SCAP_T;
/* RSA working buffer for using key store */
typedef struct
{
uint32_t au32RsaOutput[128]; /* The RSA answer. */
uint32_t au32RsaN[128]; /* The base of modulus operation word. */
uint32_t au32RsaM[128]; /* The base of exponentiation words. */
} RSA_BUF_KS_T;
/**@}*/ /* end of group CRYPTO_EXPORTED_CONSTANTS */
/** @addtogroup CRYPTO_EXPORTED_MACROS CRYPTO Exported Macros
@{
*/
/*----------------------------------------------------------------------------------------------*/
/* Macros */
/*----------------------------------------------------------------------------------------------*/
/**
* @brief This macro enables PRNG interrupt.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define PRNG_ENABLE_INT(crpt) ((crpt)->INTEN |= CRPT_INTEN_PRNGIEN_Msk)
/**
* @brief This macro disables PRNG interrupt.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define PRNG_DISABLE_INT(crpt) ((crpt)->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk)
/**
* @brief This macro gets PRNG interrupt flag.
* @param crpt Specified crypto module
* @return PRNG interrupt flag.
* \hideinitializer
*/
#define PRNG_GET_INT_FLAG(crpt) ((crpt)->INTSTS & CRPT_INTSTS_PRNGIF_Msk)
/**
* @brief This macro clears PRNG interrupt flag.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define PRNG_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = CRPT_INTSTS_PRNGIF_Msk)
/**
* @brief This macro enables AES interrupt.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define AES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk))
/**
* @brief This macro disables AES interrupt.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define AES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk))
/**
* @brief This macro gets AES interrupt flag.
* @param crpt Specified crypto module
* @return AES interrupt flag.
* \hideinitializer
*/
#define AES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk))
/**
* @brief This macro clears AES interrupt flag.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define AES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk))
/**
* @brief This macro enables AES key protection.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define AES_ENABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk)
/**
* @brief This macro disables AES key protection.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define AES_DISABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL = ((crpt)->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<<CRPT_AES_CTL_KEYUNPRT_Pos)); \
((crpt)->AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk)
/**
* @brief This macro enables TDES interrupt.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define TDES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk))
/**
* @brief This macro disables TDES interrupt.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define TDES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk))
/**
* @brief This macro gets TDES interrupt flag.
* @param crpt Specified crypto module
* @return TDES interrupt flag.
* \hideinitializer
*/
#define TDES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk))
/**
* @brief This macro clears TDES interrupt flag.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define TDES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk))
/**
* @brief This macro enables TDES key protection.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define TDES_ENABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk)
/**
* @brief This macro disables TDES key protection.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define TDES_DISABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL = ((crpt)->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16UL<<CRPT_TDES_CTL_KEYUNPRT_Pos)); \
((crpt)->TDES_CTL &= ~CRPT_TDES_CTL_KEYPRT_Msk)
/**
* @brief This macro enables SHA interrupt.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define SHA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk))
/**
* @brief This macro disables SHA interrupt.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define SHA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk))
/**
* @brief This macro gets SHA interrupt flag.
* @param crpt Specified crypto module
* @return SHA interrupt flag.
* \hideinitializer
*/
#define SHA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk))
/**
* @brief This macro clears SHA interrupt flag.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define SHA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk))
/**
* @brief This macro enables ECC interrupt.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define ECC_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk))
/**
* @brief This macro disables ECC interrupt.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define ECC_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk))
/**
* @brief This macro gets ECC interrupt flag.
* @param crpt Specified crypto module
* @return ECC interrupt flag.
* \hideinitializer
*/
#define ECC_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk))
/**
* @brief This macro clears ECC interrupt flag.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define ECC_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk))
/**
* @brief This macro enables RSA interrupt.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define RSA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_RSAIEN_Msk|CRPT_INTEN_RSAEIEN_Msk))
/**
* @brief This macro disables RSA interrupt.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define RSA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_RSAIEN_Msk|CRPT_INTEN_RSAEIEN_Msk))
/**
* @brief This macro gets RSA interrupt flag.
* @param crpt Specified crypto module
* @return ECC interrupt flag.
* \hideinitializer
*/
#define RSA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_RSAIF_Msk|CRPT_INTSTS_RSAEIF_Msk))
/**
* @brief This macro clears RSA interrupt flag.
* @param crpt Specified crypto module
* @return None
* \hideinitializer
*/
#define RSA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_RSAIF_Msk|CRPT_INTSTS_RSAEIF_Msk))
/**@}*/ /* end of group CRYPTO_EXPORTED_MACROS */
/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Functions */
/*---------------------------------------------------------------------------------------------------------*/
void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed);
int32_t PRNG_Start(CRPT_T *crpt);
void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]);
void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType);
void AES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode);
void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize);
void AES_SetKey_KS(CRPT_T *crpt, KS_MEM_Type mem, int32_t i32KeyIdx);
void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]);
void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len);
void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode);
void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt);
void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]);
void ECC_DriverISR(CRPT_T *crpt);
int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]);
int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]);
int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]);
int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S);
int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *public_k1, char *public_k2, char *R, char *S);
int32_t RSA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32KeySize, void *psRSA_Buf, uint32_t u32BufSize, uint32_t u32UseKS);
int32_t RSA_SetKey(CRPT_T *crpt, char *Key);
int32_t RSA_SetDMATransfer(CRPT_T *crpt, char *Src, char *n, char *P, char *Q);
void RSA_Start(CRPT_T *crpt);
int32_t RSA_Read(CRPT_T *crpt, char *Output);
int32_t RSA_SetKey_KS(CRPT_T *crpt, uint32_t u32KeyNum, uint32_t u32KSMemType, uint32_t u32BlindKeyNum);
int32_t RSA_SetDMATransfer_KS(CRPT_T *crpt, char *Src, char *n, uint32_t u32PNum,
uint32_t u32QNum, uint32_t u32CpNum, uint32_t u32CqNum, uint32_t u32DpNum,
uint32_t u32DqNum, uint32_t u32RpNum, uint32_t u32RqNum);
int32_t ECC_GeneratePublicKey_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[], uint32_t u32ExtraOp);
int32_t ECC_GenerateSignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, KS_MEM_Type mem_d, int32_t i32KeyIdx_d, KS_MEM_Type mem_k, int32_t i32KeyIdx_k, char *R, char *S);
int32_t ECC_VerifySignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, KS_MEM_Type mem_pk1, int32_t i32KeyIdx_pk1, KS_MEM_Type mem_pk2, int32_t i32KeyIdx_pk2, char *R, char *S);
int32_t ECC_GenerateSecretZ_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[]);
void CRPT_Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]);
void CRPT_Hex2Reg(char input[], uint32_t volatile reg[]);
int32_t ECC_GetCurve(CRPT_T *crpt, E_ECC_CURVE ecc_curve, ECC_CURVE *curve);
/**@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */
/**@}*/ /* end of group CRYPTO_Driver */
/**@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_CRYPTO_H__ */

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