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fix: remove extra space at the end of files

This commit is contained in:
wirano 2024-07-24 23:18:40 +08:00 committed by Rbb666
parent 229b2bffec
commit d56452e662
170 changed files with 6742 additions and 4645 deletions
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2
bsp/gd32/arm/gd32h759i-start/applications/main.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2023, RT-Thread Development Team * Copyright (c) 2006-2024 RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/gd32/arm/gd32h759i-start/board/board.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2023, RT-Thread Development Team * Copyright (c) 2006-2024 RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

8
bsp/gd32/arm/gd32h759i-start/board/board.h
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2023, RT-Thread Development Team * Copyright (c) 2006-2024 RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -19,10 +19,10 @@
#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */ #define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */ #define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
// <o> Internal SRAM memory size[Kbytes] <8-512> /* <o> Internal SRAM memory size[Kbytes] <8-512>*/
// <i>Default: 512 /* <i>Default: 512*/
#ifdef __ICCARM__ #ifdef __ICCARM__
// Use *.icf ram symbal, to avoid hardcode. /* Use *.icf ram symbal, to avoid hardcode.*/
extern char __ICFEDIT_region_RAM_end__; extern char __ICFEDIT_region_RAM_end__;
#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__ #define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
#else #else

32
bsp/gd32/arm/gd32h759i-start/board/gd32h7xx_libopt.h
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@ -1,34 +1,34 @@
/*! /*!
\file gd32h7xx_libopt.h \file gd32h7xx_libopt.h
\brief library optional for gd32h7xx \brief library optional for gd32h7xx
\version 2024-01-05, V1.2.0, demo for GD32H7xx \version 2024-01-05, V1.2.0, demo for GD32H7xx
*/ */
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

119
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/GD/GD32H7xx/Source/system_gd32h7xx.c
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@ -38,16 +38,16 @@
/* select a system clock by uncommenting the following line */ /* select a system clock by uncommenting the following line */
/* use IRC64M */ /* use IRC64M */
//#define __SYSTEM_CLOCK_IRC64M (__IRC64M) /*#define __SYSTEM_CLOCK_IRC64M (__IRC64M)*/
//#define __SYSTEM_CLOCK_600M_PLL0_IRC64M (uint32_t)(600000000) /*#define __SYSTEM_CLOCK_600M_PLL0_IRC64M (uint32_t)(600000000)*/
/* use LPIRC4M */ /* use LPIRC4M */
//#define __SYSTEM_CLOCK_LPIRC4M (__LPIRC4M) /*#define __SYSTEM_CLOCK_LPIRC4M (__LPIRC4M)*/
/* use HXTAL(CK_HXTAL = 25M) */ /* use HXTAL(CK_HXTAL = 25M) */
//#define __SYSTEM_CLOCK_HXTAL (__HXTAL) /*#define __SYSTEM_CLOCK_HXTAL (__HXTAL)*/
//#define __SYSTEM_CLOCK_200M_PLL0_HXTAL (uint32_t)(200000000) /*#define __SYSTEM_CLOCK_200M_PLL0_HXTAL (uint32_t)(200000000)*/
//#define __SYSTEM_CLOCK_400M_PLL0_HXTAL (uint32_t)(400000000) /*#define __SYSTEM_CLOCK_400M_PLL0_HXTAL (uint32_t)(400000000)*/
#define __SYSTEM_CLOCK_600M_PLL0_HXTAL (uint32_t)(600000000) #define __SYSTEM_CLOCK_600M_PLL0_HXTAL (uint32_t)(600000000)
/* /*
@ -63,18 +63,18 @@ Note: the power mode need to match the mcu selection and external power supply c
the following macro SEL_PMU_SMPS_MODE. the following macro SEL_PMU_SMPS_MODE.
*/ */
#if defined(GD32H7XXI) #if defined(GD32H7XXI)
//#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY /*#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY*/
//#define SEL_PMU_SMPS_MODE PMU_DIRECT_SMPS_SUPPLY /*#define SEL_PMU_SMPS_MODE PMU_DIRECT_SMPS_SUPPLY*/
//#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_LDO /*#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_LDO*/
//#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_LDO /*#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_LDO*/
//#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO /*#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO*/
//#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO /*#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO*/
//#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_EXT /*#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_EXT*/
//#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_EXT /*#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_EXT*/
#define SEL_PMU_SMPS_MODE PMU_BYPASS #define SEL_PMU_SMPS_MODE PMU_BYPASS
#elif defined(GD32H7XXZ) | defined(GD32H7XXV) #elif defined(GD32H7XXZ) | defined(GD32H7XXV)
//#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY /*#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY*/
//#define SEL_PMU_SMPS_MODE PMU_BYPASS /*#define SEL_PMU_SMPS_MODE PMU_BYPASS*/
#endif #endif
#define SEL_IRC64MDIV 0x00U #define SEL_IRC64MDIV 0x00U
@ -153,7 +153,8 @@ void SystemInit(void)
/* enable IRC64M */ /* enable IRC64M */
RCU_CTL |= RCU_CTL_IRC64MEN; RCU_CTL |= RCU_CTL_IRC64MEN;
while(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) { while(0U == (RCU_CTL & RCU_CTL_IRC64MSTB))
{
} }
/* no TCM wait state */ /* no TCM wait state */
@ -256,8 +257,10 @@ static void system_clock_64m_irc64m(void)
} while((0U == stab_flag) && (IRC64M_STARTUP_TIMEOUT != timeout)); } while((0U == stab_flag) && (IRC64M_STARTUP_TIMEOUT != timeout));
/* if fail */ /* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) { if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB))
while(1) { {
while(1)
{
} }
} }
@ -281,7 +284,8 @@ static void system_clock_64m_irc64m(void)
RCU_CFG0 |= RCU_CKSYSSRC_IRC64MDIV; RCU_CFG0 |= RCU_CKSYSSRC_IRC64MDIV;
/* wait until IRC64M is selected as system clock */ /* wait until IRC64M is selected as system clock */
while(RCU_SCSS_IRC64MDIV != (RCU_CFG0 & RCU_CFG0_SCSS)) { while(RCU_SCSS_IRC64MDIV != (RCU_CFG0 & RCU_CFG0_SCSS))
{
} }
} }
@ -307,8 +311,10 @@ static void system_clock_600m_irc64m(void)
} while((0U == stab_flag) && (IRC64M_STARTUP_TIMEOUT != timeout)); } while((0U == stab_flag) && (IRC64M_STARTUP_TIMEOUT != timeout));
/* if fail */ /* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) { if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB))
while(1) { {
while(1)
{
} }
} }
@ -347,7 +353,8 @@ static void system_clock_600m_irc64m(void)
RCU_CTL |= RCU_CTL_PLL0EN; RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */ /* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) { while(0U == (RCU_CTL & RCU_CTL_PLL0STB))
{
} }
/* select PLL0 as system clock */ /* select PLL0 as system clock */
@ -355,7 +362,8 @@ static void system_clock_600m_irc64m(void)
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P; RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */ /* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) { while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS))
{
} }
} }
@ -380,8 +388,10 @@ static void system_clock_4m_lpirc4m(void)
stab_flag = (RCU_ADDCTL1 & RCU_ADDCTL1_LPIRC4MSTB); stab_flag = (RCU_ADDCTL1 & RCU_ADDCTL1_LPIRC4MSTB);
} while((0U == stab_flag) && (LPIRC4M_STARTUP_TIMEOUT != timeout)); } while((0U == stab_flag) && (LPIRC4M_STARTUP_TIMEOUT != timeout));
/* if fail */ /* if fail */
if(0U == (RCU_ADDCTL1 & RCU_ADDCTL1_LPIRC4MSTB)) { if(0U == (RCU_ADDCTL1 & RCU_ADDCTL1_LPIRC4MSTB))
while(1) { {
while(1)
{
} }
} }
@ -402,7 +412,8 @@ static void system_clock_4m_lpirc4m(void)
RCU_CFG0 |= RCU_CKSYSSRC_LPIRC4M; RCU_CFG0 |= RCU_CKSYSSRC_LPIRC4M;
/* wait until LPIRC4M is selected as system clock */ /* wait until LPIRC4M is selected as system clock */
while(RCU_SCSS_LPIRC4M != (RCU_CFG0 & RCU_CFG0_SCSS)) { while(RCU_SCSS_LPIRC4M != (RCU_CFG0 & RCU_CFG0_SCSS))
{
} }
} }
@ -427,8 +438,10 @@ static void system_clock_hxtal(void)
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */ /* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
while(1) { {
while(1)
{
} }
} }
@ -449,7 +462,8 @@ static void system_clock_hxtal(void)
RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
/* wait until HXTAL is selected as system clock */ /* wait until HXTAL is selected as system clock */
while(RCU_SCSS_HXTAL != (RCU_CFG0 & RCU_CFG0_SCSS)) { while(RCU_SCSS_HXTAL != (RCU_CFG0 & RCU_CFG0_SCSS))
{
} }
} }
@ -474,8 +488,10 @@ static void system_clock_200m_hxtal(void)
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */ /* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
while(1) { {
while(1)
{
} }
} }
@ -508,7 +524,8 @@ static void system_clock_200m_hxtal(void)
RCU_CTL |= RCU_CTL_PLL0EN; RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */ /* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) { while(0U == (RCU_CTL & RCU_CTL_PLL0STB))
{
} }
/* select PLL0 as system clock */ /* select PLL0 as system clock */
@ -516,7 +533,8 @@ static void system_clock_200m_hxtal(void)
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P; RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */ /* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) { while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS))
{
} }
} }
@ -541,8 +559,10 @@ static void system_clock_400m_hxtal(void)
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */ /* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
while(1) { {
while(1)
{
} }
} }
@ -579,7 +599,8 @@ static void system_clock_400m_hxtal(void)
RCU_CTL |= RCU_CTL_PLL0EN; RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */ /* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) { while(0U == (RCU_CTL & RCU_CTL_PLL0STB))
{
} }
/* select PLL0 as system clock */ /* select PLL0 as system clock */
@ -587,7 +608,8 @@ static void system_clock_400m_hxtal(void)
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P; RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */ /* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) { while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS))
{
} }
} }
@ -612,8 +634,10 @@ static void system_clock_600m_hxtal(void)
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */ /* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
while(1) { {
while(1)
{
} }
} }
@ -650,7 +674,8 @@ static void system_clock_600m_hxtal(void)
RCU_CTL |= RCU_CTL_PLL0EN; RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */ /* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) { while(0U == (RCU_CTL & RCU_CTL_PLL0STB))
{
} }
/* select PLL0 as system clock */ /* select PLL0 as system clock */
@ -658,7 +683,8 @@ static void system_clock_600m_hxtal(void)
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P; RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */ /* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) { while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS))
{
} }
} }
@ -677,7 +703,8 @@ void SystemCoreClockUpdate(void)
uint32_t pllpsc = 0U, plln = 0U, pllp = 0U, pllsel = 0U; uint32_t pllpsc = 0U, plln = 0U, pllp = 0U, pllsel = 0U;
sws = GET_BITS(RCU_CFG0, 2, 3); sws = GET_BITS(RCU_CFG0, 2, 3);
switch(sws) { switch(sws)
{
/* IRC64M is selected as CK_SYS */ /* IRC64M is selected as CK_SYS */
case SEL_IRC64MDIV: case SEL_IRC64MDIV:
irc64div = (1U << GET_BITS(RCU_ADDCTL1, 16, 17)); irc64div = (1U << GET_BITS(RCU_ADDCTL1, 16, 17));
@ -700,10 +727,12 @@ void SystemCoreClockUpdate(void)
/* PLL clock source selection, HXTAL or IRC64M_VALUE or LPIRC4M_VALUE */ /* PLL clock source selection, HXTAL or IRC64M_VALUE or LPIRC4M_VALUE */
pllsel = GET_BITS(RCU_PLLALL, 16, 17); pllsel = GET_BITS(RCU_PLLALL, 16, 17);
if(0U == pllsel) { if(0U == pllsel)
{
irc64div = (1U << GET_BITS(RCU_ADDCTL1, 16, 17)); irc64div = (1U << GET_BITS(RCU_ADDCTL1, 16, 17));
SystemCoreClock = (IRC64M_VALUE / irc64div / pllpsc) * plln / pllp; SystemCoreClock = (IRC64M_VALUE / irc64div / pllpsc) * plln / pllp;
} else if(1U == pllsel) { } else if(1U == pllsel)
{
SystemCoreClock = (LPIRC4M_VALUE / pllpsc) * plln / pllp; SystemCoreClock = (LPIRC4M_VALUE / pllpsc) * plln / pllp;
} else { } else {
SystemCoreClock = (HXTAL_VALUE / pllpsc) * plln / pllp; SystemCoreClock = (HXTAL_VALUE / pllpsc) * plln / pllp;

12
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cachel1_armv7.h
View File

@ -115,7 +115,8 @@ __STATIC_FORCEINLINE void SCB_InvalidateICache (void)
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) __STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
{ {
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if ( isize > 0 ) { if ( isize > 0 )
{
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
@ -358,7 +359,8 @@ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{ {
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) { if ( dsize > 0 )
{
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
@ -388,7 +390,8 @@ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
{ {
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) { if ( dsize > 0 )
{
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
@ -418,7 +421,8 @@ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{ {
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) { if ( dsize > 0 )
{
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;

22
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_armclang.h
View File

@ -64,7 +64,8 @@
#pragma clang diagnostic push #pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked" #pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
struct __attribute__((packed)) T_UINT32 { uint32_t v; }; struct __attribute__((packed))T_UINT32
{ uint32_t v; };
#pragma clang diagnostic pop #pragma clang diagnostic pop
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif #endif
@ -153,7 +154,8 @@
#endif #endif
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop)
{
*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
} }
#endif #endif
@ -1217,7 +1219,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI /* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U; return 0U;
#else #else
uint32_t result; uint32_t result;
@ -1240,7 +1242,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{ {
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
// without main extensions, the non-secure PSPLIM is RAZ/WI /* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U; return 0U;
#else #else
uint32_t result; uint32_t result;
@ -1265,7 +1267,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI /* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit; (void)ProcStackPtrLimit;
#else #else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
@ -1287,7 +1289,7 @@ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{ {
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
// without main extensions, the non-secure PSPLIM is RAZ/WI /* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit; (void)ProcStackPtrLimit;
#else #else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
@ -1309,7 +1311,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI /* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U; return 0U;
#else #else
uint32_t result; uint32_t result;
@ -1332,7 +1334,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{ {
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
// without main extensions, the non-secure MSPLIM is RAZ/WI /* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U; return 0U;
#else #else
uint32_t result; uint32_t result;
@ -1356,7 +1358,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI /* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit; (void)MainStackPtrLimit;
#else #else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
@ -1377,7 +1379,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{ {
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
// without main extensions, the non-secure MSPLIM is RAZ/WI /* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit; (void)MainStackPtrLimit;
#else #else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));

22
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_armclang_ltm.h
View File

@ -64,7 +64,8 @@
#pragma clang diagnostic push #pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked" #pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
struct __attribute__((packed)) T_UINT32 { uint32_t v; }; struct __attribute__((packed))T_UINT32
{ uint32_t v; };
#pragma clang diagnostic pop #pragma clang diagnostic pop
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif #endif
@ -152,7 +153,8 @@
#endif #endif
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop)
{
*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
} }
#endif #endif
@ -1201,7 +1203,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI /* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U; return 0U;
#else #else
uint32_t result; uint32_t result;
@ -1223,7 +1225,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI /* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U; return 0U;
#else #else
uint32_t result; uint32_t result;
@ -1247,7 +1249,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI /* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit; (void)ProcStackPtrLimit;
#else #else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
@ -1268,7 +1270,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI /* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit; (void)ProcStackPtrLimit;
#else #else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
@ -1289,7 +1291,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI /* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U; return 0U;
#else #else
uint32_t result; uint32_t result;
@ -1311,7 +1313,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI /* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U; return 0U;
#else #else
uint32_t result; uint32_t result;
@ -1334,7 +1336,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI /* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit; (void)MainStackPtrLimit;
#else #else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
@ -1354,7 +1356,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI /* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit; (void)MainStackPtrLimit;
#else #else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));

5
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_compiler.h
View File

@ -103,7 +103,8 @@
#define __PACKED_UNION union __attribute__((packed)) #define __PACKED_UNION union __attribute__((packed))
#endif #endif
#ifndef __UNALIGNED_UINT32 /* deprecated */ #ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; }; struct __attribute__((packed))T_UINT32
{ uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif #endif
#ifndef __UNALIGNED_UINT16_WRITE #ifndef __UNALIGNED_UINT16_WRITE
@ -236,7 +237,7 @@
#define __STATIC_FORCEINLINE __STATIC_INLINE #define __STATIC_FORCEINLINE __STATIC_INLINE
#endif #endif
#ifndef __NO_RETURN #ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here /* NO RETURN is automatically detected hence no warning here*/
#define __NO_RETURN #define __NO_RETURN
#endif #endif
#ifndef __USED #ifndef __USED

48
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_gcc.h
View File

@ -71,7 +71,8 @@
#pragma GCC diagnostic push #pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes" #pragma GCC diagnostic ignored "-Wattributes"
struct __attribute__((packed)) T_UINT32 { uint32_t v; }; struct __attribute__((packed))T_UINT32
{ uint32_t v; };
#pragma GCC diagnostic pop #pragma GCC diagnostic pop
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif #endif
@ -154,14 +155,18 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
extern const __zero_table_t __zero_table_start__; extern const __zero_table_t __zero_table_start__;
extern const __zero_table_t __zero_table_end__; extern const __zero_table_t __zero_table_end__;
for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable)
for(uint32_t i=0u; i<pTable->wlen; ++i) { {
for(uint32_t i=0u; i<pTable->wlen; ++i)
{
pTable->dest[i] = pTable->src[i]; pTable->dest[i] = pTable->src[i];
} }
} }
for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable)
for(uint32_t i=0u; i<pTable->wlen; ++i) { {
for(uint32_t i=0u; i<pTable->wlen; ++i)
{
pTable->dest[i] = 0u; pTable->dest[i] = 0u;
} }
} }
@ -202,7 +207,8 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
#endif #endif
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop)
{
*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
} }
#endif #endif
@ -1421,7 +1427,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI /* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U; return 0U;
#else #else
uint32_t result; uint32_t result;
@ -1442,7 +1448,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI /* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U; return 0U;
#else #else
uint32_t result; uint32_t result;
@ -1466,7 +1472,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI /* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit; (void)ProcStackPtrLimit;
#else #else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
@ -1486,7 +1492,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI /* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit; (void)ProcStackPtrLimit;
#else #else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
@ -1508,7 +1514,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI /* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U; return 0U;
#else #else
uint32_t result; uint32_t result;
@ -1530,7 +1536,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI /* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U; return 0U;
#else #else
uint32_t result; uint32_t result;
@ -1554,7 +1560,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI /* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit; (void)MainStackPtrLimit;
#else #else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
@ -1574,7 +1580,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{ {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI /* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit; (void)MainStackPtrLimit;
#else #else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
@ -1596,8 +1602,8 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ) (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_get_fpscr) #if __has_builtin(__builtin_arm_get_fpscr)
// Re-enable using built-in when GCC has been fixed /* Re-enable using built-in when GCC has been fixed*/
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)*/
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
return __builtin_arm_get_fpscr(); return __builtin_arm_get_fpscr();
#else #else
@ -1622,8 +1628,8 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ) (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_set_fpscr) #if __has_builtin(__builtin_arm_set_fpscr)
// Re-enable using built-in when GCC has been fixed /* Re-enable using built-in when GCC has been fixed*/
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)*/
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
__builtin_arm_set_fpscr(fpscr); __builtin_arm_set_fpscr(fpscr);
#else #else
@ -1995,7 +2001,8 @@ __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
{ {
uint32_t result; uint32_t result;
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
{
__ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
} else { } else {
result = __SXTB16(__ROR(op1, rotate)) ; result = __SXTB16(__ROR(op1, rotate)) ;
@ -2014,7 +2021,8 @@ __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
{ {
uint32_t result; uint32_t result;
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
{
__ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate));
} else { } else {
result = __SXTAB16(op1, __ROR(op2, rotate)); result = __SXTAB16(op1, __ROR(op2, rotate));

105
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/mpu_armv7.h
View File

@ -21,51 +21,51 @@
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef ARM_MPU_ARMV7_H #ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) /*/!< MPU Region Size 32 Bytes*/
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) /*/!< MPU Region Size 64 Bytes*/
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) /*/!< MPU Region Size 128 Bytes*/
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) /*/!< MPU Region Size 256 Bytes*/
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) /*/!< MPU Region Size 512 Bytes*/
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) /*/!< MPU Region Size 1 KByte*/
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) /*/!< MPU Region Size 2 KBytes*/
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) /*/!< MPU Region Size 4 KBytes*/
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) /*/!< MPU Region Size 8 KBytes*/
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) /*/!< MPU Region Size 16 KBytes*/
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) /*/!< MPU Region Size 32 KBytes*/
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) /*/!< MPU Region Size 64 KBytes*/
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) /*/!< MPU Region Size 128 KBytes*/
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) /*/!< MPU Region Size 256 KBytes*/
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) /*/!< MPU Region Size 512 KBytes*/
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) /*/!< MPU Region Size 1 MByte*/
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) /*/!< MPU Region Size 2 MBytes*/
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) /*/!< MPU Region Size 4 MBytes*/
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) /*/!< MPU Region Size 8 MBytes*/
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) /*/!< MPU Region Size 16 MBytes*/
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) /*/!< MPU Region Size 32 MBytes*/
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) /*/!< MPU Region Size 64 MBytes*/
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) /*/!< MPU Region Size 128 MBytes*/
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) /*/!< MPU Region Size 256 MBytes*/
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) /*/!< MPU Region Size 512 MBytes*/
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) /*/!< MPU Region Size 1 GByte*/
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) /*/!< MPU Region Size 2 GBytes*/
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) /*/!< MPU Region Size 4 GBytes*/
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access #define ARM_MPU_AP_NONE 0U /*/!< MPU Access Permission no access*/
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only #define ARM_MPU_AP_PRIV 1U /*/!< MPU Access Permission privileged access only*/
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only #define ARM_MPU_AP_URO 2U /*/!< MPU Access Permission unprivileged access read-only*/
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access #define ARM_MPU_AP_FULL 3U /*/!< MPU Access Permission full access*/
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only #define ARM_MPU_AP_PRO 5U /*/!< MPU Access Permission privileged access read-only*/
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access #define ARM_MPU_AP_RO 6U /*/!< MPU Access Permission read-only access*/
/** MPU Region Base Address Register Value /** MPU Region Base Address Register Value
* *
@ -79,12 +79,12 @@
/** /**
* MPU Memory Access Attributes * MPU Memory Access Attributes
* *
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters. * \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/ */
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
@ -93,7 +93,7 @@
/** /**
* MPU Region Attribute and Size Register Value * MPU Region Attribute and Size Register Value
* *
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
@ -110,7 +110,7 @@
/** /**
* MPU Region Attribute and Size Register Value * MPU Region Attribute and Size Register Value
* *
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
@ -119,7 +119,7 @@
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field. * \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K. * \param Size Region size of the region to be configured, for example 4K, 8K.
*/ */
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
@ -129,7 +129,7 @@
* - Shareable * - Shareable
* - Non-cacheable * - Non-cacheable
* - Non-bufferable * - Non-bufferable
*/ */
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/** /**
@ -140,7 +140,7 @@
* - Bufferable (if shareable) or non-bufferable (if non-shareable) * - Bufferable (if shareable) or non-bufferable (if non-shareable)
* *
* \param IsShareable Configures the device memory as shareable or non-shareable. * \param IsShareable Configures the device memory as shareable or non-shareable.
*/ */
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/** /**
@ -153,7 +153,7 @@
* \param OuterCp Configures the outer cache policy. * \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy. * \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable. * \param IsShareable Configures the memory as shareable or non-shareable.
*/ */
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
/** /**
@ -181,10 +181,10 @@
* Struct for a single MPU Region * Struct for a single MPU Region
*/ */
typedef struct { typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RBAR; /*!< The region base address register value (RBAR)*/
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR uint32_t RASR; /*!< The region attribute and size register value (RASR) \ref MPU_RASR*/
} ARM_MPU_Region_t; } ARM_MPU_Region_t;
/** Enable the MPU. /** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions. * \param MPU_Control Default access permissions for unconfigured regions.
*/ */
@ -224,7 +224,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
/** Configure an MPU region. /** Configure an MPU region.
* \param rbar Value for RBAR register. * \param rbar Value for RBAR register.
* \param rasr Value for RASR register. * \param rasr Value for RASR register.
*/ */
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{ {
MPU->RBAR = rbar; MPU->RBAR = rbar;
@ -235,7 +235,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
* \param rnr Region number to be configured. * \param rnr Region number to be configured.
* \param rbar Value for RBAR register. * \param rbar Value for RBAR register.
* \param rasr Value for RASR register. * \param rasr Value for RASR register.
*/ */
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{ {
MPU->RNR = rnr; MPU->RNR = rnr;
@ -251,7 +251,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{ {
uint32_t i; uint32_t i;
for (i = 0U; i < len; ++i) for (i = 0U; i < len; ++i)
{ {
dst[i] = src[i]; dst[i] = src[i];
} }
@ -261,10 +261,11 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_
* \param table Pointer to the MPU configuration table. * \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured. * \param cnt Amount of regions to be configured.
*/ */
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{ {
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) { while (cnt > MPU_TYPE_RALIASES)
{
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES; table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES; cnt -= MPU_TYPE_RALIASES;

46
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_axiim.h
View File

@ -1,34 +1,34 @@
/*! /*!
\file gd32h7xx_axiim.h \file gd32h7xx_axiim.h
\brief definitions for AXIIM(AXI interconnect matrix) \brief definitions for AXIIM(AXI interconnect matrix)
\version 2024-01-05, V1.2.0, firmware for GD32H7xx \version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/ */
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -51,7 +51,7 @@ OF SUCH DAMAGE.
#define AXI_COMP_ID0 REG32(AXIIM + 0x00001FF0U) /*!< AXI componet ID0 register */ #define AXI_COMP_ID0 REG32(AXIIM + 0x00001FF0U) /*!< AXI componet ID0 register */
#define AXI_COMP_ID1 REG32(AXIIM + 0x00001FF4U) /*!< AXI componet ID1 register */ #define AXI_COMP_ID1 REG32(AXIIM + 0x00001FF4U) /*!< AXI componet ID1 register */
#define AXI_COMP_ID2 REG32(AXIIM + 0x00001FF8U) /*!< AXI componet ID2 register */ #define AXI_COMP_ID2 REG32(AXIIM + 0x00001FF8U) /*!< AXI componet ID2 register */
#define AXI_COMP_ID3 REG32(AXIIM + 0x00001FFCU) /*!< AXI componet ID3 register */ #define AXI_COMP_ID3 REG32(AXIIM + 0x00001FFCU) /*!< AXI componet ID3 register */
#define AXI_MPXBM_ISS_CTL(mportx) REG32(AXIIM + 0x00002008U + 0x00001000U * (mportx)) /*!< AXI master port x bus matrix issuing functionality control register */ #define AXI_MPXBM_ISS_CTL(mportx) REG32(AXIIM + 0x00002008U + 0x00001000U * (mportx)) /*!< AXI master port x bus matrix issuing functionality control register */
#define AXI_MP0BM_ISS_CTL REG32(AXIIM + 0x00002008U) /*!< AXI master port 0 bus matrix issuing functionality control register */ #define AXI_MP0BM_ISS_CTL REG32(AXIIM + 0x00002008U) /*!< AXI master port 0 bus matrix issuing functionality control register */
@ -89,7 +89,7 @@ OF SUCH DAMAGE.
/* AXI slave port x = 0 to 5 */ /* AXI slave port x = 0 to 5 */
#define AXI_SPX_RDQOS_CTL(sportx) REG32(AXIIM + 0x00042100U + 0x00001000U * (sportx)) /*!< AXI slave port x read QOS control register */ #define AXI_SPX_RDQOS_CTL(sportx) REG32(AXIIM + 0x00042100U + 0x00001000U * (sportx)) /*!< AXI slave port x read QOS control register */
#define AXI_SPX_WRQOS_CTL(sportx) REG32(AXIIM + 0x00042104U + 0x00001000U * (sportx)) /*!< AXI slave port x write QOS control register */ #define AXI_SPX_WRQOS_CTL(sportx) REG32(AXIIM + 0x00042104U + 0x00001000U * (sportx)) /*!< AXI slave port x write QOS control register */
#define AXI_SPX_ISS_CTL(sportx) REG32(AXIIM + 0x00042108U + 0x00001000U * (sportx)) /*!< AXI slave port x issuing functionality control register */ #define AXI_SPX_ISS_CTL(sportx) REG32(AXIIM + 0x00042108U + 0x00001000U * (sportx)) /*!< AXI slave port x issuing functionality control register */
#define AXI_PERIPH_ID4_JEP106CCODE BITS(0,3) /*!< JEP106 continuation code */ #define AXI_PERIPH_ID4_JEP106CCODE BITS(0,3) /*!< JEP106 continuation code */
@ -106,7 +106,7 @@ OF SUCH DAMAGE.
#define AXI_PERIPH_ID3_CUSTMOD BITS(0,3) /*!< customer modification[3:0] */ #define AXI_PERIPH_ID3_CUSTMOD BITS(0,3) /*!< customer modification[3:0] */
#define AXI_PERIPH_ID3_CUSTREV BITS(4,7) /*!< customer version */ #define AXI_PERIPH_ID3_CUSTREV BITS(4,7) /*!< customer version */
#define AXI_COMP_ID0_PREAMB BITS(0,7) /*!< preamble bits[7:0] */ #define AXI_COMP_ID0_PREAMB BITS(0,7) /*!< preamble bits[7:0] */
#define AXI_COMP_ID1_PREAMB BITS(0,3) /*!< preamble bits[11:8] */ #define AXI_COMP_ID1_PREAMB BITS(0,3) /*!< preamble bits[11:8] */
@ -131,15 +131,15 @@ OF SUCH DAMAGE.
#define AXI_SPX_AHBISS_CTL_WR_AHB_ISSOV BIT(0) /*!< converts AHB-Lite write transaction to single beat AXI transaction */ #define AXI_SPX_AHBISS_CTL_WR_AHB_ISSOV BIT(0) /*!< converts AHB-Lite write transaction to single beat AXI transaction */
#define AXI_SPX_AHBISS_CTL_RD_AHB_ISSOV BIT(1) /*!< converts AHB-Lite read transaction to single beat AXI transaction */ #define AXI_SPX_AHBISS_CTL_RD_AHB_ISSOV BIT(1) /*!< converts AHB-Lite read transaction to single beat AXI transaction */
#define AXI_SPX_RDQOS_CTL_RDQOS BITS(0,3) /*!< slave port read channel QoS configure bits */ #define AXI_SPX_RDQOS_CTL_RDQOS BITS(0,3) /*!< slave port read channel QoS configure bits */
#define AXI_SPX_WRQOS_CTL_WRQOS BITS(0,3) /*!< slave port write channel QoS configure bits */ #define AXI_SPX_WRQOS_CTL_WRQOS BITS(0,3) /*!< slave port write channel QoS configure bits */
#define AXI_SPX_ISS_CTL_RD_ISSOV BIT(0) /*!< slave port override ASIB read issuing control bit */ #define AXI_SPX_ISS_CTL_RD_ISSOV BIT(0) /*!< slave port override ASIB read issuing control bit */
#define AXI_SPX_ISS_CTL_WR_ISSOV BIT(1) /*!< slave port override ASIB write issuing control bit */ #define AXI_SPX_ISS_CTL_WR_ISSOV BIT(1) /*!< slave port override ASIB write issuing control bit */
/* AXI master port select */ /* AXI master port select */
typedef enum typedef enum
{ {
MASTER_PORT0 = 0U, /*!< AXI master port 0 */ MASTER_PORT0 = 0U, /*!< AXI master port 0 */
MASTER_PORT1, /*!< AXI master port 1 */ MASTER_PORT1, /*!< AXI master port 1 */
@ -152,7 +152,7 @@ typedef enum
} master_port_enum; } master_port_enum;
/* AXI slave port select */ /* AXI slave port select */
typedef enum typedef enum
{ {
SLAVE_PORT0 = 0U, /*!< AXI slave port 0 */ SLAVE_PORT0 = 0U, /*!< AXI slave port 0 */
SLAVE_PORT1, /*!< AXI slave port 1 */ SLAVE_PORT1, /*!< AXI slave port 1 */

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_cau.h
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@ -1,34 +1,34 @@
/*! /*!
\file gd32h7xx_cau.h \file gd32h7xx_cau.h
\brief definitions for the CAU \brief definitions for the CAU
\version 2024-01-05, V1.2.0, firmware for GD32H7xx \version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/ */
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_cpdm.h
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@ -1,34 +1,34 @@
/*! /*!
\file gd32h7xx_cpdm.h \file gd32h7xx_cpdm.h
\brief definitions for the CPDM \brief definitions for the CPDM
\version 2024-01-05, V1.2.0, firmware for GD32H7xx \version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/ */
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

34
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_ctc.h
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@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -48,7 +48,7 @@ OF SUCH DAMAGE.
/* bits definitions */ /* bits definitions */
/* CTC_CTL0 */ /* CTC_CTL0 */
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ #define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ #define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */
#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ #define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */
#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ #define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */
@ -176,7 +176,7 @@ void ctc_interrupt_enable(uint32_t interrupt);
/* disable the CTC interrupt */ /* disable the CTC interrupt */
void ctc_interrupt_disable(uint32_t interrupt); void ctc_interrupt_disable(uint32_t interrupt);
/* get CTC interrupt flag */ /* get CTC interrupt flag */
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag); FlagStatus ctc_interrupt_flag_get(uint32_t int_flag);
/* clear CTC interrupt flag */ /* clear CTC interrupt flag */
void ctc_interrupt_flag_clear(uint32_t int_flag); void ctc_interrupt_flag_clear(uint32_t int_flag);

34
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_dac.h
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@ -1,34 +1,34 @@
/*! /*!
\file gd32h7xx_dac.h \file gd32h7xx_dac.h
\brief definitions for the DAC \brief definitions for the DAC
\version 2024-01-05, V1.2.0, firmware for GD32H7xx \version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/ */
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -72,7 +72,7 @@ OF SUCH DAMAGE.
#define DAC_CTL0_DDMAEN0 BIT(12) /*!< DACx_OUT0 DMA enable */ #define DAC_CTL0_DDMAEN0 BIT(12) /*!< DACx_OUT0 DMA enable */
#define DAC_CTL0_DDUDRIE0 BIT(13) /*!< DACx_OUT0 DMA underrun interrupt enable */ #define DAC_CTL0_DDUDRIE0 BIT(13) /*!< DACx_OUT0 DMA underrun interrupt enable */
#define DAC_CTL0_CALEN0 BIT(14) /*!< DACx_OUT0 calibration enable */ #define DAC_CTL0_CALEN0 BIT(14) /*!< DACx_OUT0 calibration enable */
#define DAC_CTL0_DEN1 BIT(16) /*!< DACx_OUT1 enable bit */ #define DAC_CTL0_DEN1 BIT(16) /*!< DACx_OUT1 enable bit */
#define DAC_CTL0_DTEN1 BIT(17) /*!< DACx_OUT1 trigger enable */ #define DAC_CTL0_DTEN1 BIT(17) /*!< DACx_OUT1 trigger enable */
#define DAC_CTL0_DTSEL1 BITS(18,19) /*!< DACx_OUT1 trigger selection */ #define DAC_CTL0_DTSEL1 BITS(18,19) /*!< DACx_OUT1 trigger selection */
#define DAC_CTL0_DWM1 BITS(22,23) /*!< DACx_OUT1 noise wave mode */ #define DAC_CTL0_DWM1 BITS(22,23) /*!< DACx_OUT1 noise wave mode */

34
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_dbg.h
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@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -110,7 +110,7 @@ OF SUCH DAMAGE.
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) #define DBG_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
/* register index */ /* register index */
typedef enum typedef enum
{ {
DBG_IDX_CTL1 = 0x34U, /*!< DBG control register 1 offset */ DBG_IDX_CTL1 = 0x34U, /*!< DBG control register 1 offset */
DBG_IDX_CTL2 = 0x3CU, /*!< DBG control register 2 offset */ DBG_IDX_CTL2 = 0x3CU, /*!< DBG control register 2 offset */
@ -147,7 +147,7 @@ typedef enum
DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 17U), /*!< debug TIMER15 kept when core is halted */ DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 17U), /*!< debug TIMER15 kept when core is halted */
DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 16U), /*!< debug TIMER14 kept when core is halted */ DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 16U), /*!< debug TIMER14 kept when core is halted */
DBG_CAN2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 4U), /*!< debug CAN2 kept when core is halted */ DBG_CAN2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 4U), /*!< debug CAN2 kept when core is halted */
DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 3U), /*!< debug CAN1 kept when core is halted */ DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 3U), /*!< debug CAN1 kept when core is halted */
DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 2U), /*!< debug CAN0 kept when core is halted */ DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 2U), /*!< debug CAN0 kept when core is halted */
DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 1U), /*!< debug TIMER7 kept when core is halted */ DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 1U), /*!< debug TIMER7 kept when core is halted */
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 0U), /*!< debug TIMER0 kept when core is halted */ DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 0U), /*!< debug TIMER0 kept when core is halted */

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_enet.h
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@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -470,7 +470,7 @@ OF SUCH DAMAGE.
/* ENET DMA Tx descriptor TDES3 */ /* ENET DMA Tx descriptor TDES3 */
#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ #define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */
//#define SELECT_DESCRIPTORS_ENHANCED_MODE /*#define SELECT_DESCRIPTORS_ENHANCED_MODE*/
#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
/* ENET DMA Tx descriptor TDES6 */ /* ENET DMA Tx descriptor TDES6 */

56
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_fac.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -42,7 +42,7 @@ OF SUCH DAMAGE.
#define REG16_INT(addr) (*(volatile int16_t *)(uint32_t)(addr)) #define REG16_INT(addr) (*(volatile int16_t *)(uint32_t)(addr))
#define REG32_FLOAT(addr) (*(volatile float *)(uint32_t)(addr)) #define REG32_FLOAT(addr) (*(volatile float *)(uint32_t)(addr))
/* registers definitions */ /* registers definitions */
#define FAC_X0BCFG REG32((FAC) + 0x00000000U) /*!< FAC X0 buffer configure register */ #define FAC_X0BCFG REG32((FAC) + 0x00000000U) /*!< FAC X0 buffer configure register */
#define FAC_X1BCFG REG32((FAC) + 0x00000004U) /*!< FAC X1 buffer configure register */ #define FAC_X1BCFG REG32((FAC) + 0x00000004U) /*!< FAC X1 buffer configure register */
@ -75,14 +75,14 @@ OF SUCH DAMAGE.
#define FAC_YBCFG_Y_WBEF BITS(24,25) /*!< watermark for buffer empty flag */ #define FAC_YBCFG_Y_WBEF BITS(24,25) /*!< watermark for buffer empty flag */
/* FAC_PARACFG */ /* FAC_PARACFG */
#define FAC_PARACFG_IPP BITS(0,7) /*!< input parameter IPP */ #define FAC_PARACFG_IPP BITS(0,7) /*!< input parameter IPP */
#define FAC_PARACFG_IPQ BITS(8,15) /*!< input parameter IPQ */ #define FAC_PARACFG_IPQ BITS(8,15) /*!< input parameter IPQ */
#define FAC_PARACFG_IPR BITS(16,23) /*!< input parameter IPR */ #define FAC_PARACFG_IPR BITS(16,23) /*!< input parameter IPR */
#define FAC_PARACFG_FUN BITS(24,30) /*!< function */ #define FAC_PARACFG_FUN BITS(24,30) /*!< function */
#define FAC_PARACFG_EXE BIT(31) /*!< execution */ #define FAC_PARACFG_EXE BIT(31) /*!< execution */
/* FAC_CTL */ /* FAC_CTL */
#define FAC_CTL_RIE BIT(0) /*!< read interrupt enable */ #define FAC_CTL_RIE BIT(0) /*!< read interrupt enable */
#define FAC_CTL_WIE BIT(1) /*!< write interrupt enable */ #define FAC_CTL_WIE BIT(1) /*!< write interrupt enable */
#define FAC_CTL_OFEIE BIT(2) /*!< overflow error interrupt enable */ #define FAC_CTL_OFEIE BIT(2) /*!< overflow error interrupt enable */
#define FAC_CTL_UFEIE BIT(3) /*!< underflow error interrupt enable */ #define FAC_CTL_UFEIE BIT(3) /*!< underflow error interrupt enable */
@ -95,7 +95,7 @@ OF SUCH DAMAGE.
#define FAC_CTL_RST BIT(16) /*!< reset FAC unit */ #define FAC_CTL_RST BIT(16) /*!< reset FAC unit */
/* FAC_STAT */ /* FAC_STAT */
#define FAC_STAT_YBEF BIT(0) /*!< Y buffer empty flag */ #define FAC_STAT_YBEF BIT(0) /*!< Y buffer empty flag */
#define FAC_STAT_X0BFF BIT(1) /*!< X0 buffer full flag */ #define FAC_STAT_X0BFF BIT(1) /*!< X0 buffer full flag */
#define FAC_STAT_OFEF BIT(8) /*!< overflow error flag */ #define FAC_STAT_OFEF BIT(8) /*!< overflow error flag */
#define FAC_STAT_UFEF BIT(9) /*!< underflow error flag */ #define FAC_STAT_UFEF BIT(9) /*!< underflow error flag */
@ -167,14 +167,14 @@ typedef struct
#define FAC_THRESHOLD_2 X0BCFG_X0_WBFF(1) /*!< full/empty flag when buffer less than 2 */ #define FAC_THRESHOLD_2 X0BCFG_X0_WBFF(1) /*!< full/empty flag when buffer less than 2 */
#define FAC_THRESHOLD_4 X0BCFG_X0_WBFF(2) /*!< full/empty flag when buffer less than 4 */ #define FAC_THRESHOLD_4 X0BCFG_X0_WBFF(2) /*!< full/empty flag when buffer less than 4 */
#define FAC_THRESHOLD_8 X0BCFG_X0_WBFF(3) /*!< full/empty flag when buffer less than 8 */ #define FAC_THRESHOLD_8 X0BCFG_X0_WBFF(3) /*!< full/empty flag when buffer less than 8 */
/* FAC clip function definitions */ /* FAC clip function definitions */
#define FAC_CP_DISABLE ((uint8_t)0x00U) /*!< clipping disabled */ #define FAC_CP_DISABLE ((uint8_t)0x00U) /*!< clipping disabled */
#define FAC_CP_ENABLE ((uint8_t)0x01U) /*!< clipping enabled */ #define FAC_CP_ENABLE ((uint8_t)0x01U) /*!< clipping enabled */
/* FAC function execution definitions */ /* FAC function execution definitions */
#define PARACFG_EXE(regval) (FAC_PARACFG_EXE & ((uint32_t)(regval) << 31)) #define PARACFG_EXE(regval) (FAC_PARACFG_EXE & ((uint32_t)(regval) << 31))
#define FAC_FUNC_START PARACFG_EXE(0) /*!< start execution function */ #define FAC_FUNC_START PARACFG_EXE(0) /*!< start execution function */
#define FAC_FUNC_STOP PARACFG_EXE(1) /*!< stop execution function */ #define FAC_FUNC_STOP PARACFG_EXE(1) /*!< stop execution function */
/* FAC DMA mdoe definitions */ /* FAC DMA mdoe definitions */
@ -189,7 +189,7 @@ typedef struct
#define FAC_INT_FLAG_STEF ((uint8_t)0x04U) /*!< saturation error interrupt flag */ #define FAC_INT_FLAG_STEF ((uint8_t)0x04U) /*!< saturation error interrupt flag */
#define FAC_INT_FLAG_GSTEF ((uint8_t)0x05U) /*!< gain saturation error interrupt flag */ #define FAC_INT_FLAG_GSTEF ((uint8_t)0x05U) /*!< gain saturation error interrupt flag */
/* FAC flag definitions */ /* FAC flag definitions */
#define FAC_FLAG_YBEF FAC_STAT_YBEF /*!< Y buffer empty flag */ #define FAC_FLAG_YBEF FAC_STAT_YBEF /*!< Y buffer empty flag */
#define FAC_FLAG_X0BFF FAC_STAT_X0BFF /*!< X0 buffer full flag */ #define FAC_FLAG_X0BFF FAC_STAT_X0BFF /*!< X0 buffer full flag */
#define FAC_FLAG_OFEF FAC_STAT_OFEF /*!< overflow error flag */ #define FAC_FLAG_OFEF FAC_STAT_OFEF /*!< overflow error flag */

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_fwdgt.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

40
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_gpio.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -67,7 +67,7 @@ OF SUCH DAMAGE.
/* bits definitions */ /* bits definitions */
/* GPIO_CTL */ /* GPIO_CTL */
#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ #define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */
#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ #define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */
#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ #define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */
#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ #define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */
@ -236,8 +236,8 @@ OF SUCH DAMAGE.
#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */ #define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */
#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */ #define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */
#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */ #define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */
/* GPIO_AFSEL1 */ /* GPIO_AFSEL1 */
#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */ #define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */
#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */ #define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */
#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */ #define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */
@ -381,9 +381,9 @@ typedef FlagStatus bit_status;
/* GPIO alternate function values */ /* GPIO alternate function values */
#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) #define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
#define GPIO_AFR_MASK(n) (0xFU << (4U * (n))) #define GPIO_AFR_MASK(n) (0xFU << (4U * (n)))
/* GPIO alternate function */ /* GPIO alternate function */
#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) #define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */ #define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */
#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */ #define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */
#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */ #define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */

36
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_hau.h
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@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -90,7 +90,7 @@ OF SUCH DAMAGE.
#define HAU_STAT_BUSY BIT(3) /*!< busy bit */ #define HAU_STAT_BUSY BIT(3) /*!< busy bit */
/* constants definitions */ /* constants definitions */
/* structure for initialization of the hau */ /* structure for initialization of the hau */
typedef struct typedef struct
{ {
uint32_t algo; /*!< algorithm selection */ uint32_t algo; /*!< algorithm selection */
@ -114,7 +114,7 @@ typedef struct
uint32_t hau_ctxs_bak[54]; /*!< backup of HAU_CTXSx registers */ uint32_t hau_ctxs_bak[54]; /*!< backup of HAU_CTXSx registers */
}hau_context_parameter_struct; }hau_context_parameter_struct;
/* hau_ctl register value */ /* hau_ctl register value */
#define HAU_ALGO_SHA1 ((uint32_t)0x00000000U) /*!< HAU function is SHA1 */ #define HAU_ALGO_SHA1 ((uint32_t)0x00000000U) /*!< HAU function is SHA1 */
#define HAU_ALGO_SHA224 HAU_CTL_ALGM_1 /*!< HAU function is SHA224 */ #define HAU_ALGO_SHA224 HAU_CTL_ALGM_1 /*!< HAU function is SHA224 */
#define HAU_ALGO_SHA256 (HAU_CTL_ALGM_1 | HAU_CTL_ALGM_0) /*!< HAU function is SHA256 */ #define HAU_ALGO_SHA256 (HAU_CTL_ALGM_1 | HAU_CTL_ALGM_0) /*!< HAU function is SHA256 */
@ -148,7 +148,7 @@ typedef struct
#define HAU_FLAG_CALCULATION_COMPLETE HAU_STAT_CCF /*!< digest calculation is completed */ #define HAU_FLAG_CALCULATION_COMPLETE HAU_STAT_CCF /*!< digest calculation is completed */
#define HAU_FLAG_DMA HAU_STAT_DMAS /*!< DMA is enabled (DMAE =1) or a transfer is processing */ #define HAU_FLAG_DMA HAU_STAT_DMAS /*!< DMA is enabled (DMAE =1) or a transfer is processing */
#define HAU_FLAG_BUSY HAU_STAT_BUSY /*!< data block is in process */ #define HAU_FLAG_BUSY HAU_STAT_BUSY /*!< data block is in process */
#define HAU_FLAG_INFIFO_NO_EMPTY HAU_CTL_DINE /*!< the input FIFO is not empty */ #define HAU_FLAG_INFIFO_NO_EMPTY HAU_CTL_DINE /*!< the input FIFO is not empty */
#define HAU_INT_FLAG_DATA_INPUT HAU_STAT_DIF /*!< there is enough space (16 bytes) in the input FIFO */ #define HAU_INT_FLAG_DATA_INPUT HAU_STAT_DIF /*!< there is enough space (16 bytes) in the input FIFO */
#define HAU_INT_FLAG_CALCULATION_COMPLETE HAU_STAT_CCF /*!< digest calculation is completed */ #define HAU_INT_FLAG_CALCULATION_COMPLETE HAU_STAT_CCF /*!< digest calculation is completed */

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_mdio.h
View File

@ -1,34 +1,34 @@
/*! /*!
\file gd32h7xx_mdio.h \file gd32h7xx_mdio.h
\brief definitions for the MDIO \brief definitions for the MDIO
\version 2024-01-05, V1.2.0, firmware for GD32H7xx \version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/ */
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

28
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_mdma.h
View File

@ -42,13 +42,13 @@ OF SUCH DAMAGE.
/* registers definitions */ /* registers definitions */
#define MDMA_GINTF REG32(MDMA + 0x00000000U) /*!< MDMA global interrupt flag register */ #define MDMA_GINTF REG32(MDMA + 0x00000000U) /*!< MDMA global interrupt flag register */
#define MDMA_CHXSTAT0(mdma_chx) REG32(MDMA + 0x00000040U + (0x40U * (mdma_chx))) /*!< MDMA channel x status register 0 */ #define MDMA_CHXSTAT0(mdma_chx) REG32(MDMA + 0x00000040U + (0x40U * (mdma_chx))) /*!< MDMA channel x status register 0 */
#define MDMA_CHXSTATC(mdma_chx) REG32(MDMA + 0x00000044U + (0x40U * (mdma_chx))) /*!< MDMA channel x status clear register */ #define MDMA_CHXSTATC(mdma_chx) REG32(MDMA + 0x00000044U + (0x40U * (mdma_chx))) /*!< MDMA channel x status clear register */
#define MDMA_CHXSTAT1(mdma_chx) REG32(MDMA + 0x00000048U + (0x40U * (mdma_chx))) /*!< MDMA channel x status register 1*/ #define MDMA_CHXSTAT1(mdma_chx) REG32(MDMA + 0x00000048U + (0x40U * (mdma_chx))) /*!< MDMA channel x status register 1*/
#define MDMA_CHXCTL0(mdma_chx) REG32(MDMA + 0x0000004CU + (0x40U * (mdma_chx))) /*!< MDMA channel x control register 0 */ #define MDMA_CHXCTL0(mdma_chx) REG32(MDMA + 0x0000004CU + (0x40U * (mdma_chx))) /*!< MDMA channel x control register 0 */
#define MDMA_CHXCFG(mdma_chx) REG32(MDMA + 0x00000050U + (0x40U * (mdma_chx))) /*!< MDMA channel x configure register */ #define MDMA_CHXCFG(mdma_chx) REG32(MDMA + 0x00000050U + (0x40U * (mdma_chx))) /*!< MDMA channel x configure register */
#define MDMA_CHXBTCFG(mdma_chx) REG32(MDMA + 0x00000054U + (0x40U * (mdma_chx))) /*!< MDMA channel x block transfer configure register */ #define MDMA_CHXBTCFG(mdma_chx) REG32(MDMA + 0x00000054U + (0x40U * (mdma_chx))) /*!< MDMA channel x block transfer configure register */
#define MDMA_CHXSADDR(mdma_chx) REG32(MDMA + 0x00000058U + (0x40U * (mdma_chx))) /*!< MDMA channel x source address register */ #define MDMA_CHXSADDR(mdma_chx) REG32(MDMA + 0x00000058U + (0x40U * (mdma_chx))) /*!< MDMA channel x source address register */
#define MDMA_CHXDADDR(mdma_chx) REG32(MDMA + 0x0000005CU + (0x40U * (mdma_chx))) /*!< MDMA channel x destination address register */ #define MDMA_CHXDADDR(mdma_chx) REG32(MDMA + 0x0000005CU + (0x40U * (mdma_chx))) /*!< MDMA channel x destination address register */
#define MDMA_CHXMBADDRU(mdma_chx) REG32(MDMA + 0x00000060U + (0x40U * (mdma_chx))) /*!< MDMA channel x multi-block address update register */ #define MDMA_CHXMBADDRU(mdma_chx) REG32(MDMA + 0x00000060U + (0x40U * (mdma_chx))) /*!< MDMA channel x multi-block address update register */
@ -145,23 +145,23 @@ OF SUCH DAMAGE.
#define MDMA_CHXMBADDRU_SADDRUV BITS(0,15) /*!< source address update value */ #define MDMA_CHXMBADDRU_SADDRUV BITS(0,15) /*!< source address update value */
#define MDMA_CHXMBADDRU_DADDRUV BITS(16,31) /*!< destination address update value */ #define MDMA_CHXMBADDRU_DADDRUV BITS(16,31) /*!< destination address update value */
/* MDMA_CHxLADDR,x=0..15 */ /* MDMA_CHxLADDR,x=0..15 */
#define MDMA_CHXLADDR_LADDR BITS(0,31) /*!< link address */ #define MDMA_CHXLADDR_LADDR BITS(0,31) /*!< link address */
/* MDMA_CHxCTL1,x=0..15 */ /* MDMA_CHxCTL1,x=0..15 */
#define MDMA_CHXCTL1_TRIGSEL BITS(0,5) /*!< trigger select */ #define MDMA_CHXCTL1_TRIGSEL BITS(0,5) /*!< trigger select */
#define MDMA_CHXCTL1_SBSEL BIT(16) /*!< source bus select */ #define MDMA_CHXCTL1_SBSEL BIT(16) /*!< source bus select */
#define MDMA_CHXCTL1_DBSEL BIT(17) /*!< destination bus select */ #define MDMA_CHXCTL1_DBSEL BIT(17) /*!< destination bus select */
/* MDMA_CHxMADDR,x=0..15 */ /* MDMA_CHxMADDR,x=0..15 */
#define MDMA_CHXMADDR_MADDR BITS(0,31) /*!< mask address */ #define MDMA_CHXMADDR_MADDR BITS(0,31) /*!< mask address */
/* MDMA_CHxMDATA,x=0..15 */ /* MDMA_CHxMDATA,x=0..15 */
#define MDMA_CHXMDATA_MDATA BITS(0,31) /*!< mask data */ #define MDMA_CHXMDATA_MDATA BITS(0,31) /*!< mask data */
/* constants definitions */ /* constants definitions */
/* MDMA configuration structure definition */ /* MDMA configuration structure definition */
typedef struct { typedef struct {
uint32_t request; /*!< specifies the MDMA request */ uint32_t request; /*!< specifies the MDMA request */
uint32_t trans_trig_mode; /*!< specifies the trigger transfer mode */ uint32_t trans_trig_mode; /*!< specifies the trigger transfer mode */
uint32_t priority; /*!< specifies the software priority for the MDMA channelx */ uint32_t priority; /*!< specifies the software priority for the MDMA channelx */
@ -357,15 +357,15 @@ typedef enum {
#define MDMA_SOURCE_AXI ((uint32_t)0x00000000U) /*!< source bus of channel x is the system bus or AXI bus */ #define MDMA_SOURCE_AXI ((uint32_t)0x00000000U) /*!< source bus of channel x is the system bus or AXI bus */
#define MDMA_SOURCE_AHB_TCM MDMA_CHXCTL1_SBSEL /*!< source bus of channel x is AHB bus or TCM */ #define MDMA_SOURCE_AHB_TCM MDMA_CHXCTL1_SBSEL /*!< source bus of channel x is AHB bus or TCM */
/* destination bus select */ /* destination bus select */
#define MDMA_DESTINATION_AXI ((uint32_t)0x00000000U) /*!< destination bus of channel x is the system bus or AXI bus */ #define MDMA_DESTINATION_AXI ((uint32_t)0x00000000U) /*!< destination bus of channel x is the system bus or AXI bus */
#define MDMA_DESTINATION_AHB_TCM MDMA_CHXCTL1_DBSEL /*!< destination bus of channel x is AHB bus or TCM */ #define MDMA_DESTINATION_AHB_TCM MDMA_CHXCTL1_DBSEL /*!< destination bus of channel x is AHB bus or TCM */
/* MDMA access error direction */ /* MDMA access error direction */
#define MDMA_READ_ERROR ((uint32_t)0x00000000U) /*!< read access error */ #define MDMA_READ_ERROR ((uint32_t)0x00000000U) /*!< read access error */
#define MDMA_WRITE_ERROR MDMA_CHXSTAT1_TERRD /*!< write access error */ #define MDMA_WRITE_ERROR MDMA_CHXSTAT1_TERRD /*!< write access error */
/* MDMA bufferable write mode */ /* MDMA bufferable write mode */
#define MDMA_BUFFERABLE_WRITE_DISABLE ((uint32_t)0x00000000U) /*!< diable bufferable write mode */ #define MDMA_BUFFERABLE_WRITE_DISABLE ((uint32_t)0x00000000U) /*!< diable bufferable write mode */
#define MDMA_BUFFERABLE_WRITE_ENABLE MDMA_CHXCFG_BWMOD /*!< enable bufferable write mode */ #define MDMA_BUFFERABLE_WRITE_ENABLE MDMA_CHXCFG_BWMOD /*!< enable bufferable write mode */
@ -382,14 +382,14 @@ typedef enum {
#define MDMA_FLAG_ASERR (MDMA_CHXSTAT1_ASERR | STAT1_FLAG) /*!< address and size error flag */ #define MDMA_FLAG_ASERR (MDMA_CHXSTAT1_ASERR | STAT1_FLAG) /*!< address and size error flag */
#define MDMA_FLAG_BZERR (MDMA_CHXSTAT1_BZERR | STAT1_FLAG) /*!< block size error flag */ #define MDMA_FLAG_BZERR (MDMA_CHXSTAT1_BZERR | STAT1_FLAG) /*!< block size error flag */
/* MDMA interrupt */ /* MDMA interrupt */
#define MDMA_INT_ERR MDMA_CHXCTL0_ERRIE /*!< transfer error interrupt */ #define MDMA_INT_ERR MDMA_CHXCTL0_ERRIE /*!< transfer error interrupt */
#define MDMA_INT_CHTC MDMA_CHXCTL0_CHTCIE /*!< channel transfer complete interrupt */ #define MDMA_INT_CHTC MDMA_CHXCTL0_CHTCIE /*!< channel transfer complete interrupt */
#define MDMA_INT_MBTC MDMA_CHXCTL0_MBTCIE /*!< multi-block transfer complete interrupt */ #define MDMA_INT_MBTC MDMA_CHXCTL0_MBTCIE /*!< multi-block transfer complete interrupt */
#define MDMA_INT_BTC MDMA_CHXCTL0_BTCIE /*!< block transfer complete interrupt */ #define MDMA_INT_BTC MDMA_CHXCTL0_BTCIE /*!< block transfer complete interrupt */
#define MDMA_INT_TC MDMA_CHXCTL0_TCIE /*!< buffer transfer complete interrupt */ #define MDMA_INT_TC MDMA_CHXCTL0_TCIE /*!< buffer transfer complete interrupt */
/* MDMA interrupt flags */ /* MDMA interrupt flags */
#define MDMA_INT_FLAG_ERR MDMA_CHXSTAT0_ERR /*!< transfer error interrupt flag */ #define MDMA_INT_FLAG_ERR MDMA_CHXSTAT0_ERR /*!< transfer error interrupt flag */
#define MDMA_INT_FLAG_CHTCF MDMA_CHXSTAT0_CHTCF /*!< channel transfer complete interrupt flag */ #define MDMA_INT_FLAG_CHTCF MDMA_CHXSTAT0_CHTCF /*!< channel transfer complete interrupt flag */
#define MDMA_INT_FLAG_MBTCF MDMA_CHXSTAT0_MBTCF /*!< multi-block transfer complete interrupt flag */ #define MDMA_INT_FLAG_MBTCF MDMA_CHXSTAT0_MBTCF /*!< multi-block transfer complete interrupt flag */

64
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_ospi.h
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@ -285,69 +285,69 @@ typedef struct {
/* OSPI FIFO threshold level set */ /* OSPI FIFO threshold level set */
#define OSPI_FTL(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) #define OSPI_FTL(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U))
#define OSPI_FIFO_THRESHOLD_1 OSPI_FTL(0) /*!< in indirect write mode, there are 1 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_1 OSPI_FTL(0) /*!< in indirect write mode, there are 1 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 1 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 1 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_2 OSPI_FTL(1) /*!< in indirect write mode, there are 2 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_2 OSPI_FTL(1) /*!< in indirect write mode, there are 2 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 2 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 2 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_3 OSPI_FTL(2) /*!< in indirect write mode, there are 3 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_3 OSPI_FTL(2) /*!< in indirect write mode, there are 3 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 3 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 3 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_4 OSPI_FTL(3) /*!< in indirect write mode, there are 4 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_4 OSPI_FTL(3) /*!< in indirect write mode, there are 4 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 4 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 4 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_5 OSPI_FTL(4) /*!< in indirect write mode, there are 5 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_5 OSPI_FTL(4) /*!< in indirect write mode, there are 5 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 5 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 5 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_6 OSPI_FTL(5) /*!< in indirect write mode, there are 6 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_6 OSPI_FTL(5) /*!< in indirect write mode, there are 6 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 6 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 6 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_7 OSPI_FTL(6) /*!< in indirect write mode, there are 7 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_7 OSPI_FTL(6) /*!< in indirect write mode, there are 7 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 7 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 7 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_8 OSPI_FTL(7) /*!< in indirect write mode, there are 8 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_8 OSPI_FTL(7) /*!< in indirect write mode, there are 8 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 8 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 8 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_9 OSPI_FTL(8) /*!< in indirect write mode, there are 9 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_9 OSPI_FTL(8) /*!< in indirect write mode, there are 9 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 9 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 9 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_10 OSPI_FTL(9) /*!< in indirect write mode, there are 10 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_10 OSPI_FTL(9) /*!< in indirect write mode, there are 10 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 10 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 10 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_11 OSPI_FTL(10) /*!< in indirect write mode, there are 11 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_11 OSPI_FTL(10) /*!< in indirect write mode, there are 11 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 11 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 11 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_12 OSPI_FTL(11) /*!< in indirect write mode, there are 12 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_12 OSPI_FTL(11) /*!< in indirect write mode, there are 12 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 12 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 12 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_13 OSPI_FTL(12) /*!< in indirect write mode, there are 13 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_13 OSPI_FTL(12) /*!< in indirect write mode, there are 13 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 13 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 13 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_14 OSPI_FTL(13) /*!< in indirect write mode, there are 14 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_14 OSPI_FTL(13) /*!< in indirect write mode, there are 14 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 14 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 14 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_15 OSPI_FTL(14) /*!< in indirect write mode, there are 15 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_15 OSPI_FTL(14) /*!< in indirect write mode, there are 15 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 15 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 15 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_16 OSPI_FTL(15) /*!< in indirect write mode, there are 16 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_16 OSPI_FTL(15) /*!< in indirect write mode, there are 16 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 16 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 16 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_17 OSPI_FTL(16) /*!< in indirect write mode, there are 17 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_17 OSPI_FTL(16) /*!< in indirect write mode, there are 17 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 17 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 17 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_18 OSPI_FTL(17) /*!< in indirect write mode, there are 18 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_18 OSPI_FTL(17) /*!< in indirect write mode, there are 18 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 18 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 18 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_19 OSPI_FTL(18) /*!< in indirect write mode, there are 19 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_19 OSPI_FTL(18) /*!< in indirect write mode, there are 19 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 19 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 19 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_20 OSPI_FTL(19) /*!< in indirect write mode, there are 20 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_20 OSPI_FTL(19) /*!< in indirect write mode, there are 20 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 20 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 20 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_21 OSPI_FTL(20) /*!< in indirect write mode, there are 21 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_21 OSPI_FTL(20) /*!< in indirect write mode, there are 21 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 21 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 21 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_22 OSPI_FTL(21) /*!< in indirect write mode, there are 22 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_22 OSPI_FTL(21) /*!< in indirect write mode, there are 22 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 22 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 22 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_23 OSPI_FTL(22) /*!< in indirect write mode, there are 23 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_23 OSPI_FTL(22) /*!< in indirect write mode, there are 23 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 23 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 23 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_24 OSPI_FTL(23) /*!< in indirect write mode, there are 24 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_24 OSPI_FTL(23) /*!< in indirect write mode, there are 24 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 24 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 24 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_25 OSPI_FTL(24) /*!< in indirect write mode, there are 25 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_25 OSPI_FTL(24) /*!< in indirect write mode, there are 25 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 25 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 25 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_26 OSPI_FTL(25) /*!< in indirect write mode, there are 26 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_26 OSPI_FTL(25) /*!< in indirect write mode, there are 26 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 26 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 26 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_27 OSPI_FTL(26) /*!< in indirect write mode, there are 27 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_27 OSPI_FTL(26) /*!< in indirect write mode, there are 27 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 27 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 27 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_28 OSPI_FTL(27) /*!< in indirect write mode, there are 28 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_28 OSPI_FTL(27) /*!< in indirect write mode, there are 28 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 28 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 28 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_29 OSPI_FTL(28) /*!< in indirect write mode, there are 29 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_29 OSPI_FTL(28) /*!< in indirect write mode, there are 29 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 29 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 29 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_30 OSPI_FTL(29) /*!< in indirect write mode, there are 30 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_30 OSPI_FTL(29) /*!< in indirect write mode, there are 30 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 30 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 30 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_31 OSPI_FTL(30) /*!< in indirect write mode, there are 31 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_31 OSPI_FTL(30) /*!< in indirect write mode, there are 31 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 31 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 31 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_32 OSPI_FTL(31) /*!< in indirect write mode, there are 32 or more free bytes available to be written to the FIFO, #define OSPI_FIFO_THRESHOLD_32 OSPI_FTL(31) /*!< in indirect write mode, there are 32 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 32 or more free bytes available to be read from the FIFO */ in indirect read mode, there are 32 or more free bytes available to be read from the FIFO */
/* OSPI chip select high cycle */ /* OSPI chip select high cycle */

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_ospim.h
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@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_pmu.h
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@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

42
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_rameccmu.h
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@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -84,9 +84,9 @@ OF SUCH DAMAGE.
#define RAMECCMU_INT_GEIE BIT(0) /*!< global ECC interrupt enable */ #define RAMECCMU_INT_GEIE BIT(0) /*!< global ECC interrupt enable */
#define RAMECCMU_INT_GESERRIE BIT(1) /*!< global ECC single error interrupt enable */ #define RAMECCMU_INT_GESERRIE BIT(1) /*!< global ECC single error interrupt enable */
#define RAMECCMU_INT_GEDERRIE BIT(2) /*!< global ECC double error interrupt enable */ #define RAMECCMU_INT_GEDERRIE BIT(2) /*!< global ECC double error interrupt enable */
#define RAMECCMU_INT_GEDERRBWIE BIT(3) /*!< global ECC double error on byte write interrupt enable */ #define RAMECCMU_INT_GEDERRBWIE BIT(3) /*!< global ECC double error on byte write interrupt enable */
/* RAMECCMU_MxCTL */ /* RAMECCMU_MxCTL */
#define RAMECCMU_MXCTL_ECCSERRIE BIT(2) /*!< ECC single error interrupt enable */ #define RAMECCMU_MXCTL_ECCSERRIE BIT(2) /*!< ECC single error interrupt enable */
#define RAMECCMU_MXCTL_ECCDERRIE BIT(3) /*!< ECC double error interrupt enable */ #define RAMECCMU_MXCTL_ECCDERRIE BIT(3) /*!< ECC double error interrupt enable */
#define RAMECCMU_MXCTL_ECCDERRBWIE BIT(4) /*!< ECC double error on byte write interrupt enable */ #define RAMECCMU_MXCTL_ECCDERRBWIE BIT(4) /*!< ECC double error on byte write interrupt enable */
@ -101,17 +101,17 @@ OF SUCH DAMAGE.
#define RAMECCMU_MXFADDR_ECCFADDR BITS(0,31) /*!< ECC error failing address */ #define RAMECCMU_MXFADDR_ECCFADDR BITS(0,31) /*!< ECC error failing address */
/* RAMECCMU_MxFDL */ /* RAMECCMU_MxFDL */
#define RAMECCMU_MXFDL_ECCFDL BITS(0,31) /*!< ECC failing data low bits */ #define RAMECCMU_MXFDL_ECCFDL BITS(0,31) /*!< ECC failing data low bits */
/* RAMECCMU_MxFDH */ /* RAMECCMU_MxFDH */
#define RAMECCMU_MXFDH_ECCFDH BITS(0,31) /*!< ECC failing data high bits */ #define RAMECCMU_MXFDH_ECCFDH BITS(0,31) /*!< ECC failing data high bits */
/* RAMECCMU_MxFECODE */ /* RAMECCMU_MxFECODE */
#define RAMECCMU_MXFECODE_ECCFECODE BITS(0,31) /*!< ECC failing error code */ #define RAMECCMU_MXFECODE_ECCFECODE BITS(0,31) /*!< ECC failing error code */
/* constants definitions */ /* constants definitions */
/* RAMECCMU monitor select */ /* RAMECCMU monitor select */
typedef enum typedef enum
{ {
RAMECCMU0_MONITOR0 = 0x00U, /*!< RAMECCMU0 monitor 0 */ RAMECCMU0_MONITOR0 = 0x00U, /*!< RAMECCMU0 monitor 0 */
RAMECCMU0_MONITOR1 = 0x01U, /*!< RAMECCMU0 monitor 1 */ RAMECCMU0_MONITOR1 = 0x01U, /*!< RAMECCMU0 monitor 1 */

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_rtc.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -234,7 +234,7 @@ OF SUCH DAMAGE.
/* RTC_CFG */ /* RTC_CFG */
#define RTC_CFG_OUT2EN BIT(1) /*!< RTC_OUT is output on PB2 or PC13 */ #define RTC_CFG_OUT2EN BIT(1) /*!< RTC_OUT is output on PB2 or PC13 */
#define RTC_CFG_ALRMOUTTYPE BIT(0) /*!< RTC_ALARM output is Push-pull output type */ #define RTC_CFG_ALRMOUTTYPE BIT(0) /*!< RTC_ALARM output is Push-pull output type */
/* RTC_BKP0 */ /* RTC_BKP0 */
#define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */ #define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */

36
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_spi.h
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@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -194,7 +194,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* SPI and I2S parameter struct definitions */ /* SPI and I2S parameter struct definitions */
typedef struct typedef struct
{ {
uint32_t device_mode; /*!< SPI master or slave */ uint32_t device_mode; /*!< SPI master or slave */
uint32_t trans_mode; /*!< SPI transtype */ uint32_t trans_mode; /*!< SPI transtype */
uint32_t data_size; /*!< SPI data frame size */ uint32_t data_size; /*!< SPI data frame size */
@ -460,7 +460,7 @@ typedef struct
#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ #define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ #define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
/* SPI DMA constants definitions */ /* SPI DMA constants definitions */
#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ #define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ #define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
@ -496,7 +496,7 @@ typedef struct
#define SPI_I2S_INT_FLAG_SPD ((uint8_t)0x0BU) /*!< suspend interrupt flag */ #define SPI_I2S_INT_FLAG_SPD ((uint8_t)0x0BU) /*!< suspend interrupt flag */
#define SPI_I2S_INT_FLAG_TC ((uint8_t)0x0CU) /*!< TXFIFO clear interrupt flag */ #define SPI_I2S_INT_FLAG_TC ((uint8_t)0x0CU) /*!< TXFIFO clear interrupt flag */
/* SPI/I2S flag definitions */ /* SPI/I2S flag definitions */
#define SPI_FLAG_RP SPI_STAT_RP /*!< RP flag */ #define SPI_FLAG_RP SPI_STAT_RP /*!< RP flag */
#define SPI_FLAG_TP SPI_STAT_TP /*!< TP flag */ #define SPI_FLAG_TP SPI_STAT_TP /*!< TP flag */
#define SPI_FLAG_DP SPI_STAT_DP /*!< DP flag */ #define SPI_FLAG_DP SPI_STAT_DP /*!< DP flag */

46
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_tli.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -191,7 +191,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* TLI parameter struct definitions */ /* TLI parameter struct definitions */
typedef struct typedef struct
{ {
uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */ uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */
uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */ uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */
uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */ uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */
@ -207,7 +207,7 @@ typedef struct
uint32_t signalpolarity_vs; /*!< vertical pulse polarity selection */ uint32_t signalpolarity_vs; /*!< vertical pulse polarity selection */
uint32_t signalpolarity_de; /*!< data enable polarity selection */ uint32_t signalpolarity_de; /*!< data enable polarity selection */
uint32_t signalpolarity_pixelck; /*!< pixel clock polarity selection */ uint32_t signalpolarity_pixelck; /*!< pixel clock polarity selection */
}tli_parameter_struct; }tli_parameter_struct;
/* TLI layer parameter struct definitions */ /* TLI layer parameter struct definitions */
typedef struct typedef struct
@ -228,7 +228,7 @@ typedef struct
uint16_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */ uint16_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */
uint16_t layer_frame_line_length; /*!< frame line length */ uint16_t layer_frame_line_length; /*!< frame line length */
uint16_t layer_frame_total_line_number; /*!< frame total line number */ uint16_t layer_frame_total_line_number; /*!< frame total line number */
}tli_layer_parameter_struct; }tli_layer_parameter_struct;
/* TLI layer LUT parameter struct definitions */ /* TLI layer LUT parameter struct definitions */
typedef struct typedef struct
@ -237,10 +237,10 @@ typedef struct
uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */ uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */
uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */ uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */
uint8_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */ uint8_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */
}tli_layer_lut_parameter_struct; }tli_layer_lut_parameter_struct;
/* packeted pixel format */ /* packeted pixel format */
typedef enum typedef enum
{ {
LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */ LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */
LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */ LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */
@ -312,7 +312,7 @@ typedef enum
/* initialization functions, TLI enable or disable, TLI reload mode configuration */ /* initialization functions, TLI enable or disable, TLI reload mode configuration */
/* deinitialize TLI registers */ /* deinitialize TLI registers */
void tli_deinit(void); void tli_deinit(void);
/* initialize the parameters of TLI parameter structure with the default values, it is suggested /* initialize the parameters of TLI parameter structure with the default values, it is suggested
that call this function after a tli_parameter_struct structure is defined */ that call this function after a tli_parameter_struct structure is defined */
void tli_struct_para_init(tli_parameter_struct *tli_struct); void tli_struct_para_init(tli_parameter_struct *tli_struct);
/* initialize TLI */ /* initialize TLI */
@ -327,14 +327,14 @@ void tli_disable(void);
void tli_reload_config(uint8_t reload_mod); void tli_reload_config(uint8_t reload_mod);
/* TLI layer configuration functions */ /* TLI layer configuration functions */
/* initialize the parameters of TLI layer structure with the default values, it is suggested /* initialize the parameters of TLI layer structure with the default values, it is suggested
that call this function after a tli_layer_parameter_struct structure is defined */ that call this function after a tli_layer_parameter_struct structure is defined */
void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct); void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct);
/* initialize TLI layer */ /* initialize TLI layer */
void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct); void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct);
/* reconfigure window position */ /* reconfigure window position */
void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t offset_y); void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t offset_y);
/* initialize the parameters of TLI layer LUT structure with the default values, it is suggested /* initialize the parameters of TLI layer LUT structure with the default values, it is suggested
that call this function after a tli_layer_lut_parameter_struct structure is defined */ that call this function after a tli_layer_lut_parameter_struct structure is defined */
void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct); void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct);
/* initialize TLI layer LUT */ /* initialize TLI layer LUT */

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_tmu.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_trigsel.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_trng.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -136,7 +136,7 @@ typedef enum
/* trng status flag */ /* trng status flag */
typedef enum typedef enum
{ {
TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */ TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */
TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */ TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */
TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */ TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_vref.h
View File

@ -1,34 +1,34 @@
/*! /*!
\file gd32h7xx_vref.h \file gd32h7xx_vref.h
\brief definitions for the VREF \brief definitions for the VREF
\version 2024-01-05, V1.2.0, firmware for GD32H7xx \version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/ */
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_wwdgt.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

174
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_adc.c
View File

@ -74,7 +74,8 @@ OF SUCH DAMAGE.
*/ */
void adc_deinit(uint32_t adc_periph) void adc_deinit(uint32_t adc_periph)
{ {
switch(adc_periph) { switch(adc_periph)
{
case ADC0: case ADC0:
rcu_periph_reset_enable(RCU_ADC0RST); rcu_periph_reset_enable(RCU_ADC0RST);
rcu_periph_reset_disable(RCU_ADC0RST); rcu_periph_reset_disable(RCU_ADC0RST);
@ -121,7 +122,8 @@ void adc_deinit(uint32_t adc_periph)
*/ */
void adc_clock_config(uint32_t adc_periph, uint32_t prescaler) void adc_clock_config(uint32_t adc_periph, uint32_t prescaler)
{ {
if(ADC2 == adc_periph) { if(ADC2 == adc_periph)
{
ADC_SYNCCTL(ADC2) &= ~((uint32_t)(ADC_SYNCCTL_ADCCK | ADC_SYNCCTL_ADCSCK)); ADC_SYNCCTL(ADC2) &= ~((uint32_t)(ADC_SYNCCTL_ADCCK | ADC_SYNCCTL_ADCSCK));
ADC_SYNCCTL(ADC2) |= (uint32_t)prescaler; ADC_SYNCCTL(ADC2) |= (uint32_t)prescaler;
} else { } else {
@ -144,29 +146,36 @@ void adc_clock_config(uint32_t adc_periph, uint32_t prescaler)
*/ */
void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue)
{ {
if(ENABLE == newvalue) { if(ENABLE == newvalue)
if(RESET != (function & ADC_SCAN_MODE)) { {
if(RESET != (function & ADC_SCAN_MODE))
{
/* enable scan mode */ /* enable scan mode */
ADC_CTL0(adc_periph) |= (uint32_t)ADC_SCAN_MODE; ADC_CTL0(adc_periph) |= (uint32_t)ADC_SCAN_MODE;
} }
if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) { if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO))
{
/* enable inserted channel group convert automatically */ /* enable inserted channel group convert automatically */
ADC_CTL0(adc_periph) |= (uint32_t)ADC_INSERTED_CHANNEL_AUTO; ADC_CTL0(adc_periph) |= (uint32_t)ADC_INSERTED_CHANNEL_AUTO;
} }
if(RESET != (function & ADC_CONTINUOUS_MODE)) { if(RESET != (function & ADC_CONTINUOUS_MODE))
{
/* enable continuous mode */ /* enable continuous mode */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CONTINUOUS_MODE; ADC_CTL1(adc_periph) |= (uint32_t)ADC_CONTINUOUS_MODE;
} }
} else { } else {
if(RESET != (function & ADC_SCAN_MODE)) { if(RESET != (function & ADC_SCAN_MODE))
{
/* disable scan mode */ /* disable scan mode */
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_SCAN_MODE); ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_SCAN_MODE);
} }
if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) { if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO))
{
/* disable inserted channel group convert automatically */ /* disable inserted channel group convert automatically */
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_INSERTED_CHANNEL_AUTO); ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_INSERTED_CHANNEL_AUTO);
} }
if(RESET != (function & ADC_CONTINUOUS_MODE)) { if(RESET != (function & ADC_CONTINUOUS_MODE))
{
/* disable continuous mode */ /* disable continuous mode */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CONTINUOUS_MODE); ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CONTINUOUS_MODE);
} }
@ -185,10 +194,12 @@ void adc_special_function_config(uint32_t adc_periph, uint32_t function, Control
*/ */
void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
{ {
if(ADC_DATAALIGN_RIGHT == data_alignment) { if(ADC_DATAALIGN_RIGHT == data_alignment)
{
/* LSB alignment */ /* LSB alignment */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
} else if(ADC_DATAALIGN_LEFT == data_alignment) { } else if(ADC_DATAALIGN_LEFT == data_alignment)
{
/* MSB alignment */ /* MSB alignment */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_DAL; ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_DAL;
} else { } else {
@ -204,7 +215,8 @@ void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
*/ */
void adc_enable(uint32_t adc_periph) void adc_enable(uint32_t adc_periph)
{ {
if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)) { if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON))
{
/* enable ADC */ /* enable ADC */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
} }
@ -234,10 +246,12 @@ void adc_disable(uint32_t adc_periph)
*/ */
void adc_calibration_mode_config(uint32_t adc_periph, uint32_t clb_mode) void adc_calibration_mode_config(uint32_t adc_periph, uint32_t clb_mode)
{ {
if(ADC_CALIBRATION_OFFSET_MISMATCH == clb_mode) { if(ADC_CALIBRATION_OFFSET_MISMATCH == clb_mode)
{
/* offset and mismatch mode */ /* offset and mismatch mode */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_CALMOD); ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_CALMOD);
} else if(ADC_CALIBRATION_OFFSET == clb_mode) { } else if(ADC_CALIBRATION_OFFSET == clb_mode)
{
/* offset mode */ /* offset mode */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_CALMOD; ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_CALMOD;
} else { } else {
@ -276,12 +290,14 @@ void adc_calibration_enable(uint32_t adc_periph)
/* reset the selected ADC calibration registers */ /* reset the selected ADC calibration registers */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_RSTCLB; ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_RSTCLB;
/* check the RSTCLB bit state */ /* check the RSTCLB bit state */
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) { while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB))
{
} }
/* enable ADC calibration process */ /* enable ADC calibration process */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_CLB; ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_CLB;
/* check the CLB bit state */ /* check the CLB bit state */
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) { while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB))
{
} }
} }
@ -302,14 +318,17 @@ void adc_resolution_config(uint32_t adc_periph, uint32_t resolution)
{ {
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DRES); ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DRES);
if(ADC2 == adc_periph) { if(ADC2 == adc_periph)
if(ADC_RESOLUTION_14B == resolution) { {
if(ADC_RESOLUTION_14B == resolution)
{
/* illegal parameters */ /* illegal parameters */
} else { } else {
ADC_CTL0(adc_periph) |= (uint32_t)CTL0_DRES(resolution - 1U); ADC_CTL0(adc_periph) |= (uint32_t)CTL0_DRES(resolution - 1U);
} }
} else { } else {
if(ADC_RESOLUTION_6B == resolution) { if(ADC_RESOLUTION_6B == resolution)
{
/* illegal parameters */ /* illegal parameters */
} else { } else {
ADC_CTL0(adc_periph) |= (uint32_t)CTL0_DRES(resolution); ADC_CTL0(adc_periph) |= (uint32_t)CTL0_DRES(resolution);
@ -331,7 +350,8 @@ void adc_resolution_config(uint32_t adc_periph, uint32_t resolution)
*/ */
void adc_internal_channel_config(uint32_t internal_channel, ControlStatus newvalue) void adc_internal_channel_config(uint32_t internal_channel, ControlStatus newvalue)
{ {
if(ENABLE == newvalue) { if(ENABLE == newvalue)
{
ADC_CTL1(ADC2) |= (uint32_t)internal_channel; ADC_CTL1(ADC2) |= (uint32_t)internal_channel;
} else { } else {
ADC_CTL1(ADC2) &= ~((uint32_t)internal_channel); ADC_CTL1(ADC2) &= ~((uint32_t)internal_channel);
@ -425,11 +445,13 @@ void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_grou
{ {
/* disable discontinuous mode of regular & inserted channel */ /* disable discontinuous mode of regular & inserted channel */
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
switch(adc_channel_group) { switch(adc_channel_group)
{
case ADC_REGULAR_CHANNEL: case ADC_REGULAR_CHANNEL:
/* config the number of conversions in discontinuous mode */ /* config the number of conversions in discontinuous mode */
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
if((length <= 8U) && (length >= 1U)) { if((length <= 8U) && (length >= 1U))
{
ADC_CTL0(adc_periph) |= CTL0_DISNUM((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); ADC_CTL0(adc_periph) |= CTL0_DISNUM((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
} }
/* enable regular channel group discontinuous mode */ /* enable regular channel group discontinuous mode */
@ -461,15 +483,18 @@ void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_grou
*/ */
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
{ {
switch(adc_channel_group) { switch(adc_channel_group)
{
case ADC_REGULAR_CHANNEL: case ADC_REGULAR_CHANNEL:
if((length >= 1U) && (length <= 16U)) { if((length >= 1U) && (length <= 16U))
{
ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
} }
break; break;
case ADC_INSERTED_CHANNEL: case ADC_INSERTED_CHANNEL:
if((length >= 1U) && (length <= 4U)) { if((length >= 1U) && (length <= 4U))
{
ADC_ISQ0(adc_periph) &= ~((uint32_t)ADC_ISQ0_IL); ADC_ISQ0(adc_periph) &= ~((uint32_t)ADC_ISQ0_IL);
ADC_ISQ0(adc_periph) |= ISQ0_IL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); ADC_ISQ0(adc_periph) |= ISQ0_IL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
} }
@ -495,14 +520,16 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
uint32_t rsq; uint32_t rsq;
/* configure ADC regular sequence */ /* configure ADC regular sequence */
if(rank < ADC_REGULAR_CHANNEL_RANK_ONE) { if(rank < ADC_REGULAR_CHANNEL_RANK_ONE)
{
/* the regular group sequence rank is smaller than one */ /* the regular group sequence rank is smaller than one */
rsq = ADC_RSQ8(adc_periph); rsq = ADC_RSQ8(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rank))); rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rank)));
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
rank)); rank));
ADC_RSQ8(adc_periph) = rsq; ADC_RSQ8(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_THREE) { } else if(rank < ADC_REGULAR_CHANNEL_RANK_THREE)
{
/* the regular group sequence rank is smaller than three */ /* the regular group sequence rank is smaller than three */
rsq = ADC_RSQ7(adc_periph); rsq = ADC_RSQ7(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -510,7 +537,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_ONE))); (rank - ADC_REGULAR_CHANNEL_RANK_ONE)));
ADC_RSQ7(adc_periph) = rsq; ADC_RSQ7(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_FIVE) { } else if(rank < ADC_REGULAR_CHANNEL_RANK_FIVE)
{
/* the regular group sequence rank is smaller than five */ /* the regular group sequence rank is smaller than five */
rsq = ADC_RSQ6(adc_periph); rsq = ADC_RSQ6(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -518,7 +546,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_THREE))); (rank - ADC_REGULAR_CHANNEL_RANK_THREE)));
ADC_RSQ6(adc_periph) = rsq; ADC_RSQ6(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_SEVEN) { } else if(rank < ADC_REGULAR_CHANNEL_RANK_SEVEN)
{
/* the regular group sequence rank is smaller than seven */ /* the regular group sequence rank is smaller than seven */
rsq = ADC_RSQ5(adc_periph); rsq = ADC_RSQ5(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -526,7 +555,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_FIVE))); (rank - ADC_REGULAR_CHANNEL_RANK_FIVE)));
ADC_RSQ5(adc_periph) = rsq; ADC_RSQ5(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_NINE) { } else if(rank < ADC_REGULAR_CHANNEL_RANK_NINE)
{
/* the regular group sequence rank is smaller than nine */ /* the regular group sequence rank is smaller than nine */
rsq = ADC_RSQ4(adc_periph); rsq = ADC_RSQ4(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -534,7 +564,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_SEVEN))); (rank - ADC_REGULAR_CHANNEL_RANK_SEVEN)));
ADC_RSQ4(adc_periph) = rsq; ADC_RSQ4(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_ELEVEN) { } else if(rank < ADC_REGULAR_CHANNEL_RANK_ELEVEN)
{
/* the regular group sequence rank is smaller than eleven */ /* the regular group sequence rank is smaller than eleven */
rsq = ADC_RSQ3(adc_periph); rsq = ADC_RSQ3(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -542,7 +573,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_NINE))); (rank - ADC_REGULAR_CHANNEL_RANK_NINE)));
ADC_RSQ3(adc_periph) = rsq; ADC_RSQ3(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_THIRTEEN) { } else if(rank < ADC_REGULAR_CHANNEL_RANK_THIRTEEN)
{
/* the regular group sequence rank is smaller than thirteen */ /* the regular group sequence rank is smaller than thirteen */
rsq = ADC_RSQ2(adc_periph); rsq = ADC_RSQ2(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -550,7 +582,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_ELEVEN))); (rank - ADC_REGULAR_CHANNEL_RANK_ELEVEN)));
ADC_RSQ2(adc_periph) = rsq; ADC_RSQ2(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_FIFTEEN) { } else if(rank < ADC_REGULAR_CHANNEL_RANK_FIFTEEN)
{
/* the regular group sequence rank is smaller than fifteen */ /* the regular group sequence rank is smaller than fifteen */
rsq = ADC_RSQ1(adc_periph); rsq = ADC_RSQ1(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -558,7 +591,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_THIRTEEN))); (rank - ADC_REGULAR_CHANNEL_RANK_THIRTEEN)));
ADC_RSQ1(adc_periph) = rsq; ADC_RSQ1(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN) { } else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN)
{
/* the regular group sequence rank is smaller than sixteen */ /* the regular group sequence rank is smaller than sixteen */
rsq = ADC_RSQ0(adc_periph); rsq = ADC_RSQ0(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -592,13 +626,15 @@ void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_
rankx = ADC_OFFSET_LENGTH - inserted_length + rank; rankx = ADC_OFFSET_LENGTH - inserted_length + rank;
/* configure ADC inserted sequence */ /* configure ADC inserted sequence */
if(rankx < ADC_INSERTED_CHANNEL_RANK_ONE) { if(rankx < ADC_INSERTED_CHANNEL_RANK_ONE)
{
/* the inserted group sequence rank is smaller than one */ /* the inserted group sequence rank is smaller than one */
isq = ADC_ISQ2(adc_periph); isq = ADC_ISQ2(adc_periph);
isq &= ~((uint32_t)((ADC_ISQX_ISMPN | ADC_ISQX_ISQN) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH * rankx))); isq &= ~((uint32_t)((ADC_ISQX_ISMPN | ADC_ISQX_ISQN) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH * rankx)));
isq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH * rankx)); isq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH * rankx));
ADC_ISQ2(adc_periph) = isq; ADC_ISQ2(adc_periph) = isq;
} else if(rankx < ADC_INSERTED_CHANNEL_RANK_THREE) { } else if(rankx < ADC_INSERTED_CHANNEL_RANK_THREE)
{
/* the inserted group sequence rank is smaller than three */ /* the inserted group sequence rank is smaller than three */
isq = ADC_ISQ1(adc_periph); isq = ADC_ISQ1(adc_periph);
isq &= ~((uint32_t)((ADC_ISQX_ISMPN | ADC_ISQX_ISQN) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH * isq &= ~((uint32_t)((ADC_ISQX_ISMPN | ADC_ISQX_ISQN) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH *
@ -606,7 +642,8 @@ void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_
isq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH * isq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH *
(rankx - ADC_INSERTED_CHANNEL_RANK_ONE))); (rankx - ADC_INSERTED_CHANNEL_RANK_ONE)));
ADC_ISQ1(adc_periph) = isq; ADC_ISQ1(adc_periph) = isq;
} else if(rankx < ADC_INSERTED_CHANNEL_RANK_FOUR) { } else if(rankx < ADC_INSERTED_CHANNEL_RANK_FOUR)
{
/* the inserted group sequence rank is smaller than four */ /* the inserted group sequence rank is smaller than four */
isq = ADC_ISQ0(adc_periph); isq = ADC_ISQ0(adc_periph);
isq &= ~((uint32_t)((ADC_ISQX_ISMPN | ADC_ISQX_ISQN) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH * isq &= ~((uint32_t)((ADC_ISQX_ISMPN | ADC_ISQX_ISQN) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH *
@ -640,7 +677,8 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch
inserted_length = (uint8_t)GET_BITS(ADC_ISQ0(adc_periph), 20U, 21U); inserted_length = (uint8_t)GET_BITS(ADC_ISQ0(adc_periph), 20U, 21U);
num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel));
if(num <= ADC_OFFSET_LENGTH) { if(num <= ADC_OFFSET_LENGTH)
{
/* calculate the offset of the register */ /* calculate the offset of the register */
num = num * ADC_OFFSET_SHIFT_LENGTH; num = num * ADC_OFFSET_SHIFT_LENGTH;
/* config the offset of the selected channels */ /* config the offset of the selected channels */
@ -660,7 +698,8 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch
*/ */
void adc_channel_differential_mode_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue) void adc_channel_differential_mode_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue)
{ {
if(ENABLE == newvalue) { if(ENABLE == newvalue)
{
ADC_DIFCTL(adc_periph) |= (uint32_t)adc_channel; ADC_DIFCTL(adc_periph) |= (uint32_t)adc_channel;
} else { } else {
ADC_DIFCTL(adc_periph) &= ~((uint32_t)adc_channel); ADC_DIFCTL(adc_periph) &= ~((uint32_t)adc_channel);
@ -685,7 +724,8 @@ void adc_channel_differential_mode_config(uint32_t adc_periph, uint32_t adc_chan
*/ */
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t trigger_mode) void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t trigger_mode)
{ {
switch(adc_channel_group) { switch(adc_channel_group)
{
case ADC_REGULAR_CHANNEL: case ADC_REGULAR_CHANNEL:
/* configure ADC regular channel group external trigger mode */ /* configure ADC regular channel group external trigger mode */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC); ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC);
@ -714,11 +754,13 @@ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group,
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
{ {
/* enable regular group channel software trigger */ /* enable regular group channel software trigger */
if(RESET != (adc_channel_group & ADC_REGULAR_CHANNEL)) { if(RESET != (adc_channel_group & ADC_REGULAR_CHANNEL))
{
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST; ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST;
} }
/* enable inserted channel group software trigger */ /* enable inserted channel group software trigger */
if(RESET != (adc_channel_group & ADC_INSERTED_CHANNEL)) { if(RESET != (adc_channel_group & ADC_INSERTED_CHANNEL))
{
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST; ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST;
} }
} }
@ -735,10 +777,12 @@ void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
*/ */
void adc_end_of_conversion_config(uint32_t adc_periph, uint32_t end_selection) void adc_end_of_conversion_config(uint32_t adc_periph, uint32_t end_selection)
{ {
if(ADC_EOC_SET_SEQUENCE == end_selection) { if(ADC_EOC_SET_SEQUENCE == end_selection)
{
/* only at the end of a sequence of regular conversions, the EOC bit is set */ /* only at the end of a sequence of regular conversions, the EOC bit is set */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM); ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM);
} else if(ADC_EOC_SET_CONVERSION == end_selection) { } else if(ADC_EOC_SET_CONVERSION == end_selection)
{
/* at the end of each regular conversion, the EOC bit is set. Overflow is detected automatically */ /* at the end of each regular conversion, the EOC bit is set. Overflow is detected automatically */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_EOCM; ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_EOCM;
} else { } else {
@ -774,7 +818,8 @@ uint32_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel)
{ {
uint32_t idata; uint32_t idata;
/* read the data of the selected channel */ /* read the data of the selected channel */
switch(inserted_channel) { switch(inserted_channel)
{
case ADC_INSERTED_CHANNEL_0: case ADC_INSERTED_CHANNEL_0:
/* read the data of channel 0 */ /* read the data of channel 0 */
idata = ADC_IDATA0(adc_periph); idata = ADC_IDATA0(adc_periph);
@ -831,7 +876,8 @@ void adc_watchdog0_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel
{ {
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWD0EN | ADC_CTL0_IWD0EN | ADC_CTL0_WD0SC)); ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWD0EN | ADC_CTL0_IWD0EN | ADC_CTL0_WD0SC));
/* select the group */ /* select the group */
switch(adc_channel_group) { switch(adc_channel_group)
{
case ADC_REGULAR_CHANNEL: case ADC_REGULAR_CHANNEL:
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_RWD0EN; ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_RWD0EN;
break; break;
@ -870,7 +916,8 @@ void adc_watchdog0_disable(uint32_t adc_periph)
*/ */
void adc_watchdog1_channel_config(uint32_t adc_periph, uint32_t selection_channel, ControlStatus newvalue) void adc_watchdog1_channel_config(uint32_t adc_periph, uint32_t selection_channel, ControlStatus newvalue)
{ {
if(ENABLE == newvalue) { if(ENABLE == newvalue)
{
ADC_WD1SR(adc_periph) |= (uint32_t)selection_channel; ADC_WD1SR(adc_periph) |= (uint32_t)selection_channel;
} else { } else {
ADC_WD1SR(adc_periph) &= ~((uint32_t)selection_channel); ADC_WD1SR(adc_periph) &= ~((uint32_t)selection_channel);
@ -889,7 +936,8 @@ void adc_watchdog1_channel_config(uint32_t adc_periph, uint32_t selection_channe
*/ */
void adc_watchdog2_channel_config(uint32_t adc_periph, uint32_t selection_channel, ControlStatus newvalue) void adc_watchdog2_channel_config(uint32_t adc_periph, uint32_t selection_channel, ControlStatus newvalue)
{ {
if(ENABLE == newvalue) { if(ENABLE == newvalue)
{
ADC_WD2SR(adc_periph) |= (uint32_t)selection_channel; ADC_WD2SR(adc_periph) |= (uint32_t)selection_channel;
} else { } else {
ADC_WD2SR(adc_periph) &= ~((uint32_t)selection_channel); ADC_WD2SR(adc_periph) &= ~((uint32_t)selection_channel);
@ -987,10 +1035,12 @@ void adc_watchdog2_threshold_config(uint32_t adc_periph, uint32_t low_threshold,
*/ */
void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint16_t ratio) void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint16_t ratio)
{ {
if(ADC_OVERSAMPLING_ALL_CONVERT == mode) { if(ADC_OVERSAMPLING_ALL_CONVERT == mode)
{
/* all oversampled conversions for a channel are done consecutively after a trigger */ /* all oversampled conversions for a channel are done consecutively after a trigger */
ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS);
} else if(ADC_OVERSAMPLING_ONE_CONVERT == mode) { } else if(ADC_OVERSAMPLING_ONE_CONVERT == mode)
{
/* each oversampled conversion for a channel needs a trigger */ /* each oversampled conversion for a channel needs a trigger */
ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS;
} else { } else {
@ -1042,7 +1092,8 @@ void adc_oversample_mode_disable(uint32_t adc_periph)
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t flag) FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t flag)
{ {
FlagStatus reval = RESET; FlagStatus reval = RESET;
if(ADC_STAT(adc_periph) & flag) { if(ADC_STAT(adc_periph) & flag)
{
reval = SET; reval = SET;
} }
return reval; return reval;
@ -1126,46 +1177,53 @@ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t int_flag)
FlagStatus reval = RESET; FlagStatus reval = RESET;
uint32_t state; uint32_t state;
/* check the interrupt bits */ /* check the interrupt bits */
switch(int_flag) { switch(int_flag)
{
case ADC_INT_FLAG_WDE0: case ADC_INT_FLAG_WDE0:
/* get the ADC analog watchdog 0 interrupt bits */ /* get the ADC analog watchdog 0 interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_WDE0; state = ADC_STAT(adc_periph) & ADC_STAT_WDE0;
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE0IE) && state) { if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE0IE) && state)
{
reval = SET; reval = SET;
} }
break; break;
case ADC_INT_FLAG_EOC: case ADC_INT_FLAG_EOC:
/* get the ADC end of group conversion interrupt bits */ /* get the ADC end of group conversion interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_EOC; state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) { if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state)
{
reval = SET; reval = SET;
} }
break; break;
case ADC_INT_FLAG_EOIC: case ADC_INT_FLAG_EOIC:
/* get the ADC end of inserted group conversion interrupt bits */ /* get the ADC end of inserted group conversion interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) { if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state)
{
reval = SET; reval = SET;
} }
break; break;
case ADC_INT_FLAG_ROVF: case ADC_INT_FLAG_ROVF:
/* get the ADC regular data register overflow interrupt bits */ /* get the ADC regular data register overflow interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_ROVF; state = ADC_STAT(adc_periph) & ADC_STAT_ROVF;
if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state) { if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state)
{
reval = SET; reval = SET;
} }
break; break;
case ADC_INT_FLAG_WDE1: case ADC_INT_FLAG_WDE1:
/* get the ADC analog watchdog 1 interrupt bits */ /* get the ADC analog watchdog 1 interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_WDE1; state = ADC_STAT(adc_periph) & ADC_STAT_WDE1;
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE1IE) && state) { if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE1IE) && state)
{
reval = SET; reval = SET;
} }
break; break;
case ADC_INT_FLAG_WDE2: case ADC_INT_FLAG_WDE2:
/* get the ADC analog watchdog 2 interrupt bits */ /* get the ADC analog watchdog 2 interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_WDE2; state = ADC_STAT(adc_periph) & ADC_STAT_WDE2;
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE2IE) && state) { if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE2IE) && state)
{
reval = SET; reval = SET;
} }
break; break;

324
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_can.c
View File

@ -54,17 +54,20 @@ static uint32_t can_dlc_value_compute(uint32_t payload_size);
*/ */
void can_deinit(uint32_t can_periph) void can_deinit(uint32_t can_periph)
{ {
if(CAN0 == can_periph) { if(CAN0 == can_periph)
{
/* reset CAN0 */ /* reset CAN0 */
rcu_periph_reset_enable(RCU_CAN0RST); rcu_periph_reset_enable(RCU_CAN0RST);
rcu_periph_reset_disable(RCU_CAN0RST); rcu_periph_reset_disable(RCU_CAN0RST);
} }
if(CAN1 == can_periph) { if(CAN1 == can_periph)
{
/* reset CAN1 */ /* reset CAN1 */
rcu_periph_reset_enable(RCU_CAN1RST); rcu_periph_reset_enable(RCU_CAN1RST);
rcu_periph_reset_disable(RCU_CAN1RST); rcu_periph_reset_disable(RCU_CAN1RST);
} }
if(CAN2 == can_periph) { if(CAN2 == can_periph)
{
/* reset CAN2 */ /* reset CAN2 */
rcu_periph_reset_enable(RCU_CAN2RST); rcu_periph_reset_enable(RCU_CAN2RST);
rcu_periph_reset_disable(RCU_CAN2RST); rcu_periph_reset_disable(RCU_CAN2RST);
@ -84,10 +87,12 @@ ErrStatus can_software_reset(uint32_t can_periph)
/* reset internal state machines and CAN registers */ /* reset internal state machines and CAN registers */
CAN_CTL0(can_periph) |= CAN_CTL0_SWRST; CAN_CTL0(can_periph) |= CAN_CTL0_SWRST;
/* wait reset complete */ /* wait reset complete */
while((CAN_CTL0(can_periph) & CAN_CTL0_SWRST) && (timeout)) { while((CAN_CTL0(can_periph) & CAN_CTL0_SWRST) && (timeout))
{
timeout--; timeout--;
} }
if(CAN_CTL0(can_periph) & CAN_CTL0_SWRST) { if(CAN_CTL0(can_periph) & CAN_CTL0_SWRST)
{
return ERROR; return ERROR;
} }
return SUCCESS; return SUCCESS;
@ -131,16 +136,19 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init
uint32_t *canram = (uint32_t *)(CAN_RAM(can_periph)); uint32_t *canram = (uint32_t *)(CAN_RAM(can_periph));
/* clear CAN RAM */ /* clear CAN RAM */
for(i = 0U; i < CAN_MAX_RAM_SIZE; i++) { for(i = 0U; i < CAN_MAX_RAM_SIZE; i++)
{
canram[i] = 0U; canram[i] = 0U;
} }
/* reset CAN_RFIFOMPFx */ /* reset CAN_RFIFOMPFx */
for(i = 0U; i < CAN_MAX_MAILBOX_NUM; i++) { for(i = 0U; i < CAN_MAX_MAILBOX_NUM; i++)
{
CAN_RFIFOMPF(can_periph, i) = 0x00000000U; CAN_RFIFOMPF(can_periph, i) = 0x00000000U;
} }
/* reset internal state machines and CAN registers */ /* reset internal state machines and CAN registers */
if(ERROR == can_software_reset(can_periph)) { if(ERROR == can_software_reset(can_periph))
{
return ERROR; return ERROR;
} }
@ -149,7 +157,8 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init
/* reset CAN_STAT */ /* reset CAN_STAT */
CAN_STAT(can_periph) = (uint32_t)0xFFFFFFFFU; CAN_STAT(can_periph) = (uint32_t)0xFFFFFFFFU;
CAN_TIMER(can_periph); CAN_TIMER(can_periph);
while(CAN_STAT(can_periph) & CAN_STAT_MS5_RFNE) { while(CAN_STAT(can_periph) & CAN_STAT_MS5_RFNE)
{
CAN_STAT(can_periph) = CAN_STAT_MS5_RFNE; CAN_STAT(can_periph) = CAN_STAT_MS5_RFNE;
} }
@ -160,27 +169,33 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init
CAN_BT(can_periph) &= ~(CAN_BT_BAUDPSC | CAN_BT_SJW | CAN_BT_PTS | CAN_BT_PBS1 | CAN_BT_PBS2); CAN_BT(can_periph) &= ~(CAN_BT_BAUDPSC | CAN_BT_SJW | CAN_BT_PTS | CAN_BT_PBS1 | CAN_BT_PBS2);
/* set self reception */ /* set self reception */
if((uint8_t)DISABLE == can_parameter_init->self_reception) { if((uint8_t)DISABLE == can_parameter_init->self_reception)
{
CAN_CTL0(can_periph) |= CAN_CTL0_SRDIS; CAN_CTL0(can_periph) |= CAN_CTL0_SRDIS;
} }
/* enable local arbitration priority */ /* enable local arbitration priority */
if((uint8_t)ENABLE == can_parameter_init->local_priority_enable) { if((uint8_t)ENABLE == can_parameter_init->local_priority_enable)
{
CAN_CTL0(can_periph) |= CAN_CTL0_LAPRIOEN; CAN_CTL0(can_periph) |= CAN_CTL0_LAPRIOEN;
} }
/* set rx private filters and mailbox queue */ /* set rx private filters and mailbox queue */
if((uint8_t)ENABLE == can_parameter_init->rx_private_filter_queue_enable) { if((uint8_t)ENABLE == can_parameter_init->rx_private_filter_queue_enable)
{
CAN_CTL0(can_periph) |= CAN_CTL0_RPFQEN; CAN_CTL0(can_periph) |= CAN_CTL0_RPFQEN;
} }
/* configure edge filtering */ /* configure edge filtering */
if((uint32_t)DISABLE == can_parameter_init->edge_filter_enable) { if((uint32_t)DISABLE == can_parameter_init->edge_filter_enable)
{
CAN_CTL2(can_periph) |= CAN_CTL2_EFDIS; CAN_CTL2(can_periph) |= CAN_CTL2_EFDIS;
} }
/* configure protocol exception */ /* configure protocol exception */
if((uint32_t)ENABLE == can_parameter_init->protocol_exception_enable) { if((uint32_t)ENABLE == can_parameter_init->protocol_exception_enable)
{
CAN_CTL2(can_periph) |= CAN_CTL2_PREEN; CAN_CTL2(can_periph) |= CAN_CTL2_PREEN;
} }
/* set mailbox stop transmission */ /* set mailbox stop transmission */
if((uint8_t)ENABLE == can_parameter_init->mb_tx_abort_enable) { if((uint8_t)ENABLE == can_parameter_init->mb_tx_abort_enable)
{
CAN_CTL0(can_periph) |= CAN_CTL0_MST; CAN_CTL0(can_periph) |= CAN_CTL0_MST;
} }
@ -229,7 +244,8 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init
void can_struct_para_init(can_struct_type_enum type, void *p_struct) void can_struct_para_init(can_struct_type_enum type, void *p_struct)
{ {
/* get type of the struct */ /* get type of the struct */
switch(type) { switch(type)
{
/* used for initialize can_parameter_struct */ /* used for initialize can_parameter_struct */
case CAN_INIT_STRUCT: case CAN_INIT_STRUCT:
((can_parameter_struct *)p_struct)->self_reception = (uint8_t)DISABLE; ((can_parameter_struct *)p_struct)->self_reception = (uint8_t)DISABLE;
@ -387,15 +403,18 @@ ErrStatus can_operation_mode_enter(uint32_t can_periph, can_operation_modes_enum
CAN_CTL0(can_periph) &= ~(CAN_CTL0_PNEN | CAN_CTL0_PNMOD); CAN_CTL0(can_periph) &= ~(CAN_CTL0_PNEN | CAN_CTL0_PNMOD);
timeout = CAN_DELAY; timeout = CAN_DELAY;
/* wait for inactive mode state */ /* wait for inactive mode state */
while(((CAN_CTL0_NRDY | CAN_CTL0_INAS) != (CAN_CTL0(can_periph) & (CAN_CTL0_NRDY | CAN_CTL0_INAS))) && (timeout)) { while(((CAN_CTL0_NRDY | CAN_CTL0_INAS) != (CAN_CTL0(can_periph) & (CAN_CTL0_NRDY | CAN_CTL0_INAS))) && (timeout))
{
timeout--; timeout--;
} }
if((CAN_CTL0_NRDY | CAN_CTL0_INAS) != (CAN_CTL0(can_periph) & (CAN_CTL0_NRDY | CAN_CTL0_INAS))) { if((CAN_CTL0_NRDY | CAN_CTL0_INAS) != (CAN_CTL0(can_periph) & (CAN_CTL0_NRDY | CAN_CTL0_INAS)))
{
return ERROR; return ERROR;
} }
/* configure the modes */ /* configure the modes */
switch(mode) { switch(mode)
{
case CAN_NORMAL_MODE: case CAN_NORMAL_MODE:
CAN_CTL1(can_periph) &= ~(CAN_CTL1_LSCMOD | CAN_CTL1_MMOD); CAN_CTL1(can_periph) &= ~(CAN_CTL1_LSCMOD | CAN_CTL1_MMOD);
break; break;
@ -422,24 +441,30 @@ ErrStatus can_operation_mode_enter(uint32_t can_periph, can_operation_modes_enum
} }
/* exit INACTIVE mode */ /* exit INACTIVE mode */
if(CAN_INACTIVE_MODE != mode) { if(CAN_INACTIVE_MODE != mode)
{
/* exit inactive mode */ /* exit inactive mode */
CAN_CTL0(can_periph) &= ~(CAN_CTL0_HALT | CAN_CTL0_INAMOD); CAN_CTL0(can_periph) &= ~(CAN_CTL0_HALT | CAN_CTL0_INAMOD);
timeout = CAN_DELAY; timeout = CAN_DELAY;
while((CAN_CTL0(can_periph) & CAN_CTL0_INAS) && (timeout)) { while((CAN_CTL0(can_periph) & CAN_CTL0_INAS) && (timeout))
{
timeout--; timeout--;
} }
if(CAN_CTL0(can_periph) & CAN_CTL0_INAS) { if(CAN_CTL0(can_periph) & CAN_CTL0_INAS)
{
return ERROR; return ERROR;
} }
} }
if(CAN_PN_MODE == mode) { if(CAN_PN_MODE == mode)
{
timeout = CAN_DELAY; timeout = CAN_DELAY;
while((0U == (CAN_CTL0(can_periph) & CAN_CTL0_PNS)) && (timeout)) { while((0U == (CAN_CTL0(can_periph) & CAN_CTL0_PNS)) && (timeout))
{
timeout--; timeout--;
} }
if(0U == (CAN_CTL0(can_periph) & CAN_CTL0_PNS)) { if(0U == (CAN_CTL0(can_periph) & CAN_CTL0_PNS))
{
return ERROR; return ERROR;
} }
} }
@ -460,19 +485,25 @@ can_operation_modes_enum can_operation_mode_get(uint32_t can_periph)
reg = CAN_CTL0(can_periph); reg = CAN_CTL0(can_periph);
reg &= (CAN_CTL0_NRDY | CAN_CTL0_INAS | CAN_CTL0_PNS | CAN_CTL0_LPS); reg &= (CAN_CTL0_NRDY | CAN_CTL0_INAS | CAN_CTL0_PNS | CAN_CTL0_LPS);
if((CAN_CTL0_NRDY | CAN_CTL0_LPS) == reg) { if((CAN_CTL0_NRDY | CAN_CTL0_LPS) == reg)
{
state = CAN_DISABLE_MODE; state = CAN_DISABLE_MODE;
} else if((CAN_CTL0_NRDY | CAN_CTL0_INAS) == reg) { } else if((CAN_CTL0_NRDY | CAN_CTL0_INAS) == reg)
{
state = CAN_INACTIVE_MODE; state = CAN_INACTIVE_MODE;
} else if(0U == reg) { } else if(0U == reg)
if(CAN_CTL1(can_periph)&CAN_CTL1_MMOD) { {
if(CAN_CTL1(can_periph)&CAN_CTL1_MMOD)
{
state = CAN_MONITOR_MODE; state = CAN_MONITOR_MODE;
} else if(CAN_CTL1(can_periph)&CAN_CTL1_LSCMOD) { } else if(CAN_CTL1(can_periph)&CAN_CTL1_LSCMOD)
{
state = CAN_LOOPBACK_SILENT_MODE; state = CAN_LOOPBACK_SILENT_MODE;
} else { } else {
state = CAN_NORMAL_MODE; state = CAN_NORMAL_MODE;
} }
} else if(CAN_CTL0_PNS == reg) { } else if(CAN_CTL0_PNS == reg)
{
state = CAN_PN_MODE; state = CAN_PN_MODE;
} else { } else {
/* should not get here */ /* should not get here */
@ -494,10 +525,12 @@ ErrStatus can_inactive_mode_exit(uint32_t can_periph)
/* exit inactive mode */ /* exit inactive mode */
CAN_CTL0(can_periph) &= ~CAN_CTL0_HALT; CAN_CTL0(can_periph) &= ~CAN_CTL0_HALT;
timeout = CAN_DELAY; timeout = CAN_DELAY;
while((CAN_CTL0(can_periph) & CAN_CTL0_INAS) && (timeout)) { while((CAN_CTL0(can_periph) & CAN_CTL0_INAS) && (timeout))
{
timeout--; timeout--;
} }
if(CAN_CTL0(can_periph) & CAN_CTL0_INAS) { if(CAN_CTL0(can_periph) & CAN_CTL0_INAS)
{
return ERROR; return ERROR;
} else { } else {
return SUCCESS; return SUCCESS;
@ -517,10 +550,12 @@ ErrStatus can_pn_mode_exit(uint32_t can_periph)
CAN_CTL0(can_periph) &= ~(CAN_CTL0_PNEN | CAN_CTL0_PNMOD); CAN_CTL0(can_periph) &= ~(CAN_CTL0_PNEN | CAN_CTL0_PNMOD);
timeout = CAN_DELAY; timeout = CAN_DELAY;
while((CAN_CTL0(can_periph) & CAN_CTL0_PNS) && (timeout)) { while((CAN_CTL0(can_periph) & CAN_CTL0_PNS) && (timeout))
{
timeout--; timeout--;
} }
if(CAN_CTL0(can_periph) & CAN_CTL0_PNS) { if(CAN_CTL0(can_periph) & CAN_CTL0_PNS)
{
return ERROR; return ERROR;
} else { } else {
return SUCCESS; return SUCCESS;
@ -556,15 +591,18 @@ void can_fd_config(uint32_t can_periph, can_fd_parameter_struct *can_fd_para_ini
CAN_CTL0(can_periph) |= CAN_CTL0_FDEN; CAN_CTL0(can_periph) |= CAN_CTL0_FDEN;
/* support ISO or non-ISO mode */ /* support ISO or non-ISO mode */
if((uint32_t)ENABLE == can_fd_para_init->iso_can_fd_enable) { if((uint32_t)ENABLE == can_fd_para_init->iso_can_fd_enable)
{
CAN_CTL2(can_periph) |= CAN_CTL2_ISO; CAN_CTL2(can_periph) |= CAN_CTL2_ISO;
} }
/* set TDC parameter */ /* set TDC parameter */
if((uint32_t)ENABLE == can_fd_para_init->tdc_enable) { if((uint32_t)ENABLE == can_fd_para_init->tdc_enable)
{
CAN_FDCTL(can_periph) |= CAN_FDCTL_TDCEN; CAN_FDCTL(can_periph) |= CAN_FDCTL_TDCEN;
} }
/* set data bit rate */ /* set data bit rate */
if((uint32_t)ENABLE == can_fd_para_init->bitrate_switch_enable) { if((uint32_t)ENABLE == can_fd_para_init->bitrate_switch_enable)
{
CAN_FDCTL(can_periph) |= CAN_FDCTL_BRSEN; CAN_FDCTL(can_periph) |= CAN_FDCTL_BRSEN;
} }
@ -669,12 +707,14 @@ void can_rx_fifo_config(uint32_t can_periph, can_fifo_parameter_struct *can_fifo
/* clear FIFO status */ /* clear FIFO status */
CAN_STAT(can_periph) = (uint32_t)0xFFFFFFFFU; CAN_STAT(can_periph) = (uint32_t)0xFFFFFFFFU;
while(CAN_STAT(can_periph) & CAN_STAT_MS5_RFNE) { while(CAN_STAT(can_periph) & CAN_STAT_MS5_RFNE)
{
CAN_STAT(can_periph) = CAN_STAT_MS5_RFNE; CAN_STAT(can_periph) = CAN_STAT_MS5_RFNE;
} }
/* set DMA mode */ /* set DMA mode */
if((uint8_t)ENABLE == can_fifo_para_init->dma_enable) { if((uint8_t)ENABLE == can_fifo_para_init->dma_enable)
{
CAN_CTL0(can_periph) |= CAN_CTL0_DMAEN; CAN_CTL0(can_periph) |= CAN_CTL0_DMAEN;
} }
@ -685,8 +725,10 @@ void can_rx_fifo_config(uint32_t can_periph, can_fifo_parameter_struct *can_fifo
/* configure fifo public fiter */ /* configure fifo public fiter */
CAN_RFIFOPUBF(can_periph) = can_fifo_para_init->fifo_public_filter; CAN_RFIFOPUBF(can_periph) = can_fifo_para_init->fifo_public_filter;
/* configure fifo private fiter */ /* configure fifo private fiter */
if(!(CAN_CTL0(can_periph) & CAN_CTL0_RPFQEN)) { if(!(CAN_CTL0(can_periph) & CAN_CTL0_RPFQEN))
for(num = 0U; num < CAN_MAX_MAILBOX_NUM; num++) { {
for(num = 0U; num < CAN_MAX_MAILBOX_NUM; num++)
{
CAN_RFIFOMPF(can_periph, num) = can_fifo_para_init->fifo_public_filter; CAN_RFIFOMPF(can_periph, num) = can_fifo_para_init->fifo_public_filter;
} }
} }
@ -713,16 +755,20 @@ void can_rx_fifo_filter_table_config(uint32_t can_periph, can_rx_fifo_id_filter_
num_of_filters = (GET_CTL2_RFFN(CAN_CTL2(can_periph)) + 1U) * 8U; num_of_filters = (GET_CTL2_RFFN(CAN_CTL2(can_periph)) + 1U) * 8U;
id_format = CAN_CTL0(can_periph) & CAN_CTL0_FS; id_format = CAN_CTL0(can_periph) & CAN_CTL0_FS;
switch(id_format) { switch(id_format)
{
case(CAN_FIFO_FILTER_FORMAT_A): case(CAN_FIFO_FILTER_FORMAT_A):
/* one full id (standard and extended) per id filter table element */ /* one full id (standard and extended) per id filter table element */
for(i = 0U; i < num_of_filters; i++) { for(i = 0U; i < num_of_filters; i++)
{
val = 0U; val = 0U;
if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[i].remote_frame) { if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[i].remote_frame)
{
val |= CAN_FDESX_RTR_A; val |= CAN_FDESX_RTR_A;
} }
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[i].extended_frame) { if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[i].extended_frame)
{
val |= CAN_FDESX_IDE_A; val |= CAN_FDESX_IDE_A;
val |= (uint32_t)FIFO_FILTER_ID_EXD_A(id_filter_table[i].id); val |= (uint32_t)FIFO_FILTER_ID_EXD_A(id_filter_table[i].id);
} else { } else {
@ -734,13 +780,16 @@ void can_rx_fifo_filter_table_config(uint32_t can_periph, can_rx_fifo_id_filter_
case(CAN_FIFO_FILTER_FORMAT_B): case(CAN_FIFO_FILTER_FORMAT_B):
/* two full standard id or two partial 14-bit (standard and extended) id */ /* two full standard id or two partial 14-bit (standard and extended) id */
j = 0U; j = 0U;
for(i = 0U; i < num_of_filters; i++) { for(i = 0U; i < num_of_filters; i++)
{
val = 0U; val = 0U;
if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[j].remote_frame) { if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[j].remote_frame)
{
val |= CAN_FDESX_RTR_B0; val |= CAN_FDESX_RTR_B0;
} }
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) { if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame)
{
val |= CAN_FDESX_IDE_B0; val |= CAN_FDESX_IDE_B0;
val |= (uint32_t)FIFO_FILTER_ID_EXD_B0(id_filter_table[j].id); val |= (uint32_t)FIFO_FILTER_ID_EXD_B0(id_filter_table[j].id);
} else { } else {
@ -748,10 +797,12 @@ void can_rx_fifo_filter_table_config(uint32_t can_periph, can_rx_fifo_id_filter_
} }
j++; j++;
if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[j].remote_frame) { if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[j].remote_frame)
{
val |= CAN_FDESX_RTR_B1; val |= CAN_FDESX_RTR_B1;
} }
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) { if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame)
{
val |= CAN_FDESX_IDE_B1; val |= CAN_FDESX_IDE_B1;
val |= (uint32_t)FIFO_FILTER_ID_EXD_B1(id_filter_table[j].id); val |= (uint32_t)FIFO_FILTER_ID_EXD_B1(id_filter_table[j].id);
} else { } else {
@ -765,27 +816,32 @@ void can_rx_fifo_filter_table_config(uint32_t can_periph, can_rx_fifo_id_filter_
case(CAN_FIFO_FILTER_FORMAT_C): case(CAN_FIFO_FILTER_FORMAT_C):
/* four partial 8-bit standard id per id filter table element */ /* four partial 8-bit standard id per id filter table element */
j = 0U; j = 0U;
for(i = 0U; i < num_of_filters; i++) { for(i = 0U; i < num_of_filters; i++)
{
val = 0U; val = 0U;
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) { if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame)
{
val |= (uint32_t)FIFO_FILTER_ID_EXD_C0(id_filter_table[j].id); val |= (uint32_t)FIFO_FILTER_ID_EXD_C0(id_filter_table[j].id);
} else { } else {
val |= (uint32_t)FIFO_FILTER_ID_STD_C0(id_filter_table[j].id); val |= (uint32_t)FIFO_FILTER_ID_STD_C0(id_filter_table[j].id);
} }
j++; j++;
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) { if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame)
{
val |= (uint32_t)FIFO_FILTER_ID_EXD_C1(id_filter_table[j].id); val |= (uint32_t)FIFO_FILTER_ID_EXD_C1(id_filter_table[j].id);
} else { } else {
val |= (uint32_t)FIFO_FILTER_ID_STD_C1(id_filter_table[j].id); val |= (uint32_t)FIFO_FILTER_ID_STD_C1(id_filter_table[j].id);
} }
j++; j++;
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) { if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame)
{
val |= (uint32_t)FIFO_FILTER_ID_EXD_C2(id_filter_table[j].id); val |= (uint32_t)FIFO_FILTER_ID_EXD_C2(id_filter_table[j].id);
} else { } else {
val |= (uint32_t)FIFO_FILTER_ID_STD_C2(id_filter_table[j].id); val |= (uint32_t)FIFO_FILTER_ID_STD_C2(id_filter_table[j].id);
} }
j++; j++;
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) { if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame)
{
val |= (uint32_t)FIFO_FILTER_ID_EXD_C3(id_filter_table[j].id); val |= (uint32_t)FIFO_FILTER_ID_EXD_C3(id_filter_table[j].id);
} else { } else {
val |= (uint32_t)FIFO_FILTER_ID_STD_C3(id_filter_table[j].id); val |= (uint32_t)FIFO_FILTER_ID_STD_C3(id_filter_table[j].id);
@ -825,7 +881,8 @@ void can_rx_fifo_read(uint32_t can_periph, can_rx_fifo_struct *rx_fifo)
CAN_STAT(can_periph) = CAN_STAT_MS5_RFNE; CAN_STAT(can_periph) = CAN_STAT_MS5_RFNE;
/* read FIFO id field */ /* read FIFO id field */
if(rx_fifo->ide) { if(rx_fifo->ide)
{
rx_fifo->id = GET_FDES1_ID_EXD(rx_fifo->id); rx_fifo->id = GET_FDES1_ID_EXD(rx_fifo->id);
} else { } else {
rx_fifo->id = GET_FDES1_ID_STD(rx_fifo->id); rx_fifo->id = GET_FDES1_ID_STD(rx_fifo->id);
@ -870,7 +927,8 @@ uint32_t *can_ram_address_get(uint32_t can_periph, uint32_t index)
uint32_t *address; uint32_t *address;
/* if CAN FD mode is enabled */ /* if CAN FD mode is enabled */
if(CAN_CTL0(can_periph) & CAN_CTL0_FDEN) { if(CAN_CTL0(can_periph) & CAN_CTL0_FDEN)
{
payload_size = (uint32_t)1U << (GET_FDCTL_MDSZ(CAN_FDCTL(can_periph)) + 3U); payload_size = (uint32_t)1U << (GET_FDCTL_MDSZ(CAN_FDCTL(can_periph)) + 3U);
} else { } else {
payload_size = 8U; payload_size = 8U;
@ -920,12 +978,14 @@ void can_mailbox_config(uint32_t can_periph, uint32_t index, can_mailbox_descrip
mdes[3] = 0U; mdes[3] = 0U;
/* set RTR bit */ /* set RTR bit */
if(mdpara->rtr) { if(mdpara->rtr)
{
mdes0 |= CAN_MDES0_RTR; mdes0 |= CAN_MDES0_RTR;
} }
/* set IDE bit and ID field */ /* set IDE bit and ID field */
if(mdpara->ide) { if(mdpara->ide)
{
mdes0 |= CAN_MDES0_IDE; mdes0 |= CAN_MDES0_IDE;
mdes0 |= CAN_MDES0_SRR; mdes0 |= CAN_MDES0_SRR;
mdes[1] |= MDES1_ID_EXD(mdpara->id); mdes[1] |= MDES1_ID_EXD(mdpara->id);
@ -936,28 +996,35 @@ void can_mailbox_config(uint32_t can_periph, uint32_t index, can_mailbox_descrip
/* set CODE field */ /* set CODE field */
mdes0 |= MDES0_CODE(mdpara->code); mdes0 |= MDES0_CODE(mdpara->code);
if(mdpara->code != CAN_MB_RX_STATUS_EMPTY) { if(mdpara->code != CAN_MB_RX_STATUS_EMPTY)
{
/* copy user's buffer into the mailbox data area */ /* copy user's buffer into the mailbox data area */
if(mdpara->data_bytes) { if(mdpara->data_bytes)
{
dlc = can_dlc_value_compute(mdpara->data_bytes); dlc = can_dlc_value_compute(mdpara->data_bytes);
mdes0 |= MDES0_DLC(dlc); mdes0 |= MDES0_DLC(dlc);
length = (uint32_t)1U << (GET_FDCTL_MDSZ(CAN_FDCTL(can_periph)) + 3U); length = (uint32_t)1U << (GET_FDCTL_MDSZ(CAN_FDCTL(can_periph)) + 3U);
if(mdpara->data_bytes < length) { if(mdpara->data_bytes < length)
{
length = mdpara->data_bytes; length = mdpara->data_bytes;
} }
can_data_to_big_endian_swap(&mdes[2], mdpara->data, length); can_data_to_big_endian_swap(&mdes[2], mdpara->data, length);
} }
/* prepare mailbox for transmission */ /* prepare mailbox for transmission */
if(CAN_MB_TX_STATUS_DATA == mdpara->code) { if(CAN_MB_TX_STATUS_DATA == mdpara->code)
{
/* set ESI bit */ /* set ESI bit */
if(mdpara->esi) { if(mdpara->esi)
{
mdes0 |= CAN_MDES0_ESI; mdes0 |= CAN_MDES0_ESI;
} }
/* set FDF and BRS bit */ /* set FDF and BRS bit */
if(mdpara->fdf) { if(mdpara->fdf)
{
mdes0 |= CAN_MDES0_FDF; mdes0 |= CAN_MDES0_FDF;
if(mdpara->brs) { if(mdpara->brs)
{
mdes0 |= CAN_MDES0_BRS; mdes0 |= CAN_MDES0_BRS;
} }
mdes0 &= ~CAN_MDES0_RTR; mdes0 &= ~CAN_MDES0_RTR;
@ -1035,10 +1102,12 @@ ErrStatus can_mailbox_receive_data_read(uint32_t can_periph, uint32_t index, can
/* wait mailbox data ready */ /* wait mailbox data ready */
timeout = CAN_DELAY; timeout = CAN_DELAY;
while((mdes[0] & MDES0_CODE(CAN_MB_RX_STATUS_BUSY)) && (timeout)) { while((mdes[0] & MDES0_CODE(CAN_MB_RX_STATUS_BUSY)) && (timeout))
{
timeout--; timeout--;
} }
if(mdes[0] & MDES0_CODE(CAN_MB_RX_STATUS_BUSY)) { if(mdes[0] & MDES0_CODE(CAN_MB_RX_STATUS_BUSY))
{
return ERROR; return ERROR;
} }
@ -1049,7 +1118,8 @@ ErrStatus can_mailbox_receive_data_read(uint32_t can_periph, uint32_t index, can
cnt = (mdpara->data_bytes + 3U) / 4U; cnt = (mdpara->data_bytes + 3U) / 4U;
mdaddr = mdpara->data; mdaddr = mdpara->data;
mdes += 2U; mdes += 2U;
for(i = 0U; i < cnt; i++) { for(i = 0U; i < cnt; i++)
{
mdaddr[i] = mdes[i]; mdaddr[i] = mdes[i];
} }
@ -1059,14 +1129,16 @@ ErrStatus can_mailbox_receive_data_read(uint32_t can_periph, uint32_t index, can
CAN_TIMER(can_periph); CAN_TIMER(can_periph);
/* get mailbox ID */ /* get mailbox ID */
if(mdpara->ide) { if(mdpara->ide)
{
mdpara->id = GET_MDES1_ID_EXD(mdpara->id); mdpara->id = GET_MDES1_ID_EXD(mdpara->id);
} else { } else {
mdpara->id = GET_MDES1_ID_STD(mdpara->id); mdpara->id = GET_MDES1_ID_STD(mdpara->id);
} }
/* get mailbox data */ /* get mailbox data */
if(mdpara->data_bytes) { if(mdpara->data_bytes)
{
can_data_to_little_endian_swap(mdpara->data, mdpara->data, mdpara->data_bytes); can_data_to_little_endian_swap(mdpara->data, mdpara->data, mdpara->data_bytes);
} }
@ -1191,7 +1263,8 @@ can_error_state_enum can_error_state_get(uint32_t can_periph)
uint32_t reg; uint32_t reg;
reg = GET_ERR1_ERRSI(CAN_ERR1(can_periph)); reg = GET_ERR1_ERRSI(CAN_ERR1(can_periph));
if(reg >= (uint32_t)CAN_ERROR_STATE_BUS_OFF) { if(reg >= (uint32_t)CAN_ERROR_STATE_BUS_OFF)
{
reg = (uint32_t)CAN_ERROR_STATE_BUS_OFF; reg = (uint32_t)CAN_ERROR_STATE_BUS_OFF;
} }
@ -1285,13 +1358,16 @@ void can_pn_mode_filter_config(uint32_t can_periph, can_pn_mode_filter_struct *e
/* set filter identifier 0 */ /* set filter identifier 0 */
reg = 0U; reg = 0U;
if((uint32_t)SET == expect->ide) { if((uint32_t)SET == expect->ide)
{
reg |= CAN_PN_EID0_EIDE; reg |= CAN_PN_EID0_EIDE;
} }
if((uint32_t)SET == expect->rtr) { if((uint32_t)SET == expect->rtr)
{
reg |= CAN_PN_EID0_ERTR; reg |= CAN_PN_EID0_ERTR;
} }
if(CAN_STANDARD == (expect->id & BIT(31))){ if(CAN_STANDARD == (expect->id & BIT(31)))
{
reg |= (uint32_t)PN_EID0_EIDF_ELT_STD(expect->id); reg |= (uint32_t)PN_EID0_EIDF_ELT_STD(expect->id);
}else{ }else{
reg |= (uint32_t)PN_EID0_EIDF_ELT_EXD(expect->id); reg |= (uint32_t)PN_EID0_EIDF_ELT_EXD(expect->id);
@ -1302,17 +1378,21 @@ void can_pn_mode_filter_config(uint32_t can_periph, can_pn_mode_filter_struct *e
temp = CAN_PN_CTL0(can_periph); temp = CAN_PN_CTL0(can_periph);
reg = 0U; reg = 0U;
/* ID field 1 is used when ID filtering type is EXACT or RANGE */ /* ID field 1 is used when ID filtering type is EXACT or RANGE */
if(((temp & CAN_PN_CTL0_IDFT) == CAN_PN_ID_FILTERING_EXACT) || ((temp & CAN_PN_CTL0_IDFT) == CAN_PN_ID_FILTERING_RANGE)) { if(((temp & CAN_PN_CTL0_IDFT) == CAN_PN_ID_FILTERING_EXACT) || ((temp & CAN_PN_CTL0_IDFT) == CAN_PN_ID_FILTERING_RANGE))
if(CAN_STANDARD == (filter->id & BIT(31))){ {
if(CAN_STANDARD == (filter->id & BIT(31)))
{
reg |= (uint32_t)PN_IFEID1_IDEFD_STD(filter->id); reg |= (uint32_t)PN_IFEID1_IDEFD_STD(filter->id);
}else{ }else{
reg |= (uint32_t)PN_IFEID1_IDEFD_EXD(filter->id); reg |= (uint32_t)PN_IFEID1_IDEFD_EXD(filter->id);
} }
} }
if((uint32_t)SET == filter->ide) { if((uint32_t)SET == filter->ide)
{
reg |= CAN_PN_IFEID1_IDEFD; reg |= CAN_PN_IFEID1_IDEFD;
} }
if((uint32_t)SET == filter->rtr) { if((uint32_t)SET == filter->rtr)
{
reg |= CAN_PN_IFEID1_RTRFD; reg |= CAN_PN_IFEID1_RTRFD;
} }
/* set filter identifier 1 */ /* set filter identifier 1 */
@ -1320,7 +1400,8 @@ void can_pn_mode_filter_config(uint32_t can_periph, can_pn_mode_filter_struct *e
/* data field is used when frame filtering type is not MATCH or MATCH NMM */ /* data field is used when frame filtering type is not MATCH or MATCH NMM */
if(((temp & CAN_PN_CTL0_FFT) == CAN_PN_FRAME_FILTERING_ID_DATA) || if(((temp & CAN_PN_CTL0_FFT) == CAN_PN_FRAME_FILTERING_ID_DATA) ||
((temp & CAN_PN_CTL0_FFT) == CAN_PN_FRAME_FILTERING_ID_DATA_NMM)) { ((temp & CAN_PN_CTL0_FFT) == CAN_PN_FRAME_FILTERING_ID_DATA_NMM))
{
/* set filter data payload 0 */ /* set filter data payload 0 */
CAN_PN_EDLC(can_periph) = PN_EDLC_DLCEHT(expect->dlc_high_threshold) | PN_EDLC_DLCELT(expect->dlc_low_threshold); CAN_PN_EDLC(can_periph) = PN_EDLC_DLCEHT(expect->dlc_high_threshold) | PN_EDLC_DLCELT(expect->dlc_low_threshold);
CAN_PN_EDL0(can_periph) = ((expect->payload[0] << 24U) & CAN_PN_EDL0_DB0ELT) | CAN_PN_EDL0(can_periph) = ((expect->payload[0] << 24U) & CAN_PN_EDL0_DB0ELT) |
@ -1334,7 +1415,8 @@ void can_pn_mode_filter_config(uint32_t can_periph, can_pn_mode_filter_struct *e
/* data field 1 is used when data filtering type is EXACT or RANGE */ /* data field 1 is used when data filtering type is EXACT or RANGE */
if(((temp & CAN_PN_CTL0_DATAFT) == CAN_PN_DATA_FILTERING_EXACT) if(((temp & CAN_PN_CTL0_DATAFT) == CAN_PN_DATA_FILTERING_EXACT)
|| ((temp & CAN_PN_CTL0_DATAFT) == CAN_PN_DATA_FILTERING_RANGE)) { || ((temp & CAN_PN_CTL0_DATAFT) == CAN_PN_DATA_FILTERING_RANGE))
{
/* set filter data payload 1 */ /* set filter data payload 1 */
CAN_PN_DF0EDH0(can_periph) = ((filter->payload[0] << 24U) & CAN_PN_DF0EDH0_DB0FD_EHT) | CAN_PN_DF0EDH0(can_periph) = ((filter->payload[0] << 24U) & CAN_PN_DF0EDH0_DB0FD_EHT) |
((filter->payload[0] << 8U) & CAN_PN_DF0EDH0_DB1FD_EHT) | ((filter->payload[0] << 8U) & CAN_PN_DF0EDH0_DB1FD_EHT) |
@ -1361,7 +1443,8 @@ int32_t can_pn_mode_num_of_match_get(uint32_t can_periph)
uint32_t reg = 0U; uint32_t reg = 0U;
reg = CAN_PN_STAT(can_periph); reg = CAN_PN_STAT(can_periph);
if(0U != (reg & CAN_PN_STAT_MMCNTS)) { if(0U != (reg & CAN_PN_STAT_MMCNTS))
{
ret = (int32_t)(uint32_t)GET_PN_STAT_MMCNT(reg); ret = (int32_t)(uint32_t)GET_PN_STAT_MMCNT(reg);
} else { } else {
ret = -1; ret = -1;
@ -1386,24 +1469,28 @@ void can_pn_mode_data_read(uint32_t can_periph, uint32_t index, can_mailbox_desc
mdaddr[0] = pnram[0]; mdaddr[0] = pnram[0];
mdaddr[1] = pnram[1]; mdaddr[1] = pnram[1];
/* get mailbox ID */ /* get mailbox ID */
if(0U != mdpara->ide) { if(0U != mdpara->ide)
{
mdpara->id = GET_MDES1_ID_EXD(mdpara->id); mdpara->id = GET_MDES1_ID_EXD(mdpara->id);
} else { } else {
mdpara->id = GET_MDES1_ID_STD(mdpara->id); mdpara->id = GET_MDES1_ID_STD(mdpara->id);
} }
mdpara->data_bytes = mdpara->dlc; mdpara->data_bytes = mdpara->dlc;
/* remote frame */ /* remote frame */
if(0U != (mdaddr[0] & CAN_PN_RWMXCS_RRTR)){ if(0U != (mdaddr[0] & CAN_PN_RWMXCS_RRTR))
{
mdpara->data_bytes = 0U; mdpara->data_bytes = 0U;
}else{ }else{
/* classical frame */ /* classical frame */
if(mdpara->dlc <= 8U) { if(mdpara->dlc <= 8U)
{
mdpara->data_bytes = mdpara->dlc; mdpara->data_bytes = mdpara->dlc;
}else{ }else{
mdpara->data_bytes = 8U; mdpara->data_bytes = 8U;
} }
} }
if(mdpara->data_bytes) { if(mdpara->data_bytes)
{
can_data_to_little_endian_swap(mdpara->data, &pnram[2], mdpara->data_bytes); can_data_to_little_endian_swap(mdpara->data, &pnram[2], mdpara->data_bytes);
} }
} }
@ -1567,7 +1654,8 @@ void can_arbitration_delay_bits_config(uint32_t can_periph, uint32_t delay_bits)
*/ */
void can_bsp_mode_config(uint32_t can_periph, uint32_t sampling_mode) void can_bsp_mode_config(uint32_t can_periph, uint32_t sampling_mode)
{ {
if(CAN_BSP_MODE_ONE_SAMPLE == sampling_mode) { if(CAN_BSP_MODE_ONE_SAMPLE == sampling_mode)
{
CAN_CTL1(can_periph) &= ~CAN_CTL1_BSPMOD; CAN_CTL1(can_periph) &= ~CAN_CTL1_BSPMOD;
} else { } else {
CAN_CTL1(can_periph) |= CAN_CTL1_BSPMOD; CAN_CTL1(can_periph) |= CAN_CTL1_BSPMOD;
@ -1615,7 +1703,8 @@ void can_bsp_mode_config(uint32_t can_periph, uint32_t sampling_mode)
*/ */
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag)
{ {
if(CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag))) { if(CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -1644,7 +1733,8 @@ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag)
*/ */
void can_flag_clear(uint32_t can_periph, can_flag_enum flag) void can_flag_clear(uint32_t can_periph, can_flag_enum flag)
{ {
if(CAN_FLAG_TDC_OUT_OF_RANGE == flag) { if(CAN_FLAG_TDC_OUT_OF_RANGE == flag)
{
CAN_FDCTL(can_periph) |= CAN_FDCTL_TDCS; CAN_FDCTL(can_periph) |= CAN_FDCTL_TDCS;
} else { } else {
CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag)); CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag));
@ -1677,14 +1767,17 @@ ErrStatus can_interrupt_enable(uint32_t can_periph, can_interrupt_enum interrupt
ErrStatus ret = SUCCESS; ErrStatus ret = SUCCESS;
/* enable receive or transmit warning error interrupt should enable error warning in CTL0 register */ /* enable receive or transmit warning error interrupt should enable error warning in CTL0 register */
if((CAN_INT_RX_WARNING == interrupt) || (CAN_INT_TX_WARNING == interrupt)) { if((CAN_INT_RX_WARNING == interrupt) || (CAN_INT_TX_WARNING == interrupt))
{
mode = can_operation_mode_get(can_periph); mode = can_operation_mode_get(can_periph);
/* in INACTIVE mode */ /* in INACTIVE mode */
if(CAN_INACTIVE_MODE == mode){ if(CAN_INACTIVE_MODE == mode)
{
CAN_CTL0(can_periph) |= CAN_CTL0_WERREN; CAN_CTL0(can_periph) |= CAN_CTL0_WERREN;
}else{ }else{
ret = can_operation_mode_enter(can_periph, CAN_INACTIVE_MODE); ret = can_operation_mode_enter(can_periph, CAN_INACTIVE_MODE);
if(SUCCESS == ret){ if(SUCCESS == ret)
{
CAN_CTL0(can_periph) |= CAN_CTL0_WERREN; CAN_CTL0(can_periph) |= CAN_CTL0_WERREN;
ret = can_operation_mode_enter(can_periph, mode); ret = can_operation_mode_enter(can_periph, mode);
} }
@ -1721,14 +1814,17 @@ ErrStatus can_interrupt_disable(uint32_t can_periph, can_interrupt_enum interrup
ErrStatus ret = SUCCESS; ErrStatus ret = SUCCESS;
/* disable receive or transmit warning error interrupt should enable error warning in CTL0 register */ /* disable receive or transmit warning error interrupt should enable error warning in CTL0 register */
if((0U == (CAN_CTL0(can_periph) & CAN_CTL0_WERREN)) && ((CAN_INT_RX_WARNING == interrupt) || (CAN_INT_TX_WARNING == interrupt))) { if((0U == (CAN_CTL0(can_periph) & CAN_CTL0_WERREN)) && ((CAN_INT_RX_WARNING == interrupt) || (CAN_INT_TX_WARNING == interrupt)))
{
mode = can_operation_mode_get(can_periph); mode = can_operation_mode_get(can_periph);
/* in INACTIVE mode */ /* in INACTIVE mode */
if(CAN_INACTIVE_MODE == mode){ if(CAN_INACTIVE_MODE == mode)
{
CAN_CTL0(can_periph) |= CAN_CTL0_WERREN; CAN_CTL0(can_periph) |= CAN_CTL0_WERREN;
}else{ }else{
ret = can_operation_mode_enter(can_periph, CAN_INACTIVE_MODE); ret = can_operation_mode_enter(can_periph, CAN_INACTIVE_MODE);
if(SUCCESS == ret){ if(SUCCESS == ret)
{
CAN_CTL0(can_periph) |= CAN_CTL0_WERREN; CAN_CTL0(can_periph) |= CAN_CTL0_WERREN;
ret = can_operation_mode_enter(can_periph, mode); ret = can_operation_mode_enter(can_periph, mode);
} }
@ -1761,7 +1857,8 @@ ErrStatus can_interrupt_disable(uint32_t can_periph, can_interrupt_enum interrup
*/ */
FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum int_flag) FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum int_flag)
{ {
if(CAN_REG_VAL(can_periph, int_flag) & BIT(CAN_BIT_POS(int_flag))) { if(CAN_REG_VAL(can_periph, int_flag) & BIT(CAN_BIT_POS(int_flag)))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -1805,17 +1902,21 @@ static uint32_t can_payload_size_compute(uint32_t mdes0)
uint32_t dlc_value = GET_MDES0_DLC(mdes0); uint32_t dlc_value = GET_MDES0_DLC(mdes0);
/* remote frame */ /* remote frame */
if(0U != (mdes0 & CAN_MDES0_RTR)){ if(0U != (mdes0 & CAN_MDES0_RTR))
{
ret = 0U; ret = 0U;
}else{ }else{
/* FD frame */ /* FD frame */
if(0U != (mdes0 & CAN_MDES0_FDF)){ if(0U != (mdes0 & CAN_MDES0_FDF))
if(dlc_value <= 15U) { {
if(dlc_value <= 15U)
{
ret = dlc_to_databytes[dlc_value]; ret = dlc_to_databytes[dlc_value];
} }
/* classical frame */ /* classical frame */
}else{ }else{
if(dlc_value <= 8U) { if(dlc_value <= 8U)
{
ret = (uint8_t)dlc_value; ret = (uint8_t)dlc_value;
}else{ }else{
ret = 8U; ret = 8U;
@ -1842,7 +1943,8 @@ static void can_data_to_little_endian_swap(uint32_t dest[], uint32_t src[], uint
/* get the word length of the data */ /* get the word length of the data */
cnt = (len + 3U) / 4U; cnt = (len + 3U) / 4U;
/* change each word from big endian to little endian */ /* change each word from big endian to little endian */
for(i = 0U; i < cnt; i++) { for(i = 0U; i < cnt; i++)
{
temp_src = src[i]; temp_src = src[i];
dest[i] = ((uint32_t)(temp_src >> 24U) & 0x000000FFU) | dest[i] = ((uint32_t)(temp_src >> 24U) & 0x000000FFU) |
((uint32_t)(temp_src >> 8U) & 0x0000FF00U) | ((uint32_t)(temp_src >> 8U) & 0x0000FF00U) |
@ -1851,7 +1953,8 @@ static void can_data_to_little_endian_swap(uint32_t dest[], uint32_t src[], uint
} }
cnt = len % 4U; cnt = len % 4U;
if(cnt) { if(cnt)
{
dest[i - 1U] &= ((uint32_t)1U << (cnt * 8U)) - 1U; dest[i - 1U] &= ((uint32_t)1U << (cnt * 8U)) - 1U;
} }
} }
@ -1871,7 +1974,8 @@ static void can_data_to_big_endian_swap(uint32_t dest[], uint32_t src[], uint32_
/* get the word length of the data */ /* get the word length of the data */
cnt = (len + 3U) / 4U; cnt = (len + 3U) / 4U;
for(i = 0U; i < cnt; i++) { for(i = 0U; i < cnt; i++)
{
/* change each word from little endian to big endian */ /* change each word from little endian to big endian */
temp_src = src[i]; temp_src = src[i];
dest[i] = ((uint32_t)(temp_src >> 24U) & 0x000000FFU) | dest[i] = ((uint32_t)(temp_src >> 24U) & 0x000000FFU) |
@ -1881,7 +1985,8 @@ static void can_data_to_big_endian_swap(uint32_t dest[], uint32_t src[], uint32_
} }
cnt = len % 4U; cnt = len % 4U;
if(cnt) { if(cnt)
{
dest[i - 1U] &= ~(((uint32_t)1U << ((4U - cnt) * 8U)) - 1U); dest[i - 1U] &= ~(((uint32_t)1U << ((4U - cnt) * 8U)) - 1U);
} }
} }
@ -1896,11 +2001,14 @@ static uint32_t can_dlc_value_compute(uint32_t payload_size)
{ {
uint32_t ret = 8U; uint32_t ret = 8U;
if(payload_size <= 8U) { if(payload_size <= 8U)
{
ret = payload_size; ret = payload_size;
} else if(payload_size <= 24U) { } else if(payload_size <= 24U)
{
ret = (payload_size - 9U) / 4U + 9U; ret = (payload_size - 9U) / 4U + 9U;
} else if(payload_size <= 64U) { } else if(payload_size <= 64U)
{
ret = (payload_size - 17U) / 16U + 13U; ret = (payload_size - 17U) / 16U + 13U;
} else { } else {
ret = 8U; ret = 8U;

74
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cau.c
View File

@ -1,34 +1,34 @@
/*! /*!
\file gd32h7xx_cau.c \file gd32h7xx_cau.c
\brief CAU driver \brief CAU driver
\version 2024-01-05, V1.2.0, firmware for GD32H7xx \version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/ */
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -408,7 +408,8 @@ void cau_fifo_flush(void)
ControlStatus cau_enable_state_get(void) ControlStatus cau_enable_state_get(void)
{ {
ControlStatus ret = DISABLE; ControlStatus ret = DISABLE;
if(RESET != (CAU_CTL & CAU_CTL_CAUEN)) { if(RESET != (CAU_CTL & CAU_CTL_CAUEN))
{
ret = ENABLE; ret = ENABLE;
} }
return ret; return ret;
@ -476,7 +477,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
algm_reg = CAU_CTL & CAU_CTL_ALGM; algm_reg = CAU_CTL & CAU_CTL_ALGM;
/* AES or DES */ /* AES or DES */
if((uint32_t)0 != (algm_reg & (~CAU_MODE_TDES_CBC))) { if((uint32_t)0 != (algm_reg & (~CAU_MODE_TDES_CBC)))
{
/* wait until both the IN and OUT FIFOs are empty (IEM=1 and ONE=0 in the CAU_STAT0 register) and BUSY=0 */ /* wait until both the IN and OUT FIFOs are empty (IEM=1 and ONE=0 in the CAU_STAT0 register) and BUSY=0 */
checkbits = CAU_STAT0_IEM; checkbits = CAU_STAT0_IEM;
checkmask = STAT0_AESDES_MASK; checkmask = STAT0_AESDES_MASK;
@ -487,7 +489,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
checkmask = STAT0_TDES_MASK; checkmask = STAT0_TDES_MASK;
} }
while((CAU_STAT0 & checkmask) != checkbits) { while((CAU_STAT0 & checkmask) != checkbits)
{
} }
/* stop DMA transfers on the OUT FIFO by clear CAU_DMAEN_DMAOEN=0 */ /* stop DMA transfers on the OUT FIFO by clear CAU_DMAEN_DMAOEN=0 */
@ -513,7 +516,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
cau_context->key_3_high = key_initpara->key_3_high; cau_context->key_3_high = key_initpara->key_3_high;
cau_context->key_3_low = key_initpara->key_3_low; cau_context->key_3_low = key_initpara->key_3_low;
if((CAU_MODE_TDES_ECB != algm_reg) && (CAU_MODE_DES_ECB != algm_reg) && (CAU_MODE_AES_ECB != algm_reg)) { if((CAU_MODE_TDES_ECB != algm_reg) && (CAU_MODE_DES_ECB != algm_reg) && (CAU_MODE_AES_ECB != algm_reg))
{
/* if not in ECB mode, save the initialization vectors */ /* if not in ECB mode, save the initialization vectors */
cau_context->iv_0_high = CAU_IV0H; cau_context->iv_0_high = CAU_IV0H;
cau_context->iv_0_low = CAU_IV0L; cau_context->iv_0_low = CAU_IV0L;
@ -522,7 +526,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
} }
/* if in GCM/CCM mode, save the context switch registers */ /* if in GCM/CCM mode, save the context switch registers */
if((CAU_MODE_AES_GCM == algm_reg) || (CAU_MODE_AES_CCM == algm_reg)) { if((CAU_MODE_AES_GCM == algm_reg) || (CAU_MODE_AES_CCM == algm_reg))
{
cau_context->gcmccmctxs[0U] = CAU_GCMCCMCTXSx(0U); cau_context->gcmccmctxs[0U] = CAU_GCMCCMCTXSx(0U);
cau_context->gcmccmctxs[1U] = CAU_GCMCCMCTXSx(1U); cau_context->gcmccmctxs[1U] = CAU_GCMCCMCTXSx(1U);
cau_context->gcmccmctxs[2U] = CAU_GCMCCMCTXSx(2U); cau_context->gcmccmctxs[2U] = CAU_GCMCCMCTXSx(2U);
@ -534,7 +539,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
} }
/* if in GCM mode, save the context switch registers */ /* if in GCM mode, save the context switch registers */
if(CAU_MODE_AES_GCM == algm_reg) { if(CAU_MODE_AES_GCM == algm_reg)
{
cau_context->gcmctxs[0U] = CAU_GCMCTXSx(0U); cau_context->gcmctxs[0U] = CAU_GCMCTXSx(0U);
cau_context->gcmctxs[1U] = CAU_GCMCTXSx(1U); cau_context->gcmctxs[1U] = CAU_GCMCTXSx(1U);
cau_context->gcmctxs[2U] = CAU_GCMCTXSx(2U); cau_context->gcmctxs[2U] = CAU_GCMCTXSx(2U);
@ -586,7 +592,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
CAU_KEY3H = cau_context->key_3_high; CAU_KEY3H = cau_context->key_3_high;
CAU_KEY3L = cau_context->key_3_low; CAU_KEY3L = cau_context->key_3_low;
if((CAU_MODE_TDES_ECB != algm_reg) && (CAU_MODE_DES_ECB != algm_reg) && (CAU_MODE_AES_ECB != algm_reg)) { if((CAU_MODE_TDES_ECB != algm_reg) && (CAU_MODE_DES_ECB != algm_reg) && (CAU_MODE_AES_ECB != algm_reg))
{
/* restore the initialization vectors */ /* restore the initialization vectors */
CAU_IV0H = cau_context->iv_0_high; CAU_IV0H = cau_context->iv_0_high;
CAU_IV0L = cau_context->iv_0_low; CAU_IV0L = cau_context->iv_0_low;
@ -595,7 +602,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
} }
/* if in GCM/CCM mode, restore the context switch registers */ /* if in GCM/CCM mode, restore the context switch registers */
if((CAU_MODE_AES_GCM == algm_reg) || (CAU_MODE_AES_CCM == algm_reg)) { if((CAU_MODE_AES_GCM == algm_reg) || (CAU_MODE_AES_CCM == algm_reg))
{
CAU_GCMCCMCTXSx(0U) = cau_context->gcmccmctxs[0U]; CAU_GCMCCMCTXSx(0U) = cau_context->gcmccmctxs[0U];
CAU_GCMCCMCTXSx(1U) = cau_context->gcmccmctxs[1U]; CAU_GCMCCMCTXSx(1U) = cau_context->gcmccmctxs[1U];
CAU_GCMCCMCTXSx(2U) = cau_context->gcmccmctxs[2U]; CAU_GCMCCMCTXSx(2U) = cau_context->gcmccmctxs[2U];
@ -607,7 +615,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
} }
/* if in GCM mode, restore the context switch registers */ /* if in GCM mode, restore the context switch registers */
if(CAU_MODE_AES_GCM == algm_reg) { if(CAU_MODE_AES_GCM == algm_reg)
{
CAU_GCMCTXSx(0U) = cau_context->gcmctxs[0U]; CAU_GCMCTXSx(0U) = cau_context->gcmctxs[0U];
CAU_GCMCTXSx(1U) = cau_context->gcmctxs[1U]; CAU_GCMCTXSx(1U) = cau_context->gcmctxs[1U];
CAU_GCMCTXSx(2U) = cau_context->gcmctxs[2U]; CAU_GCMCTXSx(2U) = cau_context->gcmctxs[2U];
@ -620,7 +629,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
/* if it is AES ECB/CBC decryption, then first prepare key */ /* if it is AES ECB/CBC decryption, then first prepare key */
aes_decrypt = CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR); aes_decrypt = CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR);
if(((CAU_MODE_AES_ECB | CAU_DECRYPT) == aes_decrypt) || ((CAU_MODE_AES_CBC | CAU_DECRYPT) == aes_decrypt)) { if(((CAU_MODE_AES_ECB | CAU_DECRYPT) == aes_decrypt) || ((CAU_MODE_AES_CBC | CAU_DECRYPT) == aes_decrypt))
{
uint32_t alg_dir, algo_mode, swapping; uint32_t alg_dir, algo_mode, swapping;
/* flush IN/OUT FIFOs */ /* flush IN/OUT FIFOs */
@ -635,7 +645,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
cau_enable(); cau_enable();
/* wait until BUSY=0 */ /* wait until BUSY=0 */
while((uint32_t)0U != cau_flag_get(CAU_FLAG_BUSY)) { while((uint32_t)0U != cau_flag_get(CAU_FLAG_BUSY))
{
} }
/* parameters for decryption */ /* parameters for decryption */
@ -666,7 +677,8 @@ FlagStatus cau_flag_get(uint32_t flag)
FlagStatus ret_flag = RESET; FlagStatus ret_flag = RESET;
/* check if the flag is in CAU_STAT1 register */ /* check if the flag is in CAU_STAT1 register */
if(RESET != (flag & FLAG_MASK)) { if(RESET != (flag & FLAG_MASK))
{
reg = CAU_STAT1; reg = CAU_STAT1;
} else { } else {
/* the flag is in CAU_STAT0 register */ /* the flag is in CAU_STAT0 register */
@ -674,7 +686,8 @@ FlagStatus cau_flag_get(uint32_t flag)
} }
/* check the status of the specified CAU flag */ /* check the status of the specified CAU flag */
if(RESET != (reg & flag)) { if(RESET != (reg & flag))
{
ret_flag = SET; ret_flag = SET;
} }
@ -725,7 +738,8 @@ FlagStatus cau_interrupt_flag_get(uint32_t int_flag)
FlagStatus flag = RESET; FlagStatus flag = RESET;
/* check the status of the specified CAU interrupt */ /* check the status of the specified CAU interrupt */
if(RESET != (CAU_INTF & int_flag)) { if(RESET != (CAU_INTF & int_flag))
{
flag = SET; flag = SET;
} }

173
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cau_aes.c
View File

@ -1,34 +1,34 @@
/*! /*!
\file gd32h7xx_cau_aes.c \file gd32h7xx_cau_aes.c
\brief CAU AES driver \brief CAU AES driver
\version 2024-01-05, V1.2.0, firmware for GD32H7xx \version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/ */
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -74,7 +74,8 @@ ErrStatus cau_aes_ecb(cau_parameter_struct *cau_parameter, uint8_t *output)
cau_key_init(&key_initpara); cau_key_init(&key_initpara);
/* AES decryption */ /* AES decryption */
if(CAU_DECRYPT == cau_parameter->alg_dir) { if(CAU_DECRYPT == cau_parameter->alg_dir)
{
/* flush the IN and OUT FIFOs */ /* flush the IN and OUT FIFOs */
cau_fifo_flush(); cau_fifo_flush();
/* initialize the CAU peripheral */ /* initialize the CAU peripheral */
@ -89,7 +90,8 @@ ErrStatus cau_aes_ecb(cau_parameter_struct *cau_parameter, uint8_t *output)
counter++; counter++;
} while((AESBSY_TIMEOUT != counter) && (RESET != busystatus)); } while((AESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) { if(RESET != busystatus)
{
return ERROR; return ERROR;
} }
} }
@ -141,7 +143,8 @@ ErrStatus cau_aes_cbc(cau_parameter_struct *cau_parameter, uint8_t *output)
cau_key_init(&key_initpara); cau_key_init(&key_initpara);
/* AES decryption */ /* AES decryption */
if(CAU_DECRYPT == cau_parameter->alg_dir) { if(CAU_DECRYPT == cau_parameter->alg_dir)
{
/* flush the IN and OUT FIFOs */ /* flush the IN and OUT FIFOs */
cau_fifo_flush(); cau_fifo_flush();
/* initialize the CAU peripheral */ /* initialize the CAU peripheral */
@ -156,7 +159,8 @@ ErrStatus cau_aes_cbc(cau_parameter_struct *cau_parameter, uint8_t *output)
counter++; counter++;
} while((AESBSY_TIMEOUT != counter) && (RESET != busystatus)); } while((AESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) { if(RESET != busystatus)
{
return ERROR; return ERROR;
} }
} }
@ -396,11 +400,13 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* enable the CAU peripheral */ /* enable the CAU peripheral */
cau_enable(); cau_enable();
/* wait for CAUEN bit to be 0 */ /* wait for CAUEN bit to be 0 */
while(ENABLE == cau_enable_state_get()) { while(ENABLE == cau_enable_state_get())
{
} }
/* aad phase */ /* aad phase */
if((uint32_t)0U != cau_parameter->aad_size) { if((uint32_t)0U != cau_parameter->aad_size)
{
/* select aad phase */ /* select aad phase */
cau_phase_config(CAU_AAD_PHASE); cau_phase_config(CAU_AAD_PHASE);
/* flush the IN and OUT FIFOs */ /* flush the IN and OUT FIFOs */
@ -410,13 +416,15 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
ret = cau_fill_data(cau_parameter->aad, cau_parameter->aad_size); ret = cau_fill_data(cau_parameter->aad, cau_parameter->aad_size);
if(ERROR == ret) { if(ERROR == ret)
{
return ret; return ret;
} }
} }
/* encrypt or decrypt phase */ /* encrypt or decrypt phase */
if((uint32_t)0U != cau_parameter->in_length) { if((uint32_t)0U != cau_parameter->in_length)
{
/* select encrypt or decrypt phase */ /* select encrypt or decrypt phase */
cau_phase_config(CAU_ENCRYPT_DECRYPT_PHASE); cau_phase_config(CAU_ENCRYPT_DECRYPT_PHASE);
/* flush the IN and OUT FIFOs */ /* flush the IN and OUT FIFOs */
@ -427,7 +435,8 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* AES calculate process */ /* AES calculate process */
ret = cau_aes_calculate(cau_parameter->input, cau_parameter->in_length, output); ret = cau_aes_calculate(cau_parameter->input, cau_parameter->in_length, output);
if(ERROR == ret) { if(ERROR == ret)
{
return ret; return ret;
} }
} }
@ -440,7 +449,8 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* enable the CAU peripheral */ /* enable the CAU peripheral */
cau_enable(); cau_enable();
if(DISABLE == cau_enable_state_get()) { if(DISABLE == cau_enable_state_get())
{
return ERROR; return ERROR;
} }
@ -450,7 +460,8 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
cau_data_write(__REV((uint32_t)inputlength)); cau_data_write(__REV((uint32_t)inputlength));
/* wait until the ONE flag is set */ /* wait until the ONE flag is set */
while(RESET == cau_flag_get(CAU_FLAG_OUTFIFO_NO_EMPTY)) { while(RESET == cau_flag_get(CAU_FLAG_OUTFIFO_NO_EMPTY))
{
} }
/* read the tag in the OUT FIFO */ /* read the tag in the OUT FIFO */
@ -510,9 +521,11 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
uint32_t temp_tag[4U]; uint32_t temp_tag[4U];
/* formatting the aad block */ /* formatting the aad block */
if((uint32_t)0U != aadsize) { if((uint32_t)0U != aadsize)
{
/* check that the aad length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ /* check that the aad length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
if(aadsize < 65280U) { if(aadsize < 65280U)
{
aad_buf[head_index++] = (uint8_t)((aadsize >> 8U) & 0xFFU); aad_buf[head_index++] = (uint8_t)((aadsize >> 8U) & 0xFFU);
aad_buf[head_index++] = (uint8_t)((aadsize) & 0xFFU); aad_buf[head_index++] = (uint8_t)((aadsize) & 0xFFU);
aad_block_size = aadsize + 2U; aad_block_size = aadsize + 2U;
@ -527,13 +540,16 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
aad_block_size = aadsize + 6U; aad_block_size = aadsize + 6U;
} }
/* copy the aad buffer in internal buffer "HBuffer" */ /* copy the aad buffer in internal buffer "HBuffer" */
for(i = 0U; i < aadsize; i++) { for(i = 0U; i < aadsize; i++)
{
aad_buf[head_index++] = *(uint8_t *)((uint32_t)(aadaddr + i)); aad_buf[head_index++] = *(uint8_t *)((uint32_t)(aadaddr + i));
} }
/* check if the aad block size is modulo 16 */ /* check if the aad block size is modulo 16 */
if(0U != (aad_block_size % 16U)) { if(0U != (aad_block_size % 16U))
{
/* Pad the aad buffer with 0s till the HBuffer length is modulo 16 */ /* Pad the aad buffer with 0s till the HBuffer length is modulo 16 */
for(i = aad_block_size; i <= ((aad_block_size / 16U) + 1U) * 16U; i++) { for(i = aad_block_size; i <= ((aad_block_size / 16U) + 1U) * 16U; i++)
{
aad_buf[i] = 0U; aad_buf[i] = 0U;
} }
/* set the aad size to modulo 16 */ /* set the aad size to modulo 16 */
@ -544,26 +560,31 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
} }
/* formatting the block B0 */ /* formatting the block B0 */
if(0U != aadsize) { if(0U != aadsize)
{
blockb0[0] = 0x40U; blockb0[0] = 0x40U;
} }
/* flags byte */ /* flags byte */
blockb0[0] |= (0U | (((((uint8_t) tag_size - 2U) / 2U) & 0x07U) << 3U) | (((uint8_t)(15U - ivsize) - 1U) & 0x07U)); blockb0[0] |= (0U | (((((uint8_t) tag_size - 2U) / 2U) & 0x07U) << 3U) | (((uint8_t)(15U - ivsize) - 1U) & 0x07U));
if(ivsize > MAX_CCM_IV_SIZE) { if(ivsize > MAX_CCM_IV_SIZE)
{
return ERROR; return ERROR;
} }
for(i = 0U; i < ivsize; i++) { for(i = 0U; i < ivsize; i++)
{
blockb0[i + 1U] = *(uint8_t *)((uint32_t)(ivaddr + i)); blockb0[i + 1U] = *(uint8_t *)((uint32_t)(ivaddr + i));
} }
/* the byte length for payload length expressing, which plus the ivsize must equal to 15 bytes */ /* the byte length for payload length expressing, which plus the ivsize must equal to 15 bytes */
plen = 15U - ivsize; plen = 15U - ivsize;
/* if the byte length for payload length expressing is more than 4 bytes */ /* if the byte length for payload length expressing is more than 4 bytes */
if(plen > 4U) { if(plen > 4U)
{
/* pad the blockb0 after vectors, and before the last 4 bytes */ /* pad the blockb0 after vectors, and before the last 4 bytes */
for(; i < 11U; i++) { for(; i < 11U; i++)
{
blockb0[i + 1U] = 0U; blockb0[i + 1U] = 0U;
} }
blockb0[12U] = (uint8_t)((inputsize >> 24U) & 0xFFU); blockb0[12U] = (uint8_t)((inputsize >> 24U) & 0xFFU);
@ -572,7 +593,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
blockb0[15U] = (uint8_t)(inputsize & 0xFFU); blockb0[15U] = (uint8_t)(inputsize & 0xFFU);
} else { } else {
/* the payload length is expressed in plen bytes */ /* the payload length is expressed in plen bytes */
for(; i < 15U; i++) { for(; i < 15U; i++)
{
blockb0[i + 1U] = (uint8_t)((inputsize >> ((plen - 1U) * 8U)) & 0xFFU); blockb0[i + 1U] = (uint8_t)((inputsize >> ((plen - 1U) * 8U)) & 0xFFU);
plen--; plen--;
} }
@ -581,7 +603,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* formatting the initial counter */ /* formatting the initial counter */
/* byte 0: bits 0-2 contain the same encoding of q as in B0 */ /* byte 0: bits 0-2 contain the same encoding of q as in B0 */
counter[0] = blockb0[0] & BLOCK_B0_MASK; counter[0] = blockb0[0] & BLOCK_B0_MASK;
for(i = 1U; i < ivsize + 1U; i++) { for(i = 1U; i < ivsize + 1U; i++)
{
counter[i] = blockb0[i]; counter[i] = blockb0[i];
} }
/* set the LSB to 1 */ /* set the LSB to 1 */
@ -628,11 +651,13 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
cau_data_write(*(uint32_t *)(b0addr)); cau_data_write(*(uint32_t *)(b0addr));
/* wait for CAUEN bit to be 0 */ /* wait for CAUEN bit to be 0 */
while(ENABLE == cau_enable_state_get()) { while(ENABLE == cau_enable_state_get())
{
} }
/* aad phase */ /* aad phase */
if((uint32_t)0U != aadsize) { if((uint32_t)0U != aadsize)
{
/* select aad phase */ /* select aad phase */
cau_phase_config(CAU_AAD_PHASE); cau_phase_config(CAU_AAD_PHASE);
/* enable the CAU peripheral */ /* enable the CAU peripheral */
@ -640,7 +665,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
ret = cau_fill_data((uint8_t *)aadaddr, aad_block_size); ret = cau_fill_data((uint8_t *)aadaddr, aad_block_size);
if(ERROR == ret) { if(ERROR == ret)
{
return ret; return ret;
} }
} }
@ -648,7 +674,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* encrypt or decrypt phase */ /* encrypt or decrypt phase */
inputsize = cau_parameter->in_length; inputsize = cau_parameter->in_length;
if((uint32_t)0U != inputsize) { if((uint32_t)0U != inputsize)
{
/* select encrypt or decrypt phase */ /* select encrypt or decrypt phase */
cau_phase_config(CAU_ENCRYPT_DECRYPT_PHASE); cau_phase_config(CAU_ENCRYPT_DECRYPT_PHASE);
/* enable the CAU peripheral */ /* enable the CAU peripheral */
@ -657,7 +684,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* AES calculate process */ /* AES calculate process */
ret = cau_aes_calculate((uint8_t *)inputaddr, inputsize, (uint8_t *)outputaddr); ret = cau_aes_calculate((uint8_t *)inputaddr, inputsize, (uint8_t *)outputaddr);
if(ERROR == ret) { if(ERROR == ret)
{
return ret; return ret;
} }
} }
@ -668,7 +696,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* enable the CAU peripheral */ /* enable the CAU peripheral */
cau_enable(); cau_enable();
if(DISABLE == cau_enable_state_get()) { if(DISABLE == cau_enable_state_get())
{
return ERROR; return ERROR;
} }
@ -684,7 +713,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
cau_data_write(*(uint32_t *)(ctraddr) & 0xFEFFFFFFU); cau_data_write(*(uint32_t *)(ctraddr) & 0xFEFFFFFFU);
/* wait until the ONE flag is set */ /* wait until the ONE flag is set */
while(RESET == cau_flag_get(CAU_FLAG_OUTFIFO_NO_EMPTY)) { while(RESET == cau_flag_get(CAU_FLAG_OUTFIFO_NO_EMPTY))
{
} }
/* read the tag in the OUT FIFO */ /* read the tag in the OUT FIFO */
@ -697,7 +727,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
cau_disable(); cau_disable();
/* Copy temporary authentication TAG in user TAG buffer */ /* Copy temporary authentication TAG in user TAG buffer */
for(i = 0U; i < tag_size; i++) { for(i = 0U; i < tag_size; i++)
{
tag[i] = (uint8_t)(temp_tag[i / 4U] >> (8U * (i % 4U))); tag[i] = (uint8_t)(temp_tag[i / 4U] >> (8U * (i % 4U)));
} }
@ -722,7 +753,8 @@ static void cau_aes_key_config(uint8_t *key, uint32_t keysize, cau_key_parameter
{ {
uint32_t keyaddr = (uint32_t)key; uint32_t keyaddr = (uint32_t)key;
switch(keysize) { switch(keysize)
{
/* 128-bit key initialization */ /* 128-bit key initialization */
case 128: case 128:
cau_aes_keysize_config(CAU_KEYSIZE_128BIT); cau_aes_keysize_config(CAU_KEYSIZE_128BIT);
@ -786,16 +818,20 @@ static ErrStatus cau_fill_data(uint8_t *input, uint32_t in_length)
__IO uint32_t counter = 0U; __IO uint32_t counter = 0U;
uint32_t busystatus = 0U; uint32_t busystatus = 0U;
if(DISABLE == cau_enable_state_get()) { if(DISABLE == cau_enable_state_get())
{
return ERROR; return ERROR;
} }
for(i = 0U; i < in_length; i += BLOCK_DATA_SIZE) { for(i = 0U; i < in_length; i += BLOCK_DATA_SIZE)
{
/* wait until the IEM flag is set */ /* wait until the IEM flag is set */
while(RESET == cau_flag_get(CAU_FLAG_INFIFO_EMPTY)) { while(RESET == cau_flag_get(CAU_FLAG_INFIFO_EMPTY))
{
} }
if(i + BLOCK_DATA_SIZE > in_length) { if(i + BLOCK_DATA_SIZE > in_length)
{
/* the last block data number is less than 128bit */ /* the last block data number is less than 128bit */
uint32_t block_data_temp[4] = {0U}; uint32_t block_data_temp[4] = {0U};
@ -804,10 +840,13 @@ static ErrStatus cau_fill_data(uint8_t *input, uint32_t in_length)
inputaddr = (uint32_t)block_data_temp; inputaddr = (uint32_t)block_data_temp;
/* if GCM encryption or CCM decryption, then configurate NBPILB bits in CTL register */ /* if GCM encryption or CCM decryption, then configurate NBPILB bits in CTL register */
if((CAU_CTL & CAU_CTL_GCM_CCMPH) == CAU_ENCRYPT_DECRYPT_PHASE) { if((CAU_CTL & CAU_CTL_GCM_CCMPH) == CAU_ENCRYPT_DECRYPT_PHASE)
if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_GCM | CAU_ENCRYPT)) { {
if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_GCM | CAU_ENCRYPT))
{
CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length); CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length);
} else if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_CCM | CAU_DECRYPT)) { } else if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_CCM | CAU_DECRYPT))
{
CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length); CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length);
} else { } else {
} }
@ -831,7 +870,8 @@ static ErrStatus cau_fill_data(uint8_t *input, uint32_t in_length)
counter++; counter++;
} while((AESBSY_TIMEOUT != counter) && (RESET != busystatus)); } while((AESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) { if(RESET != busystatus)
{
return ERROR; return ERROR;
} }
@ -854,17 +894,21 @@ static ErrStatus cau_aes_calculate(uint8_t *input, uint32_t in_length, uint8_t *
uint32_t busystatus = 0U; uint32_t busystatus = 0U;
/* the clock is not enabled or there is no embedded CAU peripheral */ /* the clock is not enabled or there is no embedded CAU peripheral */
if(DISABLE == cau_enable_state_get()) { if(DISABLE == cau_enable_state_get())
{
return ERROR; return ERROR;
} }
for(i = 0U; i < in_length; i += BLOCK_DATA_SIZE) { for(i = 0U; i < in_length; i += BLOCK_DATA_SIZE)
{
/* wait until the IEM flag is set */ /* wait until the IEM flag is set */
while(RESET == cau_flag_get(CAU_FLAG_INFIFO_EMPTY)) { while(RESET == cau_flag_get(CAU_FLAG_INFIFO_EMPTY))
{
} }
/* check if the last input data block */ /* check if the last input data block */
if(i + BLOCK_DATA_SIZE > in_length) { if(i + BLOCK_DATA_SIZE > in_length)
{
/* the last block data number is less than 128bit */ /* the last block data number is less than 128bit */
uint32_t block_data_temp[4] = {0}; uint32_t block_data_temp[4] = {0};
@ -873,9 +917,11 @@ static ErrStatus cau_aes_calculate(uint8_t *input, uint32_t in_length, uint8_t *
inputaddr = (uint32_t)block_data_temp; inputaddr = (uint32_t)block_data_temp;
/* if GCM encryption or CCM decryption, then configurate NBPILB bits in CTL register */ /* if GCM encryption or CCM decryption, then configurate NBPILB bits in CTL register */
if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_GCM | CAU_ENCRYPT)) { if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_GCM | CAU_ENCRYPT))
{
CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length); CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length);
} else if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_CCM | CAU_DECRYPT)) { } else if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_CCM | CAU_DECRYPT))
{
CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length); CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length);
} else { } else {
} }
@ -898,7 +944,8 @@ static ErrStatus cau_aes_calculate(uint8_t *input, uint32_t in_length, uint8_t *
counter++; counter++;
} while((AESBSY_TIMEOUT != counter) && (RESET != busystatus)); } while((AESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) { if(RESET != busystatus)
{
return ERROR; return ERROR;
} else { } else {
/* read the output block from the output FIFO */ /* read the output block from the output FIFO */

41
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cau_des.c
View File

@ -1,34 +1,34 @@
/*! /*!
\file gd32h7xx_cau_des.c \file gd32h7xx_cau_des.c
\brief CAU DES driver \brief CAU DES driver
\version 2024-01-05, V1.2.0, firmware for GD32H7xx \version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/ */
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -150,11 +150,13 @@ static ErrStatus cau_des_calculate(uint8_t *input, uint32_t in_length, uint8_t *
uint32_t busystatus = 0U; uint32_t busystatus = 0U;
/* the clock is not enabled or there is no embedded CAU peripheral */ /* the clock is not enabled or there is no embedded CAU peripheral */
if(DISABLE == cau_enable_state_get()) { if(DISABLE == cau_enable_state_get())
{
return ERROR; return ERROR;
} }
for(i = 0U; i < in_length; i += 8U) { for(i = 0U; i < in_length; i += 8U)
{
/* write data to the IN FIFO */ /* write data to the IN FIFO */
cau_data_write(*(uint32_t *)(inputaddr)); cau_data_write(*(uint32_t *)(inputaddr));
inputaddr += 4U; inputaddr += 4U;
@ -168,7 +170,8 @@ static ErrStatus cau_des_calculate(uint8_t *input, uint32_t in_length, uint8_t *
counter++; counter++;
} while((DESBUSY_TIMEOUT != counter) && (RESET != busystatus)); } while((DESBUSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) { if(RESET != busystatus)
{
return ERROR; return ERROR;
} else { } else {
/* read the output block from the output FIFO */ /* read the output block from the output FIFO */

41
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cau_tdes.c
View File

@ -1,34 +1,34 @@
/*! /*!
\file gd32h7xx_cau_tdes.c \file gd32h7xx_cau_tdes.c
\brief CAU TDES driver \brief CAU TDES driver
\version 2024-01-05, V1.2.0, firmware for GD32H7xx \version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/ */
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -165,11 +165,13 @@ static ErrStatus cau_tdes_calculate(uint8_t *input, uint32_t in_length, uint8_t
uint32_t busystatus = 0U; uint32_t busystatus = 0U;
/* the clock is not enabled or there is no embedded CAU peripheral */ /* the clock is not enabled or there is no embedded CAU peripheral */
if(DISABLE == cau_enable_state_get()) { if(DISABLE == cau_enable_state_get())
{
return ERROR; return ERROR;
} }
for(i = 0U; i < in_length; i += 8U) { for(i = 0U; i < in_length; i += 8U)
{
/* write data to the IN FIFO */ /* write data to the IN FIFO */
cau_data_write(*(uint32_t *)(inputaddr)); cau_data_write(*(uint32_t *)(inputaddr));
inputaddr += 4U; inputaddr += 4U;
@ -183,7 +185,8 @@ static ErrStatus cau_tdes_calculate(uint8_t *input, uint32_t in_length, uint8_t
counter++; counter++;
} while((TDESBSY_TIMEOUT != counter) && (RESET != busystatus)); } while((TDESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) { if(RESET != busystatus)
{
return ERROR; return ERROR;
} else { } else {
/* read the output block from the output FIFO */ /* read the output block from the output FIFO */

168
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cmp.c
View File

@ -44,12 +44,14 @@ OF SUCH DAMAGE.
*/ */
void cmp_deinit(cmp_enum cmp_periph) void cmp_deinit(cmp_enum cmp_periph)
{ {
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
CMP0_CS &= ((uint32_t)0x00000000U); CMP0_CS &= ((uint32_t)0x00000000U);
CMP_IFC &= ((uint32_t)0xFFFEFFFFU); CMP_IFC &= ((uint32_t)0xFFFEFFFFU);
CMP_STAT &= ((uint32_t)0xFFFEFFFEU); CMP_STAT &= ((uint32_t)0xFFFEFFFEU);
CMP_SR &= ((uint32_t)0x00000000U); CMP_SR &= ((uint32_t)0x00000000U);
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
CMP1_CS &= ((uint32_t)0x00000000U); CMP1_CS &= ((uint32_t)0x00000000U);
CMP_IFC &= ((uint32_t)0xFFFDFFFFU); CMP_IFC &= ((uint32_t)0xFFFDFFFFU);
CMP_STAT &= ((uint32_t)0xFFFDFFFDU); CMP_STAT &= ((uint32_t)0xFFFDFFFDU);
@ -88,13 +90,15 @@ void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t invert
{ {
uint32_t temp = 0U; uint32_t temp = 0U;
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
/* initialize comparator 0 mode */ /* initialize comparator 0 mode */
temp = CMP0_CS; temp = CMP0_CS;
temp &= ~(uint32_t)(CMP_CS_CMPXM | CMP_CS_CMPXMISEL | CMP_CS_CMPXHST); temp &= ~(uint32_t)(CMP_CS_CMPXM | CMP_CS_CMPXMISEL | CMP_CS_CMPXHST);
temp |= (uint32_t)(operating_mode | inverting_input | output_hysteresis); temp |= (uint32_t)(operating_mode | inverting_input | output_hysteresis);
CMP0_CS = temp; CMP0_CS = temp;
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
/* initialize comparator 1 mode */ /* initialize comparator 1 mode */
temp = CMP1_CS; temp = CMP1_CS;
temp &= ~(uint32_t)(CMP_CS_CMPXM | CMP_CS_CMPXMISEL | CMP_CS_CMPXHST); temp &= ~(uint32_t)(CMP_CS_CMPXM | CMP_CS_CMPXMISEL | CMP_CS_CMPXHST);
@ -119,12 +123,14 @@ void cmp_noninverting_input_select(cmp_enum cmp_periph, uint32_t noninverting_in
{ {
uint32_t temp = 0U; uint32_t temp = 0U;
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
temp = CMP0_CS; temp = CMP0_CS;
temp &= ~(uint32_t)CMP_CS_CMPXPSEL; temp &= ~(uint32_t)CMP_CS_CMPXPSEL;
temp |= (uint32_t)noninverting_input; temp |= (uint32_t)noninverting_input;
CMP0_CS = temp; CMP0_CS = temp;
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
temp = CMP1_CS; temp = CMP1_CS;
temp &= ~(uint32_t)CMP_CS_CMPXPSEL; temp &= ~(uint32_t)CMP_CS_CMPXPSEL;
temp |= (uint32_t)noninverting_input; temp |= (uint32_t)noninverting_input;
@ -148,21 +154,25 @@ void cmp_output_init(cmp_enum cmp_periph, uint32_t output_polarity)
{ {
uint32_t temp = 0U; uint32_t temp = 0U;
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
/* initialize comparator 0 output */ /* initialize comparator 0 output */
temp = CMP0_CS; temp = CMP0_CS;
/* output polarity */ /* output polarity */
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){ if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity)
{
temp |= (uint32_t)CMP_CS_CMPXPL; temp |= (uint32_t)CMP_CS_CMPXPL;
}else{ }else{
temp &= ~(uint32_t)CMP_CS_CMPXPL; temp &= ~(uint32_t)CMP_CS_CMPXPL;
} }
CMP0_CS = temp; CMP0_CS = temp;
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
/* initialize comparator 1 output */ /* initialize comparator 1 output */
temp = CMP1_CS; temp = CMP1_CS;
/* output polarity */ /* output polarity */
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){ if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity)
{
temp |= (uint32_t)CMP_CS_CMPXPL; temp |= (uint32_t)CMP_CS_CMPXPL;
}else{ }else{
temp &= ~(uint32_t)CMP_CS_CMPXPL; temp &= ~(uint32_t)CMP_CS_CMPXPL;
@ -194,9 +204,11 @@ void cmp_output_init(cmp_enum cmp_periph, uint32_t output_polarity)
*/ */
void cmp_output_mux_config(cmp_enum cmp_periph, uint32_t cmp_output_sel) void cmp_output_mux_config(cmp_enum cmp_periph, uint32_t cmp_output_sel)
{ {
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
CMP_SR &= ~(uint32_t)cmp_output_sel; CMP_SR &= ~(uint32_t)cmp_output_sel;
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
CMP_SR |= cmp_output_sel; CMP_SR |= cmp_output_sel;
}else{ }else{
} }
@ -207,7 +219,7 @@ void cmp_output_mux_config(cmp_enum cmp_periph, uint32_t cmp_output_sel)
\param[in] cmp_periph \param[in] cmp_periph
\arg CMP0: comparator 0 \arg CMP0: comparator 0
\arg CMP1: comparator 1 \arg CMP1: comparator 1
\param[in] blanking_source_selection \param[in] blanking_source_selection
\arg CMP_BLANKING_NONE: CMP no blanking source \arg CMP_BLANKING_NONE: CMP no blanking source
\arg CMP_BLANKING_TIMER0_OC0: CMP TIMER0_CH0 output compare signal selected as blanking source \arg CMP_BLANKING_TIMER0_OC0: CMP TIMER0_CH0 output compare signal selected as blanking source
\arg CMP_BLANKING_TIMER1_OC2: CMP TIMER1_CH2 output compare signal selected as blanking source \arg CMP_BLANKING_TIMER1_OC2: CMP TIMER1_CH2 output compare signal selected as blanking source
@ -222,12 +234,14 @@ void cmp_blanking_init(cmp_enum cmp_periph, uint32_t blanking_source_selection)
{ {
uint32_t temp = 0U; uint32_t temp = 0U;
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
temp = CMP0_CS; temp = CMP0_CS;
temp &= ~(uint32_t)CMP_CS_CMPXBLK; temp &= ~(uint32_t)CMP_CS_CMPXBLK;
temp |= (uint32_t)blanking_source_selection; temp |= (uint32_t)blanking_source_selection;
CMP0_CS = temp; CMP0_CS = temp;
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
temp = CMP1_CS; temp = CMP1_CS;
temp &= ~(uint32_t)CMP_CS_CMPXBLK; temp &= ~(uint32_t)CMP_CS_CMPXBLK;
temp |= (uint32_t)blanking_source_selection; temp |= (uint32_t)blanking_source_selection;
@ -246,9 +260,11 @@ void cmp_blanking_init(cmp_enum cmp_periph, uint32_t blanking_source_selection)
*/ */
void cmp_enable(cmp_enum cmp_periph) void cmp_enable(cmp_enum cmp_periph)
{ {
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
CMP0_CS |= (uint32_t)CMP_CS_CMPXEN; CMP0_CS |= (uint32_t)CMP_CS_CMPXEN;
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
CMP1_CS |= (uint32_t)CMP_CS_CMPXEN; CMP1_CS |= (uint32_t)CMP_CS_CMPXEN;
}else{ }else{
} }
@ -264,9 +280,11 @@ void cmp_enable(cmp_enum cmp_periph)
*/ */
void cmp_disable(cmp_enum cmp_periph) void cmp_disable(cmp_enum cmp_periph)
{ {
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
CMP0_CS &= ~(uint32_t)CMP_CS_CMPXEN; CMP0_CS &= ~(uint32_t)CMP_CS_CMPXEN;
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
CMP1_CS &= ~(uint32_t)CMP_CS_CMPXEN; CMP1_CS &= ~(uint32_t)CMP_CS_CMPXEN;
}else{ }else{
} }
@ -304,10 +322,12 @@ void cmp_window_disable(void)
*/ */
void cmp_lock_enable(cmp_enum cmp_periph) void cmp_lock_enable(cmp_enum cmp_periph)
{ {
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
/* lock CMP0 */ /* lock CMP0 */
CMP0_CS |= (uint32_t)CMP_CS_CMPXLK; CMP0_CS |= (uint32_t)CMP_CS_CMPXLK;
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
/* lock CMP1 */ /* lock CMP1 */
CMP1_CS |= (uint32_t)CMP_CS_CMPXLK; CMP1_CS |= (uint32_t)CMP_CS_CMPXLK;
}else{ }else{
@ -324,9 +344,11 @@ void cmp_lock_enable(cmp_enum cmp_periph)
*/ */
void cmp_voltage_scaler_enable(cmp_enum cmp_periph) void cmp_voltage_scaler_enable(cmp_enum cmp_periph)
{ {
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
CMP0_CS |= (uint32_t)CMP_CS_CMPXSEN; CMP0_CS |= (uint32_t)CMP_CS_CMPXSEN;
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
CMP1_CS |= (uint32_t)CMP_CS_CMPXSEN; CMP1_CS |= (uint32_t)CMP_CS_CMPXSEN;
}else{ }else{
} }
@ -342,15 +364,17 @@ void cmp_voltage_scaler_enable(cmp_enum cmp_periph)
*/ */
void cmp_voltage_scaler_disable(cmp_enum cmp_periph) void cmp_voltage_scaler_disable(cmp_enum cmp_periph)
{ {
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
CMP0_CS &= ~(uint32_t)CMP_CS_CMPXSEN; CMP0_CS &= ~(uint32_t)CMP_CS_CMPXSEN;
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
CMP1_CS &= ~(uint32_t)CMP_CS_CMPXSEN; CMP1_CS &= ~(uint32_t)CMP_CS_CMPXSEN;
}else{ }else{
} }
} }
/*! /*!
\brief enable the scaler bridge \brief enable the scaler bridge
\param[in] cmp_periph \param[in] cmp_periph
\arg CMP0: comparator 0 \arg CMP0: comparator 0
@ -360,9 +384,11 @@ void cmp_voltage_scaler_disable(cmp_enum cmp_periph)
*/ */
void cmp_scaler_bridge_enable(cmp_enum cmp_periph) void cmp_scaler_bridge_enable(cmp_enum cmp_periph)
{ {
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
CMP0_CS |= (uint32_t)CMP_CS_CMPXBEN; CMP0_CS |= (uint32_t)CMP_CS_CMPXBEN;
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
CMP1_CS |= (uint32_t)CMP_CS_CMPXBEN; CMP1_CS |= (uint32_t)CMP_CS_CMPXBEN;
}else{ }else{
} }
@ -378,9 +404,11 @@ void cmp_scaler_bridge_enable(cmp_enum cmp_periph)
*/ */
void cmp_scaler_bridge_disable(cmp_enum cmp_periph) void cmp_scaler_bridge_disable(cmp_enum cmp_periph)
{ {
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
CMP0_CS &= ~(uint32_t)CMP_CS_CMPXBEN; CMP0_CS &= ~(uint32_t)CMP_CS_CMPXBEN;
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
CMP1_CS &= ~(uint32_t)CMP_CS_CMPXBEN; CMP1_CS &= ~(uint32_t)CMP_CS_CMPXBEN;
}else{ }else{
} }
@ -396,16 +424,19 @@ void cmp_scaler_bridge_disable(cmp_enum cmp_periph)
*/ */
uint32_t cmp_output_level_get(cmp_enum cmp_periph) uint32_t cmp_output_level_get(cmp_enum cmp_periph)
{ {
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
/* get output level of CMP0 */ /* get output level of CMP0 */
if((uint32_t)RESET != (CMP_STAT & CMP_STAT_CMP0O)) { if((uint32_t)RESET != (CMP_STAT & CMP_STAT_CMP0O))
{
return CMP_OUTPUTLEVEL_HIGH; return CMP_OUTPUTLEVEL_HIGH;
}else{ }else{
return CMP_OUTPUTLEVEL_LOW; return CMP_OUTPUTLEVEL_LOW;
} }
}else{ }else{
/* get output level of CMP1 */ /* get output level of CMP1 */
if((uint32_t)RESET != (CMP_STAT & CMP_STAT_CMP1O)) { if((uint32_t)RESET != (CMP_STAT & CMP_STAT_CMP1O))
{
return CMP_OUTPUTLEVEL_HIGH; return CMP_OUTPUTLEVEL_HIGH;
}else{ }else{
return CMP_OUTPUTLEVEL_LOW; return CMP_OUTPUTLEVEL_LOW;
@ -426,16 +457,22 @@ uint32_t cmp_output_level_get(cmp_enum cmp_periph)
FlagStatus cmp_flag_get(cmp_enum cmp_periph, uint32_t flag) FlagStatus cmp_flag_get(cmp_enum cmp_periph, uint32_t flag)
{ {
FlagStatus reval = RESET; FlagStatus reval = RESET;
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
if(CMP_FLAG_COMPARE == flag){ {
if(0U != (CMP_STAT & CMP_STAT_CMP0IF)){ if(CMP_FLAG_COMPARE == flag)
{
if(0U != (CMP_STAT & CMP_STAT_CMP0IF))
{
reval = SET; reval = SET;
} }
} }
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
if(CMP_FLAG_COMPARE == flag){ {
if(0U != (CMP_STAT & CMP_STAT_CMP1IF)){ if(CMP_FLAG_COMPARE == flag)
{
if(0U != (CMP_STAT & CMP_STAT_CMP1IF))
{
reval = SET; reval = SET;
} }
} }
@ -455,12 +492,16 @@ FlagStatus cmp_flag_get(cmp_enum cmp_periph, uint32_t flag)
*/ */
void cmp_flag_clear(cmp_enum cmp_periph, uint32_t flag) void cmp_flag_clear(cmp_enum cmp_periph, uint32_t flag)
{ {
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
if(CMP_FLAG_COMPARE == flag){ {
if(CMP_FLAG_COMPARE == flag)
{
CMP_IFC |= (uint32_t)CMP_IFC_CMP0IC; CMP_IFC |= (uint32_t)CMP_IFC_CMP0IC;
} }
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
if(CMP_FLAG_COMPARE == flag){ {
if(CMP_FLAG_COMPARE == flag)
{
CMP_IFC |= (uint32_t)CMP_IFC_CMP1IC; CMP_IFC |= (uint32_t)CMP_IFC_CMP1IC;
} }
}else{ }else{
@ -480,10 +521,12 @@ void cmp_flag_clear(cmp_enum cmp_periph, uint32_t flag)
*/ */
void cmp_interrupt_enable(cmp_enum cmp_periph, uint32_t interrupt) void cmp_interrupt_enable(cmp_enum cmp_periph, uint32_t interrupt)
{ {
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
/* enable CMP0 interrupt */ /* enable CMP0 interrupt */
CMP0_CS |= (uint32_t)interrupt; CMP0_CS |= (uint32_t)interrupt;
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
/* enable CMP1 interrupt */ /* enable CMP1 interrupt */
CMP1_CS |= (uint32_t)interrupt; CMP1_CS |= (uint32_t)interrupt;
}else{ }else{
@ -503,10 +546,12 @@ void cmp_interrupt_enable(cmp_enum cmp_periph, uint32_t interrupt)
*/ */
void cmp_interrupt_disable(cmp_enum cmp_periph, uint32_t interrupt) void cmp_interrupt_disable(cmp_enum cmp_periph, uint32_t interrupt)
{ {
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
{
/* disable CMP0 interrupt */ /* disable CMP0 interrupt */
CMP0_CS &= ~(uint32_t)interrupt; CMP0_CS &= ~(uint32_t)interrupt;
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
{
/* disable CMP1 interrupt */ /* disable CMP1 interrupt */
CMP1_CS &= ~(uint32_t)interrupt; CMP1_CS &= ~(uint32_t)interrupt;
}else{ }else{
@ -527,15 +572,19 @@ FlagStatus cmp_interrupt_flag_get(cmp_enum cmp_periph, uint32_t flag)
{ {
uint32_t intstatus = 0U, flagstatus = 0U; uint32_t intstatus = 0U, flagstatus = 0U;
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
if(CMP_INT_FLAG_COMPARE == flag){ {
if(CMP_INT_FLAG_COMPARE == flag)
{
/* get the corresponding flag bit status */ /* get the corresponding flag bit status */
flagstatus = CMP_STAT & CMP_STAT_CMP0IF; flagstatus = CMP_STAT & CMP_STAT_CMP0IF;
/* get the interrupt enable bit status */ /* get the interrupt enable bit status */
intstatus = CMP0_CS & CMP_CS_CMPXINTEN; intstatus = CMP0_CS & CMP_CS_CMPXINTEN;
} }
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
if(CMP_INT_FLAG_COMPARE == flag){ {
if(CMP_INT_FLAG_COMPARE == flag)
{
/* get the corresponding flag bit status */ /* get the corresponding flag bit status */
flagstatus = CMP_STAT & CMP_STAT_CMP1IF; flagstatus = CMP_STAT & CMP_STAT_CMP1IF;
/* get the interrupt enable bit status */ /* get the interrupt enable bit status */
@ -544,7 +593,8 @@ FlagStatus cmp_interrupt_flag_get(cmp_enum cmp_periph, uint32_t flag)
}else{ }else{
} }
if((0U != flagstatus) && (0U != intstatus)){ if((0U != flagstatus) && (0U != intstatus))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -564,12 +614,16 @@ FlagStatus cmp_interrupt_flag_get(cmp_enum cmp_periph, uint32_t flag)
void cmp_interrupt_flag_clear(cmp_enum cmp_periph, uint32_t flag) void cmp_interrupt_flag_clear(cmp_enum cmp_periph, uint32_t flag)
{ {
/* clear CMP interrupt flag */ /* clear CMP interrupt flag */
if(CMP0 == cmp_periph){ if(CMP0 == cmp_periph)
if(CMP_INT_FLAG_COMPARE == flag){ {
if(CMP_INT_FLAG_COMPARE == flag)
{
CMP_IFC |= (uint32_t)CMP_IFC_CMP0IC; CMP_IFC |= (uint32_t)CMP_IFC_CMP0IC;
} }
}else if(CMP1 == cmp_periph){ }else if(CMP1 == cmp_periph)
if(CMP_INT_FLAG_COMPARE == flag){ {
if(CMP_INT_FLAG_COMPARE == flag)
{
CMP_IFC |= (uint32_t)CMP_IFC_CMP1IC; CMP_IFC |= (uint32_t)CMP_IFC_CMP1IC;
} }
}else{ }else{

15
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cpdm.c
View File

@ -154,7 +154,8 @@ FlagStatus cpdm_delayline_length_valid_flag_get(uint32_t cpdm_periph)
uint32_t reg = 0U; uint32_t reg = 0U;
reg = CPDM_CFG(cpdm_periph); reg = CPDM_CFG(cpdm_periph);
if(reg & CPDM_DLLENF_MASK) { if(reg & CPDM_DLLENF_MASK)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -214,21 +215,25 @@ void cpdm_clock_output(uint32_t cpdm_periph, cpdm_output_phase_enum output_clock
reg |= CPDM_MAX_PHASE; reg |= CPDM_MAX_PHASE;
CPDM_CFG(cpdm_periph) = (uint32_t)reg; CPDM_CFG(cpdm_periph) = (uint32_t)reg;
for(delay_count = 0U; delay_count <= CPDM_MAX_DELAY_STEP_COUNT; delay_count++) { for(delay_count = 0U; delay_count <= CPDM_MAX_DELAY_STEP_COUNT; delay_count++)
{
reg = CPDM_CFG(cpdm_periph); reg = CPDM_CFG(cpdm_periph);
reg &= CPDM_DLSTCNT_MASK; reg &= CPDM_DLSTCNT_MASK;
/* configure delay line step count */ /* configure delay line step count */
reg |= delay_count << CPDM_DLSTCNT_OFFSET; reg |= delay_count << CPDM_DLSTCNT_OFFSET;
CPDM_CFG(cpdm_periph) = (uint32_t)reg; CPDM_CFG(cpdm_periph) = (uint32_t)reg;
while(SET == (CPDM_CFG(cpdm_periph) & CPDM_CFG_DLLENF)) { while(SET == (CPDM_CFG(cpdm_periph) & CPDM_CFG_DLLENF))
{
} }
while(RESET == (CPDM_CFG(cpdm_periph) & CPDM_CFG_DLLENF)) { while(RESET == (CPDM_CFG(cpdm_periph) & CPDM_CFG_DLLENF))
{
} }
reg_cfg = CPDM_CFG(cpdm_periph); reg_cfg = CPDM_CFG(cpdm_periph);
if((((reg_cfg >> CPDM_DLLEN_OFFSET) & CPDM_DLLEN_10_0_MASK) > 0U) && if((((reg_cfg >> CPDM_DLLEN_OFFSET) & CPDM_DLLEN_10_0_MASK) > 0U) &&
((RESET == (reg_cfg & CPDM_DLLEN_11)) || (RESET == (reg_cfg & CPDM_DLLEN_10)))) { ((RESET == (reg_cfg & CPDM_DLLEN_11)) || (RESET == (reg_cfg & CPDM_DLLEN_10))))
{
break; break;
} }
} }

24
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_crc.c
View File

@ -195,11 +195,14 @@ void crc_polynomial_set(uint32_t poly)
*/ */
uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format) uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format)
{ {
if(INPUT_FORMAT_WORD == data_format) { if(INPUT_FORMAT_WORD == data_format)
{
REG32(CRC) = sdata; REG32(CRC) = sdata;
} else if(INPUT_FORMAT_HALFWORD == data_format) { } else if(INPUT_FORMAT_HALFWORD == data_format)
{
REG16(CRC) = (uint16_t)sdata; REG16(CRC) = (uint16_t)sdata;
} else if(INPUT_FORMAT_BYTE == data_format) { } else if(INPUT_FORMAT_BYTE == data_format)
{
REG8(CRC) = (uint8_t)sdata; REG8(CRC) = (uint8_t)sdata;
} else { } else {
} }
@ -226,19 +229,24 @@ uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_forma
uint32_t *data32; uint32_t *data32;
uint32_t index; uint32_t index;
if(INPUT_FORMAT_WORD == data_format) { if(INPUT_FORMAT_WORD == data_format)
{
data32 = (uint32_t *)array; data32 = (uint32_t *)array;
for(index = 0U; index < size; index++) { for(index = 0U; index < size; index++)
{
REG32(CRC) = data32[index]; REG32(CRC) = data32[index];
} }
} else if(INPUT_FORMAT_HALFWORD == data_format) { } else if(INPUT_FORMAT_HALFWORD == data_format)
{
data16 = (uint16_t *)array; data16 = (uint16_t *)array;
for(index = 0U; index < size; index++) { for(index = 0U; index < size; index++)
{
REG16(CRC) = data16[index]; REG16(CRC) = data16[index];
} }
} else { } else {
data8 = (uint8_t *)array; data8 = (uint8_t *)array;
for(index = 0U; index < size; index++) { for(index = 0U; index < size; index++)
{
REG8(CRC) = data8[index]; REG8(CRC) = data8[index];
} }
} }

92
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_ctc.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -118,7 +118,7 @@ void ctc_hardware_trim_mode_config(uint32_t hardmode)
CTC_CTL0 |= (uint32_t)hardmode; CTC_CTL0 |= (uint32_t)hardmode;
} }
/*! /*!
\brief configure reference signal source polarity \brief configure reference signal source polarity
\param[in] polarity: reference signal source edge \param[in] polarity: reference signal source edge
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
@ -218,7 +218,8 @@ uint16_t ctc_counter_capture_value_read(void)
*/ */
FlagStatus ctc_counter_direction_read(void) FlagStatus ctc_counter_direction_read(void)
{ {
if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){ if(RESET != (CTC_STAT & CTC_STAT_REFDIR))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -254,10 +255,10 @@ uint8_t ctc_irc48m_trim_value_read(void)
/*! /*!
\brief get CTC flag \brief get CTC flag
\param[in] flag: the CTC flag \param[in] flag: the CTC flag
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg CTC_FLAG_CKOK: clock trim OK flag \arg CTC_FLAG_CKOK: clock trim OK flag
\arg CTC_FLAG_CKWARN: clock trim warning flag \arg CTC_FLAG_CKWARN: clock trim warning flag
\arg CTC_FLAG_ERR: error flag \arg CTC_FLAG_ERR: error flag
\arg CTC_FLAG_EREF: expect reference flag \arg CTC_FLAG_EREF: expect reference flag
\arg CTC_FLAG_CKERR: clock trim error flag \arg CTC_FLAG_CKERR: clock trim error flag
\arg CTC_FLAG_REFMISS: reference sync pulse miss flag \arg CTC_FLAG_REFMISS: reference sync pulse miss flag
@ -267,7 +268,8 @@ uint8_t ctc_irc48m_trim_value_read(void)
*/ */
FlagStatus ctc_flag_get(uint32_t flag) FlagStatus ctc_flag_get(uint32_t flag)
{ {
if(RESET != (CTC_STAT & flag)){ if(RESET != (CTC_STAT & flag))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -279,8 +281,8 @@ FlagStatus ctc_flag_get(uint32_t flag)
\param[in] flag: the CTC flag \param[in] flag: the CTC flag
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg CTC_FLAG_CKOK: clock trim OK flag \arg CTC_FLAG_CKOK: clock trim OK flag
\arg CTC_FLAG_CKWARN: clock trim warning flag \arg CTC_FLAG_CKWARN: clock trim warning flag
\arg CTC_FLAG_ERR: error flag \arg CTC_FLAG_ERR: error flag
\arg CTC_FLAG_EREF: expect reference flag \arg CTC_FLAG_EREF: expect reference flag
\arg CTC_FLAG_CKERR: clock trim error flag \arg CTC_FLAG_CKERR: clock trim error flag
\arg CTC_FLAG_REFMISS: reference sync pulse miss flag \arg CTC_FLAG_REFMISS: reference sync pulse miss flag
@ -290,7 +292,8 @@ FlagStatus ctc_flag_get(uint32_t flag)
*/ */
void ctc_flag_clear(uint32_t flag) void ctc_flag_clear(uint32_t flag)
{ {
if(RESET != (flag & CTC_FLAG_MASK)){ if(RESET != (flag & CTC_FLAG_MASK))
{
CTC_INTC |= CTC_INTC_ERRIC; CTC_INTC |= CTC_INTC_ERRIC;
}else{ }else{
CTC_INTC |= flag; CTC_INTC |= flag;
@ -301,16 +304,16 @@ void ctc_flag_clear(uint32_t flag)
\brief enable the CTC interrupt \brief enable the CTC interrupt
\param[in] interrupt: CTC interrupt enable source \param[in] interrupt: CTC interrupt enable source
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg CTC_INT_CKOK: clock trim OK interrupt \arg CTC_INT_CKOK: clock trim OK interrupt
\arg CTC_INT_CKWARN: clock trim warning interrupt \arg CTC_INT_CKWARN: clock trim warning interrupt
\arg CTC_INT_ERR: error interrupt \arg CTC_INT_ERR: error interrupt
\arg CTC_INT_EREF: expect reference interrupt \arg CTC_INT_EREF: expect reference interrupt
\param[out] none \param[out] none
\retval none \retval none
*/ */
void ctc_interrupt_enable(uint32_t interrupt) void ctc_interrupt_enable(uint32_t interrupt)
{ {
CTC_CTL0 |= (uint32_t)interrupt; CTC_CTL0 |= (uint32_t)interrupt;
} }
/*! /*!
@ -318,15 +321,15 @@ void ctc_interrupt_enable(uint32_t interrupt)
\param[in] interrupt: CTC interrupt disable source \param[in] interrupt: CTC interrupt disable source
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg CTC_INT_CKOK: clock trim OK interrupt \arg CTC_INT_CKOK: clock trim OK interrupt
\arg CTC_INT_CKWARN: clock trim warning interrupt \arg CTC_INT_CKWARN: clock trim warning interrupt
\arg CTC_INT_ERR: error interrupt \arg CTC_INT_ERR: error interrupt
\arg CTC_INT_EREF: expect reference interrupt \arg CTC_INT_EREF: expect reference interrupt
\param[out] none \param[out] none
\retval none \retval none
*/ */
void ctc_interrupt_disable(uint32_t interrupt) void ctc_interrupt_disable(uint32_t interrupt)
{ {
CTC_CTL0 &= (uint32_t)(~interrupt); CTC_CTL0 &= (uint32_t)(~interrupt);
} }
/*! /*!
@ -334,11 +337,11 @@ void ctc_interrupt_disable(uint32_t interrupt)
\param[in] int_flag: the CTC interrupt flag \param[in] int_flag: the CTC interrupt flag
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg CTC_INT_FLAG_CKOK: clock trim OK interrupt flag \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt flag
\arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt flag \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt flag
\arg CTC_INT_FLAG_ERR: error interrupt flag \arg CTC_INT_FLAG_ERR: error interrupt flag
\arg CTC_INT_FLAG_EREF: expect reference interrupt flag \arg CTC_INT_FLAG_EREF: expect reference interrupt flag
\arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt flag \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt flag
\arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt flag \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt flag
\arg CTC_INT_FLAG_TRIMERR: trim value error interrupt flag \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt flag
\param[out] none \param[out] none
\retval FlagStatus: SET or RESET \retval FlagStatus: SET or RESET
@ -346,18 +349,20 @@ void ctc_interrupt_disable(uint32_t interrupt)
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag) FlagStatus ctc_interrupt_flag_get(uint32_t int_flag)
{ {
uint32_t interrupt_flag = 0U, intenable = 0U; uint32_t interrupt_flag = 0U, intenable = 0U;
/* check whether the interrupt is enabled */ /* check whether the interrupt is enabled */
if(RESET != (int_flag & CTC_FLAG_MASK)){ if(RESET != (int_flag & CTC_FLAG_MASK))
{
intenable = CTC_CTL0 & CTC_CTL0_ERRIE; intenable = CTC_CTL0 & CTC_CTL0_ERRIE;
}else{ }else{
intenable = CTC_CTL0 & int_flag; intenable = CTC_CTL0 & int_flag;
} }
/* get interrupt flag status */ /* get interrupt flag status */
interrupt_flag = CTC_STAT & int_flag; interrupt_flag = CTC_STAT & int_flag;
if(interrupt_flag && intenable){ if(interrupt_flag && intenable)
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -370,17 +375,18 @@ FlagStatus ctc_interrupt_flag_get(uint32_t int_flag)
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg CTC_INT_FLAG_CKOK: clock trim OK interrupt flag \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt flag
\arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt flag \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt flag
\arg CTC_INT_FLAG_ERR: error interrupt flag \arg CTC_INT_FLAG_ERR: error interrupt flag
\arg CTC_INT_FLAG_EREF: expect reference interrupt flag \arg CTC_INT_FLAG_EREF: expect reference interrupt flag
\arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt flag \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt flag
\arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt flag \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt flag
\arg CTC_INT_FLAG_TRIMERR: trim value error interrupt flag \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt flag
\param[out] none \param[out] none
\retval none \retval none
*/ */
void ctc_interrupt_flag_clear(uint32_t int_flag) void ctc_interrupt_flag_clear(uint32_t int_flag)
{ {
if(RESET != (int_flag & CTC_FLAG_MASK)){ if(RESET != (int_flag & CTC_FLAG_MASK))
{
CTC_INTC |= CTC_INTC_ERRIC; CTC_INTC |= CTC_INTC_ERRIC;
}else{ }else{
CTC_INTC |= int_flag; CTC_INTC |= int_flag;

179
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_dac.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -51,7 +51,8 @@ OF SUCH DAMAGE.
*/ */
void dac_deinit(uint32_t dac_periph) void dac_deinit(uint32_t dac_periph)
{ {
switch(dac_periph){ switch(dac_periph)
{
case DAC0: case DAC0:
/* reset DAC0 */ /* reset DAC0 */
rcu_periph_reset_enable(RCU_DACRST); rcu_periph_reset_enable(RCU_DACRST);
@ -71,9 +72,11 @@ void dac_deinit(uint32_t dac_periph)
*/ */
void dac_enable(uint32_t dac_periph, uint8_t dac_out) void dac_enable(uint32_t dac_periph, uint8_t dac_out)
{ {
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DEN0; DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DEN0;
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DEN1; DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DEN1;
}else{ }else{
/* illegal parameters */ /* illegal parameters */
@ -89,9 +92,11 @@ void dac_enable(uint32_t dac_periph, uint8_t dac_out)
*/ */
void dac_disable(uint32_t dac_periph, uint8_t dac_out) void dac_disable(uint32_t dac_periph, uint8_t dac_out)
{ {
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DEN0); DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DEN0);
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DEN1); DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DEN1);
}else{ }else{
/* illegal parameters */ /* illegal parameters */
@ -107,9 +112,11 @@ void dac_disable(uint32_t dac_periph, uint8_t dac_out)
*/ */
void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out) void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out)
{ {
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DDMAEN0; DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DDMAEN0;
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DDMAEN1; DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DDMAEN1;
}else{ }else{
/* illegal parameters */ /* illegal parameters */
@ -125,9 +132,11 @@ void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out)
*/ */
void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out) void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out)
{ {
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DDMAEN0); DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DDMAEN0);
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DDMAEN1); DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DDMAEN1);
}else{ }else{
/* illegal parameters */ /* illegal parameters */
@ -153,11 +162,13 @@ void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out)
*/ */
void dac_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t mode) void dac_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t mode)
{ {
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
/* configure DAC0 mode */ /* configure DAC0 mode */
DAC_MDCR(dac_periph) &= ~(uint32_t)DAC_MDCR_MODE0; DAC_MDCR(dac_periph) &= ~(uint32_t)DAC_MDCR_MODE0;
DAC_MDCR(dac_periph) |= mode; DAC_MDCR(dac_periph) |= mode;
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
/* configure DAC1 mode */ /* configure DAC1 mode */
DAC_MDCR(dac_periph) &= ~(uint32_t)DAC_MDCR_MODE1; DAC_MDCR(dac_periph) &= ~(uint32_t)DAC_MDCR_MODE1;
DAC_MDCR(dac_periph) |= (mode << OUT1_REG_OFFSET); DAC_MDCR(dac_periph) |= (mode << OUT1_REG_OFFSET);
@ -176,10 +187,12 @@ void dac_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t mode)
uint32_t dac_trimming_value_get(uint32_t dac_periph, uint32_t dac_out) uint32_t dac_trimming_value_get(uint32_t dac_periph, uint32_t dac_out)
{ {
uint32_t tmp = 0U; uint32_t tmp = 0U;
if(DAC_OUT0 == dac_out) { if(DAC_OUT0 == dac_out)
{
/* get the DAC_OUT_0 trimming value */ /* get the DAC_OUT_0 trimming value */
tmp = DAC_CALR(dac_periph) & DAC_CALR_OTV0; tmp = DAC_CALR(dac_periph) & DAC_CALR_OTV0;
} else if(DAC_OUT1 == dac_out) { } else if(DAC_OUT1 == dac_out)
{
/* get the DAC_OUT_1 trimming value */ /* get the DAC_OUT_1 trimming value */
tmp = (DAC_CALR(dac_periph) & DAC_CALR_OTV1) >> OUT1_REG_OFFSET; tmp = (DAC_CALR(dac_periph) & DAC_CALR_OTV1) >> OUT1_REG_OFFSET;
} else { } else {
@ -198,16 +211,18 @@ uint32_t dac_trimming_value_get(uint32_t dac_periph, uint32_t dac_out)
void dac_trimming_value_set(uint32_t dac_periph, uint32_t dac_out, uint32_t trim_value) void dac_trimming_value_set(uint32_t dac_periph, uint32_t dac_out, uint32_t trim_value)
{ {
uint32_t tmp = 0U; uint32_t tmp = 0U;
/* get the trimming value */ /* get the trimming value */
tmp = DAC_CALR(dac_periph); tmp = DAC_CALR(dac_periph);
if(DAC_OUT0 == dac_out) { if(DAC_OUT0 == dac_out)
{
/* set the DACx_OUT0 trimming value */ /* set the DACx_OUT0 trimming value */
tmp &= ~(uint32_t)DAC_CALR_OTV0; tmp &= ~(uint32_t)DAC_CALR_OTV0;
tmp |= (trim_value & DAC_CALR_OTV0); tmp |= (trim_value & DAC_CALR_OTV0);
DAC_CALR(dac_periph) = tmp; DAC_CALR(dac_periph) = tmp;
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
/* set the DACx_OUT1 trimming value */ /* set the DACx_OUT1 trimming value */
tmp &= ~(uint32_t)DAC_CALR_OTV1; tmp &= ~(uint32_t)DAC_CALR_OTV1;
tmp |= ((trim_value << OUT1_REG_OFFSET) & DAC_CALR_OTV1); tmp |= ((trim_value << OUT1_REG_OFFSET) & DAC_CALR_OTV1);
@ -225,10 +240,12 @@ void dac_trimming_value_set(uint32_t dac_periph, uint32_t dac_out, uint32_t trim
*/ */
void dac_trimming_enable(uint32_t dac_periph, uint32_t dac_out) void dac_trimming_enable(uint32_t dac_periph, uint32_t dac_out)
{ {
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
/* enable the DACx_OUT0 trimming */ /* enable the DACx_OUT0 trimming */
DAC_CTL0(dac_periph) |= DAC_CTL0_CALEN0; DAC_CTL0(dac_periph) |= DAC_CTL0_CALEN0;
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
/* enable the DACx_OUT1 trimming */ /* enable the DACx_OUT1 trimming */
DAC_CTL0(dac_periph) |= DAC_CTL0_CALEN1; DAC_CTL0(dac_periph) |= DAC_CTL0_CALEN1;
}else{ }else{
@ -247,10 +264,12 @@ uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out)
{ {
uint16_t data = 0U; uint16_t data = 0U;
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
/* store the DACx_OUT0 output value */ /* store the DACx_OUT0 output value */
data = (uint16_t)DAC_OUT0_DO(dac_periph); data = (uint16_t)DAC_OUT0_DO(dac_periph);
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
/* store the DACx_OUT1 output value */ /* store the DACx_OUT1 output value */
data = (uint16_t)DAC_OUT1_DO(dac_periph); data = (uint16_t)DAC_OUT1_DO(dac_periph);
}else{ }else{
@ -276,8 +295,10 @@ uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out)
void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint16_t data) void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint16_t data)
{ {
/* DAC_OUT0 data alignment */ /* DAC_OUT0 data alignment */
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
switch(dac_align){ {
switch(dac_align)
{
/* 12-bit right-aligned data */ /* 12-bit right-aligned data */
case DAC_ALIGN_12B_R: case DAC_ALIGN_12B_R:
DAC_OUT0_R12DH(dac_periph) = data; DAC_OUT0_R12DH(dac_periph) = data;
@ -293,9 +314,11 @@ void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint
default: default:
break; break;
} }
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
/* DAC_OUT1 data alignment */ /* DAC_OUT1 data alignment */
switch(dac_align){ switch(dac_align)
{
/* 12-bit right-aligned data */ /* 12-bit right-aligned data */
case DAC_ALIGN_12B_R: case DAC_ALIGN_12B_R:
DAC_OUT1_R12DH(dac_periph) = data; DAC_OUT1_R12DH(dac_periph) = data;
@ -325,9 +348,11 @@ void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint
*/ */
void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out) void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
{ {
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DTEN0; DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DTEN0;
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DTEN1; DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DTEN1;
}else{ }else{
/* illegal parameters */ /* illegal parameters */
@ -343,9 +368,11 @@ void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
*/ */
void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out) void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out)
{ {
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTEN0); DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTEN0);
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTEN1); DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTEN1);
}else{ }else{
/* illegal parameters */ /* illegal parameters */
@ -365,11 +392,13 @@ void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out)
*/ */
void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t triggersource) void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t triggersource)
{ {
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 trigger source */ /* configure DACx_OUT0 trigger source */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTSEL0); DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTSEL0);
DAC_CTL0(dac_periph) |= triggersource; DAC_CTL0(dac_periph) |= triggersource;
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 trigger source */ /* configure DACx_OUT1 trigger source */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTSEL1); DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTSEL1);
DAC_CTL0(dac_periph) |= (triggersource << OUT1_REG_OFFSET); DAC_CTL0(dac_periph) |= (triggersource << OUT1_REG_OFFSET);
@ -386,9 +415,11 @@ void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t tr
*/ */
void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out) void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
{ {
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
DAC_SWT(dac_periph) |= (uint32_t)DAC_SWT_SWTR0; DAC_SWT(dac_periph) |= (uint32_t)DAC_SWT_SWTR0;
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
DAC_SWT(dac_periph) |= (uint32_t)DAC_SWT_SWTR1; DAC_SWT(dac_periph) |= (uint32_t)DAC_SWT_SWTR1;
}else{ }else{
/* illegal parameters */ /* illegal parameters */
@ -409,11 +440,13 @@ void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
*/ */
void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mode) void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mode)
{ {
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 wave mode */ /* configure DACx_OUT0 wave mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWM0); DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWM0);
DAC_CTL0(dac_periph) |= wave_mode; DAC_CTL0(dac_periph) |= wave_mode;
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 wave mode */ /* configure DACx_OUT1 wave mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWM1); DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWM1);
DAC_CTL0(dac_periph) |= (wave_mode << OUT1_REG_OFFSET); DAC_CTL0(dac_periph) |= (wave_mode << OUT1_REG_OFFSET);
@ -445,11 +478,13 @@ void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mo
*/ */
void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask_bits) void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask_bits)
{ {
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 LFSR noise mode */ /* configure DACx_OUT0 LFSR noise mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW0); DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW0);
DAC_CTL0(dac_periph) |= unmask_bits; DAC_CTL0(dac_periph) |= unmask_bits;
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 LFSR noise mode */ /* configure DACx_OUT1 LFSR noise mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW1); DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW1);
DAC_CTL0(dac_periph) |= (unmask_bits << OUT1_REG_OFFSET); DAC_CTL0(dac_periph) |= (unmask_bits << OUT1_REG_OFFSET);
@ -481,11 +516,13 @@ void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask
*/ */
void dac_triangle_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t amplitude) void dac_triangle_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t amplitude)
{ {
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 triangle noise mode */ /* configure DACx_OUT0 triangle noise mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW0); DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW0);
DAC_CTL0(dac_periph) |= amplitude; DAC_CTL0(dac_periph) |= amplitude;
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 triangle noise mode */ /* configure DACx_OUT1 triangle noise mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW1); DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW1);
DAC_CTL0(dac_periph) |= (amplitude << OUT1_REG_OFFSET); DAC_CTL0(dac_periph) |= (amplitude << OUT1_REG_OFFSET);
@ -533,7 +570,7 @@ void dac_concurrent_software_trigger_enable(uint32_t dac_periph)
uint32_t swt = 0U; uint32_t swt = 0U;
swt = (uint32_t)(DAC_SWT_SWTR0 | DAC_SWT_SWTR1); swt = (uint32_t)(DAC_SWT_SWTR0 | DAC_SWT_SWTR1);
DAC_SWT(dac_periph) |= (uint32_t)swt; DAC_SWT(dac_periph) |= (uint32_t)swt;
} }
/*! /*!
@ -553,7 +590,8 @@ void dac_concurrent_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t d
{ {
uint32_t data = 0U; uint32_t data = 0U;
switch(dac_align){ switch(dac_align)
{
/* 12-bit right-aligned data */ /* 12-bit right-aligned data */
case DAC_ALIGN_12B_R: case DAC_ALIGN_12B_R:
data = (uint32_t)(((uint32_t)data1 << DH_12BIT_OFFSET) | data0); data = (uint32_t)(((uint32_t)data1 << DH_12BIT_OFFSET) | data0);
@ -588,7 +626,8 @@ void dac_sample_keep_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t
{ {
uint32_t tmp = 0U; uint32_t tmp = 0U;
if(DAC_OUT0 == dac_out){ if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 Sample & Keep mode */ /* configure DACx_OUT0 Sample & Keep mode */
DAC_SKSTR0(dac_periph) |= (sample_time & DAC_SKSTR0_TSAMP0); DAC_SKSTR0(dac_periph) |= (sample_time & DAC_SKSTR0_TSAMP0);
@ -597,7 +636,8 @@ void dac_sample_keep_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t
tmp = (DAC_SKRTR(dac_periph) & ~(uint32_t)DAC_SKRTR_TREF0); tmp = (DAC_SKRTR(dac_periph) & ~(uint32_t)DAC_SKRTR_TREF0);
DAC_SKRTR(dac_periph) = tmp | (refresh_time & DAC_SKRTR_TREF0); DAC_SKRTR(dac_periph) = tmp | (refresh_time & DAC_SKRTR_TREF0);
}else if(DAC_OUT1 == dac_out){ }else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 Sample & Keep mode */ /* configure DACx_OUT1 Sample & Keep mode */
DAC_SKSTR1(dac_periph) |= (sample_time & DAC_SKSTR1_TSAMP1); DAC_SKSTR1(dac_periph) |= (sample_time & DAC_SKSTR1_TSAMP1);
@ -627,9 +667,11 @@ void dac_sample_keep_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t
*/ */
FlagStatus dac_flag_get(uint32_t dac_periph, uint32_t flag) FlagStatus dac_flag_get(uint32_t dac_periph, uint32_t flag)
{ {
if(flag & DAC_STAT_FLAG_MASK0){ if(flag & DAC_STAT_FLAG_MASK0)
{
/* check DAC_STAT0 flag */ /* check DAC_STAT0 flag */
if(RESET != (DAC_STAT0(dac_periph) & flag)){ if(RESET != (DAC_STAT0(dac_periph) & flag))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -652,7 +694,8 @@ FlagStatus dac_flag_get(uint32_t dac_periph, uint32_t flag)
*/ */
void dac_flag_clear(uint32_t dac_periph, uint32_t flag) void dac_flag_clear(uint32_t dac_periph, uint32_t flag)
{ {
if(flag & DAC_STAT_FLAG_MASK0){ if(flag & DAC_STAT_FLAG_MASK0)
{
/* check DAC_STAT0 flag */ /* check DAC_STAT0 flag */
DAC_STAT0(dac_periph) = (uint32_t)(flag & DAC_STAT_FLAG_MASK0); DAC_STAT0(dac_periph) = (uint32_t)(flag & DAC_STAT_FLAG_MASK0);
}else{ }else{
@ -665,14 +708,15 @@ void dac_flag_clear(uint32_t dac_periph, uint32_t flag)
\param[in] dac_periph: DACx(x=0) \param[in] dac_periph: DACx(x=0)
\param[in] interrupt: the DAC interrupt \param[in] interrupt: the DAC interrupt
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg DAC_INT_DDUDR0: DACx_OUT0 DMA underrun interrupt \arg DAC_INT_DDUDR0: DACx_OUT0 DMA underrun interrupt
\arg DAC_INT_DDUDR1: DACx_OUT1 DMA underrun interrupt \arg DAC_INT_DDUDR1: DACx_OUT1 DMA underrun interrupt
\param[out] none \param[out] none
\retval none \retval none
*/ */
void dac_interrupt_enable(uint32_t dac_periph, uint32_t interrupt) void dac_interrupt_enable(uint32_t dac_periph, uint32_t interrupt)
{ {
if(interrupt & DAC_INT_EN_MASK0){ if(interrupt & DAC_INT_EN_MASK0)
{
/* enable underrun interrupt */ /* enable underrun interrupt */
DAC_CTL0(dac_periph) |= (uint32_t)(interrupt & DAC_INT_EN_MASK0); DAC_CTL0(dac_periph) |= (uint32_t)(interrupt & DAC_INT_EN_MASK0);
}else{ }else{
@ -692,7 +736,8 @@ void dac_interrupt_enable(uint32_t dac_periph, uint32_t interrupt)
*/ */
void dac_interrupt_disable(uint32_t dac_periph, uint32_t interrupt) void dac_interrupt_disable(uint32_t dac_periph, uint32_t interrupt)
{ {
if(interrupt & DAC_INT_EN_MASK0){ if(interrupt & DAC_INT_EN_MASK0)
{
/* disable underrun interrupt */ /* disable underrun interrupt */
DAC_CTL0(dac_periph) &= (uint32_t)(~(interrupt & DAC_INT_EN_MASK0)); DAC_CTL0(dac_periph) &= (uint32_t)(~(interrupt & DAC_INT_EN_MASK0));
}else{ }else{
@ -714,7 +759,8 @@ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph, uint32_t int_flag)
{ {
uint32_t reg1 = 0U, reg2 = 0U; uint32_t reg1 = 0U, reg2 = 0U;
if(int_flag & DAC_INT_FLAG_MASK0){ if(int_flag & DAC_INT_FLAG_MASK0)
{
/* check underrun interrupt int_flag */ /* check underrun interrupt int_flag */
reg1 = DAC_STAT0(dac_periph) & int_flag; reg1 = DAC_STAT0(dac_periph) & int_flag;
reg2 = DAC_CTL0(dac_periph) & int_flag; reg2 = DAC_CTL0(dac_periph) & int_flag;
@ -723,7 +769,8 @@ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph, uint32_t int_flag)
} }
/*get DAC interrupt flag status */ /*get DAC interrupt flag status */
if((RESET != reg1) && (RESET != reg2)){ if((RESET != reg1) && (RESET != reg2))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;

38
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_dbg.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -115,9 +115,9 @@ void dbg_trace_pin_disable(void)
} }
/*! /*!
\brief trace pin mode selection \brief trace pin mode selection
\param[in] trace_mode: \param[in] trace_mode:
\arg TRACE_MODE_ASYNC: trace pin used for async mode \arg TRACE_MODE_ASYNC: trace pin used for async mode
\arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1
\arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2
\arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4
@ -133,7 +133,7 @@ void dbg_trace_pin_mode_set(uint32_t trace_mode)
/*! /*!
\brief enable peripheral behavior when the mcu is in debug mode \brief enable peripheral behavior when the mcu is in debug mode
\param[in] dbg_periph: refer to dbg_periph_enum \param[in] dbg_periph: refer to dbg_periph_enum
only one parameter can be selected which are shown as below: only one parameter can be selected which are shown as below:
\arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
\arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
@ -151,7 +151,7 @@ void dbg_periph_enable(dbg_periph_enum dbg_periph)
/*! /*!
\brief disable peripheral behavior when the mcu is in debug mode \brief disable peripheral behavior when the mcu is in debug mode
\param[in] dbg_periph: refer to dbg_periph_enum \param[in] dbg_periph: refer to dbg_periph_enum
only one parameter can be selected which are shown as below: only one parameter can be selected which are shown as below:
\arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
\arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted

12
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_dci.c
View File

@ -279,7 +279,8 @@ void dci_ccir_disable(void)
*/ */
void dci_ccir_mode_select(uint32_t ccir_mode) void dci_ccir_mode_select(uint32_t ccir_mode)
{ {
if(CCIR_INTERLACE_MODE == ccir_mode) { if(CCIR_INTERLACE_MODE == ccir_mode)
{
DCI_CTL |= DCI_CTL_CCMOD; DCI_CTL |= DCI_CTL_CCMOD;
} else { } else {
DCI_CTL &= ~DCI_CTL_CCMOD; DCI_CTL &= ~DCI_CTL_CCMOD;
@ -346,7 +347,8 @@ FlagStatus dci_flag_get(uint32_t flag)
{ {
uint32_t stat = 0U; uint32_t stat = 0U;
if(flag >> 31U) { if(flag >> 31U)
{
/* get flag status from DCI_STAT1 register */ /* get flag status from DCI_STAT1 register */
stat = DCI_STAT1; stat = DCI_STAT1;
} else { } else {
@ -354,7 +356,8 @@ FlagStatus dci_flag_get(uint32_t flag)
stat = DCI_STAT0; stat = DCI_STAT0;
} }
if(flag & stat) { if(flag & stat)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -421,7 +424,8 @@ void dci_interrupt_disable(uint32_t interrupt)
*/ */
FlagStatus dci_interrupt_flag_get(uint32_t int_flag) FlagStatus dci_interrupt_flag_get(uint32_t int_flag)
{ {
if(RESET == (DCI_INTF & int_flag)) { if(RESET == (DCI_INTF & int_flag))
{
return RESET; return RESET;
} else { } else {
return SET; return SET;

105
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_dma.c
View File

@ -35,7 +35,8 @@ OF SUCH DAMAGE.
#include "gd32h7xx_dma.h" #include "gd32h7xx_dma.h"
#include <stdlib.h> #include <stdlib.h>
#define DMA_WRONG_HANDLE while(1){} #define DMA_WRONG_HANDLE while(1)
{}
/* DMA register bit offset */ /* DMA register bit offset */
#define CHXFCTL_FCNT_OFFSET ((uint32_t)0x00000003U) /*!< bit offset of FCNT in DMA_CHxFCTL */ #define CHXFCTL_FCNT_OFFSET ((uint32_t)0x00000003U) /*!< bit offset of FCNT in DMA_CHxFCTL */
@ -64,7 +65,8 @@ void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
DMA_CHM0ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; DMA_CHM0ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
DMA_CHM1ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; DMA_CHM1ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
DMA_CHFCTL(dma_periph, channelx) = DMA_CHFCTL_RESET_VALUE; DMA_CHFCTL(dma_periph, channelx) = DMA_CHFCTL_RESET_VALUE;
if(channelx < DMA_CH4) { if(channelx < DMA_CH4)
{
DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
} else { } else {
channelx -= (dma_channel_enum)4; channelx -= (dma_channel_enum)4;
@ -160,9 +162,11 @@ void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, d
DMA_CHCTL(dma_periph, channelx) = ctl; DMA_CHCTL(dma_periph, channelx) = ctl;
/* configure peripheral increasing mode */ /* configure peripheral increasing mode */
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
} else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) { } else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc)
{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
} else { } else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
@ -170,19 +174,22 @@ void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, d
} }
/* configure memory increasing mode */ /* configure memory increasing mode */
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
} else { } else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
} }
/* configure DMA circular mode */ /* configure DMA circular mode */
if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) { if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
} else { } else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
} }
if(DMA0 == dma_periph) { if(DMA0 == dma_periph)
{
DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_MUXID; DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_MUXID;
DMAMUX_RM_CHXCFG(channelx) |= init_struct->request; DMAMUX_RM_CHXCFG(channelx) |= init_struct->request;
} else { } else {
@ -239,9 +246,11 @@ void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dm
DMA_CHCTL(dma_periph, channelx) = ctl; DMA_CHCTL(dma_periph, channelx) = ctl;
/* configure peripheral increasing mode */ /* configure peripheral increasing mode */
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
} else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) { } else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc)
{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
} else { } else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
@ -249,20 +258,23 @@ void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dm
} }
/* configure memory increasing mode */ /* configure memory increasing mode */
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
} else { } else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
} }
/* configure DMA circular mode */ /* configure DMA circular mode */
if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) { if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
} else { } else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
} }
if(DMA0 == dma_periph) { if(DMA0 == dma_periph)
{
DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_MUXID; DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_MUXID;
DMAMUX_RM_CHXCFG(channelx) |= init_struct->request; DMAMUX_RM_CHXCFG(channelx) |= init_struct->request;
} else { } else {
@ -301,7 +313,8 @@ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, u
*/ */
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address) void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address)
{ {
if(memory_flag) { if(memory_flag)
{
DMA_CHM1ADDR(dma_periph, channelx) = address; DMA_CHM1ADDR(dma_periph, channelx) = address;
} else { } else {
DMA_CHM0ADDR(dma_periph, channelx) = address; DMA_CHM0ADDR(dma_periph, channelx) = address;
@ -479,7 +492,8 @@ void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uin
*/ */
void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm)
{ {
if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm) { if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
} else { } else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
@ -502,9 +516,11 @@ void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum
*/ */
void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm)
{ {
if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm) { if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
} else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm) { } else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm)
{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
} else { } else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
@ -612,7 +628,8 @@ void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channel
/* configure memory1 base address */ /* configure memory1 base address */
DMA_CHM1ADDR(dma_periph, channelx) = memory1_addr; DMA_CHM1ADDR(dma_periph, channelx) = memory1_addr;
if(DMA_MEMORY_0 == memory_select) { if(DMA_MEMORY_0 == memory_select)
{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MBS; DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MBS;
} else { } else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MBS; DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MBS;
@ -630,7 +647,8 @@ void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channel
*/ */
uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx) uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx)
{ {
if((DMA_CHCTL(dma_periph, channelx)) & DMA_CHXCTL_MBS) { if((DMA_CHCTL(dma_periph, channelx)) & DMA_CHXCTL_MBS)
{
return DMA_MEMORY_1; return DMA_MEMORY_1;
} else { } else {
return DMA_MEMORY_0; return DMA_MEMORY_0;
@ -705,15 +723,18 @@ uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx)
*/ */
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{ {
if(channelx < DMA_CH4) { if(channelx < DMA_CH4)
if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx)) { {
if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
} }
} else { } else {
channelx -= (dma_channel_enum)4; channelx -= (dma_channel_enum)4;
if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channelx)) { if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channelx))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -739,7 +760,8 @@ FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t
*/ */
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{ {
if(channelx < DMA_CH4) { if(channelx < DMA_CH4)
{
DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag, channelx); DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
} else { } else {
channelx -= (dma_channel_enum)4; channelx -= (dma_channel_enum)4;
@ -765,7 +787,8 @@ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t fla
*/ */
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt)
{ {
if(DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & interrupt)) { if(DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & interrupt))
{
DMA_CHCTL(dma_periph, channelx) |= interrupt; DMA_CHCTL(dma_periph, channelx) |= interrupt;
} else { } else {
DMA_CHFCTL(dma_periph, channelx) |= DMA_CHXFCTL_FEEIE; DMA_CHFCTL(dma_periph, channelx) |= DMA_CHXFCTL_FEEIE;
@ -791,7 +814,8 @@ void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32
*/ */
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt)
{ {
if(DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & interrupt)) { if(DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & interrupt))
{
DMA_CHCTL(dma_periph, channelx) &= ~interrupt; DMA_CHCTL(dma_periph, channelx) &= ~interrupt;
} else { } else {
DMA_CHFCTL(dma_periph, channelx) &= ~DMA_CHXFCTL_FEEIE; DMA_CHFCTL(dma_periph, channelx) &= ~DMA_CHXFCTL_FEEIE;
@ -821,8 +845,10 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
dma_channel_enum channel_flag_offset = channelx; dma_channel_enum channel_flag_offset = channelx;
/* flags for channel0-3 */ /* flags for channel0-3 */
if(channelx < DMA_CH4) { if(channelx < DMA_CH4)
switch(int_flag) { {
switch(int_flag)
{
case DMA_INTF_FEEIF: case DMA_INTF_FEEIF:
interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(int_flag, channelx); interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(int_flag, channelx);
interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE; interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE;
@ -849,7 +875,8 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
/* flags for channel4-7 */ /* flags for channel4-7 */
} else { } else {
channel_flag_offset -= (dma_channel_enum)4U; channel_flag_offset -= (dma_channel_enum)4U;
switch(int_flag) { switch(int_flag)
{
case DMA_INTF_FEEIF: case DMA_INTF_FEEIF:
interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(int_flag, channel_flag_offset); interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(int_flag, channel_flag_offset);
interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE; interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE;
@ -875,7 +902,8 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
} }
} }
if(interrupt_flag && interrupt_enable) { if(interrupt_flag && interrupt_enable)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -900,7 +928,8 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
*/ */
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t int_flag) void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t int_flag)
{ {
if(channelx < DMA_CH4) { if(channelx < DMA_CH4)
{
DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(int_flag, channelx); DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(int_flag, channelx);
} else { } else {
channelx -= (dma_channel_enum)4U; channelx -= (dma_channel_enum)4U;
@ -916,7 +945,8 @@ void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, ui
*/ */
void dmamux_sync_struct_para_init(dmamux_sync_parameter_struct *init_struct) void dmamux_sync_struct_para_init(dmamux_sync_parameter_struct *init_struct)
{ {
if(NULL == init_struct) { if(NULL == init_struct)
{
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -949,7 +979,8 @@ void dmamux_synchronization_init(dmamux_multiplexer_channel_enum channelx, dmamu
{ {
uint32_t cfg; uint32_t cfg;
if(NULL == init_struct) { if(NULL == init_struct)
{
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -1022,7 +1053,8 @@ void dmamux_event_generation_disable(dmamux_multiplexer_channel_enum channelx)
*/ */
void dmamux_gen_struct_para_init(dmamux_gen_parameter_struct *init_struct) void dmamux_gen_struct_para_init(dmamux_gen_parameter_struct *init_struct)
{ {
if(NULL == init_struct) { if(NULL == init_struct)
{
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -1055,7 +1087,8 @@ void dmamux_request_generator_init(dmamux_generator_channel_enum channelx, dmamu
{ {
uint32_t cfg; uint32_t cfg;
if(NULL == init_struct) { if(NULL == init_struct)
{
DMA_WRONG_HANDLE DMA_WRONG_HANDLE
} }
@ -1506,7 +1539,8 @@ FlagStatus dmamux_flag_get(dmamux_flag_enum flag)
{ {
FlagStatus reval; FlagStatus reval;
if(RESET != (DMAMUX_REG_VAL(flag) & BIT(DMAMUX_BIT_POS(flag)))) { if(RESET != (DMAMUX_REG_VAL(flag) & BIT(DMAMUX_BIT_POS(flag))))
{
reval = SET; reval = SET;
} else { } else {
reval = RESET; reval = RESET;
@ -1664,7 +1698,8 @@ FlagStatus dmamux_interrupt_flag_get(dmamux_interrupt_flag_enum int_flag)
/* get the corresponding flag bit status */ /* get the corresponding flag bit status */
flagstatus = (DMAMUX_REG_VAL(int_flag) & BIT(DMAMUX_BIT_POS(int_flag))); flagstatus = (DMAMUX_REG_VAL(int_flag) & BIT(DMAMUX_BIT_POS(int_flag)));
if(flagstatus && intenable) { if(flagstatus && intenable)
{
reval = SET; reval = SET;
} else { } else {
reval = RESET; reval = RESET;

6
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_edout.c
View File

@ -74,10 +74,12 @@ void edout_init(uint32_t pol, uint32_t max_loc, uint32_t cur_loc)
/* reset the maximum location value */ /* reset the maximum location value */
EDOUT_LOC &= ~EDOUT_LOC_LOCMAX; EDOUT_LOC &= ~EDOUT_LOC_LOCMAX;
/* check the maximum location value */ /* check the maximum location value */
if(LOC_LOCMAX_MIN > max_loc) { if(LOC_LOCMAX_MIN > max_loc)
{
max_loc = LOC_LOCMAX_MIN; max_loc = LOC_LOCMAX_MIN;
} }
while(0U != ((max_loc + 1U) % LOC_LOCMAX_STEP)) { while(0U != ((max_loc + 1U) % LOC_LOCMAX_STEP))
{
max_loc++; max_loc++;
} }
/* set the maximum location value */ /* set the maximum location value */

90
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_efuse.c
View File

@ -73,7 +73,8 @@ ErrStatus efuse_read(uint32_t ef_addr, uint32_t size, uint32_t buf[])
uint32_t reg_addr = 0U; uint32_t reg_addr = 0U;
uint32_t i = 0U; uint32_t i = 0U;
uint32_t number = 0U; uint32_t number = 0U;
switch(ef_addr) { switch(ef_addr)
{
case USER_CTL_EFADDR: case USER_CTL_EFADDR:
/* read user control */ /* read user control */
reg_addr = EFUSE_USER_CTL_REG_ADDR; reg_addr = EFUSE_USER_CTL_REG_ADDR;
@ -86,14 +87,18 @@ ErrStatus efuse_read(uint32_t ef_addr, uint32_t size, uint32_t buf[])
break; break;
case DP_EFADDR: case DP_EFADDR:
/* read debug password */ /* read debug password */
if(RESET != (EFUSE_USER_CTL & EFUSE_USER_CTL_DPLK)) { if(RESET != (EFUSE_USER_CTL & EFUSE_USER_CTL_DPLK))
if(RESET != (EFUSE_USER_CTL & EFUSE_USER_CTL_JTAGNSW)) { {
if((RESET != (EFUSE_USER_CTL & USER_CTL_NDBG0))) { if(RESET != (EFUSE_USER_CTL & EFUSE_USER_CTL_JTAGNSW))
{
if((RESET != (EFUSE_USER_CTL & USER_CTL_NDBG0)))
{
status = ERROR; status = ERROR;
} }
} }
} }
if(SUCCESS == status) { if(SUCCESS == status)
{
reg_addr = EFUSE_DP_REG_ADDR; reg_addr = EFUSE_DP_REG_ADDR;
number = 2U; number = 2U;
} }
@ -107,7 +112,8 @@ ErrStatus efuse_read(uint32_t ef_addr, uint32_t size, uint32_t buf[])
status = ERROR; status = ERROR;
break; break;
} }
if(ERROR == status) { if(ERROR == status)
{
return status; return status;
} }
/* clear the RDIF bit if it is SET */ /* clear the RDIF bit if it is SET */
@ -120,11 +126,13 @@ ErrStatus efuse_read(uint32_t ef_addr, uint32_t size, uint32_t buf[])
EFUSE_CTL |= EFUSE_CTL_EFSTR; EFUSE_CTL |= EFUSE_CTL_EFSTR;
/* wait for the operation to complete */ /* wait for the operation to complete */
efuse_state = efuse_ready_wait(EFUSE_FLAG_READ_COMPLETE, timeout); efuse_state = efuse_ready_wait(EFUSE_FLAG_READ_COMPLETE, timeout);
if(EFUSE_READY != efuse_state) { if(EFUSE_READY != efuse_state)
{
status = ERROR; status = ERROR;
} }
/* read EFUSE register */ /* read EFUSE register */
for(i = 0U; i < number; i++) { for(i = 0U; i < number; i++)
{
buf[i] = REG32(reg_addr + (4U * i)); buf[i] = REG32(reg_addr + (4U * i));
} }
return status; return status;
@ -150,34 +158,43 @@ ErrStatus efuse_write(uint32_t ef_addr, uint32_t size, uint8_t *buf)
uint32_t buf_addr; uint32_t buf_addr;
uint32_t timeout = EFUSE_TIMEOUT; uint32_t timeout = EFUSE_TIMEOUT;
efuse_state_enum efuse_state; efuse_state_enum efuse_state;
if(0U == size) { if(0U == size)
{
return ERROR; return ERROR;
} }
/* the address should be on byte address boundary */ /* the address should be on byte address boundary */
if(ef_addr % 8U) { if(ef_addr % 8U)
{
return ERROR; return ERROR;
} }
if(MAX_EFADDR < ef_addr) { if(MAX_EFADDR < ef_addr)
{
return ERROR; return ERROR;
} }
for(i = EFUSE_PARA_CNT; i > 0U; i--) { for(i = EFUSE_PARA_CNT; i > 0U; i--)
if(ef_addr >= para_start_efaddr[i - 1U]) { {
if(ef_addr >= para_start_efaddr[i - 1U])
{
break; break;
} }
} }
/* get the index of parameter to be programmed */ /* get the index of parameter to be programmed */
para_index = i - 1U; para_index = i - 1U;
/* program range should not over parameter boundary */ /* program range should not over parameter boundary */
if(para_index == (EFUSE_PARA_CNT - 1U)) { if(para_index == (EFUSE_PARA_CNT - 1U))
if((ef_addr + size * 8U - 1U) > MAX_EFADDR) { {
if((ef_addr + size * 8U - 1U) > MAX_EFADDR)
{
return ERROR; return ERROR;
} }
} else { } else {
if((ef_addr + size * 8U - 1U) > para_start_efaddr[para_index + 1U]) { if((ef_addr + size * 8U - 1U) > para_start_efaddr[para_index + 1U])
{
return ERROR; return ERROR;
} }
} }
if((AES_KEY_IDX == para_index) && (AES_KEY_SIZE != size)) { if((AES_KEY_IDX == para_index) && (AES_KEY_SIZE != size))
{
/* AES key should be programmed in one time */ /* AES key should be programmed in one time */
return ERROR; return ERROR;
} }
@ -191,10 +208,13 @@ ErrStatus efuse_write(uint32_t ef_addr, uint32_t size, uint8_t *buf)
EFUSE_ADDR = (uint32_t)((size << EFUSE_ADDR_EFSIZE_OFFSET) | ef_addr); EFUSE_ADDR = (uint32_t)((size << EFUSE_ADDR_EFSIZE_OFFSET) | ef_addr);
buf_addr = (uint32_t)buf; buf_addr = (uint32_t)buf;
while(size) { while(size)
if((0U != byte_offset_in_reg) || ((0U == byte_offset_in_reg) && (size < 4U))) { {
if((0U != byte_offset_in_reg) || ((0U == byte_offset_in_reg) && (size < 4U)))
{
cnt = size < (4U - byte_offset_in_reg) ? size : 4U - byte_offset_in_reg; cnt = size < (4U - byte_offset_in_reg) ? size : 4U - byte_offset_in_reg;
for(i = 0U; i < cnt; i++) { for(i = 0U; i < cnt; i++)
{
tmp_buf_8 = buf_addr; tmp_buf_8 = buf_addr;
/* write the data to the corresponding register */ /* write the data to the corresponding register */
tmp_buf_8 += i; tmp_buf_8 += i;
@ -206,7 +226,8 @@ ErrStatus efuse_write(uint32_t ef_addr, uint32_t size, uint8_t *buf)
buf_addr += cnt; buf_addr += cnt;
} else { } else {
cnt = size / 4U; cnt = size / 4U;
for(i = 0U; i < cnt; i++) { for(i = 0U; i < cnt; i++)
{
tmp_buf_8 = buf_addr; tmp_buf_8 = buf_addr;
/* write the data to the corresponding register */ /* write the data to the corresponding register */
tmp_buf_8 += (i * 4U); tmp_buf_8 += (i * 4U);
@ -221,7 +242,8 @@ ErrStatus efuse_write(uint32_t ef_addr, uint32_t size, uint8_t *buf)
EFUSE_CTL |= EFUSE_CTL_EFSTR; EFUSE_CTL |= EFUSE_CTL_EFSTR;
/* wait for the operation to complete */ /* wait for the operation to complete */
efuse_state = efuse_ready_wait(EFUSE_FLAG_PROGRAM_COMPLETE, timeout); efuse_state = efuse_ready_wait(EFUSE_FLAG_PROGRAM_COMPLETE, timeout);
if(EFUSE_READY != efuse_state) { if(EFUSE_READY != efuse_state)
{
status = ERROR; status = ERROR;
} }
return status; return status;
@ -333,7 +355,8 @@ FlagStatus efuse_monitor_program_voltage_get(void)
{ {
FlagStatus mpven_state = RESET; FlagStatus mpven_state = RESET;
if(EFUSE_CTL_MPVEN == (uint32_t)(EFUSE_CTL & EFUSE_CTL_MPVEN)) { if(EFUSE_CTL_MPVEN == (uint32_t)(EFUSE_CTL & EFUSE_CTL_MPVEN))
{
mpven_state = SET; mpven_state = SET;
} else { } else {
mpven_state = RESET; mpven_state = RESET;
@ -351,7 +374,8 @@ FlagStatus efuse_ldo_ready_get(void)
{ {
FlagStatus ldo_ready_state = RESET; FlagStatus ldo_ready_state = RESET;
if(EFUSE_STAT_LDO_RDY == (uint32_t)(EFUSE_STAT & EFUSE_STAT_LDO_RDY)) { if(EFUSE_STAT_LDO_RDY == (uint32_t)(EFUSE_STAT & EFUSE_STAT_LDO_RDY))
{
ldo_ready_state = SET; ldo_ready_state = SET;
} else { } else {
ldo_ready_state = RESET; ldo_ready_state = RESET;
@ -372,7 +396,8 @@ FlagStatus efuse_ldo_ready_get(void)
*/ */
FlagStatus efuse_flag_get(uint32_t flag) FlagStatus efuse_flag_get(uint32_t flag)
{ {
if(EFUSE_STAT & (uint32_t)flag) { if(EFUSE_STAT & (uint32_t)flag)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -446,7 +471,8 @@ FlagStatus efuse_interrupt_flag_get(uint32_t int_flag)
/* get the corresponding flag bit status */ /* get the corresponding flag bit status */
flagstatus = (EFUSE_REG_VAL2(int_flag) & BIT(EFUSE_BIT_POS2(int_flag))); flagstatus = (EFUSE_REG_VAL2(int_flag) & BIT(EFUSE_BIT_POS2(int_flag)));
if(flagstatus && intenable) { if(flagstatus && intenable)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -492,11 +518,14 @@ static efuse_state_enum efuse_ready_wait(uint32_t efuse_flag, uint32_t timeout)
/* wait for EFUSE ready */ /* wait for EFUSE ready */
do { do {
/* get EFUSE flag set or not */ /* get EFUSE flag set or not */
if(EFUSE_STAT & (uint32_t)efuse_flag) { if(EFUSE_STAT & (uint32_t)efuse_flag)
{
efuse_state = EFUSE_READY; efuse_state = EFUSE_READY;
} else if(EFUSE_STAT & EFUSE_STAT_IAERRIF) { } else if(EFUSE_STAT & EFUSE_STAT_IAERRIF)
{
efuse_state = EFUSE_IAERR; efuse_state = EFUSE_IAERR;
} else if(EFUSE_STAT & EFUSE_STAT_PVIF) { } else if(EFUSE_STAT & EFUSE_STAT_PVIF)
{
efuse_state = EFUSE_PVERR; efuse_state = EFUSE_PVERR;
} else { } else {
/* illegal parameters */ /* illegal parameters */
@ -504,7 +533,8 @@ static efuse_state_enum efuse_ready_wait(uint32_t efuse_flag, uint32_t timeout)
timeout--; timeout--;
} while((EFUSE_BUSY == efuse_state) && (0U != timeout)); } while((EFUSE_BUSY == efuse_state) && (0U != timeout));
if(EFUSE_BUSY == efuse_state) { if(EFUSE_BUSY == efuse_state)
{
efuse_state = EFUSE_TOERR; efuse_state = EFUSE_TOERR;
} }

492
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_enet.c
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File diff suppressed because it is too large Load Diff

45
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_exmc.c
View File

@ -224,7 +224,8 @@ void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct)
exmc_norsram_init_struct->cram_page_size); exmc_norsram_init_struct->cram_page_size);
/* nor flash access enable */ /* nor flash access enable */
if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) { if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type)
{
snctl |= (uint32_t)EXMC_SNCTL_NREN; snctl |= (uint32_t)EXMC_SNCTL_NREN;
} }
@ -237,7 +238,8 @@ void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct)
exmc_norsram_init_struct->read_write_timing->syn_data_latency | exmc_norsram_init_struct->read_write_timing->syn_data_latency |
exmc_norsram_init_struct->read_write_timing->asyn_access_mode); exmc_norsram_init_struct->read_write_timing->asyn_access_mode);
if(ENABLE == exmc_norsram_init_struct->extended_mode) { if(ENABLE == exmc_norsram_init_struct->extended_mode)
{
/* for extended mode, configure write timing */ /* for extended mode, configure write timing */
snwtcfg = (uint32_t)(exmc_norsram_init_struct->write_timing->asyn_address_setuptime | snwtcfg = (uint32_t)(exmc_norsram_init_struct->write_timing->asyn_address_setuptime |
(exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | (exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) |
@ -459,7 +461,8 @@ void exmc_sdram_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct)
uint32_t sdctl0, sdctl1, sdtcfg0, sdtcfg1; uint32_t sdctl0, sdctl1, sdtcfg0, sdtcfg1;
/* configure EXMC_SDCTL0 or EXMC_SDCTL1 */ /* configure EXMC_SDCTL0 or EXMC_SDCTL1 */
if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device) { if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device)
{
/* configure EXMC_SDCTL0 */ /* configure EXMC_SDCTL0 */
EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)(exmc_sdram_init_struct->column_address_width | EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)(exmc_sdram_init_struct->column_address_width |
exmc_sdram_init_struct->row_address_width | exmc_sdram_init_struct->row_address_width |
@ -561,7 +564,8 @@ uint32_t exmc_norsram_sdram_remap_get(void)
*/ */
void exmc_norsram_consecutive_clock_config(uint32_t clock_mode) void exmc_norsram_consecutive_clock_config(uint32_t clock_mode)
{ {
if(EXMC_CLOCK_UNCONDITIONALLY == clock_mode) { if(EXMC_CLOCK_UNCONDITIONALLY == clock_mode)
{
EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= EXMC_CLOCK_UNCONDITIONALLY; EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= EXMC_CLOCK_UNCONDITIONALLY;
} else { } else {
EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_CLOCK_UNCONDITIONALLY; EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_CLOCK_UNCONDITIONALLY;
@ -599,7 +603,8 @@ void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_s
*/ */
void exmc_nand_ecc_config(ControlStatus newvalue) void exmc_nand_ecc_config(ControlStatus newvalue)
{ {
if(ENABLE == newvalue) { if(ENABLE == newvalue)
{
/* enable NAND bank ECC function */ /* enable NAND bank ECC function */
EXMC_NCTL |= EXMC_NCTL_ECCEN; EXMC_NCTL |= EXMC_NCTL_ECCEN;
} else { } else {
@ -722,7 +727,8 @@ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number)
*/ */
void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue) void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue)
{ {
if(ENABLE == newvalue) { if(ENABLE == newvalue)
{
EXMC_SDCTL(exmc_sdram_device) |= (uint32_t)EXMC_SDCTL_WPEN; EXMC_SDCTL(exmc_sdram_device) |= (uint32_t)EXMC_SDCTL_WPEN;
} else { } else {
EXMC_SDCTL(exmc_sdram_device) &= ~((uint32_t)EXMC_SDCTL_WPEN); EXMC_SDCTL(exmc_sdram_device) &= ~((uint32_t)EXMC_SDCTL_WPEN);
@ -741,7 +747,8 @@ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device)
{ {
uint32_t sdstat = 0U; uint32_t sdstat = 0U;
if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device) { if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device)
{
sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA0) >> SDSTAT_STA0_OFFSET); sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA0) >> SDSTAT_STA0_OFFSET);
} else { } else {
sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA1) >> SDSTAT_STA1_OFFSET); sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA1) >> SDSTAT_STA1_OFFSET);
@ -772,7 +779,8 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag)
{ {
uint32_t status = 0x00000000U; uint32_t status = 0x00000000U;
if(EXMC_BANK2_NAND == exmc_bank) { if(EXMC_BANK2_NAND == exmc_bank)
{
/* NAND bank2 */ /* NAND bank2 */
status = EXMC_NINTEN; status = EXMC_NINTEN;
} else { } else {
@ -780,7 +788,8 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag)
status = EXMC_SDSTAT; status = EXMC_SDSTAT;
} }
if((status & flag) != (uint32_t)flag) { if((status & flag) != (uint32_t)flag)
{
/* flag is reset */ /* flag is reset */
return RESET; return RESET;
} else { } else {
@ -808,7 +817,8 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag)
*/ */
void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag) void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag)
{ {
if(EXMC_BANK2_NAND == exmc_bank) { if(EXMC_BANK2_NAND == exmc_bank)
{
/* NAND bank2 */ /* NAND bank2 */
EXMC_NINTEN &= ~flag; EXMC_NINTEN &= ~flag;
} else { } else {
@ -835,7 +845,8 @@ void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag)
*/ */
void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt) void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt)
{ {
if(EXMC_BANK2_NAND == exmc_bank) { if(EXMC_BANK2_NAND == exmc_bank)
{
/* NAND bank2 */ /* NAND bank2 */
EXMC_NINTEN |= interrupt; EXMC_NINTEN |= interrupt;
} else { } else {
@ -862,7 +873,8 @@ void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt)
*/ */
void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt) void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt)
{ {
if(EXMC_BANK2_NAND == exmc_bank) { if(EXMC_BANK2_NAND == exmc_bank)
{
/* NAND bank2 */ /* NAND bank2 */
EXMC_NINTEN &= ~interrupt; EXMC_NINTEN &= ~interrupt;
} else { } else {
@ -893,7 +905,8 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt)
uint32_t interrupt_enable = 0x00000000U; uint32_t interrupt_enable = 0x00000000U;
uint32_t interrupt_status = 0x00000000U; uint32_t interrupt_status = 0x00000000U;
if(EXMC_BANK2_NAND == exmc_bank) { if(EXMC_BANK2_NAND == exmc_bank)
{
/* NAND bank2 */ /* NAND bank2 */
reg_value = EXMC_NINTEN; reg_value = EXMC_NINTEN;
interrupt_status = (reg_value & (interrupt >> NINTEN_INTEN_INTS_INTERVAL)); interrupt_status = (reg_value & (interrupt >> NINTEN_INTEN_INTS_INTERVAL));
@ -905,7 +918,8 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt)
interrupt_enable = (reg_value & interrupt); interrupt_enable = (reg_value & interrupt);
if((interrupt_enable) && (interrupt_status)) { if((interrupt_enable) && (interrupt_status))
{
/* interrupt flag is set */ /* interrupt flag is set */
return SET; return SET;
} else { } else {
@ -932,7 +946,8 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt)
*/ */
void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt) void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt)
{ {
if(EXMC_BANK2_NAND == exmc_bank) { if(EXMC_BANK2_NAND == exmc_bank)
{
/* NAND bank2 */ /* NAND bank2 */
EXMC_NINTEN &= ~(interrupt >> NINTEN_INTEN_INTS_INTERVAL); EXMC_NINTEN &= ~(interrupt >> NINTEN_INTEN_INTS_INTERVAL);
} else { } else {

12
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_exti.c
View File

@ -84,7 +84,8 @@ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum tr
EXTI_FTEN(EXTI_REG_VAL(linex)) &= ~EXTI_BIT_POS(linex); EXTI_FTEN(EXTI_REG_VAL(linex)) &= ~EXTI_BIT_POS(linex);
/* set the EXTI mode and enable the interrupts or events from EXTI line x */ /* set the EXTI mode and enable the interrupts or events from EXTI line x */
switch(mode) { switch(mode)
{
case EXTI_INTERRUPT: case EXTI_INTERRUPT:
EXTI_INTEN(EXTI_REG_VAL(linex)) |= EXTI_BIT_POS(linex); EXTI_INTEN(EXTI_REG_VAL(linex)) |= EXTI_BIT_POS(linex);
break; break;
@ -96,7 +97,8 @@ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum tr
} }
/* set the EXTI trigger type */ /* set the EXTI trigger type */
switch(trig_type) { switch(trig_type)
{
case EXTI_TRIG_RISING: case EXTI_TRIG_RISING:
EXTI_RTEN(EXTI_REG_VAL(linex)) |= EXTI_BIT_POS(linex); EXTI_RTEN(EXTI_REG_VAL(linex)) |= EXTI_BIT_POS(linex);
EXTI_FTEN(EXTI_REG_VAL(linex)) &= ~EXTI_BIT_POS(linex); EXTI_FTEN(EXTI_REG_VAL(linex)) &= ~EXTI_BIT_POS(linex);
@ -203,7 +205,8 @@ void exti_software_interrupt_disable(exti_line_enum linex)
*/ */
FlagStatus exti_flag_get(exti_line_enum linex) FlagStatus exti_flag_get(exti_line_enum linex)
{ {
if(RESET != (EXTI_PD(EXTI_REG_VAL(linex)) & EXTI_BIT_POS(linex))) { if(RESET != (EXTI_PD(EXTI_REG_VAL(linex)) & EXTI_BIT_POS(linex)))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -233,7 +236,8 @@ void exti_flag_clear(exti_line_enum linex)
*/ */
FlagStatus exti_interrupt_flag_get(exti_line_enum linex) FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
{ {
if(RESET != (EXTI_PD(EXTI_REG_VAL(linex)) & EXTI_BIT_POS(linex))) { if(RESET != (EXTI_PD(EXTI_REG_VAL(linex)) & EXTI_BIT_POS(linex)))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_fac.c
View File

@ -176,7 +176,7 @@ void fac_fixed_buffer_preload(fac_fixed_data_preload_struct *init_struct)
/* load the X0 buffer for input data */ /* load the X0 buffer for input data */
fac_fixed_data_preload(init_struct->input_size, init_struct->input_ctx); fac_fixed_data_preload(init_struct->input_size, init_struct->input_ctx);
/* configure dma for X0 preload */ /* configure dma for X0 preload */
/* FAC_PARACFG: configure parameter of filter preload */ /* FAC_PARACFG: configure parameter of filter preload */
FAC_PARACFG = (((uint32_t)init_struct->coeffb_size) & FAC_PARACFG_IPP) | \ FAC_PARACFG = (((uint32_t)init_struct->coeffb_size) & FAC_PARACFG_IPP) | \
((((uint32_t)init_struct->coeffa_size) << 8) & FAC_PARACFG_IPQ) | \ ((((uint32_t)init_struct->coeffa_size) << 8) & FAC_PARACFG_IPQ) | \
@ -186,12 +186,14 @@ void fac_fixed_buffer_preload(fac_fixed_data_preload_struct *init_struct)
fac_fixed_data_preload(init_struct->coeffb_size, (init_struct->coeffb_ctx)); fac_fixed_data_preload(init_struct->coeffb_size, (init_struct->coeffb_ctx));
/* load the x1 buffer for cofficientA */ /* load the x1 buffer for cofficientA */
if((NULL != init_struct->coeffa_ctx) && (0U != init_struct->coeffa_size)) { if((NULL != init_struct->coeffa_ctx) && (0U != init_struct->coeffa_size))
{
/* Load the buffer into the internal memory */ /* Load the buffer into the internal memory */
fac_fixed_data_preload(init_struct->coeffa_size, (init_struct->coeffa_ctx)); fac_fixed_data_preload(init_struct->coeffa_size, (init_struct->coeffa_ctx));
} }
/* if need configure to preload output buffer */ /* if need configure to preload output buffer */
if((NULL != init_struct->output_ctx) && (0U != init_struct->output_size)) { if((NULL != init_struct->output_ctx) && (0U != init_struct->output_size))
{
FAC_PARACFG = ((uint32_t)init_struct->output_size & FAC_PARACFG_IPP) | \ FAC_PARACFG = ((uint32_t)init_struct->output_size & FAC_PARACFG_IPP) | \
FUNC_LOAD_Y | FAC_PARACFG_EXE; FUNC_LOAD_Y | FAC_PARACFG_EXE;
@ -235,12 +237,14 @@ void fac_float_buffer_preload(fac_float_data_preload_struct *init_struct)
fac_float_data_preload(init_struct->coeffb_size, (init_struct->coeffb_ctx)); fac_float_data_preload(init_struct->coeffb_size, (init_struct->coeffb_ctx));
/* load the x1 buffer for cofficientA */ /* load the x1 buffer for cofficientA */
if((NULL != init_struct->coeffa_ctx) && (0U != init_struct->coeffa_size)) { if((NULL != init_struct->coeffa_ctx) && (0U != init_struct->coeffa_size))
{
/* load the buffer into the internal memory */ /* load the buffer into the internal memory */
fac_float_data_preload(init_struct->coeffa_size, (init_struct->coeffa_ctx)); fac_float_data_preload(init_struct->coeffa_size, (init_struct->coeffa_ctx));
} }
/* if need configure to preload output buffer */ /* if need configure to preload output buffer */
if((NULL != init_struct->output_ctx) && (0U != init_struct->output_size)) { if((NULL != init_struct->output_ctx) && (0U != init_struct->output_size))
{
FAC_PARACFG = ((uint32_t)init_struct->output_size & FAC_PARACFG_IPP) | \ FAC_PARACFG = ((uint32_t)init_struct->output_size & FAC_PARACFG_IPP) | \
FUNC_LOAD_Y | FAC_PARACFG_EXE; FUNC_LOAD_Y | FAC_PARACFG_EXE;
@ -258,7 +262,8 @@ void fac_float_buffer_preload(fac_float_data_preload_struct *init_struct)
void fac_fixed_data_preload(uint8_t size, int16_t array[]) void fac_fixed_data_preload(uint8_t size, int16_t array[])
{ {
uint8_t i; uint8_t i;
for(i = 0U; i < size; i++) { for(i = 0U; i < size; i++)
{
FAC_WDATA = ((*((uint16_t*)&array[i])) & FAC_WDATA_WDATA); FAC_WDATA = ((*((uint16_t*)&array[i])) & FAC_WDATA_WDATA);
} }
} }
@ -273,7 +278,8 @@ void fac_fixed_data_preload(uint8_t size, int16_t array[])
void fac_float_data_preload(uint8_t size, float array[]) void fac_float_data_preload(uint8_t size, float array[])
{ {
uint8_t i; uint8_t i;
for(i = 0U; i < size; i++) { for(i = 0U; i < size; i++)
{
FAC_WDATA = ((*((uint32_t*) & array[i]))); FAC_WDATA = ((*((uint32_t*) & array[i])));
} }
} }
@ -300,7 +306,8 @@ void fac_reset(void)
*/ */
void fac_clip_config(uint8_t cpmod) void fac_clip_config(uint8_t cpmod)
{ {
if(FAC_CP_ENABLE == cpmod) { if(FAC_CP_ENABLE == cpmod)
{
FAC_CTL |= FAC_CTL_CPEN; FAC_CTL |= FAC_CTL_CPEN;
} else { } else {
FAC_CTL &= ~(FAC_CTL_CPEN); FAC_CTL &= ~(FAC_CTL_CPEN);
@ -593,7 +600,8 @@ FlagStatus fac_interrupt_flag_get(uint8_t interrupt)
uint32_t reg1 = FAC_CTL; uint32_t reg1 = FAC_CTL;
uint32_t reg2 = FAC_STAT; uint32_t reg2 = FAC_STAT;
switch(interrupt) { switch(interrupt)
{
/* Y buffer read interrupt */ /* Y buffer read interrupt */
case FAC_INT_FLAG_YBEF: case FAC_INT_FLAG_YBEF:
reg1 = reg1 & FAC_CTL_RIE; reg1 = reg1 & FAC_CTL_RIE;
@ -628,7 +636,8 @@ FlagStatus fac_interrupt_flag_get(uint8_t interrupt)
break; break;
} }
/*get FAC interrupt flag status */ /*get FAC interrupt flag status */
if(reg1 && reg2) { if(reg1 && reg2)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -650,7 +659,8 @@ FlagStatus fac_interrupt_flag_get(uint8_t interrupt)
*/ */
FlagStatus fac_flag_get(uint32_t flag) FlagStatus fac_flag_get(uint32_t flag)
{ {
if(FAC_STAT & flag) { if(FAC_STAT & flag)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;

138
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_fmc.c
View File

@ -78,7 +78,8 @@ static fmc_state_enum fmc_ready_wait(uint32_t timeout);
*/ */
void fmc_unlock(void) void fmc_unlock(void)
{ {
if((RESET != (FMC_CTL & FMC_CTL_LK))) { if((RESET != (FMC_CTL & FMC_CTL_LK)))
{
/* write the FMC key */ /* write the FMC key */
FMC_KEY = UNLOCK_KEY0; FMC_KEY = UNLOCK_KEY0;
FMC_KEY = UNLOCK_KEY1; FMC_KEY = UNLOCK_KEY1;
@ -120,7 +121,8 @@ fmc_state_enum fmc_sector_erase(uint32_t address)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
FMC_CTL |= FMC_CTL_SER; FMC_CTL |= FMC_CTL_SER;
/* write the sector address */ /* write the sector address */
FMC_ADDR = address; FMC_ADDR = address;
@ -159,7 +161,8 @@ fmc_state_enum fmc_typical_mass_erase(void)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
/* enable mass erase operation */ /* enable mass erase operation */
FMC_CTL |= FMC_CTL_MER; FMC_CTL |= FMC_CTL_MER;
/* start whole chip erase */ /* start whole chip erase */
@ -197,7 +200,8 @@ fmc_state_enum fmc_protection_removed_mass_erase(void)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
/* remove DCRP area */ /* remove DCRP area */
ob_dcrp_area_config(OB_DCRP_AREA_ERASE_ENABLE, INVALID_DCRP_START_ADDR, INVALID_DCRP_END_ADDR); ob_dcrp_area_config(OB_DCRP_AREA_ERASE_ENABLE, INVALID_DCRP_START_ADDR, INVALID_DCRP_END_ADDR);
/* remove secure-access area */ /* remove secure-access area */
@ -242,7 +246,8 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
/* set the PG bit to start program */ /* set the PG bit to start program */
FMC_CTL |= FMC_CTL_PG; FMC_CTL |= FMC_CTL_PG;
__ISB(); __ISB();
@ -287,7 +292,8 @@ fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data)
data0 = (uint32_t)(data & 0xFFFFFFFFU); data0 = (uint32_t)(data & 0xFFFFFFFFU);
data1 = (uint32_t)((data >> 32U) & 0xFFFFFFFFU); data1 = (uint32_t)((data >> 32U) & 0xFFFFFFFFU);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
/* set the PG bit to start program */ /* set the PG bit to start program */
FMC_CTL |= FMC_CTL_PG; FMC_CTL |= FMC_CTL_PG;
__ISB(); __ISB();
@ -372,7 +378,8 @@ fmc_state_enum fmc_check_programming_area_disable(void)
*/ */
void ob_unlock(void) void ob_unlock(void)
{ {
if(RESET != (FMC_OBCTL & FMC_OBCTL_OBLK)) { if(RESET != (FMC_OBCTL & FMC_OBCTL_OBLK))
{
/* write the FMC key */ /* write the FMC key */
FMC_OBKEY = OB_UNLOCK_KEY0; FMC_OBKEY = OB_UNLOCK_KEY0;
FMC_OBKEY = OB_UNLOCK_KEY1; FMC_OBKEY = OB_UNLOCK_KEY1;
@ -442,7 +449,8 @@ fmc_state_enum ob_factory_value_config(void)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
/* get the option byte security protection value */ /* get the option byte security protection value */
obstat0_reg = (FMC_OBSTAT0_EFT & FMC_OBSTAT0_EFT_SPC); obstat0_reg = (FMC_OBSTAT0_EFT & FMC_OBSTAT0_EFT_SPC);
/* write factory value to FMC_OBSTAT0_MDF */ /* write factory value to FMC_OBSTAT0_MDF */
@ -488,7 +496,8 @@ fmc_state_enum ob_secure_access_mode_enable(void)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
obstat0_reg = FMC_OBSTAT0_EFT; obstat0_reg = FMC_OBSTAT0_EFT;
/* enable secure access mode */ /* enable secure access mode */
obstat0_reg |= FMC_OBSTAT0_MDF_SCR; obstat0_reg |= FMC_OBSTAT0_MDF_SCR;
@ -522,7 +531,8 @@ fmc_state_enum ob_secure_access_mode_disable(void)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
obstat0_reg = FMC_OBSTAT0_EFT; obstat0_reg = FMC_OBSTAT0_EFT;
/* disable secure access mode */ /* disable secure access mode */
obstat0_reg &= ~FMC_OBSTAT0_MDF_SCR; obstat0_reg &= ~FMC_OBSTAT0_MDF_SCR;
@ -560,7 +570,8 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
obstat0_reg = FMC_OBSTAT0_EFT; obstat0_reg = FMC_OBSTAT0_EFT;
/* reset the OBSTAT0_SPC, set according to ob_spc */ /* reset the OBSTAT0_SPC, set according to ob_spc */
obstat0_reg &= ~FMC_OBSTAT0_MDF_SPC; obstat0_reg &= ~FMC_OBSTAT0_MDF_SPC;
@ -600,7 +611,8 @@ fmc_state_enum ob_bor_threshold_config(uint32_t ob_bor_th)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
obstat0_reg = FMC_OBSTAT0_EFT; obstat0_reg = FMC_OBSTAT0_EFT;
/* set BOR threshold level */ /* set BOR threshold level */
obstat0_reg &= ~FMC_OBSTAT0_MDF_BOR_TH; obstat0_reg &= ~FMC_OBSTAT0_MDF_BOR_TH;
@ -654,7 +666,8 @@ fmc_state_enum ob_low_power_config(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uin
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
obstat0_reg = FMC_OBSTAT0_EFT; obstat0_reg = FMC_OBSTAT0_EFT;
/* set according to ob_fwdgt, ob_deepsleep, ob_stdby, ob_fwdg_suspend_deepsleep, ob_fwdg_suspend_standby */ /* set according to ob_fwdgt, ob_deepsleep, ob_stdby, ob_fwdg_suspend_deepsleep, ob_fwdg_suspend_standby */
obstat0_reg &= ~(FMC_OBSTAT0_MDF_NWDG_HW | FMC_OBSTAT0_MDF_NRST_DPSLP | FMC_OBSTAT0_MDF_NRST_STDBY obstat0_reg &= ~(FMC_OBSTAT0_MDF_NWDG_HW | FMC_OBSTAT0_MDF_NRST_DPSLP | FMC_OBSTAT0_MDF_NRST_STDBY
@ -700,7 +713,8 @@ fmc_state_enum ob_tcm_ecc_config(uint32_t ob_itcmecc, uint32_t ob_dtcm0ecc, uint
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
obstat0_reg = FMC_OBSTAT0_EFT; obstat0_reg = FMC_OBSTAT0_EFT;
/* set according to ob_itcmecc, ob_dtcm0ecc, ob_stdby, ob_dtcm1ecc */ /* set according to ob_itcmecc, ob_dtcm0ecc, ob_stdby, ob_dtcm1ecc */
obstat0_reg &= ~(FMC_OBSTAT0_MDF_ITCMECCEN | FMC_OBSTAT0_MDF_DTCM0ECCEN | FMC_OBSTAT0_MDF_DTCM1ECCEN); obstat0_reg &= ~(FMC_OBSTAT0_MDF_ITCMECCEN | FMC_OBSTAT0_MDF_DTCM0ECCEN | FMC_OBSTAT0_MDF_DTCM1ECCEN);
@ -737,7 +751,8 @@ fmc_state_enum ob_iospeed_optimize_config(uint32_t ob_iospeed_op)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
obstat0_reg = FMC_OBSTAT0_EFT; obstat0_reg = FMC_OBSTAT0_EFT;
/* set according to ob_iospeed_op */ /* set according to ob_iospeed_op */
obstat0_reg &= ~(FMC_OBSTAT0_MDF_IOSPDOPEN); obstat0_reg &= ~(FMC_OBSTAT0_MDF_IOSPDOPEN);
@ -786,7 +801,8 @@ fmc_state_enum ob_tcm_shared_ram_config(uint32_t itcm_shared_ram_size, uint32_t
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
obstat1_reg = FMC_OBSTAT1_EFT; obstat1_reg = FMC_OBSTAT1_EFT;
/* set ITCM shared ram size according to itcm_shared_ram_size */ /* set ITCM shared ram size according to itcm_shared_ram_size */
@ -827,7 +843,8 @@ fmc_state_enum ob_data_program(uint16_t ob_data)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
obstat1_reg = FMC_OBSTAT1_EFT; obstat1_reg = FMC_OBSTAT1_EFT;
/* modify user data according to ob_data */ /* modify user data according to ob_data */
@ -867,10 +884,12 @@ fmc_state_enum ob_boot_address_config(uint8_t boot_pin, uint16_t boot_address)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
btaddr_reg = FMC_BTADDR_EFT; btaddr_reg = FMC_BTADDR_EFT;
if(BOOT_PIN_0 == boot_pin) { if(BOOT_PIN_0 == boot_pin)
{
/* set to boot address 0 */ /* set to boot address 0 */
btaddr_reg &= ~FMC_BTADDR_MDF_BOOT_ADDR0; btaddr_reg &= ~FMC_BTADDR_MDF_BOOT_ADDR0;
btaddr_reg |= (uint32_t)((uint32_t)boot_address << BTADDR_BOOT_ADDR0_OFFSET); btaddr_reg |= (uint32_t)((uint32_t)boot_address << BTADDR_BOOT_ADDR0_OFFSET);
@ -913,7 +932,8 @@ fmc_state_enum ob_dcrp_area_config(uint32_t dcrp_eren, uint32_t dcrp_start, uint
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
dcrpaddr_reg = 0U; dcrpaddr_reg = 0U;
dcrpaddr_reg |= dcrp_eren; dcrpaddr_reg |= dcrp_eren;
dcrpaddr_reg |= dcrp_start; dcrpaddr_reg |= dcrp_start;
@ -952,7 +972,8 @@ fmc_state_enum ob_secure_area_config(uint32_t scr_eren, uint32_t scr_start, uint
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
scraddr_reg = 0U; scraddr_reg = 0U;
scraddr_reg |= scr_eren; scraddr_reg |= scr_eren;
scraddr_reg |= scr_start; scraddr_reg |= scr_start;
@ -1011,7 +1032,8 @@ fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
wp_reg &= ~ob_wp; wp_reg &= ~ob_wp;
FMC_WP_MDF = wp_reg; FMC_WP_MDF = wp_reg;
} }
@ -1067,7 +1089,8 @@ fmc_state_enum ob_write_protection_disable(uint32_t ob_wp)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
wp_reg |= ob_wp; wp_reg |= ob_wp;
FMC_WP_MDF = wp_reg; FMC_WP_MDF = wp_reg;
} }
@ -1085,7 +1108,8 @@ FlagStatus ob_secure_mode_get(void)
{ {
FlagStatus secure_mode_state = RESET; FlagStatus secure_mode_state = RESET;
if(OB_SECURE_MODE_ENABLE == (uint32_t)(FMC_OBSTAT0_EFT & FMC_OBSTAT0_EFT_SCR)) { if(OB_SECURE_MODE_ENABLE == (uint32_t)(FMC_OBSTAT0_EFT & FMC_OBSTAT0_EFT_SCR))
{
secure_mode_state = SET; secure_mode_state = SET;
} else { } else {
secure_mode_state = RESET; secure_mode_state = RESET;
@ -1103,7 +1127,8 @@ FlagStatus ob_security_protection_flag_get(void)
{ {
FlagStatus spc_state = RESET; FlagStatus spc_state = RESET;
if(((uint8_t)(FMC_OBSTAT0_EFT >> OBSTAT0_SPC_OFFSET)) != (uint8_t)FMC_NSPC) { if(((uint8_t)(FMC_OBSTAT0_EFT >> OBSTAT0_SPC_OFFSET)) != (uint8_t)FMC_NSPC)
{
spc_state = SET; spc_state = SET;
} else { } else {
spc_state = RESET; spc_state = RESET;
@ -1192,7 +1217,8 @@ FlagStatus ob_iospeed_optimize_get(void)
{ {
FlagStatus iospeed_opt_state = RESET; FlagStatus iospeed_opt_state = RESET;
if(OB_IOSPDOPEN_ENABLE == (uint32_t)(FMC_OBSTAT0_EFT & FMC_OBSTAT0_EFT_IOSPDOPEN)) { if(OB_IOSPDOPEN_ENABLE == (uint32_t)(FMC_OBSTAT0_EFT & FMC_OBSTAT0_EFT_IOSPDOPEN))
{
iospeed_opt_state = SET; iospeed_opt_state = SET;
} else { } else {
iospeed_opt_state = RESET; iospeed_opt_state = RESET;
@ -1224,7 +1250,8 @@ void ob_tcm_shared_ram_size_get(uint32_t *itcm_shared_ram_kb_size, uint32_t *dtc
itcm_size_value = (uint32_t)((uint32_t)FMC_OBSTAT1_EFT & FMC_OBSTAT1_EFT_ITCM_SZ_SHRRAM); itcm_size_value = (uint32_t)((uint32_t)FMC_OBSTAT1_EFT & FMC_OBSTAT1_EFT_ITCM_SZ_SHRRAM);
dtcm_size_value = (uint32_t)((uint32_t)FMC_OBSTAT1_EFT & FMC_OBSTAT1_EFT_DTCM_SZ_SHRRAM); dtcm_size_value = (uint32_t)((uint32_t)FMC_OBSTAT1_EFT & FMC_OBSTAT1_EFT_DTCM_SZ_SHRRAM);
switch(itcm_size_value) { switch(itcm_size_value)
{
case OB_ITCM_SHARED_RAM_0KB: case OB_ITCM_SHARED_RAM_0KB:
/* ITCM shared RAM size is 0KB */ /* ITCM shared RAM size is 0KB */
*itcm_shared_ram_kb_size = 0U; *itcm_shared_ram_kb_size = 0U;
@ -1249,7 +1276,8 @@ void ob_tcm_shared_ram_size_get(uint32_t *itcm_shared_ram_kb_size, uint32_t *dtc
break; break;
} }
switch(dtcm_size_value) { switch(dtcm_size_value)
{
case OB_DTCM_SHARED_RAM_0KB: case OB_DTCM_SHARED_RAM_0KB:
/* DTCM shared RAM size is 0KB */ /* DTCM shared RAM size is 0KB */
*dtcm_shared_ram_kb_size = 0U; *dtcm_shared_ram_kb_size = 0U;
@ -1300,7 +1328,8 @@ uint32_t ob_boot_address_get(uint8_t boot_pin)
uint32_t boot_address; uint32_t boot_address;
uint32_t btaddr_reg = FMC_BTADDR_EFT; uint32_t btaddr_reg = FMC_BTADDR_EFT;
if(BOOT_PIN_0 == boot_pin) { if(BOOT_PIN_0 == boot_pin)
{
/* get boot address 0 */ /* get boot address 0 */
boot_address = (uint32_t)((btaddr_reg & FMC_BTADDR_EFT_BOOT_ADDR0) << 16u); boot_address = (uint32_t)((btaddr_reg & FMC_BTADDR_EFT_BOOT_ADDR0) << 16u);
} else { } else {
@ -1333,12 +1362,14 @@ uint8_t ob_dcrp_area_get(uint32_t *dcrp_erase_option, uint32_t *dcrp_area_start_
*dcrp_erase_option = (uint32_t)(dcrpaddr_reg & FMC_DCRPADDR_EFT_DCRP_EREN); *dcrp_erase_option = (uint32_t)(dcrpaddr_reg & FMC_DCRPADDR_EFT_DCRP_EREN);
*dcrp_area_start_addr = ((uint32_t)(dcrpaddr_reg & FMC_DCRPADDR_EFT_DCRP_AREA_START)) >> DCRPADDR_DCRP_AREA_START_OFFSET; *dcrp_area_start_addr = ((uint32_t)(dcrpaddr_reg & FMC_DCRPADDR_EFT_DCRP_AREA_START)) >> DCRPADDR_DCRP_AREA_START_OFFSET;
*dcrp_area_end_addr = ((uint32_t)(dcrpaddr_reg & FMC_DCRPADDR_EFT_DCRP_AREA_END)) >> DCRPADDR_DCRP_AREA_END_OFFSET; *dcrp_area_end_addr = ((uint32_t)(dcrpaddr_reg & FMC_DCRPADDR_EFT_DCRP_AREA_END)) >> DCRPADDR_DCRP_AREA_END_OFFSET;
if((*dcrp_area_start_addr) == (*dcrp_area_end_addr)) { if((*dcrp_area_start_addr) == (*dcrp_area_end_addr))
{
/* the whole main flash memory is DCRP area */ /* the whole main flash memory is DCRP area */
*dcrp_area_start_addr = MAIN_FLASH_BASE_ADDRESS; *dcrp_area_start_addr = MAIN_FLASH_BASE_ADDRESS;
*dcrp_area_end_addr = MAIN_FLASH_BASE_ADDRESS + main_flash_size - 1U; *dcrp_area_end_addr = MAIN_FLASH_BASE_ADDRESS + main_flash_size - 1U;
return VLD_AREA_ADDRESS; return VLD_AREA_ADDRESS;
} else if((*dcrp_area_start_addr) < (*dcrp_area_end_addr)) { } else if((*dcrp_area_start_addr) < (*dcrp_area_end_addr))
{
/* get DCRP area start address */ /* get DCRP area start address */
*dcrp_area_start_addr = (*dcrp_area_start_addr) * DCRP_SIZE_UNIT; *dcrp_area_start_addr = (*dcrp_area_start_addr) * DCRP_SIZE_UNIT;
*dcrp_area_start_addr += MAIN_FLASH_BASE_ADDRESS; *dcrp_area_start_addr += MAIN_FLASH_BASE_ADDRESS;
@ -1375,12 +1406,14 @@ uint8_t ob_secure_area_get(uint32_t *secure_area_option, uint32_t *scr_area_star
*secure_area_option = (uint32_t)(scraddr_reg & FMC_SCRADDR_EFT_SCR_EREN); *secure_area_option = (uint32_t)(scraddr_reg & FMC_SCRADDR_EFT_SCR_EREN);
*scr_area_start_addr = ((uint32_t)(scraddr_reg & FMC_SCRADDR_EFT_SCR_AREA_START)) >> SCRADDR_SCR_AREA_START_OFFSET; *scr_area_start_addr = ((uint32_t)(scraddr_reg & FMC_SCRADDR_EFT_SCR_AREA_START)) >> SCRADDR_SCR_AREA_START_OFFSET;
*scr_area_end_addr = ((uint32_t)(scraddr_reg & FMC_SCRADDR_EFT_SCR_AREA_END)) >> SCRADDR_SCR_AREA_END_OFFSET; *scr_area_end_addr = ((uint32_t)(scraddr_reg & FMC_SCRADDR_EFT_SCR_AREA_END)) >> SCRADDR_SCR_AREA_END_OFFSET;
if((*scr_area_start_addr) == (*scr_area_end_addr)) { if((*scr_area_start_addr) == (*scr_area_end_addr))
{
/* the whole main flash memory is secure-access area */ /* the whole main flash memory is secure-access area */
*scr_area_start_addr = MAIN_FLASH_BASE_ADDRESS; *scr_area_start_addr = MAIN_FLASH_BASE_ADDRESS;
*scr_area_end_addr = MAIN_FLASH_BASE_ADDRESS + main_flash_size - 1U; *scr_area_end_addr = MAIN_FLASH_BASE_ADDRESS + main_flash_size - 1U;
return VLD_AREA_ADDRESS; return VLD_AREA_ADDRESS;
} else if((*scr_area_start_addr) < (*scr_area_end_addr)) { } else if((*scr_area_start_addr) < (*scr_area_end_addr))
{
/* get secure-access area start address */ /* get secure-access area start address */
*scr_area_start_addr = (*scr_area_start_addr) * SCR_SIZE_UNIT; *scr_area_start_addr = (*scr_area_start_addr) * SCR_SIZE_UNIT;
*scr_area_start_addr += MAIN_FLASH_BASE_ADDRESS; *scr_area_start_addr += MAIN_FLASH_BASE_ADDRESS;
@ -1431,7 +1464,8 @@ fmc_state_enum fmc_no_rtdec_config(uint32_t nodec_area_start, uint32_t nodec_are
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
fmc_unlock(); fmc_unlock();
nodec_reg = 0U; nodec_reg = 0U;
nodec_reg |= nodec_area_start; nodec_reg |= nodec_area_start;
@ -1467,7 +1501,8 @@ fmc_state_enum fmc_aes_iv_config(uint32_t *aes_iv)
/* wait for the FMC ready */ /* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) { if(FMC_READY == fmc_state)
{
fmc_unlock(); fmc_unlock();
FMC_AESIV0_MDF = *(uint32_t *)(aes_iv_addr); FMC_AESIV0_MDF = *(uint32_t *)(aes_iv_addr);
aes_iv_addr += 4U; aes_iv_addr += 4U;
@ -1556,7 +1591,8 @@ void fmc_pid_get(uint32_t *pid)
*/ */
FlagStatus fmc_flag_get(fmc_flag_enum flag) FlagStatus fmc_flag_get(fmc_flag_enum flag)
{ {
if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))) { if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag))))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -1647,7 +1683,8 @@ FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum int_flag)
/* get the corresponding flag bit status */ /* get the corresponding flag bit status */
flagstatus = (FMC_REG_VAL2(int_flag) & BIT(FMC_BIT_POS2(int_flag))); flagstatus = (FMC_REG_VAL2(int_flag) & BIT(FMC_BIT_POS2(int_flag)));
if(flagstatus && intenable) { if(flagstatus && intenable)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -1694,22 +1731,30 @@ static fmc_state_enum fmc_state_get(void)
{ {
fmc_state_enum fmc_state = FMC_READY; fmc_state_enum fmc_state = FMC_READY;
if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)) { if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY))
{
fmc_state = FMC_BUSY; fmc_state = FMC_BUSY;
} else { } else {
if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)) { if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR))
{
fmc_state = FMC_WPERR; fmc_state = FMC_WPERR;
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGSERR)) { } else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGSERR))
{
fmc_state = FMC_PGSERR; fmc_state = FMC_PGSERR;
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_RPERR)) { } else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_RPERR))
{
fmc_state = FMC_RPERR; fmc_state = FMC_RPERR;
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_RSERR)) { } else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_RSERR))
{
fmc_state = FMC_RSERR; fmc_state = FMC_RSERR;
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_ECCCOR)) { } else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_ECCCOR))
{
fmc_state = FMC_ECCCOR; fmc_state = FMC_ECCCOR;
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_ECCDET)) { } else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_ECCDET))
{
fmc_state = FMC_ECCDET; fmc_state = FMC_ECCDET;
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_OBMERR)) { } else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_OBMERR))
{
fmc_state = FMC_OBMERR; fmc_state = FMC_OBMERR;
} else { } else {
/* illegal parameters */ /* illegal parameters */
@ -1747,7 +1792,8 @@ static fmc_state_enum fmc_ready_wait(uint32_t timeout)
timeout--; timeout--;
} while((FMC_BUSY == fmc_state) && (0U != timeout)); } while((FMC_BUSY == fmc_state) && (0U != timeout));
if(FMC_BUSY == fmc_state) { if(FMC_BUSY == fmc_state)
{
fmc_state = FMC_TOERR; fmc_state = FMC_TOERR;
} }
/* return the FMC state */ /* return the FMC state */

62
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_fwdgt.c
View File

@ -8,38 +8,38 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
#include "gd32h7xx_fwdgt.h" #include "gd32h7xx_fwdgt.h"
/* write value to FWDGT_CTL_CMD bit field */ /* write value to FWDGT_CTL_CMD bit field */
#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) #define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U))
/* write value to FWDGT_RLD_RLD bit field */ /* write value to FWDGT_RLD_RLD bit field */
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) #define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U))
/* write value to FWDGT_WND_WND bit field */ /* write value to FWDGT_WND_WND bit field */
#define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) #define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U))
/*! /*!
\brief enable write access to FWDGT_PSC, FWDGT_RLD and FWDGT_WND \brief enable write access to FWDGT_PSC, FWDGT_RLD and FWDGT_WND
@ -101,7 +101,8 @@ ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
flag_status = FWDGT_STAT & FWDGT_STAT_PUD; flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
} while((--timeout > (uint32_t)0x00000000U) && (RESET != flag_status)); } while((--timeout > (uint32_t)0x00000000U) && (RESET != flag_status));
if(RESET != flag_status){ if(RESET != flag_status)
{
return ERROR; return ERROR;
} }
@ -130,7 +131,8 @@ ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
flag_status = FWDGT_STAT & FWDGT_STAT_RUD; flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
}while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status)); }while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){ if ((uint32_t)RESET != flag_status)
{
return ERROR; return ERROR;
} }
@ -158,8 +160,9 @@ ErrStatus fwdgt_window_value_config(uint16_t window_value)
flag_status = FWDGT_STAT & FWDGT_STAT_WUD; flag_status = FWDGT_STAT & FWDGT_STAT_WUD;
}while((--time_index > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status)); }while((--time_index > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){ if ((uint32_t)RESET != flag_status)
return ERROR; {
return ERROR;
} }
FWDGT_WND = WND_WND(window_value); FWDGT_WND = WND_WND(window_value);
@ -205,8 +208,9 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
do{ do{
flag_status = FWDGT_STAT & FWDGT_STAT_PUD; flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
}while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status)); }while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){ if ((uint32_t)RESET != flag_status)
{
return ERROR; return ERROR;
} }
@ -219,12 +223,13 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
flag_status = FWDGT_STAT & FWDGT_STAT_RUD; flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
}while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status)); }while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){ if ((uint32_t)RESET != flag_status)
{
return ERROR; return ERROR;
} }
FWDGT_RLD = RLD_RLD(reload_value); FWDGT_RLD = RLD_RLD(reload_value);
/* reload the counter */ /* reload the counter */
FWDGT_CTL = FWDGT_KEY_RELOAD; FWDGT_CTL = FWDGT_KEY_RELOAD;
@ -233,7 +238,7 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
/*! /*!
\brief get flag state of FWDGT \brief get flag state of FWDGT
\param[in] flag: flag to get \param[in] flag: flag to get
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
\arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
@ -243,7 +248,8 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
*/ */
FlagStatus fwdgt_flag_get(uint16_t flag) FlagStatus fwdgt_flag_get(uint16_t flag)
{ {
if (RESET != (FWDGT_STAT & flag)){ if (RESET != (FWDGT_STAT & flag))
{
return SET; return SET;
} }
return RESET; return RESET;

139
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_gpio.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -44,7 +44,8 @@ OF SUCH DAMAGE.
*/ */
void gpio_deinit(uint32_t gpio_periph) void gpio_deinit(uint32_t gpio_periph)
{ {
switch(gpio_periph){ switch(gpio_periph)
{
case GPIOA: case GPIOA:
/* reset GPIOA */ /* reset GPIOA */
rcu_periph_reset_enable(RCU_GPIOARST); rcu_periph_reset_enable(RCU_GPIOARST);
@ -130,8 +131,10 @@ void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, u
ctl = GPIO_CTL(gpio_periph); ctl = GPIO_CTL(gpio_periph);
pupd = GPIO_PUD(gpio_periph); pupd = GPIO_PUD(gpio_periph);
for(i = 0U;i < 16U;i++){ for(i = 0U;i < 16U;i++)
if((1U << i) & pin){ {
if((1U << i) & pin)
{
/* clear the specified pin mode bits */ /* clear the specified pin mode bits */
ctl &= ~GPIO_MODE_MASK(i); ctl &= ~GPIO_MODE_MASK(i);
/* set the specified pin mode bits */ /* set the specified pin mode bits */
@ -152,15 +155,15 @@ void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, u
\brief set GPIO output type and speed \brief set GPIO output type and speed
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K) \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K)
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIOx(x = A,B,C,D,E,F,G,H,J,K) \arg GPIOx(x = A,B,C,D,E,F,G,H,J,K)
\param[in] otype: gpio pin output mode \param[in] otype: gpio pin output mode
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIO_OTYPE_PP: push pull mode \arg GPIO_OTYPE_PP: push pull mode
\arg GPIO_OTYPE_OD: open drain mode \arg GPIO_OTYPE_OD: open drain mode
\param[in] speed: gpio pin output max speed \param[in] speed: gpio pin output max speed
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIO_OSPEED_12MHZ: output max speed 12MHz \arg GPIO_OSPEED_12MHZ: output max speed 12MHz
\arg GPIO_OSPEED_60MHZ: output max speed 60MHz \arg GPIO_OSPEED_60MHZ: output max speed 60MHz
\arg GPIO_OSPEED_85MHZ: output max speed 85MHz \arg GPIO_OSPEED_85MHZ: output max speed 85MHz
\arg GPIO_OSPEED_100_220MHZ: output max speed 100/220MHz \arg GPIO_OSPEED_100_220MHZ: output max speed 100/220MHz
\param[in] pin: GPIO pin \param[in] pin: GPIO pin
@ -174,7 +177,8 @@ void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed
uint16_t i; uint16_t i;
uint32_t ospeed; uint32_t ospeed;
if(GPIO_OTYPE_OD == otype){ if(GPIO_OTYPE_OD == otype)
{
GPIO_OMODE(gpio_periph) |= (uint32_t)pin; GPIO_OMODE(gpio_periph) |= (uint32_t)pin;
}else{ }else{
GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin);
@ -183,8 +187,10 @@ void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed
/* get the specified pin output speed bits value */ /* get the specified pin output speed bits value */
ospeed = GPIO_OSPD(gpio_periph); ospeed = GPIO_OSPD(gpio_periph);
for(i = 0U;i < 16U;i++){ for(i = 0U;i < 16U;i++)
if((1U << i) & pin){ {
if((1U << i) & pin)
{
/* clear the specified pin output speed bits */ /* clear the specified pin output speed bits */
ospeed &= ~GPIO_OSPEED_MASK(i); ospeed &= ~GPIO_OSPEED_MASK(i);
/* set the specified pin output speed bits */ /* set the specified pin output speed bits */
@ -196,9 +202,9 @@ void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed
/*! /*!
\brief set GPIO pin bit \brief set GPIO pin bit
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K) \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K)
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIOx(x = A,B,C,D,E,F,G,H,J,K) \arg GPIOx(x = A,B,C,D,E,F,G,H,J,K)
\param[in] pin: GPIO pin \param[in] pin: GPIO pin
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
@ -212,9 +218,9 @@ void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
/*! /*!
\brief reset GPIO pin bit \brief reset GPIO pin bit
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K) \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K)
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIOx(x = A,B,C,F) \arg GPIOx(x = A,B,C,F)
\param[in] pin: GPIO pin \param[in] pin: GPIO pin
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
@ -228,9 +234,9 @@ void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
/*! /*!
\brief write data to the specified GPIO pin \brief write data to the specified GPIO pin
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K) \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K)
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIOx(x = A,B,C,D,E,F,G,H,J,K) \arg GPIOx(x = A,B,C,D,E,F,G,H,J,K)
\param[in] pin: GPIO pin \param[in] pin: GPIO pin
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
@ -243,7 +249,8 @@ void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
*/ */
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
{ {
if(RESET != bit_value){ if(RESET != bit_value)
{
GPIO_BOP(gpio_periph) = (uint32_t)pin; GPIO_BOP(gpio_periph) = (uint32_t)pin;
}else{ }else{
GPIO_BC(gpio_periph) = (uint32_t)pin; GPIO_BC(gpio_periph) = (uint32_t)pin;
@ -252,9 +259,9 @@ void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
/*! /*!
\brief write data to the specified GPIO port \brief write data to the specified GPIO port
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K) \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K)
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIOx(x = A,B,C,D,E,F,G,H,J,K) \arg GPIOx(x = A,B,C,D,E,F,G,H,J,K)
\param[in] data: specify the value to be written to the port output control register \param[in] data: specify the value to be written to the port output control register
\param[out] none \param[out] none
\retval none \retval none
@ -266,9 +273,9 @@ void gpio_port_write(uint32_t gpio_periph, uint16_t data)
/*! /*!
\brief set GPIO input filter \brief set GPIO input filter
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K) \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K)
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIOx(x = A,B,C,D,E,F,G,H,J,K) \arg GPIOx(x = A,B,C,D,E,F,G,H,J,K)
\param[in] speriod: gpio pin input sample period \param[in] speriod: gpio pin input sample period
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIO_ISPERIOD(x): x = 0 ~ 255 \arg GPIO_ISPERIOD(x): x = 0 ~ 255
@ -291,11 +298,13 @@ void gpio_input_filter_set(uint32_t gpio_periph, uint8_t speriod, uint32_t iftyp
uint32_t iftp; uint32_t iftp;
isperiod = GPIO_IFL(gpio_periph); isperiod = GPIO_IFL(gpio_periph);
if(pin & 0x000000FFU){ if(pin & 0x000000FFU)
{
isperiod &= ~GPIO_IFL_FLPRD0; isperiod &= ~GPIO_IFL_FLPRD0;
isperiod |= (uint32_t)speriod; isperiod |= (uint32_t)speriod;
} }
if(pin & 0x0000FF00U){ if(pin & 0x0000FF00U)
{
isperiod &= ~GPIO_IFL_FLPRD1; isperiod &= ~GPIO_IFL_FLPRD1;
isperiod |= ((uint32_t)speriod << 8U); isperiod |= ((uint32_t)speriod << 8U);
} }
@ -303,8 +312,10 @@ void gpio_input_filter_set(uint32_t gpio_periph, uint8_t speriod, uint32_t iftyp
/* get the specified pin output speed bits value */ /* get the specified pin output speed bits value */
iftp = GPIO_IFTP(gpio_periph); iftp = GPIO_IFTP(gpio_periph);
for(i = 0U;i < 16U;i++){ for(i = 0U;i < 16U;i++)
if((1U << i) & pin){ {
if((1U << i) & pin)
{
/* clear the specified pin output speed bits */ /* clear the specified pin output speed bits */
iftp &= ~GPIO_IFTYPE_MASK(i); iftp &= ~GPIO_IFTYPE_MASK(i);
/* set the specified pin output speed bits */ /* set the specified pin output speed bits */
@ -316,9 +327,9 @@ void gpio_input_filter_set(uint32_t gpio_periph, uint8_t speriod, uint32_t iftyp
/*! /*!
\brief get GPIO pin input status \brief get GPIO pin input status
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K) \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K)
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIOx(x = A,B,C,D,E,F,G,H,J,K) \arg GPIOx(x = A,B,C,D,E,F,G,H,J,K)
\param[in] pin: GPIO pin \param[in] pin: GPIO pin
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
@ -327,8 +338,9 @@ void gpio_input_filter_set(uint32_t gpio_periph, uint8_t speriod, uint32_t iftyp
*/ */
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
{ {
if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin)))
return SET; {
return SET;
}else{ }else{
return RESET; return RESET;
} }
@ -336,9 +348,9 @@ FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
/*! /*!
\brief get GPIO port input status \brief get GPIO port input status
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K) \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K)
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIOx(x = A,B,C,D,E,F,G,H,J,K) \arg GPIOx(x = A,B,C,D,E,F,G,H,J,K)
\param[out] none \param[out] none
\retval state of GPIO all pins \retval state of GPIO all pins
*/ */
@ -349,9 +361,9 @@ uint16_t gpio_input_port_get(uint32_t gpio_periph)
/*! /*!
\brief get GPIO pin output status \brief get GPIO pin output status
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K) \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K)
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIOx(x = A,B,C,D,E,F,G,H,J,K) \arg GPIOx(x = A,B,C,D,E,F,G,H,J,K)
\param[in] pin: GPIO pin \param[in] pin: GPIO pin
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
@ -360,7 +372,8 @@ uint16_t gpio_input_port_get(uint32_t gpio_periph)
*/ */
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
{ {
if((uint32_t)RESET != (GPIO_OCTL(gpio_periph)&(pin))){ if((uint32_t)RESET != (GPIO_OCTL(gpio_periph)&(pin)))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -369,9 +382,9 @@ FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
/*! /*!
\brief get GPIO port output status \brief get GPIO port output status
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K) \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K)
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIOx(x = A,B,C,D,E,F,G,H,J,K) \arg GPIOx(x = A,B,C,D,E,F,G,H,J,K)
\param[out] none \param[out] none
\retval state of GPIO all pins \retval state of GPIO all pins
*/ */
@ -382,9 +395,9 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph)
/*! /*!
\brief set GPIO alternate function \brief set GPIO alternate function
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K) \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K)
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIOx(x = A,B,C,D,E,F,G,H,J,K) \arg GPIOx(x = A,B,C,D,E,F,G,H,J,K)
\param[in] alt_func_num: GPIO pin af function, please refer to specific device datasheet \param[in] alt_func_num: GPIO pin af function, please refer to specific device datasheet
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIO_AF_0: SYSTEM, TIMER40, TIMER41, TIMER42, TIMER43, TIMER44 \arg GPIO_AF_0: SYSTEM, TIMER40, TIMER41, TIMER42, TIMER43, TIMER44
@ -394,7 +407,7 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph)
\arg GPIO_AF_4: TIMER14, TIMER30, TIMER31, I2C0, I2C1, I2C2, I2C3, USART0, HPDF, OSPIM, TLI \arg GPIO_AF_4: TIMER14, TIMER30, TIMER31, I2C0, I2C1, I2C2, I2C3, USART0, HPDF, OSPIM, TLI
\arg GPIO_AF_5: SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, CAN2 \arg GPIO_AF_5: SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, CAN2
\arg GPIO_AF_6: UART3, SPI2, I2C3, HPDF, SAI0, ETH1, EDOUT, OSPIM \arg GPIO_AF_6: UART3, SPI2, I2C3, HPDF, SAI0, ETH1, EDOUT, OSPIM
\arg GPIO_AF_7: USART0, USART1, USART2, USART5, UART6, TIMER40, TIMER41, TIMER42, TIMER43, \arg GPIO_AF_7: USART0, USART1, USART2, USART5, UART6, TIMER40, TIMER41, TIMER42, TIMER43,
SPI1, SPI2, SPI5, SDIO0, USBHS1 SPI1, SPI2, SPI5, SDIO0, USBHS1
\arg GPIO_AF_8: UART3, UART4, UART7, SPI5, SDIO0, RSPDIF, TIMER44, USBHS1, SAI1, SAI2 \arg GPIO_AF_8: UART3, UART4, UART7, SPI5, SDIO0, RSPDIF, TIMER44, USBHS1, SAI1, SAI2
\arg GPIO_AF_9: SDIO1, TRGSEL, CAN0, CAN1, TLI, OPSIM, EXMC, RSPDIF, SAI2 \arg GPIO_AF_9: SDIO1, TRGSEL, CAN0, CAN1, TLI, OPSIM, EXMC, RSPDIF, SAI2
@ -418,16 +431,20 @@ void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin)
afrl = GPIO_AFSEL0(gpio_periph); afrl = GPIO_AFSEL0(gpio_periph);
afrh = GPIO_AFSEL1(gpio_periph); afrh = GPIO_AFSEL1(gpio_periph);
for(i = 0U;i < 8U;i++){ for(i = 0U;i < 8U;i++)
if((1U << i) & pin){ {
if((1U << i) & pin)
{
/* clear the specified pin alternate function bits */ /* clear the specified pin alternate function bits */
afrl &= ~GPIO_AFR_MASK(i); afrl &= ~GPIO_AFR_MASK(i);
afrl |= GPIO_AFR_SET(i,alt_func_num); afrl |= GPIO_AFR_SET(i,alt_func_num);
} }
} }
for(i = 8U;i < 16U;i++){ for(i = 8U;i < 16U;i++)
if((1U << i) & pin){ {
if((1U << i) & pin)
{
/* clear the specified pin alternate function bits */ /* clear the specified pin alternate function bits */
afrh &= ~GPIO_AFR_MASK(i - 8U); afrh &= ~GPIO_AFR_MASK(i - 8U);
afrh |= GPIO_AFR_SET(i - 8U,alt_func_num); afrh |= GPIO_AFR_SET(i - 8U,alt_func_num);
@ -440,9 +457,9 @@ void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin)
/*! /*!
\brief lock GPIO pin bit \brief lock GPIO pin bit
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K) \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K)
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIOx(x = A,B,C,D,E,F,G,H,J,K) \arg GPIOx(x = A,B,C,D,E,F,G,H,J,K)
\param[in] pin: GPIO pin \param[in] pin: GPIO pin
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
@ -464,7 +481,7 @@ void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
/*! /*!
\brief toggle GPIO pin status \brief toggle GPIO pin status
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K) \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,J,K)
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg GPIOx(x = A,B,C,D,E,F,G,H,J,K) \arg GPIOx(x = A,B,C,D,E,F,G,H,J,K)
\param[in] pin: GPIO pin \param[in] pin: GPIO pin

69
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_hau.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -70,7 +70,8 @@ void hau_init(hau_init_parameter_struct* initpara)
HAU_CTL |= (initpara->algo | initpara->datatype | initpara->mode); HAU_CTL |= (initpara->algo | initpara->datatype | initpara->mode);
/* when mode is HMAC, set the key */ /* when mode is HMAC, set the key */
if(HAU_MODE_HMAC == initpara->mode){ if(HAU_MODE_HMAC == initpara->mode)
{
HAU_CTL &= (~(uint32_t)HAU_CTL_KLM); HAU_CTL &= (~(uint32_t)HAU_CTL_KLM);
HAU_CTL |= initpara->keytype; HAU_CTL |= initpara->keytype;
} }
@ -80,9 +81,9 @@ void hau_init(hau_init_parameter_struct* initpara)
} }
/*! /*!
\brief initialize the structure hau_initpara with default value \brief initialize the structure hau_initpara with default value
\param[in] none \param[in] none
\param[out] initpara: HAU init parameter struct \param[out] initpara: HAU init parameter struct
\retval none \retval none
*/ */
void hau_init_struct_para_init(hau_init_parameter_struct* initpara) void hau_init_struct_para_init(hau_init_parameter_struct* initpara)
@ -168,7 +169,7 @@ void hau_digest_read(hau_digest_parameter_struct* digestpara)
} }
/*! /*!
\brief enable digest calculation \brief enable digest calculation
\param[in] none \param[in] none
\param[out] none \param[out] none
\retval none \retval none
@ -179,7 +180,7 @@ void hau_digest_calculation_enable(void)
} }
/*! /*!
\brief configure single or multiple DMA is used, and digest calculation at the end of a DMA transfer or not \brief configure single or multiple DMA is used, and digest calculation at the end of a DMA transfer or not
\param[in] multi_single \param[in] multi_single
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg SINGLE_DMA_AUTO_DIGEST: message padding and message digest calculation at the end of a DMA transfer \arg SINGLE_DMA_AUTO_DIGEST: message padding and message digest calculation at the end of a DMA transfer
@ -192,7 +193,7 @@ void hau_multiple_single_dma_config(uint32_t multi_single)
HAU_CTL &= (~(uint32_t)HAU_CTL_MDS); HAU_CTL &= (~(uint32_t)HAU_CTL_MDS);
HAU_CTL |= multi_single; HAU_CTL |= multi_single;
} }
/*! /*!
\brief enable the HAU DMA interface \brief enable the HAU DMA interface
\param[in] none \param[in] none
@ -229,7 +230,8 @@ void hau_context_struct_para_init(hau_context_parameter_struct* context)
context->hau_inten_bak = 0U; context->hau_inten_bak = 0U;
context->hau_cfg_bak = 0U; context->hau_cfg_bak = 0U;
context->hau_ctl_bak = 0U; context->hau_ctl_bak = 0U;
for(i = 0U; i <= HMAC_CONTEXT_INTERNAL_REG; i++){ for(i = 0U; i <= HMAC_CONTEXT_INTERNAL_REG; i++)
{
context->hau_ctxs_bak[i] = 0U; context->hau_ctxs_bak[i] = 0U;
} }
} }
@ -251,10 +253,12 @@ void hau_context_save(hau_context_parameter_struct* context_save)
context_save->hau_cfg_bak = HAU_CFG; context_save->hau_cfg_bak = HAU_CFG;
context_save->hau_ctl_bak = HAU_CTL; context_save->hau_ctl_bak = HAU_CTL;
if(0U != (HAU_CTL & HAU_CTL_HMS)){ if(0U != (HAU_CTL & HAU_CTL_HMS))
{
i_max = HMAC_CONTEXT_INTERNAL_REG; i_max = HMAC_CONTEXT_INTERNAL_REG;
} }
for(i = 0U; i <= i_max; i++){ for(i = 0U; i <= i_max; i++)
{
context_save->hau_ctxs_bak[i] = HAU_CTXS(i); context_save->hau_ctxs_bak[i] = HAU_CTXS(i);
} }
} }
@ -278,10 +282,12 @@ void hau_context_restore(hau_context_parameter_struct* context_restore)
HAU_CTL |= HAU_CTL_START; HAU_CTL |= HAU_CTL_START;
/* continue restoring context registers */ /* continue restoring context registers */
if(0U != (HAU_CTL & HAU_CTL_HMS)){ if(0U != (HAU_CTL & HAU_CTL_HMS))
{
i_max = HMAC_CONTEXT_INTERNAL_REG; i_max = HMAC_CONTEXT_INTERNAL_REG;
} }
for(i = 0U; i <= i_max; i++){ for(i = 0U; i <= i_max; i++)
{
HAU_CTXS(i) = context_restore->hau_ctxs_bak[i]; HAU_CTXS(i) = context_restore->hau_ctxs_bak[i];
} }
} }
@ -304,13 +310,15 @@ FlagStatus hau_flag_get(uint32_t flag)
FlagStatus ret_flag = RESET; FlagStatus ret_flag = RESET;
/* check if the flag is in HAU_CTL register */ /* check if the flag is in HAU_CTL register */
if(RESET != (flag & HAU_FLAG_INFIFO_NO_EMPTY)){ if(RESET != (flag & HAU_FLAG_INFIFO_NO_EMPTY))
{
ret = HAU_CTL; ret = HAU_CTL;
}else{ }else{
ret = HAU_STAT; ret = HAU_STAT;
} }
if (RESET != (ret & flag)){ if (RESET != (ret & flag))
{
ret_flag = SET; ret_flag = SET;
} }
@ -335,7 +343,7 @@ void hau_flag_clear(uint32_t flag)
\brief enable the HAU interrupts \brief enable the HAU interrupts
\param[in] interrupt: specify the HAU interrupt source to be enabled \param[in] interrupt: specify the HAU interrupt source to be enabled
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg HAU_INT_DATA_INPUT: a new block can be entered into the IN buffer \arg HAU_INT_DATA_INPUT: a new block can be entered into the IN buffer
\arg HAU_INT_CALCULATION_COMPLETE: calculation complete \arg HAU_INT_CALCULATION_COMPLETE: calculation complete
\param[out] none \param[out] none
\retval none \retval none
@ -376,7 +384,8 @@ FlagStatus hau_interrupt_flag_get(uint32_t int_flag)
/* return the status of the interrupt */ /* return the status of the interrupt */
ret = HAU_STAT; ret = HAU_STAT;
if(RESET != ((HAU_INTEN & ret) & int_flag)){ if(RESET != ((HAU_INTEN & ret) & int_flag))
{
flag = SET; flag = SET;
} }

82
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_hau_sha_md5.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -39,7 +39,7 @@ OF SUCH DAMAGE.
/* HAU SHA/MD5 digest read in HASH mode */ /* HAU SHA/MD5 digest read in HASH mode */
static void hau_sha_md5_digest_read(uint32_t algo, uint8_t output[]); static void hau_sha_md5_digest_read(uint32_t algo, uint8_t output[]);
/* HAU digest calculate process in HASH mode */ /* HAU digest calculate process in HASH mode */
static ErrStatus hau_hash_calculate(uint32_t algo, uint8_t input[], uint32_t in_length, uint8_t output[]); static ErrStatus hau_hash_calculate(uint32_t algo, uint8_t input[], uint32_t in_length, uint8_t output[]);
/* HAU digest calculate process in HMAC mode */ /* HAU digest calculate process in HMAC mode */
static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t key[], uint32_t keysize, uint8_t input[], uint32_t in_length, uint8_t output[]); static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t key[], uint32_t keysize, uint8_t input[], uint32_t in_length, uint8_t output[]);
@ -130,7 +130,7 @@ ErrStatus hau_hmac_sha_256(uint8_t key[], uint32_t keysize, uint8_t input[], uin
{ {
ErrStatus ret = ERROR; ErrStatus ret = ERROR;
ret = hau_hmac_calculate(HAU_ALGO_SHA256, key, keysize, input, in_length, output); ret = hau_hmac_calculate(HAU_ALGO_SHA256, key, keysize, input, in_length, output);
return ret; return ret;
} }
/*! /*!
@ -177,11 +177,12 @@ ErrStatus hau_hmac_md5(uint8_t key[], uint32_t keysize, uint8_t input[], uint32_
static void hau_sha_md5_digest_read(uint32_t algo, uint8_t output[]) static void hau_sha_md5_digest_read(uint32_t algo, uint8_t output[])
{ {
hau_digest_parameter_struct digest_para; hau_digest_parameter_struct digest_para;
uint32_t outputaddr = (uint32_t)output; uint32_t outputaddr = (uint32_t)output;
switch(algo){ switch(algo)
case HAU_ALGO_SHA1: {
/* read the message digest result */ case HAU_ALGO_SHA1:
/* read the message digest result */
hau_digest_read(&digest_para); hau_digest_read(&digest_para);
/* reverse byte order, copy result to outputaddr */ /* reverse byte order, copy result to outputaddr */
*(uint32_t*)(outputaddr) = __REV(digest_para.out[0]); *(uint32_t*)(outputaddr) = __REV(digest_para.out[0]);
@ -195,7 +196,7 @@ static void hau_sha_md5_digest_read(uint32_t algo, uint8_t output[])
*(uint32_t*)(outputaddr) = __REV(digest_para.out[4]); *(uint32_t*)(outputaddr) = __REV(digest_para.out[4]);
break; break;
case HAU_ALGO_SHA224: case HAU_ALGO_SHA224:
/* read the message digest result */ /* read the message digest result */
hau_digest_read(&digest_para); hau_digest_read(&digest_para);
/* reverse byte order, copy result to outputaddr */ /* reverse byte order, copy result to outputaddr */
*(uint32_t*)(outputaddr) = __REV(digest_para.out[0]); *(uint32_t*)(outputaddr) = __REV(digest_para.out[0]);
@ -213,7 +214,7 @@ static void hau_sha_md5_digest_read(uint32_t algo, uint8_t output[])
*(uint32_t*)(outputaddr) = __REV(digest_para.out[6]); *(uint32_t*)(outputaddr) = __REV(digest_para.out[6]);
break; break;
case HAU_ALGO_SHA256: case HAU_ALGO_SHA256:
/* read the message digest result */ /* read the message digest result */
hau_digest_read(&digest_para); hau_digest_read(&digest_para);
/* reverse byte order, copy result to outputaddr */ /* reverse byte order, copy result to outputaddr */
*(uint32_t*)(outputaddr) = __REV(digest_para.out[0]); *(uint32_t*)(outputaddr) = __REV(digest_para.out[0]);
@ -233,7 +234,7 @@ static void hau_sha_md5_digest_read(uint32_t algo, uint8_t output[])
*(uint32_t*)(outputaddr) = __REV(digest_para.out[7]); *(uint32_t*)(outputaddr) = __REV(digest_para.out[7]);
break; break;
case HAU_ALGO_MD5: case HAU_ALGO_MD5:
/* read the message digest result */ /* read the message digest result */
hau_digest_read(&digest_para); hau_digest_read(&digest_para);
/* reverse byte order, copy result to outputaddr */ /* reverse byte order, copy result to outputaddr */
*(uint32_t*)(outputaddr) = __REV(digest_para.out[0]); *(uint32_t*)(outputaddr) = __REV(digest_para.out[0]);
@ -243,7 +244,7 @@ static void hau_sha_md5_digest_read(uint32_t algo, uint8_t output[])
*(uint32_t*)(outputaddr) = __REV(digest_para.out[2]); *(uint32_t*)(outputaddr) = __REV(digest_para.out[2]);
outputaddr += 4U; outputaddr += 4U;
*(uint32_t*)(outputaddr) = __REV(digest_para.out[3]); *(uint32_t*)(outputaddr) = __REV(digest_para.out[3]);
break; break;
default: default:
break; break;
} }
@ -283,7 +284,8 @@ static ErrStatus hau_hash_calculate(uint32_t algo, uint8_t input[], uint32_t in_
hau_last_word_validbits_num_config(num_last_valid); hau_last_word_validbits_num_config(num_last_valid);
/* write data to the IN FIFO */ /* write data to the IN FIFO */
for(i = 0U; i < in_length; i += 4U){ for(i = 0U; i < in_length; i += 4U)
{
hau_data_write(*(uint32_t*)inputaddr); hau_data_write(*(uint32_t*)inputaddr);
inputaddr += 4U; inputaddr += 4U;
} }
@ -297,7 +299,8 @@ static ErrStatus hau_hash_calculate(uint32_t algo, uint8_t input[], uint32_t in_
counter++; counter++;
}while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus)); }while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus){ if(RESET != busystatus)
{
return ERROR; return ERROR;
}else{ }else{
/* read the message digest */ /* read the message digest */
@ -340,7 +343,8 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t key[], uint32_t keysi
init_para.algo = algo; init_para.algo = algo;
init_para.mode = HAU_MODE_HMAC; init_para.mode = HAU_MODE_HMAC;
init_para.datatype = HAU_SWAPPING_8BIT; init_para.datatype = HAU_SWAPPING_8BIT;
if(keysize > 64U){ if(keysize > 64U)
{
init_para.keytype = HAU_KEY_LONGGER_64; init_para.keytype = HAU_KEY_LONGGER_64;
}else{ }else{
init_para.keytype = HAU_KEY_SHORTER_64; init_para.keytype = HAU_KEY_SHORTER_64;
@ -351,7 +355,8 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t key[], uint32_t keysi
hau_last_word_validbits_num_config((uint32_t)num_key_valid); hau_last_word_validbits_num_config((uint32_t)num_key_valid);
/* write the key */ /* write the key */
for(i = 0U; i < keysize; i += 4U){ for(i = 0U; i < keysize; i += 4U)
{
hau_data_write(*(uint32_t*)keyaddr); hau_data_write(*(uint32_t*)keyaddr);
keyaddr += 4U; keyaddr += 4U;
} }
@ -365,14 +370,16 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t key[], uint32_t keysi
counter++; counter++;
}while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus)); }while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus){ if(RESET != busystatus)
{
return ERROR; return ERROR;
}else{ }else{
/* configure the number of valid bits in last word of the message */ /* configure the number of valid bits in last word of the message */
hau_last_word_validbits_num_config((uint32_t)num_last_valid); hau_last_word_validbits_num_config((uint32_t)num_last_valid);
/* write data to the IN FIFO */ /* write data to the IN FIFO */
for(i = 0U; i < in_length; i += 4U){ for(i = 0U; i < in_length; i += 4U)
{
hau_data_write(*(uint32_t*)inputaddr); hau_data_write(*(uint32_t*)inputaddr);
inputaddr += 4U; inputaddr += 4U;
} }
@ -387,7 +394,8 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t key[], uint32_t keysi
counter++; counter++;
}while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus)); }while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus){ if(RESET != busystatus)
{
return ERROR; return ERROR;
}else{ }else{
/* configure the number of valid bits in last word of the key */ /* configure the number of valid bits in last word of the key */
@ -395,7 +403,8 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t key[], uint32_t keysi
/* write the key */ /* write the key */
keyaddr = (uint32_t)key; keyaddr = (uint32_t)key;
for(i = 0U; i < keysize; i += 4U){ for(i = 0U; i < keysize; i += 4U)
{
hau_data_write(*(uint32_t*)keyaddr); hau_data_write(*(uint32_t*)keyaddr);
keyaddr += 4U; keyaddr += 4U;
} }
@ -410,13 +419,14 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t key[], uint32_t keysi
counter++; counter++;
}while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus)); }while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus){ if(RESET != busystatus)
{
return ERROR; return ERROR;
}else{ }else{
/* read the message digest */ /* read the message digest */
hau_sha_md5_digest_read(algo, output); hau_sha_md5_digest_read(algo, output);
} }
} }
} }
return SUCCESS; return SUCCESS;
} }

171
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_hpdf.c
View File

@ -50,7 +50,8 @@ OF SUCH DAMAGE.
#define FLTYCT_CTCNT_OFFSET ((uint32_t)0x00000004U) /*!< bit offset of CTCNT in FLTYCT */ #define FLTYCT_CTCNT_OFFSET ((uint32_t)0x00000004U) /*!< bit offset of CTCNT in FLTYCT */
#define SIGN_BIT_OFFSET ((uint32_t)0x00800000U) /*!< bit offset of signed value */ #define SIGN_BIT_OFFSET ((uint32_t)0x00800000U) /*!< bit offset of signed value */
#define HPDF_WRONG_HANDLE while(1){} #define HPDF_WRONG_HANDLE while(1)
{}
/*! /*!
\brief reset HPDF \brief reset HPDF
@ -88,7 +89,8 @@ void hpdf_deinit(void)
void hpdf_channel_struct_para_init(hpdf_channel_parameter_struct *init_struct) void hpdf_channel_struct_para_init(hpdf_channel_parameter_struct *init_struct)
{ {
/* check whether the struct is empty */ /* check whether the struct is empty */
if(NULL == init_struct) { if(NULL == init_struct)
{
HPDF_WRONG_HANDLE HPDF_WRONG_HANDLE
} }
/* set the struct with the default values */ /* set the struct with the default values */
@ -127,7 +129,8 @@ void hpdf_channel_struct_para_init(hpdf_channel_parameter_struct *init_struct)
void hpdf_filter_struct_para_init(hpdf_filter_parameter_struct *init_struct) void hpdf_filter_struct_para_init(hpdf_filter_parameter_struct *init_struct)
{ {
/* check whether the struct is empty */ /* check whether the struct is empty */
if(NULL == init_struct) { if(NULL == init_struct)
{
HPDF_WRONG_HANDLE HPDF_WRONG_HANDLE
} }
/* set the struct with the default values */ /* set the struct with the default values */
@ -152,7 +155,8 @@ void hpdf_filter_struct_para_init(hpdf_filter_parameter_struct *init_struct)
void hpdf_rc_struct_para_init(hpdf_rc_parameter_struct *init_struct) void hpdf_rc_struct_para_init(hpdf_rc_parameter_struct *init_struct)
{ {
/* check whether the struct is empty */ /* check whether the struct is empty */
if(NULL == init_struct) { if(NULL == init_struct)
{
HPDF_WRONG_HANDLE HPDF_WRONG_HANDLE
} }
/* set the struct with the default values */ /* set the struct with the default values */
@ -172,7 +176,8 @@ void hpdf_rc_struct_para_init(hpdf_rc_parameter_struct *init_struct)
void hpdf_ic_struct_para_init(hpdf_ic_parameter_struct *init_struct) void hpdf_ic_struct_para_init(hpdf_ic_parameter_struct *init_struct)
{ {
/* check whether the struct is empty */ /* check whether the struct is empty */
if(NULL == init_struct) { if(NULL == init_struct)
{
HPDF_WRONG_HANDLE HPDF_WRONG_HANDLE
} }
/* set the struct with the default values */ /* set the struct with the default values */
@ -405,7 +410,8 @@ void hpdf_clock_output_source_config(uint32_t source)
void hpdf_clock_output_duty_mode_disable(void) void hpdf_clock_output_duty_mode_disable(void)
{ {
/* make sure the HPDF_CH0CTL_HPDFEN=0 */ /* make sure the HPDF_CH0CTL_HPDFEN=0 */
if(RESET == (HPDF_CHXCTL(CHANNEL0) & HPDF_CH0CTL_HPDFEN)) { if(RESET == (HPDF_CHXCTL(CHANNEL0) & HPDF_CH0CTL_HPDFEN))
{
HPDF_CHXCTL(CHANNEL0) &= ~CKOUTDM_ENABLE; HPDF_CHXCTL(CHANNEL0) &= ~CKOUTDM_ENABLE;
} }
} }
@ -419,7 +425,8 @@ void hpdf_clock_output_duty_mode_disable(void)
void hpdf_clock_output_duty_mode_enable(void) void hpdf_clock_output_duty_mode_enable(void)
{ {
/* make sure the HPDF_CH0CTL_HPDFEN=0 */ /* make sure the HPDF_CH0CTL_HPDFEN=0 */
if(RESET == (HPDF_CHXCTL(CHANNEL0) & HPDF_CH0CTL_HPDFEN)) { if(RESET == (HPDF_CHXCTL(CHANNEL0) & HPDF_CH0CTL_HPDFEN))
{
HPDF_CHXCTL(CHANNEL0) |= CKOUTDM_ENABLE; HPDF_CHXCTL(CHANNEL0) |= CKOUTDM_ENABLE;
} }
} }
@ -434,7 +441,8 @@ void hpdf_clock_output_divider_config(uint8_t divider)
{ {
uint32_t reg; uint32_t reg;
/* make sure the HPDF_CH0CTL_HPDFEN=0 */ /* make sure the HPDF_CH0CTL_HPDFEN=0 */
if(RESET == (HPDF_CHXCTL(CHANNEL0) & HPDF_CH0CTL_HPDFEN)) { if(RESET == (HPDF_CHXCTL(CHANNEL0) & HPDF_CH0CTL_HPDFEN))
{
reg = HPDF_CHXCTL(CHANNEL0); reg = HPDF_CHXCTL(CHANNEL0);
reg &= ~HPDF_CH0CTL_CKOUTDIV; reg &= ~HPDF_CH0CTL_CKOUTDIV;
reg |= ((uint32_t)divider << CH0CTL_CKOUTDIV_OFFSET); reg |= ((uint32_t)divider << CH0CTL_CKOUTDIV_OFFSET);
@ -481,7 +489,8 @@ void hpdf_spi_clock_source_config(hpdf_channel_enum channelx, uint32_t clock_sou
uint32_t reg; uint32_t reg;
reg = HPDF_CHXCTL(channelx); reg = HPDF_CHXCTL(channelx);
/* make sure the CHEN=0 */ /* make sure the CHEN=0 */
if(RESET == (reg & HPDF_CHXCTL_CHEN)) { if(RESET == (reg & HPDF_CHXCTL_CHEN))
{
reg &= ~HPDF_CHXCTL_SPICKSS; reg &= ~HPDF_CHXCTL_SPICKSS;
reg |= clock_source; reg |= clock_source;
HPDF_CHXCTL(channelx) = reg; HPDF_CHXCTL(channelx) = reg;
@ -505,7 +514,8 @@ void hpdf_serial_interface_type_config(hpdf_channel_enum channelx, uint32_t type
uint32_t reg; uint32_t reg;
reg = HPDF_CHXCTL(channelx); reg = HPDF_CHXCTL(channelx);
/* make sure the CHEN=0 */ /* make sure the CHEN=0 */
if(RESET == (reg & HPDF_CHXCTL_CHEN)) { if(RESET == (reg & HPDF_CHXCTL_CHEN))
{
reg &= ~HPDF_CHXCTL_SITYP; reg &= ~HPDF_CHXCTL_SITYP;
reg |= type; reg |= type;
HPDF_CHXCTL(channelx) = reg; HPDF_CHXCTL(channelx) = reg;
@ -565,7 +575,8 @@ void hpdf_clock_loss_enable(hpdf_channel_enum channelx)
void hpdf_channel_pin_redirection_disable(hpdf_channel_enum channelx) void hpdf_channel_pin_redirection_disable(hpdf_channel_enum channelx)
{ {
/* make sure the CHEN=0 */ /* make sure the CHEN=0 */
if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN)) { if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN))
{
HPDF_CHXCTL(channelx) &= ~HPDF_CHXCTL_CHPINSEL; HPDF_CHXCTL(channelx) &= ~HPDF_CHXCTL_CHPINSEL;
} }
} }
@ -579,7 +590,8 @@ void hpdf_channel_pin_redirection_disable(hpdf_channel_enum channelx)
void hpdf_channel_pin_redirection_enable(hpdf_channel_enum channelx) void hpdf_channel_pin_redirection_enable(hpdf_channel_enum channelx)
{ {
/* make sure the CHEN=0 */ /* make sure the CHEN=0 */
if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN)) { if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN))
{
HPDF_CHXCTL(channelx) |= HPDF_CHXCTL_CHPINSEL; HPDF_CHXCTL(channelx) |= HPDF_CHXCTL_CHPINSEL;
} }
} }
@ -600,7 +612,8 @@ void hpdf_channel_multiplexer_config(hpdf_channel_enum channelx, uint32_t data_s
uint32_t reg; uint32_t reg;
reg = HPDF_CHXCTL(channelx); reg = HPDF_CHXCTL(channelx);
/* make sure the CHEN=0 */ /* make sure the CHEN=0 */
if(RESET == (reg & HPDF_CHXCTL_CHEN)) { if(RESET == (reg & HPDF_CHXCTL_CHEN))
{
reg &= ~HPDF_CHXCTL_CMSD; reg &= ~HPDF_CHXCTL_CMSD;
/* configure the input data source */ /* configure the input data source */
reg |= data_source; reg |= data_source;
@ -624,7 +637,8 @@ void hpdf_data_pack_mode_config(hpdf_channel_enum channelx, uint32_t mode)
uint32_t reg; uint32_t reg;
reg = HPDF_CHXCTL(channelx); reg = HPDF_CHXCTL(channelx);
/* make sure the CHEN=0 */ /* make sure the CHEN=0 */
if(RESET == (reg & HPDF_CHXCTL_CHEN)) { if(RESET == (reg & HPDF_CHXCTL_CHEN))
{
reg &= ~HPDF_CHXCTL_DPM; reg &= ~HPDF_CHXCTL_DPM;
/* configure the data packing mode */ /* configure the data packing mode */
reg |= mode; reg |= mode;
@ -643,7 +657,8 @@ void hpdf_data_right_bit_shift_config(hpdf_channel_enum channelx, uint8_t right_
{ {
uint32_t reg; uint32_t reg;
/* make sure the CHEN=0 */ /* make sure the CHEN=0 */
if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN)) { if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN))
{
reg = HPDF_CHXCFG0(channelx); reg = HPDF_CHXCFG0(channelx);
reg &= ~HPDF_CHXCFG0_DTRS; reg &= ~HPDF_CHXCFG0_DTRS;
/* configure the right shift */ /* configure the right shift */
@ -719,9 +734,11 @@ void hpdf_malfunction_counter_config(hpdf_channel_enum channelx, uint8_t thresho
void hpdf_write_parallel_data_standard_mode(hpdf_channel_enum channelx, int16_t data) void hpdf_write_parallel_data_standard_mode(hpdf_channel_enum channelx, int16_t data)
{ {
/* make sure HPDF channel is used receive parallel data */ /* make sure HPDF channel is used receive parallel data */
if(INTERNAL_INPUT == (HPDF_CHXCTL(channelx) & INTERNAL_INPUT)) { if(INTERNAL_INPUT == (HPDF_CHXCTL(channelx) & INTERNAL_INPUT))
{
/* make sure the data pack of HPDF_CHXPDI register is standard mode */ /* make sure the data pack of HPDF_CHXPDI register is standard mode */
if(DPM_STANDARD_MODE == (HPDF_CHXCTL(channelx) & DPM_STANDARD_MODE)) { if(DPM_STANDARD_MODE == (HPDF_CHXCTL(channelx) & DPM_STANDARD_MODE))
{
HPDF_CHXPDI(channelx) = (uint16_t)data; HPDF_CHXPDI(channelx) = (uint16_t)data;
} }
} }
@ -737,9 +754,11 @@ void hpdf_write_parallel_data_standard_mode(hpdf_channel_enum channelx, int16_t
void hpdf_write_parallel_data_interleaved_mode(hpdf_channel_enum channelx, int32_t data) void hpdf_write_parallel_data_interleaved_mode(hpdf_channel_enum channelx, int32_t data)
{ {
/* make sure HPDF channel is used receive parallel data */ /* make sure HPDF channel is used receive parallel data */
if(INTERNAL_INPUT == (HPDF_CHXCTL(channelx) & INTERNAL_INPUT)) { if(INTERNAL_INPUT == (HPDF_CHXCTL(channelx) & INTERNAL_INPUT))
{
/* make sure the data pack of HPDF_CH0PDI register is interleaved mode */ /* make sure the data pack of HPDF_CH0PDI register is interleaved mode */
if(DPM_INTERLEAVED_MODE == (HPDF_CHXCTL(channelx) & DPM_INTERLEAVED_MODE)) { if(DPM_INTERLEAVED_MODE == (HPDF_CHXCTL(channelx) & DPM_INTERLEAVED_MODE))
{
HPDF_CHXPDI(channelx) = (uint32_t)data; HPDF_CHXPDI(channelx) = (uint32_t)data;
} }
} }
@ -755,9 +774,11 @@ void hpdf_write_parallel_data_interleaved_mode(hpdf_channel_enum channelx, int32
void hpdf_write_parallel_data_dual_mode(hpdf_channel_enum channelx, int32_t data) void hpdf_write_parallel_data_dual_mode(hpdf_channel_enum channelx, int32_t data)
{ {
/* make sure HPDF channel is used receive parallel data */ /* make sure HPDF channel is used receive parallel data */
if(INTERNAL_INPUT == (HPDF_CHXCTL(channelx) & INTERNAL_INPUT)) { if(INTERNAL_INPUT == (HPDF_CHXCTL(channelx) & INTERNAL_INPUT))
{
/* make sure the data pack of HPDF_CH0PDI register is dual mode */ /* make sure the data pack of HPDF_CH0PDI register is dual mode */
if(DPM_DUAL_MODE == (HPDF_CHXCTL(channelx) & DPM_DUAL_MODE)) { if(DPM_DUAL_MODE == (HPDF_CHXCTL(channelx) & DPM_DUAL_MODE))
{
HPDF_CHXPDI(channelx) = (uint32_t)data; HPDF_CHXPDI(channelx) = (uint32_t)data;
} }
} }
@ -831,7 +852,8 @@ void hpdf_filter_config(hpdf_filter_enum filtery, uint32_t order, uint16_t overs
{ {
uint32_t reg; uint32_t reg;
/* make sure the FLTEN=0 */ /* make sure the FLTEN=0 */
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
reg = HPDF_FLTYSFCFG(filtery); reg = HPDF_FLTYSFCFG(filtery);
reg &= ~(HPDF_FLTYSFCFG_SFO | HPDF_FLTYSFCFG_SFOR); reg &= ~(HPDF_FLTYSFCFG_SFO | HPDF_FLTYSFCFG_SFOR);
/* configure the sinc filter order and oversample */ /* configure the sinc filter order and oversample */
@ -851,7 +873,8 @@ void hpdf_integrator_oversample(hpdf_filter_enum filtery, uint16_t oversample)
{ {
uint32_t reg; uint32_t reg;
/* make sure the FLTEN=0 */ /* make sure the FLTEN=0 */
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
reg = HPDF_FLTYSFCFG(filtery); reg = HPDF_FLTYSFCFG(filtery);
reg &= ~HPDF_FLTYSFCFG_IOR; reg &= ~HPDF_FLTYSFCFG_IOR;
/* configure the integrator oversampling rate */ /* configure the integrator oversampling rate */
@ -877,7 +900,8 @@ void hpdf_threshold_monitor_filter_config(hpdf_channel_enum channelx, uint32_t o
{ {
uint32_t reg; uint32_t reg;
/* make sure the CHEN=0 */ /* make sure the CHEN=0 */
if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN)) { if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN))
{
reg = HPDF_CHXCFG1(channelx); reg = HPDF_CHXCFG1(channelx);
reg &= ~(HPDF_CHXCFG1_TMSFO | HPDF_CHXCFG1_TMFOR); reg &= ~(HPDF_CHXCFG1_TMSFO | HPDF_CHXCFG1_TMFOR);
/* configure the threshold monitor filter order and oversample rate */ /* configure the threshold monitor filter order and oversample rate */
@ -1047,7 +1071,8 @@ int32_t hpdf_extremes_monitor_maximum_get(hpdf_filter_enum filtery)
/* get the maximum value */ /* get the maximum value */
val = HPDF_FLTYEMMAX(filtery) >> FLTYEMMAX_MAXVAL_OFFSET; val = HPDF_FLTYEMMAX(filtery) >> FLTYEMMAX_MAXVAL_OFFSET;
/* get the sign of value */ /* get the sign of value */
if(val & SIGN_BIT_OFFSET) { if(val & SIGN_BIT_OFFSET)
{
val |= 0xFF000000U; val |= 0xFF000000U;
} }
return (int32_t)val; return (int32_t)val;
@ -1065,7 +1090,8 @@ int32_t hpdf_extremes_monitor_minimum_get(hpdf_filter_enum filtery)
/* get the channel of maximum value */ /* get the channel of maximum value */
val = HPDF_FLTYEMMIN(filtery) >> FLTYEMMIN_MINVAL_OFFSET; val = HPDF_FLTYEMMIN(filtery) >> FLTYEMMIN_MINVAL_OFFSET;
/* get the sign of vlaue */ /* get the sign of vlaue */
if(val & SIGN_BIT_OFFSET) { if(val & SIGN_BIT_OFFSET)
{
val |= 0xFF000000U; val |= 0xFF000000U;
} }
return (int32_t)val; return (int32_t)val;
@ -1126,7 +1152,8 @@ void hpdf_rc_start_by_software(hpdf_filter_enum filtery)
*/ */
void hpdf_rc_syn_disable(hpdf_filter_enum filtery) void hpdf_rc_syn_disable(hpdf_filter_enum filtery)
{ {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_RCSYN; HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_RCSYN;
} }
} }
@ -1139,7 +1166,8 @@ void hpdf_rc_syn_disable(hpdf_filter_enum filtery)
*/ */
void hpdf_rc_syn_enable(hpdf_filter_enum filtery) void hpdf_rc_syn_enable(hpdf_filter_enum filtery)
{ {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_RCSYN; HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_RCSYN;
} }
} }
@ -1152,7 +1180,8 @@ void hpdf_rc_syn_enable(hpdf_filter_enum filtery)
*/ */
void hpdf_rc_dma_disable(hpdf_filter_enum filtery) void hpdf_rc_dma_disable(hpdf_filter_enum filtery)
{ {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_RCDMAEN; HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_RCDMAEN;
} }
} }
@ -1165,7 +1194,8 @@ void hpdf_rc_dma_disable(hpdf_filter_enum filtery)
*/ */
void hpdf_rc_dma_enable(hpdf_filter_enum filtery) void hpdf_rc_dma_enable(hpdf_filter_enum filtery)
{ {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_RCDMAEN; HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_RCDMAEN;
} }
} }
@ -1196,7 +1226,8 @@ void hpdf_rc_channel_config(hpdf_filter_enum filtery, uint32_t channel)
*/ */
void hpdf_rc_fast_mode_disable(hpdf_filter_enum filtery) void hpdf_rc_fast_mode_disable(hpdf_filter_enum filtery)
{ {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_FAST; HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_FAST;
} }
} }
@ -1209,7 +1240,8 @@ void hpdf_rc_fast_mode_disable(hpdf_filter_enum filtery)
*/ */
void hpdf_rc_fast_mode_enable(hpdf_filter_enum filtery) void hpdf_rc_fast_mode_enable(hpdf_filter_enum filtery)
{ {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_FAST; HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_FAST;
} }
} }
@ -1226,7 +1258,8 @@ int32_t hpdf_rc_data_get(hpdf_filter_enum filtery)
/* get the signed data */ /* get the signed data */
val = HPDF_FLTYRDATA(filtery) >> FLTYRDATAT_RDATA_OFFSET; val = HPDF_FLTYRDATA(filtery) >> FLTYRDATAT_RDATA_OFFSET;
/* get the sign of vlaue */ /* get the sign of vlaue */
if(val & SIGN_BIT_OFFSET) { if(val & SIGN_BIT_OFFSET)
{
val |= 0xFF000000U; val |= 0xFF000000U;
} }
return (int32_t)val; return (int32_t)val;
@ -1265,7 +1298,8 @@ void hpdf_ic_start_by_software(hpdf_filter_enum filtery)
*/ */
void hpdf_ic_syn_disable(hpdf_filter_enum filtery) void hpdf_ic_syn_disable(hpdf_filter_enum filtery)
{ {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_ICSYN; HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_ICSYN;
} }
} }
@ -1278,7 +1312,8 @@ void hpdf_ic_syn_disable(hpdf_filter_enum filtery)
*/ */
void hpdf_ic_syn_enable(hpdf_filter_enum filtery) void hpdf_ic_syn_enable(hpdf_filter_enum filtery)
{ {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_ICSYN; HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_ICSYN;
} }
} }
@ -1291,7 +1326,8 @@ void hpdf_ic_syn_enable(hpdf_filter_enum filtery)
*/ */
void hpdf_ic_dma_disable(hpdf_filter_enum filtery) void hpdf_ic_dma_disable(hpdf_filter_enum filtery)
{ {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_ICDMAEN; HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_ICDMAEN;
} }
} }
@ -1304,7 +1340,8 @@ void hpdf_ic_dma_disable(hpdf_filter_enum filtery)
*/ */
void hpdf_ic_dma_enable(hpdf_filter_enum filtery) void hpdf_ic_dma_enable(hpdf_filter_enum filtery)
{ {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_ICDMAEN; HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_ICDMAEN;
} }
} }
@ -1317,7 +1354,8 @@ void hpdf_ic_dma_enable(hpdf_filter_enum filtery)
*/ */
void hpdf_ic_scan_mode_disable(hpdf_filter_enum filtery) void hpdf_ic_scan_mode_disable(hpdf_filter_enum filtery)
{ {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_SCMOD; HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_SCMOD;
} }
} }
@ -1330,7 +1368,8 @@ void hpdf_ic_scan_mode_disable(hpdf_filter_enum filtery)
*/ */
void hpdf_ic_scan_mode_enable(hpdf_filter_enum filtery) void hpdf_ic_scan_mode_enable(hpdf_filter_enum filtery)
{ {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_SCMOD; HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_SCMOD;
} }
} }
@ -1343,7 +1382,8 @@ void hpdf_ic_scan_mode_enable(hpdf_filter_enum filtery)
*/ */
void hpdf_ic_trigger_signal_disable(hpdf_filter_enum filtery) void hpdf_ic_trigger_signal_disable(hpdf_filter_enum filtery)
{ {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_ICTEEN; HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_ICTEEN;
} }
} }
@ -1380,7 +1420,8 @@ void hpdf_ic_trigger_signal_config(hpdf_filter_enum filtery, uint32_t trigger, u
{ {
uint32_t reg; uint32_t reg;
/* make sure the FLTEN=0 */ /* make sure the FLTEN=0 */
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) { if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
reg = HPDF_FLTYCTL0(filtery); reg = HPDF_FLTYCTL0(filtery);
reg &= ~(HPDF_FLTYCTL0_ICTEEN | HPDF_FLTYCTL0_ICTSSEL); reg &= ~(HPDF_FLTYCTL0_ICTEEN | HPDF_FLTYCTL0_ICTSSEL);
/* configure inserted conversions trigger siganl and trigger edge */ /* configure inserted conversions trigger siganl and trigger edge */
@ -1419,7 +1460,8 @@ int32_t hpdf_ic_data_get(hpdf_filter_enum filtery)
/* get the unsigned data */ /* get the unsigned data */
val = HPDF_FLTYIDATA(filtery) >> FLTYIDATAT_IDATA_OFFSET; val = HPDF_FLTYIDATA(filtery) >> FLTYIDATAT_IDATA_OFFSET;
/* get the sign of value */ /* get the sign of value */
if(val & SIGN_BIT_OFFSET) { if(val & SIGN_BIT_OFFSET)
{
val |= 0xFF000000U; val |= 0xFF000000U;
} }
/* get the signed data */ /* get the signed data */
@ -1463,10 +1505,12 @@ uint8_t hpdf_ic_channel_get(hpdf_filter_enum filtery)
FlagStatus hpdf_flag_get(hpdf_filter_enum filtery, hpdf_flag_enum flag) FlagStatus hpdf_flag_get(hpdf_filter_enum filtery, hpdf_flag_enum flag)
{ {
FlagStatus flag_state = RESET; FlagStatus flag_state = RESET;
switch(filtery) { switch(filtery)
{
case FLT0: case FLT0:
/* get the flag in FLT0 register */ /* get the flag in FLT0 register */
if(RESET != (HPDF_REG_VAL(HPDF_FLT0, flag) & BIT(HPDF_BIT_POS(flag)))) { if(RESET != (HPDF_REG_VAL(HPDF_FLT0, flag) & BIT(HPDF_BIT_POS(flag))))
{
flag_state = SET; flag_state = SET;
} else { } else {
flag_state = RESET; flag_state = RESET;
@ -1474,7 +1518,8 @@ FlagStatus hpdf_flag_get(hpdf_filter_enum filtery, hpdf_flag_enum flag)
break; break;
case FLT1: case FLT1:
/* get the flag in FLT1 register */ /* get the flag in FLT1 register */
if(RESET != (HPDF_REG_VAL(HPDF_FLT1, flag) & BIT(HPDF_BIT_POS(flag)))) { if(RESET != (HPDF_REG_VAL(HPDF_FLT1, flag) & BIT(HPDF_BIT_POS(flag))))
{
flag_state = SET; flag_state = SET;
} else { } else {
flag_state = RESET; flag_state = RESET;
@ -1482,7 +1527,8 @@ FlagStatus hpdf_flag_get(hpdf_filter_enum filtery, hpdf_flag_enum flag)
break; break;
case FLT2: case FLT2:
/* get the flag in FLT2 register */ /* get the flag in FLT2 register */
if(RESET != (HPDF_REG_VAL(HPDF_FLT2, flag) & BIT(HPDF_BIT_POS(flag)))) { if(RESET != (HPDF_REG_VAL(HPDF_FLT2, flag) & BIT(HPDF_BIT_POS(flag))))
{
flag_state = SET; flag_state = SET;
} else { } else {
flag_state = RESET; flag_state = RESET;
@ -1490,7 +1536,8 @@ FlagStatus hpdf_flag_get(hpdf_filter_enum filtery, hpdf_flag_enum flag)
break; break;
case FLT3: case FLT3:
/* get the flag in FLT3 register */ /* get the flag in FLT3 register */
if(RESET != (HPDF_REG_VAL(HPDF_FLT3, flag) & BIT(HPDF_BIT_POS(flag)))) { if(RESET != (HPDF_REG_VAL(HPDF_FLT3, flag) & BIT(HPDF_BIT_POS(flag))))
{
flag_state = SET; flag_state = SET;
} else { } else {
flag_state = RESET; flag_state = RESET;
@ -1521,11 +1568,13 @@ FlagStatus hpdf_flag_get(hpdf_filter_enum filtery, hpdf_flag_enum flag)
*/ */
void hpdf_flag_clear(hpdf_filter_enum filtery, hpdf_flag_enum flag) void hpdf_flag_clear(hpdf_filter_enum filtery, hpdf_flag_enum flag)
{ {
if(FLTYTMSTAT_REG_OFFSET == ((uint32_t)flag >> 6)) { if(FLTYTMSTAT_REG_OFFSET == ((uint32_t)flag >> 6))
{
/* clear threshold monitor high threshold flag */ /* clear threshold monitor high threshold flag */
HPDF_FLTYTMFC(filtery) |= BIT(HPDF_BIT_POS(flag)); HPDF_FLTYTMFC(filtery) |= BIT(HPDF_BIT_POS(flag));
} else { } else {
switch(flag) { switch(flag)
{
case HPDF_FLAG_FLTY_ICEF: case HPDF_FLAG_FLTY_ICEF:
/* read the inserted conversion data */ /* read the inserted conversion data */
HPDF_FLTYIDATA(filtery); HPDF_FLTYIDATA(filtery);
@ -1562,7 +1611,8 @@ void hpdf_flag_clear(hpdf_filter_enum filtery, hpdf_flag_enum flag)
*/ */
void hpdf_interrupt_enable(hpdf_filter_enum filtery, hpdf_interrput_enum interrupt) void hpdf_interrupt_enable(hpdf_filter_enum filtery, hpdf_interrput_enum interrupt)
{ {
switch(filtery) { switch(filtery)
{
case FLT0: case FLT0:
HPDF_REG_VAL(HPDF_FLT0, interrupt) |= BIT(HPDF_BIT_POS(interrupt)); HPDF_REG_VAL(HPDF_FLT0, interrupt) |= BIT(HPDF_BIT_POS(interrupt));
break; break;
@ -1597,7 +1647,8 @@ void hpdf_interrupt_enable(hpdf_filter_enum filtery, hpdf_interrput_enum interru
*/ */
void hpdf_interrupt_disable(hpdf_filter_enum filtery, hpdf_interrput_enum interrupt) void hpdf_interrupt_disable(hpdf_filter_enum filtery, hpdf_interrput_enum interrupt)
{ {
switch(filtery) { switch(filtery)
{
case FLT0: case FLT0:
HPDF_REG_VAL(HPDF_FLT0, interrupt) &= ~BIT(HPDF_BIT_POS(interrupt)); HPDF_REG_VAL(HPDF_FLT0, interrupt) &= ~BIT(HPDF_BIT_POS(interrupt));
break; break;
@ -1634,13 +1685,15 @@ FlagStatus hpdf_interrupt_flag_get(hpdf_filter_enum filtery, hpdf_interrput_flag
{ {
FlagStatus flag_state = RESET; FlagStatus flag_state = RESET;
uint32_t int_enable = 0U, flags = 0U; uint32_t int_enable = 0U, flags = 0U;
switch(filtery) { switch(filtery)
{
case FLT0: case FLT0:
/* get the interrupt enable bit status */ /* get the interrupt enable bit status */
int_enable = (HPDF_REG_VAL(HPDF_FLT0, int_flag) & BIT(HPDF_BIT_POS(int_flag))); int_enable = (HPDF_REG_VAL(HPDF_FLT0, int_flag) & BIT(HPDF_BIT_POS(int_flag)));
/* get the interrupt enable bit status */ /* get the interrupt enable bit status */
flags = (HPDF_REG_VAL2(HPDF_FLT0, int_flag) & BIT(HPDF_BIT_POS2(int_flag))); flags = (HPDF_REG_VAL2(HPDF_FLT0, int_flag) & BIT(HPDF_BIT_POS2(int_flag)));
if(flags && int_enable) { if(flags && int_enable)
{
flag_state = SET; flag_state = SET;
} else { } else {
flag_state = RESET; flag_state = RESET;
@ -1651,7 +1704,8 @@ FlagStatus hpdf_interrupt_flag_get(hpdf_filter_enum filtery, hpdf_interrput_flag
int_enable = (HPDF_REG_VAL(HPDF_FLT1, int_flag) & BIT(HPDF_BIT_POS(int_flag))); int_enable = (HPDF_REG_VAL(HPDF_FLT1, int_flag) & BIT(HPDF_BIT_POS(int_flag)));
/* get the interrupt enable bit status */ /* get the interrupt enable bit status */
flags = (HPDF_REG_VAL2(HPDF_FLT1, int_flag) & BIT(HPDF_BIT_POS2(int_flag))); flags = (HPDF_REG_VAL2(HPDF_FLT1, int_flag) & BIT(HPDF_BIT_POS2(int_flag)));
if(flags && int_enable) { if(flags && int_enable)
{
flag_state = SET; flag_state = SET;
} else { } else {
flag_state = RESET; flag_state = RESET;
@ -1662,7 +1716,8 @@ FlagStatus hpdf_interrupt_flag_get(hpdf_filter_enum filtery, hpdf_interrput_flag
int_enable = (HPDF_REG_VAL(HPDF_FLT2, int_flag) & BIT(HPDF_BIT_POS(int_flag))); int_enable = (HPDF_REG_VAL(HPDF_FLT2, int_flag) & BIT(HPDF_BIT_POS(int_flag)));
/* get the interrupt enable bit status */ /* get the interrupt enable bit status */
flags = (HPDF_REG_VAL2(HPDF_FLT2, int_flag) & BIT(HPDF_BIT_POS2(int_flag))); flags = (HPDF_REG_VAL2(HPDF_FLT2, int_flag) & BIT(HPDF_BIT_POS2(int_flag)));
if(flags && int_enable) { if(flags && int_enable)
{
flag_state = SET; flag_state = SET;
} else { } else {
flag_state = RESET; flag_state = RESET;
@ -1673,7 +1728,8 @@ FlagStatus hpdf_interrupt_flag_get(hpdf_filter_enum filtery, hpdf_interrput_flag
int_enable = (HPDF_REG_VAL(HPDF_FLT3, int_flag) & BIT(HPDF_BIT_POS(int_flag))); int_enable = (HPDF_REG_VAL(HPDF_FLT3, int_flag) & BIT(HPDF_BIT_POS(int_flag)));
/* get the interrupt enable bit status */ /* get the interrupt enable bit status */
flags = (HPDF_REG_VAL2(HPDF_FLT3, int_flag) & BIT(HPDF_BIT_POS2(int_flag))); flags = (HPDF_REG_VAL2(HPDF_FLT3, int_flag) & BIT(HPDF_BIT_POS2(int_flag)));
if(flags && int_enable) { if(flags && int_enable)
{
flag_state = SET; flag_state = SET;
} else { } else {
flag_state = RESET; flag_state = RESET;
@ -1702,7 +1758,8 @@ FlagStatus hpdf_interrupt_flag_get(hpdf_filter_enum filtery, hpdf_interrput_flag
*/ */
void hpdf_interrupt_flag_clear(hpdf_filter_enum filtery, hpdf_interrput_flag_enum int_flag) void hpdf_interrupt_flag_clear(hpdf_filter_enum filtery, hpdf_interrput_flag_enum int_flag)
{ {
switch(int_flag) { switch(int_flag)
{
case HPDF_INT_FLAG_FLTY_ICEF: case HPDF_INT_FLAG_FLTY_ICEF:
/* read the inserted conversion data */ /* read the inserted conversion data */
HPDF_FLTYIDATA(filtery); HPDF_FLTYIDATA(filtery);

21
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_hwsem.c
View File

@ -56,7 +56,8 @@ ErrStatus hwsem_lock_set(hwsem_semaphore_enum semaphore, uint8_t process)
/* read the control register to confirm the semaphore is locked by target process or not */ /* read the control register to confirm the semaphore is locked by target process or not */
temp_mid = hwsem_master_id_get(semaphore); temp_mid = hwsem_master_id_get(semaphore);
temp_pid = hwsem_process_id_get(semaphore); temp_pid = hwsem_process_id_get(semaphore);
if((HWSEM_MASTER_ID == temp_mid) && (process == temp_pid)) { if((HWSEM_MASTER_ID == temp_mid) && (process == temp_pid))
{
ret = SUCCESS; ret = SUCCESS;
} }
@ -82,7 +83,8 @@ ErrStatus hwsem_lock_release(hwsem_semaphore_enum semaphore, uint8_t process)
HWSEM_CTL(semaphore) = (uint32_t)(CTL_MID(HWSEM_MASTER_ID) | CTL_PID(process)); HWSEM_CTL(semaphore) = (uint32_t)(CTL_MID(HWSEM_MASTER_ID) | CTL_PID(process));
lock_state = HWSEM_CTL(semaphore) & HWSEM_CTL_LK; lock_state = HWSEM_CTL(semaphore) & HWSEM_CTL_LK;
if(0U == lock_state) { if(0U == lock_state)
{
ret = SUCCESS; ret = SUCCESS;
} }
@ -101,7 +103,8 @@ ErrStatus hwsem_lock_by_reading(hwsem_semaphore_enum semaphore)
{ {
ErrStatus ret = ERROR; ErrStatus ret = ERROR;
if((uint32_t)(HWSEM_LOCK | CTL_MID(HWSEM_MASTER_ID)) == HWSEM_RLK(semaphore)) { if((uint32_t)(HWSEM_LOCK | CTL_MID(HWSEM_MASTER_ID)) == HWSEM_RLK(semaphore))
{
ret = SUCCESS; ret = SUCCESS;
} }
@ -121,7 +124,8 @@ ErrStatus hwsem_unlock_all(uint16_t key)
HWSEM_UNLK = UNLK_KEY(key) | UNLK_MID(HWSEM_MASTER_ID); HWSEM_UNLK = UNLK_KEY(key) | UNLK_MID(HWSEM_MASTER_ID);
if(key == hwsem_key_get()) { if(key == hwsem_key_get())
{
ret = SUCCESS; ret = SUCCESS;
} }
return ret; return ret;
@ -165,7 +169,8 @@ FlagStatus hwsem_lock_status_get(hwsem_semaphore_enum semaphore)
{ {
FlagStatus ret = RESET; FlagStatus ret = RESET;
if(0U != (HWSEM_CTL(semaphore) & HWSEM_LOCK)) { if(0U != (HWSEM_CTL(semaphore) & HWSEM_LOCK))
{
ret = SET; ret = SET;
} }
@ -207,7 +212,8 @@ FlagStatus hwsem_flag_get(hwsem_semaphore_enum semaphore)
{ {
FlagStatus ret = RESET; FlagStatus ret = RESET;
if(RESET != ((HWSEM_STAT >> semaphore) & 0x1U)) { if(RESET != ((HWSEM_STAT >> semaphore) & 0x1U))
{
return SET; return SET;
} }
@ -239,7 +245,8 @@ FlagStatus hwsem_interrupt_flag_get(hwsem_semaphore_enum semaphore)
{ {
FlagStatus ret = RESET; FlagStatus ret = RESET;
if(RESET != ((HWSEM_INTF >> semaphore) & 0x1U)) { if(RESET != ((HWSEM_INTF >> semaphore) & 0x1U))
{
ret = SET; ret = SET;
} }

45
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_i2c.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
#include "gd32h7xx_i2c.h" #include "gd32h7xx_i2c.h"
@ -57,7 +57,8 @@ OF SUCH DAMAGE.
*/ */
void i2c_deinit(uint32_t i2c_periph) void i2c_deinit(uint32_t i2c_periph)
{ {
switch(i2c_periph) { switch(i2c_periph)
{
/* reset I2C0 */ /* reset I2C0 */
case I2C0: case I2C0:
rcu_periph_reset_enable(RCU_I2C0RST); rcu_periph_reset_enable(RCU_I2C0RST);
@ -592,7 +593,8 @@ void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint32_t byte_number)
*/ */
void i2c_dma_enable(uint32_t i2c_periph, uint8_t dma) void i2c_dma_enable(uint32_t i2c_periph, uint8_t dma)
{ {
if(I2C_DMA_TRANSMIT == dma) { if(I2C_DMA_TRANSMIT == dma)
{
I2C_CTL0(i2c_periph) |= I2C_CTL0_DENT; I2C_CTL0(i2c_periph) |= I2C_CTL0_DENT;
} else { } else {
I2C_CTL0(i2c_periph) |= I2C_CTL0_DENR; I2C_CTL0(i2c_periph) |= I2C_CTL0_DENR;
@ -611,7 +613,8 @@ void i2c_dma_enable(uint32_t i2c_periph, uint8_t dma)
*/ */
void i2c_dma_disable(uint32_t i2c_periph, uint8_t dma) void i2c_dma_disable(uint32_t i2c_periph, uint8_t dma)
{ {
if(I2C_DMA_TRANSMIT == dma) { if(I2C_DMA_TRANSMIT == dma)
{
I2C_CTL0(i2c_periph) &= ~I2C_CTL0_DENT; I2C_CTL0(i2c_periph) &= ~I2C_CTL0_DENT;
} else { } else {
I2C_CTL0(i2c_periph) &= ~I2C_CTL0_DENR; I2C_CTL0(i2c_periph) &= ~I2C_CTL0_DENR;
@ -839,7 +842,8 @@ void i2c_idle_clock_timeout_config(uint32_t i2c_periph, uint32_t timeout)
*/ */
FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag) FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag)
{ {
if(RESET != (I2C_STAT(i2c_periph) & flag)) { if(RESET != (I2C_STAT(i2c_periph) & flag))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -938,7 +942,8 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i
ret1 = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); ret1 = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag)));
/* get the status of interrupt flag */ /* get the status of interrupt flag */
ret2 = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); ret2 = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag)));
if(ret1 && ret2) { if(ret1 && ret2)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;

173
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_ipa.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -146,8 +146,8 @@ void ipa_background_lut_loading_enable(void)
\brief set pixel format convert mode, the function is invalid when the IPA transfer is enabled \brief set pixel format convert mode, the function is invalid when the IPA transfer is enabled
\param[in] pfcm: pixel format convert mode \param[in] pfcm: pixel format convert mode
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg IPA_FGTODE: foreground memory to destination memory without pixel format convert \arg IPA_FGTODE: foreground memory to destination memory without pixel format convert
\arg IPA_FGTODE_PF_CONVERT: foreground memory to destination memory with pixel format convert \arg IPA_FGTODE_PF_CONVERT: foreground memory to destination memory with pixel format convert
\arg IPA_FGBGTODE: blending foreground and background memory to destination memory \arg IPA_FGBGTODE: blending foreground and background memory to destination memory
\arg IPA_FILL_UP_DE: fill up destination memory with specific color \arg IPA_FILL_UP_DE: fill up destination memory with specific color
\param[out] none \param[out] none
@ -182,10 +182,10 @@ void ipa_foreground_interlace_mode_disable(void)
} }
/*! /*!
\brief initialize the structure of IPA foreground parameter struct with the default values, it is \brief initialize the structure of IPA foreground parameter struct with the default values, it is
suggested that call this function after an ipa_foreground_parameter_struct structure is defined suggested that call this function after an ipa_foreground_parameter_struct structure is defined
\param[in] none \param[in] none
\param[out] foreground_struct: the data needed to initialize foreground \param[out] foreground_struct: the data needed to initialize foreground
\retval none \retval none
*/ */
void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground_struct) void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground_struct)
@ -226,12 +226,13 @@ void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground
void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct) void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct)
{ {
FlagStatus tempflag = RESET; FlagStatus tempflag = RESET;
if(RESET != (IPA_CTL & IPA_CTL_TEN)){ if(RESET != (IPA_CTL & IPA_CTL_TEN))
{
tempflag = SET; tempflag = SET;
/* reset the TEN in order to configure the following bits */ /* reset the TEN in order to configure the following bits */
IPA_CTL &= ~IPA_CTL_TEN; IPA_CTL &= ~IPA_CTL_TEN;
} }
/* foreground memory base address configuration */ /* foreground memory base address configuration */
IPA_FMADDR &= ~(IPA_FMADDR_FMADDR); IPA_FMADDR &= ~(IPA_FMADDR_FMADDR);
IPA_FMADDR = foreground_struct->foreground_memaddr; IPA_FMADDR = foreground_struct->foreground_memaddr;
@ -243,7 +244,8 @@ void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct)
IPA_FPCTL |= (foreground_struct->foreground_prealpha << 24U); IPA_FPCTL |= (foreground_struct->foreground_prealpha << 24U);
IPA_FPCTL |= foreground_struct->foreground_alpha_algorithm; IPA_FPCTL |= foreground_struct->foreground_alpha_algorithm;
IPA_FPCTL |= foreground_struct->foreground_pf; IPA_FPCTL |= foreground_struct->foreground_pf;
if(ENABLE == foreground_struct->foreground_interlace_mode){ if(ENABLE == foreground_struct->foreground_interlace_mode)
{
IPA_FPCTL |= IPA_FPCTL_FIIMEN; IPA_FPCTL |= IPA_FPCTL_FIIMEN;
} }
/* foreground pre-defined red green blue configuration */ /* foreground pre-defined red green blue configuration */
@ -253,15 +255,16 @@ void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct)
/* foreground even frame / UV memory base address configuration */ /* foreground even frame / UV memory base address configuration */
IPA_EF_UV_MADDR &= ~(IPA_EF_UV_MADDR_EFUVMADDR); IPA_EF_UV_MADDR &= ~(IPA_EF_UV_MADDR_EFUVMADDR);
IPA_EF_UV_MADDR = foreground_struct->foreground_efuv_memaddr; IPA_EF_UV_MADDR = foreground_struct->foreground_efuv_memaddr;
if(SET == tempflag){ if(SET == tempflag)
{
/* restore the state of TEN */ /* restore the state of TEN */
IPA_CTL |= IPA_CTL_TEN; IPA_CTL |= IPA_CTL_TEN;
} }
} }
/*! /*!
\brief initialize the structure of IPA background parameter struct with the default values, it is \brief initialize the structure of IPA background parameter struct with the default values, it is
suggested that call this function after an ipa_background_parameter_struct structure is defined suggested that call this function after an ipa_background_parameter_struct structure is defined
\param[in] none \param[in] none
\param[out] background_struct: the data needed to initialize background \param[out] background_struct: the data needed to initialize background
@ -299,12 +302,13 @@ void ipa_background_struct_para_init(ipa_background_parameter_struct* background
void ipa_background_init(ipa_background_parameter_struct* background_struct) void ipa_background_init(ipa_background_parameter_struct* background_struct)
{ {
FlagStatus tempflag = RESET; FlagStatus tempflag = RESET;
if(RESET != (IPA_CTL & IPA_CTL_TEN)){ if(RESET != (IPA_CTL & IPA_CTL_TEN))
{
tempflag = SET; tempflag = SET;
/* reset the TEN in order to configure the following bits */ /* reset the TEN in order to configure the following bits */
IPA_CTL &= ~IPA_CTL_TEN; IPA_CTL &= ~IPA_CTL_TEN;
} }
/* background memory base address configuration */ /* background memory base address configuration */
IPA_BMADDR &= ~(IPA_BMADDR_BMADDR); IPA_BMADDR &= ~(IPA_BMADDR_BMADDR);
IPA_BMADDR = background_struct->background_memaddr; IPA_BMADDR = background_struct->background_memaddr;
@ -315,20 +319,21 @@ void ipa_background_init(ipa_background_parameter_struct* background_struct)
IPA_BPCTL &= ~(IPA_BPCTL_BPDAV | IPA_BPCTL_BAVCA | IPA_BPCTL_BPF); IPA_BPCTL &= ~(IPA_BPCTL_BPDAV | IPA_BPCTL_BAVCA | IPA_BPCTL_BPF);
IPA_BPCTL |= (background_struct->background_prealpha << 24U); IPA_BPCTL |= (background_struct->background_prealpha << 24U);
IPA_BPCTL |= background_struct->background_alpha_algorithm; IPA_BPCTL |= background_struct->background_alpha_algorithm;
IPA_BPCTL |= background_struct->background_pf; IPA_BPCTL |= background_struct->background_pf;
/* background pre-defined red green blue configuration */ /* background pre-defined red green blue configuration */
IPA_BPV &= ~(IPA_BPV_BPDRV|IPA_BPV_BPDGV | IPA_BPV_BPDBV); IPA_BPV &= ~(IPA_BPV_BPDRV|IPA_BPV_BPDGV | IPA_BPV_BPDBV);
IPA_BPV |= ((background_struct->background_prered << 16U) | (background_struct->background_pregreen << 8U) IPA_BPV |= ((background_struct->background_prered << 16U) | (background_struct->background_pregreen << 8U)
| (background_struct->background_preblue)); | (background_struct->background_preblue));
if(SET == tempflag){ if(SET == tempflag)
{
/* restore the state of TEN */ /* restore the state of TEN */
IPA_CTL |= IPA_CTL_TEN; IPA_CTL |= IPA_CTL_TEN;
} }
} }
/*! /*!
\brief initialize the structure of IPA destination parameter struct with the default values, it is \brief initialize the structure of IPA destination parameter struct with the default values, it is
suggested that call this function after an ipa_destination_parameter_struct structure is defined suggested that call this function after an ipa_destination_parameter_struct structure is defined
\param[in] none \param[in] none
\param[out] destination_struct: the data needed to initialize destination parameter \param[out] destination_struct: the data needed to initialize destination parameter
@ -343,7 +348,7 @@ void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destinat
destination_struct->destination_prered = IPA_DEFAULT_VALUE; destination_struct->destination_prered = IPA_DEFAULT_VALUE;
destination_struct->destination_pregreen = IPA_DEFAULT_VALUE; destination_struct->destination_pregreen = IPA_DEFAULT_VALUE;
destination_struct->destination_preblue = IPA_DEFAULT_VALUE; destination_struct->destination_preblue = IPA_DEFAULT_VALUE;
destination_struct->destination_memaddr = IPA_DEFAULT_VALUE; destination_struct->destination_memaddr = IPA_DEFAULT_VALUE;
destination_struct->image_width = IPA_DEFAULT_VALUE; destination_struct->image_width = IPA_DEFAULT_VALUE;
destination_struct->image_height = IPA_DEFAULT_VALUE; destination_struct->image_height = IPA_DEFAULT_VALUE;
destination_struct->image_rotate = DESTINATION_ROTATE_0; destination_struct->image_rotate = DESTINATION_ROTATE_0;
@ -365,14 +370,14 @@ void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destinat
destination_prered: destination pre-defined red value destination_prered: destination pre-defined red value
destination_pregreen: destination pre-defined green value destination_pregreen: destination pre-defined green value
destination_preblue: destination pre-defined blue value destination_preblue: destination pre-defined blue value
destination_memaddr: destination memory base address destination_memaddr: destination memory base address
image_width: width of the image to be processed image_width: width of the image to be processed
image_height: height of the image to be processed image_height: height of the image to be processed
image_rotate: DESTINATION_ROTATE_0, DESTINATION_ROTATE_90, image_rotate: DESTINATION_ROTATE_0, DESTINATION_ROTATE_90,
DESTINATION_ROTATE_180, DESTINATION_ROTATE_270 DESTINATION_ROTATE_180, DESTINATION_ROTATE_270
image_hor_decimation: DESTINATION_HORDECIMATE_DISABLE, DESTINATION_HORDECIMATE_2, image_hor_decimation: DESTINATION_HORDECIMATE_DISABLE, DESTINATION_HORDECIMATE_2,
DESTINATION_HORDECIMATE_4, DESTINATION_HORDECIMATE_8 DESTINATION_HORDECIMATE_4, DESTINATION_HORDECIMATE_8
image_ver_decimation: DESTINATION_VERDECIMATE_DISABLE, DESTINATION_VERDECIMATE_2, image_ver_decimation: DESTINATION_VERDECIMATE_DISABLE, DESTINATION_VERDECIMATE_2,
DESTINATION_VERDECIMATE_4, DESTINATION_VERDECIMATE_8 DESTINATION_VERDECIMATE_4, DESTINATION_VERDECIMATE_8
image_bilinear_xscale: x scaling factor image_bilinear_xscale: x scaling factor
image_bilinear_yscale: y scaling factor image_bilinear_yscale: y scaling factor
@ -385,12 +390,13 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct)
{ {
uint32_t destination_pixelformat; uint32_t destination_pixelformat;
FlagStatus tempflag = RESET; FlagStatus tempflag = RESET;
if(RESET != (IPA_CTL & IPA_CTL_TEN)){ if(RESET != (IPA_CTL & IPA_CTL_TEN))
{
tempflag = SET; tempflag = SET;
/* reset the TEN in order to configure the following bits */ /* reset the TEN in order to configure the following bits */
IPA_CTL &= ~IPA_CTL_TEN; IPA_CTL &= ~IPA_CTL_TEN;
} }
/* destination pixel format, interlace sampling method and rotation configuration */ /* destination pixel format, interlace sampling method and rotation configuration */
IPA_DPCTL &= ~(IPA_DPCTL_DPF | IPA_DPCTL_ROT | IPA_DPCTL_HORDEC | IPA_DPCTL_VERDEC); IPA_DPCTL &= ~(IPA_DPCTL_DPF | IPA_DPCTL_ROT | IPA_DPCTL_HORDEC | IPA_DPCTL_VERDEC);
IPA_DPCTL = (destination_struct->destination_pf | IPA_DPCTL = (destination_struct->destination_pf |
@ -399,7 +405,8 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct)
destination_struct->image_ver_decimation); destination_struct->image_ver_decimation);
destination_pixelformat = destination_struct->destination_pf; destination_pixelformat = destination_struct->destination_pf;
/* destination pixel format ARGB8888 */ /* destination pixel format ARGB8888 */
switch(destination_pixelformat){ switch(destination_pixelformat)
{
case IPA_DPF_ARGB8888: case IPA_DPF_ARGB8888:
IPA_DPV &= ~(IPA_DPV_DPDBV_0 | (IPA_DPV_DPDGV_0) | (IPA_DPV_DPDRV_0) | (IPA_DPV_DPDAV_0)); IPA_DPV &= ~(IPA_DPV_DPDBV_0 | (IPA_DPV_DPDGV_0) | (IPA_DPV_DPDRV_0) | (IPA_DPV_DPDAV_0));
IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 8U) IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 8U)
@ -446,14 +453,15 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct)
IPA_IMS |= ((destination_struct->image_width << 16U) | (destination_struct->image_height)); IPA_IMS |= ((destination_struct->image_width << 16U) | (destination_struct->image_height));
/* xscale and yscale configuration */ /* xscale and yscale configuration */
IPA_BSCTL &= ~(IPA_BSCTL_XSCALE | IPA_BSCTL_YSCALE); IPA_BSCTL &= ~(IPA_BSCTL_XSCALE | IPA_BSCTL_YSCALE);
IPA_BSCTL = ((destination_struct->image_bilinear_xscale & IPA_BSCTL_XSCALE) | IPA_BSCTL = ((destination_struct->image_bilinear_xscale & IPA_BSCTL_XSCALE) |
((uint32_t)(destination_struct->image_bilinear_yscale << 16U) & IPA_BSCTL_YSCALE)); ((uint32_t)(destination_struct->image_bilinear_yscale << 16U) & IPA_BSCTL_YSCALE));
/* image size after scaling configuration */ /* image size after scaling configuration */
IPA_DIMS &= ~(IPA_DIMS_DWIDTH | IPA_DIMS_DHEIGHT); IPA_DIMS &= ~(IPA_DIMS_DWIDTH | IPA_DIMS_DHEIGHT);
IPA_DIMS = (destination_struct->image_scaling_height & IPA_DIMS_DHEIGHT) | IPA_DIMS = (destination_struct->image_scaling_height & IPA_DIMS_DHEIGHT) |
((uint32_t)((destination_struct->image_scaling_width << 16U) & IPA_DIMS_DWIDTH)); ((uint32_t)((destination_struct->image_scaling_width << 16U) & IPA_DIMS_DWIDTH));
if(SET == tempflag){ if(SET == tempflag)
{
/* restore the state of TEN */ /* restore the state of TEN */
IPA_CTL |= IPA_CTL_TEN; IPA_CTL |= IPA_CTL_TEN;
} }
@ -470,26 +478,30 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct)
void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr) void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr)
{ {
FlagStatus tempflag = RESET; FlagStatus tempflag = RESET;
if(RESET != (IPA_FPCTL & IPA_FPCTL_FLLEN)){ if(RESET != (IPA_FPCTL & IPA_FPCTL_FLLEN))
{
tempflag = SET; tempflag = SET;
/* reset the FLLEN in order to configure the following bits */ /* reset the FLLEN in order to configure the following bits */
IPA_FPCTL &= ~IPA_FPCTL_FLLEN; IPA_FPCTL &= ~IPA_FPCTL_FLLEN;
} }
/* foreground LUT number of pixel configuration */ /* foreground LUT number of pixel configuration */
IPA_FPCTL |= ((uint32_t)fg_lut_num << 8U); IPA_FPCTL |= ((uint32_t)fg_lut_num << 8U);
/* foreground LUT pixel format configuration */ /* foreground LUT pixel format configuration */
if(IPA_LUT_PF_RGB888 == fg_lut_pf){ if(IPA_LUT_PF_RGB888 == fg_lut_pf)
{
IPA_FPCTL |= IPA_FPCTL_FLPF; IPA_FPCTL |= IPA_FPCTL_FLPF;
}else if(IPA_LUT_PF_ARGB8888 == fg_lut_pf){ }else if(IPA_LUT_PF_ARGB8888 == fg_lut_pf)
{
IPA_FPCTL &= ~(IPA_FPCTL_FLPF); IPA_FPCTL &= ~(IPA_FPCTL_FLPF);
}else{ }else{
} }
/* foreground LUT memory base address configuration */ /* foreground LUT memory base address configuration */
IPA_FLMADDR &= ~(IPA_FLMADDR_FLMADDR); IPA_FLMADDR &= ~(IPA_FLMADDR_FLMADDR);
IPA_FLMADDR = fg_lut_addr; IPA_FLMADDR = fg_lut_addr;
if(SET == tempflag){ if(SET == tempflag)
{
/* restore the state of FLLEN */ /* restore the state of FLLEN */
IPA_FPCTL |= IPA_FPCTL_FLLEN; IPA_FPCTL |= IPA_FPCTL_FLLEN;
} }
@ -506,26 +518,30 @@ void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_
void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr) void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr)
{ {
FlagStatus tempflag = RESET; FlagStatus tempflag = RESET;
if(RESET != (IPA_BPCTL & IPA_BPCTL_BLLEN)){ if(RESET != (IPA_BPCTL & IPA_BPCTL_BLLEN))
{
tempflag = SET; tempflag = SET;
/* reset the BLLEN in order to configure the following bits */ /* reset the BLLEN in order to configure the following bits */
IPA_BPCTL &= ~IPA_BPCTL_BLLEN; IPA_BPCTL &= ~IPA_BPCTL_BLLEN;
} }
/* background LUT number of pixel configuration */ /* background LUT number of pixel configuration */
IPA_BPCTL |= ((uint32_t)bg_lut_num << 8U); IPA_BPCTL |= ((uint32_t)bg_lut_num << 8U);
/* background LUT pixel format configuration */ /* background LUT pixel format configuration */
if(IPA_LUT_PF_RGB888 == bg_lut_pf){ if(IPA_LUT_PF_RGB888 == bg_lut_pf)
{
IPA_BPCTL |= IPA_BPCTL_BLPF; IPA_BPCTL |= IPA_BPCTL_BLPF;
}else if(IPA_LUT_PF_ARGB8888 == bg_lut_pf){ }else if(IPA_LUT_PF_ARGB8888 == bg_lut_pf)
{
IPA_BPCTL &= ~(IPA_BPCTL_BLPF); IPA_BPCTL &= ~(IPA_BPCTL_BLPF);
}else{ }else{
} }
/* background LUT memory base address configuration */ /* background LUT memory base address configuration */
IPA_BLMADDR &= ~(IPA_BLMADDR_BLMADDR); IPA_BLMADDR &= ~(IPA_BLMADDR_BLMADDR);
IPA_BLMADDR = bg_lut_addr; IPA_BLMADDR = bg_lut_addr;
if(SET == tempflag){ if(SET == tempflag)
{
/* restore the state of BLLEN */ /* restore the state of BLLEN */
IPA_BPCTL |= IPA_BPCTL_BLLEN; IPA_BPCTL |= IPA_BPCTL_BLLEN;
} }
@ -551,10 +567,12 @@ void ipa_line_mark_config(uint16_t line_num)
*/ */
void ipa_inter_timer_config(uint8_t timer_cfg) void ipa_inter_timer_config(uint8_t timer_cfg)
{ {
if(IPA_INTER_TIMER_ENABLE == timer_cfg){ if(IPA_INTER_TIMER_ENABLE == timer_cfg)
{
/* inter-timer enable */ /* inter-timer enable */
IPA_ITCTL |= IPA_ITCTL_ITEN; IPA_ITCTL |= IPA_ITCTL_ITEN;
}else if(IPA_INTER_TIMER_DISABLE == timer_cfg){ }else if(IPA_INTER_TIMER_DISABLE == timer_cfg)
{
/* inter-timer disable */ /* inter-timer disable */
IPA_ITCTL &= ~(IPA_ITCTL_ITEN); IPA_ITCTL &= ~(IPA_ITCTL_ITEN);
}else{ }else{
@ -584,8 +602,9 @@ void ipa_interval_clock_num_config(uint8_t clk_num)
\retval none \retval none
*/ */
void ipa_color_conversion_struct_para_init(ipa_conversion_parameter_struct* conversion_struct, ipa_colorspace_enum colorspace) void ipa_color_conversion_struct_para_init(ipa_conversion_parameter_struct* conversion_struct, ipa_colorspace_enum colorspace)
{ {
if(IPA_COLORSPACE_YUV == colorspace){ if(IPA_COLORSPACE_YUV == colorspace)
{
/* initialize the struct parameters with default YUV conversion values */ /* initialize the struct parameters with default YUV conversion values */
conversion_struct->color_space = IPA_COLORSPACE_YUV; conversion_struct->color_space = IPA_COLORSPACE_YUV;
conversion_struct->y_offset = IPA_DEFAULT_YUV_CONV_YOFFSET; conversion_struct->y_offset = IPA_DEFAULT_YUV_CONV_YOFFSET;
@ -595,7 +614,8 @@ void ipa_color_conversion_struct_para_init(ipa_conversion_parameter_struct* conv
conversion_struct->coef_c2 = IPA_DEFAULT_YUV_CONV_C2OFFSET; conversion_struct->coef_c2 = IPA_DEFAULT_YUV_CONV_C2OFFSET;
conversion_struct->coef_c3 = IPA_DEFAULT_YUV_CONV_C3OFFSET; conversion_struct->coef_c3 = IPA_DEFAULT_YUV_CONV_C3OFFSET;
conversion_struct->coef_c4 = IPA_DEFAULT_YUV_CONV_C4OFFSET; conversion_struct->coef_c4 = IPA_DEFAULT_YUV_CONV_C4OFFSET;
}else if(IPA_COLORSPACE_YCBCR == colorspace){ }else if(IPA_COLORSPACE_YCBCR == colorspace)
{
/* initialize the struct parameters with default YCbCr conversion values */ /* initialize the struct parameters with default YCbCr conversion values */
conversion_struct->color_space = IPA_COLORSPACE_YCBCR; conversion_struct->color_space = IPA_COLORSPACE_YCBCR;
conversion_struct->y_offset = IPA_DEFAULT_YCBCR_CONV_YOFFSET; conversion_struct->y_offset = IPA_DEFAULT_YCBCR_CONV_YOFFSET;
@ -619,7 +639,7 @@ void ipa_color_conversion_struct_para_init(ipa_conversion_parameter_struct* conv
coef_c0: Y multiplier coefficient coef_c0: Y multiplier coefficient
coef_c1: V/Cr red multiplier coefficient coef_c1: V/Cr red multiplier coefficient
coef_c2: V/Cr green multiplier coefficient coef_c2: V/Cr green multiplier coefficient
coef_c3: U/Cb green multiplier coefficient coef_c3: U/Cb green multiplier coefficient
coef_c4: U/Cb blue multiplier coefficient coef_c4: U/Cb blue multiplier coefficient
\param[out] none \param[out] none
\retval none \retval none
@ -627,16 +647,17 @@ void ipa_color_conversion_struct_para_init(ipa_conversion_parameter_struct* conv
void ipa_color_conversion_config(ipa_conversion_parameter_struct* conversion_struct) void ipa_color_conversion_config(ipa_conversion_parameter_struct* conversion_struct)
{ {
FlagStatus tempflag = RESET; FlagStatus tempflag = RESET;
if(RESET != (IPA_CTL & IPA_CTL_TEN)){ if(RESET != (IPA_CTL & IPA_CTL_TEN))
{
tempflag = SET; tempflag = SET;
/* reset the TEN in order to configure the following bits */ /* reset the TEN in order to configure the following bits */
IPA_CTL &= ~IPA_CTL_TEN; IPA_CTL &= ~IPA_CTL_TEN;
} }
/* Y offset, UV offset, compliment Y multiplier configuration */ /* Y offset, UV offset, compliment Y multiplier configuration */
IPA_CSCC_CFG0 &= ~(IPA_CSCC_CFG0_YOFF | IPA_CSCC_CFG0_UVOFF | IPA_CSCC_CFG0_C0); IPA_CSCC_CFG0 &= ~(IPA_CSCC_CFG0_YOFF | IPA_CSCC_CFG0_UVOFF | IPA_CSCC_CFG0_C0);
IPA_CSCC_CFG0 |= (((conversion_struct->y_offset) & IPA_CSCC_CFG0_YOFF) | IPA_CSCC_CFG0 |= (((conversion_struct->y_offset) & IPA_CSCC_CFG0_YOFF) |
((uint32_t)(conversion_struct->uv_offset << 9U) & IPA_CSCC_CFG0_UVOFF) | ((uint32_t)(conversion_struct->uv_offset << 9U) & IPA_CSCC_CFG0_UVOFF) |
((uint32_t)(conversion_struct->coef_c0 << 18U) & IPA_CSCC_CFG0_C0)); ((uint32_t)(conversion_struct->coef_c0 << 18U) & IPA_CSCC_CFG0_C0));
/* red V/Cr multiplier, blue U/Cb multiplier configuration */ /* red V/Cr multiplier, blue U/Cb multiplier configuration */
IPA_CSCC_CFG1 &= ~(IPA_CSCC_CFG1_C1 | IPA_CSCC_CFG1_C4); IPA_CSCC_CFG1 &= ~(IPA_CSCC_CFG1_C1 | IPA_CSCC_CFG1_C4);
@ -646,16 +667,18 @@ void ipa_color_conversion_config(ipa_conversion_parameter_struct* conversion_str
IPA_CSCC_CFG2 &= ~(IPA_CSCC_CFG2_C2 | IPA_CSCC_CFG2_C3); IPA_CSCC_CFG2 &= ~(IPA_CSCC_CFG2_C2 | IPA_CSCC_CFG2_C3);
IPA_CSCC_CFG2 |= ((conversion_struct->coef_c3 & IPA_CSCC_CFG2_C3) | IPA_CSCC_CFG2 |= ((conversion_struct->coef_c3 & IPA_CSCC_CFG2_C3) |
((uint32_t)(conversion_struct->coef_c2 << 16U) & IPA_CSCC_CFG2_C2)); ((uint32_t)(conversion_struct->coef_c2 << 16U) & IPA_CSCC_CFG2_C2));
if(IPA_COLORSPACE_YUV == conversion_struct->color_space){ if(IPA_COLORSPACE_YUV == conversion_struct->color_space)
{
/* convert YUV to RGB */ /* convert YUV to RGB */
IPA_CSCC_CFG0 &= ~(IPA_CSCC_CFG0_CONVMOD); IPA_CSCC_CFG0 &= ~(IPA_CSCC_CFG0_CONVMOD);
}else{ }else{
/* convert YCbCr to RGB */ /* convert YCbCr to RGB */
IPA_CSCC_CFG0 |= IPA_CSCC_CFG0_CONVMOD; IPA_CSCC_CFG0 |= IPA_CSCC_CFG0_CONVMOD;
} }
if(SET == tempflag){ if(SET == tempflag)
{
/* restore the state of TEN */ /* restore the state of TEN */
IPA_CTL |= IPA_CTL_TEN; IPA_CTL |= IPA_CTL_TEN;
} }
@ -685,10 +708,10 @@ void ipa_foreground_scaling_config(uint32_t horizontal_decimation, uint32_t vert
/* configure decimation filter */ /* configure decimation filter */
IPA_DPCTL &= ~(uint32_t)(IPA_DPCTL_VERDEC | IPA_DPCTL_HORDEC); IPA_DPCTL &= ~(uint32_t)(IPA_DPCTL_VERDEC | IPA_DPCTL_HORDEC);
IPA_DPCTL |= (horizontal_decimation | vertical_decimation); IPA_DPCTL |= (horizontal_decimation | vertical_decimation);
/* XScaling and YScaling configuration */ /* XScaling and YScaling configuration */
IPA_BSCTL &= ~(IPA_BSCTL_XSCALE | IPA_BSCTL_YSCALE); IPA_BSCTL &= ~(IPA_BSCTL_XSCALE | IPA_BSCTL_YSCALE);
IPA_BSCTL = ((image_scaling_width & IPA_BSCTL_XSCALE) | IPA_BSCTL = ((image_scaling_width & IPA_BSCTL_XSCALE) |
((uint32_t)(image_scaling_height << 16U) & IPA_BSCTL_YSCALE)); ((uint32_t)(image_scaling_height << 16U) & IPA_BSCTL_YSCALE));
} }
@ -702,7 +725,7 @@ void ipa_foreground_scaling_config(uint32_t horizontal_decimation, uint32_t vert
void ipa_destination_scaling_config(uint32_t dest_scaling_width, uint32_t dest_scaling_height) void ipa_destination_scaling_config(uint32_t dest_scaling_width, uint32_t dest_scaling_height)
{ {
IPA_DIMS &= ~(IPA_DIMS_DWIDTH | IPA_DIMS_DHEIGHT); IPA_DIMS &= ~(IPA_DIMS_DWIDTH | IPA_DIMS_DHEIGHT);
IPA_DIMS = (dest_scaling_height & IPA_DIMS_DHEIGHT) | IPA_DIMS = (dest_scaling_height & IPA_DIMS_DHEIGHT) |
((uint32_t)((dest_scaling_width << 16U) & IPA_DIMS_DWIDTH)); ((uint32_t)((dest_scaling_width << 16U) & IPA_DIMS_DWIDTH));
} }
@ -721,7 +744,8 @@ void ipa_destination_scaling_config(uint32_t dest_scaling_width, uint32_t dest_s
*/ */
FlagStatus ipa_flag_get(uint32_t flag) FlagStatus ipa_flag_get(uint32_t flag)
{ {
if(RESET != (IPA_INTF & flag)){ if(RESET != (IPA_INTF & flag))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -797,7 +821,8 @@ void ipa_interrupt_disable(uint32_t int_flag)
*/ */
FlagStatus ipa_interrupt_flag_get(uint32_t int_flag) FlagStatus ipa_interrupt_flag_get(uint32_t int_flag)
{ {
if(RESET != (IPA_INTF & int_flag)){ if(RESET != (IPA_INTF & int_flag))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;

15
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_lpdts.c
View File

@ -205,7 +205,8 @@ int32_t lpdts_temperature_get(void)
reg_cfg = LPDTS_CFG; reg_cfg = LPDTS_CFG;
/* get the module frequency on Hz */ /* get the module frequency on Hz */
if((reg_cfg & LPDTS_CFG_REFSEL) == LPDTS_CFG_REFSEL) { if((reg_cfg & LPDTS_CFG_REFSEL) == LPDTS_CFG_REFSEL)
{
freq = (LXTAL_VALUE * count) / (2U * ((reg_cfg & LPDTS_CFG_SPT) >> LPDTS_CFG_SPT_OFFSET)); freq = (LXTAL_VALUE * count) / (2U * ((reg_cfg & LPDTS_CFG_SPT) >> LPDTS_CFG_SPT_OFFSET));
} else { } else {
freq = (2U * rcu_clock_freq_get(CK_APB1) / count) * ((reg_cfg & LPDTS_CFG_SPT) >> LPDTS_CFG_SPT_OFFSET); freq = (2U * rcu_clock_freq_get(CK_APB1) / count) * ((reg_cfg & LPDTS_CFG_SPT) >> LPDTS_CFG_SPT_OFFSET);
@ -213,7 +214,8 @@ int32_t lpdts_temperature_get(void)
/* read factory settings */ /* read factory settings */
t0 = (LPDTS_SDATA & LPDTS_SDATA_VAL) >> LPDTS_SDATA_VAL_OFFSET; t0 = (LPDTS_SDATA & LPDTS_SDATA_VAL) >> LPDTS_SDATA_VAL_OFFSET;
if(t0 == 0U) { if(t0 == 0U)
{
t0 = LPDTS_T0_TMP_VAL; t0 = LPDTS_T0_TMP_VAL;
} }
@ -240,7 +242,8 @@ FlagStatus lpdts_flag_get(uint32_t flag)
{ {
FlagStatus status = RESET; FlagStatus status = RESET;
if(LPDTS_STAT & flag) { if(LPDTS_STAT & flag)
{
status = SET; status = SET;
} }
/* return the state of corresponding LPDTS flag */ /* return the state of corresponding LPDTS flag */
@ -302,9 +305,11 @@ FlagStatus lpdts_interrupt_flag_get(uint32_t flag)
uint32_t state; uint32_t state;
state = LPDTS_STAT; state = LPDTS_STAT;
if(state & flag) { if(state & flag)
{
state = LPDTS_INTEN; state = LPDTS_INTEN;
if(state & flag) { if(state & flag)
{
status = SET; status = SET;
} }
} }

92
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_mdio.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -59,7 +59,7 @@ void mdio_software_reset(void)
} }
/*! /*!
\brief initialize MDIO for communication \brief initialize MDIO for communication
\param[in] phy_size: PHY bit length \param[in] phy_size: PHY bit length
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg MDIO_PHY_BITS_3: PHY use 3 bits \arg MDIO_PHY_BITS_3: PHY use 3 bits
@ -84,19 +84,19 @@ void mdio_software_reset(void)
uint32_t mdio_init(uint32_t phy_size, uint32_t phy_softaddr, uint32_t phy_sel, uint16_t devadd) uint32_t mdio_init(uint32_t phy_size, uint32_t phy_softaddr, uint32_t phy_sel, uint16_t devadd)
{ {
uint32_t phy_addr = 0U, phy_hard = 0U; uint32_t phy_addr = 0U, phy_hard = 0U;
/* configure MDIO phy bit length */ /* configure MDIO phy bit length */
MDIO_CTL &= ~MDIO_CTL_PHYB; MDIO_CTL &= ~MDIO_CTL_PHYB;
MDIO_CTL |= phy_size; MDIO_CTL |= phy_size;
/* configure the PHYADR and DEVADD */ /* configure the PHYADR and DEVADD */
MDIO_CFG &= ~(MDIO_CFG_PHYSW | MDIO_CFG_EPHYSEL | MDIO_CFG_EDEVADD); MDIO_CFG &= ~(MDIO_CFG_PHYSW | MDIO_CFG_EPHYSEL | MDIO_CFG_EDEVADD);
MDIO_CFG |= CFG_PHYSW(phy_softaddr) | CFG_EPHYSEL(phy_sel) | CFG_EDEVADD(devadd); MDIO_CFG |= CFG_PHYSW(phy_softaddr) | CFG_EPHYSEL(phy_sel) | CFG_EDEVADD(devadd);
/* calculate the PHYADR that the device will respond to */ /* calculate the PHYADR that the device will respond to */
phy_hard = mdio_phy_pin_read(); phy_hard = mdio_phy_pin_read();
phy_addr = (phy_hard & (~phy_sel)) | (phy_softaddr & phy_sel); phy_addr = (phy_hard & (~phy_sel)) | (phy_softaddr & phy_sel);
return phy_addr; return phy_addr;
} }
@ -128,7 +128,7 @@ void mdio_soft_phyadr_set(uint32_t phy_soft)
} }
/*! /*!
\brief select the expected frame field PHYADR \brief select the expected frame field PHYADR
\param[in] phy_sel: PHYADR select \param[in] phy_sel: PHYADR select
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg MDIO_PHYADR_HARDWARE: sets expected PHYADR = PHYPIN[4:0] \arg MDIO_PHYADR_HARDWARE: sets expected PHYADR = PHYPIN[4:0]
@ -144,7 +144,7 @@ void mdio_framefield_phyadr_config(uint32_t phy_sel)
} }
/*! /*!
\brief configure the expected frame field DEVADD \brief configure the expected frame field DEVADD
\param[in] type: device type \param[in] type: device type
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg DEVADD_PMA_PMD: device type PMA/PMD \arg DEVADD_PMA_PMD: device type PMA/PMD
@ -162,7 +162,7 @@ void mdio_framefield_devadd_config(uint16_t type)
} }
/*! /*!
\brief read the hardware PRTADR[4:0] value \brief read the hardware PRTADR[4:0] value
\param[in] none \param[in] none
\param[out] none \param[out] none
\retval uint32_t: 0x0-0x1F \retval uint32_t: 0x0-0x1F
@ -173,7 +173,7 @@ uint32_t mdio_phy_pin_read(void)
} }
/*! /*!
\brief configure the expected frame bit timeout \brief configure the expected frame bit timeout
\param[in] timeout: timeout counter among frame bits (0 - 0xFFFF) \param[in] timeout: timeout counter among frame bits (0 - 0xFFFF)
\param[out] none \param[out] none
\retval none \retval none
@ -185,7 +185,7 @@ void mdio_timeout_config(uint16_t timeout)
} }
/*! /*!
\brief enable MDIO frame bit timeout \brief enable MDIO frame bit timeout
\param[in] none \param[in] none
\param[out] none \param[out] none
\retval none \retval none
@ -196,7 +196,7 @@ void mdio_timeout_enable(void)
} }
/*! /*!
\brief disable MDIO frame bit timeout \brief disable MDIO frame bit timeout
\param[in] none \param[in] none
\param[out] none \param[out] none
\retval none \retval none
@ -207,7 +207,7 @@ void mdio_timeout_disable(void)
} }
/*! /*!
\brief read the received frame field OP \brief read the received frame field OP
\param[in] none \param[in] none
\param[out] none \param[out] none
\retval uint16_t: 0x0-0x11 \retval uint16_t: 0x0-0x11
@ -218,7 +218,7 @@ uint16_t mdio_op_receive(void)
} }
/*! /*!
\brief read the received frame field PHYADR \brief read the received frame field PHYADR
\param[in] none \param[in] none
\param[out] none \param[out] none
\retval uint16_t: 0x0-0x1F \retval uint16_t: 0x0-0x1F
@ -229,7 +229,7 @@ uint16_t mdio_phyadr_receive(void)
} }
/*! /*!
\brief read the received frame field DEVADD \brief read the received frame field DEVADD
\param[in] none \param[in] none
\param[out] none \param[out] none
\retval uint16_t: 0x0-0x1F \retval uint16_t: 0x0-0x1F
@ -240,7 +240,7 @@ uint16_t mdio_devadd_receive(void)
} }
/*! /*!
\brief read the received frame field TA \brief read the received frame field TA
\param[in] none \param[in] none
\param[out] none \param[out] none
\retval uint16_t: 0x0-0x11 \retval uint16_t: 0x0-0x11
@ -251,7 +251,7 @@ uint16_t mdio_ta_receive(void)
} }
/*! /*!
\brief read the received frame field DATA \brief read the received frame field DATA
\param[in] none \param[in] none
\param[out] none \param[out] none
\retval uint16_t: 0x0-0xFFFF \retval uint16_t: 0x0-0xFFFF
@ -262,7 +262,7 @@ uint16_t mdio_data_receive(void)
} }
/*! /*!
\brief read the received frame field ADDRESS \brief read the received frame field ADDRESS
\param[in] none \param[in] none
\param[out] none \param[out] none
\retval uint16_t: 0x0-0xFFFF \retval uint16_t: 0x0-0xFFFF
@ -273,7 +273,7 @@ uint16_t mdio_address_receive(void)
} }
/*! /*!
\brief transmit the frame field DATA \brief transmit the frame field DATA
\param[in] data: data to put in a read or post read increment address frame for transmission (0x0-0xFFFF) \param[in] data: data to put in a read or post read increment address frame for transmission (0x0-0xFFFF)
\param[out] none \param[out] none
\retval none \retval none
@ -284,12 +284,12 @@ void mdio_data_transmit(uint16_t data)
} }
/*! /*!
\brief get the flag status of the frame \brief get the flag status of the frame
\param[in] flag: MDIO flag \param[in] flag: MDIO flag
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg MDIO_FLAG_WRFRM: a write data frame flag status \arg MDIO_FLAG_WRFRM: a write data frame flag status
\arg MDIO_FLAG_ADDRFRM: an address frame flag status \arg MDIO_FLAG_ADDRFRM: an address frame flag status
\arg MDIO_FLAG_RDINCFRM: a post read increment address frame flag status \arg MDIO_FLAG_RDINCFRM: a post read increment address frame flag status
\arg MDIO_FLAG_RDFRM: a read data frame flag status \arg MDIO_FLAG_RDFRM: a read data frame flag status
\arg MDIO_FLAG_DEVM: a DEVADD match frame flag status \arg MDIO_FLAG_DEVM: a DEVADD match frame flag status
\arg MDIO_FLAG_DEVNM: a DEVADD nonmatch frame flag status \arg MDIO_FLAG_DEVNM: a DEVADD nonmatch frame flag status
@ -308,7 +308,8 @@ FlagStatus mdio_flag_get(uint32_t flag)
__IO uint32_t reg = 0U; __IO uint32_t reg = 0U;
reg = MDIO_STAT; reg = MDIO_STAT;
if(RESET != (reg & flag)){ if(RESET != (reg & flag))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -321,7 +322,7 @@ FlagStatus mdio_flag_get(uint32_t flag)
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg MDIO_FLAG_WRFRM: a write data frame flag status \arg MDIO_FLAG_WRFRM: a write data frame flag status
\arg MDIO_FLAG_ADDRFRM: an address frame flag status \arg MDIO_FLAG_ADDRFRM: an address frame flag status
\arg MDIO_FLAG_RDINCFRM: a post read increment address frame flag status \arg MDIO_FLAG_RDINCFRM: a post read increment address frame flag status
\arg MDIO_FLAG_RDFRM: a read data frame flag status \arg MDIO_FLAG_RDFRM: a read data frame flag status
\arg MDIO_FLAG_DEVM: a DEVADD match frame flag status \arg MDIO_FLAG_DEVM: a DEVADD match frame flag status
\arg MDIO_FLAG_DEVNM: a DEVADD nonmatch frame flag status \arg MDIO_FLAG_DEVNM: a DEVADD nonmatch frame flag status
@ -338,15 +339,18 @@ FlagStatus mdio_flag_get(uint32_t flag)
void mdio_flag_clear(uint32_t flag) void mdio_flag_clear(uint32_t flag)
{ {
__IO uint32_t reg = 0U; __IO uint32_t reg = 0U;
reg = MDIO_TDATA; reg = MDIO_TDATA;
if((MDIO_FLAG_RX_OVERRUN | MDIO_FLAG_RBNE) & flag){ if((MDIO_FLAG_RX_OVERRUN | MDIO_FLAG_RBNE) & flag)
{
(void)(MDIO_RDATA); (void)(MDIO_RDATA);
}else if(MDIO_FLAG_TX_UNDERRUN & flag){ }else if(MDIO_FLAG_TX_UNDERRUN & flag)
{
MDIO_TDATA = reg; MDIO_TDATA = reg;
}else if((MDIO_FLAG_WRFRM | MDIO_FLAG_ADDRFRM | MDIO_FLAG_RDINCFRM | MDIO_FLAG_RDFRM }else if((MDIO_FLAG_WRFRM | MDIO_FLAG_ADDRFRM | MDIO_FLAG_RDINCFRM | MDIO_FLAG_RDFRM
| MDIO_FLAG_DEVM | MDIO_FLAG_DEVNM | MDIO_FLAG_PHYM | MDIO_FLAG_PHYNM | MDIO_FLAG_TIMEOUT) & flag){ | MDIO_FLAG_DEVM | MDIO_FLAG_DEVNM | MDIO_FLAG_PHYM | MDIO_FLAG_PHYNM | MDIO_FLAG_TIMEOUT) & flag)
{
(void)(MDIO_STAT); (void)(MDIO_STAT);
} else { } else {
/* illegal parameters */ /* illegal parameters */
@ -354,7 +358,7 @@ void mdio_flag_clear(uint32_t flag)
} }
/*! /*!
\brief enable MDIO interrupt \brief enable MDIO interrupt
\param[in] interrupt: MDIO interrupt \param[in] interrupt: MDIO interrupt
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg MDIO_INT_WRFRM: a write data frame interrupt \arg MDIO_INT_WRFRM: a write data frame interrupt
@ -379,7 +383,7 @@ void mdio_interrupt_enable(uint32_t interrupt)
} }
/*! /*!
\brief disable MDIO interrupt \brief disable MDIO interrupt
\param[in] interrupt: MDIO interrupt \param[in] interrupt: MDIO interrupt
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg MDIO_INT_WRFRM: a write data frame interrupt \arg MDIO_INT_WRFRM: a write data frame interrupt

53
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_mdma.c
View File

@ -204,14 +204,18 @@ void mdma_init(mdma_channel_enum channelx, mdma_parameter_struct *init_struct)
MDMA_CHXDADDR(channelx) = init_struct->destination_addr; MDMA_CHXDADDR(channelx) = init_struct->destination_addr;
/* configure block transfer byte number */ /* configure block transfer byte number */
if(MDMA_BUFFER_TRANSFER == init_struct->trans_trig_mode) { if(MDMA_BUFFER_TRANSFER == init_struct->trans_trig_mode)
{
MDMA_CHXBTCFG(channelx) = (init_struct->tbytes_num_in_block & MDMA_CHXBTCFG_TBNUM); MDMA_CHXBTCFG(channelx) = (init_struct->tbytes_num_in_block & MDMA_CHXBTCFG_TBNUM);
} else if(MDMA_BLOCK_TRANSFER == init_struct->trans_trig_mode) { } else if(MDMA_BLOCK_TRANSFER == init_struct->trans_trig_mode)
{
MDMA_CHXBTCFG(channelx) = (init_struct->tbytes_num_in_block & MDMA_CHXBTCFG_TBNUM); MDMA_CHXBTCFG(channelx) = (init_struct->tbytes_num_in_block & MDMA_CHXBTCFG_TBNUM);
} else if(MDMA_MULTI_BLOCK_TRANSFER == init_struct->trans_trig_mode) { } else if(MDMA_MULTI_BLOCK_TRANSFER == init_struct->trans_trig_mode)
{
MDMA_CHXBTCFG(channelx) &= ~MDMA_CHXBTCFG_TBNUM; MDMA_CHXBTCFG(channelx) &= ~MDMA_CHXBTCFG_TBNUM;
MDMA_CHXBTCFG(channelx) |= (init_struct->tbytes_num_in_block & MDMA_CHXBTCFG_TBNUM); MDMA_CHXBTCFG(channelx) |= (init_struct->tbytes_num_in_block & MDMA_CHXBTCFG_TBNUM);
} else if(MDMA_COMPLETE_TRANSFER == init_struct->trans_trig_mode) { } else if(MDMA_COMPLETE_TRANSFER == init_struct->trans_trig_mode)
{
MDMA_CHXBTCFG(channelx) &= ~MDMA_CHXBTCFG_TBNUM; MDMA_CHXBTCFG(channelx) &= ~MDMA_CHXBTCFG_TBNUM;
MDMA_CHXBTCFG(channelx) |= (init_struct->tbytes_num_in_block & MDMA_CHXBTCFG_TBNUM); MDMA_CHXBTCFG(channelx) |= (init_struct->tbytes_num_in_block & MDMA_CHXBTCFG_TBNUM);
} else { } else {
@ -220,7 +224,8 @@ void mdma_init(mdma_channel_enum channelx, mdma_parameter_struct *init_struct)
/* configure request source */ /* configure request source */
MDMA_CHXCFG(channelx) &= ~MDMA_CHXCFG_SWREQMOD; MDMA_CHXCFG(channelx) &= ~MDMA_CHXCFG_SWREQMOD;
if(MDMA_REQUEST_SW == init_struct->request) { if(MDMA_REQUEST_SW == init_struct->request)
{
MDMA_CHXCFG(channelx) |= MDMA_CHXCFG_SWREQMOD; MDMA_CHXCFG(channelx) |= MDMA_CHXCFG_SWREQMOD;
} else { } else {
MDMA_CHXCTL1(channelx) &= ~MDMA_CHXCTL1_TRIGSEL; MDMA_CHXCTL1(channelx) &= ~MDMA_CHXCTL1_TRIGSEL;
@ -274,7 +279,8 @@ void mdma_multi_block_mode_config(mdma_channel_enum channelx, uint32_t tbnum, md
MDMA_CHXMBADDRU(channelx) &= ~(MDMA_CHXMBADDRU_SADDRUV | MDMA_CHXMBADDRU_DADDRUV); MDMA_CHXMBADDRU(channelx) &= ~(MDMA_CHXMBADDRU_SADDRUV | MDMA_CHXMBADDRU_DADDRUV);
/* if block source address offset is negative, set the block repeat source address update mode to decrement */ /* if block source address offset is negative, set the block repeat source address update mode to decrement */
if(UPDATE_DIR_DECREASE == block_init_struct->saddr_update_dir) { if(UPDATE_DIR_DECREASE == block_init_struct->saddr_update_dir)
{
MDMA_CHXBTCFG(channelx) |= MDMA_CHXBTCFG_SADDRUM; MDMA_CHXBTCFG(channelx) |= MDMA_CHXBTCFG_SADDRUM;
/* write new chxmbaddru register value: source repeat block offset */ /* write new chxmbaddru register value: source repeat block offset */
blockoffset = (uint32_t)block_init_struct->saddr_update_val; blockoffset = (uint32_t)block_init_struct->saddr_update_val;
@ -285,7 +291,8 @@ void mdma_multi_block_mode_config(mdma_channel_enum channelx, uint32_t tbnum, md
MDMA_CHXMBADDRU(channelx) |= (((uint32_t)block_init_struct->saddr_update_val) & MDMA_ADDRESS_MASK); MDMA_CHXMBADDRU(channelx) |= (((uint32_t)block_init_struct->saddr_update_val) & MDMA_ADDRESS_MASK);
} }
if(UPDATE_DIR_DECREASE == block_init_struct->dstaddr_update_dir) { if(UPDATE_DIR_DECREASE == block_init_struct->dstaddr_update_dir)
{
MDMA_CHXBTCFG(channelx) |= MDMA_CHXBTCFG_DADDRUM; MDMA_CHXBTCFG(channelx) |= MDMA_CHXBTCFG_DADDRUM;
/* write new chxmbaddru register value: destination repeat block offset */ /* write new chxmbaddru register value: destination repeat block offset */
blockoffset = (uint32_t)block_init_struct->dstaddr_update_val; blockoffset = (uint32_t)block_init_struct->dstaddr_update_val;
@ -357,7 +364,8 @@ void mdma_node_create(mdma_link_node_parameter_struct *node, mdma_multi_block_pa
node->chxcfg_reg = cfg; node->chxcfg_reg = cfg;
/* configure channel request source */ /* configure channel request source */
if(MDMA_REQUEST_SW == init_struct->request) { if(MDMA_REQUEST_SW == init_struct->request)
{
node->chxcfg_reg |= MDMA_CHXCFG_SWREQMOD; node->chxcfg_reg |= MDMA_CHXCFG_SWREQMOD;
} else { } else {
node->chxctl1_reg &= ~MDMA_CHXCTL1_TRIGSEL; node->chxctl1_reg &= ~MDMA_CHXCTL1_TRIGSEL;
@ -366,7 +374,7 @@ void mdma_node_create(mdma_link_node_parameter_struct *node, mdma_multi_block_pa
/* configure bus type for source and destination */ /* configure bus type for source and destination */
node->chxctl1_reg &= ~(MDMA_CHXCTL1_SBSEL | MDMA_CHXCTL1_DBSEL); node->chxctl1_reg &= ~(MDMA_CHXCTL1_SBSEL | MDMA_CHXCTL1_DBSEL);
node->chxctl1_reg |= (init_struct->source_bus | init_struct->destination_bus); node->chxctl1_reg |= (init_struct->source_bus | init_struct->destination_bus);
/* configure channel block transfer configure register */ /* configure channel block transfer configure register */
cfg = (((block_init_struct->block_num << CHXBTCFG_BRNUM_OFFSET) & MDMA_CHXBTCFG_BRNUM)| (init_struct->tbytes_num_in_block & MDMA_CHXBTCFG_TBNUM)); cfg = (((block_init_struct->block_num << CHXBTCFG_BRNUM_OFFSET) & MDMA_CHXBTCFG_BRNUM)| (init_struct->tbytes_num_in_block & MDMA_CHXBTCFG_TBNUM));
node->chxbtcfg_reg = cfg; node->chxbtcfg_reg = cfg;
@ -379,7 +387,8 @@ void mdma_node_create(mdma_link_node_parameter_struct *node, mdma_multi_block_pa
node->chxmbaddru_reg &= ~(MDMA_CHXMBADDRU_SADDRUV | MDMA_CHXMBADDRU_DADDRUV); node->chxmbaddru_reg &= ~(MDMA_CHXMBADDRU_SADDRUV | MDMA_CHXMBADDRU_DADDRUV);
/* if block source address offset is negative, set the block repeat source address update mode to decrement */ /* if block source address offset is negative, set the block repeat source address update mode to decrement */
if(UPDATE_DIR_DECREASE == block_init_struct->saddr_update_val) { if(UPDATE_DIR_DECREASE == block_init_struct->saddr_update_val)
{
node->chxbtcfg_reg |= MDMA_CHXBTCFG_SADDRUM; node->chxbtcfg_reg |= MDMA_CHXBTCFG_SADDRUM;
/* write new chxmbaddru register value: source repeat block offset */ /* write new chxmbaddru register value: source repeat block offset */
blockoffset = (uint32_t)block_init_struct->saddr_update_val; blockoffset = (uint32_t)block_init_struct->saddr_update_val;
@ -390,7 +399,8 @@ void mdma_node_create(mdma_link_node_parameter_struct *node, mdma_multi_block_pa
node->chxmbaddru_reg |= (((uint32_t)block_init_struct->saddr_update_val) & MDMA_ADDRESS_MASK); node->chxmbaddru_reg |= (((uint32_t)block_init_struct->saddr_update_val) & MDMA_ADDRESS_MASK);
} }
if(UPDATE_DIR_DECREASE == block_init_struct->dstaddr_update_dir) { if(UPDATE_DIR_DECREASE == block_init_struct->dstaddr_update_dir)
{
node->chxbtcfg_reg |= MDMA_CHXBTCFG_DADDRUM; node->chxbtcfg_reg |= MDMA_CHXBTCFG_DADDRUM;
/* write new chxmbaddru register value: destination repeat block offset */ /* write new chxmbaddru register value: destination repeat block offset */
blockoffset = (uint32_t)block_init_struct->dstaddr_update_val; blockoffset = (uint32_t)block_init_struct->dstaddr_update_val;
@ -462,7 +472,8 @@ void mdma_node_add(mdma_link_node_parameter_struct *pre_node, mdma_link_node_par
*/ */
ErrStatus mdma_node_delete(mdma_link_node_parameter_struct *pre_node, mdma_link_node_parameter_struct *unused_node) ErrStatus mdma_node_delete(mdma_link_node_parameter_struct *pre_node, mdma_link_node_parameter_struct *unused_node)
{ {
if(pre_node->chxladdr_reg != (uint32_t)unused_node) { if(pre_node->chxladdr_reg != (uint32_t)unused_node)
{
/* link address unmatched */ /* link address unmatched */
return ERROR; return ERROR;
} else { } else {
@ -855,17 +866,20 @@ FlagStatus mdma_flag_get(mdma_channel_enum channelx, uint32_t flag)
{ {
uint32_t flag_pos = 0U; uint32_t flag_pos = 0U;
if(STAT1_FLAG & flag) { if(STAT1_FLAG & flag)
{
/* get the flag in CHXSTAT1 */ /* get the flag in CHXSTAT1 */
flag_pos = (flag & STAT1_FLAG_MASK); flag_pos = (flag & STAT1_FLAG_MASK);
if(MDMA_CHXSTAT1(channelx) & flag_pos) { if(MDMA_CHXSTAT1(channelx) & flag_pos)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
} }
} else { } else {
/* get the flag in CHXSTAT0 */ /* get the flag in CHXSTAT0 */
if(MDMA_CHXSTAT0(channelx) & flag) { if(MDMA_CHXSTAT0(channelx) & flag)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -894,7 +908,8 @@ FlagStatus mdma_flag_get(mdma_channel_enum channelx, uint32_t flag)
*/ */
void mdma_flag_clear(mdma_channel_enum channelx, uint32_t flag) void mdma_flag_clear(mdma_channel_enum channelx, uint32_t flag)
{ {
if(STAT1_FLAG & flag) { if(STAT1_FLAG & flag)
{
MDMA_CHXSTATC(channelx) |= MDMA_CHXSTATC_ERRC; MDMA_CHXSTATC(channelx) |= MDMA_CHXSTATC_ERRC;
} else { } else {
MDMA_CHXSTATC(channelx) |= flag; MDMA_CHXSTATC(channelx) |= flag;
@ -960,7 +975,8 @@ FlagStatus mdma_interrupt_flag_get(mdma_channel_enum channelx, uint32_t int_flag
{ {
uint32_t interrupt_enable = 0U, interrupt_flag = 0U; uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
switch(int_flag) { switch(int_flag)
{
case MDMA_INT_FLAG_ERR: case MDMA_INT_FLAG_ERR:
/* get error interrupt enable bit and flag bit */ /* get error interrupt enable bit and flag bit */
interrupt_enable = (MDMA_CHXCTL0(channelx) & MDMA_CHXCTL0_ERRIE); interrupt_enable = (MDMA_CHXCTL0(channelx) & MDMA_CHXCTL0_ERRIE);
@ -990,7 +1006,8 @@ FlagStatus mdma_interrupt_flag_get(mdma_channel_enum channelx, uint32_t int_flag
break; break;
} }
if(interrupt_flag && interrupt_enable) { if(interrupt_flag && interrupt_enable)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;

14
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_misc.c
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@ -66,7 +66,8 @@ void nvic_irq_enable(uint8_t nvic_irq,
uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
/* use the priority group value to get the temp_pre and the temp_sub */ /* use the priority group value to get the temp_pre and the temp_sub */
switch((SCB->AIRCR) & (uint32_t)0x700U) { switch((SCB->AIRCR) & (uint32_t)0x700U)
{
case NVIC_PRIGROUP_PRE0_SUB4: case NVIC_PRIGROUP_PRE0_SUB4:
temp_pre = 0U; temp_pre = 0U;
temp_sub = 0x4U; temp_sub = 0x4U;
@ -175,7 +176,8 @@ void system_lowpower_reset(uint8_t lowpower_mode)
*/ */
void systick_clksource_set(uint32_t systick_clksource) void systick_clksource_set(uint32_t systick_clksource)
{ {
if(SYSTICK_CLKSOURCE_CKSYS == systick_clksource) { if(SYSTICK_CLKSOURCE_CKSYS == systick_clksource)
{
/* set the systick clock source from CK_SYS */ /* set the systick clock source from CK_SYS */
SysTick->CTRL |= SYSTICK_CLKSOURCE_CKSYS; SysTick->CTRL |= SYSTICK_CLKSOURCE_CKSYS;
} else { } else {
@ -212,11 +214,11 @@ void mpu_region_struct_para_init(mpu_region_init_struct *mpu_init_struct)
region_number: region number region_number: region number
MPU_REGION_NUMBERn (n=0,..,15) MPU_REGION_NUMBERn (n=0,..,15)
region_base_address: region base address region_base_address: region base address
region_size: MPU_REGION_SIZE_32B, MPU_REGION_SIZE_64B, MPU_REGION_SIZE_128B, MPU_REGION_SIZE_256B, MPU_REGION_SIZE_512B, region_size: MPU_REGION_SIZE_32B, MPU_REGION_SIZE_64B, MPU_REGION_SIZE_128B, MPU_REGION_SIZE_256B, MPU_REGION_SIZE_512B,
MPU_REGION_SIZE_1KB, MPU_REGION_SIZE_2KB, MPU_REGION_SIZE_4KB, MPU_REGION_SIZE_8KB, MPU_REGION_SIZE_16KB, MPU_REGION_SIZE_1KB, MPU_REGION_SIZE_2KB, MPU_REGION_SIZE_4KB, MPU_REGION_SIZE_8KB, MPU_REGION_SIZE_16KB,
MPU_REGION_SIZE_32KB, MPU_REGION_SIZE_64KB, MPU_REGION_SIZE_128KB, MPU_REGION_SIZE_256KB, MPU_REGION_SIZE_512KB, MPU_REGION_SIZE_32KB, MPU_REGION_SIZE_64KB, MPU_REGION_SIZE_128KB, MPU_REGION_SIZE_256KB, MPU_REGION_SIZE_512KB,
MPU_REGION_SIZE_1MB, MPU_REGION_SIZE_2MB, MPU_REGION_SIZE_4MB, MPU_REGION_SIZE_8MB, MPU_REGION_SIZE_16MB, MPU_REGION_SIZE_1MB, MPU_REGION_SIZE_2MB, MPU_REGION_SIZE_4MB, MPU_REGION_SIZE_8MB, MPU_REGION_SIZE_16MB,
MPU_REGION_SIZE_32MB, MPU_REGION_SIZE_64MB, MPU_REGION_SIZE_128MB, MPU_REGION_SIZE_256MB, MPU_REGION_SIZE_512MB, MPU_REGION_SIZE_32MB, MPU_REGION_SIZE_64MB, MPU_REGION_SIZE_128MB, MPU_REGION_SIZE_256MB, MPU_REGION_SIZE_512MB,
MPU_REGION_SIZE_1GB, MPU_REGION_SIZE_2GB, MPU_REGION_SIZE_4GB MPU_REGION_SIZE_1GB, MPU_REGION_SIZE_2GB, MPU_REGION_SIZE_4GB
subregion_disable: MPU_SUBREGION_ENABLE, MPU_SUBREGION_DISABLE subregion_disable: MPU_SUBREGION_ENABLE, MPU_SUBREGION_DISABLE
tex_type: MPU_TEX_TYPE0, MPU_TEX_TYPE1, MPU_TEX_TYPE2 tex_type: MPU_TEX_TYPE0, MPU_TEX_TYPE1, MPU_TEX_TYPE2

208
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_ospi.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -44,7 +44,8 @@ static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct
*/ */
void ospi_deinit(uint32_t ospi_periph) void ospi_deinit(uint32_t ospi_periph)
{ {
switch(ospi_periph){ switch(ospi_periph)
{
case OSPI0: case OSPI0:
/* reset OSPI0 */ /* reset OSPI0 */
rcu_periph_reset_enable(RCU_OSPI0RST); rcu_periph_reset_enable(RCU_OSPI0RST);
@ -98,29 +99,30 @@ void ospi_struct_init(ospi_parameter_struct *ospi_struct)
delay_hold_cycle: OSPI_DELAY_HOLD_NONE, OSPI_DELAY_HOLD_QUARTER_CYCLE delay_hold_cycle: OSPI_DELAY_HOLD_NONE, OSPI_DELAY_HOLD_QUARTER_CYCLE
\retval none \retval none
*/ */
void ospi_init(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct) void ospi_init(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct)
{ {
uint32_t reg = 0U; uint32_t reg = 0U;
/* configure memory type, device size, chip select high time, delay block bypass, free running clock, clock mode */ /* configure memory type, device size, chip select high time, delay block bypass, free running clock, clock mode */
reg = OSPI_DCFG0(ospi_periph); reg = OSPI_DCFG0(ospi_periph);
reg &= ~(OSPI_DCFG0_DTYSEL | OSPI_DCFG0_MESZ | OSPI_DCFG0_CSHC); reg &= ~(OSPI_DCFG0_DTYSEL | OSPI_DCFG0_MESZ | OSPI_DCFG0_CSHC);
reg |= (ospi_struct->memory_type | ospi_struct->device_size | ospi_struct->cs_hightime); reg |= (ospi_struct->memory_type | ospi_struct->device_size | ospi_struct->cs_hightime);
OSPI_DCFG0(ospi_periph) = reg; OSPI_DCFG0(ospi_periph) = reg;
/* configure wrap size */ /* configure wrap size */
OSPI_DCFG1(ospi_periph) = (OSPI_DCFG1(ospi_periph) & ~OSPI_DCFG1_WPSZ) | ospi_struct->wrap_size; OSPI_DCFG1(ospi_periph) = (OSPI_DCFG1(ospi_periph) & ~OSPI_DCFG1_WPSZ) | ospi_struct->wrap_size;
/* configure FIFO threshold */ /* configure FIFO threshold */
OSPI_CTL(ospi_periph) = (OSPI_CTL(ospi_periph) & ~OSPI_CTL_FTL) | ospi_struct->fifo_threshold; OSPI_CTL(ospi_periph) = (OSPI_CTL(ospi_periph) & ~OSPI_CTL_FTL) | ospi_struct->fifo_threshold;
/* wait till BUSY flag reset */ /* wait till BUSY flag reset */
while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_BUSY)){ while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_BUSY))
{
} }
/* configure clock prescaler */ /* configure clock prescaler */
OSPI_DCFG1(ospi_periph) = (OSPI_DCFG1(ospi_periph) & ~OSPI_DCFG1_PSC) | OSPI_PSC(ospi_struct->prescaler); OSPI_DCFG1(ospi_periph) = (OSPI_DCFG1(ospi_periph) & ~OSPI_DCFG1_PSC) | OSPI_PSC(ospi_struct->prescaler);
@ -291,7 +293,7 @@ void ospi_chip_select_high_cycle_config(uint32_t ospi_periph, uint32_t cshc)
} }
/*! /*!
\brief configure OSPI prescaler \brief configure OSPI prescaler
\param[in] ospi_periph: OSPIx(x=0,1) \param[in] ospi_periph: OSPIx(x=0,1)
\param[in] psc: between 0 and 0xFF \param[in] psc: between 0 and 0xFF
\param[out] none \param[out] none
@ -314,7 +316,7 @@ void ospi_prescaler_config(uint32_t ospi_periph, uint32_t psc)
*/ */
void ospi_dummy_cycles_config(uint32_t ospi_periph, uint32_t dumyc) void ospi_dummy_cycles_config(uint32_t ospi_periph, uint32_t dumyc)
{ {
OSPI_TIMCFG(ospi_periph) &= (uint32_t)(~OSPI_TIMCFG_DUMYC); OSPI_TIMCFG(ospi_periph) &= (uint32_t)(~OSPI_TIMCFG_DUMYC);
OSPI_TIMCFG(ospi_periph) |= (uint32_t)dumyc ; OSPI_TIMCFG(ospi_periph) |= (uint32_t)dumyc ;
} }
@ -1022,7 +1024,7 @@ void ospi_write_address_size_config(uint32_t ospi_periph, uint32_t addrsz)
\retval none \retval none
*/ */
void ospi_write_alternate_byte_config(uint32_t ospi_periph, uint32_t alte) void ospi_write_alternate_byte_config(uint32_t ospi_periph, uint32_t alte)
{ {
OSPI_WALTE(ospi_periph) = (uint32_t)alte; OSPI_WALTE(ospi_periph) = (uint32_t)alte;
} }
@ -1040,7 +1042,7 @@ void ospi_write_alternate_byte_config(uint32_t ospi_periph, uint32_t alte)
\retval none \retval none
*/ */
void ospi_write_alternate_byte_mode_config(uint32_t ospi_periph, uint32_t atlemod) void ospi_write_alternate_byte_mode_config(uint32_t ospi_periph, uint32_t atlemod)
{ {
OSPI_WTCFG(ospi_periph) &= (uint32_t)~(OSPI_WTCFG_ALTEMOD); OSPI_WTCFG(ospi_periph) &= (uint32_t)~(OSPI_WTCFG_ALTEMOD);
OSPI_WTCFG(ospi_periph) |= (uint32_t)atlemod; OSPI_WTCFG(ospi_periph) |= (uint32_t)atlemod;
} }
@ -1056,7 +1058,7 @@ void ospi_write_alternate_byte_mode_config(uint32_t ospi_periph, uint32_t atlemo
\retval none \retval none
*/ */
void ospi_write_alternate_byte_dtr_config(uint32_t ospi_periph, uint32_t abdtr) void ospi_write_alternate_byte_dtr_config(uint32_t ospi_periph, uint32_t abdtr)
{ {
OSPI_WTCFG(ospi_periph) &= (uint32_t)~(OSPI_WTCFG_ABDTR); OSPI_WTCFG(ospi_periph) &= (uint32_t)~(OSPI_WTCFG_ABDTR);
OSPI_WTCFG(ospi_periph) |= (uint32_t)abdtr; OSPI_WTCFG(ospi_periph) |= (uint32_t)abdtr;
} }
@ -1074,7 +1076,7 @@ void ospi_write_alternate_byte_dtr_config(uint32_t ospi_periph, uint32_t abdtr)
\retval none \retval none
*/ */
void ospi_write_alternate_byte_size_config(uint32_t ospi_periph, uint32_t altesz) void ospi_write_alternate_byte_size_config(uint32_t ospi_periph, uint32_t altesz)
{ {
OSPI_WTCFG(ospi_periph) &= (uint32_t)~(OSPI_WTCFG_ALTESZ); OSPI_WTCFG(ospi_periph) &= (uint32_t)~(OSPI_WTCFG_ALTESZ);
OSPI_WTCFG(ospi_periph) |= (uint32_t)altesz; OSPI_WTCFG(ospi_periph) |= (uint32_t)altesz;
} }
@ -1143,7 +1145,7 @@ void ospi_write_dummy_cycles_config(uint32_t ospi_periph, uint32_t dumyc)
memory_type: OSPI_MICRON_MODE, OSPI_MACRONIX_MODE, OSPI_STANDARD_MODE memory_type: OSPI_MICRON_MODE, OSPI_MACRONIX_MODE, OSPI_STANDARD_MODE
OSPI_MACRONIX_RAM_MODE OSPI_MACRONIX_RAM_MODE
wrap_size: OSPI_DIRECT, OSPI_WRAP_16BYTES, OSPI_WRAP_32BYTES wrap_size: OSPI_DIRECT, OSPI_WRAP_16BYTES, OSPI_WRAP_32BYTES
OSPI_WRAP_64BYTES, OSPI_WRAP_128BYTES OSPI_WRAP_64BYTES, OSPI_WRAP_128BYTES
\param[in] cmd_struct: structure that contains the command configuration information \param[in] cmd_struct: structure that contains the command configuration information
and the member values are shown as below: and the member values are shown as below:
operation_type: OSPI_OPTYPE_COMMON_CFG, OSPI_OPTYPE_READ_CFG operation_type: OSPI_OPTYPE_COMMON_CFG, OSPI_OPTYPE_READ_CFG
@ -1177,18 +1179,22 @@ void ospi_write_dummy_cycles_config(uint32_t ospi_periph, uint32_t dumyc)
void ospi_command_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct, ospi_regular_cmd_struct *cmd_struct) void ospi_command_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct, ospi_regular_cmd_struct *cmd_struct)
{ {
if(((cmd_struct->operation_type == OSPI_OPTYPE_WRITE_CFG) || (cmd_struct->operation_type == OSPI_OPTYPE_WRAP_CFG)) || if(((cmd_struct->operation_type == OSPI_OPTYPE_WRITE_CFG) || (cmd_struct->operation_type == OSPI_OPTYPE_WRAP_CFG)) ||
((cmd_struct->operation_type == OSPI_OPTYPE_READ_CFG) || (cmd_struct->operation_type == OSPI_OPTYPE_COMMON_CFG))){ ((cmd_struct->operation_type == OSPI_OPTYPE_READ_CFG) || (cmd_struct->operation_type == OSPI_OPTYPE_COMMON_CFG)))
{
/* wait till busy flag is reset */ /* wait till busy flag is reset */
while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_BUSY)){ while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_BUSY))
{
} }
/* configure the registers */ /* configure the registers */
ospi_config(ospi_periph, ospi_struct, cmd_struct); ospi_config(ospi_periph, ospi_struct, cmd_struct);
if(cmd_struct->data_mode == OSPI_DATA_NONE){ if(cmd_struct->data_mode == OSPI_DATA_NONE)
{
/* when there is no data phase, the transfer start as soon as the configuration is done /* when there is no data phase, the transfer start as soon as the configuration is done
so wait until TC flag is set to go back in idle state */ so wait until TC flag is set to go back in idle state */
while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_TC)){ while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_TC))
{
} }
OSPI_STATC(ospi_periph) = OSPI_STATC_TCC; OSPI_STATC(ospi_periph) = OSPI_STATC_TCC;
@ -1202,9 +1208,9 @@ void ospi_command_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struc
\param[in] pdata: pointer to data buffer \param[in] pdata: pointer to data buffer
\param[out] none \param[out] none
\retval none \retval none
*/ */
void ospi_transmit(uint32_t ospi_periph, uint8_t *pdata) void ospi_transmit(uint32_t ospi_periph, uint8_t *pdata)
{ {
uint32_t txcounter; uint32_t txcounter;
uint32_t address; uint32_t address;
/* configure counters and size */ /* configure counters and size */
@ -1216,7 +1222,8 @@ void ospi_transmit(uint32_t ospi_periph, uint8_t *pdata)
do{ do{
/* wait till fifo threshold flag is set to send data */ /* wait till fifo threshold flag is set to send data */
while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_FT)){ while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_FT))
{
} }
*((__IO uint8_t *)&OSPI_DATA(ospi_periph)) = *(uint8_t *)address; *((__IO uint8_t *)&OSPI_DATA(ospi_periph)) = *(uint8_t *)address;
address++; address++;
@ -1224,7 +1231,8 @@ void ospi_transmit(uint32_t ospi_periph, uint8_t *pdata)
}while(txcounter > 0U); }while(txcounter > 0U);
/* wait till transfer complete flag is set to go back in idle state */ /* wait till transfer complete flag is set to go back in idle state */
while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_TC)){ while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_TC))
{
} }
/* clear transfer complete flag */ /* clear transfer complete flag */
@ -1253,7 +1261,8 @@ void ospi_receive(uint32_t ospi_periph, uint8_t *pdata)
OSPI_CTL(ospi_periph) = (OSPI_CTL(ospi_periph) & ~OSPI_CTL_FMOD) | OSPI_INDIRECT_READ; OSPI_CTL(ospi_periph) = (OSPI_CTL(ospi_periph) & ~OSPI_CTL_FMOD) | OSPI_INDIRECT_READ;
/* trigger the transfer by re-writing address or instruction register */ /* trigger the transfer by re-writing address or instruction register */
if((OSPI_TCFG(ospi_periph) & OSPI_TCFG_ADDRMOD) != OSPI_ADDRESS_NONE){ if((OSPI_TCFG(ospi_periph) & OSPI_TCFG_ADDRMOD) != OSPI_ADDRESS_NONE)
{
OSPI_ADDR(ospi_periph) = addr_reg; OSPI_ADDR(ospi_periph) = addr_reg;
}else{ }else{
OSPI_INS(ospi_periph) = ins_reg; OSPI_INS(ospi_periph) = ins_reg;
@ -1261,17 +1270,19 @@ void ospi_receive(uint32_t ospi_periph, uint8_t *pdata)
do{ do{
/* wait till fifo threshold or transfer complete flags are set to read received data */ /* wait till fifo threshold or transfer complete flags are set to read received data */
while(RESET == (OSPI_STAT(ospi_periph) & (OSPI_FLAG_FT | OSPI_FLAG_TC))){ while(RESET == (OSPI_STAT(ospi_periph) & (OSPI_FLAG_FT | OSPI_FLAG_TC)))
{
} }
*(uint8_t *)address = *((__IO uint8_t *)&OSPI_DATA(ospi_periph)); *(uint8_t *)address = *((__IO uint8_t *)&OSPI_DATA(ospi_periph));
address++; address++;
rxcounter--; rxcounter--;
}while(rxcounter > 0U); }while(rxcounter > 0U);
/* wait till transfer complete flag is set to go back in idle state */ /* wait till transfer complete flag is set to go back in idle state */
while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_TC)){ while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_TC))
{
} }
/* clear transfer complete flag */ /* clear transfer complete flag */
@ -1308,28 +1319,32 @@ void ospi_autopolling_mode(uint32_t ospi_periph, ospi_parameter_struct *ospi_str
{ {
uint32_t addr_reg = OSPI_ADDR(ospi_periph); uint32_t addr_reg = OSPI_ADDR(ospi_periph);
uint32_t ins_reg = OSPI_INS(ospi_periph); uint32_t ins_reg = OSPI_INS(ospi_periph);
if(autopl_cfg_struct->automatic_stop == OSPI_AUTOMATIC_STOP_MATCH){ if(autopl_cfg_struct->automatic_stop == OSPI_AUTOMATIC_STOP_MATCH)
{
/* wait till busy flag is reset */ /* wait till busy flag is reset */
while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_BUSY)){ while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_BUSY))
{
} }
/* configure registers */ /* configure registers */
OSPI_STATMATCH(ospi_periph) = autopl_cfg_struct->match; OSPI_STATMATCH(ospi_periph) = autopl_cfg_struct->match;
OSPI_STATMK(ospi_periph) = autopl_cfg_struct->mask; OSPI_STATMK(ospi_periph) = autopl_cfg_struct->mask;
OSPI_INTERVAL(ospi_periph) = autopl_cfg_struct->interval; OSPI_INTERVAL(ospi_periph) = autopl_cfg_struct->interval;
OSPI_CTL(ospi_periph) = (OSPI_CTL(ospi_periph) & (~OSPI_CTL_SPMOD | ~OSPI_CTL_SPS | ~OSPI_CTL_FMOD)) | OSPI_CTL(ospi_periph) = (OSPI_CTL(ospi_periph) & (~OSPI_CTL_SPMOD | ~OSPI_CTL_SPS | ~OSPI_CTL_FMOD)) |
(autopl_cfg_struct->match_mode | autopl_cfg_struct->automatic_stop | OSPI_STATUS_POLLING); (autopl_cfg_struct->match_mode | autopl_cfg_struct->automatic_stop | OSPI_STATUS_POLLING);
/* trig the transfer by re-writing address or instruction register */ /* trig the transfer by re-writing address or instruction register */
if((OSPI_TCFG(ospi_periph) & OSPI_TCFG_ADDRMOD) != OSPI_ADDRESS_NONE){ if((OSPI_TCFG(ospi_periph) & OSPI_TCFG_ADDRMOD) != OSPI_ADDRESS_NONE)
{
OSPI_ADDR(ospi_periph) = addr_reg; OSPI_ADDR(ospi_periph) = addr_reg;
}else{ }else{
OSPI_INS(ospi_periph) = ins_reg; OSPI_INS(ospi_periph) = ins_reg;
} }
/* wait till status match flag is set to go back in idle state */ /* wait till status match flag is set to go back in idle state */
while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_SM)){ while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_SM))
{
} }
/* clear status match flag */ /* clear status match flag */
@ -1386,16 +1401,18 @@ void ospi_autopolling_mode(uint32_t ospi_periph, ospi_parameter_struct *ospi_str
static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct, ospi_regular_cmd_struct* cmd_struct) static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct, ospi_regular_cmd_struct* cmd_struct)
{ {
__IO uint32_t *tcfg_reg, *timcfg_reg, *ins_reg, *alte_reg; __IO uint32_t *tcfg_reg, *timcfg_reg, *ins_reg, *alte_reg;
/* re-initialize the value of the functional mode */ /* re-initialize the value of the functional mode */
OSPI_CTL(ospi_periph) &= ~OSPI_CTL_FMOD; OSPI_CTL(ospi_periph) &= ~OSPI_CTL_FMOD;
if(cmd_struct->operation_type == OSPI_OPTYPE_WRITE_CFG){ if(cmd_struct->operation_type == OSPI_OPTYPE_WRITE_CFG)
{
tcfg_reg = &(OSPI_WTCFG(ospi_periph)); tcfg_reg = &(OSPI_WTCFG(ospi_periph));
timcfg_reg = &(OSPI_WTIMCFG(ospi_periph)); timcfg_reg = &(OSPI_WTIMCFG(ospi_periph));
ins_reg = &(OSPI_WINS(ospi_periph)); ins_reg = &(OSPI_WINS(ospi_periph));
alte_reg = &(OSPI_WALTE(ospi_periph)); alte_reg = &(OSPI_WALTE(ospi_periph));
}else if(cmd_struct->operation_type == OSPI_OPTYPE_WRAP_CFG){ }else if(cmd_struct->operation_type == OSPI_OPTYPE_WRAP_CFG)
{
tcfg_reg = &(OSPI_WPTCFG(ospi_periph)); tcfg_reg = &(OSPI_WPTCFG(ospi_periph));
timcfg_reg = &(OSPI_WPTIMCFG(ospi_periph)); timcfg_reg = &(OSPI_WPTIMCFG(ospi_periph));
ins_reg = &(OSPI_WPINS(ospi_periph)); ins_reg = &(OSPI_WPINS(ospi_periph));
@ -1407,49 +1424,56 @@ static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct
alte_reg = &(OSPI_ALTE(ospi_periph)); alte_reg = &(OSPI_ALTE(ospi_periph));
} }
if(cmd_struct->alter_bytes_mode != OSPI_ALTERNATE_BYTES_NONE){ if(cmd_struct->alter_bytes_mode != OSPI_ALTERNATE_BYTES_NONE)
{
/* configure the ALTE register with alternate bytes value */ /* configure the ALTE register with alternate bytes value */
*alte_reg = cmd_struct->alter_bytes; *alte_reg = cmd_struct->alter_bytes;
/* configure the TCFG register with alternate bytes communication parameters */ /* configure the TCFG register with alternate bytes communication parameters */
*tcfg_reg = (*tcfg_reg & ~(OSPI_TCFG_ALTEMOD | OSPI_TCFG_ABDTR | OSPI_TCFG_ALTESZ)) | *tcfg_reg = (*tcfg_reg & ~(OSPI_TCFG_ALTEMOD | OSPI_TCFG_ABDTR | OSPI_TCFG_ALTESZ)) |
(cmd_struct->alter_bytes_mode | cmd_struct->alter_bytes_dtr_mode | cmd_struct->alter_bytes_size); (cmd_struct->alter_bytes_mode | cmd_struct->alter_bytes_dtr_mode | cmd_struct->alter_bytes_size);
} }
/* configure the TIMCFG register with the number of dummy cycles */ /* configure the TIMCFG register with the number of dummy cycles */
*timcfg_reg = (*timcfg_reg & ~OSPI_TIMCFG_DUMYC) | cmd_struct->dummy_cycles; *timcfg_reg = (*timcfg_reg & ~OSPI_TIMCFG_DUMYC) | cmd_struct->dummy_cycles;
if(cmd_struct->data_mode != OSPI_DATA_NONE){ if(cmd_struct->data_mode != OSPI_DATA_NONE)
if(cmd_struct->operation_type == OSPI_OPTYPE_COMMON_CFG){ {
if(cmd_struct->operation_type == OSPI_OPTYPE_COMMON_CFG)
{
/* configure the DTLEN register with the number of data */ /* configure the DTLEN register with the number of data */
OSPI_DTLEN(ospi_periph) = (cmd_struct->nbdata - 1U); OSPI_DTLEN(ospi_periph) = (cmd_struct->nbdata - 1U);
} }
} }
if(cmd_struct->ins_mode != OSPI_INSTRUCTION_NONE){ if(cmd_struct->ins_mode != OSPI_INSTRUCTION_NONE)
if(cmd_struct->addr_mode != OSPI_ADDRESS_NONE){ {
if(cmd_struct->data_mode != OSPI_DATA_NONE){ if(cmd_struct->addr_mode != OSPI_ADDRESS_NONE)
{
if(cmd_struct->data_mode != OSPI_DATA_NONE)
{
/* command with instruction, address and data */ /* command with instruction, address and data */
/* configure the TCFG register with all communication parameters */ /* configure the TCFG register with all communication parameters */
*tcfg_reg &= ~(OSPI_TCFG_IMOD | OSPI_TCFG_INSSZ | *tcfg_reg &= ~(OSPI_TCFG_IMOD | OSPI_TCFG_INSSZ |
OSPI_TCFG_ADDRMOD | OSPI_TCFG_ADDRDTR | OSPI_TCFG_ADDRSZ | OSPI_TCFG_ADDRMOD | OSPI_TCFG_ADDRDTR | OSPI_TCFG_ADDRSZ |
OSPI_TCFG_DATAMOD | OSPI_TCFG_DADTR); OSPI_TCFG_DATAMOD | OSPI_TCFG_DADTR);
*tcfg_reg = cmd_struct->ins_mode | cmd_struct->ins_size | *tcfg_reg = cmd_struct->ins_mode | cmd_struct->ins_size |
cmd_struct->addr_mode | cmd_struct->addr_dtr_mode | cmd_struct->addr_size | cmd_struct->addr_mode | cmd_struct->addr_dtr_mode | cmd_struct->addr_size |
cmd_struct->data_mode | cmd_struct->data_dtr_mode; cmd_struct->data_mode | cmd_struct->data_dtr_mode;
}else{ }else{
/* command with instruction and address */ /* command with instruction and address */
/* configure the TCFG register with all communication parameters */ /* configure the TCFG register with all communication parameters */
*tcfg_reg &= ~(OSPI_TCFG_IMOD | OSPI_TCFG_INSSZ | *tcfg_reg &= ~(OSPI_TCFG_IMOD | OSPI_TCFG_INSSZ |
OSPI_TCFG_ADDRMOD | OSPI_TCFG_ADDRDTR | OSPI_TCFG_ADDRSZ); OSPI_TCFG_ADDRMOD | OSPI_TCFG_ADDRDTR | OSPI_TCFG_ADDRSZ);
*tcfg_reg = cmd_struct->ins_mode | cmd_struct->ins_size | *tcfg_reg = cmd_struct->ins_mode | cmd_struct->ins_size |
cmd_struct->addr_mode | cmd_struct->addr_dtr_mode | cmd_struct->addr_size; cmd_struct->addr_mode | cmd_struct->addr_dtr_mode | cmd_struct->addr_size;
/* the DHQC bit is linked with DDTR bit which should be activated */ /* the DHQC bit is linked with DDTR bit which should be activated */
if((ospi_struct->delay_hold_cycle == OSPI_DELAY_HOLD_QUARTER_CYCLE) ){ if((ospi_struct->delay_hold_cycle == OSPI_DELAY_HOLD_QUARTER_CYCLE) )
{
*tcfg_reg = (*tcfg_reg & ~OSPI_DADTR_MODE_ENABLE) | OSPI_DADTR_MODE_ENABLE; *tcfg_reg = (*tcfg_reg & ~OSPI_DADTR_MODE_ENABLE) | OSPI_DADTR_MODE_ENABLE;
} }
} }
@ -1460,10 +1484,11 @@ static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct
/* configure the ADDR register with the address value */ /* configure the ADDR register with the address value */
OSPI_ADDR(ospi_periph) = cmd_struct->address; OSPI_ADDR(ospi_periph) = cmd_struct->address;
}else{ }else{
if(cmd_struct->data_mode != OSPI_DATA_NONE){ if(cmd_struct->data_mode != OSPI_DATA_NONE)
{
/* command with instruction and data */ /* command with instruction and data */
/* configure the TCFG register with all communication parameters */ /* configure the TCFG register with all communication parameters */
*tcfg_reg &= ~(OSPI_TCFG_IMOD | OSPI_TCFG_INSSZ | *tcfg_reg &= ~(OSPI_TCFG_IMOD | OSPI_TCFG_INSSZ |
OSPI_TCFG_DATAMOD | OSPI_TCFG_DADTR); OSPI_TCFG_DATAMOD | OSPI_TCFG_DADTR);
*tcfg_reg = cmd_struct->ins_mode | cmd_struct->ins_size | *tcfg_reg = cmd_struct->ins_mode | cmd_struct->ins_size |
@ -1472,36 +1497,39 @@ static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct
/* command with only instruction */ /* command with only instruction */
/* configure the TCFG register with all communication parameters */ /* configure the TCFG register with all communication parameters */
*tcfg_reg &= ~(OSPI_TCFG_IMOD | OSPI_TCFG_INSSZ); *tcfg_reg &= ~(OSPI_TCFG_IMOD | OSPI_TCFG_INSSZ);
*tcfg_reg = cmd_struct->ins_mode | cmd_struct->ins_size; *tcfg_reg = cmd_struct->ins_mode | cmd_struct->ins_size;
/* the DEHQC bit is linked with DDTR bit which should be activated */ /* the DEHQC bit is linked with DDTR bit which should be activated */
if((ospi_struct->delay_hold_cycle == OSPI_DELAY_HOLD_QUARTER_CYCLE)){ if((ospi_struct->delay_hold_cycle == OSPI_DELAY_HOLD_QUARTER_CYCLE))
{
*tcfg_reg = (*tcfg_reg & ~OSPI_DADTR_MODE_ENABLE) | OSPI_DADTR_MODE_ENABLE; *tcfg_reg = (*tcfg_reg & ~OSPI_DADTR_MODE_ENABLE) | OSPI_DADTR_MODE_ENABLE;
} }
} }
/* configure the INS register with the instruction value */ /* configure the INS register with the instruction value */
*ins_reg = cmd_struct->instruction; *ins_reg = cmd_struct->instruction;
} }
}else{ }else{
if(cmd_struct->addr_mode != OSPI_ADDRESS_NONE){ if(cmd_struct->addr_mode != OSPI_ADDRESS_NONE)
if(cmd_struct->data_mode != OSPI_DATA_NONE){ {
if(cmd_struct->data_mode != OSPI_DATA_NONE)
{
/* command with address and data */ /* command with address and data */
/* configure the TCFG register with all communication parameters */ /* configure the TCFG register with all communication parameters */
*tcfg_reg &= ~(OSPI_TCFG_ADDRMOD | OSPI_TCFG_ADDRDTR | OSPI_TCFG_ADDRSZ | *tcfg_reg &= ~(OSPI_TCFG_ADDRMOD | OSPI_TCFG_ADDRDTR | OSPI_TCFG_ADDRSZ |
OSPI_TCFG_DATAMOD | OSPI_TCFG_DADTR); OSPI_TCFG_DATAMOD | OSPI_TCFG_DADTR);
*tcfg_reg = cmd_struct->addr_mode | cmd_struct->addr_dtr_mode | cmd_struct->addr_size | *tcfg_reg = cmd_struct->addr_mode | cmd_struct->addr_dtr_mode | cmd_struct->addr_size |
cmd_struct->data_mode | cmd_struct->data_dtr_mode; cmd_struct->data_mode | cmd_struct->data_dtr_mode;
}else{ }else{
/* command with only address */ /* command with only address */
/* configure the TCFG register with all communication parameters */ /* configure the TCFG register with all communication parameters */
*tcfg_reg &= ~(OSPI_TCFG_ADDRMOD | OSPI_TCFG_ADDRDTR | OSPI_TCFG_ADDRSZ); *tcfg_reg &= ~(OSPI_TCFG_ADDRMOD | OSPI_TCFG_ADDRDTR | OSPI_TCFG_ADDRSZ);
*tcfg_reg = cmd_struct->addr_mode | cmd_struct->addr_dtr_mode | cmd_struct->addr_size; *tcfg_reg = cmd_struct->addr_mode | cmd_struct->addr_dtr_mode | cmd_struct->addr_size;
} }
/* configure the ADDR register with the instruction value */ /* configure the ADDR register with the instruction value */
@ -1511,11 +1539,11 @@ static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct
} }
/*! /*!
\brief enable OSPI interrupt \brief enable OSPI interrupt
\param[in] ospi_periph: OSPIx(x=0,1) \param[in] ospi_periph: OSPIx(x=0,1)
\param[in] interrupt: OSPI interrupt \param[in] interrupt: OSPI interrupt
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg OSPI_INT_TERR: transfer error interrupt \arg OSPI_INT_TERR: transfer error interrupt
\arg OSPI_INT_TC: transfer complete interrupt \arg OSPI_INT_TC: transfer complete interrupt
\arg OSPI_INT_FT: fifo threshold interrupt \arg OSPI_INT_FT: fifo threshold interrupt
\arg OSPI_INT_SM: status match interrupt \arg OSPI_INT_SM: status match interrupt
@ -1529,11 +1557,11 @@ void ospi_interrupt_enable(uint32_t ospi_periph, uint32_t interrupt)
} }
/*! /*!
\brief disable OSPI interrupt \brief disable OSPI interrupt
\param[in] ospi_periph: OSPIx(x=0,1) \param[in] ospi_periph: OSPIx(x=0,1)
\param[in] interrupt: OSPI interrupt \param[in] interrupt: OSPI interrupt
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg OSPI_INT_TERR: transfer error interrupt \arg OSPI_INT_TERR: transfer error interrupt
\arg OSPI_INT_TC: transfer complete interrupt \arg OSPI_INT_TC: transfer complete interrupt
\arg OSPI_INT_FT: fifo threshold interrupt \arg OSPI_INT_FT: fifo threshold interrupt
\arg OSPI_INT_SM: status match interrupt \arg OSPI_INT_SM: status match interrupt
@ -1545,7 +1573,7 @@ void ospi_interrupt_disable(uint32_t ospi_periph, uint32_t interrupt)
OSPI_CTL(ospi_periph) &= ~interrupt; OSPI_CTL(ospi_periph) &= ~interrupt;
} }
/*! /*!
\brief get OSPI fifo level \brief get OSPI fifo level
\param[in] ospi_periph: OSPIx(x=0,1) \param[in] ospi_periph: OSPIx(x=0,1)
\param[out] none \param[out] none
@ -1573,7 +1601,8 @@ uint32_t ospi_fifo_level_get(uint32_t ospi_periph)
*/ */
FlagStatus ospi_flag_get(uint32_t ospi_periph, uint32_t flag) FlagStatus ospi_flag_get(uint32_t ospi_periph, uint32_t flag)
{ {
if(RESET != (OSPI_STAT(ospi_periph) & flag)){ if(RESET != (OSPI_STAT(ospi_periph) & flag))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -1612,12 +1641,13 @@ FlagStatus ospi_interrupt_flag_get(uint32_t ospi_periph, uint32_t int_flag)
{ {
uint32_t ret1 = RESET; uint32_t ret1 = RESET;
uint32_t ret2 = RESET; uint32_t ret2 = RESET;
/* get the status of interrupt enable bit */ /* get the status of interrupt enable bit */
ret1 = (OSPI_REG_VAL(ospi_periph, int_flag) & BIT(OSPI_BIT_POS(int_flag))); ret1 = (OSPI_REG_VAL(ospi_periph, int_flag) & BIT(OSPI_BIT_POS(int_flag)));
/* get the status of interrupt flag */ /* get the status of interrupt flag */
ret2 = (OSPI_REG_VAL2(ospi_periph, int_flag) & BIT(OSPI_BIT_POS2(int_flag))); ret2 = (OSPI_REG_VAL2(ospi_periph, int_flag) & BIT(OSPI_BIT_POS2(int_flag)));
if(ret1 && ret2) { if(ret1 && ret2)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_ospim.c
View File

@ -8,32 +8,32 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
#include "gd32h7xx_ospim.h" #include "gd32h7xx_ospim.h"
#include "gd32h7xx_ospi.h" #include "gd32h7xx_ospi.h"
/*! /*!
\brief reset the OSPIM peripheral \brief reset the OSPIM peripheral

27
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_pmu.c
View File

@ -333,15 +333,18 @@ void pmu_smps_ldo_supply_config(uint32_t smpsmode)
temp |= smpsmode; temp |= smpsmode;
PMU_CTL2 = temp; PMU_CTL2 = temp;
while(0U == (PMU_CTL3 & PMU_CTL3_VOVRF)) { while(0U == (PMU_CTL3 & PMU_CTL3_VOVRF))
{
} }
/* When the SMPS supplies external circuits verify that DVSRF flag is set */ /* When the SMPS supplies external circuits verify that DVSRF flag is set */
if((smpsmode == PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || if((smpsmode == PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||
(smpsmode == PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || (smpsmode == PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||
(smpsmode == PMU_SMPS_1V8_SUPPLIES_EXT) || (smpsmode == PMU_SMPS_1V8_SUPPLIES_EXT) ||
(smpsmode == PMU_SMPS_2V5_SUPPLIES_EXT)) { (smpsmode == PMU_SMPS_2V5_SUPPLIES_EXT))
while(0U == (PMU_CTL2 & PMU_CTL2_DVSRF)) { {
while(0U == (PMU_CTL2 & PMU_CTL2_DVSRF))
{
} }
} }
} }
@ -361,7 +364,8 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd)
SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
/* select WFI or WFE command to enter sleep mode */ /* select WFI or WFE command to enter sleep mode */
if(WFI_CMD == sleepmodecmd) { if(WFI_CMD == sleepmodecmd)
{
__WFI(); __WFI();
} else { } else {
__WFE(); __WFE();
@ -387,7 +391,8 @@ void pmu_to_deepsleepmode(uint8_t deepsleepmodecmd)
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* select WFI or WFE command to enter deepsleep mode */ /* select WFI or WFE command to enter deepsleep mode */
if(WFI_CMD == deepsleepmodecmd) { if(WFI_CMD == deepsleepmodecmd)
{
__WFI(); __WFI();
} else { } else {
__SEV(); __SEV();
@ -490,7 +495,8 @@ void pmu_backup_write_disable(void)
void pmu_backup_voltage_stabilizer_enable(void) void pmu_backup_voltage_stabilizer_enable(void)
{ {
PMU_CTL1 |= PMU_CTL1_BKPVSEN; PMU_CTL1 |= PMU_CTL1_BKPVSEN;
while(RESET == (PMU_CTL1 & PMU_CTL1_BKPVSRF)) { while(RESET == (PMU_CTL1 & PMU_CTL1_BKPVSRF))
{
} }
} }
@ -556,7 +562,8 @@ void pmu_exit_deepsleep_wait_time_config(uint32_t wait_time)
*/ */
FlagStatus pmu_flag_get(uint32_t flag) FlagStatus pmu_flag_get(uint32_t flag)
{ {
if(PMU_REG_VAL(flag) & BIT(PMU_BIT_POS(flag))) { if(PMU_REG_VAL(flag) & BIT(PMU_BIT_POS(flag)))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -573,10 +580,12 @@ FlagStatus pmu_flag_get(uint32_t flag)
*/ */
void pmu_flag_clear(uint32_t flag_reset) void pmu_flag_clear(uint32_t flag_reset)
{ {
if(PMU_FLAG_WAKEUP == flag_reset) { if(PMU_FLAG_WAKEUP == flag_reset)
{
PMU_CTL0 |= PMU_CTL0_WURST; PMU_CTL0 |= PMU_CTL0_WURST;
} else { } else {
if(PMU_FLAG_STANDBY == flag_reset) { if(PMU_FLAG_STANDBY == flag_reset)
{
PMU_CTL0 |= PMU_CTL0_STBRST; PMU_CTL0 |= PMU_CTL0_STBRST;
} }
} }

41
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_rameccmu.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -45,7 +45,8 @@ OF SUCH DAMAGE.
void rameccmu_deinit(uint32_t rameccmu_periph) void rameccmu_deinit(uint32_t rameccmu_periph)
{ {
RAMECCMU_INT(rameccmu_periph) = RAMECCMU_REG_RESET_VALUE; RAMECCMU_INT(rameccmu_periph) = RAMECCMU_REG_RESET_VALUE;
if(RAMECCMU0 == rameccmu_periph){ if(RAMECCMU0 == rameccmu_periph)
{
/* reset RAMECCMU0_MONITOR0 registers */ /* reset RAMECCMU0_MONITOR0 registers */
RAMECCMU_MXCTL(RAMECCMU0_MONITOR0) = RAMECCMU_REG_RESET_VALUE; RAMECCMU_MXCTL(RAMECCMU0_MONITOR0) = RAMECCMU_REG_RESET_VALUE;
RAMECCMU_MXSTAT(RAMECCMU0_MONITOR0) = RAMECCMU_REG_RESET_VALUE; RAMECCMU_MXSTAT(RAMECCMU0_MONITOR0) = RAMECCMU_REG_RESET_VALUE;
@ -107,7 +108,7 @@ void rameccmu_deinit(uint32_t rameccmu_periph)
} }
/*! /*!
\brief get RAMECCMU monitor ECC failing address \brief get RAMECCMU monitor ECC failing address
\param[in] rameccmu_monitor: RAMECCMU monitor \param[in] rameccmu_monitor: RAMECCMU monitor
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg RAMECCMU0_MONITOR0: RAMECCMU0 monitor 0 \arg RAMECCMU0_MONITOR0: RAMECCMU0 monitor 0
@ -300,7 +301,8 @@ void rameccmu_monitor_interrupt_disable(rameccmu_monitor_enum rameccmu_monitor,
*/ */
FlagStatus rameccmu_monitor_flag_get(rameccmu_monitor_enum rameccmu_monitor, uint32_t flag) FlagStatus rameccmu_monitor_flag_get(rameccmu_monitor_enum rameccmu_monitor, uint32_t flag)
{ {
if(RESET != ((RAMECCMU_MXSTAT(rameccmu_monitor)) & flag)){ if(RESET != ((RAMECCMU_MXSTAT(rameccmu_monitor)) & flag))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -362,7 +364,8 @@ FlagStatus rameccmu_monitor_interrupt_flag_get(rameccmu_monitor_enum rameccmu_mo
/* get the status of interrupt flag */ /* get the status of interrupt flag */
ret2 = RAMECCMU_MXSTAT(rameccmu_monitor) & int_flag; ret2 = RAMECCMU_MXSTAT(rameccmu_monitor) & int_flag;
if(ret1 && ret2) { if(ret1 && ret2)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;

393
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_rcu.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -66,7 +66,8 @@ void rcu_deinit(void)
{ {
/* enable IRC64M */ /* enable IRC64M */
RCU_CTL |= RCU_CTL_IRC64MEN; RCU_CTL |= RCU_CTL_IRC64MEN;
while(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)){ while(0U == (RCU_CTL & RCU_CTL_IRC64MSTB))
{
} }
RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 &= ~RCU_CFG0_SCS;
@ -709,7 +710,8 @@ void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div)
*/ */
void rcu_pll_input_output_clock_range_config(pll_idx_enum pll_idx, uint32_t ck_input, uint32_t ck_output) void rcu_pll_input_output_clock_range_config(pll_idx_enum pll_idx, uint32_t ck_input, uint32_t ck_output)
{ {
switch(pll_idx) { switch(pll_idx)
{
case IDX_PLL0: case IDX_PLL0:
/* reset the PLLRNG/PLLVCOSEL bits and set according to ck_input/ck_output */ /* reset the PLLRNG/PLLVCOSEL bits and set according to ck_input/ck_output */
RCU_PLLALL &= ~(RCU_PLLALL_PLL0RNG | RCU_PLLALL_PLL0VCOSEL); RCU_PLLALL &= ~(RCU_PLLALL_PLL0RNG | RCU_PLLALL_PLL0VCOSEL);
@ -740,7 +742,8 @@ void rcu_pll_input_output_clock_range_config(pll_idx_enum pll_idx, uint32_t ck_i
*/ */
void rcu_pll_fractional_config(pll_idx_enum pll_idx, uint32_t pll_fracn) void rcu_pll_fractional_config(pll_idx_enum pll_idx, uint32_t pll_fracn)
{ {
switch(pll_idx) { switch(pll_idx)
{
case IDX_PLL0: case IDX_PLL0:
/* reset the PLLFRAN and set according to pll_fracn */ /* reset the PLLFRAN and set according to pll_fracn */
RCU_PLL0FRA &= ~(RCU_PLL0FRA_PLL0FRAN); RCU_PLL0FRA &= ~(RCU_PLL0FRA_PLL0FRAN);
@ -769,7 +772,8 @@ void rcu_pll_fractional_config(pll_idx_enum pll_idx, uint32_t pll_fracn)
*/ */
void rcu_pll_fractional_latch_enable(pll_idx_enum pll_idx) void rcu_pll_fractional_latch_enable(pll_idx_enum pll_idx)
{ {
switch(pll_idx) { switch(pll_idx)
{
case IDX_PLL0: case IDX_PLL0:
/* set the PLL0FRAEN */ /* set the PLL0FRAEN */
RCU_PLL0FRA |= RCU_PLL0FRA_PLL0FRAEN ; RCU_PLL0FRA |= RCU_PLL0FRA_PLL0FRAEN ;
@ -795,7 +799,8 @@ void rcu_pll_fractional_latch_enable(pll_idx_enum pll_idx)
*/ */
void rcu_pll_fractional_latch_disable(pll_idx_enum pll_idx) void rcu_pll_fractional_latch_disable(pll_idx_enum pll_idx)
{ {
switch(pll_idx) { switch(pll_idx)
{
case IDX_PLL0: case IDX_PLL0:
/* reset the PLL0FRAEN */ /* reset the PLL0FRAEN */
RCU_PLL0FRA &= ~RCU_PLL0FRA_PLL0FRAEN ; RCU_PLL0FRA &= ~RCU_PLL0FRA_PLL0FRAEN ;
@ -849,7 +854,8 @@ ErrStatus rcu_pll0_config(uint32_t pll0_psc, uint32_t pll0_n, uint32_t pll0_p, u
/* check the function parameter */ /* check the function parameter */
if(CHECK_PLL0_PSC_VALID(pll0_psc) && CHECK_PLL0_N_VALID(pll0_n) && if(CHECK_PLL0_PSC_VALID(pll0_psc) && CHECK_PLL0_N_VALID(pll0_n) &&
CHECK_PLL0_P_VALID(pll0_p) && CHECK_PLL0_Q_VALID(pll0_q) && CHECK_PLL0_P_VALID(pll0_p) && CHECK_PLL0_Q_VALID(pll0_q) &&
CHECK_PLL0_R_VALID(pll0_r)) { CHECK_PLL0_R_VALID(pll0_r))
{
RCU_PLL0 &= ~(RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0N | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R); RCU_PLL0 &= ~(RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0N | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R);
RCU_PLL0 |= pll0_psc | ((pll0_n - 1U) << RCU_PLLNOFFSET) | ((pll0_p - 1U) << RCU_PLLPOFFSET) | RCU_PLL0 |= pll0_psc | ((pll0_n - 1U) << RCU_PLLNOFFSET) | ((pll0_p - 1U) << RCU_PLLPOFFSET) |
((pll0_r - 1U) << RCU_PLLROFFSET); ((pll0_r - 1U) << RCU_PLLROFFSET);
@ -885,7 +891,8 @@ ErrStatus rcu_pll1_config(uint32_t pll1_psc, uint32_t pll1_n, uint32_t pll1_p, u
/* check the function parameter */ /* check the function parameter */
if(CHECK_PLL1_PSC_VALID(pll1_psc) && CHECK_PLL1_N_VALID(pll1_n) && if(CHECK_PLL1_PSC_VALID(pll1_psc) && CHECK_PLL1_N_VALID(pll1_n) &&
CHECK_PLL1_P_VALID(pll1_p) && CHECK_PLL1_Q_VALID(pll1_q) && CHECK_PLL1_P_VALID(pll1_p) && CHECK_PLL1_Q_VALID(pll1_q) &&
CHECK_PLL1_R_VALID(pll1_r)) { CHECK_PLL1_R_VALID(pll1_r))
{
RCU_PLL1 = (pll1_psc | ((pll1_n - 1U) << RCU_PLLNOFFSET) | ((pll1_p - 1U) << RCU_PLLPOFFSET) | RCU_PLL1 = (pll1_psc | ((pll1_n - 1U) << RCU_PLLNOFFSET) | ((pll1_p - 1U) << RCU_PLLPOFFSET) |
((pll1_r - 1U) << RCU_PLLROFFSET)); ((pll1_r - 1U) << RCU_PLLROFFSET));
RCU_PLLADDCTL &= ~RCU_PLLADDCTL_PLL1Q; RCU_PLLADDCTL &= ~RCU_PLLADDCTL_PLL1Q;
@ -920,7 +927,8 @@ ErrStatus rcu_pll2_config(uint32_t pll2_psc, uint32_t pll2_n, uint32_t pll2_p, u
/* check the function parameter */ /* check the function parameter */
if(CHECK_PLL2_PSC_VALID(pll2_psc) && CHECK_PLL2_N_VALID(pll2_n) && if(CHECK_PLL2_PSC_VALID(pll2_psc) && CHECK_PLL2_N_VALID(pll2_n) &&
CHECK_PLL2_P_VALID(pll2_p) && CHECK_PLL2_R_VALID(pll2_q) && CHECK_PLL2_P_VALID(pll2_p) && CHECK_PLL2_R_VALID(pll2_q) &&
CHECK_PLL2_R_VALID(pll2_r)) { CHECK_PLL2_R_VALID(pll2_r))
{
RCU_PLL2 = (pll2_psc | ((pll2_n - 1U) << RCU_PLLNOFFSET) | ((pll2_p - 1U) << RCU_PLLPOFFSET) | RCU_PLL2 = (pll2_psc | ((pll2_n - 1U) << RCU_PLLNOFFSET) | ((pll2_p - 1U) << RCU_PLLPOFFSET) |
((pll2_r - 1U) << RCU_PLLROFFSET)); ((pll2_r - 1U) << RCU_PLLROFFSET));
RCU_PLLADDCTL &= ~RCU_PLLADDCTL_PLL2Q; RCU_PLLADDCTL &= ~RCU_PLLADDCTL_PLL2Q;
@ -1133,13 +1141,17 @@ uint32_t rcu_irc64mdiv_freq_get(void)
uint32_t irc64m_freq = 0U; uint32_t irc64m_freq = 0U;
/* CK_IRC64MDIV = CK_IRC64M/1/2/4/8 */ /* CK_IRC64MDIV = CK_IRC64M/1/2/4/8 */
if(RCU_IRC64M_DIV1 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV)) { if(RCU_IRC64M_DIV1 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV))
{
irc64m_freq = IRC64M_VALUE; irc64m_freq = IRC64M_VALUE;
} else if(RCU_IRC64M_DIV2 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV)) { } else if(RCU_IRC64M_DIV2 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV))
{
irc64m_freq = IRC64M_VALUE / 2U; irc64m_freq = IRC64M_VALUE / 2U;
} else if(RCU_IRC64M_DIV4 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV)) { } else if(RCU_IRC64M_DIV4 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV))
{
irc64m_freq = IRC64M_VALUE / 4U; irc64m_freq = IRC64M_VALUE / 4U;
} else if(RCU_IRC64M_DIV8 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV)) { } else if(RCU_IRC64M_DIV8 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV))
{
irc64m_freq = IRC64M_VALUE / 8U; irc64m_freq = IRC64M_VALUE / 8U;
} else { } else {
} }
@ -1165,7 +1177,8 @@ uint32_t rcu_irc64mdiv_freq_get(void)
void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler) void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler)
{ {
/* configure the TIMERSEL bit and select the TIMER clock prescaler */ /* configure the TIMERSEL bit and select the TIMER clock prescaler */
if(timer_clock_prescaler == RCU_TIMER_PSC_MUL2) { if(timer_clock_prescaler == RCU_TIMER_PSC_MUL2)
{
RCU_CFG1 &= timer_clock_prescaler; RCU_CFG1 &= timer_clock_prescaler;
} else { } else {
RCU_CFG1 |= timer_clock_prescaler; RCU_CFG1 |= timer_clock_prescaler;
@ -1196,7 +1209,8 @@ void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler)
*/ */
void rcu_spi_clock_config(spi_idx_enum spi_idx, uint32_t ck_spi) void rcu_spi_clock_config(spi_idx_enum spi_idx, uint32_t ck_spi)
{ {
switch(spi_idx) { switch(spi_idx)
{
case IDX_SPI0: case IDX_SPI0:
/* reset the SPI0SEL bits and set according to ck_spi */ /* reset the SPI0SEL bits and set according to ck_spi */
RCU_CFG5 &= ~RCU_CFG5_SPI0SEL; RCU_CFG5 &= ~RCU_CFG5_SPI0SEL;
@ -1246,7 +1260,8 @@ void rcu_spi_clock_config(spi_idx_enum spi_idx, uint32_t ck_spi)
*/ */
void rcu_sdio_clock_config(sdio_idx_enum sdio_idx, uint32_t ck_sdio) void rcu_sdio_clock_config(sdio_idx_enum sdio_idx, uint32_t ck_sdio)
{ {
switch(sdio_idx) { switch(sdio_idx)
{
case IDX_SDIO0: case IDX_SDIO0:
/* reset the SDIO0SEL bits and set according to ck_sdio */ /* reset the SDIO0SEL bits and set according to ck_sdio */
RCU_CFG4 &= ~RCU_CFG4_SDIO0SEL; RCU_CFG4 &= ~RCU_CFG4_SDIO0SEL;
@ -1310,7 +1325,8 @@ void rcu_tli_clock_div_config(uint32_t pll2_r_div)
*/ */
void rcu_usart_clock_config(usart_idx_enum usart_idx, uint32_t ck_usart) void rcu_usart_clock_config(usart_idx_enum usart_idx, uint32_t ck_usart)
{ {
switch(usart_idx) { switch(usart_idx)
{
case IDX_USART0: case IDX_USART0:
/* reset the USART0SEL bits and set according to ck_usart */ /* reset the USART0SEL bits and set according to ck_usart */
RCU_CFG1 &= ~RCU_CFG1_USART0SEL; RCU_CFG1 &= ~RCU_CFG1_USART0SEL;
@ -1350,7 +1366,8 @@ void rcu_usart_clock_config(usart_idx_enum usart_idx, uint32_t ck_usart)
*/ */
void rcu_i2c_clock_config(i2c_idx_enum i2c_idx, uint32_t ck_i2c) void rcu_i2c_clock_config(i2c_idx_enum i2c_idx, uint32_t ck_i2c)
{ {
switch(i2c_idx) { switch(i2c_idx)
{
case IDX_I2C0: case IDX_I2C0:
/* reset the I2C0SEL bits and set according to ck_i2c */ /* reset the I2C0SEL bits and set according to ck_i2c */
RCU_CFG0 &= ~RCU_CFG0_I2C0SEL; RCU_CFG0 &= ~RCU_CFG0_I2C0SEL;
@ -1390,7 +1407,8 @@ void rcu_i2c_clock_config(i2c_idx_enum i2c_idx, uint32_t ck_i2c)
*/ */
void rcu_can_clock_config(can_idx_enum can_idx, uint32_t ck_can) void rcu_can_clock_config(can_idx_enum can_idx, uint32_t ck_can)
{ {
switch(can_idx) { switch(can_idx)
{
case IDX_CAN0: case IDX_CAN0:
/* reset the CAN0SEL bits and set according to ck_can */ /* reset the CAN0SEL bits and set according to ck_can */
RCU_CFG1 &= ~RCU_CFG1_CAN0SEL; RCU_CFG1 &= ~RCU_CFG1_CAN0SEL;
@ -1424,7 +1442,8 @@ void rcu_can_clock_config(can_idx_enum can_idx, uint32_t ck_can)
*/ */
void rcu_adc_clock_config(adc_idx_enum adc_idx, uint32_t ck_adc) void rcu_adc_clock_config(adc_idx_enum adc_idx, uint32_t ck_adc)
{ {
switch(adc_idx) { switch(adc_idx)
{
case IDX_ADC0: case IDX_ADC0:
case IDX_ADC1: case IDX_ADC1:
/* reset the ADC0SEL/ADC1SEL bits and set according to ck_adc */ /* reset the ADC0SEL/ADC1SEL bits and set according to ck_adc */
@ -1456,7 +1475,8 @@ void rcu_adc_clock_config(adc_idx_enum adc_idx, uint32_t ck_adc)
*/ */
void rcu_sai_clock_config(sai_idx_enum sai_idx, uint32_t ck_sai) void rcu_sai_clock_config(sai_idx_enum sai_idx, uint32_t ck_sai)
{ {
switch(sai_idx) { switch(sai_idx)
{
case IDX_SAI0: case IDX_SAI0:
/* reset the SAI0SEL bits and set according to ck_sai */ /* reset the SAI0SEL bits and set according to ck_sai */
RCU_CFG2 &= ~RCU_CFG2_SAI0SEL; RCU_CFG2 &= ~RCU_CFG2_SAI0SEL;
@ -1488,7 +1508,8 @@ void rcu_sai_clock_config(sai_idx_enum sai_idx, uint32_t ck_sai)
*/ */
void rcu_sai2_block_clock_config(sai2b_idx_enum sai2b_idx, uint32_t ck_sai2b) void rcu_sai2_block_clock_config(sai2b_idx_enum sai2b_idx, uint32_t ck_sai2b)
{ {
switch(sai2b_idx) { switch(sai2b_idx)
{
case IDX_SAI2B0: case IDX_SAI2B0:
/* reset the SAI2B0SEL bits and set according to ck_sai2b */ /* reset the SAI2B0SEL bits and set according to ck_sai2b */
RCU_CFG2 &= ~RCU_CFG2_SAI2B0SEL; RCU_CFG2 &= ~RCU_CFG2_SAI2B0SEL;
@ -1591,7 +1612,8 @@ void rcu_per_clock_config(uint32_t ck_per)
*/ */
void rcu_usbhs_pll1qpsc_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usbhspsc) void rcu_usbhs_pll1qpsc_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usbhspsc)
{ {
switch(usbhs_idx) { switch(usbhs_idx)
{
case IDX_USBHS0: case IDX_USBHS0:
/* reset the USBHS0PSC bits and set according to ck_usbhspsc */ /* reset the USBHS0PSC bits and set according to ck_usbhspsc */
RCU_USBCLKCTL &= ~RCU_USBCLKCTL_USBHS0PSC; RCU_USBCLKCTL &= ~RCU_USBCLKCTL_USBHS0PSC;
@ -1621,7 +1643,8 @@ void rcu_usbhs_pll1qpsc_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usbhspsc)
*/ */
void rcu_usb48m_clock_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usb48m) void rcu_usb48m_clock_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usb48m)
{ {
switch(usbhs_idx) { switch(usbhs_idx)
{
case IDX_USBHS0: case IDX_USBHS0:
/* reset the USB048MSEL bits and set according to ck_usb48m */ /* reset the USB048MSEL bits and set according to ck_usb48m */
RCU_USBCLKCTL &= ~RCU_USBCLKCTL_USBHS048MSEL; RCU_USBCLKCTL &= ~RCU_USBCLKCTL_USBHS048MSEL;
@ -1649,7 +1672,8 @@ void rcu_usb48m_clock_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usb48m)
*/ */
void rcu_usbhs_clock_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usbhs) void rcu_usbhs_clock_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usbhs)
{ {
switch(usbhs_idx) { switch(usbhs_idx)
{
case IDX_USBHS0: case IDX_USBHS0:
/* reset the USBHS0SEL bits and set according to ck_usbhs */ /* reset the USBHS0SEL bits and set according to ck_usbhs */
RCU_USBCLKCTL &= ~RCU_USBCLKCTL_USBHS0SEL; RCU_USBCLKCTL &= ~RCU_USBCLKCTL_USBHS0SEL;
@ -1673,7 +1697,8 @@ void rcu_usbhs_clock_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usbhs)
*/ */
void rcu_usbhs_clock_selection_enable(usbhs_idx_enum usbhs_idx) void rcu_usbhs_clock_selection_enable(usbhs_idx_enum usbhs_idx)
{ {
switch(usbhs_idx) { switch(usbhs_idx)
{
case IDX_USBHS0: case IDX_USBHS0:
/* set the USB0SWEN bit */ /* set the USB0SWEN bit */
RCU_USBCLKCTL |= RCU_USBCLKCTL_USBHS0SWEN; RCU_USBCLKCTL |= RCU_USBCLKCTL_USBHS0SWEN;
@ -1695,7 +1720,8 @@ void rcu_usbhs_clock_selection_enable(usbhs_idx_enum usbhs_idx)
*/ */
void rcu_usbhs_clock_selection_disable(usbhs_idx_enum usbhs_idx) void rcu_usbhs_clock_selection_disable(usbhs_idx_enum usbhs_idx)
{ {
switch(usbhs_idx) { switch(usbhs_idx)
{
case IDX_USBHS0: case IDX_USBHS0:
/* reset the USB0SWEN bit */ /* reset the USB0SWEN bit */
RCU_USBCLKCTL &= ~RCU_USBCLKCTL_USBHS0SWEN; RCU_USBCLKCTL &= ~RCU_USBCLKCTL_USBHS0SWEN;
@ -1755,136 +1781,159 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
ErrStatus reval = ERROR; ErrStatus reval = ERROR;
FlagStatus osci_stat = RESET; FlagStatus osci_stat = RESET;
switch(osci) { switch(osci)
{
/* wait HXTAL stable */ /* wait HXTAL stable */
case RCU_HXTAL: case RCU_HXTAL:
while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set */ /* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB))
{
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait LXTAL stable */ /* wait LXTAL stable */
case RCU_LXTAL: case RCU_LXTAL:
while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set */ /* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB))
{
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait IRC64M stable */ /* wait IRC64M stable */
case RCU_IRC64M: case RCU_IRC64M:
while((RESET == osci_stat) && (IRC64M_STARTUP_TIMEOUT != stb_cnt)) { while((RESET == osci_stat) && (IRC64M_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_IRC64MSTB); osci_stat = rcu_flag_get(RCU_FLAG_IRC64MSTB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set */ /* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_IRC64MSTB)) { if(RESET != rcu_flag_get(RCU_FLAG_IRC64MSTB))
{
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait IRC48M stable */ /* wait IRC48M stable */
case RCU_IRC48M: case RCU_IRC48M:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set */ /* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)) { if(RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB))
{
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait IRC32K stable */ /* wait IRC32K stable */
case RCU_IRC32K: case RCU_IRC32K:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_IRC32KSTB); osci_stat = rcu_flag_get(RCU_FLAG_IRC32KSTB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set */ /* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_IRC32KSTB)) { if(RESET != rcu_flag_get(RCU_FLAG_IRC32KSTB))
{
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait LPIRC4M stable */ /* wait LPIRC4M stable */
case RCU_LPIRC4M: case RCU_LPIRC4M:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_LPIRC4MSTB); osci_stat = rcu_flag_get(RCU_FLAG_LPIRC4MSTB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set */ /* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_LPIRC4MSTB)) { if(RESET != rcu_flag_get(RCU_FLAG_LPIRC4MSTB))
{
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait PLL0 stable */ /* wait PLL0 stable */
case RCU_PLL0_CK: case RCU_PLL0_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_PLL0STB); osci_stat = rcu_flag_get(RCU_FLAG_PLL0STB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set */ /* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_PLL0STB)) { if(RESET != rcu_flag_get(RCU_FLAG_PLL0STB))
{
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait PLL1 stable */ /* wait PLL1 stable */
case RCU_PLL1_CK: case RCU_PLL1_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set */ /* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)) { if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB))
{
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait PLL2 stable */ /* wait PLL2 stable */
case RCU_PLL2_CK: case RCU_PLL2_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set */ /* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)) { if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB))
{
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait PLLUSBHS0 stable */ /* wait PLLUSBHS0 stable */
case RCU_PLLUSBHS0_CK: case RCU_PLLUSBHS0_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_PLLUSBHS0STB); osci_stat = rcu_flag_get(RCU_FLAG_PLLUSBHS0STB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set */ /* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_PLLUSBHS0STB)) { if(RESET != rcu_flag_get(RCU_FLAG_PLLUSBHS0STB))
{
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
/* wait PLLUSBHS1 stable */ /* wait PLLUSBHS1 stable */
case RCU_PLLUSBHS1_CK: case RCU_PLLUSBHS1_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_PLLUSBHS1STB); osci_stat = rcu_flag_get(RCU_FLAG_PLLUSBHS1STB);
stb_cnt++; stb_cnt++;
} }
/* check whether flag is set */ /* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_PLLUSBHS1STB)) { if(RESET != rcu_flag_get(RCU_FLAG_PLLUSBHS1STB))
{
reval = SUCCESS; reval = SUCCESS;
} }
break; break;
@ -1955,7 +2004,8 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
{ {
uint32_t reg; uint32_t reg;
switch(osci) { switch(osci)
{
/* enable HXTAL to bypass mode */ /* enable HXTAL to bypass mode */
case RCU_HXTAL: case RCU_HXTAL:
reg = RCU_CTL; reg = RCU_CTL;
@ -1986,7 +2036,8 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
{ {
uint32_t reg; uint32_t reg;
switch(osci) { switch(osci)
{
/* disable HXTAL to bypass mode */ /* disable HXTAL to bypass mode */
case RCU_HXTAL: case RCU_HXTAL:
reg = RCU_CTL; reg = RCU_CTL;
@ -2157,7 +2208,8 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
irc64mdiv_freq = rcu_irc64mdiv_freq_get(); irc64mdiv_freq = rcu_irc64mdiv_freq_get();
sws = GET_BITS(RCU_CFG0, 2, 3); sws = GET_BITS(RCU_CFG0, 2, 3);
switch(sws) { switch(sws)
{
/* IRC64MDIV is selected as CK_SYS */ /* IRC64MDIV is selected as CK_SYS */
case SEL_IRC64MDIV: case SEL_IRC64MDIV:
cksys_freq = irc64mdiv_freq; cksys_freq = irc64mdiv_freq;
@ -2177,16 +2229,19 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll0n = (GET_BITS(RCU_PLL0, 6U, 14U) + 1U); pll0n = (GET_BITS(RCU_PLL0, 6U, 14U) + 1U);
pll0p = (GET_BITS(RCU_PLL0, 16U, 22U) + 1U); pll0p = (GET_BITS(RCU_PLL0, 16U, 22U) + 1U);
if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U) { if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL0FRA, 0U, 12U); fracn = GET_BITS(RCU_PLL0FRA, 0U, 12U);
} }
/* PLL clock source selection, HXTAL or IRC64MDIV */ /* PLL clock source selection, HXTAL or IRC64MDIV */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL); pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) { if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE; ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) { } else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq; ck_src = irc64mdiv_freq;
} else { } else {
ck_src = LPIRC4M_VALUE; ck_src = LPIRC4M_VALUE;
@ -2226,7 +2281,8 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
apb4_freq = ahb_freq >> clk_exp; apb4_freq = ahb_freq >> clk_exp;
/* return the clocks frequency */ /* return the clocks frequency */
switch(clock) { switch(clock)
{
case CK_SYS: case CK_SYS:
ck_freq = cksys_freq; ck_freq = cksys_freq;
break; break;
@ -2252,23 +2308,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll0n = (GET_BITS(RCU_PLL0, 6U, 14U) + 1U); pll0n = (GET_BITS(RCU_PLL0, 6U, 14U) + 1U);
pll0p = (GET_BITS(RCU_PLL0, 16U, 22U) + 1U); pll0p = (GET_BITS(RCU_PLL0, 16U, 22U) + 1U);
if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U) { if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL0FRA, 0U, 12U); fracn = GET_BITS(RCU_PLL0FRA, 0U, 12U);
} }
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */ /* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL); pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) { if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE; ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) { } else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq; ck_src = irc64mdiv_freq;
} else { } else {
ck_src = LPIRC4M_VALUE; ck_src = LPIRC4M_VALUE;
} }
if((pll0psc != 0U) && (ck_src != 0U)) { if((pll0psc != 0U) && (ck_src != 0U))
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL0PEN) != 0U) { {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL0PEN) != 0U)
{
pll0p_freq = rcu_pll_clock_freq_cal(ck_src, pll0psc, pll0n, fracn, pll0p); pll0p_freq = rcu_pll_clock_freq_cal(ck_src, pll0psc, pll0n, fracn, pll0p);
} }
} }
@ -2282,23 +2343,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll0n = (GET_BITS(RCU_PLL0, 6U, 14U) + 1U); pll0n = (GET_BITS(RCU_PLL0, 6U, 14U) + 1U);
pll0r = (GET_BITS(RCU_PLL0, 24U, 30U) + 1U); pll0r = (GET_BITS(RCU_PLL0, 24U, 30U) + 1U);
if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U) { if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL0FRA, 0U, 12U); fracn = GET_BITS(RCU_PLL0FRA, 0U, 12U);
} }
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */ /* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL); pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) { if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE; ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) { } else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq; ck_src = irc64mdiv_freq;
} else { } else {
ck_src = LPIRC4M_VALUE; ck_src = LPIRC4M_VALUE;
} }
if((pll0psc != 0U) && (ck_src != 0U)) { if((pll0psc != 0U) && (ck_src != 0U))
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL0REN) != 0U) { {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL0REN) != 0U)
{
pll0r_freq = rcu_pll_clock_freq_cal(ck_src, pll0psc, pll0n, fracn, pll0r); pll0r_freq = rcu_pll_clock_freq_cal(ck_src, pll0psc, pll0n, fracn, pll0r);
} }
} }
@ -2312,23 +2378,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll0n = (GET_BITS(RCU_PLL0, 6U, 14U) + 1U); pll0n = (GET_BITS(RCU_PLL0, 6U, 14U) + 1U);
pll0q = (GET_BITS(RCU_PLLADDCTL, 0U, 6U) + 1U); pll0q = (GET_BITS(RCU_PLLADDCTL, 0U, 6U) + 1U);
if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U) { if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL0FRA, 0U, 12U); fracn = GET_BITS(RCU_PLL0FRA, 0U, 12U);
} }
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */ /* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL); pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) { if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE; ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) { } else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq; ck_src = irc64mdiv_freq;
} else { } else {
ck_src = LPIRC4M_VALUE; ck_src = LPIRC4M_VALUE;
} }
if((pll0psc != 0U) && (ck_src != 0U)) { if((pll0psc != 0U) && (ck_src != 0U))
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL0QEN) != 0U) { {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL0QEN) != 0U)
{
pll0q_freq = rcu_pll_clock_freq_cal(ck_src, pll0psc, pll0n, fracn, pll0q); pll0q_freq = rcu_pll_clock_freq_cal(ck_src, pll0psc, pll0n, fracn, pll0q);
} }
} }
@ -2342,23 +2413,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll1n = (GET_BITS(RCU_PLL1, 6U, 14U) + 1U); pll1n = (GET_BITS(RCU_PLL1, 6U, 14U) + 1U);
pll1p = (GET_BITS(RCU_PLL1, 16U, 22U) + 1U); pll1p = (GET_BITS(RCU_PLL1, 16U, 22U) + 1U);
if((RCU_PLL1FRA & RCU_PLL1FRA_PLL1FRAEN) != 0U) { if((RCU_PLL1FRA & RCU_PLL1FRA_PLL1FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL1FRA, 0U, 12U); fracn = GET_BITS(RCU_PLL1FRA, 0U, 12U);
} }
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */ /* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL); pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) { if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE; ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) { } else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq; ck_src = irc64mdiv_freq;
} else { } else {
ck_src = LPIRC4M_VALUE; ck_src = LPIRC4M_VALUE;
} }
if((pll1psc != 0U) && (ck_src != 0U)) { if((pll1psc != 0U) && (ck_src != 0U))
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL1PEN) != 0U) { {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL1PEN) != 0U)
{
pll1p_freq = rcu_pll_clock_freq_cal(ck_src, pll1psc, pll1n, fracn, pll1p); pll1p_freq = rcu_pll_clock_freq_cal(ck_src, pll1psc, pll1n, fracn, pll1p);
} }
} }
@ -2372,23 +2448,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll1n = (GET_BITS(RCU_PLL1, 6U, 14U) + 1U); pll1n = (GET_BITS(RCU_PLL1, 6U, 14U) + 1U);
pll1r = (GET_BITS(RCU_PLL1, 24U, 30U) + 1U); pll1r = (GET_BITS(RCU_PLL1, 24U, 30U) + 1U);
if((RCU_PLL1FRA & RCU_PLL1FRA_PLL1FRAEN) != 0U) { if((RCU_PLL1FRA & RCU_PLL1FRA_PLL1FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL1FRA, 0U, 12U); fracn = GET_BITS(RCU_PLL1FRA, 0U, 12U);
} }
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */ /* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL); pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) { if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE; ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) { } else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq; ck_src = irc64mdiv_freq;
} else { } else {
ck_src = LPIRC4M_VALUE; ck_src = LPIRC4M_VALUE;
} }
if((pll1psc != 0U) && (ck_src != 0U)) { if((pll1psc != 0U) && (ck_src != 0U))
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL1REN) != 0U) { {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL1REN) != 0U)
{
pll1r_freq = rcu_pll_clock_freq_cal(ck_src, pll1psc, pll1n, fracn, pll1r); pll1r_freq = rcu_pll_clock_freq_cal(ck_src, pll1psc, pll1n, fracn, pll1r);
} }
} }
@ -2402,23 +2483,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll1n = (GET_BITS(RCU_PLL1, 6U, 14U) + 1U); pll1n = (GET_BITS(RCU_PLL1, 6U, 14U) + 1U);
pll1q = (GET_BITS(RCU_PLLADDCTL, 8U, 14U) + 1U); pll1q = (GET_BITS(RCU_PLLADDCTL, 8U, 14U) + 1U);
if((RCU_PLL1FRA & RCU_PLL1FRA_PLL1FRAEN) != 0U) { if((RCU_PLL1FRA & RCU_PLL1FRA_PLL1FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL1FRA, 0U, 12U); fracn = GET_BITS(RCU_PLL1FRA, 0U, 12U);
} }
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */ /* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL); pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) { if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE; ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) { } else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq; ck_src = irc64mdiv_freq;
} else { } else {
ck_src = LPIRC4M_VALUE; ck_src = LPIRC4M_VALUE;
} }
if((pll1psc != 0U) && (ck_src != 0U)) { if((pll1psc != 0U) && (ck_src != 0U))
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL1QEN) != 0U) { {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL1QEN) != 0U)
{
pll1q_freq = rcu_pll_clock_freq_cal(ck_src, pll1psc, pll1n, fracn, pll1q); pll1q_freq = rcu_pll_clock_freq_cal(ck_src, pll1psc, pll1n, fracn, pll1q);
} }
} }
@ -2432,23 +2518,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll2n = (GET_BITS(RCU_PLL2, 6U, 14U) + 1U); pll2n = (GET_BITS(RCU_PLL2, 6U, 14U) + 1U);
pll2p = (GET_BITS(RCU_PLL2, 16U, 22U) + 1U); pll2p = (GET_BITS(RCU_PLL2, 16U, 22U) + 1U);
if((RCU_PLL2FRA & RCU_PLL2FRA_PLL2FRAEN) != 0U) { if((RCU_PLL2FRA & RCU_PLL2FRA_PLL2FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL2FRA, 0U, 12U); fracn = GET_BITS(RCU_PLL2FRA, 0U, 12U);
} }
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */ /* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL); pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) { if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE; ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) { } else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq; ck_src = irc64mdiv_freq;
} else { } else {
ck_src = LPIRC4M_VALUE; ck_src = LPIRC4M_VALUE;
} }
if((pll2psc != 0U) && (ck_src != 0U)) { if((pll2psc != 0U) && (ck_src != 0U))
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL2PEN) != 0U) { {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL2PEN) != 0U)
{
pll2p_freq = rcu_pll_clock_freq_cal(ck_src, pll2psc, pll2n, fracn, pll2p); pll2p_freq = rcu_pll_clock_freq_cal(ck_src, pll2psc, pll2n, fracn, pll2p);
} }
} }
@ -2462,23 +2553,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll2n = (GET_BITS(RCU_PLL2, 6U, 14U) + 1U); pll2n = (GET_BITS(RCU_PLL2, 6U, 14U) + 1U);
pll2r = (GET_BITS(RCU_PLL2, 24U, 30U) + 1U); pll2r = (GET_BITS(RCU_PLL2, 24U, 30U) + 1U);
if((RCU_PLL2FRA & RCU_PLL2FRA_PLL2FRAEN) != 0U) { if((RCU_PLL2FRA & RCU_PLL2FRA_PLL2FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL2FRA, 0U, 12U); fracn = GET_BITS(RCU_PLL2FRA, 0U, 12U);
} }
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */ /* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL); pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) { if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE; ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) { } else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq; ck_src = irc64mdiv_freq;
} else { } else {
ck_src = LPIRC4M_VALUE; ck_src = LPIRC4M_VALUE;
} }
if((pll2psc != 0U) && (ck_src != 0U)) { if((pll2psc != 0U) && (ck_src != 0U))
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL2REN) != 0U) { {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL2REN) != 0U)
{
pll2r_freq = rcu_pll_clock_freq_cal(ck_src, pll2psc, pll2n, fracn, pll2r); pll2r_freq = rcu_pll_clock_freq_cal(ck_src, pll2psc, pll2n, fracn, pll2r);
} }
} }
@ -2492,23 +2588,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll2n = (GET_BITS(RCU_PLL2, 6U, 14U) + 1U); pll2n = (GET_BITS(RCU_PLL2, 6U, 14U) + 1U);
pll2q = (GET_BITS(RCU_PLLADDCTL, 16U, 22U) + 1U); pll2q = (GET_BITS(RCU_PLLADDCTL, 16U, 22U) + 1U);
if((RCU_PLL2FRA & RCU_PLL2FRA_PLL2FRAEN) != 0U) { if((RCU_PLL2FRA & RCU_PLL2FRA_PLL2FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL2FRA, 0U, 12U); fracn = GET_BITS(RCU_PLL2FRA, 0U, 12U);
} }
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */ /* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL); pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) { if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE; ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) { } else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq; ck_src = irc64mdiv_freq;
} else { } else {
ck_src = LPIRC4M_VALUE; ck_src = LPIRC4M_VALUE;
} }
if((pll2psc != 0U) && (ck_src != 0U)) { if((pll2psc != 0U) && (ck_src != 0U))
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL2QEN) != 0U) { {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL2QEN) != 0U)
{
pll2q_freq = rcu_pll_clock_freq_cal(ck_src, pll2psc, pll2n, fracn, pll2q); pll2q_freq = rcu_pll_clock_freq_cal(ck_src, pll2psc, pll2n, fracn, pll2q);
} }
} }
@ -2519,9 +2620,11 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
/* calculate peripheral clock frequency */ /* calculate peripheral clock frequency */
persel = (RCU_CFG1 & RCU_CFG1_PERSEL); persel = (RCU_CFG1 & RCU_CFG1_PERSEL);
if(RCU_PERSRC_HXTAL == persel) { if(RCU_PERSRC_HXTAL == persel)
{
per_freq = HXTAL_VALUE; per_freq = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == persel) { } else if(RCU_PLLSRC_IRC64MDIV == persel)
{
per_freq = irc64mdiv_freq; per_freq = irc64mdiv_freq;
} else { } else {
per_freq = LPIRC4M_VALUE; per_freq = LPIRC4M_VALUE;
@ -2531,13 +2634,17 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
break; break;
case CK_USART0: case CK_USART0:
/* calculate USART0 clock frequency */ /* calculate USART0 clock frequency */
if(RCU_USARTSRC_APB == (RCU_CFG1 & RCU_CFG1_USART0SEL)) { if(RCU_USARTSRC_APB == (RCU_CFG1 & RCU_CFG1_USART0SEL))
{
usart_freq = apb2_freq; usart_freq = apb2_freq;
} else if(RCU_USARTSRC_AHB == (RCU_CFG1 & RCU_CFG1_USART0SEL)) { } else if(RCU_USARTSRC_AHB == (RCU_CFG1 & RCU_CFG1_USART0SEL))
{
usart_freq = ahb_freq; usart_freq = ahb_freq;
} else if(RCU_USARTSRC_LXTAL == (RCU_CFG1 & RCU_CFG1_USART0SEL)) { } else if(RCU_USARTSRC_LXTAL == (RCU_CFG1 & RCU_CFG1_USART0SEL))
{
usart_freq = LXTAL_VALUE; usart_freq = LXTAL_VALUE;
} else if(RCU_USARTSRC_IRC64MDIV == (RCU_CFG1 & RCU_CFG1_USART0SEL)) { } else if(RCU_USARTSRC_IRC64MDIV == (RCU_CFG1 & RCU_CFG1_USART0SEL))
{
usart_freq = irc64mdiv_freq; usart_freq = irc64mdiv_freq;
} else { } else {
} }
@ -2546,13 +2653,17 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
break; break;
case CK_USART1: case CK_USART1:
/* calculate USART1 clock frequency */ /* calculate USART1 clock frequency */
if((RCU_USARTSRC_APB << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL)) { if((RCU_USARTSRC_APB << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL))
{
usart_freq = apb1_freq; usart_freq = apb1_freq;
} else if((RCU_USARTSRC_AHB << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL)) { } else if((RCU_USARTSRC_AHB << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL))
{
usart_freq = ahb_freq; usart_freq = ahb_freq;
} else if((RCU_USARTSRC_LXTAL << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL)) { } else if((RCU_USARTSRC_LXTAL << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL))
{
usart_freq = LXTAL_VALUE; usart_freq = LXTAL_VALUE;
} else if((RCU_USARTSRC_IRC64MDIV << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL)) { } else if((RCU_USARTSRC_IRC64MDIV << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL))
{
usart_freq = irc64mdiv_freq; usart_freq = irc64mdiv_freq;
} else { } else {
} }
@ -2561,13 +2672,17 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
break; break;
case CK_USART2: case CK_USART2:
/* calculate USART2 clock frequency */ /* calculate USART2 clock frequency */
if((RCU_USARTSRC_APB << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL)) { if((RCU_USARTSRC_APB << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL))
{
usart_freq = apb1_freq; usart_freq = apb1_freq;
} else if((RCU_USARTSRC_AHB << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL)) { } else if((RCU_USARTSRC_AHB << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL))
{
usart_freq = ahb_freq; usart_freq = ahb_freq;
} else if((RCU_USARTSRC_LXTAL << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL)) { } else if((RCU_USARTSRC_LXTAL << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL))
{
usart_freq = LXTAL_VALUE; usart_freq = LXTAL_VALUE;
} else if((RCU_USARTSRC_IRC64MDIV << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL)) { } else if((RCU_USARTSRC_IRC64MDIV << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL))
{
usart_freq = irc64mdiv_freq; usart_freq = irc64mdiv_freq;
} else { } else {
} }
@ -2576,13 +2691,17 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
break; break;
case CK_USART5: case CK_USART5:
/* calculate USART5 clock frequency */ /* calculate USART5 clock frequency */
if((RCU_USARTSRC_APB << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL)) { if((RCU_USARTSRC_APB << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL))
{
usart_freq = apb2_freq; usart_freq = apb2_freq;
} else if((RCU_USARTSRC_AHB << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL)) { } else if((RCU_USARTSRC_AHB << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL))
{
usart_freq = ahb_freq; usart_freq = ahb_freq;
} else if((RCU_USARTSRC_LXTAL << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL)) { } else if((RCU_USARTSRC_LXTAL << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL))
{
usart_freq = LXTAL_VALUE; usart_freq = LXTAL_VALUE;
} else if((RCU_USARTSRC_IRC64MDIV << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL)) { } else if((RCU_USARTSRC_IRC64MDIV << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL))
{
usart_freq = irc64mdiv_freq; usart_freq = irc64mdiv_freq;
} else { } else {
} }
@ -2634,7 +2753,8 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
FlagStatus rcu_flag_get(rcu_flag_enum flag) FlagStatus rcu_flag_get(rcu_flag_enum flag)
{ {
/* get the rcu flag */ /* get the rcu flag */
if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag))))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -2722,7 +2842,8 @@ void rcu_interrupt_disable(rcu_int_enum interrupt)
FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
{ {
/* get the rcu interrupt flag */ /* get the rcu interrupt flag */
if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag))))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;

15
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_rspdif.c
View File

@ -281,7 +281,8 @@ void rspdif_data_read(rspdif_data_struct *data_struct)
/* get data format */ /* get data format */
data_struct->format = RSPDIF_CTL & RSPDIF_CTL_RXDF; data_struct->format = RSPDIF_CTL & RSPDIF_CTL_RXDF;
switch(data_struct->format) { switch(data_struct->format)
{
/* data format 0 */ /* data format 0 */
case RSPDIF_DATAFORMAT_LSB: case RSPDIF_DATAFORMAT_LSB:
/* the preamble type */ /* the preamble type */
@ -379,7 +380,8 @@ uint32_t rspdif_channel_status_get(void)
*/ */
FlagStatus rspdif_start_block_status_get(void) FlagStatus rspdif_start_block_status_get(void)
{ {
if(RESET != (RSPDIF_CHSTAT & RSPDIF_CHSTAT_SOB)) { if(RESET != (RSPDIF_CHSTAT & RSPDIF_CHSTAT_SOB))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -426,7 +428,8 @@ uint32_t rspdif_high_threshold_get(void)
*/ */
FlagStatus rspdif_flag_get(uint16_t flag) FlagStatus rspdif_flag_get(uint16_t flag)
{ {
if(RESET != (RSPDIF_STAT & flag)) { if(RESET != (RSPDIF_STAT & flag))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -508,7 +511,8 @@ FlagStatus rspdif_interrupt_flag_get(uint16_t int_flag)
uint32_t reg1 = RSPDIF_STAT; uint32_t reg1 = RSPDIF_STAT;
uint32_t reg2 = RSPDIF_INTEN; uint32_t reg2 = RSPDIF_INTEN;
switch(int_flag) { switch(int_flag)
{
/* RSPDIF RX buffer is not empty interrupt */ /* RSPDIF RX buffer is not empty interrupt */
case RSPDIF_INT_FLAG_RBNE: case RSPDIF_INT_FLAG_RBNE:
reg1 = reg1 & RSPDIF_STAT_RBNE; reg1 = reg1 & RSPDIF_STAT_RBNE;
@ -558,7 +562,8 @@ FlagStatus rspdif_interrupt_flag_get(uint16_t int_flag)
break; break;
} }
/*get RSPDIF interrupt flag status */ /*get RSPDIF interrupt flag status */
if((0U != reg1) && (0U != reg2)) { if((0U != reg1) && (0U != reg2))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;

121
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_rtc.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -79,7 +79,8 @@ ErrStatus rtc_deinit(void)
flag_status = RTC_STAT & RTC_STAT_WTWF; flag_status = RTC_STAT & RTC_STAT_WTWF;
} while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); } while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
if((uint32_t)RESET == flag_status) { if((uint32_t)RESET == flag_status)
{
error_status = ERROR; error_status = ERROR;
} else { } else {
RTC_CTL &= ((uint32_t)~RTC_CTL_WTCS); RTC_CTL &= ((uint32_t)~RTC_CTL_WTCS);
@ -91,7 +92,8 @@ ErrStatus rtc_deinit(void)
/* enter init mode */ /* enter init mode */
error_status = rtc_init_mode_enter(); error_status = rtc_init_mode_enter();
if(ERROR != error_status) { if(ERROR != error_status)
{
/* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition. /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition.
in order to read calendar from shadow register, not the real registers being reset */ in order to read calendar from shadow register, not the real registers being reset */
RTC_TIME = RTC_REGISTER_RESET; RTC_TIME = RTC_REGISTER_RESET;
@ -167,7 +169,8 @@ ErrStatus rtc_init(rtc_parameter_struct *rtc_initpara_struct)
/* 2nd: enter init mode */ /* 2nd: enter init mode */
error_status = rtc_init_mode_enter(); error_status = rtc_init_mode_enter();
if(ERROR != error_status) { if(ERROR != error_status)
{
RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->factor_asyn) | \ RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->factor_asyn) | \
PSC_FACTOR_S(rtc_initpara_struct->factor_syn)); PSC_FACTOR_S(rtc_initpara_struct->factor_syn));
@ -203,7 +206,8 @@ ErrStatus rtc_init_mode_enter(void)
ErrStatus error_status = ERROR; ErrStatus error_status = ERROR;
/* check whether it has been in init mode */ /* check whether it has been in init mode */
if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)) { if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF))
{
RTC_STAT |= RTC_STAT_INITM; RTC_STAT |= RTC_STAT_INITM;
/* wait until the INITF flag to be set */ /* wait until the INITF flag to be set */
@ -211,7 +215,8 @@ ErrStatus rtc_init_mode_enter(void)
flag_status = RTC_STAT & RTC_STAT_INITF; flag_status = RTC_STAT & RTC_STAT_INITF;
} while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status)); } while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status));
if((uint32_t)RESET != flag_status) { if((uint32_t)RESET != flag_status)
{
error_status = SUCCESS; error_status = SUCCESS;
} }
} else { } else {
@ -244,7 +249,8 @@ ErrStatus rtc_register_sync_wait(void)
uint32_t flag_status = RESET; uint32_t flag_status = RESET;
ErrStatus error_status = ERROR; ErrStatus error_status = ERROR;
if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)) { if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD))
{
/* disable the write protection */ /* disable the write protection */
RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY1;
RTC_WPK = RTC_UNLOCK_KEY2; RTC_WPK = RTC_UNLOCK_KEY2;
@ -257,7 +263,8 @@ ErrStatus rtc_register_sync_wait(void)
flag_status = RTC_STAT & RTC_STAT_RSYNF; flag_status = RTC_STAT & RTC_STAT_RSYNF;
} while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); } while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
if((uint32_t)RESET != flag_status) { if((uint32_t)RESET != flag_status)
{
error_status = SUCCESS; error_status = SUCCESS;
} }
@ -366,7 +373,8 @@ void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time)
ALRMTD_MN(rtc_alarm_time->alarm_minute) | \ ALRMTD_MN(rtc_alarm_time->alarm_minute) | \
ALRMTD_SC(rtc_alarm_time->alarm_second)); ALRMTD_SC(rtc_alarm_time->alarm_second));
if(RTC_ALARM0 == rtc_alarm) { if(RTC_ALARM0 == rtc_alarm)
{
RTC_ALRM0TD = (uint32_t)reg_alrmtd; RTC_ALRM0TD = (uint32_t)reg_alrmtd;
} else { } else {
@ -411,7 +419,8 @@ void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint
/* 2nd: enter init mode */ /* 2nd: enter init mode */
if(ERROR != (rtc_init_mode_enter())) if(ERROR != (rtc_init_mode_enter()))
{ {
if(RTC_ALARM0 == rtc_alarm) { if(RTC_ALARM0 == rtc_alarm)
{
RTC_ALRM0SS = mask_subsecond | subsecond; RTC_ALRM0SS = mask_subsecond | subsecond;
} else { } else {
RTC_ALRM1SS = mask_subsecond | subsecond; RTC_ALRM1SS = mask_subsecond | subsecond;
@ -444,7 +453,8 @@ void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time)
uint32_t reg_alrmtd = 0U; uint32_t reg_alrmtd = 0U;
/* get the value of RTC_ALRM0TD register */ /* get the value of RTC_ALRM0TD register */
if(RTC_ALARM0 == rtc_alarm) { if(RTC_ALARM0 == rtc_alarm)
{
reg_alrmtd = RTC_ALRM0TD; reg_alrmtd = RTC_ALRM0TD;
} else { } else {
reg_alrmtd = RTC_ALRM1TD; reg_alrmtd = RTC_ALRM1TD;
@ -467,7 +477,8 @@ void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time)
*/ */
uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm) uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm)
{ {
if(RTC_ALARM0 == rtc_alarm) { if(RTC_ALARM0 == rtc_alarm)
{
return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC)); return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC));
} else { } else {
return ((uint32_t)(RTC_ALRM1SS & RTC_ALRM1SS_SSC)); return ((uint32_t)(RTC_ALRM1SS & RTC_ALRM1SS_SSC));
@ -486,7 +497,8 @@ void rtc_alarm_enable(uint8_t rtc_alarm)
RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY1;
RTC_WPK = RTC_UNLOCK_KEY2; RTC_WPK = RTC_UNLOCK_KEY2;
if(RTC_ALARM0 == rtc_alarm) { if(RTC_ALARM0 == rtc_alarm)
{
RTC_CTL |= RTC_CTL_ALRM0EN; RTC_CTL |= RTC_CTL_ALRM0EN;
} else { } else {
RTC_CTL |= RTC_CTL_ALRM1EN; RTC_CTL |= RTC_CTL_ALRM1EN;
@ -513,7 +525,8 @@ ErrStatus rtc_alarm_disable(uint8_t rtc_alarm)
RTC_WPK = RTC_UNLOCK_KEY2; RTC_WPK = RTC_UNLOCK_KEY2;
/* clear the state of alarm */ /* clear the state of alarm */
if(RTC_ALARM0 == rtc_alarm) { if(RTC_ALARM0 == rtc_alarm)
{
RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN);
/* wait until ALRM0WF flag to be set after the alarm is disabled */ /* wait until ALRM0WF flag to be set after the alarm is disabled */
do { do {
@ -527,7 +540,8 @@ ErrStatus rtc_alarm_disable(uint8_t rtc_alarm)
} while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); } while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
} }
if((uint32_t)RESET != flag_status) { if((uint32_t)RESET != flag_status)
{
error_status = SUCCESS; error_status = SUCCESS;
} }
@ -600,7 +614,8 @@ void rtc_timestamp_internalevent_config(uint32_t mode)
RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY1;
RTC_WPK = RTC_UNLOCK_KEY2; RTC_WPK = RTC_UNLOCK_KEY2;
if(mode == RTC_ITSEN_ENABLE) { if(mode == RTC_ITSEN_ENABLE)
{
RTC_CTL |= RTC_CTL_ITSEN; RTC_CTL |= RTC_CTL_ITSEN;
} else { } else {
RTC_CTL &= ~(uint32_t)RTC_CTL_ITSEN; RTC_CTL &= ~(uint32_t)RTC_CTL_ITSEN;
@ -689,11 +704,13 @@ void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper)
RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT; RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT;
/* the tamper source is voltage level detection */ /* the tamper source is voltage level detection */
if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE) { if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE)
{
RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT); RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT);
/* check if the tamper pin need precharge, if need, then configure the precharge time */ /* check if the tamper pin need precharge, if need, then configure the precharge time */
if(DISABLE == rtc_tamper->tamper_precharge_enable) { if(DISABLE == rtc_tamper->tamper_precharge_enable)
{
RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU;
} else { } else {
RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_precharge_time); RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_precharge_time);
@ -704,18 +721,21 @@ void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper)
/* configure the tamper trigger */ /* configure the tamper trigger */
RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS));
if(RTC_TAMPER_TRIGGER_LEVEL_LOW != rtc_tamper->tamper_trigger) { if(RTC_TAMPER_TRIGGER_LEVEL_LOW != rtc_tamper->tamper_trigger)
{
RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS); RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS);
} }
} else { } else {
/* configure the tamper trigger */ /* configure the tamper trigger */
RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS));
if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger) { if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger)
{
RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS); RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS);
} }
} }
RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS;
if(DISABLE != rtc_tamper->tamper_with_timestamp) { if(DISABLE != rtc_tamper->tamper_with_timestamp)
{
/* the tamper event also cause a time-stamp event */ /* the tamper event also cause a time-stamp event */
RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS; RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS;
} }
@ -758,7 +778,8 @@ void rtc_output_pin_select(uint32_t outputpin)
/* enter init mode */ /* enter init mode */
error_status = rtc_init_mode_enter(); error_status = rtc_init_mode_enter();
if(ERROR != error_status) { if(ERROR != error_status)
{
RTC_CFG &= (uint32_t)(~RTC_CFG_OUT2EN); RTC_CFG &= (uint32_t)(~RTC_CFG_OUT2EN);
RTC_CFG |= (uint32_t)(outputpin); RTC_CFG |= (uint32_t)(outputpin);
/* exit init mode */ /* exit init mode */
@ -872,7 +893,8 @@ ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus)
/* check if the function of reference clock detection is disabled */ /* check if the function of reference clock detection is disabled */
temp = RTC_CTL & RTC_CTL_REFEN; temp = RTC_CTL & RTC_CTL_REFEN;
if((RESET == flag_status) && (RESET == temp)) { if((RESET == flag_status) && (RESET == temp))
{
RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus)); RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus));
error_status = rtc_register_sync_wait(); error_status = rtc_register_sync_wait();
} }
@ -936,7 +958,8 @@ ErrStatus rtc_refclock_detection_enable(void)
/* enter init mode */ /* enter init mode */
error_status = rtc_init_mode_enter(); error_status = rtc_init_mode_enter();
if(ERROR != error_status) { if(ERROR != error_status)
{
RTC_CTL |= (uint32_t)RTC_CTL_REFEN; RTC_CTL |= (uint32_t)RTC_CTL_REFEN;
/* exit init mode */ /* exit init mode */
rtc_init_mode_exit(); rtc_init_mode_exit();
@ -965,7 +988,8 @@ ErrStatus rtc_refclock_detection_disable(void)
/* enter init mode */ /* enter init mode */
error_status = rtc_init_mode_enter(); error_status = rtc_init_mode_enter();
if(ERROR != error_status) { if(ERROR != error_status)
{
RTC_CTL &= (uint32_t)~RTC_CTL_REFEN; RTC_CTL &= (uint32_t)~RTC_CTL_REFEN;
/* exit init mode */ /* exit init mode */
rtc_init_mode_exit(); rtc_init_mode_exit();
@ -1017,7 +1041,8 @@ ErrStatus rtc_wakeup_disable(void)
flag_status = RTC_STAT & RTC_STAT_WTWF; flag_status = RTC_STAT & RTC_STAT_WTWF;
} while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); } while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
if((uint32_t)RESET == flag_status) { if((uint32_t)RESET == flag_status)
{
error_status = ERROR; error_status = ERROR;
} else { } else {
error_status = SUCCESS; error_status = SUCCESS;
@ -1057,7 +1082,8 @@ ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock)
flag_status = RTC_STAT & RTC_STAT_WTWF; flag_status = RTC_STAT & RTC_STAT_WTWF;
} while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); } while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
if((uint32_t)RESET == flag_status) { if((uint32_t)RESET == flag_status)
{
error_status = ERROR; error_status = ERROR;
} else { } else {
RTC_CTL &= (uint32_t)~ RTC_CTL_WTCS; RTC_CTL &= (uint32_t)~ RTC_CTL_WTCS;
@ -1092,7 +1118,8 @@ ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer)
flag_status = RTC_STAT & RTC_STAT_WTWF; flag_status = RTC_STAT & RTC_STAT_WTWF;
} while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); } while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
if((uint32_t)RESET == flag_status) { if((uint32_t)RESET == flag_status)
{
error_status = ERROR; error_status = ERROR;
} else { } else {
RTC_WUT = (uint32_t)wakeup_timer; RTC_WUT = (uint32_t)wakeup_timer;
@ -1144,7 +1171,8 @@ ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t
flag_status = RTC_STAT & RTC_STAT_SCPF; flag_status = RTC_STAT & RTC_STAT_SCPF;
} while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); } while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
if((uint32_t)RESET == flag_status) { if((uint32_t)RESET == flag_status)
{
RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus)); RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus));
error_status = SUCCESS; error_status = SUCCESS;
} }
@ -1232,7 +1260,8 @@ FlagStatus rtc_flag_get(uint32_t flag)
{ {
FlagStatus flag_state = RESET; FlagStatus flag_state = RESET;
if((uint32_t)RESET != (RTC_STAT & flag)) { if((uint32_t)RESET != (RTC_STAT & flag))
{
flag_state = SET; flag_state = SET;
} }
return flag_state; return flag_state;
@ -1257,9 +1286,9 @@ void rtc_flag_clear(uint32_t flag)
/* disable the write protection */ /* disable the write protection */
RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY1;
RTC_WPK = RTC_UNLOCK_KEY2; RTC_WPK = RTC_UNLOCK_KEY2;
RTC_STAT &= (uint32_t)(~flag); RTC_STAT &= (uint32_t)(~flag);
/* enable the write protection */ /* enable the write protection */
RTC_WPK = RTC_LOCK_KEY; RTC_WPK = RTC_LOCK_KEY;
} }

60
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_rtdec.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -45,12 +45,14 @@ OF SUCH DAMAGE.
*/ */
void rtdec_deinit(uint32_t rtdec_periph) void rtdec_deinit(uint32_t rtdec_periph)
{ {
if(RTDEC0 == rtdec_periph){ if(RTDEC0 == rtdec_periph)
{
/* reset RTDEC0 */ /* reset RTDEC0 */
rcu_periph_reset_enable(RCU_RTDEC0RST); rcu_periph_reset_enable(RCU_RTDEC0RST);
rcu_periph_reset_disable(RCU_RTDEC0RST); rcu_periph_reset_disable(RCU_RTDEC0RST);
} }
if(RTDEC1 == rtdec_periph) { if(RTDEC1 == rtdec_periph)
{
/* reset RTDEC1 */ /* reset RTDEC1 */
rcu_periph_reset_enable(RCU_RTDEC1RST); rcu_periph_reset_enable(RCU_RTDEC1RST);
rcu_periph_reset_disable(RCU_RTDEC1RST); rcu_periph_reset_disable(RCU_RTDEC1RST);
@ -79,7 +81,7 @@ void rtdec_struct_para_init(rtdec_parameter_struct* rtdec_struct)
\brief initialize RTDEC \brief initialize RTDEC
\param[in] rtdec_periph: RTDECx(x = 0, 1) \param[in] rtdec_periph: RTDECx(x = 0, 1)
\param[in] rtdec_area: RTDEC_AREAx(x = 0, 1, 2, 3) \param[in] rtdec_area: RTDEC_AREAx(x = 0, 1, 2, 3)
\param[in] rtdec_struct: RTDEC parameter initialization stuct members of the structure \param[in] rtdec_struct: RTDEC parameter initialization stuct members of the structure
and the member values are shown as below: and the member values are shown as below:
access_mode: RTDEC_MODE_CODE_ACCESS, RTDEC_MODE_DATA_ACCESS, RTDEC_MODE_BOTH_ACCESS access_mode: RTDEC_MODE_CODE_ACCESS, RTDEC_MODE_DATA_ACCESS, RTDEC_MODE_BOTH_ACCESS
key_crc: CRC value of area key key_crc: CRC value of area key
@ -113,7 +115,8 @@ ErrStatus rtdec_init(uint32_t rtdec_periph, uint32_t rtdec_area, rtdec_parameter
/* check the key CRC */ /* check the key CRC */
key_crc_reg = (uint8_t)GET_BITS(RTDEC_ARE_CFG(rtdec_periph, rtdec_area), 8U, 15U); key_crc_reg = (uint8_t)GET_BITS(RTDEC_ARE_CFG(rtdec_periph, rtdec_area), 8U, 15U);
if(key_crc_reg != rtdec_struct->key_crc){ if(key_crc_reg != rtdec_struct->key_crc)
{
return ERROR; return ERROR;
} }
@ -154,7 +157,7 @@ void rtdec_config(uint32_t rtdec_periph, uint32_t rtdec_area, uint8_t access_mod
\brief configure RTDEC key or register lock \brief configure RTDEC key or register lock
\param[in] rtdec_periph: RTDECx(x = 0, 1) \param[in] rtdec_periph: RTDECx(x = 0, 1)
\param[in] rtdec_area: RTDEC_AREAx(x = 0, 1, 2, 3) \param[in] rtdec_area: RTDEC_AREAx(x = 0, 1, 2, 3)
\param[in]: lock_type: key lock or register lock \param[in]: lock_type: key lock or register lock
\arg: RTDEC_ARE_CFG_LK: register lock \arg: RTDEC_ARE_CFG_LK: register lock
\arg: RTDEC_ARE_K_LK: key lock \arg: RTDEC_ARE_K_LK: key lock
\param[out] none \param[out] none
@ -270,7 +273,8 @@ void rtdec_disable(uint32_t rtdec_periph, uint32_t rtdec_area)
*/ */
FlagStatus rtdec_flag_get(uint32_t rtdec_periph, uint32_t flag) FlagStatus rtdec_flag_get(uint32_t rtdec_periph, uint32_t flag)
{ {
if(RESET != (RTDEC_INTF(rtdec_periph) & flag)){ if(RESET != (RTDEC_INTF(rtdec_periph) & flag))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -278,7 +282,7 @@ FlagStatus rtdec_flag_get(uint32_t rtdec_periph, uint32_t flag)
} }
/*! /*!
\brief clear RTDEC error flag \brief clear RTDEC error flag
\param[in] rtdec_periph: RTDECx(x = 0, 1) \param[in] rtdec_periph: RTDECx(x = 0, 1)
\param[in]: flag: error flag \param[in]: flag: error flag
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
@ -310,7 +314,7 @@ void rtdec_interrupt_enable(uint32_t rtdec_periph, uint32_t interrupt)
} }
/*! /*!
\brief disable RTDEC interrupt \brief disable RTDEC interrupt
\param[in] rtdec_periph: RTDECx(x = 0, 1) \param[in] rtdec_periph: RTDECx(x = 0, 1)
\param[in]: interrupt: interrupt type \param[in]: interrupt: interrupt type
one or more parameters can be selected which is shown as below: one or more parameters can be selected which is shown as below:
@ -326,7 +330,7 @@ void rtdec_interrupt_disable(uint32_t rtdec_periph, uint32_t interrupt)
} }
/*! /*!
\brief get RTDEC interrupt flag \brief get RTDEC interrupt flag
\param[in] rtdec_periph: RTDECx(x = 0, 1) \param[in] rtdec_periph: RTDECx(x = 0, 1)
\param[in]: int_flag: interrupt flag \param[in]: int_flag: interrupt flag
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
@ -340,7 +344,8 @@ FlagStatus rtdec_interrupt_flag_get(uint32_t rtdec_periph, uint32_t int_flag)
{ {
uint32_t interrupt_enable = 0U, interrupt_flag = 0U; uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
switch(int_flag){ switch(int_flag)
{
/* RTDEC security error interrupt */ /* RTDEC security error interrupt */
case RTDEC_INT_FLAG_SEC_ERROR: case RTDEC_INT_FLAG_SEC_ERROR:
interrupt_flag = RTDEC_INTF(rtdec_periph) & int_flag; interrupt_flag = RTDEC_INTF(rtdec_periph) & int_flag;
@ -360,7 +365,8 @@ FlagStatus rtdec_interrupt_flag_get(uint32_t rtdec_periph, uint32_t int_flag)
break; break;
} }
/* get RTDEC interrupt flag status */ /* get RTDEC interrupt flag status */
if(interrupt_flag && interrupt_enable){ if(interrupt_flag && interrupt_enable)
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -368,7 +374,7 @@ FlagStatus rtdec_interrupt_flag_get(uint32_t rtdec_periph, uint32_t int_flag)
} }
/*! /*!
\brief clear RTDEC interrupt flag \brief clear RTDEC interrupt flag
\param[in] rtdec_periph: RTDECx(x = 0, 1) \param[in] rtdec_periph: RTDECx(x = 0, 1)
\param[in]: int_flag: interrupt flag \param[in]: int_flag: interrupt flag
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:

26
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_sai.c
View File

@ -47,7 +47,8 @@ OF SUCH DAMAGE.
*/ */
void sai_deinit(uint32_t sai_periph) void sai_deinit(uint32_t sai_periph)
{ {
switch(sai_periph) { switch(sai_periph)
{
case SAI0: case SAI0:
/* reset SAI0 */ /* reset SAI0 */
rcu_periph_reset_enable(RCU_SAI0RST); rcu_periph_reset_enable(RCU_SAI0RST);
@ -293,7 +294,7 @@ void sai_sdoutput_config(uint32_t sai_periph, uint32_t block, uint32_t sdout)
\retval none \retval none
*/ */
void sai_monomode_config(uint32_t sai_periph, uint32_t block, uint32_t mono) void sai_monomode_config(uint32_t sai_periph, uint32_t block, uint32_t mono)
{ {
SAI_CFG0(sai_periph, block) &= ~SAI_CFG0_MONO; SAI_CFG0(sai_periph, block) &= ~SAI_CFG0_MONO;
SAI_CFG0(sai_periph, block) |= mono ; SAI_CFG0(sai_periph, block) |= mono ;
} }
@ -440,15 +441,20 @@ sai_fifo_state_enum sai_fifo_status_get(uint32_t sai_periph, uint32_t block)
{ {
sai_fifo_state_enum sai_fifo_state = FIFO_EMPTY; sai_fifo_state_enum sai_fifo_state = FIFO_EMPTY;
if(SAI_FIFO_STAT_EMPTY == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT)) { if(SAI_FIFO_STAT_EMPTY == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT))
{
sai_fifo_state = FIFO_EMPTY; sai_fifo_state = FIFO_EMPTY;
} else if(SAI_FIFO_STAT_QUARTER == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT)) { } else if(SAI_FIFO_STAT_QUARTER == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT))
{
sai_fifo_state = FIFO_EMPTY_TO_1_4_FULL; sai_fifo_state = FIFO_EMPTY_TO_1_4_FULL;
} else if(SAI_FIFO_STAT_HALF == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT)) { } else if(SAI_FIFO_STAT_HALF == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT))
{
sai_fifo_state = FIFO_1_4_FULL_TO_1_2_FULL; sai_fifo_state = FIFO_1_4_FULL_TO_1_2_FULL;
} else if(SAI_FIFO_STAT_THREE_QUARTER == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT)) { } else if(SAI_FIFO_STAT_THREE_QUARTER == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT))
{
sai_fifo_state = FIFO_1_2_FULL_TO_3_4_FULL; sai_fifo_state = FIFO_1_2_FULL_TO_3_4_FULL;
} else if(SAI_FIFO_STAT_NEARFULL == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT)) { } else if(SAI_FIFO_STAT_NEARFULL == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT))
{
sai_fifo_state = FIFO_3_4_FULL_TO_FULL; sai_fifo_state = FIFO_3_4_FULL_TO_FULL;
} else { } else {
sai_fifo_state = FIFO_FULL; sai_fifo_state = FIFO_FULL;
@ -713,7 +719,8 @@ FlagStatus sai_interrupt_flag_get(uint32_t sai_periph, uint32_t block, uint32_t
{ {
uint32_t inten = 0U; uint32_t inten = 0U;
inten = SAI_INTEN(sai_periph, block) & interrupt; inten = SAI_INTEN(sai_periph, block) & interrupt;
if((RESET != (SAI_STAT(sai_periph, block) & interrupt)) && (RESET != inten)) { if((RESET != (SAI_STAT(sai_periph, block) & interrupt)) && (RESET != inten))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -762,7 +769,8 @@ void sai_interrupt_flag_clear(uint32_t sai_periph, uint32_t block, uint32_t inte
*/ */
FlagStatus sai_flag_get(uint32_t sai_periph, uint32_t block, uint32_t flag) FlagStatus sai_flag_get(uint32_t sai_periph, uint32_t block, uint32_t flag)
{ {
if(RESET != (SAI_STAT(sai_periph, block) & flag)) { if(RESET != (SAI_STAT(sai_periph, block) & flag))
{
return SET; return SET;
} else { } else {
return RESET; return RESET;

12
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_sdio.c
View File

@ -45,7 +45,8 @@ OF SUCH DAMAGE.
*/ */
void sdio_deinit(uint32_t sdio_periph) void sdio_deinit(uint32_t sdio_periph)
{ {
switch(sdio_periph) { switch(sdio_periph)
{
/* reset SDIO0 */ /* reset SDIO0 */
case SDIO0: case SDIO0:
rcu_periph_reset_enable(RCU_SDIO0RST); rcu_periph_reset_enable(RCU_SDIO0RST);
@ -375,7 +376,8 @@ uint32_t sdio_response_get(uint32_t sdio_periph, uint32_t sdio_responsex)
uint32_t resp_content = 0U; uint32_t resp_content = 0U;
/* get the content of the last response */ /* get the content of the last response */
switch(sdio_responsex) { switch(sdio_responsex)
{
case SDIO_RESPONSE0: case SDIO_RESPONSE0:
resp_content = SDIO_RESP0(sdio_periph); resp_content = SDIO_RESP0(sdio_periph);
break; break;
@ -725,7 +727,8 @@ void sdio_idma_disable(uint32_t sdio_periph)
FlagStatus sdio_flag_get(uint32_t sdio_periph, uint32_t flag) FlagStatus sdio_flag_get(uint32_t sdio_periph, uint32_t flag)
{ {
FlagStatus temp_flag = RESET; FlagStatus temp_flag = RESET;
if(RESET != (SDIO_STAT(sdio_periph) & flag)) { if(RESET != (SDIO_STAT(sdio_periph) & flag))
{
temp_flag = SET; temp_flag = SET;
} }
return temp_flag; return temp_flag;
@ -873,7 +876,8 @@ void sdio_interrupt_disable(uint32_t sdio_periph, uint32_t int_flag)
FlagStatus sdio_interrupt_flag_get(uint32_t sdio_periph, uint32_t int_flag) FlagStatus sdio_interrupt_flag_get(uint32_t sdio_periph, uint32_t int_flag)
{ {
FlagStatus temp_flag = RESET; FlagStatus temp_flag = RESET;
if(RESET != (SDIO_STAT(sdio_periph) & int_flag)) { if(RESET != (SDIO_STAT(sdio_periph) & int_flag))
{
temp_flag = SET; temp_flag = SET;
} }
return temp_flag; return temp_flag;

371
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_spi.c
View File

@ -8,40 +8,40 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
#include "gd32h7xx_spi.h" #include "gd32h7xx_spi.h"
#define SPI_ERROR_HANDLE(s) do{}while(1) #define SPI_ERROR_HANDLE(s) do{}while(1)
/* external clock value to ckin */ /* external clock value to ckin */
#define I2S_CKIN_VALUE ((uint32_t)0U) #define I2S_CKIN_VALUE ((uint32_t)0U)
/* SPI fifo data size */ /* SPI fifo data size */
#define SPI_DATASIZE_SUBTRACT_ONE ((uint8_t)0x01U) #define SPI_DATASIZE_SUBTRACT_ONE ((uint8_t)0x01U)
/* SPI/I2S parameter initialization mask */ /* SPI/I2S parameter initialization mask */
#define SPI_INIT_MASK ((uint32_t)0x00003040U) #define SPI_INIT_MASK ((uint32_t)0x00003040U)
#define I2S_INIT_MASK ((uint32_t)0xFFFFF047U) #define I2S_INIT_MASK ((uint32_t)0xFFFFF047U)
@ -54,17 +54,18 @@ OF SUCH DAMAGE.
#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /*!< I2S clock multiplication mask */ #define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /*!< I2S clock multiplication mask */
#define I2S_CLOCK_DIV_MASK ((uint32_t)0x00030000U) /*!< I2S clock division mask */ #define I2S_CLOCK_DIV_MASK ((uint32_t)0x00030000U) /*!< I2S clock division mask */
/*! /*!
\brief reset SPI and I2S \brief reset SPI and I2S
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void spi_i2s_deinit(uint32_t spi_periph) void spi_i2s_deinit(uint32_t spi_periph)
{ {
switch(spi_periph){ switch(spi_periph)
{
case SPI0: case SPI0:
/* reset SPI0 and I2S0 */ /* reset SPI0 and I2S0 */
rcu_periph_reset_enable(RCU_SPI0RST); rcu_periph_reset_enable(RCU_SPI0RST);
@ -84,7 +85,7 @@ void spi_i2s_deinit(uint32_t spi_periph)
/* reset SPI3 */ /* reset SPI3 */
rcu_periph_reset_enable(RCU_SPI3RST); rcu_periph_reset_enable(RCU_SPI3RST);
rcu_periph_reset_disable(RCU_SPI3RST); rcu_periph_reset_disable(RCU_SPI3RST);
break; break;
case SPI4: case SPI4:
/* reset SPI4 */ /* reset SPI4 */
rcu_periph_reset_enable(RCU_SPI4RST); rcu_periph_reset_enable(RCU_SPI4RST);
@ -94,7 +95,7 @@ void spi_i2s_deinit(uint32_t spi_periph)
/* reset SPI5 and I2S5 */ /* reset SPI5 and I2S5 */
rcu_periph_reset_enable(RCU_SPI5RST); rcu_periph_reset_enable(RCU_SPI5RST);
rcu_periph_reset_disable(RCU_SPI5RST); rcu_periph_reset_disable(RCU_SPI5RST);
break; break;
default : default :
break; break;
} }
@ -121,7 +122,7 @@ void spi_struct_para_init(spi_parameter_struct *spi_struct)
/*! /*!
\brief initialize SPI parameter \brief initialize SPI parameter
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] spi_struct: SPI parameter initialization stuct members of the structure \param[in] spi_struct: SPI parameter initialization stuct members of the structure
and the member values are shown as below: and the member values are shown as below:
device_mode: SPI_MASTER, SPI_SLAVE device_mode: SPI_MASTER, SPI_SLAVE
trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY,
@ -145,7 +146,7 @@ void spi_struct_para_init(spi_parameter_struct *spi_struct)
\retval none \retval none
*/ */
void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct)
{ {
uint32_t reg1 = 0U, reg2 = 0U; uint32_t reg1 = 0U, reg2 = 0U;
reg1 = SPI_CFG0(spi_periph); reg1 = SPI_CFG0(spi_periph);
reg2 = SPI_CFG1(spi_periph); reg2 = SPI_CFG1(spi_periph);
@ -169,7 +170,7 @@ void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct)
/* write to SPI_CFG0 & SPI_CFG1 register */ /* write to SPI_CFG0 & SPI_CFG1 register */
SPI_CFG0(spi_periph) = (uint32_t)reg1; SPI_CFG0(spi_periph) = (uint32_t)reg1;
SPI_CFG1(spi_periph) = (uint32_t)reg2; SPI_CFG1(spi_periph) = (uint32_t)reg2;
SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL);
} }
@ -185,7 +186,7 @@ void spi_enable(uint32_t spi_periph)
} }
/*! /*!
\brief disable SPI \brief disable SPI
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[out] none \param[out] none
\retval none \retval none
@ -196,7 +197,7 @@ void spi_disable(uint32_t spi_periph)
} }
/*! /*!
\brief initialize I2S parameter \brief initialize I2S parameter
\param[in] spi_periph: SPIx(x=0,1,2,5) \param[in] spi_periph: SPIx(x=0,1,2,5)
\param[in] i2s_mode: I2S operation mode \param[in] i2s_mode: I2S operation mode
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
@ -225,7 +226,7 @@ void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uin
reg &= I2S_INIT_MASK; reg &= I2S_INIT_MASK;
/* enable I2S mode */ /* enable I2S mode */
reg |= (uint32_t)SPI_I2SCTL_I2SSEL; reg |= (uint32_t)SPI_I2SCTL_I2SSEL;
/* select I2S mode */ /* select I2S mode */
reg |= (uint32_t)i2s_mode; reg |= (uint32_t)i2s_mode;
/* select I2S standard */ /* select I2S standard */
@ -238,7 +239,7 @@ void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uin
} }
/*! /*!
\brief configure I2S prescaler \brief configure I2S prescaler
\param[in] spi_periph: SPIx(x=0,1,2,5) \param[in] spi_periph: SPIx(x=0,1,2,5)
\param[in] i2s_audiosample: I2S audio sample rate \param[in] i2s_audiosample: I2S audio sample rate
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
@ -271,73 +272,82 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_
uint32_t i2sclock = 0U; uint32_t i2sclock = 0U;
uint32_t i2s_clk_sel = 0U; uint32_t i2s_clk_sel = 0U;
uint32_t spi0_2_clksel[5] = {CK_PLL0Q, CK_PLL1P, CK_PLL2P, I2S_CKIN_VALUE, CK_PER}; uint32_t spi0_2_clksel[5] = {CK_PLL0Q, CK_PLL1P, CK_PLL2P, I2S_CKIN_VALUE, CK_PER};
uint32_t spi3_5_clksel[7] = {CK_APB2, CK_PLL1Q, CK_PLL2Q, CK_IRC64MDIV, CK_LPIRC4M, CK_HXTAL, I2S_CKIN_VALUE}; uint32_t spi3_5_clksel[7] = {CK_APB2, CK_PLL1Q, CK_PLL2Q, CK_IRC64MDIV, CK_LPIRC4M, CK_HXTAL, I2S_CKIN_VALUE};
/* judge whether the audiosample is 0 */ /* judge whether the audiosample is 0 */
if(0U == i2s_audiosample){ if(0U == i2s_audiosample)
{
SPI_ERROR_HANDLE("the parameter can not be 0 \r\n"); SPI_ERROR_HANDLE("the parameter can not be 0 \r\n");
} }
/* get the I2S clock source */ /* get the I2S clock source */
switch(spi_periph){ switch(spi_periph)
case SPI0: {
case SPI0:
/* I2S0 clock source selection */ /* I2S0 clock source selection */
i2s_clk_sel = RCU_CFG5 & RCU_CFG5_SPI0SEL; i2s_clk_sel = RCU_CFG5 & RCU_CFG5_SPI0SEL;
if(3U == i2s_clk_sel){ if(3U == i2s_clk_sel)
{
i2sclock = spi0_2_clksel[i2s_clk_sel]; i2sclock = spi0_2_clksel[i2s_clk_sel];
}else{ }else{
i2sclock = rcu_clock_freq_get((rcu_clock_freq_enum)spi0_2_clksel[i2s_clk_sel]); i2sclock = rcu_clock_freq_get((rcu_clock_freq_enum)spi0_2_clksel[i2s_clk_sel]);
} }
break; break;
case SPI1: case SPI1:
/* I2S1 clock source selection */ /* I2S1 clock source selection */
i2s_clk_sel = (RCU_CFG5 & RCU_CFG5_SPI1SEL) >> 4U; i2s_clk_sel = (RCU_CFG5 & RCU_CFG5_SPI1SEL) >> 4U;
if(3U == i2s_clk_sel){ if(3U == i2s_clk_sel)
{
i2sclock = spi0_2_clksel[i2s_clk_sel]; i2sclock = spi0_2_clksel[i2s_clk_sel];
}else{ }else{
i2sclock = rcu_clock_freq_get((rcu_clock_freq_enum)spi0_2_clksel[i2s_clk_sel]); i2sclock = rcu_clock_freq_get((rcu_clock_freq_enum)spi0_2_clksel[i2s_clk_sel]);
} }
break; break;
case SPI2: case SPI2:
/* I2S2 clock source selection */ /* I2S2 clock source selection */
i2s_clk_sel = (RCU_CFG5 & RCU_CFG5_SPI2SEL) >> 8U; i2s_clk_sel = (RCU_CFG5 & RCU_CFG5_SPI2SEL) >> 8U;
if(3U == i2s_clk_sel){ if(3U == i2s_clk_sel)
{
i2sclock = spi0_2_clksel[i2s_clk_sel]; i2sclock = spi0_2_clksel[i2s_clk_sel];
}else{ }else{
i2sclock = rcu_clock_freq_get((rcu_clock_freq_enum)spi0_2_clksel[i2s_clk_sel]); i2sclock = rcu_clock_freq_get((rcu_clock_freq_enum)spi0_2_clksel[i2s_clk_sel]);
} }
break; break;
case SPI5: case SPI5:
/* I2S5 clock source selection */ /* I2S5 clock source selection */
i2s_clk_sel = (RCU_CFG5 & RCU_CFG5_SPI5SEL) >> 20U; i2s_clk_sel = (RCU_CFG5 & RCU_CFG5_SPI5SEL) >> 20U;
if(3U > i2s_clk_sel){ if(3U > i2s_clk_sel)
{
i2sclock = rcu_clock_freq_get((rcu_clock_freq_enum)spi3_5_clksel[i2s_clk_sel]); i2sclock = rcu_clock_freq_get((rcu_clock_freq_enum)spi3_5_clksel[i2s_clk_sel]);
}else{ }else{
i2sclock = spi3_5_clksel[i2s_clk_sel]; i2sclock = spi3_5_clksel[i2s_clk_sel];
} }
break; break;
default : default :
break; break;
} }
/* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
if(I2S_MCKOUT_ENABLE == i2s_mckout){ if(I2S_MCKOUT_ENABLE == i2s_mckout)
{
clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample); clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample);
}else{ }else{
if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat){ if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat)
{
clks = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample); clks = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample);
}else{ }else{
clks = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample); clks = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample);
} }
} }
/* remove the floating point */ /* remove the floating point */
clks = (clks + 5U) / 10U; clks = (clks + 5U) / 10U;
i2sof = (clks & 0x00000001U); i2sof = (clks & 0x00000001U);
i2sdiv = ((clks - i2sof) / 2U); i2sdiv = ((clks - i2sof) / 2U);
/* set the default values */ /* set the default values */
if((i2sdiv < 2U) || (i2sdiv > 255U)){ if((i2sdiv < 2U) || (i2sdiv > 255U))
{
i2sdiv = 2U; i2sdiv = 2U;
i2sof = 0U; i2sof = 0U;
} }
@ -353,7 +363,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_
} }
/*! /*!
\brief enable I2S \brief enable I2S
\param[in] spi_periph: SPIx(x=0,1,2,5) \param[in] spi_periph: SPIx(x=0,1,2,5)
\param[out] none \param[out] none
\retval none \retval none
@ -364,7 +374,7 @@ void i2s_enable(uint32_t spi_periph)
} }
/*! /*!
\brief disable I2S \brief disable I2S
\param[in] spi_periph: SPIx(x=0,1,2,5) \param[in] spi_periph: SPIx(x=0,1,2,5)
\param[out] none \param[out] none
\retval none \retval none
@ -375,7 +385,7 @@ void i2s_disable(uint32_t spi_periph)
} }
/*! /*!
\brief SPI MOSI and MISO pin swap \brief SPI MOSI and MISO pin swap
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] io_cfg: SPI IO swap config \param[in] io_cfg: SPI IO swap config
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
@ -386,60 +396,61 @@ void i2s_disable(uint32_t spi_periph)
*/ */
void spi_io_config(uint32_t spi_periph, uint32_t io_cfg) void spi_io_config(uint32_t spi_periph, uint32_t io_cfg)
{ {
if(SPI_IO_SWAP == io_cfg){ if(SPI_IO_SWAP == io_cfg)
SPI_CFG1(spi_periph) |= (uint32_t)SPI_CFG1_SWPMIO; {
SPI_CFG1(spi_periph) |= (uint32_t)SPI_CFG1_SWPMIO;
} }
else{ else{
SPI_CFG1(spi_periph) &= (uint32_t)(~SPI_CFG1_SWPMIO); SPI_CFG1(spi_periph) &= (uint32_t)(~SPI_CFG1_SWPMIO);
} }
} }
/*! /*!
\brief set delay between active edge of NSS and start transfer or receive data in SPI master mode \brief set delay between active edge of NSS and start transfer or receive data in SPI master mode
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] delay_cycle: SPI_NSS_IDLENESS_00CYCLE, SPI_NSS_IDLENESS_01CYCLE, SPI_NSS_IDLENESS_02CYCLE, \param[in] delay_cycle: SPI_NSS_IDLENESS_00CYCLE, SPI_NSS_IDLENESS_01CYCLE, SPI_NSS_IDLENESS_02CYCLE,
SPI_NSS_IDLENESS_03CYCLE, SPI_NSS_IDLENESS_04CYCLE, SPI_NSS_IDLENESS_05CYCLE, SPI_NSS_IDLENESS_03CYCLE, SPI_NSS_IDLENESS_04CYCLE, SPI_NSS_IDLENESS_05CYCLE,
SPI_NSS_IDLENESS_06CYCLE, SPI_NSS_IDLENESS_07CYCLE, SPI_NSS_IDLENESS_08CYCLE, SPI_NSS_IDLENESS_06CYCLE, SPI_NSS_IDLENESS_07CYCLE, SPI_NSS_IDLENESS_08CYCLE,
SPI_NSS_IDLENESS_09CYCLE, SPI_NSS_IDLENESS_10CYCLE, SPI_NSS_IDLENESS_11CYCLE, SPI_NSS_IDLENESS_09CYCLE, SPI_NSS_IDLENESS_10CYCLE, SPI_NSS_IDLENESS_11CYCLE,
SPI_NSS_IDLENESS_12CYCLE, SPI_NSS_IDLENESS_13CYCLE, SPI_NSS_IDLENESS_14CYCLE, SPI_NSS_IDLENESS_12CYCLE, SPI_NSS_IDLENESS_13CYCLE, SPI_NSS_IDLENESS_14CYCLE,
SPI_NSS_IDLENESS_15CYCLE SPI_NSS_IDLENESS_15CYCLE
\param[out] none \param[out] none
\retval none \retval none
*/ */
void spi_nss_idleness_delay_set(uint32_t spi_periph, uint32_t delay_cycle) void spi_nss_idleness_delay_set(uint32_t spi_periph, uint32_t delay_cycle)
{ {
/* acquire SPI_CFG1 register */ /* acquire SPI_CFG1 register */
uint32_t reg = SPI_CFG1(spi_periph); uint32_t reg = SPI_CFG1(spi_periph);
reg &= (uint32_t)(~SPI_CFG1_MSSD); reg &= (uint32_t)(~SPI_CFG1_MSSD);
reg |= (uint32_t)delay_cycle; reg |= (uint32_t)delay_cycle;
/* assign regiser */ /* assign regiser */
SPI_CFG1(spi_periph) = reg; SPI_CFG1(spi_periph) = reg;
} }
/*! /*!
\brief set SPI master data frame delay \brief set SPI master data frame delay
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] delay_cycle: SPI_DATA_IDLENESS_00CYCLE, SPI_DATA_IDLENESS_01CYCLE, SPI_DATA_IDLENESS_02CYCLE, \param[in] delay_cycle: SPI_DATA_IDLENESS_00CYCLE, SPI_DATA_IDLENESS_01CYCLE, SPI_DATA_IDLENESS_02CYCLE,
SPI_DATA_IDLENESS_03CYCLE, SPI_DATA_IDLENESS_04CYCLE, SPI_DATA_IDLENESS_05CYCLE, SPI_DATA_IDLENESS_03CYCLE, SPI_DATA_IDLENESS_04CYCLE, SPI_DATA_IDLENESS_05CYCLE,
SPI_DATA_IDLENESS_06CYCLE, SPI_DATA_IDLENESS_07CYCLE, SPI_DATA_IDLENESS_08CYCLE, SPI_DATA_IDLENESS_06CYCLE, SPI_DATA_IDLENESS_07CYCLE, SPI_DATA_IDLENESS_08CYCLE,
SPI_DATA_IDLENESS_09CYCLE, SPI_DATA_IDLENESS_10CYCLE, SPI_DATA_IDLENESS_11CYCLE, SPI_DATA_IDLENESS_09CYCLE, SPI_DATA_IDLENESS_10CYCLE, SPI_DATA_IDLENESS_11CYCLE,
SPI_DATA_IDLENESS_12CYCLE, SPI_DATA_IDLENESS_13CYCLE, SPI_DATA_IDLENESS_14CYCLE, SPI_DATA_IDLENESS_12CYCLE, SPI_DATA_IDLENESS_13CYCLE, SPI_DATA_IDLENESS_14CYCLE,
SPI_DATA_IDLENESS_15CYCLE SPI_DATA_IDLENESS_15CYCLE
\param[out] none \param[out] none
\retval none \retval none
*/ */
void spi_data_frame_delay_set(uint32_t spi_periph, uint32_t delay_cycle) void spi_data_frame_delay_set(uint32_t spi_periph, uint32_t delay_cycle)
{ {
/* acquire SPI_CFG1 register */ /* acquire SPI_CFG1 register */
uint32_t reg = SPI_CFG1(spi_periph); uint32_t reg = SPI_CFG1(spi_periph);
reg &= (uint32_t)(~SPI_CFG1_MDFD); reg &= (uint32_t)(~SPI_CFG1_MDFD);
reg |= (uint32_t)delay_cycle; reg |= (uint32_t)delay_cycle;
/* assign regiser */ /* assign regiser */
SPI_CFG1(spi_periph) = reg; SPI_CFG1(spi_periph) = reg;
} }
/*! /*!
\brief set SPI master mode rx clock delay \brief set SPI master mode rx clock delay
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] delay_unit: master mode receive clock delay \param[in] delay_unit: master mode receive clock delay
it can be 0-0x1f it can be 0-0x1f
@ -448,13 +459,13 @@ void spi_data_frame_delay_set(uint32_t spi_periph, uint32_t delay_cycle)
*/ */
void spi_master_receive_clock_delay_set(uint32_t spi_periph, uint32_t delay_unit) void spi_master_receive_clock_delay_set(uint32_t spi_periph, uint32_t delay_unit)
{ {
SPI_RXDLYCK(spi_periph) &= (uint32_t)(~SPI_RXDLYCK_MRXDEN); SPI_RXDLYCK(spi_periph) &= (uint32_t)(~SPI_RXDLYCK_MRXDEN);
SPI_RXDLYCK(spi_periph) &= (uint32_t)(~SPI_RXDLYCK_MRXD); SPI_RXDLYCK(spi_periph) &= (uint32_t)(~SPI_RXDLYCK_MRXD);
SPI_RXDLYCK(spi_periph) |= (uint32_t)(delay_unit << 6U); SPI_RXDLYCK(spi_periph) |= (uint32_t)(delay_unit << 6U);
} }
/*! /*!
\brief set SPI slave mode rx clock delay \brief set SPI slave mode rx clock delay
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] delay_unit: slave mode receive clock delay \param[in] delay_unit: slave mode receive clock delay
it can be 0-0x1f it can be 0-0x1f
@ -463,31 +474,31 @@ void spi_master_receive_clock_delay_set(uint32_t spi_periph, uint32_t delay_unit
*/ */
void spi_slave_receive_clock_delay_set(uint32_t spi_periph, uint32_t delay_unit) void spi_slave_receive_clock_delay_set(uint32_t spi_periph, uint32_t delay_unit)
{ {
SPI_RXDLYCK(spi_periph) &= (uint32_t)(~SPI_RXDLYCK_SRXDEN); SPI_RXDLYCK(spi_periph) &= (uint32_t)(~SPI_RXDLYCK_SRXDEN);
SPI_RXDLYCK(spi_periph) &= (uint32_t)(~SPI_RXDLYCK_SRXD); SPI_RXDLYCK(spi_periph) &= (uint32_t)(~SPI_RXDLYCK_SRXD);
SPI_RXDLYCK(spi_periph) |= (uint32_t)delay_unit; SPI_RXDLYCK(spi_periph) |= (uint32_t)delay_unit;
} }
/*! /*!
\brief clear SPI master mode rx clock delay \brief clear SPI master mode rx clock delay
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void spi_master_receive_clock_delay_clear(uint32_t spi_periph) void spi_master_receive_clock_delay_clear(uint32_t spi_periph)
{ {
SPI_RXDLYCK(spi_periph) |= (uint32_t)SPI_RXDLYCK_MRXDEN; SPI_RXDLYCK(spi_periph) |= (uint32_t)SPI_RXDLYCK_MRXDEN;
} }
/*! /*!
\brief clear SPI slave mode rx clock delay \brief clear SPI slave mode rx clock delay
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void spi_slave_receive_clock_delay_clear(uint32_t spi_periph) void spi_slave_receive_clock_delay_clear(uint32_t spi_periph)
{ {
SPI_RXDLYCK(spi_periph) |= (uint32_t)SPI_RXDLYCK_SRXDEN; SPI_RXDLYCK(spi_periph) |= (uint32_t)SPI_RXDLYCK_SRXDEN;
} }
/*! /*!
@ -502,16 +513,17 @@ void spi_slave_receive_clock_delay_clear(uint32_t spi_periph)
*/ */
void spi_nss_output_control(uint32_t spi_periph, uint32_t nss_ctl) void spi_nss_output_control(uint32_t spi_periph, uint32_t nss_ctl)
{ {
if(SPI_NSS_HOLD_UNTIL_TRANS_END == nss_ctl){ if(SPI_NSS_HOLD_UNTIL_TRANS_END == nss_ctl)
SPI_CFG1(spi_periph) &= (uint32_t)(~SPI_CFG1_NSSCTL); {
SPI_CFG1(spi_periph) &= (uint32_t)(~SPI_CFG1_NSSCTL);
} }
else{ else{
SPI_CFG1(spi_periph) |= (uint32_t)SPI_CFG1_NSSCTL; SPI_CFG1(spi_periph) |= (uint32_t)SPI_CFG1_NSSCTL;
} }
} }
/*! /*!
\brief set SPI NSS active polarity \brief set SPI NSS active polarity
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] polarity: SPI NSS active level \param[in] polarity: SPI NSS active level
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
@ -522,16 +534,17 @@ void spi_nss_output_control(uint32_t spi_periph, uint32_t nss_ctl)
*/ */
void spi_nss_polarity_set(uint32_t spi_periph, uint32_t polarity) void spi_nss_polarity_set(uint32_t spi_periph, uint32_t polarity)
{ {
if(SPI_NSS_POLARITY_HIGH == polarity){ if(SPI_NSS_POLARITY_HIGH == polarity)
SPI_CFG1(spi_periph) |= (uint32_t)SPI_CFG1_NSSIOPL; {
SPI_CFG1(spi_periph) |= (uint32_t)SPI_CFG1_NSSIOPL;
} }
else{ else{
SPI_CFG1(spi_periph) &= (uint32_t)(~SPI_CFG1_NSSIOPL); SPI_CFG1(spi_periph) &= (uint32_t)(~SPI_CFG1_NSSIOPL);
} }
} }
/*! /*!
\brief enable SPI NSS output \brief enable SPI NSS output
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[out] none \param[out] none
\retval none \retval none
@ -542,7 +555,7 @@ void spi_nss_output_enable(uint32_t spi_periph)
} }
/*! /*!
\brief disable SPI NSS output \brief disable SPI NSS output
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[out] none \param[out] none
\retval none \retval none
@ -575,7 +588,7 @@ void spi_nss_internal_low(uint32_t spi_periph)
} }
/*! /*!
\brief enable SPI DMA send or receive \brief enable SPI DMA send or receive
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] spi_dma: SPI DMA mode \param[in] spi_dma: SPI DMA mode
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
@ -586,7 +599,8 @@ void spi_nss_internal_low(uint32_t spi_periph)
*/ */
void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma) void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma)
{ {
if(SPI_DMA_TRANSMIT == spi_dma){ if(SPI_DMA_TRANSMIT == spi_dma)
{
SPI_CFG0(spi_periph) |= (uint32_t)SPI_CFG0_DMATEN; SPI_CFG0(spi_periph) |= (uint32_t)SPI_CFG0_DMATEN;
}else{ }else{
SPI_CFG0(spi_periph) |= (uint32_t)SPI_CFG0_DMAREN; SPI_CFG0(spi_periph) |= (uint32_t)SPI_CFG0_DMAREN;
@ -594,7 +608,7 @@ void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma)
} }
/*! /*!
\brief disable SPI DMA send or receive \brief disable SPI DMA send or receive
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] spi_dma: SPI DMA mode \param[in] spi_dma: SPI DMA mode
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
@ -605,7 +619,8 @@ void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma)
*/ */
void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma) void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma)
{ {
if(SPI_DMA_TRANSMIT == spi_dma){ if(SPI_DMA_TRANSMIT == spi_dma)
{
SPI_CFG0(spi_periph) &= (uint32_t)(~SPI_CFG0_DMATEN); SPI_CFG0(spi_periph) &= (uint32_t)(~SPI_CFG0_DMATEN);
}else{ }else{
SPI_CFG0(spi_periph) &= (uint32_t)(~SPI_CFG0_DMAREN); SPI_CFG0(spi_periph) &= (uint32_t)(~SPI_CFG0_DMAREN);
@ -624,7 +639,7 @@ void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma)
SPI_DATASIZE_22BIT, SPI_DATASIZE_23BIT, SPI_DATASIZE_24BIT, SPI_DATASIZE_22BIT, SPI_DATASIZE_23BIT, SPI_DATASIZE_24BIT,
SPI_DATASIZE_25BIT, SPI_DATASIZE_26BIT, SPI_DATASIZE_27BIT, SPI_DATASIZE_25BIT, SPI_DATASIZE_26BIT, SPI_DATASIZE_27BIT,
SPI_DATASIZE_28BIT, SPI_DATASIZE_29BIT, SPI_DATASIZE_30BIT, SPI_DATASIZE_28BIT, SPI_DATASIZE_29BIT, SPI_DATASIZE_30BIT,
SPI_DATASIZE_31BIT, SPI_DATASIZE_32BIT SPI_DATASIZE_31BIT, SPI_DATASIZE_32BIT
\param[out] none \param[out] none
\retval none \retval none
*/ */
@ -645,7 +660,7 @@ void spi_i2s_data_frame_size_config(uint32_t spi_periph, uint32_t frame_size)
\retval none \retval none
*/ */
void spi_i2s_data_transmit(uint32_t spi_periph, uint32_t data) void spi_i2s_data_transmit(uint32_t spi_periph, uint32_t data)
{ {
SPI_TDATA(spi_periph) = (uint32_t)data; SPI_TDATA(spi_periph) = (uint32_t)data;
} }
@ -657,7 +672,7 @@ void spi_i2s_data_transmit(uint32_t spi_periph, uint32_t data)
*/ */
uint32_t spi_i2s_data_receive(uint32_t spi_periph) uint32_t spi_i2s_data_receive(uint32_t spi_periph)
{ {
return ((uint32_t)SPI_RDATA(spi_periph)); return ((uint32_t)SPI_RDATA(spi_periph));
} }
/*! /*!
@ -671,7 +686,8 @@ uint32_t spi_i2s_data_receive(uint32_t spi_periph)
*/ */
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
{ {
if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction)
{
/* set the transmit only mode */ /* set the transmit only mode */
SPI_CFG1(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; SPI_CFG1(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
}else{ }else{
@ -685,14 +701,15 @@ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_di
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] transfer_start: transfer start bit \param[in] transfer_start: transfer start bit
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg SPI_TRANS_START: the master transmission is occurring, \arg SPI_TRANS_START: the master transmission is occurring,
or has been temporarily suspended by automatic suspend or has been temporarily suspended by automatic suspend
\arg SPI_TRANS_IDLE: the master transfer is idle status \arg SPI_TRANS_IDLE: the master transfer is idle status
\retval none \retval none
*/ */
void spi_master_transfer_start(uint32_t spi_periph, uint32_t transfer_start) void spi_master_transfer_start(uint32_t spi_periph, uint32_t transfer_start)
{ {
if(SPI_TRANS_START == transfer_start){ if(SPI_TRANS_START == transfer_start)
{
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_MSTART; SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_MSTART;
}else{ }else{
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_MSTART); SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_MSTART);
@ -700,7 +717,7 @@ void spi_master_transfer_start(uint32_t spi_periph, uint32_t transfer_start)
} }
/*! /*!
\brief configure SPI current data number \brief configure SPI current data number
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] current_num: SPI transfer current data number \param[in] current_num: SPI transfer current data number
it can be 0-0xFFFF it can be 0-0xFFFF
@ -712,7 +729,7 @@ void spi_current_data_num_config(uint32_t spi_periph, uint32_t current_num)
/* confige SPI current data number */ /* confige SPI current data number */
reg &= (uint32_t)(~BITS(0,15)); reg &= (uint32_t)(~BITS(0,15));
reg |= (uint32_t)current_num; reg |= (uint32_t)current_num;
SPI_CTL1(spi_periph) = reg; SPI_CTL1(spi_periph) = reg;
} }
/*! /*!
@ -732,14 +749,14 @@ void spi_reload_data_num_config(uint32_t spi_periph, uint32_t reload_num)
} }
/*! /*!
\brief set SPI CRC polynomial \brief set SPI CRC polynomial
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] crc_poly: CRC polynomial value \param[in] crc_poly: CRC polynomial value
\param[out] none \param[out] none
\retval none \retval none
*/ */
void spi_crc_polynomial_set(uint32_t spi_periph,uint32_t crc_poly) void spi_crc_polynomial_set(uint32_t spi_periph,uint32_t crc_poly)
{ {
/* enable SPI CRC */ /* enable SPI CRC */
SPI_CFG0(spi_periph) |= (uint32_t)SPI_CFG0_CRCEN; SPI_CFG0(spi_periph) |= (uint32_t)SPI_CFG0_CRCEN;
/* set SPI CRC polynomial */ /* set SPI CRC polynomial */
@ -747,7 +764,7 @@ void spi_crc_polynomial_set(uint32_t spi_periph,uint32_t crc_poly)
} }
/*! /*!
\brief get SPI CRC polynomial \brief get SPI CRC polynomial
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[out] none \param[out] none
\retval 32-bit CRC polynomial \retval 32-bit CRC polynomial
@ -758,15 +775,15 @@ uint32_t spi_crc_polynomial_get(uint32_t spi_periph)
} }
/*! /*!
\brief configure SPI CRC length \brief configure SPI CRC length
\param[in] spi_periph: (x=0,1,2,3,4,5) \param[in] spi_periph: (x=0,1,2,3,4,5)
\param[in] crc_size: SPI_CRCSIZE_4BIT, SPI_CRCSIZE_5BIT, SPI_CRCSIZE_6BIT, \param[in] crc_size: SPI_CRCSIZE_4BIT, SPI_CRCSIZE_5BIT, SPI_CRCSIZE_6BIT,
SPI_CRCSIZE_7BIT, SPI_CRCSIZE_8BIT, SPI_CRCSIZE_9BIT, SPI_CRCSIZE_10BIT, SPI_CRCSIZE_7BIT, SPI_CRCSIZE_8BIT, SPI_CRCSIZE_9BIT, SPI_CRCSIZE_10BIT,
SPI_CRCSIZE_11BIT, SPI_CRCSIZE_12BIT, SPI_CRCSIZE_13BIT, SPI_CRCSIZE_14BIT, SPI_CRCSIZE_11BIT, SPI_CRCSIZE_12BIT, SPI_CRCSIZE_13BIT, SPI_CRCSIZE_14BIT,
SPI_CRCSIZE_15BIT, SPI_CRCSIZE_16BIT, SPI_CRCSIZE_17BIT, SPI_CRCSIZE_18BIT, SPI_CRCSIZE_15BIT, SPI_CRCSIZE_16BIT, SPI_CRCSIZE_17BIT, SPI_CRCSIZE_18BIT,
SPI_CRCSIZE_19BIT, SPI_CRCSIZE_20BIT, SPI_CRCSIZE_21BIT, SPI_CRCSIZE_22BIT, SPI_CRCSIZE_19BIT, SPI_CRCSIZE_20BIT, SPI_CRCSIZE_21BIT, SPI_CRCSIZE_22BIT,
SPI_CRCSIZE_23BIT, SPI_CRCSIZE_24BIT, SPI_CRCSIZE_25BIT, SPI_CRCSIZE_26BIT, SPI_CRCSIZE_23BIT, SPI_CRCSIZE_24BIT, SPI_CRCSIZE_25BIT, SPI_CRCSIZE_26BIT,
SPI_CRCSIZE_27BIT, SPI_CRCSIZE_28BIT, SPI_CRCSIZE_29BIT, SPI_CRCSIZE_30BIT, SPI_CRCSIZE_27BIT, SPI_CRCSIZE_28BIT, SPI_CRCSIZE_29BIT, SPI_CRCSIZE_30BIT,
SPI_CRCSIZE_31BIT, SPI_CRCSIZE_32BIT SPI_CRCSIZE_31BIT, SPI_CRCSIZE_32BIT
\param[out] none \param[out] none
\retval none \retval none
@ -781,7 +798,7 @@ void spi_crc_length_config(uint32_t spi_periph, uint32_t crc_size)
} }
/*! /*!
\brief turn on CRC function \brief turn on CRC function
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[out] none \param[out] none
\retval none \retval none
@ -792,7 +809,7 @@ void spi_crc_on(uint32_t spi_periph)
} }
/*! /*!
\brief turn off CRC function \brief turn off CRC function
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[out] none \param[out] none
\retval none \retval none
@ -814,33 +831,34 @@ void spi_crc_off(uint32_t spi_periph)
*/ */
uint32_t spi_crc_get(uint32_t spi_periph, uint8_t crc) uint32_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
{ {
if(SPI_CRC_TX == crc){ if(SPI_CRC_TX == crc)
{
return ((uint32_t)(SPI_TCRC(spi_periph))); return ((uint32_t)(SPI_TCRC(spi_periph)));
}else{ }else{
return ((uint32_t)(SPI_RCRC(spi_periph))); return ((uint32_t)(SPI_RCRC(spi_periph)));
} }
} }
/*! /*!
\brief enable SPI CRC full size(33 bit or 17 bit) polynomial \brief enable SPI CRC full size(33 bit or 17 bit) polynomial
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void spi_crc_full_size_enable(uint32_t spi_periph) void spi_crc_full_size_enable(uint32_t spi_periph)
{ {
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCFS; SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCFS;
} }
/*! /*!
\brief disable SPI CRC full size(33 bit or 17 bit) polynomial \brief disable SPI CRC full size(33 bit or 17 bit) polynomial
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void spi_crc_full_size_disable(uint32_t spi_periph) void spi_crc_full_size_disable(uint32_t spi_periph)
{ {
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCFS); SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCFS);
} }
/*! /*!
@ -855,10 +873,11 @@ void spi_crc_full_size_disable(uint32_t spi_periph)
*/ */
void spi_tcrc_init_pattern(uint32_t spi_periph, uint32_t init_pattern) void spi_tcrc_init_pattern(uint32_t spi_periph, uint32_t init_pattern)
{ {
if(init_pattern == SPI_TCRC_INIT_1){ if(init_pattern == SPI_TCRC_INIT_1)
{
SPI_CTL0(spi_periph) |= (uint32_t)(SPI_CTL0_TXCRCI); SPI_CTL0(spi_periph) |= (uint32_t)(SPI_CTL0_TXCRCI);
}else{ }else{
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_TXCRCI); SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_TXCRCI);
} }
} }
@ -874,10 +893,11 @@ void spi_tcrc_init_pattern(uint32_t spi_periph, uint32_t init_pattern)
*/ */
void spi_rcrc_init_pattern(uint32_t spi_periph, uint32_t init_pattern) void spi_rcrc_init_pattern(uint32_t spi_periph, uint32_t init_pattern)
{ {
if(init_pattern == SPI_RCRC_INIT_1){ if(init_pattern == SPI_RCRC_INIT_1)
{
SPI_CTL0(spi_periph) |= (uint32_t)(SPI_CTL0_RXCRCI); SPI_CTL0(spi_periph) |= (uint32_t)(SPI_CTL0_RXCRCI);
}else{ }else{
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_RXCRCI); SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_RXCRCI);
} }
} }
@ -915,7 +935,7 @@ void spi_quad_enable(uint32_t spi_periph)
} }
/*! /*!
\brief disable quad wire SPI \brief disable quad wire SPI
\param[in] spi_periph: SPIx(x=3,4) \param[in] spi_periph: SPIx(x=3,4)
\param[out] none \param[out] none
\retval none \retval none
@ -926,7 +946,7 @@ void spi_quad_disable(uint32_t spi_periph)
} }
/*! /*!
\brief enable quad wire SPI write \brief enable quad wire SPI write
\param[in] spi_periph: SPIx(x=3,4) \param[in] spi_periph: SPIx(x=3,4)
\param[out] none \param[out] none
\retval none \retval none
@ -937,7 +957,7 @@ void spi_quad_write_enable(uint32_t spi_periph)
} }
/*! /*!
\brief enable quad wire SPI read \brief enable quad wire SPI read
\param[in] spi_periph: SPIx(x=3,4) \param[in] spi_periph: SPIx(x=3,4)
\param[out] none \param[out] none
\retval none \retval none
@ -948,7 +968,7 @@ void spi_quad_read_enable(uint32_t spi_periph)
} }
/*! /*!
\brief enable SPI_IO2 and SPI_IO3 pin output \brief enable SPI_IO2 and SPI_IO3 pin output
\param[in] spi_periph: SPIx(x=3,4) \param[in] spi_periph: SPIx(x=3,4)
\param[out] none \param[out] none
\retval none \retval none
@ -959,7 +979,7 @@ void spi_quad_io23_output_enable(uint32_t spi_periph)
} }
/*! /*!
\brief disable SPI_IO2 and SPI_IO3 pin output \brief disable SPI_IO2 and SPI_IO3 pin output
\param[in] spi_periph: SPIx(x=3,4) \param[in] spi_periph: SPIx(x=3,4)
\param[out] none \param[out] none
\retval none \retval none
@ -970,7 +990,7 @@ void spi_quad_io23_output_enable(uint32_t spi_periph)
} }
/*! /*!
\brief slave transmitter underrun detected operation \brief slave transmitter underrun detected operation
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] ur_ope: underrun operation \param[in] ur_ope: underrun operation
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
@ -982,16 +1002,16 @@ void spi_quad_io23_output_enable(uint32_t spi_periph)
*/ */
void spi_underrun_operation(uint32_t spi_periph, uint32_t ur_ope) void spi_underrun_operation(uint32_t spi_periph, uint32_t ur_ope)
{ {
/* acquire SPI_CFG0 register */ /* acquire SPI_CFG0 register */
uint32_t reg = SPI_CFG0(spi_periph); uint32_t reg = SPI_CFG0(spi_periph);
reg &= (uint32_t)(~SPI_CFG0_TXUROP); reg &= (uint32_t)(~SPI_CFG0_TXUROP);
reg |= (uint32_t)ur_ope; reg |= (uint32_t)ur_ope;
/* assign regiser */ /* assign regiser */
SPI_CFG0(spi_periph) = reg; SPI_CFG0(spi_periph) = reg;
} }
/*! /*!
\brief configure slave transmitter underrun detected \brief configure slave transmitter underrun detected
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] ur_cfg: underrun config \param[in] ur_cfg: underrun config
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
@ -1003,12 +1023,12 @@ void spi_underrun_operation(uint32_t spi_periph, uint32_t ur_ope)
*/ */
void spi_underrun_config(uint32_t spi_periph, uint32_t ur_cfg) void spi_underrun_config(uint32_t spi_periph, uint32_t ur_cfg)
{ {
/* acquire SPI_CFG0 register */ /* acquire SPI_CFG0 register */
uint32_t reg = SPI_CFG0(spi_periph); uint32_t reg = SPI_CFG0(spi_periph);
reg &= (uint32_t)(~SPI_CFG0_TXURDT); reg &= (uint32_t)(~SPI_CFG0_TXURDT);
reg |= (uint32_t)ur_cfg; reg |= (uint32_t)ur_cfg;
/* assign regiser */ /* assign regiser */
SPI_CFG0(spi_periph) = ur_cfg; SPI_CFG0(spi_periph) = ur_cfg;
} }
/*! /*!
@ -1021,7 +1041,7 @@ void spi_underrun_config(uint32_t spi_periph, uint32_t ur_cfg)
*/ */
void spi_underrun_data_config(uint32_t spi_periph, uint32_t udata) void spi_underrun_data_config(uint32_t spi_periph, uint32_t udata)
{ {
SPI_URDATA(spi_periph) = (uint32_t)udata; SPI_URDATA(spi_periph) = (uint32_t)udata;
} }
/*! /*!
@ -1029,7 +1049,7 @@ void spi_underrun_data_config(uint32_t spi_periph, uint32_t udata)
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] sus_mode: suspend mode \param[in] sus_mode: suspend mode
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg SPI_AUTO_SUSPEND: until the overrun condition is reached, \arg SPI_AUTO_SUSPEND: until the overrun condition is reached,
the SPI stream is suspended in the full RxFIFO state the SPI stream is suspended in the full RxFIFO state
\arg SPI_CONTINUOUS: SPI stream/clock generation is continuous whether or not an overrun occurs \arg SPI_CONTINUOUS: SPI stream/clock generation is continuous whether or not an overrun occurs
\param[out] none \param[out] none
@ -1037,11 +1057,12 @@ void spi_underrun_data_config(uint32_t spi_periph, uint32_t udata)
*/ */
void spi_suspend_mode_config(uint32_t spi_periph, uint32_t sus_mode) void spi_suspend_mode_config(uint32_t spi_periph, uint32_t sus_mode)
{ {
if(SPI_AUTO_SUSPEND == sus_mode){ if(SPI_AUTO_SUSPEND == sus_mode)
{
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_MASP; SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_MASP;
}else{ }else{
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_MASP); SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_MASP);
} }
} }
/*! /*!
@ -1052,29 +1073,29 @@ void spi_suspend_mode_config(uint32_t spi_periph, uint32_t sus_mode)
*/ */
void spi_suspend_request(uint32_t spi_periph) void spi_suspend_request(uint32_t spi_periph)
{ {
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_MSPDR; SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_MSPDR;
} }
/*! /*!
\brief enable SPI related IOs AF \brief enable SPI related IOs AF
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void spi_related_ios_af_enable(uint32_t spi_periph) void spi_related_ios_af_enable(uint32_t spi_periph)
{ {
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_IOAFEN); SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_IOAFEN);
} }
/*! /*!
\brief disable SPI related IOs AF \brief disable SPI related IOs AF
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[out] none \param[out] none
\retval none \retval none
*/ */
void spi_related_ios_af_disable(uint32_t spi_periph) void spi_related_ios_af_disable(uint32_t spi_periph)
{ {
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_IOAFEN; SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_IOAFEN;
} }
/*! /*!
@ -1089,15 +1110,16 @@ void spi_related_ios_af_disable(uint32_t spi_periph)
*/ */
void spi_af_gpio_control(uint32_t spi_periph, uint32_t ctl) void spi_af_gpio_control(uint32_t spi_periph, uint32_t ctl)
{ {
if(SPI_GPIO_CONTROL == ctl){ if(SPI_GPIO_CONTROL == ctl)
{
SPI_CFG1(spi_periph) |= (uint32_t)SPI_CFG1_AFCTL; SPI_CFG1(spi_periph) |= (uint32_t)SPI_CFG1_AFCTL;
}else{ }else{
SPI_CFG1(spi_periph) &= (uint32_t)(~SPI_CFG1_AFCTL); SPI_CFG1(spi_periph) &= (uint32_t)(~SPI_CFG1_AFCTL);
} }
} }
/*! /*!
\brief enable SPI and I2S interrupt \brief enable SPI and I2S interrupt
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] interrupt: SPI/I2S interrupt \param[in] interrupt: SPI/I2S interrupt
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
@ -1117,7 +1139,8 @@ void spi_af_gpio_control(uint32_t spi_periph, uint32_t ctl)
*/ */
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
{ {
switch(interrupt){ switch(interrupt)
{
/* SPI/I2S RP interrupt */ /* SPI/I2S RP interrupt */
case SPI_I2S_INT_RP: case SPI_I2S_INT_RP:
SPI_INT(spi_periph) |= (uint32_t)SPI_INT_RPIE; SPI_INT(spi_periph) |= (uint32_t)SPI_INT_RPIE;
@ -1157,18 +1180,18 @@ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
/* SPI/I2S mode error interrupt */ /* SPI/I2S mode error interrupt */
case SPI_I2S_INT_CONFE: case SPI_I2S_INT_CONFE:
SPI_INT(spi_periph) |= (uint32_t)SPI_INT_CONFEIE; SPI_INT(spi_periph) |= (uint32_t)SPI_INT_CONFEIE;
break; break;
/* SPI/I2S TXSER reload interrupt */ /* SPI/I2S TXSER reload interrupt */
case SPI_I2S_INT_TXSERF: case SPI_I2S_INT_TXSERF:
SPI_INT(spi_periph) |= (uint32_t)SPI_INT_TXSERFIE; SPI_INT(spi_periph) |= (uint32_t)SPI_INT_TXSERFIE;
break; break;
default: default:
break; break;
} }
} }
/*! /*!
\brief disable SPI and I2S interrupt \brief disable SPI and I2S interrupt
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] interrupt: SPI/I2S interrupt \param[in] interrupt: SPI/I2S interrupt
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
@ -1188,7 +1211,8 @@ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
*/ */
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
{ {
switch(interrupt){ switch(interrupt)
{
/* SPI/I2S RP interrupt */ /* SPI/I2S RP interrupt */
case SPI_I2S_INT_RP: case SPI_I2S_INT_RP:
SPI_INT(spi_periph) &= (uint32_t)(~SPI_INT_RPIE); SPI_INT(spi_periph) &= (uint32_t)(~SPI_INT_RPIE);
@ -1228,11 +1252,11 @@ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
/* SPI/I2S mode error interrupt */ /* SPI/I2S mode error interrupt */
case SPI_I2S_INT_CONFE: case SPI_I2S_INT_CONFE:
SPI_INT(spi_periph) &= (uint32_t)(~SPI_INT_CONFEIE); SPI_INT(spi_periph) &= (uint32_t)(~SPI_INT_CONFEIE);
break; break;
/* SPI/I2S TXSER reload interrupt */ /* SPI/I2S TXSER reload interrupt */
case SPI_I2S_INT_TXSERF: case SPI_I2S_INT_TXSERF:
SPI_INT(spi_periph) &= (uint32_t)(~SPI_INT_TXSERFIE); SPI_INT(spi_periph) &= (uint32_t)(~SPI_INT_TXSERFIE);
break; break;
default: default:
break; break;
} }
@ -1264,7 +1288,8 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
uint32_t reg1 = SPI_STAT(spi_periph); uint32_t reg1 = SPI_STAT(spi_periph);
uint32_t reg2 = SPI_INT(spi_periph); uint32_t reg2 = SPI_INT(spi_periph);
switch(interrupt){ switch(interrupt)
{
/* SPI/I2S RP interrupt */ /* SPI/I2S RP interrupt */
case SPI_I2S_INT_FLAG_RP: case SPI_I2S_INT_FLAG_RP:
reg1 = reg1 & SPI_STAT_RP; reg1 = reg1 & SPI_STAT_RP;
@ -1319,7 +1344,7 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
case SPI_I2S_INT_FLAG_TXSERF: case SPI_I2S_INT_FLAG_TXSERF:
reg1 = reg1 & SPI_STAT_TXSERF; reg1 = reg1 & SPI_STAT_TXSERF;
reg2 = reg2 & SPI_INT_TXSERFIE; reg2 = reg2 & SPI_INT_TXSERFIE;
break; break;
/* SPI suspend interrupt */ /* SPI suspend interrupt */
case SPI_I2S_INT_FLAG_SPD: case SPI_I2S_INT_FLAG_SPD:
reg1 = reg1 & SPI_STAT_SPD; reg1 = reg1 & SPI_STAT_SPD;
@ -1334,7 +1359,8 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
break; break;
} }
/*get SPI/I2S interrupt flag status */ /*get SPI/I2S interrupt flag status */
if(reg1 && reg2){ if(reg1 && reg2)
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -1373,7 +1399,8 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
*/ */
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
{ {
if(SPI_STAT(spi_periph) & flag){ if(SPI_STAT(spi_periph) & flag)
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -1399,7 +1426,7 @@ FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
*/ */
void spi_i2s_flag_clear(uint32_t spi_periph, uint32_t flag) void spi_i2s_flag_clear(uint32_t spi_periph, uint32_t flag)
{ {
SPI_STATC(spi_periph) |= (uint32_t)flag; SPI_STATC(spi_periph) |= (uint32_t)flag;
} }
/*! /*!
@ -1409,7 +1436,7 @@ void spi_i2s_flag_clear(uint32_t spi_periph, uint32_t flag)
\retval 2-bit RXFIFO packing data frame number \retval 2-bit RXFIFO packing data frame number
*/ */
uint32_t spi_i2s_rxfifo_plevel_get(uint32_t spi_periph) uint32_t spi_i2s_rxfifo_plevel_get(uint32_t spi_periph)
{ {
return ((uint32_t)((SPI_STAT(spi_periph) & SPI_STAT_RPLVL) >> 13U)); return ((uint32_t)((SPI_STAT(spi_periph) & SPI_STAT_RPLVL) >> 13U));
} }
@ -1420,18 +1447,18 @@ uint32_t spi_i2s_rxfifo_plevel_get(uint32_t spi_periph)
\retval 32-bit value \retval 32-bit value
*/ */
uint32_t spi_i2s_remain_data_num_get(uint32_t spi_periph) uint32_t spi_i2s_remain_data_num_get(uint32_t spi_periph)
{ {
return ((uint32_t)((SPI_STAT(spi_periph) & SPI_STAT_CTXSIZE) >> 16U)); return ((uint32_t)((SPI_STAT(spi_periph) & SPI_STAT_CTXSIZE) >> 16U));
} }
/*! /*!
\brief set SPI FIFO threshold level \brief set SPI FIFO threshold level
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
\param[in] fifo_thl: SPI_FIFO_TH_01DATA, SPI_FIFO_TH_02DATA, SPI_FIFO_TH_03DATA, \param[in] fifo_thl: SPI_FIFO_TH_01DATA, SPI_FIFO_TH_02DATA, SPI_FIFO_TH_03DATA,
SPI_FIFO_TH_04DATA, SPI_FIFO_TH_05DATA, SPI_FIFO_TH_06DATA, SPI_FIFO_TH_04DATA, SPI_FIFO_TH_05DATA, SPI_FIFO_TH_06DATA,
SPI_FIFO_TH_07DATA, SPI_FIFO_TH_08DATA, SPI_FIFO_TH_09DATA, SPI_FIFO_TH_07DATA, SPI_FIFO_TH_08DATA, SPI_FIFO_TH_09DATA,
SPI_FIFO_TH_10DATA, SPI_FIFO_TH_11DATA, SPI_FIFO_TH_12DATA, SPI_FIFO_TH_10DATA, SPI_FIFO_TH_11DATA, SPI_FIFO_TH_12DATA,
SPI_FIFO_TH_13DATA, SPI_FIFO_TH_14DATA, SPI_FIFO_TH_15DATA, SPI_FIFO_TH_13DATA, SPI_FIFO_TH_14DATA, SPI_FIFO_TH_15DATA,
SPI_FIFO_TH_16DATA SPI_FIFO_TH_16DATA
\param[out] none \param[out] none
\retval none \retval none
@ -1439,7 +1466,7 @@ uint32_t spi_i2s_remain_data_num_get(uint32_t spi_periph)
void spi_fifo_threshold_level_set(uint32_t spi_periph, uint32_t fifo_thl) void spi_fifo_threshold_level_set(uint32_t spi_periph, uint32_t fifo_thl)
{ {
SPI_CFG0(spi_periph) &= (uint32_t)(~SPI_CFG0_FIFOLVL); SPI_CFG0(spi_periph) &= (uint32_t)(~SPI_CFG0_FIFOLVL);
SPI_CFG0(spi_periph) |= (uint32_t)fifo_thl; SPI_CFG0(spi_periph) |= (uint32_t)fifo_thl;
} }
/*! /*!

24
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_syscfg.c
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@ -133,7 +133,8 @@ void syscfg_enet_phy_interface_config(uint32_t ethernet, uint32_t phy_interface)
/* read the value of SYSCFG_PMCFG register */ /* read the value of SYSCFG_PMCFG register */
reg = SYSCFG_PMCFG; reg = SYSCFG_PMCFG;
/* configure the ENET media interface */ /* configure the ENET media interface */
if(ENET0 == ethernet) { if(ENET0 == ethernet)
{
reg &= ~SYSCFG_PMCFG_ENET0_PHY_SEL; reg &= ~SYSCFG_PMCFG_ENET0_PHY_SEL;
reg |= ENET0_MEDIA_INTERFACE(phy_interface); reg |= ENET0_MEDIA_INTERFACE(phy_interface);
} else { } else {
@ -160,7 +161,8 @@ void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin)
uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin))); uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin)));
uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin)); uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin));
switch(exti_pin / EXTI_SS_JSTEP) { switch(exti_pin / EXTI_SS_JSTEP)
{
case EXTISS0: case EXTISS0:
/* clear EXTI source line(0..3) */ /* clear EXTI source line(0..3) */
SYSCFG_EXTISS0 &= clear_exti_mask; SYSCFG_EXTISS0 &= clear_exti_mask;
@ -351,7 +353,8 @@ void syscfg_timer_input_source_select(timer_channel_input_enum timer_input)
uint32_t clear_timer_mask = ~((uint32_t)TIMER_IS_MASK << (TIMER_BIT_POS(timer_input))); uint32_t clear_timer_mask = ~((uint32_t)TIMER_IS_MASK << (TIMER_BIT_POS(timer_input)));
uint32_t config_timer_mask = (TIMER_SEL_VAL(timer_input) << TIMER_BIT_POS(timer_input)); uint32_t config_timer_mask = (TIMER_SEL_VAL(timer_input) << TIMER_BIT_POS(timer_input));
switch(TIMER_REG_INDEX(timer_input)) { switch(TIMER_REG_INDEX(timer_input))
{
case TIMERCISEL0: case TIMERCISEL0:
/* clear TIMER channel input select */ /* clear TIMER channel input select */
SYSCFG_TIMERCISEL0 &= clear_timer_mask; SYSCFG_TIMERCISEL0 &= clear_timer_mask;
@ -454,7 +457,8 @@ void syscfg_pnmos_compensation_code_set(uint32_t mos, uint32_t code)
{ {
uint32_t value; uint32_t value;
value = SYSCFG_CPSCCCFG; value = SYSCFG_CPSCCCFG;
if(NMOS_COMPENSATION == mos) { if(NMOS_COMPENSATION == mos)
{
value &= ~SYSCFG_CPSCCCFG_NCPSCC; value &= ~SYSCFG_CPSCCCFG_NCPSCC;
value |= (code & 0x0FU); value |= (code & 0x0FU);
} else { } else {
@ -579,7 +583,8 @@ void syscfg_fpu_interrupt_disable(uint32_t fpu_int)
*/ */
FlagStatus syscfg_compensation_flag_get(uint32_t cps_flag) FlagStatus syscfg_compensation_flag_get(uint32_t cps_flag)
{ {
if(SYSCFG_CPSCTL & cps_flag) { if(SYSCFG_CPSCTL & cps_flag)
{
return SET; return SET;
} else { } else {
return RESET; return RESET;
@ -602,10 +607,12 @@ FlagStatus syscfg_compensation_flag_get(uint32_t cps_flag)
uint32_t syscfg_cpu_cache_status_get(uint32_t cache, uint32_t status) uint32_t syscfg_cpu_cache_status_get(uint32_t cache, uint32_t status)
{ {
uint32_t value = 0U; uint32_t value = 0U;
switch(cache) { switch(cache)
{
/* get ICACHE information */ /* get ICACHE information */
case ICACHE_STATUS: case ICACHE_STATUS:
if(CPU_CACHE_ERROR_DETECTION == status) { if(CPU_CACHE_ERROR_DETECTION == status)
{
/* return detection information */ /* return detection information */
value = (uint32_t)((SYSCFG_CPUICAC & SYSCFG_CPUICAC_CPU_ICDET) >> 28U); value = (uint32_t)((SYSCFG_CPUICAC & SYSCFG_CPUICAC_CPU_ICDET) >> 28U);
} else { } else {
@ -615,7 +622,8 @@ uint32_t syscfg_cpu_cache_status_get(uint32_t cache, uint32_t status)
break; break;
/* get DCACHE information */ /* get DCACHE information */
case DCACHE_STATUS: case DCACHE_STATUS:
if(CPU_CACHE_ERROR_DETECTION == status) { if(CPU_CACHE_ERROR_DETECTION == status)
{
/* return detection information */ /* return detection information */
value = (uint32_t)((SYSCFG_CPUDCAC & SYSCFG_CPUICAC_CPU_ICDET) >> 28U); value = (uint32_t)((SYSCFG_CPUDCAC & SYSCFG_CPUICAC_CPU_ICDET) >> 28U);
} else { } else {

489
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_timer.c
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135
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_tli.c
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@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -121,13 +121,13 @@ void tli_init(tli_parameter_struct *tli_struct)
/* back-porch size configuration */ /* back-porch size configuration */
TLI_BPSZ &= ~(TLI_BPSZ_VBPSZ | TLI_BPSZ_HBPSZ); TLI_BPSZ &= ~(TLI_BPSZ_VBPSZ | TLI_BPSZ_HBPSZ);
TLI_BPSZ = (uint32_t)((uint32_t)tli_struct->backpsz_vbpsz | ((uint32_t)tli_struct->backpsz_hbpsz << 16U)); TLI_BPSZ = (uint32_t)((uint32_t)tli_struct->backpsz_vbpsz | ((uint32_t)tli_struct->backpsz_hbpsz << 16U));
/* active size configuration */ /* active size configuration */
TLI_ASZ &= ~(TLI_ASZ_VASZ | TLI_ASZ_HASZ); TLI_ASZ &= ~(TLI_ASZ_VASZ | TLI_ASZ_HASZ);
TLI_ASZ = (tli_struct->activesz_vasz | (tli_struct->activesz_hasz << 16U)); TLI_ASZ = (tli_struct->activesz_vasz | (tli_struct->activesz_hasz << 16U));
/* total size configuration */ /* total size configuration */
TLI_TSZ &= ~(TLI_TSZ_VTSZ | TLI_TSZ_HTSZ); TLI_TSZ &= ~(TLI_TSZ_VTSZ | TLI_TSZ_HTSZ);
TLI_TSZ = (tli_struct->totalsz_vtsz | (tli_struct->totalsz_htsz << 16U)); TLI_TSZ = (tli_struct->totalsz_vtsz | (tli_struct->totalsz_htsz << 16U));
/* background color configuration */ /* background color configuration */
TLI_BGC &= ~(TLI_BGC_BVB | (TLI_BGC_BVG) | (TLI_BGC_BVR)); TLI_BGC &= ~(TLI_BGC_BVB | (TLI_BGC_BVG) | (TLI_BGC_BVR));
TLI_BGC = (tli_struct->backcolor_blue | (tli_struct->backcolor_green << 8U) | (tli_struct->backcolor_red << 16U)); TLI_BGC = (tli_struct->backcolor_blue | (tli_struct->backcolor_green << 8U) | (tli_struct->backcolor_red << 16U));
TLI_CTL &= ~(TLI_CTL_HPPS|TLI_CTL_VPPS | TLI_CTL_DEPS|TLI_CTL_CLKPS); TLI_CTL &= ~(TLI_CTL_HPPS|TLI_CTL_VPPS | TLI_CTL_DEPS|TLI_CTL_CLKPS);
@ -146,7 +146,8 @@ void tli_init(tli_parameter_struct *tli_struct)
*/ */
void tli_dither_config(uint8_t dither_stat) void tli_dither_config(uint8_t dither_stat)
{ {
if(TLI_DITHER_ENABLE == dither_stat){ if(TLI_DITHER_ENABLE == dither_stat)
{
TLI_CTL |= TLI_CTL_DFEN; TLI_CTL |= TLI_CTL_DFEN;
} else { } else {
TLI_CTL &= ~(TLI_CTL_DFEN); TLI_CTL &= ~(TLI_CTL_DFEN);
@ -154,7 +155,7 @@ void tli_dither_config(uint8_t dither_stat)
} }
/*! /*!
\brief enable TLI \brief enable TLI
\param[in] none \param[in] none
\param[out] none \param[out] none
\retval none \retval none
@ -165,7 +166,7 @@ void tli_enable(void)
} }
/*! /*!
\brief disable TLI \brief disable TLI
\param[in] none \param[in] none
\param[out] none \param[out] none
\retval none \retval none
@ -186,7 +187,8 @@ void tli_disable(void)
*/ */
void tli_reload_config(uint8_t reload_mod) void tli_reload_config(uint8_t reload_mod)
{ {
if(TLI_FRAME_BLANK_RELOAD_EN == reload_mod){ if(TLI_FRAME_BLANK_RELOAD_EN == reload_mod)
{
/* the layer configuration will be reloaded at frame blank */ /* the layer configuration will be reloaded at frame blank */
TLI_RL |= TLI_RL_FBR; TLI_RL |= TLI_RL_FBR;
} else { } else {
@ -196,7 +198,7 @@ void tli_reload_config(uint8_t reload_mod)
} }
/*! /*!
\brief initialize the parameters of TLI layer structure with the default values, it is suggested \brief initialize the parameters of TLI layer structure with the default values, it is suggested
that call this function after a tli_layer_parameter_struct structure is defined that call this function after a tli_layer_parameter_struct structure is defined
\param[in] none \param[in] none
\param[out] layer_struct: TLI Layer parameter struct \param[out] layer_struct: TLI Layer parameter struct
@ -242,12 +244,12 @@ void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct)
} }
/*! /*!
\brief initialize TLI layer \brief initialize TLI layer
\param[in] layerx: LAYERx(x=0,1) \param[in] layerx: LAYERx(x=0,1)
\param[in] layer_struct: TLI Layer parameter struct \param[in] layer_struct: TLI Layer parameter struct
layer_window_rightpos: window right position layer_window_rightpos: window right position
layer_window_leftpos: window left position layer_window_leftpos: window left position
layer_window_bottompos: window bottom position layer_window_bottompos: window bottom position
layer_window_toppos: window top position layer_window_toppos: window top position
layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565,
LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8,
@ -282,9 +284,9 @@ void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct)
TLI_LXSA(layerx) = layer_struct->layer_sa; TLI_LXSA(layerx) = layer_struct->layer_sa;
/* configure layer default color */ /* configure layer default color */
TLI_LXDC(layerx) &= ~(TLI_LXDC_DCB | (TLI_LXDC_DCG) | (TLI_LXDC_DCR) | (TLI_LXDC_DCA)); TLI_LXDC(layerx) &= ~(TLI_LXDC_DCB | (TLI_LXDC_DCG) | (TLI_LXDC_DCR) | (TLI_LXDC_DCA));
TLI_LXDC(layerx) = (uint32_t)((uint32_t)layer_struct->layer_default_blue | TLI_LXDC(layerx) = (uint32_t)((uint32_t)layer_struct->layer_default_blue |
((uint32_t)layer_struct->layer_default_green << 8U) | ((uint32_t)layer_struct->layer_default_green << 8U) |
((uint32_t)layer_struct->layer_default_red << 16U) | ((uint32_t)layer_struct->layer_default_red << 16U) |
((uint32_t)layer_struct->layer_default_alpha << 24U)); ((uint32_t)layer_struct->layer_default_alpha << 24U));
/* configure layer alpha calculation factors */ /* configure layer alpha calculation factors */
@ -303,7 +305,7 @@ void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct)
} }
/*! /*!
\brief reconfigure window position \brief reconfigure window position
\param[in] layerx: LAYERx(x=0,1) \param[in] layerx: LAYERx(x=0,1)
\param[in] offset_x: new horizontal offset \param[in] offset_x: new horizontal offset
\param[in] offset_y: new vertical offset \param[in] offset_y: new vertical offset
@ -322,7 +324,8 @@ void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t o
line_num = (TLI_LXFTLN(layerx) & TLI_LXFTLN_FTLN); line_num = (TLI_LXFTLN(layerx) & TLI_LXFTLN_FTLN);
layer_ppf = (TLI_LXPPF(layerx) & TLI_LXPPF_PPF); layer_ppf = (TLI_LXPPF(layerx) & TLI_LXPPF_PPF);
/* the bytes of a line equal TLI_LXFLLEN_FLL bits value minus 3 */ /* the bytes of a line equal TLI_LXFLLEN_FLL bits value minus 3 */
switch(layer_ppf){ switch(layer_ppf)
{
case LAYER_PPF_ARGB8888: case LAYER_PPF_ARGB8888:
/* each pixel includes 4bytes, when pixel format is ARGB8888 */ /* each pixel includes 4bytes, when pixel format is ARGB8888 */
line_length = (((TLI_LXFLLEN(layerx) & TLI_LXFLLEN_FLL) -3U) / 4U); line_length = (((TLI_LXFLLEN(layerx) & TLI_LXFLLEN_FLL) -3U) / 4U);
@ -352,7 +355,7 @@ void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t o
} }
/*! /*!
\brief initialize the parameters of TLI layer LUT structure with the default values, it is suggested \brief initialize the parameters of TLI layer LUT structure with the default values, it is suggested
that call this function after a tli_layer_lut_parameter_struct structure is defined that call this function after a tli_layer_lut_parameter_struct structure is defined
\param[in] none \param[in] none
\param[out] lut_struct: TLI layer LUT parameter struct \param[out] lut_struct: TLI layer LUT parameter struct
@ -372,7 +375,7 @@ void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct)
} }
/*! /*!
\brief initialize TLI layer LUT \brief initialize TLI layer LUT
\param[in] layerx: LAYERx(x=0,1) \param[in] layerx: LAYERx(x=0,1)
\param[in] lut_struct: TLI layer LUT parameter struct \param[in] lut_struct: TLI layer LUT parameter struct
layer_table_addr: look up table write address layer_table_addr: look up table write address
@ -384,17 +387,17 @@ void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct)
*/ */
void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct) void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct)
{ {
TLI_LXLUT(layerx) = (uint32_t)(((uint32_t)lut_struct->layer_lut_channel_blue) | TLI_LXLUT(layerx) = (uint32_t)(((uint32_t)lut_struct->layer_lut_channel_blue) |
((uint32_t)lut_struct->layer_lut_channel_green << 8U) | ((uint32_t)lut_struct->layer_lut_channel_green << 8U) |
((uint32_t)lut_struct->layer_lut_channel_red << 16U) | ((uint32_t)lut_struct->layer_lut_channel_red << 16U) |
((uint32_t)lut_struct->layer_table_addr << 24U)); ((uint32_t)lut_struct->layer_table_addr << 24U));
} }
/*! /*!
\brief initialize TLI layer color key \brief initialize TLI layer color key
\param[in] layerx: LAYERx(x=0,1) \param[in] layerx: LAYERx(x=0,1)
\param[in] redkey: color key red \param[in] redkey: color key red
\param[in] greenkey: color key green \param[in] greenkey: color key green
\param[in] bluekey: color key blue \param[in] bluekey: color key blue
\param[out] none \param[out] none
\retval none \retval none
@ -405,7 +408,7 @@ void tli_color_key_init(uint32_t layerx,uint8_t redkey,uint8_t greenkey,uint8_t
} }
/*! /*!
\brief enable TLI layer \brief enable TLI layer
\param[in] layerx: LAYERx(x=0,1) \param[in] layerx: LAYERx(x=0,1)
\param[out] none \param[out] none
\retval none \retval none
@ -416,7 +419,7 @@ void tli_layer_enable(uint32_t layerx)
} }
/*! /*!
\brief disable TLI layer \brief disable TLI layer
\param[in] layerx: LAYERx(x=0,1) \param[in] layerx: LAYERx(x=0,1)
\param[out] none \param[out] none
\retval none \retval none
@ -427,7 +430,7 @@ void tli_layer_disable(uint32_t layerx)
} }
/*! /*!
\brief enable TLI layer color keying \brief enable TLI layer color keying
\param[in] layerx: LAYERx(x=0,1) \param[in] layerx: LAYERx(x=0,1)
\param[out] none \param[out] none
\retval none \retval none
@ -438,7 +441,7 @@ void tli_color_key_enable(uint32_t layerx)
} }
/*! /*!
\brief disable TLI layer color keying \brief disable TLI layer color keying
\param[in] layerx: LAYERx(x=0,1) \param[in] layerx: LAYERx(x=0,1)
\param[out] none \param[out] none
\retval none \retval none
@ -449,7 +452,7 @@ void tli_color_key_disable(uint32_t layerx)
} }
/*! /*!
\brief enable TLI layer LUT \brief enable TLI layer LUT
\param[in] layerx: LAYERx(x=0,1) \param[in] layerx: LAYERx(x=0,1)
\param[out] none \param[out] none
\retval none \retval none
@ -460,7 +463,7 @@ void tli_lut_enable(uint32_t layerx)
} }
/*! /*!
\brief disable TLI layer LUT \brief disable TLI layer LUT
\param[in] layerx: LAYERx(x=0,1) \param[in] layerx: LAYERx(x=0,1)
\param[out] none \param[out] none
\retval none \retval none
@ -471,8 +474,8 @@ void tli_lut_disable(uint32_t layerx)
} }
/*! /*!
\brief set line mark value \brief set line mark value
\param[in] line_num: line number \param[in] line_num: line number
\param[out] none \param[out] none
\retval none \retval none
*/ */
@ -483,7 +486,7 @@ void tli_line_mark_set(uint16_t line_num)
} }
/*! /*!
\brief get current displayed position \brief get current displayed position
\param[in] none \param[in] none
\param[out] none \param[out] none
\retval position of current pixel \retval position of current pixel
@ -494,13 +497,13 @@ uint32_t tli_current_pos_get(void)
} }
/*! /*!
\brief enable TLI interrupt \brief enable TLI interrupt
\param[in] int_flag: TLI interrupt flags \param[in] int_flag: TLI interrupt flags
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg TLI_INT_LM: line mark interrupt \arg TLI_INT_LM: line mark interrupt
\arg TLI_INT_FE: FIFO error interrupt \arg TLI_INT_FE: FIFO error interrupt
\arg TLI_INT_TE: transaction error interrupt \arg TLI_INT_TE: transaction error interrupt
\arg TLI_INT_LCR: layer configuration reloaded interrupt \arg TLI_INT_LCR: layer configuration reloaded interrupt
\param[out] none \param[out] none
\retval none \retval none
*/ */
@ -510,13 +513,13 @@ void tli_interrupt_enable(uint32_t int_flag)
} }
/*! /*!
\brief disable TLI interrupt \brief disable TLI interrupt
\param[in] int_flag: TLI interrupt flags \param[in] int_flag: TLI interrupt flags
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg TLI_INT_LM: line mark interrupt \arg TLI_INT_LM: line mark interrupt
\arg TLI_INT_FE: FIFO error interrupt \arg TLI_INT_FE: FIFO error interrupt
\arg TLI_INT_TE: transaction error interrupt \arg TLI_INT_TE: transaction error interrupt
\arg TLI_INT_LCR: layer configuration reloaded interrupt \arg TLI_INT_LCR: layer configuration reloaded interrupt
\param[out] none \param[out] none
\retval none \retval none
*/ */
@ -526,7 +529,7 @@ void tli_interrupt_disable(uint32_t int_flag)
} }
/*! /*!
\brief get TLI interrupt flag \brief get TLI interrupt flag
\param[in] int_flag: TLI interrupt flags \param[in] int_flag: TLI interrupt flags
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg TLI_INT_FLAG_LM: line mark interrupt flag \arg TLI_INT_FLAG_LM: line mark interrupt flag
@ -540,9 +543,11 @@ FlagStatus tli_interrupt_flag_get(uint32_t int_flag)
{ {
uint32_t state; uint32_t state;
state = TLI_INTF; state = TLI_INTF;
if(state & int_flag){ if(state & int_flag)
{
state = TLI_INTEN; state = TLI_INTEN;
if(state & int_flag){ if(state & int_flag)
{
return SET; return SET;
} }
} }
@ -550,7 +555,7 @@ FlagStatus tli_interrupt_flag_get(uint32_t int_flag)
} }
/*! /*!
\brief clear TLI interrupt flag \brief clear TLI interrupt flag
\param[in] int_flag: TLI interrupt flags \param[in] int_flag: TLI interrupt flags
one or more parameters can be selected which are shown as below: one or more parameters can be selected which are shown as below:
\arg TLI_INT_FLAG_LM: line mark interrupt flag \arg TLI_INT_FLAG_LM: line mark interrupt flag
@ -569,14 +574,14 @@ void tli_interrupt_flag_clear(uint32_t int_flag)
\brief get TLI flag or state in TLI_INTF register or TLI_STAT register \brief get TLI flag or state in TLI_INTF register or TLI_STAT register
\param[in] flag: TLI flags or states \param[in] flag: TLI flags or states
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg TLI_FLAG_VDE: current VDE state \arg TLI_FLAG_VDE: current VDE state
\arg TLI_FLAG_HDE: current HDE state \arg TLI_FLAG_HDE: current HDE state
\arg TLI_FLAG_VS: current VS status of the TLI \arg TLI_FLAG_VS: current VS status of the TLI
\arg TLI_FLAG_HS: current HS status of the TLI \arg TLI_FLAG_HS: current HS status of the TLI
\arg TLI_FLAG_LM: line mark interrupt flag \arg TLI_FLAG_LM: line mark interrupt flag
\arg TLI_FLAG_FE: FIFO error interrupt flag \arg TLI_FLAG_FE: FIFO error interrupt flag
\arg TLI_FLAG_TE: transaction error interrupt flag \arg TLI_FLAG_TE: transaction error interrupt flag
\arg TLI_FLAG_LCR: layer configuration reloaded interrupt flag \arg TLI_FLAG_LCR: layer configuration reloaded interrupt flag
\param[out] none \param[out] none
\retval FlagStatus: SET or RESET \retval FlagStatus: SET or RESET
*/ */
@ -584,12 +589,14 @@ FlagStatus tli_flag_get(uint32_t flag)
{ {
uint32_t stat; uint32_t stat;
/* choose which register to get flag or state */ /* choose which register to get flag or state */
if(flag >> 31U){ if(flag >> 31U)
{
stat = TLI_INTF; stat = TLI_INTF;
}else{ }else{
stat = TLI_STAT; stat = TLI_STAT;
} }
if(flag & stat){ if(flag & stat)
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;

34
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_tmu.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -70,7 +70,7 @@ void tmu_struct_para_init(tmu_parameter_struct* init_struct)
} }
/*! /*!
\brief initialize TMU \brief initialize TMU
\param[in] init_struct: pointer to init parameter struct \param[in] init_struct: pointer to init parameter struct
mode: TMU_MODE_COS,TMU_MODE_SIN,TMU_MODE_ATAN2,TMU_MODE_MODULUS,TMU_MODE_ATAN, mode: TMU_MODE_COS,TMU_MODE_SIN,TMU_MODE_ATAN2,TMU_MODE_MODULUS,TMU_MODE_ATAN,
TMU_MODE_COSH,TMU_MODE_SINH,TMU_MODE_ATANH,TMU_MODE_LN,TMU_MODE_SQRT TMU_MODE_COSH,TMU_MODE_SINH,TMU_MODE_ATANH,TMU_MODE_LN,TMU_MODE_SQRT
@ -229,7 +229,7 @@ void tmu_two_q31_read(uint32_t* p1, uint32_t* p2)
*/ */
void tmu_two_q15_read(uint16_t* p1, uint16_t* p2) void tmu_two_q15_read(uint16_t* p1, uint16_t* p2)
{ {
uint32_t data; uint32_t data;
data = TMU_ODATA; data = TMU_ODATA;
*p1 = (uint16_t)data; *p1 = (uint16_t)data;
*p2 = (uint16_t)(data >> 16U); *p2 = (uint16_t)(data >> 16U);

40
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_trigsel.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -252,8 +252,8 @@ void trigsel_deinit(void)
\arg TRIGSEL_INPUT_TIMER44_BRKIN: trigger input source TIMER44 BRKIN \arg TRIGSEL_INPUT_TIMER44_BRKIN: trigger input source TIMER44 BRKIN
\arg TRIGSEL_INPUT_TIMER50_TRGO0: trigger input source TIMER50 TRGO0 \arg TRIGSEL_INPUT_TIMER50_TRGO0: trigger input source TIMER50 TRGO0
\arg TRIGSEL_INPUT_TIMER51_TRGO0: trigger input source TIMER51 TRGO0 \arg TRIGSEL_INPUT_TIMER51_TRGO0: trigger input source TIMER51 TRGO0
\arg TRIGSEL_INPUT_RTC_ALARM: trigger input source RTC alarm \arg TRIGSEL_INPUT_RTC_ALARM: trigger input source RTC alarm
\arg TRIGSEL_INPUT_RTC_TPTS: trigger input source RTC TPTS \arg TRIGSEL_INPUT_RTC_TPTS: trigger input source RTC TPTS
\arg TRIGSEL_INPUT_ADC0_WD0_OUT: trigger input source ADC0 watchdog0 output \arg TRIGSEL_INPUT_ADC0_WD0_OUT: trigger input source ADC0 watchdog0 output
\arg TRIGSEL_INPUT_ADC0_WD1_OUT: trigger input source ADC0 watchdog1 output \arg TRIGSEL_INPUT_ADC0_WD1_OUT: trigger input source ADC0 watchdog1 output
\arg TRIGSEL_INPUT_ADC0_WD2_OUT: trigger input source ADC0 watchdog2 output \arg TRIGSEL_INPUT_ADC0_WD2_OUT: trigger input source ADC0 watchdog2 output
@ -275,7 +275,8 @@ void trigsel_deinit(void)
void trigsel_init(trigsel_periph_enum target_periph, trigsel_source_enum trigger_source) void trigsel_init(trigsel_periph_enum target_periph, trigsel_source_enum trigger_source)
{ {
/* if register write is enabled, set trigger source to target peripheral */ /* if register write is enabled, set trigger source to target peripheral */
if (RESET == trigsel_register_lock_get(target_periph)){ if (RESET == trigsel_register_lock_get(target_periph))
{
TRIGSEL_TARGET_REG(target_periph) &= ~TRIGSEL_TARGET_PERIPH_MASK(target_periph); TRIGSEL_TARGET_REG(target_periph) &= ~TRIGSEL_TARGET_PERIPH_MASK(target_periph);
TRIGSEL_TARGET_REG(target_periph) |= ((uint32_t)trigger_source << TRIGSEL_TARGET_PERIPH_SHIFT(target_periph)) & TRIGSEL_TARGET_PERIPH_MASK(target_periph); TRIGSEL_TARGET_REG(target_periph) |= ((uint32_t)trigger_source << TRIGSEL_TARGET_PERIPH_SHIFT(target_periph)) & TRIGSEL_TARGET_PERIPH_MASK(target_periph);
} }
@ -505,7 +506,8 @@ void trigsel_register_lock_set(trigsel_periph_enum target_periph)
*/ */
FlagStatus trigsel_register_lock_get(trigsel_periph_enum target_periph) FlagStatus trigsel_register_lock_get(trigsel_periph_enum target_periph)
{ {
if(RESET != (TRIGSEL_TARGET_REG(target_periph) & TRIGSEL_TARGET_LK)){ if(RESET != (TRIGSEL_TARGET_REG(target_periph) & TRIGSEL_TARGET_LK))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;

40
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_trng.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -156,7 +156,7 @@ void trng_conditioning_disable(void)
void trng_conditioning_input_bitwidth(trng_inmod_enum input_bitwidth) void trng_conditioning_input_bitwidth(trng_inmod_enum input_bitwidth)
{ {
uint32_t trng_config = TRNG_CTL; uint32_t trng_config = TRNG_CTL;
trng_config &= ~TRNG_CTL_INMOD; trng_config &= ~TRNG_CTL_INMOD;
trng_config |= input_bitwidth; trng_config |= input_bitwidth;
TRNG_CTL = trng_config; TRNG_CTL = trng_config;
@ -164,7 +164,7 @@ void trng_conditioning_input_bitwidth(trng_inmod_enum input_bitwidth)
/*! /*!
\brief configure TRNG conditioning module output bitwidth \brief configure TRNG conditioning module output bitwidth
\param[in] output_bitwidth: \param[in] output_bitwidth:
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg TRNG_OUTMOD_128BIT: conditioning module output bitwidth 128bits \arg TRNG_OUTMOD_128BIT: conditioning module output bitwidth 128bits
\arg TRNG_OUTMOD_256BIT: conditioning module output bitwidth 256bits \arg TRNG_OUTMOD_256BIT: conditioning module output bitwidth 256bits
@ -364,7 +364,8 @@ void trng_health_tests_config(uint32_t adpo_threshold, uint8_t rep_threshold)
*/ */
FlagStatus trng_flag_get(trng_flag_enum flag) FlagStatus trng_flag_get(trng_flag_enum flag)
{ {
if(RESET != (TRNG_STAT & flag)){ if(RESET != (TRNG_STAT & flag))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -404,7 +405,8 @@ void trng_interrupt_disable(void)
*/ */
FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag) FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag)
{ {
if(RESET != (TRNG_STAT & int_flag)){ if(RESET != (TRNG_STAT & int_flag))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;

36
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_usart.c
View File

@ -52,7 +52,8 @@ OF SUCH DAMAGE.
*/ */
void usart_deinit(uint32_t usart_periph) void usart_deinit(uint32_t usart_periph)
{ {
switch(usart_periph){ switch(usart_periph)
{
case USART0: case USART0:
/* reset USART0 */ /* reset USART0 */
rcu_periph_reset_enable(RCU_USART0RST); rcu_periph_reset_enable(RCU_USART0RST);
@ -108,7 +109,8 @@ void usart_deinit(uint32_t usart_periph)
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
{ {
uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U;
switch(usart_periph){ switch(usart_periph)
{
/* get clock frequency */ /* get clock frequency */
case USART0: case USART0:
/* get USART0 clock */ /* get USART0 clock */
@ -146,7 +148,8 @@ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
break; break;
} }
if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){ if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD)
{
/* oversampling by 8, configure the value of USART_BAUD */ /* oversampling by 8, configure the value of USART_BAUD */
udiv = ((2U * uclk) + baudval / 2U) / baudval; udiv = ((2U * uclk) + baudval / 2U) / baudval;
intdiv = udiv & 0x0000fff0U; intdiv = udiv & 0x0000fff0U;
@ -319,7 +322,8 @@ void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara)
{ {
USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
/* inverted or not the specified signal */ /* inverted or not the specified signal */
switch(invertpara){ switch(invertpara)
{
case USART_DINV_ENABLE: case USART_DINV_ENABLE:
USART_CTL1(usart_periph) |= USART_CTL1_DINV; USART_CTL1(usart_periph) |= USART_CTL1_DINV;
break; break;
@ -1342,7 +1346,8 @@ uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph)
*/ */
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
{ {
if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag))))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -1374,11 +1379,14 @@ FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
*/ */
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
{ {
if(USART_FLAG_AM1 == flag){ if(USART_FLAG_AM1 == flag)
{
USART_INTC(usart_periph) |= USART_INTC_AMC1; USART_INTC(usart_periph) |= USART_INTC_AMC1;
}else if(USART_FLAG_EPERR == flag){ }else if(USART_FLAG_EPERR == flag)
{
USART_CHC(usart_periph) &= (uint32_t)(~USART_CHC_EPERR); USART_CHC(usart_periph) &= (uint32_t)(~USART_CHC_EPERR);
}else if(USART_FLAG_TFE == flag){ }else if(USART_FLAG_TFE == flag)
{
USART_FCS(usart_periph) |= USART_FCS_TFEC; USART_FCS(usart_periph) |= USART_FCS_TFEC;
}else{ }else{
USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag)); USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag));
@ -1488,7 +1496,8 @@ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_
/* get the corresponding flag bit status */ /* get the corresponding flag bit status */
flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
if(flagstatus && intenable){ if(flagstatus && intenable)
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -1522,11 +1531,14 @@ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_
*/ */
void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag)
{ {
if(USART_INT_FLAG_TFE == int_flag){ if(USART_INT_FLAG_TFE == int_flag)
{
USART_FCS(usart_periph) |= USART_FCS_TFEC; USART_FCS(usart_periph) |= USART_FCS_TFEC;
}else if(USART_INT_FLAG_RFF == int_flag){ }else if(USART_INT_FLAG_RFF == int_flag)
{
USART_FCS(usart_periph) &= (uint32_t)(~USART_FCS_RFFIF); USART_FCS(usart_periph) &= (uint32_t)(~USART_FCS_RFFIF);
}else if(USART_INT_FLAG_RFT == int_flag){ }else if(USART_INT_FLAG_RFT == int_flag)
{
USART_FCS(usart_periph) &= (uint32_t)(~USART_FCS_RFTIF); USART_FCS(usart_periph) &= (uint32_t)(~USART_FCS_RFTIF);
}else{ }else{
USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(int_flag)); USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(int_flag));

41
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_vref.c
View File

@ -1,34 +1,34 @@
/*! /*!
\file gd32h7xx_vref.c \file gd32h7xx_vref.c
\brief VREF driver \brief VREF driver
\version 2024-01-05, V1.2.0, firmware for GD32H7xx \version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/ */
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -100,7 +100,8 @@ void vref_high_impedance_mode_disable(void)
*/ */
FlagStatus vref_status_get(void) FlagStatus vref_status_get(void)
{ {
if(RESET != (VREF_CS & (uint32_t)VREF_CS_VREFRDY)){ if(RESET != (VREF_CS & (uint32_t)VREF_CS_VREFRDY))
{
return SET; return SET;
}else{ }else{
return RESET; return RESET;
@ -108,8 +109,8 @@ FlagStatus vref_status_get(void)
} }
/*! /*!
\brief select the VREF voltage reference \brief select the VREF voltage reference
\param[in] vref_voltage: voltage reference select, \param[in] vref_voltage: voltage reference select,
only one parameter can be selected which is shown as below: only one parameter can be selected which is shown as below:
\arg VREF_VOLTAGE_SEL_2_5V: VREF voltage reference select 2.5 V \arg VREF_VOLTAGE_SEL_2_5V: VREF voltage reference select 2.5 V
\arg VREF_VOLTAGE_SEL_2_048V: VREF voltage reference select 2.048 V \arg VREF_VOLTAGE_SEL_2_048V: VREF voltage reference select 2.048 V
@ -125,7 +126,7 @@ void vref_voltage_select(uint32_t vref_voltage)
/* clear old value */ /* clear old value */
temp &= ~(uint32_t)VREF_VOLTAGE_SEL_1_5V; temp &= ~(uint32_t)VREF_VOLTAGE_SEL_1_5V;
temp |= (uint32_t)vref_voltage; temp |= (uint32_t)vref_voltage;
VREF_CS = temp; VREF_CS = temp;
} }

39
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_wwdgt.c
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -36,9 +36,9 @@ OF SUCH DAMAGE.
#include "gd32h7xx_wwdgt.h" #include "gd32h7xx_wwdgt.h"
/* WWDGT_CTL register value */ /* WWDGT_CTL register value */
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) #define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
/* WWDGT_CFG register value */ /* WWDGT_CFG register value */
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) #define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
/*! /*!
\brief reset the window watchdog timer configuration \brief reset the window watchdog timer configuration
@ -75,7 +75,7 @@ void wwdgt_counter_update(uint16_t counter_value)
} }
/*! /*!
\brief configure counter value, window value, and prescaler divider value \brief configure counter value, window value, and prescaler divider value
\param[in] counter: 0x0000 - 0x007F \param[in] counter: 0x0000 - 0x007F
\param[in] window: 0x0000 - 0x007F \param[in] window: 0x0000 - 0x007F
\param[in] prescaler: WWDGT prescaler value \param[in] prescaler: WWDGT prescaler value
@ -112,7 +112,8 @@ void wwdgt_interrupt_enable(void)
*/ */
FlagStatus wwdgt_flag_get(void) FlagStatus wwdgt_flag_get(void)
{ {
if (RESET != (WWDGT_STAT & WWDGT_STAT_EWIF)){ if (RESET != (WWDGT_STAT & WWDGT_STAT_EWIF))
{
return SET; return SET;
} }

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/audio/Include/audio_core.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/audio/Include/audio_out_itf.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

274
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/audio/Source/audio_core.c
View File

@ -84,9 +84,9 @@ usb_class_core usbd_audio_cb = {
/* USB standard device descriptor */ /* USB standard device descriptor */
__ALIGN_BEGIN const usb_desc_dev audio_dev_desc __ALIGN_END = __ALIGN_BEGIN const usb_desc_dev audio_dev_desc __ALIGN_END =
{ {
.header = .header =
{ {
.bLength = USB_DEV_DESC_LEN, .bLength = USB_DEV_DESC_LEN,
.bDescriptorType = USB_DESCTYPE_DEV .bDescriptorType = USB_DESCTYPE_DEV
}, },
.bcdUSB = 0x0200U, .bcdUSB = 0x0200U,
@ -104,14 +104,14 @@ __ALIGN_BEGIN const usb_desc_dev audio_dev_desc __ALIGN_END =
}; };
/* USB device configuration descriptor */ /* USB device configuration descriptor */
__ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END = __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
{ {
.config = .config =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_config), .bLength = sizeof(usb_desc_config),
.bDescriptorType = USB_DESCTYPE_CONFIG .bDescriptorType = USB_DESCTYPE_CONFIG
}, },
.wTotalLength = AD_CONFIG_DESC_SET_LEN, .wTotalLength = AD_CONFIG_DESC_SET_LEN,
.bNumInterfaces = 0x01U + CONFIG_DESC_AS_ITF_COUNT, .bNumInterfaces = 0x01U + CONFIG_DESC_AS_ITF_COUNT,
@ -121,12 +121,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.bMaxPower = 0x32U .bMaxPower = 0x32U
}, },
.std_itf = .std_itf =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_itf), .bLength = sizeof(usb_desc_itf),
.bDescriptorType = USB_DESCTYPE_ITF .bDescriptorType = USB_DESCTYPE_ITF
}, },
.bInterfaceNumber = 0x00U, .bInterfaceNumber = 0x00U,
.bAlternateSetting = 0x00U, .bAlternateSetting = 0x00U,
@ -137,12 +137,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.iInterface = 0x00U .iInterface = 0x00U
}, },
.ac_itf = .ac_itf =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_AC_itf), .bLength = sizeof(usb_desc_AC_itf),
.bDescriptorType = AD_DESCTYPE_INTERFACE .bDescriptorType = AD_DESCTYPE_INTERFACE
}, },
.bDescriptorSubtype = 0x01U, .bDescriptorSubtype = 0x01U,
.bcdADC = 0x0100U, .bcdADC = 0x0100U,
@ -158,11 +158,11 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
}, },
#ifdef USE_USB_AD_MICPHONE #ifdef USE_USB_AD_MICPHONE
.mic_in_terminal = .mic_in_terminal =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_input_terminal), .bLength = sizeof(usb_desc_input_terminal),
.bDescriptorType = AD_DESCTYPE_INTERFACE .bDescriptorType = AD_DESCTYPE_INTERFACE
}, },
.bDescriptorSubtype = 0x02U, .bDescriptorSubtype = 0x02U,
@ -175,12 +175,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.iTerminal = 0x00U .iTerminal = 0x00U
}, },
.mic_feature_unit = .mic_feature_unit =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_mono_feature_unit), .bLength = sizeof(usb_desc_mono_feature_unit),
.bDescriptorType = AD_DESCTYPE_INTERFACE .bDescriptorType = AD_DESCTYPE_INTERFACE
}, },
.bDescriptorSubtype = AD_CONTROL_FEATURE_UNIT, .bDescriptorSubtype = AD_CONTROL_FEATURE_UNIT,
.bUnitID = AD_IN_STREAMING_CTRL, .bUnitID = AD_IN_STREAMING_CTRL,
@ -191,11 +191,11 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.iFeature = 0x00U .iFeature = 0x00U
}, },
.mic_out_terminal = .mic_out_terminal =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_output_terminal), .bLength = sizeof(usb_desc_output_terminal),
.bDescriptorType = AD_DESCTYPE_INTERFACE .bDescriptorType = AD_DESCTYPE_INTERFACE
}, },
.bDescriptorSubtype = AD_CONTROL_OUTPUT_TERMINAL, .bDescriptorSubtype = AD_CONTROL_OUTPUT_TERMINAL,
@ -208,11 +208,11 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
#endif /* USE_USB_AD_MICPHONE */ #endif /* USE_USB_AD_MICPHONE */
#ifdef USE_USB_AD_SPEAKER #ifdef USE_USB_AD_SPEAKER
.speak_in_terminal = .speak_in_terminal =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_input_terminal), .bLength = sizeof(usb_desc_input_terminal),
.bDescriptorType = AD_DESCTYPE_INTERFACE .bDescriptorType = AD_DESCTYPE_INTERFACE
}, },
.bDescriptorSubtype = AD_CONTROL_INPUT_TERMINAL, .bDescriptorSubtype = AD_CONTROL_INPUT_TERMINAL,
@ -225,12 +225,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.iTerminal = 0x00U .iTerminal = 0x00U
}, },
.speak_feature_unit = .speak_feature_unit =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_mono_feature_unit), .bLength = sizeof(usb_desc_mono_feature_unit),
.bDescriptorType = AD_DESCTYPE_INTERFACE .bDescriptorType = AD_DESCTYPE_INTERFACE
}, },
.bDescriptorSubtype = AD_CONTROL_FEATURE_UNIT, .bDescriptorSubtype = AD_CONTROL_FEATURE_UNIT,
.bUnitID = AD_OUT_STREAMING_CTRL, .bUnitID = AD_OUT_STREAMING_CTRL,
@ -241,11 +241,11 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.iFeature = 0x00U .iFeature = 0x00U
}, },
.speak_out_terminal = .speak_out_terminal =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_output_terminal), .bLength = sizeof(usb_desc_output_terminal),
.bDescriptorType = AD_DESCTYPE_INTERFACE .bDescriptorType = AD_DESCTYPE_INTERFACE
}, },
.bDescriptorSubtype = AD_CONTROL_OUTPUT_TERMINAL, .bDescriptorSubtype = AD_CONTROL_OUTPUT_TERMINAL,
@ -258,12 +258,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
#endif /* USE_USB_AD_SPEAKER */ #endif /* USE_USB_AD_SPEAKER */
#ifdef USE_USB_AD_MICPHONE #ifdef USE_USB_AD_MICPHONE
.mic_std_as_itf_zeroband = .mic_std_as_itf_zeroband =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_itf), .bLength = sizeof(usb_desc_itf),
.bDescriptorType = USB_DESCTYPE_ITF .bDescriptorType = USB_DESCTYPE_ITF
}, },
.bInterfaceNumber = 0x01U, .bInterfaceNumber = 0x01U,
.bAlternateSetting = 0x00U, .bAlternateSetting = 0x00U,
@ -274,12 +274,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.iInterface = 0x00U .iInterface = 0x00U
}, },
.mic_std_as_itf_opera = .mic_std_as_itf_opera =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_itf), .bLength = sizeof(usb_desc_itf),
.bDescriptorType = USB_DESCTYPE_ITF .bDescriptorType = USB_DESCTYPE_ITF
}, },
.bInterfaceNumber = 0x01U, .bInterfaceNumber = 0x01U,
.bAlternateSetting = 0x01U, .bAlternateSetting = 0x01U,
@ -290,12 +290,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.iInterface = 0x00U .iInterface = 0x00U
}, },
.mic_as_itf = .mic_as_itf =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_AS_itf), .bLength = sizeof(usb_desc_AS_itf),
.bDescriptorType = AD_DESCTYPE_INTERFACE .bDescriptorType = AD_DESCTYPE_INTERFACE
}, },
.bDescriptorSubtype = AD_STREAMING_GENERAL, .bDescriptorSubtype = AD_STREAMING_GENERAL,
.bTerminalLink = 0x03U, .bTerminalLink = 0x03U,
@ -303,12 +303,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.wFormatTag = 0x0001U, .wFormatTag = 0x0001U,
}, },
.mic_format_typeI = .mic_format_typeI =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_format_type), .bLength = sizeof(usb_desc_format_type),
.bDescriptorType = AD_DESCTYPE_INTERFACE .bDescriptorType = AD_DESCTYPE_INTERFACE
}, },
.bDescriptorSubtype = AD_STREAMING_FORMAT_TYPE, .bDescriptorSubtype = AD_STREAMING_FORMAT_TYPE,
.bFormatType = AD_FORMAT_TYPE_I, .bFormatType = AD_FORMAT_TYPE_I,
@ -321,12 +321,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.bSamFreq[2] = USBD_MIC_FREQ >> 16U .bSamFreq[2] = USBD_MIC_FREQ >> 16U
}, },
.mic_std_endpoint = .mic_std_endpoint =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_std_ep), .bLength = sizeof(usb_desc_std_ep),
.bDescriptorType = USB_DESCTYPE_EP .bDescriptorType = USB_DESCTYPE_EP
}, },
.bEndpointAddress = AD_IN_EP, .bEndpointAddress = AD_IN_EP,
.bmAttributes = USB_ENDPOINT_TYPE_ISOCHRONOUS, .bmAttributes = USB_ENDPOINT_TYPE_ISOCHRONOUS,
@ -336,12 +336,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.bSynchAddress = 0x00U .bSynchAddress = 0x00U
}, },
.mic_as_endpoint = .mic_as_endpoint =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_AS_ep), .bLength = sizeof(usb_desc_AS_ep),
.bDescriptorType = AD_DESCTYPE_ENDPOINT .bDescriptorType = AD_DESCTYPE_ENDPOINT
}, },
.bDescriptorSubtype = AD_ENDPOINT_GENERAL, .bDescriptorSubtype = AD_ENDPOINT_GENERAL,
.bmAttributes = 0x00U, .bmAttributes = 0x00U,
@ -351,12 +351,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
#endif /* USE_USB_AD_MICPHONE */ #endif /* USE_USB_AD_MICPHONE */
#ifdef USE_USB_AD_SPEAKER #ifdef USE_USB_AD_SPEAKER
.speak_std_as_itf_zeroband = .speak_std_as_itf_zeroband =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_itf), .bLength = sizeof(usb_desc_itf),
.bDescriptorType = USB_DESCTYPE_ITF .bDescriptorType = USB_DESCTYPE_ITF
}, },
.bInterfaceNumber = 0x02U, .bInterfaceNumber = 0x02U,
.bAlternateSetting = 0x00U, .bAlternateSetting = 0x00U,
@ -367,12 +367,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.iInterface = 0x00U .iInterface = 0x00U
}, },
.speak_std_as_itf_opera = .speak_std_as_itf_opera =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_itf), .bLength = sizeof(usb_desc_itf),
.bDescriptorType = USB_DESCTYPE_ITF .bDescriptorType = USB_DESCTYPE_ITF
}, },
.bInterfaceNumber = 0x02U, .bInterfaceNumber = 0x02U,
.bAlternateSetting = 0x01U, .bAlternateSetting = 0x01U,
@ -383,12 +383,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.iInterface = 0x00U .iInterface = 0x00U
}, },
.speak_as_itf = .speak_as_itf =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_AS_itf), .bLength = sizeof(usb_desc_AS_itf),
.bDescriptorType = AD_DESCTYPE_INTERFACE .bDescriptorType = AD_DESCTYPE_INTERFACE
}, },
.bDescriptorSubtype = AD_STREAMING_GENERAL, .bDescriptorSubtype = AD_STREAMING_GENERAL,
.bTerminalLink = 0x04U, .bTerminalLink = 0x04U,
@ -396,12 +396,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.wFormatTag = 0x0001U, .wFormatTag = 0x0001U,
}, },
.speak_format_typeI = .speak_format_typeI =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_format_type), .bLength = sizeof(usb_desc_format_type),
.bDescriptorType = AD_DESCTYPE_INTERFACE .bDescriptorType = AD_DESCTYPE_INTERFACE
}, },
.bDescriptorSubtype = AD_STREAMING_FORMAT_TYPE, .bDescriptorSubtype = AD_STREAMING_FORMAT_TYPE,
.bFormatType = AD_FORMAT_TYPE_I, .bFormatType = AD_FORMAT_TYPE_I,
@ -414,12 +414,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.bSamFreq[2] = USBD_SPEAKER_FREQ >> 16U .bSamFreq[2] = USBD_SPEAKER_FREQ >> 16U
}, },
.speak_std_endpoint = .speak_std_endpoint =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_std_ep), .bLength = sizeof(usb_desc_std_ep),
.bDescriptorType = USB_DESCTYPE_EP .bDescriptorType = USB_DESCTYPE_EP
}, },
.bEndpointAddress = AD_OUT_EP, .bEndpointAddress = AD_OUT_EP,
.bmAttributes = USB_EP_ATTR_ISO | USB_EP_ATTR_ASYNC, .bmAttributes = USB_EP_ATTR_ISO | USB_EP_ATTR_ASYNC,
@ -429,12 +429,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.bSynchAddress = AD_FEEDBACK_IN_EP, .bSynchAddress = AD_FEEDBACK_IN_EP,
}, },
.speak_as_endpoint = .speak_as_endpoint =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_AS_ep), .bLength = sizeof(usb_desc_AS_ep),
.bDescriptorType = AD_DESCTYPE_ENDPOINT .bDescriptorType = AD_DESCTYPE_ENDPOINT
}, },
.bDescriptorSubtype = AD_ENDPOINT_GENERAL, .bDescriptorSubtype = AD_ENDPOINT_GENERAL,
.bmAttributes = 0x00U, .bmAttributes = 0x00U,
@ -442,12 +442,12 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
.wLockDelay = 0x0000U, .wLockDelay = 0x0000U,
}, },
.speak_feedback_endpoint = .speak_feedback_endpoint =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_FeedBack_ep), .bLength = sizeof(usb_desc_FeedBack_ep),
.bDescriptorType = USB_DESCTYPE_EP .bDescriptorType = USB_DESCTYPE_EP
}, },
.bEndpointAddress = AD_FEEDBACK_IN_EP, .bEndpointAddress = AD_FEEDBACK_IN_EP,
.bmAttributes = USB_EP_ATTR_ISO | USB_EP_ATTR_ASYNC | USB_EP_ATTR_FEEDBACK, .bmAttributes = USB_EP_ATTR_ISO | USB_EP_ATTR_ASYNC | USB_EP_ATTR_FEEDBACK,
@ -460,11 +460,11 @@ __ALIGN_BEGIN const usb_desc_config_set audio_config_set __ALIGN_END =
}; };
/* USB language ID descriptor */ /* USB language ID descriptor */
static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END =
{ {
.header = .header =
{ {
.bLength = sizeof(usb_desc_LANGID), .bLength = sizeof(usb_desc_LANGID),
.bDescriptorType = USB_DESCTYPE_STR .bDescriptorType = USB_DESCTYPE_STR
}, },
@ -472,39 +472,39 @@ static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END =
}; };
/* USB manufacture string */ /* USB manufacture string */
static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END =
{ {
.header = .header =
{ {
.bLength = USB_STRING_LEN(10), .bLength = USB_STRING_LEN(10),
.bDescriptorType = USB_DESCTYPE_STR, .bDescriptorType = USB_DESCTYPE_STR,
}, },
.unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'}
}; };
/* USB product string */ /* USB product string */
static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END =
{ {
.header = .header =
{ {
.bLength = USB_STRING_LEN(14), .bLength = USB_STRING_LEN(14),
.bDescriptorType = USB_DESCTYPE_STR, .bDescriptorType = USB_DESCTYPE_STR,
}, },
.unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'A', 'u', 'd', 'i', 'o'} .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'A', 'u', 'd', 'i', 'o'}
}; };
/* USBD serial string */ /* USBD serial string */
static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END =
{ {
.header = .header =
{ {
.bLength = USB_STRING_LEN(12), .bLength = USB_STRING_LEN(12),
.bDescriptorType = USB_DESCTYPE_STR, .bDescriptorType = USB_DESCTYPE_STR,
} }
}; };
/* USB string descriptor */ /* USB string descriptor */
void *const usbd_audio_strings[] = void *const usbd_audio_strings[] =
{ {
[STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc,
[STR_IDX_MFC] = (uint8_t *)&manufacturer_string, [STR_IDX_MFC] = (uint8_t *)&manufacturer_string,
@ -539,7 +539,7 @@ static uint8_t audio_init (usb_dev *udev, uint8_t config_index)
.bEndpointAddress = std_ep.bEndpointAddress, .bEndpointAddress = std_ep.bEndpointAddress,
.bmAttributes = std_ep.bmAttributes, .bmAttributes = std_ep.bmAttributes,
.wMaxPacketSize = std_ep.wMaxPacketSize, .wMaxPacketSize = std_ep.wMaxPacketSize,
.bInterval = std_ep.bInterval .bInterval = std_ep.bInterval
}; };
/* initialize TX endpoint */ /* initialize TX endpoint */
@ -559,7 +559,7 @@ static uint8_t audio_init (usb_dev *udev, uint8_t config_index)
.bEndpointAddress = std_ep.bEndpointAddress, .bEndpointAddress = std_ep.bEndpointAddress,
.bmAttributes = std_ep.bmAttributes, .bmAttributes = std_ep.bmAttributes,
.wMaxPacketSize = SPEAKER_OUT_MAX_PACKET, .wMaxPacketSize = SPEAKER_OUT_MAX_PACKET,
.bInterval = std_ep.bInterval .bInterval = std_ep.bInterval
}; };
/* initialize RX endpoint */ /* initialize RX endpoint */
@ -569,7 +569,8 @@ static uint8_t audio_init (usb_dev *udev, uint8_t config_index)
usbd_ep_recev (udev, AD_OUT_EP, audio_handler.usb_rx_buffer, SPEAKER_OUT_MAX_PACKET); usbd_ep_recev (udev, AD_OUT_EP, audio_handler.usb_rx_buffer, SPEAKER_OUT_MAX_PACKET);
/* initialize the audio output hardware layer */ /* initialize the audio output hardware layer */
if (USBD_OK != audio_out_fops.audio_init(USBD_SPEAKER_FREQ, DEFAULT_VOLUME)) { if (USBD_OK != audio_out_fops.audio_init(USBD_SPEAKER_FREQ, DEFAULT_VOLUME))
{
return USBD_FAIL; return USBD_FAIL;
} }
@ -580,7 +581,7 @@ static uint8_t audio_init (usb_dev *udev, uint8_t config_index)
.bEndpointAddress = feedback_ep.bEndpointAddress, .bEndpointAddress = feedback_ep.bEndpointAddress,
.bmAttributes = feedback_ep.bmAttributes, .bmAttributes = feedback_ep.bmAttributes,
.wMaxPacketSize = feedback_ep.wMaxPacketSize, .wMaxPacketSize = feedback_ep.wMaxPacketSize,
.bInterval = feedback_ep.bInterval .bInterval = feedback_ep.bInterval
}; };
/* initialize Tx endpoint */ /* initialize Tx endpoint */
@ -610,7 +611,8 @@ static uint8_t audio_deinit (usb_dev *udev, uint8_t config_index)
usbd_ep_clear(udev, AD_OUT_EP); usbd_ep_clear(udev, AD_OUT_EP);
/* deinitialize the audio output hardware layer */ /* deinitialize the audio output hardware layer */
if (USBD_OK != audio_out_fops.audio_deinit()) { if (USBD_OK != audio_out_fops.audio_deinit())
{
return USBD_FAIL; return USBD_FAIL;
} }
@ -635,7 +637,8 @@ static uint8_t audio_req_handler (usb_dev *udev, usb_req *req)
usb_transc *transc_in = &udev->dev.transc_in[0]; usb_transc *transc_in = &udev->dev.transc_in[0];
usb_transc *transc_out = &udev->dev.transc_out[0]; usb_transc *transc_out = &udev->dev.transc_out[0];
switch (req->bRequest) { switch (req->bRequest)
{
case AD_REQ_GET_CUR: case AD_REQ_GET_CUR:
transc_in->xfer_buf = audio_handler.audioctl; transc_in->xfer_buf = audio_handler.audioctl;
transc_in->remain_len = req->wLength; transc_in->remain_len = req->wLength;
@ -644,7 +647,8 @@ static uint8_t audio_req_handler (usb_dev *udev, usb_req *req)
break; break;
case AD_REQ_SET_CUR: case AD_REQ_SET_CUR:
if (req->wLength) { if (req->wLength)
{
transc_out->xfer_buf = audio_handler.audioctl; transc_out->xfer_buf = audio_handler.audioctl;
transc_out->remain_len = req->wLength; transc_out->remain_len = req->wLength;
@ -696,8 +700,10 @@ static uint8_t audio_set_intf(usb_dev *udev, usb_req *req)
{ {
udev->dev.class_core->alter_set = req->wValue; udev->dev.class_core->alter_set = req->wValue;
if(0xFF != req->wValue){ if(0xFF != req->wValue)
if (req->wValue != 0){ {
if (req->wValue != 0)
{
/* deinit audio handler */ /* deinit audio handler */
memset((void *)&audio_handler, 0, sizeof(usbd_audio_handler)); memset((void *)&audio_handler, 0, sizeof(usbd_audio_handler));
@ -739,11 +745,13 @@ static uint8_t audio_ctlx_out (usb_dev *udev)
#ifdef USE_USB_AD_SPEAKER #ifdef USE_USB_AD_SPEAKER
/* handles audio control requests data */ /* handles audio control requests data */
/* check if an audio_control request has been issued */ /* check if an audio_control request has been issued */
if (AD_REQ_SET_CUR == udev->dev.class_core->command) { if (AD_REQ_SET_CUR == udev->dev.class_core->command)
{
/* in this driver, to simplify code, only SET_CUR request is managed */ /* in this driver, to simplify code, only SET_CUR request is managed */
/* check for which addressed unit the audio_control request has been issued */ /* check for which addressed unit the audio_control request has been issued */
if (AD_OUT_STREAMING_CTRL == audio_handler.audioctl_unit) { if (AD_OUT_STREAMING_CTRL == audio_handler.audioctl_unit)
{
/* in this driver, to simplify code, only one unit is manage */ /* in this driver, to simplify code, only one unit is manage */
/* reset the audioctl_cmd variable to prevent re-entering this function */ /* reset the audioctl_cmd variable to prevent re-entering this function */
@ -767,8 +775,10 @@ static uint8_t audio_ctlx_out (usb_dev *udev)
static uint8_t audio_data_in (usb_dev *udev, uint8_t ep_num) static uint8_t audio_data_in (usb_dev *udev, uint8_t ep_num)
{ {
#ifdef USE_USB_AD_MICPHONE #ifdef USE_USB_AD_MICPHONE
if(ep_num == EP_ID(AD_IN_EP)){ if(ep_num == EP_ID(AD_IN_EP))
if(count_data < LENGTH_DATA){ {
if(count_data < LENGTH_DATA)
{
/* Prepare next buffer to be sent: dummy data */ /* Prepare next buffer to be sent: dummy data */
usbd_ep_send(udev, AD_IN_EP,(uint8_t*)&wavetestdata[count_data],MIC_IN_PACKET); usbd_ep_send(udev, AD_IN_EP,(uint8_t*)&wavetestdata[count_data],MIC_IN_PACKET);
count_data += MIC_IN_PACKET; count_data += MIC_IN_PACKET;
@ -780,7 +790,8 @@ static uint8_t audio_data_in (usb_dev *udev, uint8_t ep_num)
#endif /* USE_USB_AD_MICPHONE */ #endif /* USE_USB_AD_MICPHONE */
#ifdef USE_USB_AD_SPEAKER #ifdef USE_USB_AD_SPEAKER
if(ep_num == EP_ID(AD_FEEDBACK_IN_EP)){ if(ep_num == EP_ID(AD_FEEDBACK_IN_EP))
{
/* calculate feedback actual freq */ /* calculate feedback actual freq */
audio_handler.actual_freq = usbd_audio_spk_get_feedback(udev); audio_handler.actual_freq = usbd_audio_spk_get_feedback(udev);
get_feedback_fs_rate(audio_handler.actual_freq, audio_handler.feedback_freq); get_feedback_fs_rate(audio_handler.actual_freq, audio_handler.feedback_freq);
@ -806,25 +817,30 @@ static uint8_t audio_data_out (usb_dev *udev, uint8_t ep_num)
/* get receive length */ /* get receive length */
usb_rx_length = ((usb_core_driver *)udev)->dev.transc_out[ep_num].xfer_count; usb_rx_length = ((usb_core_driver *)udev)->dev.transc_out[ep_num].xfer_count;
if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){ if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr)
{
audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr;
}else{ }else{
audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr;
} }
/* free buffer enough to save rx data */ /* free buffer enough to save rx data */
if(audio_handler.buf_free_size > usb_rx_length){ if(audio_handler.buf_free_size > usb_rx_length)
if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){ {
if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr)
{
tail_len = audio_handler.isoc_out_buff + TOTAL_OUT_BUF_SIZE - audio_handler.isoc_out_wrptr; tail_len = audio_handler.isoc_out_buff + TOTAL_OUT_BUF_SIZE - audio_handler.isoc_out_wrptr;
if(tail_len >= usb_rx_length){ if(tail_len >= usb_rx_length)
{
memcpy(audio_handler.isoc_out_wrptr, audio_handler.usb_rx_buffer, usb_rx_length); memcpy(audio_handler.isoc_out_wrptr, audio_handler.usb_rx_buffer, usb_rx_length);
/* increment the buffer pointer */ /* increment the buffer pointer */
audio_handler.isoc_out_wrptr += usb_rx_length; audio_handler.isoc_out_wrptr += usb_rx_length;
/* increment the Buffer pointer or roll it back when all buffers are full */ /* increment the Buffer pointer or roll it back when all buffers are full */
if(audio_handler.isoc_out_wrptr >= (audio_handler.isoc_out_buff + TOTAL_OUT_BUF_SIZE)){ if(audio_handler.isoc_out_wrptr >= (audio_handler.isoc_out_buff + TOTAL_OUT_BUF_SIZE))
{
/* all buffers are full: roll back */ /* all buffers are full: roll back */
audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff; audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff;
} }
@ -845,24 +861,27 @@ static uint8_t audio_data_out (usb_dev *udev, uint8_t ep_num)
} }
} }
/* Toggle the frame index */ /* Toggle the frame index */
udev->dev.transc_out[ep_num].frame_num = (udev->dev.transc_out[ep_num].frame_num)? 0U:1U; udev->dev.transc_out[ep_num].frame_num = (udev->dev.transc_out[ep_num].frame_num)? 0U:1U;
/* prepare out endpoint to receive next audio packet */ /* prepare out endpoint to receive next audio packet */
usbd_ep_recev (udev, AD_OUT_EP, audio_handler.usb_rx_buffer, SPEAKER_OUT_MAX_PACKET); usbd_ep_recev (udev, AD_OUT_EP, audio_handler.usb_rx_buffer, SPEAKER_OUT_MAX_PACKET);
if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){ if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr)
{
audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr;
}else{ }else{
audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr;
} }
if ((0U == audio_handler.play_flag) && (audio_handler.buf_free_size < TOTAL_OUT_BUF_SIZE/2)) { if ((0U == audio_handler.play_flag) && (audio_handler.buf_free_size < TOTAL_OUT_BUF_SIZE/2))
{
/* enable start of streaming */ /* enable start of streaming */
audio_handler.play_flag = 1U; audio_handler.play_flag = 1U;
/* initialize the audio output hardware layer */ /* initialize the audio output hardware layer */
if (USBD_OK != audio_out_fops.audio_cmd(audio_handler.isoc_out_rdptr, SPEAKER_OUT_MAX_PACKET/2, AD_CMD_PLAY)) { if (USBD_OK != audio_out_fops.audio_cmd(audio_handler.isoc_out_rdptr, SPEAKER_OUT_MAX_PACKET/2, AD_CMD_PLAY))
{
return USBD_FAIL; return USBD_FAIL;
} }
@ -924,16 +943,19 @@ static uint32_t usbd_audio_spk_get_feedback(usb_dev *udev)
static uint32_t fb_freq; static uint32_t fb_freq;
/* calculate buffer free size */ /* calculate buffer free size */
if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){ if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr)
{
audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr;
}else{ }else{
audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr;
} }
/* calculate feedback frequency */ /* calculate feedback frequency */
if(audio_handler.buf_free_size <= (TOTAL_OUT_BUF_SIZE/4)){ if(audio_handler.buf_free_size <= (TOTAL_OUT_BUF_SIZE/4))
{
fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ) - FEEDBACK_FREQ_OFFSET; fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ) - FEEDBACK_FREQ_OFFSET;
}else if(audio_handler.buf_free_size >= (TOTAL_OUT_BUF_SIZE*3/4)){ }else if(audio_handler.buf_free_size >= (TOTAL_OUT_BUF_SIZE*3/4))
{
fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ) + FEEDBACK_FREQ_OFFSET; fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ) + FEEDBACK_FREQ_OFFSET;
}else{ }else{
fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ); fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ);

23
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/audio/Source/audio_out_itf.c
View File

@ -43,7 +43,7 @@ static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd);
/* local variable defines */ /* local variable defines */
static uint8_t audio_state = AD_STATE_INACTIVE; static uint8_t audio_state = AD_STATE_INACTIVE;
audio_fops_struct audio_out_fops = audio_fops_struct audio_out_fops =
{ {
.audio_init = init, .audio_init = init,
.audio_deinit = deinit, .audio_deinit = deinit,
@ -62,7 +62,8 @@ static uint8_t init (uint32_t audio_freq, uint32_t volume)
static uint32_t initialized = 0U; static uint32_t initialized = 0U;
/* check if the low layer has already been initialized */ /* check if the low layer has already been initialized */
if (0U == initialized) { if (0U == initialized)
{
/* initialize GPIO */ /* initialize GPIO */
codec_gpio_init(); codec_gpio_init();
@ -111,24 +112,28 @@ static uint8_t deinit (void)
static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd) static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd)
{ {
/* check the current state */ /* check the current state */
if ((AD_STATE_INACTIVE == audio_state) || (AD_STATE_ERROR == audio_state)) { if ((AD_STATE_INACTIVE == audio_state) || (AD_STATE_ERROR == audio_state))
{
audio_state = AD_STATE_ERROR; audio_state = AD_STATE_ERROR;
return AD_FAIL; return AD_FAIL;
} }
switch (cmd) { switch (cmd)
{
/* process the play command */ /* process the play command */
case AD_CMD_PLAY: case AD_CMD_PLAY:
/* if current state is active or stopped */ /* if current state is active or stopped */
if ((AD_STATE_ACTIVE == audio_state) || \ if ((AD_STATE_ACTIVE == audio_state) || \
(AD_STATE_STOPPED == audio_state) || \ (AD_STATE_STOPPED == audio_state) || \
(AD_STATE_PLAYING == audio_state)) { (AD_STATE_PLAYING == audio_state))
{
audio_play((uint32_t)pbuf, size); audio_play((uint32_t)pbuf, size);
audio_state = AD_STATE_PLAYING; audio_state = AD_STATE_PLAYING;
return AD_OK; return AD_OK;
} else if (AD_STATE_PAUSED == audio_state) { } else if (AD_STATE_PAUSED == audio_state)
{
audio_pause_resume(AD_RESUME, (uint32_t)pbuf, (size/2)); audio_pause_resume(AD_RESUME, (uint32_t)pbuf, (size/2));
audio_state = AD_STATE_PLAYING; audio_state = AD_STATE_PLAYING;
@ -139,7 +144,8 @@ static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd)
/* process the stop command */ /* process the stop command */
case AD_CMD_STOP: case AD_CMD_STOP:
if (AD_STATE_PLAYING != audio_state) { if (AD_STATE_PLAYING != audio_state)
{
/* unsupported command */ /* unsupported command */
return AD_FAIL; return AD_FAIL;
} else { } else {
@ -151,7 +157,8 @@ static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd)
/* process the pause command */ /* process the pause command */
case AD_CMD_PAUSE: case AD_CMD_PAUSE:
if (AD_STATE_PLAYING != audio_state) { if (AD_STATE_PLAYING != audio_state)
{
/* unsupported command */ /* unsupported command */
return AD_FAIL; return AD_FAIL;
} else { } else {

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/cdc/Include/cdc_acm_core.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

21
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/cdc/Source/cdc_acm_core.c
View File

@ -277,10 +277,12 @@ usb_class_core cdc_class = {
*/ */
uint8_t cdc_acm_check_ready(usb_dev *udev) uint8_t cdc_acm_check_ready(usb_dev *udev)
{ {
if(udev->dev.class_data[CDC_COM_INTERFACE] != NULL) { if(udev->dev.class_data[CDC_COM_INTERFACE] != NULL)
{
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE];
if((1U == cdc->packet_receive) && (1U == cdc->packet_sent)) { if((1U == cdc->packet_receive) && (1U == cdc->packet_sent))
{
return 0U; return 0U;
} }
} }
@ -298,7 +300,8 @@ void cdc_acm_data_send(usb_dev *udev)
{ {
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE];
if(0U != cdc->receive_length) { if(0U != cdc->receive_length)
{
cdc->packet_sent = 0U; cdc->packet_sent = 0U;
usbd_ep_send(udev, CDC_DATA_IN_EP, (uint8_t *)(cdc->data), cdc->receive_length); usbd_ep_send(udev, CDC_DATA_IN_EP, (uint8_t *)(cdc->data), cdc->receive_length);
@ -348,7 +351,8 @@ static uint8_t cdc_acm_init(usb_dev *udev, uint8_t config_index)
cdc_handler.packet_sent = 1U; cdc_handler.packet_sent = 1U;
cdc_handler.receive_length = 0U; cdc_handler.receive_length = 0U;
cdc_handler.line_coding = (acm_line) { cdc_handler.line_coding = (acm_line)
{
.dwDTERate = 115200, .dwDTERate = 115200,
.bCharFormat = 0, .bCharFormat = 0,
.bParityType = 0, .bParityType = 0,
@ -392,7 +396,8 @@ static uint8_t cdc_acm_req(usb_dev *udev, usb_req *req)
usb_transc *transc = NULL; usb_transc *transc = NULL;
switch(req->bRequest) { switch(req->bRequest)
{
case SEND_ENCAPSULATED_COMMAND: case SEND_ENCAPSULATED_COMMAND:
/* no operation for this driver */ /* no operation for this driver */
break; break;
@ -457,7 +462,8 @@ static uint8_t cdc_ctlx_out(usb_dev *udev)
{ {
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE];
if(NO_CMD != udev->dev.class_core->alter_set) { if(NO_CMD != udev->dev.class_core->alter_set)
{
/* process the command data */ /* process the command data */
cdc->line_coding.dwDTERate = (uint32_t)((uint32_t)cdc->cmd[0] | cdc->line_coding.dwDTERate = (uint32_t)((uint32_t)cdc->cmd[0] |
((uint32_t)cdc->cmd[1] << 8U) | ((uint32_t)cdc->cmd[1] << 8U) |
@ -487,7 +493,8 @@ static uint8_t cdc_acm_in(usb_dev *udev, uint8_t ep_num)
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE];
if((0U == transc->xfer_len % transc->max_len) && (0U != transc->xfer_len)) { if((0U == transc->xfer_len % transc->max_len) && (0U != transc->xfer_len))
{
usbd_ep_send(udev, ep_num, NULL, 0U); usbd_ep_send(udev, ep_num, NULL, 0U);
} else { } else {
cdc->packet_sent = 1U; cdc->packet_sent = 1U;

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/dfu/Include/dfu_core.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */
@ -136,7 +136,7 @@ typedef struct
{ {
usb_desc_header header; /*!< descriptor header, including type and size */ usb_desc_header header; /*!< descriptor header, including type and size */
uint8_t bmAttributes; /*!< DFU attributes */ uint8_t bmAttributes; /*!< DFU attributes */
uint16_t wDetachTimeOut; /*!< time, in milliseconds, that the device will wait after receipt of the DFU_DETACH request. If */ uint16_t wDetachTimeOut; /*!< time, in milliseconds, that the device will wait after receipt of the DFU_DETACH request. If */
uint16_t wTransferSize; /*!< maximum number of bytes that the device can accept per control-write transaction */ uint16_t wTransferSize; /*!< maximum number of bytes that the device can accept per control-write transaction */
uint16_t bcdDFUVersion; /*!< numeric expression identifying the version of the DFU Specification release. */ uint16_t bcdDFUVersion; /*!< numeric expression identifying the version of the DFU Specification release. */
} usb_desc_dfu_func; } usb_desc_dfu_func;

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/dfu/Include/dfu_mal.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

84
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/dfu/Source/dfu_core.c
View File

@ -56,7 +56,8 @@ static void dfu_abort(usb_dev *udev, usb_req *req);
static void dfu_mode_leave(usb_dev *udev); static void dfu_mode_leave(usb_dev *udev);
static uint8_t dfu_getstatus_complete(usb_dev *udev); static uint8_t dfu_getstatus_complete(usb_dev *udev);
static void (*dfu_request_process[])(usb_dev *udev, usb_req *req) = { static void (*dfu_request_process[])(usb_dev *udev, usb_req *req)=
{
[DFU_DETACH] = dfu_detach, [DFU_DETACH] = dfu_detach,
[DFU_DNLOAD] = dfu_dnload, [DFU_DNLOAD] = dfu_dnload,
[DFU_UPLOAD] = dfu_upload, [DFU_UPLOAD] = dfu_upload,
@ -274,7 +275,8 @@ static uint8_t dfu_deinit(usb_dev *udev, uint8_t config_index)
*/ */
static uint8_t dfu_req_handler(usb_dev *udev, usb_req *req) static uint8_t dfu_req_handler(usb_dev *udev, usb_req *req)
{ {
if(req->bRequest < DFU_REQ_MAX) { if(req->bRequest < DFU_REQ_MAX)
{
dfu_request_process[req->bRequest](udev, req); dfu_request_process[req->bRequest](udev, req);
} else { } else {
return USBD_FAIL; return USBD_FAIL;
@ -309,7 +311,8 @@ static void dfu_mode_leave(usb_dev *udev)
dfu->manifest_state = MANIFEST_COMPLETE; dfu->manifest_state = MANIFEST_COMPLETE;
if(dfu_config_desc.dfu_func.bmAttributes & 0x04U) { if(dfu_config_desc.dfu_func.bmAttributes & 0x04U)
{
dfu->bState = STATE_DFU_MANIFEST_SYNC; dfu->bState = STATE_DFU_MANIFEST_SYNC;
} else { } else {
dfu->bState = STATE_DFU_MANIFEST_WAIT_RESET; dfu->bState = STATE_DFU_MANIFEST_WAIT_RESET;
@ -334,18 +337,25 @@ static uint8_t dfu_getstatus_complete(usb_dev *udev)
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE];
if(STATE_DFU_DNBUSY == dfu->bState) { if(STATE_DFU_DNBUSY == dfu->bState)
{
/* decode the special command */ /* decode the special command */
if(0U == dfu->block_num) { if(0U == dfu->block_num)
if(1U == dfu->data_len) { {
if(GET_COMMANDS == dfu->buf[0]) { if(1U == dfu->data_len)
{
if(GET_COMMANDS == dfu->buf[0])
{
/* no operation */ /* no operation */
} }
} else if(5U == dfu->data_len) { } else if(5U == dfu->data_len)
if(SET_ADDRESS_POINTER == dfu->buf[0]) { {
if(SET_ADDRESS_POINTER == dfu->buf[0])
{
/* set flash operation address */ /* set flash operation address */
dfu->base_addr = *(uint32_t *)(dfu->buf + 1U); dfu->base_addr = *(uint32_t *)(dfu->buf + 1U);
} else if(ERASE == dfu->buf[0]) { } else if(ERASE == dfu->buf[0])
{
dfu->base_addr = *(uint32_t *)(dfu->buf + 1U); dfu->base_addr = *(uint32_t *)(dfu->buf + 1U);
dfu_mal_erase(dfu->base_addr); dfu_mal_erase(dfu->base_addr);
@ -355,7 +365,8 @@ static uint8_t dfu_getstatus_complete(usb_dev *udev)
} else { } else {
/* no operation */ /* no operation */
} }
} else if(dfu->block_num > 1U) { /* regular download command */ } else if(dfu->block_num > 1U)
{ /* regular download command */
/* decode the required address */ /* decode the required address */
addr = (dfu->block_num - 2U) * TRANSFER_SIZE + dfu->base_addr; addr = (dfu->block_num - 2U) * TRANSFER_SIZE + dfu->base_addr;
@ -372,7 +383,8 @@ static uint8_t dfu_getstatus_complete(usb_dev *udev)
dfu->bState = STATE_DFU_DNLOAD_SYNC; dfu->bState = STATE_DFU_DNLOAD_SYNC;
return USBD_OK; return USBD_OK;
} else if(STATE_DFU_MANIFEST == dfu->bState) { /* manifestation in progress */ } else if(STATE_DFU_MANIFEST == dfu->bState)
{ /* manifestation in progress */
/* start leaving DFU mode */ /* start leaving DFU mode */
dfu_mode_leave(udev); dfu_mode_leave(udev);
} else { } else {
@ -393,7 +405,8 @@ static void dfu_detach(usb_dev *udev, usb_req *req)
{ {
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE];
switch(dfu->bState) { switch(dfu->bState)
{
case STATE_DFU_IDLE: case STATE_DFU_IDLE:
case STATE_DFU_DNLOAD_SYNC: case STATE_DFU_DNLOAD_SYNC:
case STATE_DFU_DNLOAD_IDLE: case STATE_DFU_DNLOAD_IDLE:
@ -412,7 +425,8 @@ static void dfu_detach(usb_dev *udev, usb_req *req)
} }
/* check the detach capability in the DFU functional descriptor */ /* check the detach capability in the DFU functional descriptor */
if(dfu_config_desc.dfu_func.wDetachTimeOut & DFU_DETACH_MASK) { if(dfu_config_desc.dfu_func.wDetachTimeOut & DFU_DETACH_MASK)
{
usbd_disconnect(udev); usbd_disconnect(udev);
usbd_connect(udev); usbd_connect(udev);
@ -434,10 +448,12 @@ static void dfu_dnload(usb_dev *udev, usb_req *req)
usb_transc *transc = &udev->dev.transc_out[0]; usb_transc *transc = &udev->dev.transc_out[0];
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE];
switch(dfu->bState) { switch(dfu->bState)
{
case STATE_DFU_IDLE: case STATE_DFU_IDLE:
case STATE_DFU_DNLOAD_IDLE: case STATE_DFU_DNLOAD_IDLE:
if(req->wLength > 0U) { if(req->wLength > 0U)
{
/* update the global length and block number */ /* update the global length and block number */
dfu->block_num = req->wValue; dfu->block_num = req->wValue;
dfu->data_len = req->wLength; dfu->data_len = req->wLength;
@ -472,12 +488,14 @@ static void dfu_upload(usb_dev *udev, usb_req *req)
usb_transc *transc = &udev->dev.transc_in[0]; usb_transc *transc = &udev->dev.transc_in[0];
if(req->wLength <= 0U) { if(req->wLength <= 0U)
{
dfu->bState = STATE_DFU_IDLE; dfu->bState = STATE_DFU_IDLE;
return; return;
} }
switch(dfu->bState) { switch(dfu->bState)
{
case STATE_DFU_IDLE: case STATE_DFU_IDLE:
case STATE_DFU_UPLOAD_IDLE: case STATE_DFU_UPLOAD_IDLE:
/* update the global length and block number */ /* update the global length and block number */
@ -485,7 +503,8 @@ static void dfu_upload(usb_dev *udev, usb_req *req)
dfu->data_len = req->wLength; dfu->data_len = req->wLength;
/* DFU get command */ /* DFU get command */
if(0U == dfu->block_num) { if(0U == dfu->block_num)
{
/* update the state machine */ /* update the state machine */
dfu->bState = (dfu->data_len > 3U) ? STATE_DFU_IDLE : STATE_DFU_UPLOAD_IDLE; dfu->bState = (dfu->data_len > 3U) ? STATE_DFU_IDLE : STATE_DFU_UPLOAD_IDLE;
@ -497,7 +516,8 @@ static void dfu_upload(usb_dev *udev, usb_req *req)
/* send the status data over EP0 */ /* send the status data over EP0 */
transc->xfer_buf = &(dfu->buf[0]); transc->xfer_buf = &(dfu->buf[0]);
transc->remain_len = 3U; transc->remain_len = 3U;
} else if(dfu->block_num > 1U) { } else if(dfu->block_num > 1U)
{
dfu->bState = STATE_DFU_UPLOAD_IDLE; dfu->bState = STATE_DFU_UPLOAD_IDLE;
/* change is accelerated */ /* change is accelerated */
@ -534,13 +554,17 @@ static void dfu_getstatus(usb_dev *udev, usb_req *req)
usb_transc *transc = &udev->dev.transc_in[0]; usb_transc *transc = &udev->dev.transc_in[0];
switch(dfu->bState) { switch(dfu->bState)
{
case STATE_DFU_DNLOAD_SYNC: case STATE_DFU_DNLOAD_SYNC:
if(0U != dfu->data_len) { if(0U != dfu->data_len)
{
dfu->bState = STATE_DFU_DNBUSY; dfu->bState = STATE_DFU_DNBUSY;
if(0U == dfu->block_num) { if(0U == dfu->block_num)
if(ERASE == dfu->buf[0]) { {
if(ERASE == dfu->buf[0])
{
dfu_mal_getstatus(dfu->base_addr, CMD_ERASE, (uint8_t *)&dfu->bwPollTimeout0); dfu_mal_getstatus(dfu->base_addr, CMD_ERASE, (uint8_t *)&dfu->bwPollTimeout0);
} else { } else {
dfu_mal_getstatus(dfu->base_addr, CMD_WRITE, (uint8_t *)&dfu->bwPollTimeout0); dfu_mal_getstatus(dfu->base_addr, CMD_WRITE, (uint8_t *)&dfu->bwPollTimeout0);
@ -552,11 +576,13 @@ static void dfu_getstatus(usb_dev *udev, usb_req *req)
break; break;
case STATE_DFU_MANIFEST_SYNC: case STATE_DFU_MANIFEST_SYNC:
if(MANIFEST_IN_PROGRESS == dfu->manifest_state) { if(MANIFEST_IN_PROGRESS == dfu->manifest_state)
{
dfu->bState = STATE_DFU_MANIFEST; dfu->bState = STATE_DFU_MANIFEST;
dfu->bwPollTimeout0 = 1U; dfu->bwPollTimeout0 = 1U;
} else if((MANIFEST_COMPLETE == dfu->manifest_state) && \ } else if((MANIFEST_COMPLETE == dfu->manifest_state) && \
(dfu_config_desc.dfu_func.bmAttributes & 0x04U)) { (dfu_config_desc.dfu_func.bmAttributes & 0x04U))
{
dfu->bState = STATE_DFU_IDLE; dfu->bState = STATE_DFU_IDLE;
dfu->bwPollTimeout0 = 0U; dfu->bwPollTimeout0 = 0U;
} else { } else {
@ -583,7 +609,8 @@ static void dfu_clrstatus(usb_dev *udev, usb_req *req)
{ {
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE];
if(STATE_DFU_ERROR == dfu->bState) { if(STATE_DFU_ERROR == dfu->bState)
{
dfu->bStatus = STATUS_OK; dfu->bStatus = STATUS_OK;
dfu->bState = STATE_DFU_IDLE; dfu->bState = STATE_DFU_IDLE;
} else { } else {
@ -622,7 +649,8 @@ static void dfu_abort(usb_dev *udev, usb_req *req)
{ {
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE];
switch(dfu->bState) { switch(dfu->bState)
{
case STATE_DFU_IDLE: case STATE_DFU_IDLE:
case STATE_DFU_DNLOAD_SYNC: case STATE_DFU_DNLOAD_SYNC:
case STATE_DFU_DNLOAD_IDLE: case STATE_DFU_DNLOAD_IDLE:

42
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/dfu/Source/dfu_mal.c
View File

@ -69,9 +69,11 @@ uint8_t dfu_mal_init(void)
uint32_t mem_index = 0U; uint32_t mem_index = 0U;
/* initialize all supported memory medias */ /* initialize all supported memory medias */
for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) { for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++)
{
/* check if the memory media exists */ /* check if the memory media exists */
if(NULL != tMALTab[mem_index]->mal_init) { if(NULL != tMALTab[mem_index]->mal_init)
{
tMALTab[mem_index]->mal_init(); tMALTab[mem_index]->mal_init();
} }
} }
@ -90,9 +92,11 @@ uint8_t dfu_mal_deinit(void)
uint32_t mem_index = 0U; uint32_t mem_index = 0U;
/* deinitializes all supported memory medias */ /* deinitializes all supported memory medias */
for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) { for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++)
{
/* check if the memory media exists */ /* check if the memory media exists */
if(NULL != tMALTab[mem_index]->mal_deinit) { if(NULL != tMALTab[mem_index]->mal_deinit)
{
tMALTab[mem_index]->mal_deinit(); tMALTab[mem_index]->mal_deinit();
} }
} }
@ -110,9 +114,11 @@ uint8_t dfu_mal_erase(uint32_t addr)
{ {
uint32_t mem_index = dfu_mal_checkaddr(addr); uint32_t mem_index = dfu_mal_checkaddr(addr);
if(mem_index < MAX_USED_MEMORY_MEDIA) { if(mem_index < MAX_USED_MEMORY_MEDIA)
{
/* check if the operation is supported */ /* check if the operation is supported */
if(NULL != tMALTab[mem_index]->mal_erase) { if(NULL != tMALTab[mem_index]->mal_erase)
{
return tMALTab[mem_index]->mal_erase(addr); return tMALTab[mem_index]->mal_erase(addr);
} else { } else {
return MAL_FAIL; return MAL_FAIL;
@ -134,9 +140,11 @@ uint8_t dfu_mal_write(uint8_t *buf, uint32_t addr, uint32_t len)
{ {
uint32_t mem_index = dfu_mal_checkaddr(addr); uint32_t mem_index = dfu_mal_checkaddr(addr);
if(mem_index < MAX_USED_MEMORY_MEDIA) { if(mem_index < MAX_USED_MEMORY_MEDIA)
{
/* check if the operation is supported */ /* check if the operation is supported */
if(NULL != tMALTab[mem_index]->mal_write) { if(NULL != tMALTab[mem_index]->mal_write)
{
return tMALTab[mem_index]->mal_write(buf, addr, len); return tMALTab[mem_index]->mal_write(buf, addr, len);
} else { } else {
return MAL_FAIL; return MAL_FAIL;
@ -158,9 +166,11 @@ uint8_t *dfu_mal_read(uint8_t *buf, uint32_t addr, uint32_t len)
{ {
uint32_t mem_index = 0U; uint32_t mem_index = 0U;
if(mem_index < MAX_USED_MEMORY_MEDIA) { if(mem_index < MAX_USED_MEMORY_MEDIA)
{
/* check if the operation is supported */ /* check if the operation is supported */
if(NULL != tMALTab[mem_index]->mal_read) { if(NULL != tMALTab[mem_index]->mal_read)
{
return tMALTab[mem_index]->mal_read(buf, addr, len); return tMALTab[mem_index]->mal_read(buf, addr, len);
} else { } else {
return buf; return buf;
@ -182,8 +192,10 @@ uint8_t dfu_mal_getstatus(uint32_t addr, uint8_t cmd, uint8_t *buffer)
{ {
uint32_t mem_index = dfu_mal_checkaddr(addr); uint32_t mem_index = dfu_mal_checkaddr(addr);
if(mem_index < MAX_USED_MEMORY_MEDIA) { if(mem_index < MAX_USED_MEMORY_MEDIA)
if(cmd & 0x01U) { {
if(cmd & 0x01U)
{
SET_POLLING_TIMEOUT(tMALTab[mem_index]->write_timeout); SET_POLLING_TIMEOUT(tMALTab[mem_index]->write_timeout);
} else { } else {
SET_POLLING_TIMEOUT(tMALTab[mem_index]->erase_timeout); SET_POLLING_TIMEOUT(tMALTab[mem_index]->erase_timeout);
@ -206,9 +218,11 @@ static uint8_t dfu_mal_checkaddr(uint32_t addr)
uint8_t mem_index = 0U; uint8_t mem_index = 0U;
/* check with all supported memories */ /* check with all supported memories */
for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) { for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++)
{
/* if the check address is supported, return the memory index */ /* if the check address is supported, return the memory index */
if(MAL_OK == tMALTab[mem_index]->mal_checkaddr(addr)) { if(MAL_OK == tMALTab[mem_index]->mal_checkaddr(addr))
{
return mem_index; return mem_index;
} }
} }

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/hid/Include/custom_hid_core.h
View File

@ -8,27 +8,27 @@
/* /*
Copyright (c) 2024, GigaDevice Semiconductor Inc. Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this 1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer. list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, 2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution. and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors 3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without may be used to endorse or promote products derived from this software without
specific prior written permission. specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE. OF SUCH DAMAGE.
*/ */

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