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fix: remove extra space at the end of files

This commit is contained in:
wirano 2024-07-24 23:18:40 +08:00 committed by Rbb666
parent 229b2bffec
commit d56452e662
170 changed files with 6742 additions and 4645 deletions
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2
bsp/gd32/arm/gd32h759i-start/applications/main.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32/arm/gd32h759i-start/board/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

8
bsp/gd32/arm/gd32h759i-start/board/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -19,10 +19,10 @@
#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
// <o> Internal SRAM memory size[Kbytes] <8-512>
// <i>Default: 512
/* <o> Internal SRAM memory size[Kbytes] <8-512>*/
/* <i>Default: 512*/
#ifdef __ICCARM__
// Use *.icf ram symbal, to avoid hardcode.
/* Use *.icf ram symbal, to avoid hardcode.*/
extern char __ICFEDIT_region_RAM_end__;
#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
#else

119
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/GD/GD32H7xx/Source/system_gd32h7xx.c
View File

@ -38,16 +38,16 @@
/* select a system clock by uncommenting the following line */
/* use IRC64M */
//#define __SYSTEM_CLOCK_IRC64M (__IRC64M)
//#define __SYSTEM_CLOCK_600M_PLL0_IRC64M (uint32_t)(600000000)
/*#define __SYSTEM_CLOCK_IRC64M (__IRC64M)*/
/*#define __SYSTEM_CLOCK_600M_PLL0_IRC64M (uint32_t)(600000000)*/
/* use LPIRC4M */
//#define __SYSTEM_CLOCK_LPIRC4M (__LPIRC4M)
/*#define __SYSTEM_CLOCK_LPIRC4M (__LPIRC4M)*/
/* use HXTAL(CK_HXTAL = 25M) */
//#define __SYSTEM_CLOCK_HXTAL (__HXTAL)
//#define __SYSTEM_CLOCK_200M_PLL0_HXTAL (uint32_t)(200000000)
//#define __SYSTEM_CLOCK_400M_PLL0_HXTAL (uint32_t)(400000000)
/*#define __SYSTEM_CLOCK_HXTAL (__HXTAL)*/
/*#define __SYSTEM_CLOCK_200M_PLL0_HXTAL (uint32_t)(200000000)*/
/*#define __SYSTEM_CLOCK_400M_PLL0_HXTAL (uint32_t)(400000000)*/
#define __SYSTEM_CLOCK_600M_PLL0_HXTAL (uint32_t)(600000000)
/*
@ -63,18 +63,18 @@ Note: the power mode need to match the mcu selection and external power supply c
the following macro SEL_PMU_SMPS_MODE.
*/
#if defined(GD32H7XXI)
//#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY
//#define SEL_PMU_SMPS_MODE PMU_DIRECT_SMPS_SUPPLY
//#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_LDO
//#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_LDO
//#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO
//#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO
//#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_EXT
//#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_EXT
/*#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY*/
/*#define SEL_PMU_SMPS_MODE PMU_DIRECT_SMPS_SUPPLY*/
/*#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_LDO*/
/*#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_LDO*/
/*#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO*/
/*#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO*/
/*#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_EXT*/
/*#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_EXT*/
#define SEL_PMU_SMPS_MODE PMU_BYPASS
#elif defined(GD32H7XXZ) | defined(GD32H7XXV)
//#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY
//#define SEL_PMU_SMPS_MODE PMU_BYPASS
/*#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY*/
/*#define SEL_PMU_SMPS_MODE PMU_BYPASS*/
#endif
#define SEL_IRC64MDIV 0x00U
@ -153,7 +153,8 @@ void SystemInit(void)
/* enable IRC64M */
RCU_CTL |= RCU_CTL_IRC64MEN;
while(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
while(0U == (RCU_CTL & RCU_CTL_IRC64MSTB))
{
}
/* no TCM wait state */
@ -256,8 +257,10 @@ static void system_clock_64m_irc64m(void)
} while((0U == stab_flag) && (IRC64M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
while(1) {
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB))
{
while(1)
{
}
}
@ -281,7 +284,8 @@ static void system_clock_64m_irc64m(void)
RCU_CFG0 |= RCU_CKSYSSRC_IRC64MDIV;
/* wait until IRC64M is selected as system clock */
while(RCU_SCSS_IRC64MDIV != (RCU_CFG0 & RCU_CFG0_SCSS)) {
while(RCU_SCSS_IRC64MDIV != (RCU_CFG0 & RCU_CFG0_SCSS))
{
}
}
@ -307,8 +311,10 @@ static void system_clock_600m_irc64m(void)
} while((0U == stab_flag) && (IRC64M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
while(1) {
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB))
{
while(1)
{
}
}
@ -347,7 +353,8 @@ static void system_clock_600m_irc64m(void)
RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
while(0U == (RCU_CTL & RCU_CTL_PLL0STB))
{
}
/* select PLL0 as system clock */
@ -355,7 +362,8 @@ static void system_clock_600m_irc64m(void)
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS))
{
}
}
@ -380,8 +388,10 @@ static void system_clock_4m_lpirc4m(void)
stab_flag = (RCU_ADDCTL1 & RCU_ADDCTL1_LPIRC4MSTB);
} while((0U == stab_flag) && (LPIRC4M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_ADDCTL1 & RCU_ADDCTL1_LPIRC4MSTB)) {
while(1) {
if(0U == (RCU_ADDCTL1 & RCU_ADDCTL1_LPIRC4MSTB))
{
while(1)
{
}
}
@ -402,7 +412,8 @@ static void system_clock_4m_lpirc4m(void)
RCU_CFG0 |= RCU_CKSYSSRC_LPIRC4M;
/* wait until LPIRC4M is selected as system clock */
while(RCU_SCSS_LPIRC4M != (RCU_CFG0 & RCU_CFG0_SCSS)) {
while(RCU_SCSS_LPIRC4M != (RCU_CFG0 & RCU_CFG0_SCSS))
{
}
}
@ -427,8 +438,10 @@ static void system_clock_hxtal(void)
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while(1) {
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
{
while(1)
{
}
}
@ -449,7 +462,8 @@ static void system_clock_hxtal(void)
RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
/* wait until HXTAL is selected as system clock */
while(RCU_SCSS_HXTAL != (RCU_CFG0 & RCU_CFG0_SCSS)) {
while(RCU_SCSS_HXTAL != (RCU_CFG0 & RCU_CFG0_SCSS))
{
}
}
@ -474,8 +488,10 @@ static void system_clock_200m_hxtal(void)
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while(1) {
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
{
while(1)
{
}
}
@ -508,7 +524,8 @@ static void system_clock_200m_hxtal(void)
RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
while(0U == (RCU_CTL & RCU_CTL_PLL0STB))
{
}
/* select PLL0 as system clock */
@ -516,7 +533,8 @@ static void system_clock_200m_hxtal(void)
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS))
{
}
}
@ -541,8 +559,10 @@ static void system_clock_400m_hxtal(void)
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while(1) {
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
{
while(1)
{
}
}
@ -579,7 +599,8 @@ static void system_clock_400m_hxtal(void)
RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
while(0U == (RCU_CTL & RCU_CTL_PLL0STB))
{
}
/* select PLL0 as system clock */
@ -587,7 +608,8 @@ static void system_clock_400m_hxtal(void)
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS))
{
}
}
@ -612,8 +634,10 @@ static void system_clock_600m_hxtal(void)
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while(1) {
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
{
while(1)
{
}
}
@ -650,7 +674,8 @@ static void system_clock_600m_hxtal(void)
RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
while(0U == (RCU_CTL & RCU_CTL_PLL0STB))
{
}
/* select PLL0 as system clock */
@ -658,7 +683,8 @@ static void system_clock_600m_hxtal(void)
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS))
{
}
}
@ -677,7 +703,8 @@ void SystemCoreClockUpdate(void)
uint32_t pllpsc = 0U, plln = 0U, pllp = 0U, pllsel = 0U;
sws = GET_BITS(RCU_CFG0, 2, 3);
switch(sws) {
switch(sws)
{
/* IRC64M is selected as CK_SYS */
case SEL_IRC64MDIV:
irc64div = (1U << GET_BITS(RCU_ADDCTL1, 16, 17));
@ -700,10 +727,12 @@ void SystemCoreClockUpdate(void)
/* PLL clock source selection, HXTAL or IRC64M_VALUE or LPIRC4M_VALUE */
pllsel = GET_BITS(RCU_PLLALL, 16, 17);
if(0U == pllsel) {
if(0U == pllsel)
{
irc64div = (1U << GET_BITS(RCU_ADDCTL1, 16, 17));
SystemCoreClock = (IRC64M_VALUE / irc64div / pllpsc) * plln / pllp;
} else if(1U == pllsel) {
} else if(1U == pllsel)
{
SystemCoreClock = (LPIRC4M_VALUE / pllpsc) * plln / pllp;
} else {
SystemCoreClock = (HXTAL_VALUE / pllpsc) * plln / pllp;

12
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cachel1_armv7.h
View File

@ -115,7 +115,8 @@ __STATIC_FORCEINLINE void SCB_InvalidateICache (void)
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if ( isize > 0 ) {
if ( isize > 0 )
{
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
@ -358,7 +359,8 @@ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
if ( dsize > 0 )
{
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
@ -388,7 +390,8 @@ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
if ( dsize > 0 )
{
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
@ -418,7 +421,8 @@ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
if ( dsize > 0 )
{
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;

22
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_armclang.h
View File

@ -64,7 +64,8 @@
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
struct __attribute__((packed))T_UINT32
{ uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
@ -153,7 +154,8 @@
#endif
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop)
{
*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
}
#endif
@ -1217,7 +1219,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@ -1240,7 +1242,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@ -1265,7 +1267,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
@ -1287,7 +1289,7 @@ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
@ -1309,7 +1311,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@ -1332,7 +1334,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@ -1356,7 +1358,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
@ -1377,7 +1379,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));

22
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_armclang_ltm.h
View File

@ -64,7 +64,8 @@
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
struct __attribute__((packed))T_UINT32
{ uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
@ -152,7 +153,8 @@
#endif
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop)
{
*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
}
#endif
@ -1201,7 +1203,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@ -1223,7 +1225,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@ -1247,7 +1249,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
@ -1268,7 +1270,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
@ -1289,7 +1291,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@ -1311,7 +1313,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@ -1334,7 +1336,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
@ -1354,7 +1356,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));

5
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_compiler.h
View File

@ -103,7 +103,8 @@
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
struct __attribute__((packed))T_UINT32
{ uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
@ -236,7 +237,7 @@
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
/* NO RETURN is automatically detected hence no warning here*/
#define __NO_RETURN
#endif
#ifndef __USED

48
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_gcc.h
View File

@ -71,7 +71,8 @@
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
struct __attribute__((packed))T_UINT32
{ uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
@ -154,14 +155,18 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
extern const __zero_table_t __zero_table_start__;
extern const __zero_table_t __zero_table_end__;
for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
for(uint32_t i=0u; i<pTable->wlen; ++i) {
for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable)
{
for(uint32_t i=0u; i<pTable->wlen; ++i)
{
pTable->dest[i] = pTable->src[i];
}
}
for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
for(uint32_t i=0u; i<pTable->wlen; ++i) {
for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable)
{
for(uint32_t i=0u; i<pTable->wlen; ++i)
{
pTable->dest[i] = 0u;
}
}
@ -202,7 +207,8 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
#endif
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop)
{
*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
}
#endif
@ -1421,7 +1427,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@ -1442,7 +1448,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@ -1466,7 +1472,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
@ -1486,7 +1492,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
@ -1508,7 +1514,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@ -1530,7 +1536,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@ -1554,7 +1560,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
@ -1574,7 +1580,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
@ -1596,8 +1602,8 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_get_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* Re-enable using built-in when GCC has been fixed*/
/* || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)*/
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
return __builtin_arm_get_fpscr();
#else
@ -1622,8 +1628,8 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_set_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* Re-enable using built-in when GCC has been fixed*/
/* || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)*/
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
__builtin_arm_set_fpscr(fpscr);
#else
@ -1995,7 +2001,8 @@ __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
{
uint32_t result;
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
{
__ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
} else {
result = __SXTB16(__ROR(op1, rotate)) ;
@ -2014,7 +2021,8 @@ __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
{
uint32_t result;
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
{
__ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate));
} else {
result = __SXTAB16(op1, __ROR(op2, rotate));

75
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/mpu_armv7.h
View File

@ -31,41 +31,41 @@
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) /*/!< MPU Region Size 32 Bytes*/
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) /*/!< MPU Region Size 64 Bytes*/
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) /*/!< MPU Region Size 128 Bytes*/
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) /*/!< MPU Region Size 256 Bytes*/
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) /*/!< MPU Region Size 512 Bytes*/
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) /*/!< MPU Region Size 1 KByte*/
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) /*/!< MPU Region Size 2 KBytes*/
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) /*/!< MPU Region Size 4 KBytes*/
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) /*/!< MPU Region Size 8 KBytes*/
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) /*/!< MPU Region Size 16 KBytes*/
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) /*/!< MPU Region Size 32 KBytes*/
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) /*/!< MPU Region Size 64 KBytes*/
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) /*/!< MPU Region Size 128 KBytes*/
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) /*/!< MPU Region Size 256 KBytes*/
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) /*/!< MPU Region Size 512 KBytes*/
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) /*/!< MPU Region Size 1 MByte*/
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) /*/!< MPU Region Size 2 MBytes*/
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) /*/!< MPU Region Size 4 MBytes*/
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) /*/!< MPU Region Size 8 MBytes*/
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) /*/!< MPU Region Size 16 MBytes*/
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) /*/!< MPU Region Size 32 MBytes*/
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) /*/!< MPU Region Size 64 MBytes*/
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) /*/!< MPU Region Size 128 MBytes*/
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) /*/!< MPU Region Size 256 MBytes*/
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) /*/!< MPU Region Size 512 MBytes*/
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) /*/!< MPU Region Size 1 GByte*/
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) /*/!< MPU Region Size 2 GBytes*/
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) /*/!< MPU Region Size 4 GBytes*/
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
#define ARM_MPU_AP_NONE 0U /*/!< MPU Access Permission no access*/
#define ARM_MPU_AP_PRIV 1U /*/!< MPU Access Permission privileged access only*/
#define ARM_MPU_AP_URO 2U /*/!< MPU Access Permission unprivileged access read-only*/
#define ARM_MPU_AP_FULL 3U /*/!< MPU Access Permission full access*/
#define ARM_MPU_AP_PRO 5U /*/!< MPU Access Permission privileged access read-only*/
#define ARM_MPU_AP_RO 6U /*/!< MPU Access Permission read-only access*/
/** MPU Region Base Address Register Value
*
@ -181,8 +181,8 @@
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
uint32_t RBAR; /*!< The region base address register value (RBAR)*/
uint32_t RASR; /*!< The region attribute and size register value (RASR) \ref MPU_RASR*/
} ARM_MPU_Region_t;
/** Enable the MPU.
@ -264,7 +264,8 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
while (cnt > MPU_TYPE_RALIASES)
{
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;

2
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_enet.h
View File

@ -470,7 +470,7 @@ OF SUCH DAMAGE.
/* ENET DMA Tx descriptor TDES3 */
#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */
//#define SELECT_DESCRIPTORS_ENHANCED_MODE
/*#define SELECT_DESCRIPTORS_ENHANCED_MODE*/
#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
/* ENET DMA Tx descriptor TDES6 */

174
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_adc.c
View File

@ -74,7 +74,8 @@ OF SUCH DAMAGE.
*/
void adc_deinit(uint32_t adc_periph)
{
switch(adc_periph) {
switch(adc_periph)
{
case ADC0:
rcu_periph_reset_enable(RCU_ADC0RST);
rcu_periph_reset_disable(RCU_ADC0RST);
@ -121,7 +122,8 @@ void adc_deinit(uint32_t adc_periph)
*/
void adc_clock_config(uint32_t adc_periph, uint32_t prescaler)
{
if(ADC2 == adc_periph) {
if(ADC2 == adc_periph)
{
ADC_SYNCCTL(ADC2) &= ~((uint32_t)(ADC_SYNCCTL_ADCCK | ADC_SYNCCTL_ADCSCK));
ADC_SYNCCTL(ADC2) |= (uint32_t)prescaler;
} else {
@ -144,29 +146,36 @@ void adc_clock_config(uint32_t adc_periph, uint32_t prescaler)
*/
void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue)
{
if(ENABLE == newvalue) {
if(RESET != (function & ADC_SCAN_MODE)) {
if(ENABLE == newvalue)
{
if(RESET != (function & ADC_SCAN_MODE))
{
/* enable scan mode */
ADC_CTL0(adc_periph) |= (uint32_t)ADC_SCAN_MODE;
}
if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) {
if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO))
{
/* enable inserted channel group convert automatically */
ADC_CTL0(adc_periph) |= (uint32_t)ADC_INSERTED_CHANNEL_AUTO;
}
if(RESET != (function & ADC_CONTINUOUS_MODE)) {
if(RESET != (function & ADC_CONTINUOUS_MODE))
{
/* enable continuous mode */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CONTINUOUS_MODE;
}
} else {
if(RESET != (function & ADC_SCAN_MODE)) {
if(RESET != (function & ADC_SCAN_MODE))
{
/* disable scan mode */
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_SCAN_MODE);
}
if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) {
if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO))
{
/* disable inserted channel group convert automatically */
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_INSERTED_CHANNEL_AUTO);
}
if(RESET != (function & ADC_CONTINUOUS_MODE)) {
if(RESET != (function & ADC_CONTINUOUS_MODE))
{
/* disable continuous mode */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CONTINUOUS_MODE);
}
@ -185,10 +194,12 @@ void adc_special_function_config(uint32_t adc_periph, uint32_t function, Control
*/
void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
{
if(ADC_DATAALIGN_RIGHT == data_alignment) {
if(ADC_DATAALIGN_RIGHT == data_alignment)
{
/* LSB alignment */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
} else if(ADC_DATAALIGN_LEFT == data_alignment) {
} else if(ADC_DATAALIGN_LEFT == data_alignment)
{
/* MSB alignment */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_DAL;
} else {
@ -204,7 +215,8 @@ void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
*/
void adc_enable(uint32_t adc_periph)
{
if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)) {
if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON))
{
/* enable ADC */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
}
@ -234,10 +246,12 @@ void adc_disable(uint32_t adc_periph)
*/
void adc_calibration_mode_config(uint32_t adc_periph, uint32_t clb_mode)
{
if(ADC_CALIBRATION_OFFSET_MISMATCH == clb_mode) {
if(ADC_CALIBRATION_OFFSET_MISMATCH == clb_mode)
{
/* offset and mismatch mode */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_CALMOD);
} else if(ADC_CALIBRATION_OFFSET == clb_mode) {
} else if(ADC_CALIBRATION_OFFSET == clb_mode)
{
/* offset mode */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_CALMOD;
} else {
@ -276,12 +290,14 @@ void adc_calibration_enable(uint32_t adc_periph)
/* reset the selected ADC calibration registers */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_RSTCLB;
/* check the RSTCLB bit state */
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) {
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB))
{
}
/* enable ADC calibration process */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_CLB;
/* check the CLB bit state */
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) {
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB))
{
}
}
@ -302,14 +318,17 @@ void adc_resolution_config(uint32_t adc_periph, uint32_t resolution)
{
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DRES);
if(ADC2 == adc_periph) {
if(ADC_RESOLUTION_14B == resolution) {
if(ADC2 == adc_periph)
{
if(ADC_RESOLUTION_14B == resolution)
{
/* illegal parameters */
} else {
ADC_CTL0(adc_periph) |= (uint32_t)CTL0_DRES(resolution - 1U);
}
} else {
if(ADC_RESOLUTION_6B == resolution) {
if(ADC_RESOLUTION_6B == resolution)
{
/* illegal parameters */
} else {
ADC_CTL0(adc_periph) |= (uint32_t)CTL0_DRES(resolution);
@ -331,7 +350,8 @@ void adc_resolution_config(uint32_t adc_periph, uint32_t resolution)
*/
void adc_internal_channel_config(uint32_t internal_channel, ControlStatus newvalue)
{
if(ENABLE == newvalue) {
if(ENABLE == newvalue)
{
ADC_CTL1(ADC2) |= (uint32_t)internal_channel;
} else {
ADC_CTL1(ADC2) &= ~((uint32_t)internal_channel);
@ -425,11 +445,13 @@ void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_grou
{
/* disable discontinuous mode of regular & inserted channel */
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
switch(adc_channel_group) {
switch(adc_channel_group)
{
case ADC_REGULAR_CHANNEL:
/* config the number of conversions in discontinuous mode */
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
if((length <= 8U) && (length >= 1U)) {
if((length <= 8U) && (length >= 1U))
{
ADC_CTL0(adc_periph) |= CTL0_DISNUM((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
}
/* enable regular channel group discontinuous mode */
@ -461,15 +483,18 @@ void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_grou
*/
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
{
switch(adc_channel_group) {
switch(adc_channel_group)
{
case ADC_REGULAR_CHANNEL:
if((length >= 1U) && (length <= 16U)) {
if((length >= 1U) && (length <= 16U))
{
ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
}
break;
case ADC_INSERTED_CHANNEL:
if((length >= 1U) && (length <= 4U)) {
if((length >= 1U) && (length <= 4U))
{
ADC_ISQ0(adc_periph) &= ~((uint32_t)ADC_ISQ0_IL);
ADC_ISQ0(adc_periph) |= ISQ0_IL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
}
@ -495,14 +520,16 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
uint32_t rsq;
/* configure ADC regular sequence */
if(rank < ADC_REGULAR_CHANNEL_RANK_ONE) {
if(rank < ADC_REGULAR_CHANNEL_RANK_ONE)
{
/* the regular group sequence rank is smaller than one */
rsq = ADC_RSQ8(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rank)));
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
rank));
ADC_RSQ8(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_THREE) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_THREE)
{
/* the regular group sequence rank is smaller than three */
rsq = ADC_RSQ7(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -510,7 +537,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_ONE)));
ADC_RSQ7(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_FIVE) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_FIVE)
{
/* the regular group sequence rank is smaller than five */
rsq = ADC_RSQ6(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -518,7 +546,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_THREE)));
ADC_RSQ6(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_SEVEN) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_SEVEN)
{
/* the regular group sequence rank is smaller than seven */
rsq = ADC_RSQ5(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -526,7 +555,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_FIVE)));
ADC_RSQ5(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_NINE) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_NINE)
{
/* the regular group sequence rank is smaller than nine */
rsq = ADC_RSQ4(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -534,7 +564,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_SEVEN)));
ADC_RSQ4(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_ELEVEN) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_ELEVEN)
{
/* the regular group sequence rank is smaller than eleven */
rsq = ADC_RSQ3(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -542,7 +573,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_NINE)));
ADC_RSQ3(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_THIRTEEN) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_THIRTEEN)
{
/* the regular group sequence rank is smaller than thirteen */
rsq = ADC_RSQ2(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -550,7 +582,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_ELEVEN)));
ADC_RSQ2(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_FIFTEEN) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_FIFTEEN)
{
/* the regular group sequence rank is smaller than fifteen */
rsq = ADC_RSQ1(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -558,7 +591,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_THIRTEEN)));
ADC_RSQ1(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN)
{
/* the regular group sequence rank is smaller than sixteen */
rsq = ADC_RSQ0(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@ -592,13 +626,15 @@ void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_
rankx = ADC_OFFSET_LENGTH - inserted_length + rank;
/* configure ADC inserted sequence */
if(rankx < ADC_INSERTED_CHANNEL_RANK_ONE) {
if(rankx < ADC_INSERTED_CHANNEL_RANK_ONE)
{
/* the inserted group sequence rank is smaller than one */
isq = ADC_ISQ2(adc_periph);
isq &= ~((uint32_t)((ADC_ISQX_ISMPN | ADC_ISQX_ISQN) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH * rankx)));
isq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH * rankx));
ADC_ISQ2(adc_periph) = isq;
} else if(rankx < ADC_INSERTED_CHANNEL_RANK_THREE) {
} else if(rankx < ADC_INSERTED_CHANNEL_RANK_THREE)
{
/* the inserted group sequence rank is smaller than three */
isq = ADC_ISQ1(adc_periph);
isq &= ~((uint32_t)((ADC_ISQX_ISMPN | ADC_ISQX_ISQN) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH *
@ -606,7 +642,8 @@ void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_
isq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH *
(rankx - ADC_INSERTED_CHANNEL_RANK_ONE)));
ADC_ISQ1(adc_periph) = isq;
} else if(rankx < ADC_INSERTED_CHANNEL_RANK_FOUR) {
} else if(rankx < ADC_INSERTED_CHANNEL_RANK_FOUR)
{
/* the inserted group sequence rank is smaller than four */
isq = ADC_ISQ0(adc_periph);
isq &= ~((uint32_t)((ADC_ISQX_ISMPN | ADC_ISQX_ISQN) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH *
@ -640,7 +677,8 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch
inserted_length = (uint8_t)GET_BITS(ADC_ISQ0(adc_periph), 20U, 21U);
num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel));
if(num <= ADC_OFFSET_LENGTH) {
if(num <= ADC_OFFSET_LENGTH)
{
/* calculate the offset of the register */
num = num * ADC_OFFSET_SHIFT_LENGTH;
/* config the offset of the selected channels */
@ -660,7 +698,8 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch
*/
void adc_channel_differential_mode_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue)
{
if(ENABLE == newvalue) {
if(ENABLE == newvalue)
{
ADC_DIFCTL(adc_periph) |= (uint32_t)adc_channel;
} else {
ADC_DIFCTL(adc_periph) &= ~((uint32_t)adc_channel);
@ -685,7 +724,8 @@ void adc_channel_differential_mode_config(uint32_t adc_periph, uint32_t adc_chan
*/
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t trigger_mode)
{
switch(adc_channel_group) {
switch(adc_channel_group)
{
case ADC_REGULAR_CHANNEL:
/* configure ADC regular channel group external trigger mode */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC);
@ -714,11 +754,13 @@ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group,
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
{
/* enable regular group channel software trigger */
if(RESET != (adc_channel_group & ADC_REGULAR_CHANNEL)) {
if(RESET != (adc_channel_group & ADC_REGULAR_CHANNEL))
{
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST;
}
/* enable inserted channel group software trigger */
if(RESET != (adc_channel_group & ADC_INSERTED_CHANNEL)) {
if(RESET != (adc_channel_group & ADC_INSERTED_CHANNEL))
{
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST;
}
}
@ -735,10 +777,12 @@ void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
*/
void adc_end_of_conversion_config(uint32_t adc_periph, uint32_t end_selection)
{
if(ADC_EOC_SET_SEQUENCE == end_selection) {
if(ADC_EOC_SET_SEQUENCE == end_selection)
{
/* only at the end of a sequence of regular conversions, the EOC bit is set */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM);
} else if(ADC_EOC_SET_CONVERSION == end_selection) {
} else if(ADC_EOC_SET_CONVERSION == end_selection)
{
/* at the end of each regular conversion, the EOC bit is set. Overflow is detected automatically */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_EOCM;
} else {
@ -774,7 +818,8 @@ uint32_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel)
{
uint32_t idata;
/* read the data of the selected channel */
switch(inserted_channel) {
switch(inserted_channel)
{
case ADC_INSERTED_CHANNEL_0:
/* read the data of channel 0 */
idata = ADC_IDATA0(adc_periph);
@ -831,7 +876,8 @@ void adc_watchdog0_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel
{
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWD0EN | ADC_CTL0_IWD0EN | ADC_CTL0_WD0SC));
/* select the group */
switch(adc_channel_group) {
switch(adc_channel_group)
{
case ADC_REGULAR_CHANNEL:
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_RWD0EN;
break;
@ -870,7 +916,8 @@ void adc_watchdog0_disable(uint32_t adc_periph)
*/
void adc_watchdog1_channel_config(uint32_t adc_periph, uint32_t selection_channel, ControlStatus newvalue)
{
if(ENABLE == newvalue) {
if(ENABLE == newvalue)
{
ADC_WD1SR(adc_periph) |= (uint32_t)selection_channel;
} else {
ADC_WD1SR(adc_periph) &= ~((uint32_t)selection_channel);
@ -889,7 +936,8 @@ void adc_watchdog1_channel_config(uint32_t adc_periph, uint32_t selection_channe
*/
void adc_watchdog2_channel_config(uint32_t adc_periph, uint32_t selection_channel, ControlStatus newvalue)
{
if(ENABLE == newvalue) {
if(ENABLE == newvalue)
{
ADC_WD2SR(adc_periph) |= (uint32_t)selection_channel;
} else {
ADC_WD2SR(adc_periph) &= ~((uint32_t)selection_channel);
@ -987,10 +1035,12 @@ void adc_watchdog2_threshold_config(uint32_t adc_periph, uint32_t low_threshold,
*/
void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint16_t ratio)
{
if(ADC_OVERSAMPLING_ALL_CONVERT == mode) {
if(ADC_OVERSAMPLING_ALL_CONVERT == mode)
{
/* all oversampled conversions for a channel are done consecutively after a trigger */
ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS);
} else if(ADC_OVERSAMPLING_ONE_CONVERT == mode) {
} else if(ADC_OVERSAMPLING_ONE_CONVERT == mode)
{
/* each oversampled conversion for a channel needs a trigger */
ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS;
} else {
@ -1042,7 +1092,8 @@ void adc_oversample_mode_disable(uint32_t adc_periph)
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t flag)
{
FlagStatus reval = RESET;
if(ADC_STAT(adc_periph) & flag) {
if(ADC_STAT(adc_periph) & flag)
{
reval = SET;
}
return reval;
@ -1126,46 +1177,53 @@ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t int_flag)
FlagStatus reval = RESET;
uint32_t state;
/* check the interrupt bits */
switch(int_flag) {
switch(int_flag)
{
case ADC_INT_FLAG_WDE0:
/* get the ADC analog watchdog 0 interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_WDE0;
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE0IE) && state) {
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE0IE) && state)
{
reval = SET;
}
break;
case ADC_INT_FLAG_EOC:
/* get the ADC end of group conversion interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) {
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state)
{
reval = SET;
}
break;
case ADC_INT_FLAG_EOIC:
/* get the ADC end of inserted group conversion interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) {
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state)
{
reval = SET;
}
break;
case ADC_INT_FLAG_ROVF:
/* get the ADC regular data register overflow interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_ROVF;
if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state) {
if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state)
{
reval = SET;
}
break;
case ADC_INT_FLAG_WDE1:
/* get the ADC analog watchdog 1 interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_WDE1;
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE1IE) && state) {
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE1IE) && state)
{
reval = SET;
}
break;
case ADC_INT_FLAG_WDE2:
/* get the ADC analog watchdog 2 interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_WDE2;
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE2IE) && state) {
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE2IE) && state)
{
reval = SET;
}
break;

324
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_can.c
View File

@ -54,17 +54,20 @@ static uint32_t can_dlc_value_compute(uint32_t payload_size);
*/
void can_deinit(uint32_t can_periph)
{
if(CAN0 == can_periph) {
if(CAN0 == can_periph)
{
/* reset CAN0 */
rcu_periph_reset_enable(RCU_CAN0RST);
rcu_periph_reset_disable(RCU_CAN0RST);
}
if(CAN1 == can_periph) {
if(CAN1 == can_periph)
{
/* reset CAN1 */
rcu_periph_reset_enable(RCU_CAN1RST);
rcu_periph_reset_disable(RCU_CAN1RST);
}
if(CAN2 == can_periph) {
if(CAN2 == can_periph)
{
/* reset CAN2 */
rcu_periph_reset_enable(RCU_CAN2RST);
rcu_periph_reset_disable(RCU_CAN2RST);
@ -84,10 +87,12 @@ ErrStatus can_software_reset(uint32_t can_periph)
/* reset internal state machines and CAN registers */
CAN_CTL0(can_periph) |= CAN_CTL0_SWRST;
/* wait reset complete */
while((CAN_CTL0(can_periph) & CAN_CTL0_SWRST) && (timeout)) {
while((CAN_CTL0(can_periph) & CAN_CTL0_SWRST) && (timeout))
{
timeout--;
}
if(CAN_CTL0(can_periph) & CAN_CTL0_SWRST) {
if(CAN_CTL0(can_periph) & CAN_CTL0_SWRST)
{
return ERROR;
}
return SUCCESS;
@ -131,16 +136,19 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init
uint32_t *canram = (uint32_t *)(CAN_RAM(can_periph));
/* clear CAN RAM */
for(i = 0U; i < CAN_MAX_RAM_SIZE; i++) {
for(i = 0U; i < CAN_MAX_RAM_SIZE; i++)
{
canram[i] = 0U;
}
/* reset CAN_RFIFOMPFx */
for(i = 0U; i < CAN_MAX_MAILBOX_NUM; i++) {
for(i = 0U; i < CAN_MAX_MAILBOX_NUM; i++)
{
CAN_RFIFOMPF(can_periph, i) = 0x00000000U;
}
/* reset internal state machines and CAN registers */
if(ERROR == can_software_reset(can_periph)) {
if(ERROR == can_software_reset(can_periph))
{
return ERROR;
}
@ -149,7 +157,8 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init
/* reset CAN_STAT */
CAN_STAT(can_periph) = (uint32_t)0xFFFFFFFFU;
CAN_TIMER(can_periph);
while(CAN_STAT(can_periph) & CAN_STAT_MS5_RFNE) {
while(CAN_STAT(can_periph) & CAN_STAT_MS5_RFNE)
{
CAN_STAT(can_periph) = CAN_STAT_MS5_RFNE;
}
@ -160,27 +169,33 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init
CAN_BT(can_periph) &= ~(CAN_BT_BAUDPSC | CAN_BT_SJW | CAN_BT_PTS | CAN_BT_PBS1 | CAN_BT_PBS2);
/* set self reception */
if((uint8_t)DISABLE == can_parameter_init->self_reception) {
if((uint8_t)DISABLE == can_parameter_init->self_reception)
{
CAN_CTL0(can_periph) |= CAN_CTL0_SRDIS;
}
/* enable local arbitration priority */
if((uint8_t)ENABLE == can_parameter_init->local_priority_enable) {
if((uint8_t)ENABLE == can_parameter_init->local_priority_enable)
{
CAN_CTL0(can_periph) |= CAN_CTL0_LAPRIOEN;
}
/* set rx private filters and mailbox queue */
if((uint8_t)ENABLE == can_parameter_init->rx_private_filter_queue_enable) {
if((uint8_t)ENABLE == can_parameter_init->rx_private_filter_queue_enable)
{
CAN_CTL0(can_periph) |= CAN_CTL0_RPFQEN;
}
/* configure edge filtering */
if((uint32_t)DISABLE == can_parameter_init->edge_filter_enable) {
if((uint32_t)DISABLE == can_parameter_init->edge_filter_enable)
{
CAN_CTL2(can_periph) |= CAN_CTL2_EFDIS;
}
/* configure protocol exception */
if((uint32_t)ENABLE == can_parameter_init->protocol_exception_enable) {
if((uint32_t)ENABLE == can_parameter_init->protocol_exception_enable)
{
CAN_CTL2(can_periph) |= CAN_CTL2_PREEN;
}
/* set mailbox stop transmission */
if((uint8_t)ENABLE == can_parameter_init->mb_tx_abort_enable) {
if((uint8_t)ENABLE == can_parameter_init->mb_tx_abort_enable)
{
CAN_CTL0(can_periph) |= CAN_CTL0_MST;
}
@ -229,7 +244,8 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init
void can_struct_para_init(can_struct_type_enum type, void *p_struct)
{
/* get type of the struct */
switch(type) {
switch(type)
{
/* used for initialize can_parameter_struct */
case CAN_INIT_STRUCT:
((can_parameter_struct *)p_struct)->self_reception = (uint8_t)DISABLE;
@ -387,15 +403,18 @@ ErrStatus can_operation_mode_enter(uint32_t can_periph, can_operation_modes_enum
CAN_CTL0(can_periph) &= ~(CAN_CTL0_PNEN | CAN_CTL0_PNMOD);
timeout = CAN_DELAY;
/* wait for inactive mode state */
while(((CAN_CTL0_NRDY | CAN_CTL0_INAS) != (CAN_CTL0(can_periph) & (CAN_CTL0_NRDY | CAN_CTL0_INAS))) && (timeout)) {
while(((CAN_CTL0_NRDY | CAN_CTL0_INAS) != (CAN_CTL0(can_periph) & (CAN_CTL0_NRDY | CAN_CTL0_INAS))) && (timeout))
{
timeout--;
}
if((CAN_CTL0_NRDY | CAN_CTL0_INAS) != (CAN_CTL0(can_periph) & (CAN_CTL0_NRDY | CAN_CTL0_INAS))) {
if((CAN_CTL0_NRDY | CAN_CTL0_INAS) != (CAN_CTL0(can_periph) & (CAN_CTL0_NRDY | CAN_CTL0_INAS)))
{
return ERROR;
}
/* configure the modes */
switch(mode) {
switch(mode)
{
case CAN_NORMAL_MODE:
CAN_CTL1(can_periph) &= ~(CAN_CTL1_LSCMOD | CAN_CTL1_MMOD);
break;
@ -422,24 +441,30 @@ ErrStatus can_operation_mode_enter(uint32_t can_periph, can_operation_modes_enum
}
/* exit INACTIVE mode */
if(CAN_INACTIVE_MODE != mode) {
if(CAN_INACTIVE_MODE != mode)
{
/* exit inactive mode */
CAN_CTL0(can_periph) &= ~(CAN_CTL0_HALT | CAN_CTL0_INAMOD);
timeout = CAN_DELAY;
while((CAN_CTL0(can_periph) & CAN_CTL0_INAS) && (timeout)) {
while((CAN_CTL0(can_periph) & CAN_CTL0_INAS) && (timeout))
{
timeout--;
}
if(CAN_CTL0(can_periph) & CAN_CTL0_INAS) {
if(CAN_CTL0(can_periph) & CAN_CTL0_INAS)
{
return ERROR;
}
}
if(CAN_PN_MODE == mode) {
if(CAN_PN_MODE == mode)
{
timeout = CAN_DELAY;
while((0U == (CAN_CTL0(can_periph) & CAN_CTL0_PNS)) && (timeout)) {
while((0U == (CAN_CTL0(can_periph) & CAN_CTL0_PNS)) && (timeout))
{
timeout--;
}
if(0U == (CAN_CTL0(can_periph) & CAN_CTL0_PNS)) {
if(0U == (CAN_CTL0(can_periph) & CAN_CTL0_PNS))
{
return ERROR;
}
}
@ -460,19 +485,25 @@ can_operation_modes_enum can_operation_mode_get(uint32_t can_periph)
reg = CAN_CTL0(can_periph);
reg &= (CAN_CTL0_NRDY | CAN_CTL0_INAS | CAN_CTL0_PNS | CAN_CTL0_LPS);
if((CAN_CTL0_NRDY | CAN_CTL0_LPS) == reg) {
if((CAN_CTL0_NRDY | CAN_CTL0_LPS) == reg)
{
state = CAN_DISABLE_MODE;
} else if((CAN_CTL0_NRDY | CAN_CTL0_INAS) == reg) {
} else if((CAN_CTL0_NRDY | CAN_CTL0_INAS) == reg)
{
state = CAN_INACTIVE_MODE;
} else if(0U == reg) {
if(CAN_CTL1(can_periph)&CAN_CTL1_MMOD) {
} else if(0U == reg)
{
if(CAN_CTL1(can_periph)&CAN_CTL1_MMOD)
{
state = CAN_MONITOR_MODE;
} else if(CAN_CTL1(can_periph)&CAN_CTL1_LSCMOD) {
} else if(CAN_CTL1(can_periph)&CAN_CTL1_LSCMOD)
{
state = CAN_LOOPBACK_SILENT_MODE;
} else {
state = CAN_NORMAL_MODE;
}
} else if(CAN_CTL0_PNS == reg) {
} else if(CAN_CTL0_PNS == reg)
{
state = CAN_PN_MODE;
} else {
/* should not get here */
@ -494,10 +525,12 @@ ErrStatus can_inactive_mode_exit(uint32_t can_periph)
/* exit inactive mode */
CAN_CTL0(can_periph) &= ~CAN_CTL0_HALT;
timeout = CAN_DELAY;
while((CAN_CTL0(can_periph) & CAN_CTL0_INAS) && (timeout)) {
while((CAN_CTL0(can_periph) & CAN_CTL0_INAS) && (timeout))
{
timeout--;
}
if(CAN_CTL0(can_periph) & CAN_CTL0_INAS) {
if(CAN_CTL0(can_periph) & CAN_CTL0_INAS)
{
return ERROR;
} else {
return SUCCESS;
@ -517,10 +550,12 @@ ErrStatus can_pn_mode_exit(uint32_t can_periph)
CAN_CTL0(can_periph) &= ~(CAN_CTL0_PNEN | CAN_CTL0_PNMOD);
timeout = CAN_DELAY;
while((CAN_CTL0(can_periph) & CAN_CTL0_PNS) && (timeout)) {
while((CAN_CTL0(can_periph) & CAN_CTL0_PNS) && (timeout))
{
timeout--;
}
if(CAN_CTL0(can_periph) & CAN_CTL0_PNS) {
if(CAN_CTL0(can_periph) & CAN_CTL0_PNS)
{
return ERROR;
} else {
return SUCCESS;
@ -556,15 +591,18 @@ void can_fd_config(uint32_t can_periph, can_fd_parameter_struct *can_fd_para_ini
CAN_CTL0(can_periph) |= CAN_CTL0_FDEN;
/* support ISO or non-ISO mode */
if((uint32_t)ENABLE == can_fd_para_init->iso_can_fd_enable) {
if((uint32_t)ENABLE == can_fd_para_init->iso_can_fd_enable)
{
CAN_CTL2(can_periph) |= CAN_CTL2_ISO;
}
/* set TDC parameter */
if((uint32_t)ENABLE == can_fd_para_init->tdc_enable) {
if((uint32_t)ENABLE == can_fd_para_init->tdc_enable)
{
CAN_FDCTL(can_periph) |= CAN_FDCTL_TDCEN;
}
/* set data bit rate */
if((uint32_t)ENABLE == can_fd_para_init->bitrate_switch_enable) {
if((uint32_t)ENABLE == can_fd_para_init->bitrate_switch_enable)
{
CAN_FDCTL(can_periph) |= CAN_FDCTL_BRSEN;
}
@ -669,12 +707,14 @@ void can_rx_fifo_config(uint32_t can_periph, can_fifo_parameter_struct *can_fifo
/* clear FIFO status */
CAN_STAT(can_periph) = (uint32_t)0xFFFFFFFFU;
while(CAN_STAT(can_periph) & CAN_STAT_MS5_RFNE) {
while(CAN_STAT(can_periph) & CAN_STAT_MS5_RFNE)
{
CAN_STAT(can_periph) = CAN_STAT_MS5_RFNE;
}
/* set DMA mode */
if((uint8_t)ENABLE == can_fifo_para_init->dma_enable) {
if((uint8_t)ENABLE == can_fifo_para_init->dma_enable)
{
CAN_CTL0(can_periph) |= CAN_CTL0_DMAEN;
}
@ -685,8 +725,10 @@ void can_rx_fifo_config(uint32_t can_periph, can_fifo_parameter_struct *can_fifo
/* configure fifo public fiter */
CAN_RFIFOPUBF(can_periph) = can_fifo_para_init->fifo_public_filter;
/* configure fifo private fiter */
if(!(CAN_CTL0(can_periph) & CAN_CTL0_RPFQEN)) {
for(num = 0U; num < CAN_MAX_MAILBOX_NUM; num++) {
if(!(CAN_CTL0(can_periph) & CAN_CTL0_RPFQEN))
{
for(num = 0U; num < CAN_MAX_MAILBOX_NUM; num++)
{
CAN_RFIFOMPF(can_periph, num) = can_fifo_para_init->fifo_public_filter;
}
}
@ -713,16 +755,20 @@ void can_rx_fifo_filter_table_config(uint32_t can_periph, can_rx_fifo_id_filter_
num_of_filters = (GET_CTL2_RFFN(CAN_CTL2(can_periph)) + 1U) * 8U;
id_format = CAN_CTL0(can_periph) & CAN_CTL0_FS;
switch(id_format) {
switch(id_format)
{
case(CAN_FIFO_FILTER_FORMAT_A):
/* one full id (standard and extended) per id filter table element */
for(i = 0U; i < num_of_filters; i++) {
for(i = 0U; i < num_of_filters; i++)
{
val = 0U;
if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[i].remote_frame) {
if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[i].remote_frame)
{
val |= CAN_FDESX_RTR_A;
}
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[i].extended_frame) {
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[i].extended_frame)
{
val |= CAN_FDESX_IDE_A;
val |= (uint32_t)FIFO_FILTER_ID_EXD_A(id_filter_table[i].id);
} else {
@ -734,13 +780,16 @@ void can_rx_fifo_filter_table_config(uint32_t can_periph, can_rx_fifo_id_filter_
case(CAN_FIFO_FILTER_FORMAT_B):
/* two full standard id or two partial 14-bit (standard and extended) id */
j = 0U;
for(i = 0U; i < num_of_filters; i++) {
for(i = 0U; i < num_of_filters; i++)
{
val = 0U;
if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[j].remote_frame) {
if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[j].remote_frame)
{
val |= CAN_FDESX_RTR_B0;
}
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) {
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame)
{
val |= CAN_FDESX_IDE_B0;
val |= (uint32_t)FIFO_FILTER_ID_EXD_B0(id_filter_table[j].id);
} else {
@ -748,10 +797,12 @@ void can_rx_fifo_filter_table_config(uint32_t can_periph, can_rx_fifo_id_filter_
}
j++;
if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[j].remote_frame) {
if(CAN_REMOTE_FRAME_ACCEPTED == id_filter_table[j].remote_frame)
{
val |= CAN_FDESX_RTR_B1;
}
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) {
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame)
{
val |= CAN_FDESX_IDE_B1;
val |= (uint32_t)FIFO_FILTER_ID_EXD_B1(id_filter_table[j].id);
} else {
@ -765,27 +816,32 @@ void can_rx_fifo_filter_table_config(uint32_t can_periph, can_rx_fifo_id_filter_
case(CAN_FIFO_FILTER_FORMAT_C):
/* four partial 8-bit standard id per id filter table element */
j = 0U;
for(i = 0U; i < num_of_filters; i++) {
for(i = 0U; i < num_of_filters; i++)
{
val = 0U;
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) {
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame)
{
val |= (uint32_t)FIFO_FILTER_ID_EXD_C0(id_filter_table[j].id);
} else {
val |= (uint32_t)FIFO_FILTER_ID_STD_C0(id_filter_table[j].id);
}
j++;
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) {
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame)
{
val |= (uint32_t)FIFO_FILTER_ID_EXD_C1(id_filter_table[j].id);
} else {
val |= (uint32_t)FIFO_FILTER_ID_STD_C1(id_filter_table[j].id);
}
j++;
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) {
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame)
{
val |= (uint32_t)FIFO_FILTER_ID_EXD_C2(id_filter_table[j].id);
} else {
val |= (uint32_t)FIFO_FILTER_ID_STD_C2(id_filter_table[j].id);
}
j++;
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame) {
if(CAN_EXTENDED_FRAME_ACCEPTED == id_filter_table[j].extended_frame)
{
val |= (uint32_t)FIFO_FILTER_ID_EXD_C3(id_filter_table[j].id);
} else {
val |= (uint32_t)FIFO_FILTER_ID_STD_C3(id_filter_table[j].id);
@ -825,7 +881,8 @@ void can_rx_fifo_read(uint32_t can_periph, can_rx_fifo_struct *rx_fifo)
CAN_STAT(can_periph) = CAN_STAT_MS5_RFNE;
/* read FIFO id field */
if(rx_fifo->ide) {
if(rx_fifo->ide)
{
rx_fifo->id = GET_FDES1_ID_EXD(rx_fifo->id);
} else {
rx_fifo->id = GET_FDES1_ID_STD(rx_fifo->id);
@ -870,7 +927,8 @@ uint32_t *can_ram_address_get(uint32_t can_periph, uint32_t index)
uint32_t *address;
/* if CAN FD mode is enabled */
if(CAN_CTL0(can_periph) & CAN_CTL0_FDEN) {
if(CAN_CTL0(can_periph) & CAN_CTL0_FDEN)
{
payload_size = (uint32_t)1U << (GET_FDCTL_MDSZ(CAN_FDCTL(can_periph)) + 3U);
} else {
payload_size = 8U;
@ -920,12 +978,14 @@ void can_mailbox_config(uint32_t can_periph, uint32_t index, can_mailbox_descrip
mdes[3] = 0U;
/* set RTR bit */
if(mdpara->rtr) {
if(mdpara->rtr)
{
mdes0 |= CAN_MDES0_RTR;
}
/* set IDE bit and ID field */
if(mdpara->ide) {
if(mdpara->ide)
{
mdes0 |= CAN_MDES0_IDE;
mdes0 |= CAN_MDES0_SRR;
mdes[1] |= MDES1_ID_EXD(mdpara->id);
@ -936,28 +996,35 @@ void can_mailbox_config(uint32_t can_periph, uint32_t index, can_mailbox_descrip
/* set CODE field */
mdes0 |= MDES0_CODE(mdpara->code);
if(mdpara->code != CAN_MB_RX_STATUS_EMPTY) {
if(mdpara->code != CAN_MB_RX_STATUS_EMPTY)
{
/* copy user's buffer into the mailbox data area */
if(mdpara->data_bytes) {
if(mdpara->data_bytes)
{
dlc = can_dlc_value_compute(mdpara->data_bytes);
mdes0 |= MDES0_DLC(dlc);
length = (uint32_t)1U << (GET_FDCTL_MDSZ(CAN_FDCTL(can_periph)) + 3U);
if(mdpara->data_bytes < length) {
if(mdpara->data_bytes < length)
{
length = mdpara->data_bytes;
}
can_data_to_big_endian_swap(&mdes[2], mdpara->data, length);
}
/* prepare mailbox for transmission */
if(CAN_MB_TX_STATUS_DATA == mdpara->code) {
if(CAN_MB_TX_STATUS_DATA == mdpara->code)
{
/* set ESI bit */
if(mdpara->esi) {
if(mdpara->esi)
{
mdes0 |= CAN_MDES0_ESI;
}
/* set FDF and BRS bit */
if(mdpara->fdf) {
if(mdpara->fdf)
{
mdes0 |= CAN_MDES0_FDF;
if(mdpara->brs) {
if(mdpara->brs)
{
mdes0 |= CAN_MDES0_BRS;
}
mdes0 &= ~CAN_MDES0_RTR;
@ -1035,10 +1102,12 @@ ErrStatus can_mailbox_receive_data_read(uint32_t can_periph, uint32_t index, can
/* wait mailbox data ready */
timeout = CAN_DELAY;
while((mdes[0] & MDES0_CODE(CAN_MB_RX_STATUS_BUSY)) && (timeout)) {
while((mdes[0] & MDES0_CODE(CAN_MB_RX_STATUS_BUSY)) && (timeout))
{
timeout--;
}
if(mdes[0] & MDES0_CODE(CAN_MB_RX_STATUS_BUSY)) {
if(mdes[0] & MDES0_CODE(CAN_MB_RX_STATUS_BUSY))
{
return ERROR;
}
@ -1049,7 +1118,8 @@ ErrStatus can_mailbox_receive_data_read(uint32_t can_periph, uint32_t index, can
cnt = (mdpara->data_bytes + 3U) / 4U;
mdaddr = mdpara->data;
mdes += 2U;
for(i = 0U; i < cnt; i++) {
for(i = 0U; i < cnt; i++)
{
mdaddr[i] = mdes[i];
}
@ -1059,14 +1129,16 @@ ErrStatus can_mailbox_receive_data_read(uint32_t can_periph, uint32_t index, can
CAN_TIMER(can_periph);
/* get mailbox ID */
if(mdpara->ide) {
if(mdpara->ide)
{
mdpara->id = GET_MDES1_ID_EXD(mdpara->id);
} else {
mdpara->id = GET_MDES1_ID_STD(mdpara->id);
}
/* get mailbox data */
if(mdpara->data_bytes) {
if(mdpara->data_bytes)
{
can_data_to_little_endian_swap(mdpara->data, mdpara->data, mdpara->data_bytes);
}
@ -1191,7 +1263,8 @@ can_error_state_enum can_error_state_get(uint32_t can_periph)
uint32_t reg;
reg = GET_ERR1_ERRSI(CAN_ERR1(can_periph));
if(reg >= (uint32_t)CAN_ERROR_STATE_BUS_OFF) {
if(reg >= (uint32_t)CAN_ERROR_STATE_BUS_OFF)
{
reg = (uint32_t)CAN_ERROR_STATE_BUS_OFF;
}
@ -1285,13 +1358,16 @@ void can_pn_mode_filter_config(uint32_t can_periph, can_pn_mode_filter_struct *e
/* set filter identifier 0 */
reg = 0U;
if((uint32_t)SET == expect->ide) {
if((uint32_t)SET == expect->ide)
{
reg |= CAN_PN_EID0_EIDE;
}
if((uint32_t)SET == expect->rtr) {
if((uint32_t)SET == expect->rtr)
{
reg |= CAN_PN_EID0_ERTR;
}
if(CAN_STANDARD == (expect->id & BIT(31))){
if(CAN_STANDARD == (expect->id & BIT(31)))
{
reg |= (uint32_t)PN_EID0_EIDF_ELT_STD(expect->id);
}else{
reg |= (uint32_t)PN_EID0_EIDF_ELT_EXD(expect->id);
@ -1302,17 +1378,21 @@ void can_pn_mode_filter_config(uint32_t can_periph, can_pn_mode_filter_struct *e
temp = CAN_PN_CTL0(can_periph);
reg = 0U;
/* ID field 1 is used when ID filtering type is EXACT or RANGE */
if(((temp & CAN_PN_CTL0_IDFT) == CAN_PN_ID_FILTERING_EXACT) || ((temp & CAN_PN_CTL0_IDFT) == CAN_PN_ID_FILTERING_RANGE)) {
if(CAN_STANDARD == (filter->id & BIT(31))){
if(((temp & CAN_PN_CTL0_IDFT) == CAN_PN_ID_FILTERING_EXACT) || ((temp & CAN_PN_CTL0_IDFT) == CAN_PN_ID_FILTERING_RANGE))
{
if(CAN_STANDARD == (filter->id & BIT(31)))
{
reg |= (uint32_t)PN_IFEID1_IDEFD_STD(filter->id);
}else{
reg |= (uint32_t)PN_IFEID1_IDEFD_EXD(filter->id);
}
}
if((uint32_t)SET == filter->ide) {
if((uint32_t)SET == filter->ide)
{
reg |= CAN_PN_IFEID1_IDEFD;
}
if((uint32_t)SET == filter->rtr) {
if((uint32_t)SET == filter->rtr)
{
reg |= CAN_PN_IFEID1_RTRFD;
}
/* set filter identifier 1 */
@ -1320,7 +1400,8 @@ void can_pn_mode_filter_config(uint32_t can_periph, can_pn_mode_filter_struct *e
/* data field is used when frame filtering type is not MATCH or MATCH NMM */
if(((temp & CAN_PN_CTL0_FFT) == CAN_PN_FRAME_FILTERING_ID_DATA) ||
((temp & CAN_PN_CTL0_FFT) == CAN_PN_FRAME_FILTERING_ID_DATA_NMM)) {
((temp & CAN_PN_CTL0_FFT) == CAN_PN_FRAME_FILTERING_ID_DATA_NMM))
{
/* set filter data payload 0 */
CAN_PN_EDLC(can_periph) = PN_EDLC_DLCEHT(expect->dlc_high_threshold) | PN_EDLC_DLCELT(expect->dlc_low_threshold);
CAN_PN_EDL0(can_periph) = ((expect->payload[0] << 24U) & CAN_PN_EDL0_DB0ELT) |
@ -1334,7 +1415,8 @@ void can_pn_mode_filter_config(uint32_t can_periph, can_pn_mode_filter_struct *e
/* data field 1 is used when data filtering type is EXACT or RANGE */
if(((temp & CAN_PN_CTL0_DATAFT) == CAN_PN_DATA_FILTERING_EXACT)
|| ((temp & CAN_PN_CTL0_DATAFT) == CAN_PN_DATA_FILTERING_RANGE)) {
|| ((temp & CAN_PN_CTL0_DATAFT) == CAN_PN_DATA_FILTERING_RANGE))
{
/* set filter data payload 1 */
CAN_PN_DF0EDH0(can_periph) = ((filter->payload[0] << 24U) & CAN_PN_DF0EDH0_DB0FD_EHT) |
((filter->payload[0] << 8U) & CAN_PN_DF0EDH0_DB1FD_EHT) |
@ -1361,7 +1443,8 @@ int32_t can_pn_mode_num_of_match_get(uint32_t can_periph)
uint32_t reg = 0U;
reg = CAN_PN_STAT(can_periph);
if(0U != (reg & CAN_PN_STAT_MMCNTS)) {
if(0U != (reg & CAN_PN_STAT_MMCNTS))
{
ret = (int32_t)(uint32_t)GET_PN_STAT_MMCNT(reg);
} else {
ret = -1;
@ -1386,24 +1469,28 @@ void can_pn_mode_data_read(uint32_t can_periph, uint32_t index, can_mailbox_desc
mdaddr[0] = pnram[0];
mdaddr[1] = pnram[1];
/* get mailbox ID */
if(0U != mdpara->ide) {
if(0U != mdpara->ide)
{
mdpara->id = GET_MDES1_ID_EXD(mdpara->id);
} else {
mdpara->id = GET_MDES1_ID_STD(mdpara->id);
}
mdpara->data_bytes = mdpara->dlc;
/* remote frame */
if(0U != (mdaddr[0] & CAN_PN_RWMXCS_RRTR)){
if(0U != (mdaddr[0] & CAN_PN_RWMXCS_RRTR))
{
mdpara->data_bytes = 0U;
}else{
/* classical frame */
if(mdpara->dlc <= 8U) {
if(mdpara->dlc <= 8U)
{
mdpara->data_bytes = mdpara->dlc;
}else{
mdpara->data_bytes = 8U;
}
}
if(mdpara->data_bytes) {
if(mdpara->data_bytes)
{
can_data_to_little_endian_swap(mdpara->data, &pnram[2], mdpara->data_bytes);
}
}
@ -1567,7 +1654,8 @@ void can_arbitration_delay_bits_config(uint32_t can_periph, uint32_t delay_bits)
*/
void can_bsp_mode_config(uint32_t can_periph, uint32_t sampling_mode)
{
if(CAN_BSP_MODE_ONE_SAMPLE == sampling_mode) {
if(CAN_BSP_MODE_ONE_SAMPLE == sampling_mode)
{
CAN_CTL1(can_periph) &= ~CAN_CTL1_BSPMOD;
} else {
CAN_CTL1(can_periph) |= CAN_CTL1_BSPMOD;
@ -1615,7 +1703,8 @@ void can_bsp_mode_config(uint32_t can_periph, uint32_t sampling_mode)
*/
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag)
{
if(CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag))) {
if(CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))
{
return SET;
} else {
return RESET;
@ -1644,7 +1733,8 @@ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag)
*/
void can_flag_clear(uint32_t can_periph, can_flag_enum flag)
{
if(CAN_FLAG_TDC_OUT_OF_RANGE == flag) {
if(CAN_FLAG_TDC_OUT_OF_RANGE == flag)
{
CAN_FDCTL(can_periph) |= CAN_FDCTL_TDCS;
} else {
CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag));
@ -1677,14 +1767,17 @@ ErrStatus can_interrupt_enable(uint32_t can_periph, can_interrupt_enum interrupt
ErrStatus ret = SUCCESS;
/* enable receive or transmit warning error interrupt should enable error warning in CTL0 register */
if((CAN_INT_RX_WARNING == interrupt) || (CAN_INT_TX_WARNING == interrupt)) {
if((CAN_INT_RX_WARNING == interrupt) || (CAN_INT_TX_WARNING == interrupt))
{
mode = can_operation_mode_get(can_periph);
/* in INACTIVE mode */
if(CAN_INACTIVE_MODE == mode){
if(CAN_INACTIVE_MODE == mode)
{
CAN_CTL0(can_periph) |= CAN_CTL0_WERREN;
}else{
ret = can_operation_mode_enter(can_periph, CAN_INACTIVE_MODE);
if(SUCCESS == ret){
if(SUCCESS == ret)
{
CAN_CTL0(can_periph) |= CAN_CTL0_WERREN;
ret = can_operation_mode_enter(can_periph, mode);
}
@ -1721,14 +1814,17 @@ ErrStatus can_interrupt_disable(uint32_t can_periph, can_interrupt_enum interrup
ErrStatus ret = SUCCESS;
/* disable receive or transmit warning error interrupt should enable error warning in CTL0 register */
if((0U == (CAN_CTL0(can_periph) & CAN_CTL0_WERREN)) && ((CAN_INT_RX_WARNING == interrupt) || (CAN_INT_TX_WARNING == interrupt))) {
if((0U == (CAN_CTL0(can_periph) & CAN_CTL0_WERREN)) && ((CAN_INT_RX_WARNING == interrupt) || (CAN_INT_TX_WARNING == interrupt)))
{
mode = can_operation_mode_get(can_periph);
/* in INACTIVE mode */
if(CAN_INACTIVE_MODE == mode){
if(CAN_INACTIVE_MODE == mode)
{
CAN_CTL0(can_periph) |= CAN_CTL0_WERREN;
}else{
ret = can_operation_mode_enter(can_periph, CAN_INACTIVE_MODE);
if(SUCCESS == ret){
if(SUCCESS == ret)
{
CAN_CTL0(can_periph) |= CAN_CTL0_WERREN;
ret = can_operation_mode_enter(can_periph, mode);
}
@ -1761,7 +1857,8 @@ ErrStatus can_interrupt_disable(uint32_t can_periph, can_interrupt_enum interrup
*/
FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum int_flag)
{
if(CAN_REG_VAL(can_periph, int_flag) & BIT(CAN_BIT_POS(int_flag))) {
if(CAN_REG_VAL(can_periph, int_flag) & BIT(CAN_BIT_POS(int_flag)))
{
return SET;
} else {
return RESET;
@ -1805,17 +1902,21 @@ static uint32_t can_payload_size_compute(uint32_t mdes0)
uint32_t dlc_value = GET_MDES0_DLC(mdes0);
/* remote frame */
if(0U != (mdes0 & CAN_MDES0_RTR)){
if(0U != (mdes0 & CAN_MDES0_RTR))
{
ret = 0U;
}else{
/* FD frame */
if(0U != (mdes0 & CAN_MDES0_FDF)){
if(dlc_value <= 15U) {
if(0U != (mdes0 & CAN_MDES0_FDF))
{
if(dlc_value <= 15U)
{
ret = dlc_to_databytes[dlc_value];
}
/* classical frame */
}else{
if(dlc_value <= 8U) {
if(dlc_value <= 8U)
{
ret = (uint8_t)dlc_value;
}else{
ret = 8U;
@ -1842,7 +1943,8 @@ static void can_data_to_little_endian_swap(uint32_t dest[], uint32_t src[], uint
/* get the word length of the data */
cnt = (len + 3U) / 4U;
/* change each word from big endian to little endian */
for(i = 0U; i < cnt; i++) {
for(i = 0U; i < cnt; i++)
{
temp_src = src[i];
dest[i] = ((uint32_t)(temp_src >> 24U) & 0x000000FFU) |
((uint32_t)(temp_src >> 8U) & 0x0000FF00U) |
@ -1851,7 +1953,8 @@ static void can_data_to_little_endian_swap(uint32_t dest[], uint32_t src[], uint
}
cnt = len % 4U;
if(cnt) {
if(cnt)
{
dest[i - 1U] &= ((uint32_t)1U << (cnt * 8U)) - 1U;
}
}
@ -1871,7 +1974,8 @@ static void can_data_to_big_endian_swap(uint32_t dest[], uint32_t src[], uint32_
/* get the word length of the data */
cnt = (len + 3U) / 4U;
for(i = 0U; i < cnt; i++) {
for(i = 0U; i < cnt; i++)
{
/* change each word from little endian to big endian */
temp_src = src[i];
dest[i] = ((uint32_t)(temp_src >> 24U) & 0x000000FFU) |
@ -1881,7 +1985,8 @@ static void can_data_to_big_endian_swap(uint32_t dest[], uint32_t src[], uint32_
}
cnt = len % 4U;
if(cnt) {
if(cnt)
{
dest[i - 1U] &= ~(((uint32_t)1U << ((4U - cnt) * 8U)) - 1U);
}
}
@ -1896,11 +2001,14 @@ static uint32_t can_dlc_value_compute(uint32_t payload_size)
{
uint32_t ret = 8U;
if(payload_size <= 8U) {
if(payload_size <= 8U)
{
ret = payload_size;
} else if(payload_size <= 24U) {
} else if(payload_size <= 24U)
{
ret = (payload_size - 9U) / 4U + 9U;
} else if(payload_size <= 64U) {
} else if(payload_size <= 64U)
{
ret = (payload_size - 17U) / 16U + 13U;
} else {
ret = 8U;

42
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cau.c
View File

@ -408,7 +408,8 @@ void cau_fifo_flush(void)
ControlStatus cau_enable_state_get(void)
{
ControlStatus ret = DISABLE;
if(RESET != (CAU_CTL & CAU_CTL_CAUEN)) {
if(RESET != (CAU_CTL & CAU_CTL_CAUEN))
{
ret = ENABLE;
}
return ret;
@ -476,7 +477,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
algm_reg = CAU_CTL & CAU_CTL_ALGM;
/* AES or DES */
if((uint32_t)0 != (algm_reg & (~CAU_MODE_TDES_CBC))) {
if((uint32_t)0 != (algm_reg & (~CAU_MODE_TDES_CBC)))
{
/* wait until both the IN and OUT FIFOs are empty (IEM=1 and ONE=0 in the CAU_STAT0 register) and BUSY=0 */
checkbits = CAU_STAT0_IEM;
checkmask = STAT0_AESDES_MASK;
@ -487,7 +489,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
checkmask = STAT0_TDES_MASK;
}
while((CAU_STAT0 & checkmask) != checkbits) {
while((CAU_STAT0 & checkmask) != checkbits)
{
}
/* stop DMA transfers on the OUT FIFO by clear CAU_DMAEN_DMAOEN=0 */
@ -513,7 +516,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
cau_context->key_3_high = key_initpara->key_3_high;
cau_context->key_3_low = key_initpara->key_3_low;
if((CAU_MODE_TDES_ECB != algm_reg) && (CAU_MODE_DES_ECB != algm_reg) && (CAU_MODE_AES_ECB != algm_reg)) {
if((CAU_MODE_TDES_ECB != algm_reg) && (CAU_MODE_DES_ECB != algm_reg) && (CAU_MODE_AES_ECB != algm_reg))
{
/* if not in ECB mode, save the initialization vectors */
cau_context->iv_0_high = CAU_IV0H;
cau_context->iv_0_low = CAU_IV0L;
@ -522,7 +526,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
}
/* if in GCM/CCM mode, save the context switch registers */
if((CAU_MODE_AES_GCM == algm_reg) || (CAU_MODE_AES_CCM == algm_reg)) {
if((CAU_MODE_AES_GCM == algm_reg) || (CAU_MODE_AES_CCM == algm_reg))
{
cau_context->gcmccmctxs[0U] = CAU_GCMCCMCTXSx(0U);
cau_context->gcmccmctxs[1U] = CAU_GCMCCMCTXSx(1U);
cau_context->gcmccmctxs[2U] = CAU_GCMCCMCTXSx(2U);
@ -534,7 +539,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
}
/* if in GCM mode, save the context switch registers */
if(CAU_MODE_AES_GCM == algm_reg) {
if(CAU_MODE_AES_GCM == algm_reg)
{
cau_context->gcmctxs[0U] = CAU_GCMCTXSx(0U);
cau_context->gcmctxs[1U] = CAU_GCMCTXSx(1U);
cau_context->gcmctxs[2U] = CAU_GCMCTXSx(2U);
@ -586,7 +592,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
CAU_KEY3H = cau_context->key_3_high;
CAU_KEY3L = cau_context->key_3_low;
if((CAU_MODE_TDES_ECB != algm_reg) && (CAU_MODE_DES_ECB != algm_reg) && (CAU_MODE_AES_ECB != algm_reg)) {
if((CAU_MODE_TDES_ECB != algm_reg) && (CAU_MODE_DES_ECB != algm_reg) && (CAU_MODE_AES_ECB != algm_reg))
{
/* restore the initialization vectors */
CAU_IV0H = cau_context->iv_0_high;
CAU_IV0L = cau_context->iv_0_low;
@ -595,7 +602,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
}
/* if in GCM/CCM mode, restore the context switch registers */
if((CAU_MODE_AES_GCM == algm_reg) || (CAU_MODE_AES_CCM == algm_reg)) {
if((CAU_MODE_AES_GCM == algm_reg) || (CAU_MODE_AES_CCM == algm_reg))
{
CAU_GCMCCMCTXSx(0U) = cau_context->gcmccmctxs[0U];
CAU_GCMCCMCTXSx(1U) = cau_context->gcmccmctxs[1U];
CAU_GCMCCMCTXSx(2U) = cau_context->gcmccmctxs[2U];
@ -607,7 +615,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
}
/* if in GCM mode, restore the context switch registers */
if(CAU_MODE_AES_GCM == algm_reg) {
if(CAU_MODE_AES_GCM == algm_reg)
{
CAU_GCMCTXSx(0U) = cau_context->gcmctxs[0U];
CAU_GCMCTXSx(1U) = cau_context->gcmctxs[1U];
CAU_GCMCTXSx(2U) = cau_context->gcmctxs[2U];
@ -620,7 +629,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
/* if it is AES ECB/CBC decryption, then first prepare key */
aes_decrypt = CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR);
if(((CAU_MODE_AES_ECB | CAU_DECRYPT) == aes_decrypt) || ((CAU_MODE_AES_CBC | CAU_DECRYPT) == aes_decrypt)) {
if(((CAU_MODE_AES_ECB | CAU_DECRYPT) == aes_decrypt) || ((CAU_MODE_AES_CBC | CAU_DECRYPT) == aes_decrypt))
{
uint32_t alg_dir, algo_mode, swapping;
/* flush IN/OUT FIFOs */
@ -635,7 +645,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
cau_enable();
/* wait until BUSY=0 */
while((uint32_t)0U != cau_flag_get(CAU_FLAG_BUSY)) {
while((uint32_t)0U != cau_flag_get(CAU_FLAG_BUSY))
{
}
/* parameters for decryption */
@ -666,7 +677,8 @@ FlagStatus cau_flag_get(uint32_t flag)
FlagStatus ret_flag = RESET;
/* check if the flag is in CAU_STAT1 register */
if(RESET != (flag & FLAG_MASK)) {
if(RESET != (flag & FLAG_MASK))
{
reg = CAU_STAT1;
} else {
/* the flag is in CAU_STAT0 register */
@ -674,7 +686,8 @@ FlagStatus cau_flag_get(uint32_t flag)
}
/* check the status of the specified CAU flag */
if(RESET != (reg & flag)) {
if(RESET != (reg & flag))
{
ret_flag = SET;
}
@ -725,7 +738,8 @@ FlagStatus cau_interrupt_flag_get(uint32_t int_flag)
FlagStatus flag = RESET;
/* check the status of the specified CAU interrupt */
if(RESET != (CAU_INTF & int_flag)) {
if(RESET != (CAU_INTF & int_flag))
{
flag = SET;
}

141
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cau_aes.c
View File

@ -74,7 +74,8 @@ ErrStatus cau_aes_ecb(cau_parameter_struct *cau_parameter, uint8_t *output)
cau_key_init(&key_initpara);
/* AES decryption */
if(CAU_DECRYPT == cau_parameter->alg_dir) {
if(CAU_DECRYPT == cau_parameter->alg_dir)
{
/* flush the IN and OUT FIFOs */
cau_fifo_flush();
/* initialize the CAU peripheral */
@ -89,7 +90,8 @@ ErrStatus cau_aes_ecb(cau_parameter_struct *cau_parameter, uint8_t *output)
counter++;
} while((AESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) {
if(RESET != busystatus)
{
return ERROR;
}
}
@ -141,7 +143,8 @@ ErrStatus cau_aes_cbc(cau_parameter_struct *cau_parameter, uint8_t *output)
cau_key_init(&key_initpara);
/* AES decryption */
if(CAU_DECRYPT == cau_parameter->alg_dir) {
if(CAU_DECRYPT == cau_parameter->alg_dir)
{
/* flush the IN and OUT FIFOs */
cau_fifo_flush();
/* initialize the CAU peripheral */
@ -156,7 +159,8 @@ ErrStatus cau_aes_cbc(cau_parameter_struct *cau_parameter, uint8_t *output)
counter++;
} while((AESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) {
if(RESET != busystatus)
{
return ERROR;
}
}
@ -396,11 +400,13 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* enable the CAU peripheral */
cau_enable();
/* wait for CAUEN bit to be 0 */
while(ENABLE == cau_enable_state_get()) {
while(ENABLE == cau_enable_state_get())
{
}
/* aad phase */
if((uint32_t)0U != cau_parameter->aad_size) {
if((uint32_t)0U != cau_parameter->aad_size)
{
/* select aad phase */
cau_phase_config(CAU_AAD_PHASE);
/* flush the IN and OUT FIFOs */
@ -410,13 +416,15 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
ret = cau_fill_data(cau_parameter->aad, cau_parameter->aad_size);
if(ERROR == ret) {
if(ERROR == ret)
{
return ret;
}
}
/* encrypt or decrypt phase */
if((uint32_t)0U != cau_parameter->in_length) {
if((uint32_t)0U != cau_parameter->in_length)
{
/* select encrypt or decrypt phase */
cau_phase_config(CAU_ENCRYPT_DECRYPT_PHASE);
/* flush the IN and OUT FIFOs */
@ -427,7 +435,8 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* AES calculate process */
ret = cau_aes_calculate(cau_parameter->input, cau_parameter->in_length, output);
if(ERROR == ret) {
if(ERROR == ret)
{
return ret;
}
}
@ -440,7 +449,8 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* enable the CAU peripheral */
cau_enable();
if(DISABLE == cau_enable_state_get()) {
if(DISABLE == cau_enable_state_get())
{
return ERROR;
}
@ -450,7 +460,8 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
cau_data_write(__REV((uint32_t)inputlength));
/* wait until the ONE flag is set */
while(RESET == cau_flag_get(CAU_FLAG_OUTFIFO_NO_EMPTY)) {
while(RESET == cau_flag_get(CAU_FLAG_OUTFIFO_NO_EMPTY))
{
}
/* read the tag in the OUT FIFO */
@ -510,9 +521,11 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
uint32_t temp_tag[4U];
/* formatting the aad block */
if((uint32_t)0U != aadsize) {
if((uint32_t)0U != aadsize)
{
/* check that the aad length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
if(aadsize < 65280U) {
if(aadsize < 65280U)
{
aad_buf[head_index++] = (uint8_t)((aadsize >> 8U) & 0xFFU);
aad_buf[head_index++] = (uint8_t)((aadsize) & 0xFFU);
aad_block_size = aadsize + 2U;
@ -527,13 +540,16 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
aad_block_size = aadsize + 6U;
}
/* copy the aad buffer in internal buffer "HBuffer" */
for(i = 0U; i < aadsize; i++) {
for(i = 0U; i < aadsize; i++)
{
aad_buf[head_index++] = *(uint8_t *)((uint32_t)(aadaddr + i));
}
/* check if the aad block size is modulo 16 */
if(0U != (aad_block_size % 16U)) {
if(0U != (aad_block_size % 16U))
{
/* Pad the aad buffer with 0s till the HBuffer length is modulo 16 */
for(i = aad_block_size; i <= ((aad_block_size / 16U) + 1U) * 16U; i++) {
for(i = aad_block_size; i <= ((aad_block_size / 16U) + 1U) * 16U; i++)
{
aad_buf[i] = 0U;
}
/* set the aad size to modulo 16 */
@ -544,26 +560,31 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
}
/* formatting the block B0 */
if(0U != aadsize) {
if(0U != aadsize)
{
blockb0[0] = 0x40U;
}
/* flags byte */
blockb0[0] |= (0U | (((((uint8_t) tag_size - 2U) / 2U) & 0x07U) << 3U) | (((uint8_t)(15U - ivsize) - 1U) & 0x07U));
if(ivsize > MAX_CCM_IV_SIZE) {
if(ivsize > MAX_CCM_IV_SIZE)
{
return ERROR;
}
for(i = 0U; i < ivsize; i++) {
for(i = 0U; i < ivsize; i++)
{
blockb0[i + 1U] = *(uint8_t *)((uint32_t)(ivaddr + i));
}
/* the byte length for payload length expressing, which plus the ivsize must equal to 15 bytes */
plen = 15U - ivsize;
/* if the byte length for payload length expressing is more than 4 bytes */
if(plen > 4U) {
if(plen > 4U)
{
/* pad the blockb0 after vectors, and before the last 4 bytes */
for(; i < 11U; i++) {
for(; i < 11U; i++)
{
blockb0[i + 1U] = 0U;
}
blockb0[12U] = (uint8_t)((inputsize >> 24U) & 0xFFU);
@ -572,7 +593,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
blockb0[15U] = (uint8_t)(inputsize & 0xFFU);
} else {
/* the payload length is expressed in plen bytes */
for(; i < 15U; i++) {
for(; i < 15U; i++)
{
blockb0[i + 1U] = (uint8_t)((inputsize >> ((plen - 1U) * 8U)) & 0xFFU);
plen--;
}
@ -581,7 +603,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* formatting the initial counter */
/* byte 0: bits 0-2 contain the same encoding of q as in B0 */
counter[0] = blockb0[0] & BLOCK_B0_MASK;
for(i = 1U; i < ivsize + 1U; i++) {
for(i = 1U; i < ivsize + 1U; i++)
{
counter[i] = blockb0[i];
}
/* set the LSB to 1 */
@ -628,11 +651,13 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
cau_data_write(*(uint32_t *)(b0addr));
/* wait for CAUEN bit to be 0 */
while(ENABLE == cau_enable_state_get()) {
while(ENABLE == cau_enable_state_get())
{
}
/* aad phase */
if((uint32_t)0U != aadsize) {
if((uint32_t)0U != aadsize)
{
/* select aad phase */
cau_phase_config(CAU_AAD_PHASE);
/* enable the CAU peripheral */
@ -640,7 +665,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
ret = cau_fill_data((uint8_t *)aadaddr, aad_block_size);
if(ERROR == ret) {
if(ERROR == ret)
{
return ret;
}
}
@ -648,7 +674,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* encrypt or decrypt phase */
inputsize = cau_parameter->in_length;
if((uint32_t)0U != inputsize) {
if((uint32_t)0U != inputsize)
{
/* select encrypt or decrypt phase */
cau_phase_config(CAU_ENCRYPT_DECRYPT_PHASE);
/* enable the CAU peripheral */
@ -657,7 +684,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* AES calculate process */
ret = cau_aes_calculate((uint8_t *)inputaddr, inputsize, (uint8_t *)outputaddr);
if(ERROR == ret) {
if(ERROR == ret)
{
return ret;
}
}
@ -668,7 +696,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* enable the CAU peripheral */
cau_enable();
if(DISABLE == cau_enable_state_get()) {
if(DISABLE == cau_enable_state_get())
{
return ERROR;
}
@ -684,7 +713,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
cau_data_write(*(uint32_t *)(ctraddr) & 0xFEFFFFFFU);
/* wait until the ONE flag is set */
while(RESET == cau_flag_get(CAU_FLAG_OUTFIFO_NO_EMPTY)) {
while(RESET == cau_flag_get(CAU_FLAG_OUTFIFO_NO_EMPTY))
{
}
/* read the tag in the OUT FIFO */
@ -697,7 +727,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
cau_disable();
/* Copy temporary authentication TAG in user TAG buffer */
for(i = 0U; i < tag_size; i++) {
for(i = 0U; i < tag_size; i++)
{
tag[i] = (uint8_t)(temp_tag[i / 4U] >> (8U * (i % 4U)));
}
@ -722,7 +753,8 @@ static void cau_aes_key_config(uint8_t *key, uint32_t keysize, cau_key_parameter
{
uint32_t keyaddr = (uint32_t)key;
switch(keysize) {
switch(keysize)
{
/* 128-bit key initialization */
case 128:
cau_aes_keysize_config(CAU_KEYSIZE_128BIT);
@ -786,16 +818,20 @@ static ErrStatus cau_fill_data(uint8_t *input, uint32_t in_length)
__IO uint32_t counter = 0U;
uint32_t busystatus = 0U;
if(DISABLE == cau_enable_state_get()) {
if(DISABLE == cau_enable_state_get())
{
return ERROR;
}
for(i = 0U; i < in_length; i += BLOCK_DATA_SIZE) {
for(i = 0U; i < in_length; i += BLOCK_DATA_SIZE)
{
/* wait until the IEM flag is set */
while(RESET == cau_flag_get(CAU_FLAG_INFIFO_EMPTY)) {
while(RESET == cau_flag_get(CAU_FLAG_INFIFO_EMPTY))
{
}
if(i + BLOCK_DATA_SIZE > in_length) {
if(i + BLOCK_DATA_SIZE > in_length)
{
/* the last block data number is less than 128bit */
uint32_t block_data_temp[4] = {0U};
@ -804,10 +840,13 @@ static ErrStatus cau_fill_data(uint8_t *input, uint32_t in_length)
inputaddr = (uint32_t)block_data_temp;
/* if GCM encryption or CCM decryption, then configurate NBPILB bits in CTL register */
if((CAU_CTL & CAU_CTL_GCM_CCMPH) == CAU_ENCRYPT_DECRYPT_PHASE) {
if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_GCM | CAU_ENCRYPT)) {
if((CAU_CTL & CAU_CTL_GCM_CCMPH) == CAU_ENCRYPT_DECRYPT_PHASE)
{
if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_GCM | CAU_ENCRYPT))
{
CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length);
} else if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_CCM | CAU_DECRYPT)) {
} else if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_CCM | CAU_DECRYPT))
{
CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length);
} else {
}
@ -831,7 +870,8 @@ static ErrStatus cau_fill_data(uint8_t *input, uint32_t in_length)
counter++;
} while((AESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) {
if(RESET != busystatus)
{
return ERROR;
}
@ -854,17 +894,21 @@ static ErrStatus cau_aes_calculate(uint8_t *input, uint32_t in_length, uint8_t *
uint32_t busystatus = 0U;
/* the clock is not enabled or there is no embedded CAU peripheral */
if(DISABLE == cau_enable_state_get()) {
if(DISABLE == cau_enable_state_get())
{
return ERROR;
}
for(i = 0U; i < in_length; i += BLOCK_DATA_SIZE) {
for(i = 0U; i < in_length; i += BLOCK_DATA_SIZE)
{
/* wait until the IEM flag is set */
while(RESET == cau_flag_get(CAU_FLAG_INFIFO_EMPTY)) {
while(RESET == cau_flag_get(CAU_FLAG_INFIFO_EMPTY))
{
}
/* check if the last input data block */
if(i + BLOCK_DATA_SIZE > in_length) {
if(i + BLOCK_DATA_SIZE > in_length)
{
/* the last block data number is less than 128bit */
uint32_t block_data_temp[4] = {0};
@ -873,9 +917,11 @@ static ErrStatus cau_aes_calculate(uint8_t *input, uint32_t in_length, uint8_t *
inputaddr = (uint32_t)block_data_temp;
/* if GCM encryption or CCM decryption, then configurate NBPILB bits in CTL register */
if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_GCM | CAU_ENCRYPT)) {
if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_GCM | CAU_ENCRYPT))
{
CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length);
} else if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_CCM | CAU_DECRYPT)) {
} else if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_CCM | CAU_DECRYPT))
{
CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length);
} else {
}
@ -898,7 +944,8 @@ static ErrStatus cau_aes_calculate(uint8_t *input, uint32_t in_length, uint8_t *
counter++;
} while((AESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) {
if(RESET != busystatus)
{
return ERROR;
} else {
/* read the output block from the output FIFO */

9
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cau_des.c
View File

@ -150,11 +150,13 @@ static ErrStatus cau_des_calculate(uint8_t *input, uint32_t in_length, uint8_t *
uint32_t busystatus = 0U;
/* the clock is not enabled or there is no embedded CAU peripheral */
if(DISABLE == cau_enable_state_get()) {
if(DISABLE == cau_enable_state_get())
{
return ERROR;
}
for(i = 0U; i < in_length; i += 8U) {
for(i = 0U; i < in_length; i += 8U)
{
/* write data to the IN FIFO */
cau_data_write(*(uint32_t *)(inputaddr));
inputaddr += 4U;
@ -168,7 +170,8 @@ static ErrStatus cau_des_calculate(uint8_t *input, uint32_t in_length, uint8_t *
counter++;
} while((DESBUSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) {
if(RESET != busystatus)
{
return ERROR;
} else {
/* read the output block from the output FIFO */

9
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cau_tdes.c
View File

@ -165,11 +165,13 @@ static ErrStatus cau_tdes_calculate(uint8_t *input, uint32_t in_length, uint8_t
uint32_t busystatus = 0U;
/* the clock is not enabled or there is no embedded CAU peripheral */
if(DISABLE == cau_enable_state_get()) {
if(DISABLE == cau_enable_state_get())
{
return ERROR;
}
for(i = 0U; i < in_length; i += 8U) {
for(i = 0U; i < in_length; i += 8U)
{
/* write data to the IN FIFO */
cau_data_write(*(uint32_t *)(inputaddr));
inputaddr += 4U;
@ -183,7 +185,8 @@ static ErrStatus cau_tdes_calculate(uint8_t *input, uint32_t in_length, uint8_t
counter++;
} while((TDESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) {
if(RESET != busystatus)
{
return ERROR;
} else {
/* read the output block from the output FIFO */

162
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cmp.c
View File

@ -44,12 +44,14 @@ OF SUCH DAMAGE.
*/
void cmp_deinit(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP0_CS &= ((uint32_t)0x00000000U);
CMP_IFC &= ((uint32_t)0xFFFEFFFFU);
CMP_STAT &= ((uint32_t)0xFFFEFFFEU);
CMP_SR &= ((uint32_t)0x00000000U);
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP1_CS &= ((uint32_t)0x00000000U);
CMP_IFC &= ((uint32_t)0xFFFDFFFFU);
CMP_STAT &= ((uint32_t)0xFFFDFFFDU);
@ -88,13 +90,15 @@ void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t invert
{
uint32_t temp = 0U;
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
/* initialize comparator 0 mode */
temp = CMP0_CS;
temp &= ~(uint32_t)(CMP_CS_CMPXM | CMP_CS_CMPXMISEL | CMP_CS_CMPXHST);
temp |= (uint32_t)(operating_mode | inverting_input | output_hysteresis);
CMP0_CS = temp;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
/* initialize comparator 1 mode */
temp = CMP1_CS;
temp &= ~(uint32_t)(CMP_CS_CMPXM | CMP_CS_CMPXMISEL | CMP_CS_CMPXHST);
@ -119,12 +123,14 @@ void cmp_noninverting_input_select(cmp_enum cmp_periph, uint32_t noninverting_in
{
uint32_t temp = 0U;
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
temp = CMP0_CS;
temp &= ~(uint32_t)CMP_CS_CMPXPSEL;
temp |= (uint32_t)noninverting_input;
CMP0_CS = temp;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
temp = CMP1_CS;
temp &= ~(uint32_t)CMP_CS_CMPXPSEL;
temp |= (uint32_t)noninverting_input;
@ -148,21 +154,25 @@ void cmp_output_init(cmp_enum cmp_periph, uint32_t output_polarity)
{
uint32_t temp = 0U;
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
/* initialize comparator 0 output */
temp = CMP0_CS;
/* output polarity */
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity)
{
temp |= (uint32_t)CMP_CS_CMPXPL;
}else{
temp &= ~(uint32_t)CMP_CS_CMPXPL;
}
CMP0_CS = temp;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
/* initialize comparator 1 output */
temp = CMP1_CS;
/* output polarity */
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity)
{
temp |= (uint32_t)CMP_CS_CMPXPL;
}else{
temp &= ~(uint32_t)CMP_CS_CMPXPL;
@ -194,9 +204,11 @@ void cmp_output_init(cmp_enum cmp_periph, uint32_t output_polarity)
*/
void cmp_output_mux_config(cmp_enum cmp_periph, uint32_t cmp_output_sel)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP_SR &= ~(uint32_t)cmp_output_sel;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP_SR |= cmp_output_sel;
}else{
}
@ -222,12 +234,14 @@ void cmp_blanking_init(cmp_enum cmp_periph, uint32_t blanking_source_selection)
{
uint32_t temp = 0U;
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
temp = CMP0_CS;
temp &= ~(uint32_t)CMP_CS_CMPXBLK;
temp |= (uint32_t)blanking_source_selection;
CMP0_CS = temp;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
temp = CMP1_CS;
temp &= ~(uint32_t)CMP_CS_CMPXBLK;
temp |= (uint32_t)blanking_source_selection;
@ -246,9 +260,11 @@ void cmp_blanking_init(cmp_enum cmp_periph, uint32_t blanking_source_selection)
*/
void cmp_enable(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP0_CS |= (uint32_t)CMP_CS_CMPXEN;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP1_CS |= (uint32_t)CMP_CS_CMPXEN;
}else{
}
@ -264,9 +280,11 @@ void cmp_enable(cmp_enum cmp_periph)
*/
void cmp_disable(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP0_CS &= ~(uint32_t)CMP_CS_CMPXEN;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP1_CS &= ~(uint32_t)CMP_CS_CMPXEN;
}else{
}
@ -304,10 +322,12 @@ void cmp_window_disable(void)
*/
void cmp_lock_enable(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
/* lock CMP0 */
CMP0_CS |= (uint32_t)CMP_CS_CMPXLK;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
/* lock CMP1 */
CMP1_CS |= (uint32_t)CMP_CS_CMPXLK;
}else{
@ -324,9 +344,11 @@ void cmp_lock_enable(cmp_enum cmp_periph)
*/
void cmp_voltage_scaler_enable(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP0_CS |= (uint32_t)CMP_CS_CMPXSEN;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP1_CS |= (uint32_t)CMP_CS_CMPXSEN;
}else{
}
@ -342,9 +364,11 @@ void cmp_voltage_scaler_enable(cmp_enum cmp_periph)
*/
void cmp_voltage_scaler_disable(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP0_CS &= ~(uint32_t)CMP_CS_CMPXSEN;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP1_CS &= ~(uint32_t)CMP_CS_CMPXSEN;
}else{
}
@ -360,9 +384,11 @@ void cmp_voltage_scaler_disable(cmp_enum cmp_periph)
*/
void cmp_scaler_bridge_enable(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP0_CS |= (uint32_t)CMP_CS_CMPXBEN;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP1_CS |= (uint32_t)CMP_CS_CMPXBEN;
}else{
}
@ -378,9 +404,11 @@ void cmp_scaler_bridge_enable(cmp_enum cmp_periph)
*/
void cmp_scaler_bridge_disable(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP0_CS &= ~(uint32_t)CMP_CS_CMPXBEN;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP1_CS &= ~(uint32_t)CMP_CS_CMPXBEN;
}else{
}
@ -396,16 +424,19 @@ void cmp_scaler_bridge_disable(cmp_enum cmp_periph)
*/
uint32_t cmp_output_level_get(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
/* get output level of CMP0 */
if((uint32_t)RESET != (CMP_STAT & CMP_STAT_CMP0O)) {
if((uint32_t)RESET != (CMP_STAT & CMP_STAT_CMP0O))
{
return CMP_OUTPUTLEVEL_HIGH;
}else{
return CMP_OUTPUTLEVEL_LOW;
}
}else{
/* get output level of CMP1 */
if((uint32_t)RESET != (CMP_STAT & CMP_STAT_CMP1O)) {
if((uint32_t)RESET != (CMP_STAT & CMP_STAT_CMP1O))
{
return CMP_OUTPUTLEVEL_HIGH;
}else{
return CMP_OUTPUTLEVEL_LOW;
@ -427,15 +458,21 @@ FlagStatus cmp_flag_get(cmp_enum cmp_periph, uint32_t flag)
{
FlagStatus reval = RESET;
if(CMP0 == cmp_periph){
if(CMP_FLAG_COMPARE == flag){
if(0U != (CMP_STAT & CMP_STAT_CMP0IF)){
if(CMP0 == cmp_periph)
{
if(CMP_FLAG_COMPARE == flag)
{
if(0U != (CMP_STAT & CMP_STAT_CMP0IF))
{
reval = SET;
}
}
}else if(CMP1 == cmp_periph){
if(CMP_FLAG_COMPARE == flag){
if(0U != (CMP_STAT & CMP_STAT_CMP1IF)){
}else if(CMP1 == cmp_periph)
{
if(CMP_FLAG_COMPARE == flag)
{
if(0U != (CMP_STAT & CMP_STAT_CMP1IF))
{
reval = SET;
}
}
@ -455,12 +492,16 @@ FlagStatus cmp_flag_get(cmp_enum cmp_periph, uint32_t flag)
*/
void cmp_flag_clear(cmp_enum cmp_periph, uint32_t flag)
{
if(CMP0 == cmp_periph){
if(CMP_FLAG_COMPARE == flag){
if(CMP0 == cmp_periph)
{
if(CMP_FLAG_COMPARE == flag)
{
CMP_IFC |= (uint32_t)CMP_IFC_CMP0IC;
}
}else if(CMP1 == cmp_periph){
if(CMP_FLAG_COMPARE == flag){
}else if(CMP1 == cmp_periph)
{
if(CMP_FLAG_COMPARE == flag)
{
CMP_IFC |= (uint32_t)CMP_IFC_CMP1IC;
}
}else{
@ -480,10 +521,12 @@ void cmp_flag_clear(cmp_enum cmp_periph, uint32_t flag)
*/
void cmp_interrupt_enable(cmp_enum cmp_periph, uint32_t interrupt)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
/* enable CMP0 interrupt */
CMP0_CS |= (uint32_t)interrupt;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
/* enable CMP1 interrupt */
CMP1_CS |= (uint32_t)interrupt;
}else{
@ -503,10 +546,12 @@ void cmp_interrupt_enable(cmp_enum cmp_periph, uint32_t interrupt)
*/
void cmp_interrupt_disable(cmp_enum cmp_periph, uint32_t interrupt)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
/* disable CMP0 interrupt */
CMP0_CS &= ~(uint32_t)interrupt;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
/* disable CMP1 interrupt */
CMP1_CS &= ~(uint32_t)interrupt;
}else{
@ -527,15 +572,19 @@ FlagStatus cmp_interrupt_flag_get(cmp_enum cmp_periph, uint32_t flag)
{
uint32_t intstatus = 0U, flagstatus = 0U;
if(CMP0 == cmp_periph){
if(CMP_INT_FLAG_COMPARE == flag){
if(CMP0 == cmp_periph)
{
if(CMP_INT_FLAG_COMPARE == flag)
{
/* get the corresponding flag bit status */
flagstatus = CMP_STAT & CMP_STAT_CMP0IF;
/* get the interrupt enable bit status */
intstatus = CMP0_CS & CMP_CS_CMPXINTEN;
}
}else if(CMP1 == cmp_periph){
if(CMP_INT_FLAG_COMPARE == flag){
}else if(CMP1 == cmp_periph)
{
if(CMP_INT_FLAG_COMPARE == flag)
{
/* get the corresponding flag bit status */
flagstatus = CMP_STAT & CMP_STAT_CMP1IF;
/* get the interrupt enable bit status */
@ -544,7 +593,8 @@ FlagStatus cmp_interrupt_flag_get(cmp_enum cmp_periph, uint32_t flag)
}else{
}
if((0U != flagstatus) && (0U != intstatus)){
if((0U != flagstatus) && (0U != intstatus))
{
return SET;
}else{
return RESET;
@ -564,12 +614,16 @@ FlagStatus cmp_interrupt_flag_get(cmp_enum cmp_periph, uint32_t flag)
void cmp_interrupt_flag_clear(cmp_enum cmp_periph, uint32_t flag)
{
/* clear CMP interrupt flag */
if(CMP0 == cmp_periph){
if(CMP_INT_FLAG_COMPARE == flag){
if(CMP0 == cmp_periph)
{
if(CMP_INT_FLAG_COMPARE == flag)
{
CMP_IFC |= (uint32_t)CMP_IFC_CMP0IC;
}
}else if(CMP1 == cmp_periph){
if(CMP_INT_FLAG_COMPARE == flag){
}else if(CMP1 == cmp_periph)
{
if(CMP_INT_FLAG_COMPARE == flag)
{
CMP_IFC |= (uint32_t)CMP_IFC_CMP1IC;
}
}else{

15
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cpdm.c
View File

@ -154,7 +154,8 @@ FlagStatus cpdm_delayline_length_valid_flag_get(uint32_t cpdm_periph)
uint32_t reg = 0U;
reg = CPDM_CFG(cpdm_periph);
if(reg & CPDM_DLLENF_MASK) {
if(reg & CPDM_DLLENF_MASK)
{
return SET;
} else {
return RESET;
@ -214,21 +215,25 @@ void cpdm_clock_output(uint32_t cpdm_periph, cpdm_output_phase_enum output_clock
reg |= CPDM_MAX_PHASE;
CPDM_CFG(cpdm_periph) = (uint32_t)reg;
for(delay_count = 0U; delay_count <= CPDM_MAX_DELAY_STEP_COUNT; delay_count++) {
for(delay_count = 0U; delay_count <= CPDM_MAX_DELAY_STEP_COUNT; delay_count++)
{
reg = CPDM_CFG(cpdm_periph);
reg &= CPDM_DLSTCNT_MASK;
/* configure delay line step count */
reg |= delay_count << CPDM_DLSTCNT_OFFSET;
CPDM_CFG(cpdm_periph) = (uint32_t)reg;
while(SET == (CPDM_CFG(cpdm_periph) & CPDM_CFG_DLLENF)) {
while(SET == (CPDM_CFG(cpdm_periph) & CPDM_CFG_DLLENF))
{
}
while(RESET == (CPDM_CFG(cpdm_periph) & CPDM_CFG_DLLENF)) {
while(RESET == (CPDM_CFG(cpdm_periph) & CPDM_CFG_DLLENF))
{
}
reg_cfg = CPDM_CFG(cpdm_periph);
if((((reg_cfg >> CPDM_DLLEN_OFFSET) & CPDM_DLLEN_10_0_MASK) > 0U) &&
((RESET == (reg_cfg & CPDM_DLLEN_11)) || (RESET == (reg_cfg & CPDM_DLLEN_10)))) {
((RESET == (reg_cfg & CPDM_DLLEN_11)) || (RESET == (reg_cfg & CPDM_DLLEN_10))))
{
break;
}
}

24
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_crc.c
View File

@ -195,11 +195,14 @@ void crc_polynomial_set(uint32_t poly)
*/
uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format)
{
if(INPUT_FORMAT_WORD == data_format) {
if(INPUT_FORMAT_WORD == data_format)
{
REG32(CRC) = sdata;
} else if(INPUT_FORMAT_HALFWORD == data_format) {
} else if(INPUT_FORMAT_HALFWORD == data_format)
{
REG16(CRC) = (uint16_t)sdata;
} else if(INPUT_FORMAT_BYTE == data_format) {
} else if(INPUT_FORMAT_BYTE == data_format)
{
REG8(CRC) = (uint8_t)sdata;
} else {
}
@ -226,19 +229,24 @@ uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_forma
uint32_t *data32;
uint32_t index;
if(INPUT_FORMAT_WORD == data_format) {
if(INPUT_FORMAT_WORD == data_format)
{
data32 = (uint32_t *)array;
for(index = 0U; index < size; index++) {
for(index = 0U; index < size; index++)
{
REG32(CRC) = data32[index];
}
} else if(INPUT_FORMAT_HALFWORD == data_format) {
} else if(INPUT_FORMAT_HALFWORD == data_format)
{
data16 = (uint16_t *)array;
for(index = 0U; index < size; index++) {
for(index = 0U; index < size; index++)
{
REG16(CRC) = data16[index];
}
} else {
data8 = (uint8_t *)array;
for(index = 0U; index < size; index++) {
for(index = 0U; index < size; index++)
{
REG8(CRC) = data8[index];
}
}

18
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_ctc.c
View File

@ -218,7 +218,8 @@ uint16_t ctc_counter_capture_value_read(void)
*/
FlagStatus ctc_counter_direction_read(void)
{
if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){
if(RESET != (CTC_STAT & CTC_STAT_REFDIR))
{
return SET;
}else{
return RESET;
@ -267,7 +268,8 @@ uint8_t ctc_irc48m_trim_value_read(void)
*/
FlagStatus ctc_flag_get(uint32_t flag)
{
if(RESET != (CTC_STAT & flag)){
if(RESET != (CTC_STAT & flag))
{
return SET;
}else{
return RESET;
@ -290,7 +292,8 @@ FlagStatus ctc_flag_get(uint32_t flag)
*/
void ctc_flag_clear(uint32_t flag)
{
if(RESET != (flag & CTC_FLAG_MASK)){
if(RESET != (flag & CTC_FLAG_MASK))
{
CTC_INTC |= CTC_INTC_ERRIC;
}else{
CTC_INTC |= flag;
@ -348,7 +351,8 @@ FlagStatus ctc_interrupt_flag_get(uint32_t int_flag)
uint32_t interrupt_flag = 0U, intenable = 0U;
/* check whether the interrupt is enabled */
if(RESET != (int_flag & CTC_FLAG_MASK)){
if(RESET != (int_flag & CTC_FLAG_MASK))
{
intenable = CTC_CTL0 & CTC_CTL0_ERRIE;
}else{
intenable = CTC_CTL0 & int_flag;
@ -357,7 +361,8 @@ FlagStatus ctc_interrupt_flag_get(uint32_t int_flag)
/* get interrupt flag status */
interrupt_flag = CTC_STAT & int_flag;
if(interrupt_flag && intenable){
if(interrupt_flag && intenable)
{
return SET;
}else{
return RESET;
@ -380,7 +385,8 @@ FlagStatus ctc_interrupt_flag_get(uint32_t int_flag)
*/
void ctc_interrupt_flag_clear(uint32_t int_flag)
{
if(RESET != (int_flag & CTC_FLAG_MASK)){
if(RESET != (int_flag & CTC_FLAG_MASK))
{
CTC_INTC |= CTC_INTC_ERRIC;
}else{
CTC_INTC |= int_flag;

141
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_dac.c
View File

@ -51,7 +51,8 @@ OF SUCH DAMAGE.
*/
void dac_deinit(uint32_t dac_periph)
{
switch(dac_periph){
switch(dac_periph)
{
case DAC0:
/* reset DAC0 */
rcu_periph_reset_enable(RCU_DACRST);
@ -71,9 +72,11 @@ void dac_deinit(uint32_t dac_periph)
*/
void dac_enable(uint32_t dac_periph, uint8_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DEN0;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DEN1;
}else{
/* illegal parameters */
@ -89,9 +92,11 @@ void dac_enable(uint32_t dac_periph, uint8_t dac_out)
*/
void dac_disable(uint32_t dac_periph, uint8_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DEN0);
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DEN1);
}else{
/* illegal parameters */
@ -107,9 +112,11 @@ void dac_disable(uint32_t dac_periph, uint8_t dac_out)
*/
void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DDMAEN0;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DDMAEN1;
}else{
/* illegal parameters */
@ -125,9 +132,11 @@ void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out)
*/
void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DDMAEN0);
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DDMAEN1);
}else{
/* illegal parameters */
@ -153,11 +162,13 @@ void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out)
*/
void dac_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t mode)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* configure DAC0 mode */
DAC_MDCR(dac_periph) &= ~(uint32_t)DAC_MDCR_MODE0;
DAC_MDCR(dac_periph) |= mode;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* configure DAC1 mode */
DAC_MDCR(dac_periph) &= ~(uint32_t)DAC_MDCR_MODE1;
DAC_MDCR(dac_periph) |= (mode << OUT1_REG_OFFSET);
@ -176,10 +187,12 @@ void dac_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t mode)
uint32_t dac_trimming_value_get(uint32_t dac_periph, uint32_t dac_out)
{
uint32_t tmp = 0U;
if(DAC_OUT0 == dac_out) {
if(DAC_OUT0 == dac_out)
{
/* get the DAC_OUT_0 trimming value */
tmp = DAC_CALR(dac_periph) & DAC_CALR_OTV0;
} else if(DAC_OUT1 == dac_out) {
} else if(DAC_OUT1 == dac_out)
{
/* get the DAC_OUT_1 trimming value */
tmp = (DAC_CALR(dac_periph) & DAC_CALR_OTV1) >> OUT1_REG_OFFSET;
} else {
@ -202,12 +215,14 @@ void dac_trimming_value_set(uint32_t dac_periph, uint32_t dac_out, uint32_t trim
/* get the trimming value */
tmp = DAC_CALR(dac_periph);
if(DAC_OUT0 == dac_out) {
if(DAC_OUT0 == dac_out)
{
/* set the DACx_OUT0 trimming value */
tmp &= ~(uint32_t)DAC_CALR_OTV0;
tmp |= (trim_value & DAC_CALR_OTV0);
DAC_CALR(dac_periph) = tmp;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* set the DACx_OUT1 trimming value */
tmp &= ~(uint32_t)DAC_CALR_OTV1;
tmp |= ((trim_value << OUT1_REG_OFFSET) & DAC_CALR_OTV1);
@ -225,10 +240,12 @@ void dac_trimming_value_set(uint32_t dac_periph, uint32_t dac_out, uint32_t trim
*/
void dac_trimming_enable(uint32_t dac_periph, uint32_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* enable the DACx_OUT0 trimming */
DAC_CTL0(dac_periph) |= DAC_CTL0_CALEN0;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* enable the DACx_OUT1 trimming */
DAC_CTL0(dac_periph) |= DAC_CTL0_CALEN1;
}else{
@ -247,10 +264,12 @@ uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out)
{
uint16_t data = 0U;
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* store the DACx_OUT0 output value */
data = (uint16_t)DAC_OUT0_DO(dac_periph);
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* store the DACx_OUT1 output value */
data = (uint16_t)DAC_OUT1_DO(dac_periph);
}else{
@ -276,8 +295,10 @@ uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out)
void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint16_t data)
{
/* DAC_OUT0 data alignment */
if(DAC_OUT0 == dac_out){
switch(dac_align){
if(DAC_OUT0 == dac_out)
{
switch(dac_align)
{
/* 12-bit right-aligned data */
case DAC_ALIGN_12B_R:
DAC_OUT0_R12DH(dac_periph) = data;
@ -293,9 +314,11 @@ void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint
default:
break;
}
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* DAC_OUT1 data alignment */
switch(dac_align){
switch(dac_align)
{
/* 12-bit right-aligned data */
case DAC_ALIGN_12B_R:
DAC_OUT1_R12DH(dac_periph) = data;
@ -325,9 +348,11 @@ void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint
*/
void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DTEN0;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DTEN1;
}else{
/* illegal parameters */
@ -343,9 +368,11 @@ void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
*/
void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTEN0);
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTEN1);
}else{
/* illegal parameters */
@ -365,11 +392,13 @@ void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out)
*/
void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t triggersource)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 trigger source */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTSEL0);
DAC_CTL0(dac_periph) |= triggersource;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 trigger source */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTSEL1);
DAC_CTL0(dac_periph) |= (triggersource << OUT1_REG_OFFSET);
@ -386,9 +415,11 @@ void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t tr
*/
void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
DAC_SWT(dac_periph) |= (uint32_t)DAC_SWT_SWTR0;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
DAC_SWT(dac_periph) |= (uint32_t)DAC_SWT_SWTR1;
}else{
/* illegal parameters */
@ -409,11 +440,13 @@ void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
*/
void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mode)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 wave mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWM0);
DAC_CTL0(dac_periph) |= wave_mode;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 wave mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWM1);
DAC_CTL0(dac_periph) |= (wave_mode << OUT1_REG_OFFSET);
@ -445,11 +478,13 @@ void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mo
*/
void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask_bits)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 LFSR noise mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW0);
DAC_CTL0(dac_periph) |= unmask_bits;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 LFSR noise mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW1);
DAC_CTL0(dac_periph) |= (unmask_bits << OUT1_REG_OFFSET);
@ -481,11 +516,13 @@ void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask
*/
void dac_triangle_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t amplitude)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 triangle noise mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW0);
DAC_CTL0(dac_periph) |= amplitude;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 triangle noise mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW1);
DAC_CTL0(dac_periph) |= (amplitude << OUT1_REG_OFFSET);
@ -553,7 +590,8 @@ void dac_concurrent_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t d
{
uint32_t data = 0U;
switch(dac_align){
switch(dac_align)
{
/* 12-bit right-aligned data */
case DAC_ALIGN_12B_R:
data = (uint32_t)(((uint32_t)data1 << DH_12BIT_OFFSET) | data0);
@ -588,7 +626,8 @@ void dac_sample_keep_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t
{
uint32_t tmp = 0U;
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 Sample & Keep mode */
DAC_SKSTR0(dac_periph) |= (sample_time & DAC_SKSTR0_TSAMP0);
@ -597,7 +636,8 @@ void dac_sample_keep_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t
tmp = (DAC_SKRTR(dac_periph) & ~(uint32_t)DAC_SKRTR_TREF0);
DAC_SKRTR(dac_periph) = tmp | (refresh_time & DAC_SKRTR_TREF0);
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 Sample & Keep mode */
DAC_SKSTR1(dac_periph) |= (sample_time & DAC_SKSTR1_TSAMP1);
@ -627,9 +667,11 @@ void dac_sample_keep_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t
*/
FlagStatus dac_flag_get(uint32_t dac_periph, uint32_t flag)
{
if(flag & DAC_STAT_FLAG_MASK0){
if(flag & DAC_STAT_FLAG_MASK0)
{
/* check DAC_STAT0 flag */
if(RESET != (DAC_STAT0(dac_periph) & flag)){
if(RESET != (DAC_STAT0(dac_periph) & flag))
{
return SET;
}else{
return RESET;
@ -652,7 +694,8 @@ FlagStatus dac_flag_get(uint32_t dac_periph, uint32_t flag)
*/
void dac_flag_clear(uint32_t dac_periph, uint32_t flag)
{
if(flag & DAC_STAT_FLAG_MASK0){
if(flag & DAC_STAT_FLAG_MASK0)
{
/* check DAC_STAT0 flag */
DAC_STAT0(dac_periph) = (uint32_t)(flag & DAC_STAT_FLAG_MASK0);
}else{
@ -672,7 +715,8 @@ void dac_flag_clear(uint32_t dac_periph, uint32_t flag)
*/
void dac_interrupt_enable(uint32_t dac_periph, uint32_t interrupt)
{
if(interrupt & DAC_INT_EN_MASK0){
if(interrupt & DAC_INT_EN_MASK0)
{
/* enable underrun interrupt */
DAC_CTL0(dac_periph) |= (uint32_t)(interrupt & DAC_INT_EN_MASK0);
}else{
@ -692,7 +736,8 @@ void dac_interrupt_enable(uint32_t dac_periph, uint32_t interrupt)
*/
void dac_interrupt_disable(uint32_t dac_periph, uint32_t interrupt)
{
if(interrupt & DAC_INT_EN_MASK0){
if(interrupt & DAC_INT_EN_MASK0)
{
/* disable underrun interrupt */
DAC_CTL0(dac_periph) &= (uint32_t)(~(interrupt & DAC_INT_EN_MASK0));
}else{
@ -714,7 +759,8 @@ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph, uint32_t int_flag)
{
uint32_t reg1 = 0U, reg2 = 0U;
if(int_flag & DAC_INT_FLAG_MASK0){
if(int_flag & DAC_INT_FLAG_MASK0)
{
/* check underrun interrupt int_flag */
reg1 = DAC_STAT0(dac_periph) & int_flag;
reg2 = DAC_CTL0(dac_periph) & int_flag;
@ -723,7 +769,8 @@ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph, uint32_t int_flag)
}
/*get DAC interrupt flag status */
if((RESET != reg1) && (RESET != reg2)){
if((RESET != reg1) && (RESET != reg2))
{
return SET;
}else{
return RESET;

12
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_dci.c
View File

@ -279,7 +279,8 @@ void dci_ccir_disable(void)
*/
void dci_ccir_mode_select(uint32_t ccir_mode)
{
if(CCIR_INTERLACE_MODE == ccir_mode) {
if(CCIR_INTERLACE_MODE == ccir_mode)
{
DCI_CTL |= DCI_CTL_CCMOD;
} else {
DCI_CTL &= ~DCI_CTL_CCMOD;
@ -346,7 +347,8 @@ FlagStatus dci_flag_get(uint32_t flag)
{
uint32_t stat = 0U;
if(flag >> 31U) {
if(flag >> 31U)
{
/* get flag status from DCI_STAT1 register */
stat = DCI_STAT1;
} else {
@ -354,7 +356,8 @@ FlagStatus dci_flag_get(uint32_t flag)
stat = DCI_STAT0;
}
if(flag & stat) {
if(flag & stat)
{
return SET;
} else {
return RESET;
@ -421,7 +424,8 @@ void dci_interrupt_disable(uint32_t interrupt)
*/
FlagStatus dci_interrupt_flag_get(uint32_t int_flag)
{
if(RESET == (DCI_INTF & int_flag)) {
if(RESET == (DCI_INTF & int_flag))
{
return RESET;
} else {
return SET;

105
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_dma.c
View File

@ -35,7 +35,8 @@ OF SUCH DAMAGE.
#include "gd32h7xx_dma.h"
#include <stdlib.h>
#define DMA_WRONG_HANDLE while(1){}
#define DMA_WRONG_HANDLE while(1)
{}
/* DMA register bit offset */
#define CHXFCTL_FCNT_OFFSET ((uint32_t)0x00000003U) /*!< bit offset of FCNT in DMA_CHxFCTL */
@ -64,7 +65,8 @@ void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
DMA_CHM0ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
DMA_CHM1ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
DMA_CHFCTL(dma_periph, channelx) = DMA_CHFCTL_RESET_VALUE;
if(channelx < DMA_CH4) {
if(channelx < DMA_CH4)
{
DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
} else {
channelx -= (dma_channel_enum)4;
@ -160,9 +162,11 @@ void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, d
DMA_CHCTL(dma_periph, channelx) = ctl;
/* configure peripheral increasing mode */
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) {
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
} else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) {
} else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc)
{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
} else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
@ -170,19 +174,22 @@ void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, d
}
/* configure memory increasing mode */
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) {
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
} else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
}
/* configure DMA circular mode */
if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) {
if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
} else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
}
if(DMA0 == dma_periph) {
if(DMA0 == dma_periph)
{
DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_MUXID;
DMAMUX_RM_CHXCFG(channelx) |= init_struct->request;
} else {
@ -239,9 +246,11 @@ void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dm
DMA_CHCTL(dma_periph, channelx) = ctl;
/* configure peripheral increasing mode */
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) {
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
} else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) {
} else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc)
{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
} else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
@ -249,20 +258,23 @@ void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dm
}
/* configure memory increasing mode */
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) {
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
} else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
}
/* configure DMA circular mode */
if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) {
if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
} else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
}
if(DMA0 == dma_periph) {
if(DMA0 == dma_periph)
{
DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_MUXID;
DMAMUX_RM_CHXCFG(channelx) |= init_struct->request;
} else {
@ -301,7 +313,8 @@ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, u
*/
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address)
{
if(memory_flag) {
if(memory_flag)
{
DMA_CHM1ADDR(dma_periph, channelx) = address;
} else {
DMA_CHM0ADDR(dma_periph, channelx) = address;
@ -479,7 +492,8 @@ void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uin
*/
void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm)
{
if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm) {
if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
} else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
@ -502,9 +516,11 @@ void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum
*/
void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm)
{
if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm) {
if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
} else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm) {
} else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm)
{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
} else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
@ -612,7 +628,8 @@ void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channel
/* configure memory1 base address */
DMA_CHM1ADDR(dma_periph, channelx) = memory1_addr;
if(DMA_MEMORY_0 == memory_select) {
if(DMA_MEMORY_0 == memory_select)
{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MBS;
} else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MBS;
@ -630,7 +647,8 @@ void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channel
*/
uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx)
{
if((DMA_CHCTL(dma_periph, channelx)) & DMA_CHXCTL_MBS) {
if((DMA_CHCTL(dma_periph, channelx)) & DMA_CHXCTL_MBS)
{
return DMA_MEMORY_1;
} else {
return DMA_MEMORY_0;
@ -705,15 +723,18 @@ uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx)
*/
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
if(channelx < DMA_CH4) {
if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx)) {
if(channelx < DMA_CH4)
{
if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx))
{
return SET;
} else {
return RESET;
}
} else {
channelx -= (dma_channel_enum)4;
if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channelx)) {
if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channelx))
{
return SET;
} else {
return RESET;
@ -739,7 +760,8 @@ FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t
*/
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
if(channelx < DMA_CH4) {
if(channelx < DMA_CH4)
{
DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
} else {
channelx -= (dma_channel_enum)4;
@ -765,7 +787,8 @@ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t fla
*/
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt)
{
if(DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & interrupt)) {
if(DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & interrupt))
{
DMA_CHCTL(dma_periph, channelx) |= interrupt;
} else {
DMA_CHFCTL(dma_periph, channelx) |= DMA_CHXFCTL_FEEIE;
@ -791,7 +814,8 @@ void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32
*/
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt)
{
if(DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & interrupt)) {
if(DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & interrupt))
{
DMA_CHCTL(dma_periph, channelx) &= ~interrupt;
} else {
DMA_CHFCTL(dma_periph, channelx) &= ~DMA_CHXFCTL_FEEIE;
@ -821,8 +845,10 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
dma_channel_enum channel_flag_offset = channelx;
/* flags for channel0-3 */
if(channelx < DMA_CH4) {
switch(int_flag) {
if(channelx < DMA_CH4)
{
switch(int_flag)
{
case DMA_INTF_FEEIF:
interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(int_flag, channelx);
interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE;
@ -849,7 +875,8 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
/* flags for channel4-7 */
} else {
channel_flag_offset -= (dma_channel_enum)4U;
switch(int_flag) {
switch(int_flag)
{
case DMA_INTF_FEEIF:
interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(int_flag, channel_flag_offset);
interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE;
@ -875,7 +902,8 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
}
}
if(interrupt_flag && interrupt_enable) {
if(interrupt_flag && interrupt_enable)
{
return SET;
} else {
return RESET;
@ -900,7 +928,8 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
*/
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t int_flag)
{
if(channelx < DMA_CH4) {
if(channelx < DMA_CH4)
{
DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(int_flag, channelx);
} else {
channelx -= (dma_channel_enum)4U;
@ -916,7 +945,8 @@ void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, ui
*/
void dmamux_sync_struct_para_init(dmamux_sync_parameter_struct *init_struct)
{
if(NULL == init_struct) {
if(NULL == init_struct)
{
DMA_WRONG_HANDLE
}
@ -949,7 +979,8 @@ void dmamux_synchronization_init(dmamux_multiplexer_channel_enum channelx, dmamu
{
uint32_t cfg;
if(NULL == init_struct) {
if(NULL == init_struct)
{
DMA_WRONG_HANDLE
}
@ -1022,7 +1053,8 @@ void dmamux_event_generation_disable(dmamux_multiplexer_channel_enum channelx)
*/
void dmamux_gen_struct_para_init(dmamux_gen_parameter_struct *init_struct)
{
if(NULL == init_struct) {
if(NULL == init_struct)
{
DMA_WRONG_HANDLE
}
@ -1055,7 +1087,8 @@ void dmamux_request_generator_init(dmamux_generator_channel_enum channelx, dmamu
{
uint32_t cfg;
if(NULL == init_struct) {
if(NULL == init_struct)
{
DMA_WRONG_HANDLE
}
@ -1506,7 +1539,8 @@ FlagStatus dmamux_flag_get(dmamux_flag_enum flag)
{
FlagStatus reval;
if(RESET != (DMAMUX_REG_VAL(flag) & BIT(DMAMUX_BIT_POS(flag)))) {
if(RESET != (DMAMUX_REG_VAL(flag) & BIT(DMAMUX_BIT_POS(flag))))
{
reval = SET;
} else {
reval = RESET;
@ -1664,7 +1698,8 @@ FlagStatus dmamux_interrupt_flag_get(dmamux_interrupt_flag_enum int_flag)
/* get the corresponding flag bit status */
flagstatus = (DMAMUX_REG_VAL(int_flag) & BIT(DMAMUX_BIT_POS(int_flag)));
if(flagstatus && intenable) {
if(flagstatus && intenable)
{
reval = SET;
} else {
reval = RESET;

6
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_edout.c
View File

@ -74,10 +74,12 @@ void edout_init(uint32_t pol, uint32_t max_loc, uint32_t cur_loc)
/* reset the maximum location value */
EDOUT_LOC &= ~EDOUT_LOC_LOCMAX;
/* check the maximum location value */
if(LOC_LOCMAX_MIN > max_loc) {
if(LOC_LOCMAX_MIN > max_loc)
{
max_loc = LOC_LOCMAX_MIN;
}
while(0U != ((max_loc + 1U) % LOC_LOCMAX_STEP)) {
while(0U != ((max_loc + 1U) % LOC_LOCMAX_STEP))
{
max_loc++;
}
/* set the maximum location value */

90
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_efuse.c
View File

@ -73,7 +73,8 @@ ErrStatus efuse_read(uint32_t ef_addr, uint32_t size, uint32_t buf[])
uint32_t reg_addr = 0U;
uint32_t i = 0U;
uint32_t number = 0U;
switch(ef_addr) {
switch(ef_addr)
{
case USER_CTL_EFADDR:
/* read user control */
reg_addr = EFUSE_USER_CTL_REG_ADDR;
@ -86,14 +87,18 @@ ErrStatus efuse_read(uint32_t ef_addr, uint32_t size, uint32_t buf[])
break;
case DP_EFADDR:
/* read debug password */
if(RESET != (EFUSE_USER_CTL & EFUSE_USER_CTL_DPLK)) {
if(RESET != (EFUSE_USER_CTL & EFUSE_USER_CTL_JTAGNSW)) {
if((RESET != (EFUSE_USER_CTL & USER_CTL_NDBG0))) {
if(RESET != (EFUSE_USER_CTL & EFUSE_USER_CTL_DPLK))
{
if(RESET != (EFUSE_USER_CTL & EFUSE_USER_CTL_JTAGNSW))
{
if((RESET != (EFUSE_USER_CTL & USER_CTL_NDBG0)))
{
status = ERROR;
}
}
}
if(SUCCESS == status) {
if(SUCCESS == status)
{
reg_addr = EFUSE_DP_REG_ADDR;
number = 2U;
}
@ -107,7 +112,8 @@ ErrStatus efuse_read(uint32_t ef_addr, uint32_t size, uint32_t buf[])
status = ERROR;
break;
}
if(ERROR == status) {
if(ERROR == status)
{
return status;
}
/* clear the RDIF bit if it is SET */
@ -120,11 +126,13 @@ ErrStatus efuse_read(uint32_t ef_addr, uint32_t size, uint32_t buf[])
EFUSE_CTL |= EFUSE_CTL_EFSTR;
/* wait for the operation to complete */
efuse_state = efuse_ready_wait(EFUSE_FLAG_READ_COMPLETE, timeout);
if(EFUSE_READY != efuse_state) {
if(EFUSE_READY != efuse_state)
{
status = ERROR;
}
/* read EFUSE register */
for(i = 0U; i < number; i++) {
for(i = 0U; i < number; i++)
{
buf[i] = REG32(reg_addr + (4U * i));
}
return status;
@ -150,34 +158,43 @@ ErrStatus efuse_write(uint32_t ef_addr, uint32_t size, uint8_t *buf)
uint32_t buf_addr;
uint32_t timeout = EFUSE_TIMEOUT;
efuse_state_enum efuse_state;
if(0U == size) {
if(0U == size)
{
return ERROR;
}
/* the address should be on byte address boundary */
if(ef_addr % 8U) {
if(ef_addr % 8U)
{
return ERROR;
}
if(MAX_EFADDR < ef_addr) {
if(MAX_EFADDR < ef_addr)
{
return ERROR;
}
for(i = EFUSE_PARA_CNT; i > 0U; i--) {
if(ef_addr >= para_start_efaddr[i - 1U]) {
for(i = EFUSE_PARA_CNT; i > 0U; i--)
{
if(ef_addr >= para_start_efaddr[i - 1U])
{
break;
}
}
/* get the index of parameter to be programmed */
para_index = i - 1U;
/* program range should not over parameter boundary */
if(para_index == (EFUSE_PARA_CNT - 1U)) {
if((ef_addr + size * 8U - 1U) > MAX_EFADDR) {
if(para_index == (EFUSE_PARA_CNT - 1U))
{
if((ef_addr + size * 8U - 1U) > MAX_EFADDR)
{
return ERROR;
}
} else {
if((ef_addr + size * 8U - 1U) > para_start_efaddr[para_index + 1U]) {
if((ef_addr + size * 8U - 1U) > para_start_efaddr[para_index + 1U])
{
return ERROR;
}
}
if((AES_KEY_IDX == para_index) && (AES_KEY_SIZE != size)) {
if((AES_KEY_IDX == para_index) && (AES_KEY_SIZE != size))
{
/* AES key should be programmed in one time */
return ERROR;
}
@ -191,10 +208,13 @@ ErrStatus efuse_write(uint32_t ef_addr, uint32_t size, uint8_t *buf)
EFUSE_ADDR = (uint32_t)((size << EFUSE_ADDR_EFSIZE_OFFSET) | ef_addr);
buf_addr = (uint32_t)buf;
while(size) {
if((0U != byte_offset_in_reg) || ((0U == byte_offset_in_reg) && (size < 4U))) {
while(size)
{
if((0U != byte_offset_in_reg) || ((0U == byte_offset_in_reg) && (size < 4U)))
{
cnt = size < (4U - byte_offset_in_reg) ? size : 4U - byte_offset_in_reg;
for(i = 0U; i < cnt; i++) {
for(i = 0U; i < cnt; i++)
{
tmp_buf_8 = buf_addr;
/* write the data to the corresponding register */
tmp_buf_8 += i;
@ -206,7 +226,8 @@ ErrStatus efuse_write(uint32_t ef_addr, uint32_t size, uint8_t *buf)
buf_addr += cnt;
} else {
cnt = size / 4U;
for(i = 0U; i < cnt; i++) {
for(i = 0U; i < cnt; i++)
{
tmp_buf_8 = buf_addr;
/* write the data to the corresponding register */
tmp_buf_8 += (i * 4U);
@ -221,7 +242,8 @@ ErrStatus efuse_write(uint32_t ef_addr, uint32_t size, uint8_t *buf)
EFUSE_CTL |= EFUSE_CTL_EFSTR;
/* wait for the operation to complete */
efuse_state = efuse_ready_wait(EFUSE_FLAG_PROGRAM_COMPLETE, timeout);
if(EFUSE_READY != efuse_state) {
if(EFUSE_READY != efuse_state)
{
status = ERROR;
}
return status;
@ -333,7 +355,8 @@ FlagStatus efuse_monitor_program_voltage_get(void)
{
FlagStatus mpven_state = RESET;
if(EFUSE_CTL_MPVEN == (uint32_t)(EFUSE_CTL & EFUSE_CTL_MPVEN)) {
if(EFUSE_CTL_MPVEN == (uint32_t)(EFUSE_CTL & EFUSE_CTL_MPVEN))
{
mpven_state = SET;
} else {
mpven_state = RESET;
@ -351,7 +374,8 @@ FlagStatus efuse_ldo_ready_get(void)
{
FlagStatus ldo_ready_state = RESET;
if(EFUSE_STAT_LDO_RDY == (uint32_t)(EFUSE_STAT & EFUSE_STAT_LDO_RDY)) {
if(EFUSE_STAT_LDO_RDY == (uint32_t)(EFUSE_STAT & EFUSE_STAT_LDO_RDY))
{
ldo_ready_state = SET;
} else {
ldo_ready_state = RESET;
@ -372,7 +396,8 @@ FlagStatus efuse_ldo_ready_get(void)
*/
FlagStatus efuse_flag_get(uint32_t flag)
{
if(EFUSE_STAT & (uint32_t)flag) {
if(EFUSE_STAT & (uint32_t)flag)
{
return SET;
} else {
return RESET;
@ -446,7 +471,8 @@ FlagStatus efuse_interrupt_flag_get(uint32_t int_flag)
/* get the corresponding flag bit status */
flagstatus = (EFUSE_REG_VAL2(int_flag) & BIT(EFUSE_BIT_POS2(int_flag)));
if(flagstatus && intenable) {
if(flagstatus && intenable)
{
return SET;
} else {
return RESET;
@ -492,11 +518,14 @@ static efuse_state_enum efuse_ready_wait(uint32_t efuse_flag, uint32_t timeout)
/* wait for EFUSE ready */
do {
/* get EFUSE flag set or not */
if(EFUSE_STAT & (uint32_t)efuse_flag) {
if(EFUSE_STAT & (uint32_t)efuse_flag)
{
efuse_state = EFUSE_READY;
} else if(EFUSE_STAT & EFUSE_STAT_IAERRIF) {
} else if(EFUSE_STAT & EFUSE_STAT_IAERRIF)
{
efuse_state = EFUSE_IAERR;
} else if(EFUSE_STAT & EFUSE_STAT_PVIF) {
} else if(EFUSE_STAT & EFUSE_STAT_PVIF)
{
efuse_state = EFUSE_PVERR;
} else {
/* illegal parameters */
@ -504,7 +533,8 @@ static efuse_state_enum efuse_ready_wait(uint32_t efuse_flag, uint32_t timeout)
timeout--;
} while((EFUSE_BUSY == efuse_state) && (0U != timeout));
if(EFUSE_BUSY == efuse_state) {
if(EFUSE_BUSY == efuse_state)
{
efuse_state = EFUSE_TOERR;
}

492
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_enet.c
View File

File diff suppressed because it is too large Load Diff

45
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_exmc.c
View File

@ -224,7 +224,8 @@ void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct)
exmc_norsram_init_struct->cram_page_size);
/* nor flash access enable */
if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) {
if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type)
{
snctl |= (uint32_t)EXMC_SNCTL_NREN;
}
@ -237,7 +238,8 @@ void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct)
exmc_norsram_init_struct->read_write_timing->syn_data_latency |
exmc_norsram_init_struct->read_write_timing->asyn_access_mode);
if(ENABLE == exmc_norsram_init_struct->extended_mode) {
if(ENABLE == exmc_norsram_init_struct->extended_mode)
{
/* for extended mode, configure write timing */
snwtcfg = (uint32_t)(exmc_norsram_init_struct->write_timing->asyn_address_setuptime |
(exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) |
@ -459,7 +461,8 @@ void exmc_sdram_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct)
uint32_t sdctl0, sdctl1, sdtcfg0, sdtcfg1;
/* configure EXMC_SDCTL0 or EXMC_SDCTL1 */
if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device) {
if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device)
{
/* configure EXMC_SDCTL0 */
EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)(exmc_sdram_init_struct->column_address_width |
exmc_sdram_init_struct->row_address_width |
@ -561,7 +564,8 @@ uint32_t exmc_norsram_sdram_remap_get(void)
*/
void exmc_norsram_consecutive_clock_config(uint32_t clock_mode)
{
if(EXMC_CLOCK_UNCONDITIONALLY == clock_mode) {
if(EXMC_CLOCK_UNCONDITIONALLY == clock_mode)
{
EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= EXMC_CLOCK_UNCONDITIONALLY;
} else {
EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_CLOCK_UNCONDITIONALLY;
@ -599,7 +603,8 @@ void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_s
*/
void exmc_nand_ecc_config(ControlStatus newvalue)
{
if(ENABLE == newvalue) {
if(ENABLE == newvalue)
{
/* enable NAND bank ECC function */
EXMC_NCTL |= EXMC_NCTL_ECCEN;
} else {
@ -722,7 +727,8 @@ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number)
*/
void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue)
{
if(ENABLE == newvalue) {
if(ENABLE == newvalue)
{
EXMC_SDCTL(exmc_sdram_device) |= (uint32_t)EXMC_SDCTL_WPEN;
} else {
EXMC_SDCTL(exmc_sdram_device) &= ~((uint32_t)EXMC_SDCTL_WPEN);
@ -741,7 +747,8 @@ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device)
{
uint32_t sdstat = 0U;
if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device) {
if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device)
{
sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA0) >> SDSTAT_STA0_OFFSET);
} else {
sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA1) >> SDSTAT_STA1_OFFSET);
@ -772,7 +779,8 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag)
{
uint32_t status = 0x00000000U;
if(EXMC_BANK2_NAND == exmc_bank) {
if(EXMC_BANK2_NAND == exmc_bank)
{
/* NAND bank2 */
status = EXMC_NINTEN;
} else {
@ -780,7 +788,8 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag)
status = EXMC_SDSTAT;
}
if((status & flag) != (uint32_t)flag) {
if((status & flag) != (uint32_t)flag)
{
/* flag is reset */
return RESET;
} else {
@ -808,7 +817,8 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag)
*/
void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag)
{
if(EXMC_BANK2_NAND == exmc_bank) {
if(EXMC_BANK2_NAND == exmc_bank)
{
/* NAND bank2 */
EXMC_NINTEN &= ~flag;
} else {
@ -835,7 +845,8 @@ void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag)
*/
void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt)
{
if(EXMC_BANK2_NAND == exmc_bank) {
if(EXMC_BANK2_NAND == exmc_bank)
{
/* NAND bank2 */
EXMC_NINTEN |= interrupt;
} else {
@ -862,7 +873,8 @@ void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt)
*/
void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt)
{
if(EXMC_BANK2_NAND == exmc_bank) {
if(EXMC_BANK2_NAND == exmc_bank)
{
/* NAND bank2 */
EXMC_NINTEN &= ~interrupt;
} else {
@ -893,7 +905,8 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt)
uint32_t interrupt_enable = 0x00000000U;
uint32_t interrupt_status = 0x00000000U;
if(EXMC_BANK2_NAND == exmc_bank) {
if(EXMC_BANK2_NAND == exmc_bank)
{
/* NAND bank2 */
reg_value = EXMC_NINTEN;
interrupt_status = (reg_value & (interrupt >> NINTEN_INTEN_INTS_INTERVAL));
@ -905,7 +918,8 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt)
interrupt_enable = (reg_value & interrupt);
if((interrupt_enable) && (interrupt_status)) {
if((interrupt_enable) && (interrupt_status))
{
/* interrupt flag is set */
return SET;
} else {
@ -932,7 +946,8 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt)
*/
void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt)
{
if(EXMC_BANK2_NAND == exmc_bank) {
if(EXMC_BANK2_NAND == exmc_bank)
{
/* NAND bank2 */
EXMC_NINTEN &= ~(interrupt >> NINTEN_INTEN_INTS_INTERVAL);
} else {

12
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_exti.c
View File

@ -84,7 +84,8 @@ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum tr
EXTI_FTEN(EXTI_REG_VAL(linex)) &= ~EXTI_BIT_POS(linex);
/* set the EXTI mode and enable the interrupts or events from EXTI line x */
switch(mode) {
switch(mode)
{
case EXTI_INTERRUPT:
EXTI_INTEN(EXTI_REG_VAL(linex)) |= EXTI_BIT_POS(linex);
break;
@ -96,7 +97,8 @@ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum tr
}
/* set the EXTI trigger type */
switch(trig_type) {
switch(trig_type)
{
case EXTI_TRIG_RISING:
EXTI_RTEN(EXTI_REG_VAL(linex)) |= EXTI_BIT_POS(linex);
EXTI_FTEN(EXTI_REG_VAL(linex)) &= ~EXTI_BIT_POS(linex);
@ -203,7 +205,8 @@ void exti_software_interrupt_disable(exti_line_enum linex)
*/
FlagStatus exti_flag_get(exti_line_enum linex)
{
if(RESET != (EXTI_PD(EXTI_REG_VAL(linex)) & EXTI_BIT_POS(linex))) {
if(RESET != (EXTI_PD(EXTI_REG_VAL(linex)) & EXTI_BIT_POS(linex)))
{
return SET;
} else {
return RESET;
@ -233,7 +236,8 @@ void exti_flag_clear(exti_line_enum linex)
*/
FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
{
if(RESET != (EXTI_PD(EXTI_REG_VAL(linex)) & EXTI_BIT_POS(linex))) {
if(RESET != (EXTI_PD(EXTI_REG_VAL(linex)) & EXTI_BIT_POS(linex)))
{
return SET;
} else {
return RESET;

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_fac.c
View File

@ -186,12 +186,14 @@ void fac_fixed_buffer_preload(fac_fixed_data_preload_struct *init_struct)
fac_fixed_data_preload(init_struct->coeffb_size, (init_struct->coeffb_ctx));
/* load the x1 buffer for cofficientA */
if((NULL != init_struct->coeffa_ctx) && (0U != init_struct->coeffa_size)) {
if((NULL != init_struct->coeffa_ctx) && (0U != init_struct->coeffa_size))
{
/* Load the buffer into the internal memory */
fac_fixed_data_preload(init_struct->coeffa_size, (init_struct->coeffa_ctx));
}
/* if need configure to preload output buffer */
if((NULL != init_struct->output_ctx) && (0U != init_struct->output_size)) {
if((NULL != init_struct->output_ctx) && (0U != init_struct->output_size))
{
FAC_PARACFG = ((uint32_t)init_struct->output_size & FAC_PARACFG_IPP) | \
FUNC_LOAD_Y | FAC_PARACFG_EXE;
@ -235,12 +237,14 @@ void fac_float_buffer_preload(fac_float_data_preload_struct *init_struct)
fac_float_data_preload(init_struct->coeffb_size, (init_struct->coeffb_ctx));
/* load the x1 buffer for cofficientA */
if((NULL != init_struct->coeffa_ctx) && (0U != init_struct->coeffa_size)) {
if((NULL != init_struct->coeffa_ctx) && (0U != init_struct->coeffa_size))
{
/* load the buffer into the internal memory */
fac_float_data_preload(init_struct->coeffa_size, (init_struct->coeffa_ctx));
}
/* if need configure to preload output buffer */
if((NULL != init_struct->output_ctx) && (0U != init_struct->output_size)) {
if((NULL != init_struct->output_ctx) && (0U != init_struct->output_size))
{
FAC_PARACFG = ((uint32_t)init_struct->output_size & FAC_PARACFG_IPP) | \
FUNC_LOAD_Y | FAC_PARACFG_EXE;
@ -258,7 +262,8 @@ void fac_float_buffer_preload(fac_float_data_preload_struct *init_struct)
void fac_fixed_data_preload(uint8_t size, int16_t array[])
{
uint8_t i;
for(i = 0U; i < size; i++) {
for(i = 0U; i < size; i++)
{
FAC_WDATA = ((*((uint16_t*)&array[i])) & FAC_WDATA_WDATA);
}
}
@ -273,7 +278,8 @@ void fac_fixed_data_preload(uint8_t size, int16_t array[])
void fac_float_data_preload(uint8_t size, float array[])
{
uint8_t i;
for(i = 0U; i < size; i++) {
for(i = 0U; i < size; i++)
{
FAC_WDATA = ((*((uint32_t*) & array[i])));
}
}
@ -300,7 +306,8 @@ void fac_reset(void)
*/
void fac_clip_config(uint8_t cpmod)
{
if(FAC_CP_ENABLE == cpmod) {
if(FAC_CP_ENABLE == cpmod)
{
FAC_CTL |= FAC_CTL_CPEN;
} else {
FAC_CTL &= ~(FAC_CTL_CPEN);
@ -593,7 +600,8 @@ FlagStatus fac_interrupt_flag_get(uint8_t interrupt)
uint32_t reg1 = FAC_CTL;
uint32_t reg2 = FAC_STAT;
switch(interrupt) {
switch(interrupt)
{
/* Y buffer read interrupt */
case FAC_INT_FLAG_YBEF:
reg1 = reg1 & FAC_CTL_RIE;
@ -628,7 +636,8 @@ FlagStatus fac_interrupt_flag_get(uint8_t interrupt)
break;
}
/*get FAC interrupt flag status */
if(reg1 && reg2) {
if(reg1 && reg2)
{
return SET;
} else {
return RESET;
@ -650,7 +659,8 @@ FlagStatus fac_interrupt_flag_get(uint8_t interrupt)
*/
FlagStatus fac_flag_get(uint32_t flag)
{
if(FAC_STAT & flag) {
if(FAC_STAT & flag)
{
return SET;
} else {
return RESET;

138
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_fmc.c
View File

@ -78,7 +78,8 @@ static fmc_state_enum fmc_ready_wait(uint32_t timeout);
*/
void fmc_unlock(void)
{
if((RESET != (FMC_CTL & FMC_CTL_LK))) {
if((RESET != (FMC_CTL & FMC_CTL_LK)))
{
/* write the FMC key */
FMC_KEY = UNLOCK_KEY0;
FMC_KEY = UNLOCK_KEY1;
@ -120,7 +121,8 @@ fmc_state_enum fmc_sector_erase(uint32_t address)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
FMC_CTL |= FMC_CTL_SER;
/* write the sector address */
FMC_ADDR = address;
@ -159,7 +161,8 @@ fmc_state_enum fmc_typical_mass_erase(void)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
/* enable mass erase operation */
FMC_CTL |= FMC_CTL_MER;
/* start whole chip erase */
@ -197,7 +200,8 @@ fmc_state_enum fmc_protection_removed_mass_erase(void)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
/* remove DCRP area */
ob_dcrp_area_config(OB_DCRP_AREA_ERASE_ENABLE, INVALID_DCRP_START_ADDR, INVALID_DCRP_END_ADDR);
/* remove secure-access area */
@ -242,7 +246,8 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
/* set the PG bit to start program */
FMC_CTL |= FMC_CTL_PG;
__ISB();
@ -287,7 +292,8 @@ fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data)
data0 = (uint32_t)(data & 0xFFFFFFFFU);
data1 = (uint32_t)((data >> 32U) & 0xFFFFFFFFU);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
/* set the PG bit to start program */
FMC_CTL |= FMC_CTL_PG;
__ISB();
@ -372,7 +378,8 @@ fmc_state_enum fmc_check_programming_area_disable(void)
*/
void ob_unlock(void)
{
if(RESET != (FMC_OBCTL & FMC_OBCTL_OBLK)) {
if(RESET != (FMC_OBCTL & FMC_OBCTL_OBLK))
{
/* write the FMC key */
FMC_OBKEY = OB_UNLOCK_KEY0;
FMC_OBKEY = OB_UNLOCK_KEY1;
@ -442,7 +449,8 @@ fmc_state_enum ob_factory_value_config(void)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
/* get the option byte security protection value */
obstat0_reg = (FMC_OBSTAT0_EFT & FMC_OBSTAT0_EFT_SPC);
/* write factory value to FMC_OBSTAT0_MDF */
@ -488,7 +496,8 @@ fmc_state_enum ob_secure_access_mode_enable(void)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
obstat0_reg = FMC_OBSTAT0_EFT;
/* enable secure access mode */
obstat0_reg |= FMC_OBSTAT0_MDF_SCR;
@ -522,7 +531,8 @@ fmc_state_enum ob_secure_access_mode_disable(void)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
obstat0_reg = FMC_OBSTAT0_EFT;
/* disable secure access mode */
obstat0_reg &= ~FMC_OBSTAT0_MDF_SCR;
@ -560,7 +570,8 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
obstat0_reg = FMC_OBSTAT0_EFT;
/* reset the OBSTAT0_SPC, set according to ob_spc */
obstat0_reg &= ~FMC_OBSTAT0_MDF_SPC;
@ -600,7 +611,8 @@ fmc_state_enum ob_bor_threshold_config(uint32_t ob_bor_th)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
obstat0_reg = FMC_OBSTAT0_EFT;
/* set BOR threshold level */
obstat0_reg &= ~FMC_OBSTAT0_MDF_BOR_TH;
@ -654,7 +666,8 @@ fmc_state_enum ob_low_power_config(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uin
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
obstat0_reg = FMC_OBSTAT0_EFT;
/* set according to ob_fwdgt, ob_deepsleep, ob_stdby, ob_fwdg_suspend_deepsleep, ob_fwdg_suspend_standby */
obstat0_reg &= ~(FMC_OBSTAT0_MDF_NWDG_HW | FMC_OBSTAT0_MDF_NRST_DPSLP | FMC_OBSTAT0_MDF_NRST_STDBY
@ -700,7 +713,8 @@ fmc_state_enum ob_tcm_ecc_config(uint32_t ob_itcmecc, uint32_t ob_dtcm0ecc, uint
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
obstat0_reg = FMC_OBSTAT0_EFT;
/* set according to ob_itcmecc, ob_dtcm0ecc, ob_stdby, ob_dtcm1ecc */
obstat0_reg &= ~(FMC_OBSTAT0_MDF_ITCMECCEN | FMC_OBSTAT0_MDF_DTCM0ECCEN | FMC_OBSTAT0_MDF_DTCM1ECCEN);
@ -737,7 +751,8 @@ fmc_state_enum ob_iospeed_optimize_config(uint32_t ob_iospeed_op)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
obstat0_reg = FMC_OBSTAT0_EFT;
/* set according to ob_iospeed_op */
obstat0_reg &= ~(FMC_OBSTAT0_MDF_IOSPDOPEN);
@ -786,7 +801,8 @@ fmc_state_enum ob_tcm_shared_ram_config(uint32_t itcm_shared_ram_size, uint32_t
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
obstat1_reg = FMC_OBSTAT1_EFT;
/* set ITCM shared ram size according to itcm_shared_ram_size */
@ -827,7 +843,8 @@ fmc_state_enum ob_data_program(uint16_t ob_data)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
obstat1_reg = FMC_OBSTAT1_EFT;
/* modify user data according to ob_data */
@ -867,10 +884,12 @@ fmc_state_enum ob_boot_address_config(uint8_t boot_pin, uint16_t boot_address)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
btaddr_reg = FMC_BTADDR_EFT;
if(BOOT_PIN_0 == boot_pin) {
if(BOOT_PIN_0 == boot_pin)
{
/* set to boot address 0 */
btaddr_reg &= ~FMC_BTADDR_MDF_BOOT_ADDR0;
btaddr_reg |= (uint32_t)((uint32_t)boot_address << BTADDR_BOOT_ADDR0_OFFSET);
@ -913,7 +932,8 @@ fmc_state_enum ob_dcrp_area_config(uint32_t dcrp_eren, uint32_t dcrp_start, uint
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
dcrpaddr_reg = 0U;
dcrpaddr_reg |= dcrp_eren;
dcrpaddr_reg |= dcrp_start;
@ -952,7 +972,8 @@ fmc_state_enum ob_secure_area_config(uint32_t scr_eren, uint32_t scr_start, uint
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
scraddr_reg = 0U;
scraddr_reg |= scr_eren;
scraddr_reg |= scr_start;
@ -1011,7 +1032,8 @@ fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
wp_reg &= ~ob_wp;
FMC_WP_MDF = wp_reg;
}
@ -1067,7 +1089,8 @@ fmc_state_enum ob_write_protection_disable(uint32_t ob_wp)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
wp_reg |= ob_wp;
FMC_WP_MDF = wp_reg;
}
@ -1085,7 +1108,8 @@ FlagStatus ob_secure_mode_get(void)
{
FlagStatus secure_mode_state = RESET;
if(OB_SECURE_MODE_ENABLE == (uint32_t)(FMC_OBSTAT0_EFT & FMC_OBSTAT0_EFT_SCR)) {
if(OB_SECURE_MODE_ENABLE == (uint32_t)(FMC_OBSTAT0_EFT & FMC_OBSTAT0_EFT_SCR))
{
secure_mode_state = SET;
} else {
secure_mode_state = RESET;
@ -1103,7 +1127,8 @@ FlagStatus ob_security_protection_flag_get(void)
{
FlagStatus spc_state = RESET;
if(((uint8_t)(FMC_OBSTAT0_EFT >> OBSTAT0_SPC_OFFSET)) != (uint8_t)FMC_NSPC) {
if(((uint8_t)(FMC_OBSTAT0_EFT >> OBSTAT0_SPC_OFFSET)) != (uint8_t)FMC_NSPC)
{
spc_state = SET;
} else {
spc_state = RESET;
@ -1192,7 +1217,8 @@ FlagStatus ob_iospeed_optimize_get(void)
{
FlagStatus iospeed_opt_state = RESET;
if(OB_IOSPDOPEN_ENABLE == (uint32_t)(FMC_OBSTAT0_EFT & FMC_OBSTAT0_EFT_IOSPDOPEN)) {
if(OB_IOSPDOPEN_ENABLE == (uint32_t)(FMC_OBSTAT0_EFT & FMC_OBSTAT0_EFT_IOSPDOPEN))
{
iospeed_opt_state = SET;
} else {
iospeed_opt_state = RESET;
@ -1224,7 +1250,8 @@ void ob_tcm_shared_ram_size_get(uint32_t *itcm_shared_ram_kb_size, uint32_t *dtc
itcm_size_value = (uint32_t)((uint32_t)FMC_OBSTAT1_EFT & FMC_OBSTAT1_EFT_ITCM_SZ_SHRRAM);
dtcm_size_value = (uint32_t)((uint32_t)FMC_OBSTAT1_EFT & FMC_OBSTAT1_EFT_DTCM_SZ_SHRRAM);
switch(itcm_size_value) {
switch(itcm_size_value)
{
case OB_ITCM_SHARED_RAM_0KB:
/* ITCM shared RAM size is 0KB */
*itcm_shared_ram_kb_size = 0U;
@ -1249,7 +1276,8 @@ void ob_tcm_shared_ram_size_get(uint32_t *itcm_shared_ram_kb_size, uint32_t *dtc
break;
}
switch(dtcm_size_value) {
switch(dtcm_size_value)
{
case OB_DTCM_SHARED_RAM_0KB:
/* DTCM shared RAM size is 0KB */
*dtcm_shared_ram_kb_size = 0U;
@ -1300,7 +1328,8 @@ uint32_t ob_boot_address_get(uint8_t boot_pin)
uint32_t boot_address;
uint32_t btaddr_reg = FMC_BTADDR_EFT;
if(BOOT_PIN_0 == boot_pin) {
if(BOOT_PIN_0 == boot_pin)
{
/* get boot address 0 */
boot_address = (uint32_t)((btaddr_reg & FMC_BTADDR_EFT_BOOT_ADDR0) << 16u);
} else {
@ -1333,12 +1362,14 @@ uint8_t ob_dcrp_area_get(uint32_t *dcrp_erase_option, uint32_t *dcrp_area_start_
*dcrp_erase_option = (uint32_t)(dcrpaddr_reg & FMC_DCRPADDR_EFT_DCRP_EREN);
*dcrp_area_start_addr = ((uint32_t)(dcrpaddr_reg & FMC_DCRPADDR_EFT_DCRP_AREA_START)) >> DCRPADDR_DCRP_AREA_START_OFFSET;
*dcrp_area_end_addr = ((uint32_t)(dcrpaddr_reg & FMC_DCRPADDR_EFT_DCRP_AREA_END)) >> DCRPADDR_DCRP_AREA_END_OFFSET;
if((*dcrp_area_start_addr) == (*dcrp_area_end_addr)) {
if((*dcrp_area_start_addr) == (*dcrp_area_end_addr))
{
/* the whole main flash memory is DCRP area */
*dcrp_area_start_addr = MAIN_FLASH_BASE_ADDRESS;
*dcrp_area_end_addr = MAIN_FLASH_BASE_ADDRESS + main_flash_size - 1U;
return VLD_AREA_ADDRESS;
} else if((*dcrp_area_start_addr) < (*dcrp_area_end_addr)) {
} else if((*dcrp_area_start_addr) < (*dcrp_area_end_addr))
{
/* get DCRP area start address */
*dcrp_area_start_addr = (*dcrp_area_start_addr) * DCRP_SIZE_UNIT;
*dcrp_area_start_addr += MAIN_FLASH_BASE_ADDRESS;
@ -1375,12 +1406,14 @@ uint8_t ob_secure_area_get(uint32_t *secure_area_option, uint32_t *scr_area_star
*secure_area_option = (uint32_t)(scraddr_reg & FMC_SCRADDR_EFT_SCR_EREN);
*scr_area_start_addr = ((uint32_t)(scraddr_reg & FMC_SCRADDR_EFT_SCR_AREA_START)) >> SCRADDR_SCR_AREA_START_OFFSET;
*scr_area_end_addr = ((uint32_t)(scraddr_reg & FMC_SCRADDR_EFT_SCR_AREA_END)) >> SCRADDR_SCR_AREA_END_OFFSET;
if((*scr_area_start_addr) == (*scr_area_end_addr)) {
if((*scr_area_start_addr) == (*scr_area_end_addr))
{
/* the whole main flash memory is secure-access area */
*scr_area_start_addr = MAIN_FLASH_BASE_ADDRESS;
*scr_area_end_addr = MAIN_FLASH_BASE_ADDRESS + main_flash_size - 1U;
return VLD_AREA_ADDRESS;
} else if((*scr_area_start_addr) < (*scr_area_end_addr)) {
} else if((*scr_area_start_addr) < (*scr_area_end_addr))
{
/* get secure-access area start address */
*scr_area_start_addr = (*scr_area_start_addr) * SCR_SIZE_UNIT;
*scr_area_start_addr += MAIN_FLASH_BASE_ADDRESS;
@ -1431,7 +1464,8 @@ fmc_state_enum fmc_no_rtdec_config(uint32_t nodec_area_start, uint32_t nodec_are
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
fmc_unlock();
nodec_reg = 0U;
nodec_reg |= nodec_area_start;
@ -1467,7 +1501,8 @@ fmc_state_enum fmc_aes_iv_config(uint32_t *aes_iv)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state) {
if(FMC_READY == fmc_state)
{
fmc_unlock();
FMC_AESIV0_MDF = *(uint32_t *)(aes_iv_addr);
aes_iv_addr += 4U;
@ -1556,7 +1591,8 @@ void fmc_pid_get(uint32_t *pid)
*/
FlagStatus fmc_flag_get(fmc_flag_enum flag)
{
if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))) {
if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag))))
{
return SET;
} else {
return RESET;
@ -1647,7 +1683,8 @@ FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum int_flag)
/* get the corresponding flag bit status */
flagstatus = (FMC_REG_VAL2(int_flag) & BIT(FMC_BIT_POS2(int_flag)));
if(flagstatus && intenable) {
if(flagstatus && intenable)
{
return SET;
} else {
return RESET;
@ -1694,22 +1731,30 @@ static fmc_state_enum fmc_state_get(void)
{
fmc_state_enum fmc_state = FMC_READY;
if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)) {
if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY))
{
fmc_state = FMC_BUSY;
} else {
if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)) {
if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR))
{
fmc_state = FMC_WPERR;
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGSERR)) {
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGSERR))
{
fmc_state = FMC_PGSERR;
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_RPERR)) {
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_RPERR))
{
fmc_state = FMC_RPERR;
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_RSERR)) {
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_RSERR))
{
fmc_state = FMC_RSERR;
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_ECCCOR)) {
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_ECCCOR))
{
fmc_state = FMC_ECCCOR;
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_ECCDET)) {
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_ECCDET))
{
fmc_state = FMC_ECCDET;
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_OBMERR)) {
} else if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_OBMERR))
{
fmc_state = FMC_OBMERR;
} else {
/* illegal parameters */
@ -1747,7 +1792,8 @@ static fmc_state_enum fmc_ready_wait(uint32_t timeout)
timeout--;
} while((FMC_BUSY == fmc_state) && (0U != timeout));
if(FMC_BUSY == fmc_state) {
if(FMC_BUSY == fmc_state)
{
fmc_state = FMC_TOERR;
}
/* return the FMC state */

18
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_fwdgt.c
View File

@ -101,7 +101,8 @@ ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
} while((--timeout > (uint32_t)0x00000000U) && (RESET != flag_status));
if(RESET != flag_status){
if(RESET != flag_status)
{
return ERROR;
}
@ -130,7 +131,8 @@ ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
}while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){
if ((uint32_t)RESET != flag_status)
{
return ERROR;
}
@ -158,7 +160,8 @@ ErrStatus fwdgt_window_value_config(uint16_t window_value)
flag_status = FWDGT_STAT & FWDGT_STAT_WUD;
}while((--time_index > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){
if ((uint32_t)RESET != flag_status)
{
return ERROR;
}
@ -206,7 +209,8 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
}while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){
if ((uint32_t)RESET != flag_status)
{
return ERROR;
}
@ -219,7 +223,8 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
}while((--timeout > (uint32_t)0x00000000U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){
if ((uint32_t)RESET != flag_status)
{
return ERROR;
}
@ -243,7 +248,8 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
*/
FlagStatus fwdgt_flag_get(uint16_t flag)
{
if (RESET != (FWDGT_STAT & flag)){
if (RESET != (FWDGT_STAT & flag))
{
return SET;
}
return RESET;

51
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_gpio.c
View File

@ -44,7 +44,8 @@ OF SUCH DAMAGE.
*/
void gpio_deinit(uint32_t gpio_periph)
{
switch(gpio_periph){
switch(gpio_periph)
{
case GPIOA:
/* reset GPIOA */
rcu_periph_reset_enable(RCU_GPIOARST);
@ -130,8 +131,10 @@ void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, u
ctl = GPIO_CTL(gpio_periph);
pupd = GPIO_PUD(gpio_periph);
for(i = 0U;i < 16U;i++){
if((1U << i) & pin){
for(i = 0U;i < 16U;i++)
{
if((1U << i) & pin)
{
/* clear the specified pin mode bits */
ctl &= ~GPIO_MODE_MASK(i);
/* set the specified pin mode bits */
@ -174,7 +177,8 @@ void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed
uint16_t i;
uint32_t ospeed;
if(GPIO_OTYPE_OD == otype){
if(GPIO_OTYPE_OD == otype)
{
GPIO_OMODE(gpio_periph) |= (uint32_t)pin;
}else{
GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin);
@ -183,8 +187,10 @@ void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed
/* get the specified pin output speed bits value */
ospeed = GPIO_OSPD(gpio_periph);
for(i = 0U;i < 16U;i++){
if((1U << i) & pin){
for(i = 0U;i < 16U;i++)
{
if((1U << i) & pin)
{
/* clear the specified pin output speed bits */
ospeed &= ~GPIO_OSPEED_MASK(i);
/* set the specified pin output speed bits */
@ -243,7 +249,8 @@ void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
*/
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
{
if(RESET != bit_value){
if(RESET != bit_value)
{
GPIO_BOP(gpio_periph) = (uint32_t)pin;
}else{
GPIO_BC(gpio_periph) = (uint32_t)pin;
@ -291,11 +298,13 @@ void gpio_input_filter_set(uint32_t gpio_periph, uint8_t speriod, uint32_t iftyp
uint32_t iftp;
isperiod = GPIO_IFL(gpio_periph);
if(pin & 0x000000FFU){
if(pin & 0x000000FFU)
{
isperiod &= ~GPIO_IFL_FLPRD0;
isperiod |= (uint32_t)speriod;
}
if(pin & 0x0000FF00U){
if(pin & 0x0000FF00U)
{
isperiod &= ~GPIO_IFL_FLPRD1;
isperiod |= ((uint32_t)speriod << 8U);
}
@ -303,8 +312,10 @@ void gpio_input_filter_set(uint32_t gpio_periph, uint8_t speriod, uint32_t iftyp
/* get the specified pin output speed bits value */
iftp = GPIO_IFTP(gpio_periph);
for(i = 0U;i < 16U;i++){
if((1U << i) & pin){
for(i = 0U;i < 16U;i++)
{
if((1U << i) & pin)
{
/* clear the specified pin output speed bits */
iftp &= ~GPIO_IFTYPE_MASK(i);
/* set the specified pin output speed bits */
@ -327,7 +338,8 @@ void gpio_input_filter_set(uint32_t gpio_periph, uint8_t speriod, uint32_t iftyp
*/
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
{
if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){
if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin)))
{
return SET;
}else{
return RESET;
@ -360,7 +372,8 @@ uint16_t gpio_input_port_get(uint32_t gpio_periph)
*/
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
{
if((uint32_t)RESET != (GPIO_OCTL(gpio_periph)&(pin))){
if((uint32_t)RESET != (GPIO_OCTL(gpio_periph)&(pin)))
{
return SET;
}else{
return RESET;
@ -418,16 +431,20 @@ void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin)
afrl = GPIO_AFSEL0(gpio_periph);
afrh = GPIO_AFSEL1(gpio_periph);
for(i = 0U;i < 8U;i++){
if((1U << i) & pin){
for(i = 0U;i < 8U;i++)
{
if((1U << i) & pin)
{
/* clear the specified pin alternate function bits */
afrl &= ~GPIO_AFR_MASK(i);
afrl |= GPIO_AFR_SET(i,alt_func_num);
}
}
for(i = 8U;i < 16U;i++){
if((1U << i) & pin){
for(i = 8U;i < 16U;i++)
{
if((1U << i) & pin)
{
/* clear the specified pin alternate function bits */
afrh &= ~GPIO_AFR_MASK(i - 8U);
afrh |= GPIO_AFR_SET(i - 8U,alt_func_num);

27
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_hau.c
View File

@ -70,7 +70,8 @@ void hau_init(hau_init_parameter_struct* initpara)
HAU_CTL |= (initpara->algo | initpara->datatype | initpara->mode);
/* when mode is HMAC, set the key */
if(HAU_MODE_HMAC == initpara->mode){
if(HAU_MODE_HMAC == initpara->mode)
{
HAU_CTL &= (~(uint32_t)HAU_CTL_KLM);
HAU_CTL |= initpara->keytype;
}
@ -229,7 +230,8 @@ void hau_context_struct_para_init(hau_context_parameter_struct* context)
context->hau_inten_bak = 0U;
context->hau_cfg_bak = 0U;
context->hau_ctl_bak = 0U;
for(i = 0U; i <= HMAC_CONTEXT_INTERNAL_REG; i++){
for(i = 0U; i <= HMAC_CONTEXT_INTERNAL_REG; i++)
{
context->hau_ctxs_bak[i] = 0U;
}
}
@ -251,10 +253,12 @@ void hau_context_save(hau_context_parameter_struct* context_save)
context_save->hau_cfg_bak = HAU_CFG;
context_save->hau_ctl_bak = HAU_CTL;
if(0U != (HAU_CTL & HAU_CTL_HMS)){
if(0U != (HAU_CTL & HAU_CTL_HMS))
{
i_max = HMAC_CONTEXT_INTERNAL_REG;
}
for(i = 0U; i <= i_max; i++){
for(i = 0U; i <= i_max; i++)
{
context_save->hau_ctxs_bak[i] = HAU_CTXS(i);
}
}
@ -278,10 +282,12 @@ void hau_context_restore(hau_context_parameter_struct* context_restore)
HAU_CTL |= HAU_CTL_START;
/* continue restoring context registers */
if(0U != (HAU_CTL & HAU_CTL_HMS)){
if(0U != (HAU_CTL & HAU_CTL_HMS))
{
i_max = HMAC_CONTEXT_INTERNAL_REG;
}
for(i = 0U; i <= i_max; i++){
for(i = 0U; i <= i_max; i++)
{
HAU_CTXS(i) = context_restore->hau_ctxs_bak[i];
}
}
@ -304,13 +310,15 @@ FlagStatus hau_flag_get(uint32_t flag)
FlagStatus ret_flag = RESET;
/* check if the flag is in HAU_CTL register */
if(RESET != (flag & HAU_FLAG_INFIFO_NO_EMPTY)){
if(RESET != (flag & HAU_FLAG_INFIFO_NO_EMPTY))
{
ret = HAU_CTL;
}else{
ret = HAU_STAT;
}
if (RESET != (ret & flag)){
if (RESET != (ret & flag))
{
ret_flag = SET;
}
@ -376,7 +384,8 @@ FlagStatus hau_interrupt_flag_get(uint32_t int_flag)
/* return the status of the interrupt */
ret = HAU_STAT;
if(RESET != ((HAU_INTEN & ret) & int_flag)){
if(RESET != ((HAU_INTEN & ret) & int_flag))
{
flag = SET;
}

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_hau_sha_md5.c
View File

@ -179,7 +179,8 @@ static void hau_sha_md5_digest_read(uint32_t algo, uint8_t output[])
hau_digest_parameter_struct digest_para;
uint32_t outputaddr = (uint32_t)output;
switch(algo){
switch(algo)
{
case HAU_ALGO_SHA1:
/* read the message digest result */
hau_digest_read(&digest_para);
@ -283,7 +284,8 @@ static ErrStatus hau_hash_calculate(uint32_t algo, uint8_t input[], uint32_t in_
hau_last_word_validbits_num_config(num_last_valid);
/* write data to the IN FIFO */
for(i = 0U; i < in_length; i += 4U){
for(i = 0U; i < in_length; i += 4U)
{
hau_data_write(*(uint32_t*)inputaddr);
inputaddr += 4U;
}
@ -297,7 +299,8 @@ static ErrStatus hau_hash_calculate(uint32_t algo, uint8_t input[], uint32_t in_
counter++;
}while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus){
if(RESET != busystatus)
{
return ERROR;
}else{
/* read the message digest */
@ -340,7 +343,8 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t key[], uint32_t keysi
init_para.algo = algo;
init_para.mode = HAU_MODE_HMAC;
init_para.datatype = HAU_SWAPPING_8BIT;
if(keysize > 64U){
if(keysize > 64U)
{
init_para.keytype = HAU_KEY_LONGGER_64;
}else{
init_para.keytype = HAU_KEY_SHORTER_64;
@ -351,7 +355,8 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t key[], uint32_t keysi
hau_last_word_validbits_num_config((uint32_t)num_key_valid);
/* write the key */
for(i = 0U; i < keysize; i += 4U){
for(i = 0U; i < keysize; i += 4U)
{
hau_data_write(*(uint32_t*)keyaddr);
keyaddr += 4U;
}
@ -365,14 +370,16 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t key[], uint32_t keysi
counter++;
}while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus){
if(RESET != busystatus)
{
return ERROR;
}else{
/* configure the number of valid bits in last word of the message */
hau_last_word_validbits_num_config((uint32_t)num_last_valid);
/* write data to the IN FIFO */
for(i = 0U; i < in_length; i += 4U){
for(i = 0U; i < in_length; i += 4U)
{
hau_data_write(*(uint32_t*)inputaddr);
inputaddr += 4U;
}
@ -387,7 +394,8 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t key[], uint32_t keysi
counter++;
}while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus){
if(RESET != busystatus)
{
return ERROR;
}else{
/* configure the number of valid bits in last word of the key */
@ -395,7 +403,8 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t key[], uint32_t keysi
/* write the key */
keyaddr = (uint32_t)key;
for(i = 0U; i < keysize; i += 4U){
for(i = 0U; i < keysize; i += 4U)
{
hau_data_write(*(uint32_t*)keyaddr);
keyaddr += 4U;
}
@ -410,7 +419,8 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t key[], uint32_t keysi
counter++;
}while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus){
if(RESET != busystatus)
{
return ERROR;
}else{
/* read the message digest */

171
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_hpdf.c
View File

@ -50,7 +50,8 @@ OF SUCH DAMAGE.
#define FLTYCT_CTCNT_OFFSET ((uint32_t)0x00000004U) /*!< bit offset of CTCNT in FLTYCT */
#define SIGN_BIT_OFFSET ((uint32_t)0x00800000U) /*!< bit offset of signed value */
#define HPDF_WRONG_HANDLE while(1){}
#define HPDF_WRONG_HANDLE while(1)
{}
/*!
\brief reset HPDF
@ -88,7 +89,8 @@ void hpdf_deinit(void)
void hpdf_channel_struct_para_init(hpdf_channel_parameter_struct *init_struct)
{
/* check whether the struct is empty */
if(NULL == init_struct) {
if(NULL == init_struct)
{
HPDF_WRONG_HANDLE
}
/* set the struct with the default values */
@ -127,7 +129,8 @@ void hpdf_channel_struct_para_init(hpdf_channel_parameter_struct *init_struct)
void hpdf_filter_struct_para_init(hpdf_filter_parameter_struct *init_struct)
{
/* check whether the struct is empty */
if(NULL == init_struct) {
if(NULL == init_struct)
{
HPDF_WRONG_HANDLE
}
/* set the struct with the default values */
@ -152,7 +155,8 @@ void hpdf_filter_struct_para_init(hpdf_filter_parameter_struct *init_struct)
void hpdf_rc_struct_para_init(hpdf_rc_parameter_struct *init_struct)
{
/* check whether the struct is empty */
if(NULL == init_struct) {
if(NULL == init_struct)
{
HPDF_WRONG_HANDLE
}
/* set the struct with the default values */
@ -172,7 +176,8 @@ void hpdf_rc_struct_para_init(hpdf_rc_parameter_struct *init_struct)
void hpdf_ic_struct_para_init(hpdf_ic_parameter_struct *init_struct)
{
/* check whether the struct is empty */
if(NULL == init_struct) {
if(NULL == init_struct)
{
HPDF_WRONG_HANDLE
}
/* set the struct with the default values */
@ -405,7 +410,8 @@ void hpdf_clock_output_source_config(uint32_t source)
void hpdf_clock_output_duty_mode_disable(void)
{
/* make sure the HPDF_CH0CTL_HPDFEN=0 */
if(RESET == (HPDF_CHXCTL(CHANNEL0) & HPDF_CH0CTL_HPDFEN)) {
if(RESET == (HPDF_CHXCTL(CHANNEL0) & HPDF_CH0CTL_HPDFEN))
{
HPDF_CHXCTL(CHANNEL0) &= ~CKOUTDM_ENABLE;
}
}
@ -419,7 +425,8 @@ void hpdf_clock_output_duty_mode_disable(void)
void hpdf_clock_output_duty_mode_enable(void)
{
/* make sure the HPDF_CH0CTL_HPDFEN=0 */
if(RESET == (HPDF_CHXCTL(CHANNEL0) & HPDF_CH0CTL_HPDFEN)) {
if(RESET == (HPDF_CHXCTL(CHANNEL0) & HPDF_CH0CTL_HPDFEN))
{
HPDF_CHXCTL(CHANNEL0) |= CKOUTDM_ENABLE;
}
}
@ -434,7 +441,8 @@ void hpdf_clock_output_divider_config(uint8_t divider)
{
uint32_t reg;
/* make sure the HPDF_CH0CTL_HPDFEN=0 */
if(RESET == (HPDF_CHXCTL(CHANNEL0) & HPDF_CH0CTL_HPDFEN)) {
if(RESET == (HPDF_CHXCTL(CHANNEL0) & HPDF_CH0CTL_HPDFEN))
{
reg = HPDF_CHXCTL(CHANNEL0);
reg &= ~HPDF_CH0CTL_CKOUTDIV;
reg |= ((uint32_t)divider << CH0CTL_CKOUTDIV_OFFSET);
@ -481,7 +489,8 @@ void hpdf_spi_clock_source_config(hpdf_channel_enum channelx, uint32_t clock_sou
uint32_t reg;
reg = HPDF_CHXCTL(channelx);
/* make sure the CHEN=0 */
if(RESET == (reg & HPDF_CHXCTL_CHEN)) {
if(RESET == (reg & HPDF_CHXCTL_CHEN))
{
reg &= ~HPDF_CHXCTL_SPICKSS;
reg |= clock_source;
HPDF_CHXCTL(channelx) = reg;
@ -505,7 +514,8 @@ void hpdf_serial_interface_type_config(hpdf_channel_enum channelx, uint32_t type
uint32_t reg;
reg = HPDF_CHXCTL(channelx);
/* make sure the CHEN=0 */
if(RESET == (reg & HPDF_CHXCTL_CHEN)) {
if(RESET == (reg & HPDF_CHXCTL_CHEN))
{
reg &= ~HPDF_CHXCTL_SITYP;
reg |= type;
HPDF_CHXCTL(channelx) = reg;
@ -565,7 +575,8 @@ void hpdf_clock_loss_enable(hpdf_channel_enum channelx)
void hpdf_channel_pin_redirection_disable(hpdf_channel_enum channelx)
{
/* make sure the CHEN=0 */
if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN)) {
if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN))
{
HPDF_CHXCTL(channelx) &= ~HPDF_CHXCTL_CHPINSEL;
}
}
@ -579,7 +590,8 @@ void hpdf_channel_pin_redirection_disable(hpdf_channel_enum channelx)
void hpdf_channel_pin_redirection_enable(hpdf_channel_enum channelx)
{
/* make sure the CHEN=0 */
if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN)) {
if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN))
{
HPDF_CHXCTL(channelx) |= HPDF_CHXCTL_CHPINSEL;
}
}
@ -600,7 +612,8 @@ void hpdf_channel_multiplexer_config(hpdf_channel_enum channelx, uint32_t data_s
uint32_t reg;
reg = HPDF_CHXCTL(channelx);
/* make sure the CHEN=0 */
if(RESET == (reg & HPDF_CHXCTL_CHEN)) {
if(RESET == (reg & HPDF_CHXCTL_CHEN))
{
reg &= ~HPDF_CHXCTL_CMSD;
/* configure the input data source */
reg |= data_source;
@ -624,7 +637,8 @@ void hpdf_data_pack_mode_config(hpdf_channel_enum channelx, uint32_t mode)
uint32_t reg;
reg = HPDF_CHXCTL(channelx);
/* make sure the CHEN=0 */
if(RESET == (reg & HPDF_CHXCTL_CHEN)) {
if(RESET == (reg & HPDF_CHXCTL_CHEN))
{
reg &= ~HPDF_CHXCTL_DPM;
/* configure the data packing mode */
reg |= mode;
@ -643,7 +657,8 @@ void hpdf_data_right_bit_shift_config(hpdf_channel_enum channelx, uint8_t right_
{
uint32_t reg;
/* make sure the CHEN=0 */
if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN)) {
if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN))
{
reg = HPDF_CHXCFG0(channelx);
reg &= ~HPDF_CHXCFG0_DTRS;
/* configure the right shift */
@ -719,9 +734,11 @@ void hpdf_malfunction_counter_config(hpdf_channel_enum channelx, uint8_t thresho
void hpdf_write_parallel_data_standard_mode(hpdf_channel_enum channelx, int16_t data)
{
/* make sure HPDF channel is used receive parallel data */
if(INTERNAL_INPUT == (HPDF_CHXCTL(channelx) & INTERNAL_INPUT)) {
if(INTERNAL_INPUT == (HPDF_CHXCTL(channelx) & INTERNAL_INPUT))
{
/* make sure the data pack of HPDF_CHXPDI register is standard mode */
if(DPM_STANDARD_MODE == (HPDF_CHXCTL(channelx) & DPM_STANDARD_MODE)) {
if(DPM_STANDARD_MODE == (HPDF_CHXCTL(channelx) & DPM_STANDARD_MODE))
{
HPDF_CHXPDI(channelx) = (uint16_t)data;
}
}
@ -737,9 +754,11 @@ void hpdf_write_parallel_data_standard_mode(hpdf_channel_enum channelx, int16_t
void hpdf_write_parallel_data_interleaved_mode(hpdf_channel_enum channelx, int32_t data)
{
/* make sure HPDF channel is used receive parallel data */
if(INTERNAL_INPUT == (HPDF_CHXCTL(channelx) & INTERNAL_INPUT)) {
if(INTERNAL_INPUT == (HPDF_CHXCTL(channelx) & INTERNAL_INPUT))
{
/* make sure the data pack of HPDF_CH0PDI register is interleaved mode */
if(DPM_INTERLEAVED_MODE == (HPDF_CHXCTL(channelx) & DPM_INTERLEAVED_MODE)) {
if(DPM_INTERLEAVED_MODE == (HPDF_CHXCTL(channelx) & DPM_INTERLEAVED_MODE))
{
HPDF_CHXPDI(channelx) = (uint32_t)data;
}
}
@ -755,9 +774,11 @@ void hpdf_write_parallel_data_interleaved_mode(hpdf_channel_enum channelx, int32
void hpdf_write_parallel_data_dual_mode(hpdf_channel_enum channelx, int32_t data)
{
/* make sure HPDF channel is used receive parallel data */
if(INTERNAL_INPUT == (HPDF_CHXCTL(channelx) & INTERNAL_INPUT)) {
if(INTERNAL_INPUT == (HPDF_CHXCTL(channelx) & INTERNAL_INPUT))
{
/* make sure the data pack of HPDF_CH0PDI register is dual mode */
if(DPM_DUAL_MODE == (HPDF_CHXCTL(channelx) & DPM_DUAL_MODE)) {
if(DPM_DUAL_MODE == (HPDF_CHXCTL(channelx) & DPM_DUAL_MODE))
{
HPDF_CHXPDI(channelx) = (uint32_t)data;
}
}
@ -831,7 +852,8 @@ void hpdf_filter_config(hpdf_filter_enum filtery, uint32_t order, uint16_t overs
{
uint32_t reg;
/* make sure the FLTEN=0 */
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
reg = HPDF_FLTYSFCFG(filtery);
reg &= ~(HPDF_FLTYSFCFG_SFO | HPDF_FLTYSFCFG_SFOR);
/* configure the sinc filter order and oversample */
@ -851,7 +873,8 @@ void hpdf_integrator_oversample(hpdf_filter_enum filtery, uint16_t oversample)
{
uint32_t reg;
/* make sure the FLTEN=0 */
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
reg = HPDF_FLTYSFCFG(filtery);
reg &= ~HPDF_FLTYSFCFG_IOR;
/* configure the integrator oversampling rate */
@ -877,7 +900,8 @@ void hpdf_threshold_monitor_filter_config(hpdf_channel_enum channelx, uint32_t o
{
uint32_t reg;
/* make sure the CHEN=0 */
if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN)) {
if(RESET == (HPDF_CHXCTL(channelx) & HPDF_CHXCTL_CHEN))
{
reg = HPDF_CHXCFG1(channelx);
reg &= ~(HPDF_CHXCFG1_TMSFO | HPDF_CHXCFG1_TMFOR);
/* configure the threshold monitor filter order and oversample rate */
@ -1047,7 +1071,8 @@ int32_t hpdf_extremes_monitor_maximum_get(hpdf_filter_enum filtery)
/* get the maximum value */
val = HPDF_FLTYEMMAX(filtery) >> FLTYEMMAX_MAXVAL_OFFSET;
/* get the sign of value */
if(val & SIGN_BIT_OFFSET) {
if(val & SIGN_BIT_OFFSET)
{
val |= 0xFF000000U;
}
return (int32_t)val;
@ -1065,7 +1090,8 @@ int32_t hpdf_extremes_monitor_minimum_get(hpdf_filter_enum filtery)
/* get the channel of maximum value */
val = HPDF_FLTYEMMIN(filtery) >> FLTYEMMIN_MINVAL_OFFSET;
/* get the sign of vlaue */
if(val & SIGN_BIT_OFFSET) {
if(val & SIGN_BIT_OFFSET)
{
val |= 0xFF000000U;
}
return (int32_t)val;
@ -1126,7 +1152,8 @@ void hpdf_rc_start_by_software(hpdf_filter_enum filtery)
*/
void hpdf_rc_syn_disable(hpdf_filter_enum filtery)
{
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_RCSYN;
}
}
@ -1139,7 +1166,8 @@ void hpdf_rc_syn_disable(hpdf_filter_enum filtery)
*/
void hpdf_rc_syn_enable(hpdf_filter_enum filtery)
{
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_RCSYN;
}
}
@ -1152,7 +1180,8 @@ void hpdf_rc_syn_enable(hpdf_filter_enum filtery)
*/
void hpdf_rc_dma_disable(hpdf_filter_enum filtery)
{
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_RCDMAEN;
}
}
@ -1165,7 +1194,8 @@ void hpdf_rc_dma_disable(hpdf_filter_enum filtery)
*/
void hpdf_rc_dma_enable(hpdf_filter_enum filtery)
{
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_RCDMAEN;
}
}
@ -1196,7 +1226,8 @@ void hpdf_rc_channel_config(hpdf_filter_enum filtery, uint32_t channel)
*/
void hpdf_rc_fast_mode_disable(hpdf_filter_enum filtery)
{
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_FAST;
}
}
@ -1209,7 +1240,8 @@ void hpdf_rc_fast_mode_disable(hpdf_filter_enum filtery)
*/
void hpdf_rc_fast_mode_enable(hpdf_filter_enum filtery)
{
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_FAST;
}
}
@ -1226,7 +1258,8 @@ int32_t hpdf_rc_data_get(hpdf_filter_enum filtery)
/* get the signed data */
val = HPDF_FLTYRDATA(filtery) >> FLTYRDATAT_RDATA_OFFSET;
/* get the sign of vlaue */
if(val & SIGN_BIT_OFFSET) {
if(val & SIGN_BIT_OFFSET)
{
val |= 0xFF000000U;
}
return (int32_t)val;
@ -1265,7 +1298,8 @@ void hpdf_ic_start_by_software(hpdf_filter_enum filtery)
*/
void hpdf_ic_syn_disable(hpdf_filter_enum filtery)
{
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_ICSYN;
}
}
@ -1278,7 +1312,8 @@ void hpdf_ic_syn_disable(hpdf_filter_enum filtery)
*/
void hpdf_ic_syn_enable(hpdf_filter_enum filtery)
{
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_ICSYN;
}
}
@ -1291,7 +1326,8 @@ void hpdf_ic_syn_enable(hpdf_filter_enum filtery)
*/
void hpdf_ic_dma_disable(hpdf_filter_enum filtery)
{
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_ICDMAEN;
}
}
@ -1304,7 +1340,8 @@ void hpdf_ic_dma_disable(hpdf_filter_enum filtery)
*/
void hpdf_ic_dma_enable(hpdf_filter_enum filtery)
{
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_ICDMAEN;
}
}
@ -1317,7 +1354,8 @@ void hpdf_ic_dma_enable(hpdf_filter_enum filtery)
*/
void hpdf_ic_scan_mode_disable(hpdf_filter_enum filtery)
{
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_SCMOD;
}
}
@ -1330,7 +1368,8 @@ void hpdf_ic_scan_mode_disable(hpdf_filter_enum filtery)
*/
void hpdf_ic_scan_mode_enable(hpdf_filter_enum filtery)
{
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) |= HPDF_FLTYCTL0_SCMOD;
}
}
@ -1343,7 +1382,8 @@ void hpdf_ic_scan_mode_enable(hpdf_filter_enum filtery)
*/
void hpdf_ic_trigger_signal_disable(hpdf_filter_enum filtery)
{
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
HPDF_FLTYCTL0(filtery) &= ~HPDF_FLTYCTL0_ICTEEN;
}
}
@ -1380,7 +1420,8 @@ void hpdf_ic_trigger_signal_config(hpdf_filter_enum filtery, uint32_t trigger, u
{
uint32_t reg;
/* make sure the FLTEN=0 */
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN)) {
if(RESET == (HPDF_FLTYCTL0(filtery) & HPDF_FLTYCTL0_FLTEN))
{
reg = HPDF_FLTYCTL0(filtery);
reg &= ~(HPDF_FLTYCTL0_ICTEEN | HPDF_FLTYCTL0_ICTSSEL);
/* configure inserted conversions trigger siganl and trigger edge */
@ -1419,7 +1460,8 @@ int32_t hpdf_ic_data_get(hpdf_filter_enum filtery)
/* get the unsigned data */
val = HPDF_FLTYIDATA(filtery) >> FLTYIDATAT_IDATA_OFFSET;
/* get the sign of value */
if(val & SIGN_BIT_OFFSET) {
if(val & SIGN_BIT_OFFSET)
{
val |= 0xFF000000U;
}
/* get the signed data */
@ -1463,10 +1505,12 @@ uint8_t hpdf_ic_channel_get(hpdf_filter_enum filtery)
FlagStatus hpdf_flag_get(hpdf_filter_enum filtery, hpdf_flag_enum flag)
{
FlagStatus flag_state = RESET;
switch(filtery) {
switch(filtery)
{
case FLT0:
/* get the flag in FLT0 register */
if(RESET != (HPDF_REG_VAL(HPDF_FLT0, flag) & BIT(HPDF_BIT_POS(flag)))) {
if(RESET != (HPDF_REG_VAL(HPDF_FLT0, flag) & BIT(HPDF_BIT_POS(flag))))
{
flag_state = SET;
} else {
flag_state = RESET;
@ -1474,7 +1518,8 @@ FlagStatus hpdf_flag_get(hpdf_filter_enum filtery, hpdf_flag_enum flag)
break;
case FLT1:
/* get the flag in FLT1 register */
if(RESET != (HPDF_REG_VAL(HPDF_FLT1, flag) & BIT(HPDF_BIT_POS(flag)))) {
if(RESET != (HPDF_REG_VAL(HPDF_FLT1, flag) & BIT(HPDF_BIT_POS(flag))))
{
flag_state = SET;
} else {
flag_state = RESET;
@ -1482,7 +1527,8 @@ FlagStatus hpdf_flag_get(hpdf_filter_enum filtery, hpdf_flag_enum flag)
break;
case FLT2:
/* get the flag in FLT2 register */
if(RESET != (HPDF_REG_VAL(HPDF_FLT2, flag) & BIT(HPDF_BIT_POS(flag)))) {
if(RESET != (HPDF_REG_VAL(HPDF_FLT2, flag) & BIT(HPDF_BIT_POS(flag))))
{
flag_state = SET;
} else {
flag_state = RESET;
@ -1490,7 +1536,8 @@ FlagStatus hpdf_flag_get(hpdf_filter_enum filtery, hpdf_flag_enum flag)
break;
case FLT3:
/* get the flag in FLT3 register */
if(RESET != (HPDF_REG_VAL(HPDF_FLT3, flag) & BIT(HPDF_BIT_POS(flag)))) {
if(RESET != (HPDF_REG_VAL(HPDF_FLT3, flag) & BIT(HPDF_BIT_POS(flag))))
{
flag_state = SET;
} else {
flag_state = RESET;
@ -1521,11 +1568,13 @@ FlagStatus hpdf_flag_get(hpdf_filter_enum filtery, hpdf_flag_enum flag)
*/
void hpdf_flag_clear(hpdf_filter_enum filtery, hpdf_flag_enum flag)
{
if(FLTYTMSTAT_REG_OFFSET == ((uint32_t)flag >> 6)) {
if(FLTYTMSTAT_REG_OFFSET == ((uint32_t)flag >> 6))
{
/* clear threshold monitor high threshold flag */
HPDF_FLTYTMFC(filtery) |= BIT(HPDF_BIT_POS(flag));
} else {
switch(flag) {
switch(flag)
{
case HPDF_FLAG_FLTY_ICEF:
/* read the inserted conversion data */
HPDF_FLTYIDATA(filtery);
@ -1562,7 +1611,8 @@ void hpdf_flag_clear(hpdf_filter_enum filtery, hpdf_flag_enum flag)
*/
void hpdf_interrupt_enable(hpdf_filter_enum filtery, hpdf_interrput_enum interrupt)
{
switch(filtery) {
switch(filtery)
{
case FLT0:
HPDF_REG_VAL(HPDF_FLT0, interrupt) |= BIT(HPDF_BIT_POS(interrupt));
break;
@ -1597,7 +1647,8 @@ void hpdf_interrupt_enable(hpdf_filter_enum filtery, hpdf_interrput_enum interru
*/
void hpdf_interrupt_disable(hpdf_filter_enum filtery, hpdf_interrput_enum interrupt)
{
switch(filtery) {
switch(filtery)
{
case FLT0:
HPDF_REG_VAL(HPDF_FLT0, interrupt) &= ~BIT(HPDF_BIT_POS(interrupt));
break;
@ -1634,13 +1685,15 @@ FlagStatus hpdf_interrupt_flag_get(hpdf_filter_enum filtery, hpdf_interrput_flag
{
FlagStatus flag_state = RESET;
uint32_t int_enable = 0U, flags = 0U;
switch(filtery) {
switch(filtery)
{
case FLT0:
/* get the interrupt enable bit status */
int_enable = (HPDF_REG_VAL(HPDF_FLT0, int_flag) & BIT(HPDF_BIT_POS(int_flag)));
/* get the interrupt enable bit status */
flags = (HPDF_REG_VAL2(HPDF_FLT0, int_flag) & BIT(HPDF_BIT_POS2(int_flag)));
if(flags && int_enable) {
if(flags && int_enable)
{
flag_state = SET;
} else {
flag_state = RESET;
@ -1651,7 +1704,8 @@ FlagStatus hpdf_interrupt_flag_get(hpdf_filter_enum filtery, hpdf_interrput_flag
int_enable = (HPDF_REG_VAL(HPDF_FLT1, int_flag) & BIT(HPDF_BIT_POS(int_flag)));
/* get the interrupt enable bit status */
flags = (HPDF_REG_VAL2(HPDF_FLT1, int_flag) & BIT(HPDF_BIT_POS2(int_flag)));
if(flags && int_enable) {
if(flags && int_enable)
{
flag_state = SET;
} else {
flag_state = RESET;
@ -1662,7 +1716,8 @@ FlagStatus hpdf_interrupt_flag_get(hpdf_filter_enum filtery, hpdf_interrput_flag
int_enable = (HPDF_REG_VAL(HPDF_FLT2, int_flag) & BIT(HPDF_BIT_POS(int_flag)));
/* get the interrupt enable bit status */
flags = (HPDF_REG_VAL2(HPDF_FLT2, int_flag) & BIT(HPDF_BIT_POS2(int_flag)));
if(flags && int_enable) {
if(flags && int_enable)
{
flag_state = SET;
} else {
flag_state = RESET;
@ -1673,7 +1728,8 @@ FlagStatus hpdf_interrupt_flag_get(hpdf_filter_enum filtery, hpdf_interrput_flag
int_enable = (HPDF_REG_VAL(HPDF_FLT3, int_flag) & BIT(HPDF_BIT_POS(int_flag)));
/* get the interrupt enable bit status */
flags = (HPDF_REG_VAL2(HPDF_FLT3, int_flag) & BIT(HPDF_BIT_POS2(int_flag)));
if(flags && int_enable) {
if(flags && int_enable)
{
flag_state = SET;
} else {
flag_state = RESET;
@ -1702,7 +1758,8 @@ FlagStatus hpdf_interrupt_flag_get(hpdf_filter_enum filtery, hpdf_interrput_flag
*/
void hpdf_interrupt_flag_clear(hpdf_filter_enum filtery, hpdf_interrput_flag_enum int_flag)
{
switch(int_flag) {
switch(int_flag)
{
case HPDF_INT_FLAG_FLTY_ICEF:
/* read the inserted conversion data */
HPDF_FLTYIDATA(filtery);

21
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_hwsem.c
View File

@ -56,7 +56,8 @@ ErrStatus hwsem_lock_set(hwsem_semaphore_enum semaphore, uint8_t process)
/* read the control register to confirm the semaphore is locked by target process or not */
temp_mid = hwsem_master_id_get(semaphore);
temp_pid = hwsem_process_id_get(semaphore);
if((HWSEM_MASTER_ID == temp_mid) && (process == temp_pid)) {
if((HWSEM_MASTER_ID == temp_mid) && (process == temp_pid))
{
ret = SUCCESS;
}
@ -82,7 +83,8 @@ ErrStatus hwsem_lock_release(hwsem_semaphore_enum semaphore, uint8_t process)
HWSEM_CTL(semaphore) = (uint32_t)(CTL_MID(HWSEM_MASTER_ID) | CTL_PID(process));
lock_state = HWSEM_CTL(semaphore) & HWSEM_CTL_LK;
if(0U == lock_state) {
if(0U == lock_state)
{
ret = SUCCESS;
}
@ -101,7 +103,8 @@ ErrStatus hwsem_lock_by_reading(hwsem_semaphore_enum semaphore)
{
ErrStatus ret = ERROR;
if((uint32_t)(HWSEM_LOCK | CTL_MID(HWSEM_MASTER_ID)) == HWSEM_RLK(semaphore)) {
if((uint32_t)(HWSEM_LOCK | CTL_MID(HWSEM_MASTER_ID)) == HWSEM_RLK(semaphore))
{
ret = SUCCESS;
}
@ -121,7 +124,8 @@ ErrStatus hwsem_unlock_all(uint16_t key)
HWSEM_UNLK = UNLK_KEY(key) | UNLK_MID(HWSEM_MASTER_ID);
if(key == hwsem_key_get()) {
if(key == hwsem_key_get())
{
ret = SUCCESS;
}
return ret;
@ -165,7 +169,8 @@ FlagStatus hwsem_lock_status_get(hwsem_semaphore_enum semaphore)
{
FlagStatus ret = RESET;
if(0U != (HWSEM_CTL(semaphore) & HWSEM_LOCK)) {
if(0U != (HWSEM_CTL(semaphore) & HWSEM_LOCK))
{
ret = SET;
}
@ -207,7 +212,8 @@ FlagStatus hwsem_flag_get(hwsem_semaphore_enum semaphore)
{
FlagStatus ret = RESET;
if(RESET != ((HWSEM_STAT >> semaphore) & 0x1U)) {
if(RESET != ((HWSEM_STAT >> semaphore) & 0x1U))
{
return SET;
}
@ -239,7 +245,8 @@ FlagStatus hwsem_interrupt_flag_get(hwsem_semaphore_enum semaphore)
{
FlagStatus ret = RESET;
if(RESET != ((HWSEM_INTF >> semaphore) & 0x1U)) {
if(RESET != ((HWSEM_INTF >> semaphore) & 0x1U))
{
ret = SET;
}

15
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_i2c.c
View File

@ -57,7 +57,8 @@ OF SUCH DAMAGE.
*/
void i2c_deinit(uint32_t i2c_periph)
{
switch(i2c_periph) {
switch(i2c_periph)
{
/* reset I2C0 */
case I2C0:
rcu_periph_reset_enable(RCU_I2C0RST);
@ -592,7 +593,8 @@ void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint32_t byte_number)
*/
void i2c_dma_enable(uint32_t i2c_periph, uint8_t dma)
{
if(I2C_DMA_TRANSMIT == dma) {
if(I2C_DMA_TRANSMIT == dma)
{
I2C_CTL0(i2c_periph) |= I2C_CTL0_DENT;
} else {
I2C_CTL0(i2c_periph) |= I2C_CTL0_DENR;
@ -611,7 +613,8 @@ void i2c_dma_enable(uint32_t i2c_periph, uint8_t dma)
*/
void i2c_dma_disable(uint32_t i2c_periph, uint8_t dma)
{
if(I2C_DMA_TRANSMIT == dma) {
if(I2C_DMA_TRANSMIT == dma)
{
I2C_CTL0(i2c_periph) &= ~I2C_CTL0_DENT;
} else {
I2C_CTL0(i2c_periph) &= ~I2C_CTL0_DENR;
@ -839,7 +842,8 @@ void i2c_idle_clock_timeout_config(uint32_t i2c_periph, uint32_t timeout)
*/
FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag)
{
if(RESET != (I2C_STAT(i2c_periph) & flag)) {
if(RESET != (I2C_STAT(i2c_periph) & flag))
{
return SET;
} else {
return RESET;
@ -938,7 +942,8 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i
ret1 = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag)));
/* get the status of interrupt flag */
ret2 = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag)));
if(ret1 && ret2) {
if(ret1 && ret2)
{
return SET;
} else {
return RESET;

75
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_ipa.c
View File

@ -226,7 +226,8 @@ void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground
void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct)
{
FlagStatus tempflag = RESET;
if(RESET != (IPA_CTL & IPA_CTL_TEN)){
if(RESET != (IPA_CTL & IPA_CTL_TEN))
{
tempflag = SET;
/* reset the TEN in order to configure the following bits */
IPA_CTL &= ~IPA_CTL_TEN;
@ -243,7 +244,8 @@ void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct)
IPA_FPCTL |= (foreground_struct->foreground_prealpha << 24U);
IPA_FPCTL |= foreground_struct->foreground_alpha_algorithm;
IPA_FPCTL |= foreground_struct->foreground_pf;
if(ENABLE == foreground_struct->foreground_interlace_mode){
if(ENABLE == foreground_struct->foreground_interlace_mode)
{
IPA_FPCTL |= IPA_FPCTL_FIIMEN;
}
/* foreground pre-defined red green blue configuration */
@ -254,7 +256,8 @@ void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct)
IPA_EF_UV_MADDR &= ~(IPA_EF_UV_MADDR_EFUVMADDR);
IPA_EF_UV_MADDR = foreground_struct->foreground_efuv_memaddr;
if(SET == tempflag){
if(SET == tempflag)
{
/* restore the state of TEN */
IPA_CTL |= IPA_CTL_TEN;
}
@ -299,7 +302,8 @@ void ipa_background_struct_para_init(ipa_background_parameter_struct* background
void ipa_background_init(ipa_background_parameter_struct* background_struct)
{
FlagStatus tempflag = RESET;
if(RESET != (IPA_CTL & IPA_CTL_TEN)){
if(RESET != (IPA_CTL & IPA_CTL_TEN))
{
tempflag = SET;
/* reset the TEN in order to configure the following bits */
IPA_CTL &= ~IPA_CTL_TEN;
@ -321,7 +325,8 @@ void ipa_background_init(ipa_background_parameter_struct* background_struct)
IPA_BPV |= ((background_struct->background_prered << 16U) | (background_struct->background_pregreen << 8U)
| (background_struct->background_preblue));
if(SET == tempflag){
if(SET == tempflag)
{
/* restore the state of TEN */
IPA_CTL |= IPA_CTL_TEN;
}
@ -385,7 +390,8 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct)
{
uint32_t destination_pixelformat;
FlagStatus tempflag = RESET;
if(RESET != (IPA_CTL & IPA_CTL_TEN)){
if(RESET != (IPA_CTL & IPA_CTL_TEN))
{
tempflag = SET;
/* reset the TEN in order to configure the following bits */
IPA_CTL &= ~IPA_CTL_TEN;
@ -399,7 +405,8 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct)
destination_struct->image_ver_decimation);
destination_pixelformat = destination_struct->destination_pf;
/* destination pixel format ARGB8888 */
switch(destination_pixelformat){
switch(destination_pixelformat)
{
case IPA_DPF_ARGB8888:
IPA_DPV &= ~(IPA_DPV_DPDBV_0 | (IPA_DPV_DPDGV_0) | (IPA_DPV_DPDRV_0) | (IPA_DPV_DPDAV_0));
IPA_DPV = (destination_struct->destination_preblue | (destination_struct->destination_pregreen << 8U)
@ -453,7 +460,8 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct)
IPA_DIMS = (destination_struct->image_scaling_height & IPA_DIMS_DHEIGHT) |
((uint32_t)((destination_struct->image_scaling_width << 16U) & IPA_DIMS_DWIDTH));
if(SET == tempflag){
if(SET == tempflag)
{
/* restore the state of TEN */
IPA_CTL |= IPA_CTL_TEN;
}
@ -470,7 +478,8 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct)
void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr)
{
FlagStatus tempflag = RESET;
if(RESET != (IPA_FPCTL & IPA_FPCTL_FLLEN)){
if(RESET != (IPA_FPCTL & IPA_FPCTL_FLLEN))
{
tempflag = SET;
/* reset the FLLEN in order to configure the following bits */
IPA_FPCTL &= ~IPA_FPCTL_FLLEN;
@ -479,9 +488,11 @@ void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_
/* foreground LUT number of pixel configuration */
IPA_FPCTL |= ((uint32_t)fg_lut_num << 8U);
/* foreground LUT pixel format configuration */
if(IPA_LUT_PF_RGB888 == fg_lut_pf){
if(IPA_LUT_PF_RGB888 == fg_lut_pf)
{
IPA_FPCTL |= IPA_FPCTL_FLPF;
}else if(IPA_LUT_PF_ARGB8888 == fg_lut_pf){
}else if(IPA_LUT_PF_ARGB8888 == fg_lut_pf)
{
IPA_FPCTL &= ~(IPA_FPCTL_FLPF);
}else{
}
@ -489,7 +500,8 @@ void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_
IPA_FLMADDR &= ~(IPA_FLMADDR_FLMADDR);
IPA_FLMADDR = fg_lut_addr;
if(SET == tempflag){
if(SET == tempflag)
{
/* restore the state of FLLEN */
IPA_FPCTL |= IPA_FPCTL_FLLEN;
}
@ -506,7 +518,8 @@ void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_
void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr)
{
FlagStatus tempflag = RESET;
if(RESET != (IPA_BPCTL & IPA_BPCTL_BLLEN)){
if(RESET != (IPA_BPCTL & IPA_BPCTL_BLLEN))
{
tempflag = SET;
/* reset the BLLEN in order to configure the following bits */
IPA_BPCTL &= ~IPA_BPCTL_BLLEN;
@ -515,9 +528,11 @@ void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_
/* background LUT number of pixel configuration */
IPA_BPCTL |= ((uint32_t)bg_lut_num << 8U);
/* background LUT pixel format configuration */
if(IPA_LUT_PF_RGB888 == bg_lut_pf){
if(IPA_LUT_PF_RGB888 == bg_lut_pf)
{
IPA_BPCTL |= IPA_BPCTL_BLPF;
}else if(IPA_LUT_PF_ARGB8888 == bg_lut_pf){
}else if(IPA_LUT_PF_ARGB8888 == bg_lut_pf)
{
IPA_BPCTL &= ~(IPA_BPCTL_BLPF);
}else{
}
@ -525,7 +540,8 @@ void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_
IPA_BLMADDR &= ~(IPA_BLMADDR_BLMADDR);
IPA_BLMADDR = bg_lut_addr;
if(SET == tempflag){
if(SET == tempflag)
{
/* restore the state of BLLEN */
IPA_BPCTL |= IPA_BPCTL_BLLEN;
}
@ -551,10 +567,12 @@ void ipa_line_mark_config(uint16_t line_num)
*/
void ipa_inter_timer_config(uint8_t timer_cfg)
{
if(IPA_INTER_TIMER_ENABLE == timer_cfg){
if(IPA_INTER_TIMER_ENABLE == timer_cfg)
{
/* inter-timer enable */
IPA_ITCTL |= IPA_ITCTL_ITEN;
}else if(IPA_INTER_TIMER_DISABLE == timer_cfg){
}else if(IPA_INTER_TIMER_DISABLE == timer_cfg)
{
/* inter-timer disable */
IPA_ITCTL &= ~(IPA_ITCTL_ITEN);
}else{
@ -585,7 +603,8 @@ void ipa_interval_clock_num_config(uint8_t clk_num)
*/
void ipa_color_conversion_struct_para_init(ipa_conversion_parameter_struct* conversion_struct, ipa_colorspace_enum colorspace)
{
if(IPA_COLORSPACE_YUV == colorspace){
if(IPA_COLORSPACE_YUV == colorspace)
{
/* initialize the struct parameters with default YUV conversion values */
conversion_struct->color_space = IPA_COLORSPACE_YUV;
conversion_struct->y_offset = IPA_DEFAULT_YUV_CONV_YOFFSET;
@ -595,7 +614,8 @@ void ipa_color_conversion_struct_para_init(ipa_conversion_parameter_struct* conv
conversion_struct->coef_c2 = IPA_DEFAULT_YUV_CONV_C2OFFSET;
conversion_struct->coef_c3 = IPA_DEFAULT_YUV_CONV_C3OFFSET;
conversion_struct->coef_c4 = IPA_DEFAULT_YUV_CONV_C4OFFSET;
}else if(IPA_COLORSPACE_YCBCR == colorspace){
}else if(IPA_COLORSPACE_YCBCR == colorspace)
{
/* initialize the struct parameters with default YCbCr conversion values */
conversion_struct->color_space = IPA_COLORSPACE_YCBCR;
conversion_struct->y_offset = IPA_DEFAULT_YCBCR_CONV_YOFFSET;
@ -627,7 +647,8 @@ void ipa_color_conversion_struct_para_init(ipa_conversion_parameter_struct* conv
void ipa_color_conversion_config(ipa_conversion_parameter_struct* conversion_struct)
{
FlagStatus tempflag = RESET;
if(RESET != (IPA_CTL & IPA_CTL_TEN)){
if(RESET != (IPA_CTL & IPA_CTL_TEN))
{
tempflag = SET;
/* reset the TEN in order to configure the following bits */
IPA_CTL &= ~IPA_CTL_TEN;
@ -647,7 +668,8 @@ void ipa_color_conversion_config(ipa_conversion_parameter_struct* conversion_str
IPA_CSCC_CFG2 |= ((conversion_struct->coef_c3 & IPA_CSCC_CFG2_C3) |
((uint32_t)(conversion_struct->coef_c2 << 16U) & IPA_CSCC_CFG2_C2));
if(IPA_COLORSPACE_YUV == conversion_struct->color_space){
if(IPA_COLORSPACE_YUV == conversion_struct->color_space)
{
/* convert YUV to RGB */
IPA_CSCC_CFG0 &= ~(IPA_CSCC_CFG0_CONVMOD);
}else{
@ -655,7 +677,8 @@ void ipa_color_conversion_config(ipa_conversion_parameter_struct* conversion_str
IPA_CSCC_CFG0 |= IPA_CSCC_CFG0_CONVMOD;
}
if(SET == tempflag){
if(SET == tempflag)
{
/* restore the state of TEN */
IPA_CTL |= IPA_CTL_TEN;
}
@ -721,7 +744,8 @@ void ipa_destination_scaling_config(uint32_t dest_scaling_width, uint32_t dest_s
*/
FlagStatus ipa_flag_get(uint32_t flag)
{
if(RESET != (IPA_INTF & flag)){
if(RESET != (IPA_INTF & flag))
{
return SET;
}else{
return RESET;
@ -797,7 +821,8 @@ void ipa_interrupt_disable(uint32_t int_flag)
*/
FlagStatus ipa_interrupt_flag_get(uint32_t int_flag)
{
if(RESET != (IPA_INTF & int_flag)){
if(RESET != (IPA_INTF & int_flag))
{
return SET;
}else{
return RESET;

15
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_lpdts.c
View File

@ -205,7 +205,8 @@ int32_t lpdts_temperature_get(void)
reg_cfg = LPDTS_CFG;
/* get the module frequency on Hz */
if((reg_cfg & LPDTS_CFG_REFSEL) == LPDTS_CFG_REFSEL) {
if((reg_cfg & LPDTS_CFG_REFSEL) == LPDTS_CFG_REFSEL)
{
freq = (LXTAL_VALUE * count) / (2U * ((reg_cfg & LPDTS_CFG_SPT) >> LPDTS_CFG_SPT_OFFSET));
} else {
freq = (2U * rcu_clock_freq_get(CK_APB1) / count) * ((reg_cfg & LPDTS_CFG_SPT) >> LPDTS_CFG_SPT_OFFSET);
@ -213,7 +214,8 @@ int32_t lpdts_temperature_get(void)
/* read factory settings */
t0 = (LPDTS_SDATA & LPDTS_SDATA_VAL) >> LPDTS_SDATA_VAL_OFFSET;
if(t0 == 0U) {
if(t0 == 0U)
{
t0 = LPDTS_T0_TMP_VAL;
}
@ -240,7 +242,8 @@ FlagStatus lpdts_flag_get(uint32_t flag)
{
FlagStatus status = RESET;
if(LPDTS_STAT & flag) {
if(LPDTS_STAT & flag)
{
status = SET;
}
/* return the state of corresponding LPDTS flag */
@ -302,9 +305,11 @@ FlagStatus lpdts_interrupt_flag_get(uint32_t flag)
uint32_t state;
state = LPDTS_STAT;
if(state & flag) {
if(state & flag)
{
state = LPDTS_INTEN;
if(state & flag) {
if(state & flag)
{
status = SET;
}
}

12
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_mdio.c
View File

@ -308,7 +308,8 @@ FlagStatus mdio_flag_get(uint32_t flag)
__IO uint32_t reg = 0U;
reg = MDIO_STAT;
if(RESET != (reg & flag)){
if(RESET != (reg & flag))
{
return SET;
}else{
return RESET;
@ -341,12 +342,15 @@ void mdio_flag_clear(uint32_t flag)
reg = MDIO_TDATA;
if((MDIO_FLAG_RX_OVERRUN | MDIO_FLAG_RBNE) & flag){
if((MDIO_FLAG_RX_OVERRUN | MDIO_FLAG_RBNE) & flag)
{
(void)(MDIO_RDATA);
}else if(MDIO_FLAG_TX_UNDERRUN & flag){
}else if(MDIO_FLAG_TX_UNDERRUN & flag)
{
MDIO_TDATA = reg;
}else if((MDIO_FLAG_WRFRM | MDIO_FLAG_ADDRFRM | MDIO_FLAG_RDINCFRM | MDIO_FLAG_RDFRM
| MDIO_FLAG_DEVM | MDIO_FLAG_DEVNM | MDIO_FLAG_PHYM | MDIO_FLAG_PHYNM | MDIO_FLAG_TIMEOUT) & flag){
| MDIO_FLAG_DEVM | MDIO_FLAG_DEVNM | MDIO_FLAG_PHYM | MDIO_FLAG_PHYNM | MDIO_FLAG_TIMEOUT) & flag)
{
(void)(MDIO_STAT);
} else {
/* illegal parameters */

51
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_mdma.c
View File

@ -204,14 +204,18 @@ void mdma_init(mdma_channel_enum channelx, mdma_parameter_struct *init_struct)
MDMA_CHXDADDR(channelx) = init_struct->destination_addr;
/* configure block transfer byte number */
if(MDMA_BUFFER_TRANSFER == init_struct->trans_trig_mode) {
if(MDMA_BUFFER_TRANSFER == init_struct->trans_trig_mode)
{
MDMA_CHXBTCFG(channelx) = (init_struct->tbytes_num_in_block & MDMA_CHXBTCFG_TBNUM);
} else if(MDMA_BLOCK_TRANSFER == init_struct->trans_trig_mode) {
} else if(MDMA_BLOCK_TRANSFER == init_struct->trans_trig_mode)
{
MDMA_CHXBTCFG(channelx) = (init_struct->tbytes_num_in_block & MDMA_CHXBTCFG_TBNUM);
} else if(MDMA_MULTI_BLOCK_TRANSFER == init_struct->trans_trig_mode) {
} else if(MDMA_MULTI_BLOCK_TRANSFER == init_struct->trans_trig_mode)
{
MDMA_CHXBTCFG(channelx) &= ~MDMA_CHXBTCFG_TBNUM;
MDMA_CHXBTCFG(channelx) |= (init_struct->tbytes_num_in_block & MDMA_CHXBTCFG_TBNUM);
} else if(MDMA_COMPLETE_TRANSFER == init_struct->trans_trig_mode) {
} else if(MDMA_COMPLETE_TRANSFER == init_struct->trans_trig_mode)
{
MDMA_CHXBTCFG(channelx) &= ~MDMA_CHXBTCFG_TBNUM;
MDMA_CHXBTCFG(channelx) |= (init_struct->tbytes_num_in_block & MDMA_CHXBTCFG_TBNUM);
} else {
@ -220,7 +224,8 @@ void mdma_init(mdma_channel_enum channelx, mdma_parameter_struct *init_struct)
/* configure request source */
MDMA_CHXCFG(channelx) &= ~MDMA_CHXCFG_SWREQMOD;
if(MDMA_REQUEST_SW == init_struct->request) {
if(MDMA_REQUEST_SW == init_struct->request)
{
MDMA_CHXCFG(channelx) |= MDMA_CHXCFG_SWREQMOD;
} else {
MDMA_CHXCTL1(channelx) &= ~MDMA_CHXCTL1_TRIGSEL;
@ -274,7 +279,8 @@ void mdma_multi_block_mode_config(mdma_channel_enum channelx, uint32_t tbnum, md
MDMA_CHXMBADDRU(channelx) &= ~(MDMA_CHXMBADDRU_SADDRUV | MDMA_CHXMBADDRU_DADDRUV);
/* if block source address offset is negative, set the block repeat source address update mode to decrement */
if(UPDATE_DIR_DECREASE == block_init_struct->saddr_update_dir) {
if(UPDATE_DIR_DECREASE == block_init_struct->saddr_update_dir)
{
MDMA_CHXBTCFG(channelx) |= MDMA_CHXBTCFG_SADDRUM;
/* write new chxmbaddru register value: source repeat block offset */
blockoffset = (uint32_t)block_init_struct->saddr_update_val;
@ -285,7 +291,8 @@ void mdma_multi_block_mode_config(mdma_channel_enum channelx, uint32_t tbnum, md
MDMA_CHXMBADDRU(channelx) |= (((uint32_t)block_init_struct->saddr_update_val) & MDMA_ADDRESS_MASK);
}
if(UPDATE_DIR_DECREASE == block_init_struct->dstaddr_update_dir) {
if(UPDATE_DIR_DECREASE == block_init_struct->dstaddr_update_dir)
{
MDMA_CHXBTCFG(channelx) |= MDMA_CHXBTCFG_DADDRUM;
/* write new chxmbaddru register value: destination repeat block offset */
blockoffset = (uint32_t)block_init_struct->dstaddr_update_val;
@ -357,7 +364,8 @@ void mdma_node_create(mdma_link_node_parameter_struct *node, mdma_multi_block_pa
node->chxcfg_reg = cfg;
/* configure channel request source */
if(MDMA_REQUEST_SW == init_struct->request) {
if(MDMA_REQUEST_SW == init_struct->request)
{
node->chxcfg_reg |= MDMA_CHXCFG_SWREQMOD;
} else {
node->chxctl1_reg &= ~MDMA_CHXCTL1_TRIGSEL;
@ -379,7 +387,8 @@ void mdma_node_create(mdma_link_node_parameter_struct *node, mdma_multi_block_pa
node->chxmbaddru_reg &= ~(MDMA_CHXMBADDRU_SADDRUV | MDMA_CHXMBADDRU_DADDRUV);
/* if block source address offset is negative, set the block repeat source address update mode to decrement */
if(UPDATE_DIR_DECREASE == block_init_struct->saddr_update_val) {
if(UPDATE_DIR_DECREASE == block_init_struct->saddr_update_val)
{
node->chxbtcfg_reg |= MDMA_CHXBTCFG_SADDRUM;
/* write new chxmbaddru register value: source repeat block offset */
blockoffset = (uint32_t)block_init_struct->saddr_update_val;
@ -390,7 +399,8 @@ void mdma_node_create(mdma_link_node_parameter_struct *node, mdma_multi_block_pa
node->chxmbaddru_reg |= (((uint32_t)block_init_struct->saddr_update_val) & MDMA_ADDRESS_MASK);
}
if(UPDATE_DIR_DECREASE == block_init_struct->dstaddr_update_dir) {
if(UPDATE_DIR_DECREASE == block_init_struct->dstaddr_update_dir)
{
node->chxbtcfg_reg |= MDMA_CHXBTCFG_DADDRUM;
/* write new chxmbaddru register value: destination repeat block offset */
blockoffset = (uint32_t)block_init_struct->dstaddr_update_val;
@ -462,7 +472,8 @@ void mdma_node_add(mdma_link_node_parameter_struct *pre_node, mdma_link_node_par
*/
ErrStatus mdma_node_delete(mdma_link_node_parameter_struct *pre_node, mdma_link_node_parameter_struct *unused_node)
{
if(pre_node->chxladdr_reg != (uint32_t)unused_node) {
if(pre_node->chxladdr_reg != (uint32_t)unused_node)
{
/* link address unmatched */
return ERROR;
} else {
@ -855,17 +866,20 @@ FlagStatus mdma_flag_get(mdma_channel_enum channelx, uint32_t flag)
{
uint32_t flag_pos = 0U;
if(STAT1_FLAG & flag) {
if(STAT1_FLAG & flag)
{
/* get the flag in CHXSTAT1 */
flag_pos = (flag & STAT1_FLAG_MASK);
if(MDMA_CHXSTAT1(channelx) & flag_pos) {
if(MDMA_CHXSTAT1(channelx) & flag_pos)
{
return SET;
} else {
return RESET;
}
} else {
/* get the flag in CHXSTAT0 */
if(MDMA_CHXSTAT0(channelx) & flag) {
if(MDMA_CHXSTAT0(channelx) & flag)
{
return SET;
} else {
return RESET;
@ -894,7 +908,8 @@ FlagStatus mdma_flag_get(mdma_channel_enum channelx, uint32_t flag)
*/
void mdma_flag_clear(mdma_channel_enum channelx, uint32_t flag)
{
if(STAT1_FLAG & flag) {
if(STAT1_FLAG & flag)
{
MDMA_CHXSTATC(channelx) |= MDMA_CHXSTATC_ERRC;
} else {
MDMA_CHXSTATC(channelx) |= flag;
@ -960,7 +975,8 @@ FlagStatus mdma_interrupt_flag_get(mdma_channel_enum channelx, uint32_t int_flag
{
uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
switch(int_flag) {
switch(int_flag)
{
case MDMA_INT_FLAG_ERR:
/* get error interrupt enable bit and flag bit */
interrupt_enable = (MDMA_CHXCTL0(channelx) & MDMA_CHXCTL0_ERRIE);
@ -990,7 +1006,8 @@ FlagStatus mdma_interrupt_flag_get(mdma_channel_enum channelx, uint32_t int_flag
break;
}
if(interrupt_flag && interrupt_enable) {
if(interrupt_flag && interrupt_enable)
{
return SET;
} else {
return RESET;

6
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_misc.c
View File

@ -66,7 +66,8 @@ void nvic_irq_enable(uint8_t nvic_irq,
uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
/* use the priority group value to get the temp_pre and the temp_sub */
switch((SCB->AIRCR) & (uint32_t)0x700U) {
switch((SCB->AIRCR) & (uint32_t)0x700U)
{
case NVIC_PRIGROUP_PRE0_SUB4:
temp_pre = 0U;
temp_sub = 0x4U;
@ -175,7 +176,8 @@ void system_lowpower_reset(uint8_t lowpower_mode)
*/
void systick_clksource_set(uint32_t systick_clksource)
{
if(SYSTICK_CLKSOURCE_CKSYS == systick_clksource) {
if(SYSTICK_CLKSOURCE_CKSYS == systick_clksource)
{
/* set the systick clock source from CK_SYS */
SysTick->CTRL |= SYSTICK_CLKSOURCE_CKSYS;
} else {

90
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_ospi.c
View File

@ -44,7 +44,8 @@ static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct
*/
void ospi_deinit(uint32_t ospi_periph)
{
switch(ospi_periph){
switch(ospi_periph)
{
case OSPI0:
/* reset OSPI0 */
rcu_periph_reset_enable(RCU_OSPI0RST);
@ -118,7 +119,8 @@ void ospi_init(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct)
OSPI_CTL(ospi_periph) = (OSPI_CTL(ospi_periph) & ~OSPI_CTL_FTL) | ospi_struct->fifo_threshold;
/* wait till BUSY flag reset */
while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_BUSY)){
while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_BUSY))
{
}
/* configure clock prescaler */
@ -1177,18 +1179,22 @@ void ospi_write_dummy_cycles_config(uint32_t ospi_periph, uint32_t dumyc)
void ospi_command_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct, ospi_regular_cmd_struct *cmd_struct)
{
if(((cmd_struct->operation_type == OSPI_OPTYPE_WRITE_CFG) || (cmd_struct->operation_type == OSPI_OPTYPE_WRAP_CFG)) ||
((cmd_struct->operation_type == OSPI_OPTYPE_READ_CFG) || (cmd_struct->operation_type == OSPI_OPTYPE_COMMON_CFG))){
((cmd_struct->operation_type == OSPI_OPTYPE_READ_CFG) || (cmd_struct->operation_type == OSPI_OPTYPE_COMMON_CFG)))
{
/* wait till busy flag is reset */
while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_BUSY)){
while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_BUSY))
{
}
/* configure the registers */
ospi_config(ospi_periph, ospi_struct, cmd_struct);
if(cmd_struct->data_mode == OSPI_DATA_NONE){
if(cmd_struct->data_mode == OSPI_DATA_NONE)
{
/* when there is no data phase, the transfer start as soon as the configuration is done
so wait until TC flag is set to go back in idle state */
while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_TC)){
while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_TC))
{
}
OSPI_STATC(ospi_periph) = OSPI_STATC_TCC;
@ -1216,7 +1222,8 @@ void ospi_transmit(uint32_t ospi_periph, uint8_t *pdata)
do{
/* wait till fifo threshold flag is set to send data */
while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_FT)){
while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_FT))
{
}
*((__IO uint8_t *)&OSPI_DATA(ospi_periph)) = *(uint8_t *)address;
address++;
@ -1224,7 +1231,8 @@ void ospi_transmit(uint32_t ospi_periph, uint8_t *pdata)
}while(txcounter > 0U);
/* wait till transfer complete flag is set to go back in idle state */
while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_TC)){
while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_TC))
{
}
/* clear transfer complete flag */
@ -1253,7 +1261,8 @@ void ospi_receive(uint32_t ospi_periph, uint8_t *pdata)
OSPI_CTL(ospi_periph) = (OSPI_CTL(ospi_periph) & ~OSPI_CTL_FMOD) | OSPI_INDIRECT_READ;
/* trigger the transfer by re-writing address or instruction register */
if((OSPI_TCFG(ospi_periph) & OSPI_TCFG_ADDRMOD) != OSPI_ADDRESS_NONE){
if((OSPI_TCFG(ospi_periph) & OSPI_TCFG_ADDRMOD) != OSPI_ADDRESS_NONE)
{
OSPI_ADDR(ospi_periph) = addr_reg;
}else{
OSPI_INS(ospi_periph) = ins_reg;
@ -1261,7 +1270,8 @@ void ospi_receive(uint32_t ospi_periph, uint8_t *pdata)
do{
/* wait till fifo threshold or transfer complete flags are set to read received data */
while(RESET == (OSPI_STAT(ospi_periph) & (OSPI_FLAG_FT | OSPI_FLAG_TC))){
while(RESET == (OSPI_STAT(ospi_periph) & (OSPI_FLAG_FT | OSPI_FLAG_TC)))
{
}
*(uint8_t *)address = *((__IO uint8_t *)&OSPI_DATA(ospi_periph));
@ -1271,7 +1281,8 @@ void ospi_receive(uint32_t ospi_periph, uint8_t *pdata)
}while(rxcounter > 0U);
/* wait till transfer complete flag is set to go back in idle state */
while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_TC)){
while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_TC))
{
}
/* clear transfer complete flag */
@ -1309,9 +1320,11 @@ void ospi_autopolling_mode(uint32_t ospi_periph, ospi_parameter_struct *ospi_str
uint32_t addr_reg = OSPI_ADDR(ospi_periph);
uint32_t ins_reg = OSPI_INS(ospi_periph);
if(autopl_cfg_struct->automatic_stop == OSPI_AUTOMATIC_STOP_MATCH){
if(autopl_cfg_struct->automatic_stop == OSPI_AUTOMATIC_STOP_MATCH)
{
/* wait till busy flag is reset */
while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_BUSY)){
while(RESET != (OSPI_STAT(ospi_periph) & OSPI_FLAG_BUSY))
{
}
/* configure registers */
@ -1322,14 +1335,16 @@ void ospi_autopolling_mode(uint32_t ospi_periph, ospi_parameter_struct *ospi_str
(autopl_cfg_struct->match_mode | autopl_cfg_struct->automatic_stop | OSPI_STATUS_POLLING);
/* trig the transfer by re-writing address or instruction register */
if((OSPI_TCFG(ospi_periph) & OSPI_TCFG_ADDRMOD) != OSPI_ADDRESS_NONE){
if((OSPI_TCFG(ospi_periph) & OSPI_TCFG_ADDRMOD) != OSPI_ADDRESS_NONE)
{
OSPI_ADDR(ospi_periph) = addr_reg;
}else{
OSPI_INS(ospi_periph) = ins_reg;
}
/* wait till status match flag is set to go back in idle state */
while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_SM)){
while(RESET == (OSPI_STAT(ospi_periph) & OSPI_FLAG_SM))
{
}
/* clear status match flag */
@ -1390,12 +1405,14 @@ static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct
/* re-initialize the value of the functional mode */
OSPI_CTL(ospi_periph) &= ~OSPI_CTL_FMOD;
if(cmd_struct->operation_type == OSPI_OPTYPE_WRITE_CFG){
if(cmd_struct->operation_type == OSPI_OPTYPE_WRITE_CFG)
{
tcfg_reg = &(OSPI_WTCFG(ospi_periph));
timcfg_reg = &(OSPI_WTIMCFG(ospi_periph));
ins_reg = &(OSPI_WINS(ospi_periph));
alte_reg = &(OSPI_WALTE(ospi_periph));
}else if(cmd_struct->operation_type == OSPI_OPTYPE_WRAP_CFG){
}else if(cmd_struct->operation_type == OSPI_OPTYPE_WRAP_CFG)
{
tcfg_reg = &(OSPI_WPTCFG(ospi_periph));
timcfg_reg = &(OSPI_WPTIMCFG(ospi_periph));
ins_reg = &(OSPI_WPINS(ospi_periph));
@ -1407,7 +1424,8 @@ static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct
alte_reg = &(OSPI_ALTE(ospi_periph));
}
if(cmd_struct->alter_bytes_mode != OSPI_ALTERNATE_BYTES_NONE){
if(cmd_struct->alter_bytes_mode != OSPI_ALTERNATE_BYTES_NONE)
{
/* configure the ALTE register with alternate bytes value */
*alte_reg = cmd_struct->alter_bytes;
@ -1419,17 +1437,22 @@ static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct
/* configure the TIMCFG register with the number of dummy cycles */
*timcfg_reg = (*timcfg_reg & ~OSPI_TIMCFG_DUMYC) | cmd_struct->dummy_cycles;
if(cmd_struct->data_mode != OSPI_DATA_NONE){
if(cmd_struct->operation_type == OSPI_OPTYPE_COMMON_CFG){
if(cmd_struct->data_mode != OSPI_DATA_NONE)
{
if(cmd_struct->operation_type == OSPI_OPTYPE_COMMON_CFG)
{
/* configure the DTLEN register with the number of data */
OSPI_DTLEN(ospi_periph) = (cmd_struct->nbdata - 1U);
}
}
if(cmd_struct->ins_mode != OSPI_INSTRUCTION_NONE){
if(cmd_struct->addr_mode != OSPI_ADDRESS_NONE){
if(cmd_struct->data_mode != OSPI_DATA_NONE){
if(cmd_struct->ins_mode != OSPI_INSTRUCTION_NONE)
{
if(cmd_struct->addr_mode != OSPI_ADDRESS_NONE)
{
if(cmd_struct->data_mode != OSPI_DATA_NONE)
{
/* command with instruction, address and data */
/* configure the TCFG register with all communication parameters */
*tcfg_reg &= ~(OSPI_TCFG_IMOD | OSPI_TCFG_INSSZ |
@ -1449,7 +1472,8 @@ static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct
cmd_struct->addr_mode | cmd_struct->addr_dtr_mode | cmd_struct->addr_size;
/* the DHQC bit is linked with DDTR bit which should be activated */
if((ospi_struct->delay_hold_cycle == OSPI_DELAY_HOLD_QUARTER_CYCLE) ){
if((ospi_struct->delay_hold_cycle == OSPI_DELAY_HOLD_QUARTER_CYCLE) )
{
*tcfg_reg = (*tcfg_reg & ~OSPI_DADTR_MODE_ENABLE) | OSPI_DADTR_MODE_ENABLE;
}
}
@ -1460,7 +1484,8 @@ static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct
/* configure the ADDR register with the address value */
OSPI_ADDR(ospi_periph) = cmd_struct->address;
}else{
if(cmd_struct->data_mode != OSPI_DATA_NONE){
if(cmd_struct->data_mode != OSPI_DATA_NONE)
{
/* command with instruction and data */
/* configure the TCFG register with all communication parameters */
*tcfg_reg &= ~(OSPI_TCFG_IMOD | OSPI_TCFG_INSSZ |
@ -1476,7 +1501,8 @@ static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct
*tcfg_reg = cmd_struct->ins_mode | cmd_struct->ins_size;
/* the DEHQC bit is linked with DDTR bit which should be activated */
if((ospi_struct->delay_hold_cycle == OSPI_DELAY_HOLD_QUARTER_CYCLE)){
if((ospi_struct->delay_hold_cycle == OSPI_DELAY_HOLD_QUARTER_CYCLE))
{
*tcfg_reg = (*tcfg_reg & ~OSPI_DADTR_MODE_ENABLE) | OSPI_DADTR_MODE_ENABLE;
}
}
@ -1485,8 +1511,10 @@ static void ospi_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct
*ins_reg = cmd_struct->instruction;
}
}else{
if(cmd_struct->addr_mode != OSPI_ADDRESS_NONE){
if(cmd_struct->data_mode != OSPI_DATA_NONE){
if(cmd_struct->addr_mode != OSPI_ADDRESS_NONE)
{
if(cmd_struct->data_mode != OSPI_DATA_NONE)
{
/* command with address and data */
/* configure the TCFG register with all communication parameters */
@ -1573,7 +1601,8 @@ uint32_t ospi_fifo_level_get(uint32_t ospi_periph)
*/
FlagStatus ospi_flag_get(uint32_t ospi_periph, uint32_t flag)
{
if(RESET != (OSPI_STAT(ospi_periph) & flag)){
if(RESET != (OSPI_STAT(ospi_periph) & flag))
{
return SET;
}else{
return RESET;
@ -1617,7 +1646,8 @@ FlagStatus ospi_interrupt_flag_get(uint32_t ospi_periph, uint32_t int_flag)
ret1 = (OSPI_REG_VAL(ospi_periph, int_flag) & BIT(OSPI_BIT_POS(int_flag)));
/* get the status of interrupt flag */
ret2 = (OSPI_REG_VAL2(ospi_periph, int_flag) & BIT(OSPI_BIT_POS2(int_flag)));
if(ret1 && ret2) {
if(ret1 && ret2)
{
return SET;
} else {
return RESET;

27
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_pmu.c
View File

@ -333,15 +333,18 @@ void pmu_smps_ldo_supply_config(uint32_t smpsmode)
temp |= smpsmode;
PMU_CTL2 = temp;
while(0U == (PMU_CTL3 & PMU_CTL3_VOVRF)) {
while(0U == (PMU_CTL3 & PMU_CTL3_VOVRF))
{
}
/* When the SMPS supplies external circuits verify that DVSRF flag is set */
if((smpsmode == PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||
(smpsmode == PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||
(smpsmode == PMU_SMPS_1V8_SUPPLIES_EXT) ||
(smpsmode == PMU_SMPS_2V5_SUPPLIES_EXT)) {
while(0U == (PMU_CTL2 & PMU_CTL2_DVSRF)) {
(smpsmode == PMU_SMPS_2V5_SUPPLIES_EXT))
{
while(0U == (PMU_CTL2 & PMU_CTL2_DVSRF))
{
}
}
}
@ -361,7 +364,8 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd)
SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
/* select WFI or WFE command to enter sleep mode */
if(WFI_CMD == sleepmodecmd) {
if(WFI_CMD == sleepmodecmd)
{
__WFI();
} else {
__WFE();
@ -387,7 +391,8 @@ void pmu_to_deepsleepmode(uint8_t deepsleepmodecmd)
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* select WFI or WFE command to enter deepsleep mode */
if(WFI_CMD == deepsleepmodecmd) {
if(WFI_CMD == deepsleepmodecmd)
{
__WFI();
} else {
__SEV();
@ -490,7 +495,8 @@ void pmu_backup_write_disable(void)
void pmu_backup_voltage_stabilizer_enable(void)
{
PMU_CTL1 |= PMU_CTL1_BKPVSEN;
while(RESET == (PMU_CTL1 & PMU_CTL1_BKPVSRF)) {
while(RESET == (PMU_CTL1 & PMU_CTL1_BKPVSRF))
{
}
}
@ -556,7 +562,8 @@ void pmu_exit_deepsleep_wait_time_config(uint32_t wait_time)
*/
FlagStatus pmu_flag_get(uint32_t flag)
{
if(PMU_REG_VAL(flag) & BIT(PMU_BIT_POS(flag))) {
if(PMU_REG_VAL(flag) & BIT(PMU_BIT_POS(flag)))
{
return SET;
} else {
return RESET;
@ -573,10 +580,12 @@ FlagStatus pmu_flag_get(uint32_t flag)
*/
void pmu_flag_clear(uint32_t flag_reset)
{
if(PMU_FLAG_WAKEUP == flag_reset) {
if(PMU_FLAG_WAKEUP == flag_reset)
{
PMU_CTL0 |= PMU_CTL0_WURST;
} else {
if(PMU_FLAG_STANDBY == flag_reset) {
if(PMU_FLAG_STANDBY == flag_reset)
{
PMU_CTL0 |= PMU_CTL0_STBRST;
}
}

9
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_rameccmu.c
View File

@ -45,7 +45,8 @@ OF SUCH DAMAGE.
void rameccmu_deinit(uint32_t rameccmu_periph)
{
RAMECCMU_INT(rameccmu_periph) = RAMECCMU_REG_RESET_VALUE;
if(RAMECCMU0 == rameccmu_periph){
if(RAMECCMU0 == rameccmu_periph)
{
/* reset RAMECCMU0_MONITOR0 registers */
RAMECCMU_MXCTL(RAMECCMU0_MONITOR0) = RAMECCMU_REG_RESET_VALUE;
RAMECCMU_MXSTAT(RAMECCMU0_MONITOR0) = RAMECCMU_REG_RESET_VALUE;
@ -300,7 +301,8 @@ void rameccmu_monitor_interrupt_disable(rameccmu_monitor_enum rameccmu_monitor,
*/
FlagStatus rameccmu_monitor_flag_get(rameccmu_monitor_enum rameccmu_monitor, uint32_t flag)
{
if(RESET != ((RAMECCMU_MXSTAT(rameccmu_monitor)) & flag)){
if(RESET != ((RAMECCMU_MXSTAT(rameccmu_monitor)) & flag))
{
return SET;
}else{
return RESET;
@ -362,7 +364,8 @@ FlagStatus rameccmu_monitor_interrupt_flag_get(rameccmu_monitor_enum rameccmu_mo
/* get the status of interrupt flag */
ret2 = RAMECCMU_MXSTAT(rameccmu_monitor) & int_flag;
if(ret1 && ret2) {
if(ret1 && ret2)
{
return SET;
} else {
return RESET;

363
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_rcu.c
View File

@ -66,7 +66,8 @@ void rcu_deinit(void)
{
/* enable IRC64M */
RCU_CTL |= RCU_CTL_IRC64MEN;
while(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)){
while(0U == (RCU_CTL & RCU_CTL_IRC64MSTB))
{
}
RCU_CFG0 &= ~RCU_CFG0_SCS;
@ -709,7 +710,8 @@ void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div)
*/
void rcu_pll_input_output_clock_range_config(pll_idx_enum pll_idx, uint32_t ck_input, uint32_t ck_output)
{
switch(pll_idx) {
switch(pll_idx)
{
case IDX_PLL0:
/* reset the PLLRNG/PLLVCOSEL bits and set according to ck_input/ck_output */
RCU_PLLALL &= ~(RCU_PLLALL_PLL0RNG | RCU_PLLALL_PLL0VCOSEL);
@ -740,7 +742,8 @@ void rcu_pll_input_output_clock_range_config(pll_idx_enum pll_idx, uint32_t ck_i
*/
void rcu_pll_fractional_config(pll_idx_enum pll_idx, uint32_t pll_fracn)
{
switch(pll_idx) {
switch(pll_idx)
{
case IDX_PLL0:
/* reset the PLLFRAN and set according to pll_fracn */
RCU_PLL0FRA &= ~(RCU_PLL0FRA_PLL0FRAN);
@ -769,7 +772,8 @@ void rcu_pll_fractional_config(pll_idx_enum pll_idx, uint32_t pll_fracn)
*/
void rcu_pll_fractional_latch_enable(pll_idx_enum pll_idx)
{
switch(pll_idx) {
switch(pll_idx)
{
case IDX_PLL0:
/* set the PLL0FRAEN */
RCU_PLL0FRA |= RCU_PLL0FRA_PLL0FRAEN ;
@ -795,7 +799,8 @@ void rcu_pll_fractional_latch_enable(pll_idx_enum pll_idx)
*/
void rcu_pll_fractional_latch_disable(pll_idx_enum pll_idx)
{
switch(pll_idx) {
switch(pll_idx)
{
case IDX_PLL0:
/* reset the PLL0FRAEN */
RCU_PLL0FRA &= ~RCU_PLL0FRA_PLL0FRAEN ;
@ -849,7 +854,8 @@ ErrStatus rcu_pll0_config(uint32_t pll0_psc, uint32_t pll0_n, uint32_t pll0_p, u
/* check the function parameter */
if(CHECK_PLL0_PSC_VALID(pll0_psc) && CHECK_PLL0_N_VALID(pll0_n) &&
CHECK_PLL0_P_VALID(pll0_p) && CHECK_PLL0_Q_VALID(pll0_q) &&
CHECK_PLL0_R_VALID(pll0_r)) {
CHECK_PLL0_R_VALID(pll0_r))
{
RCU_PLL0 &= ~(RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0N | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R);
RCU_PLL0 |= pll0_psc | ((pll0_n - 1U) << RCU_PLLNOFFSET) | ((pll0_p - 1U) << RCU_PLLPOFFSET) |
((pll0_r - 1U) << RCU_PLLROFFSET);
@ -885,7 +891,8 @@ ErrStatus rcu_pll1_config(uint32_t pll1_psc, uint32_t pll1_n, uint32_t pll1_p, u
/* check the function parameter */
if(CHECK_PLL1_PSC_VALID(pll1_psc) && CHECK_PLL1_N_VALID(pll1_n) &&
CHECK_PLL1_P_VALID(pll1_p) && CHECK_PLL1_Q_VALID(pll1_q) &&
CHECK_PLL1_R_VALID(pll1_r)) {
CHECK_PLL1_R_VALID(pll1_r))
{
RCU_PLL1 = (pll1_psc | ((pll1_n - 1U) << RCU_PLLNOFFSET) | ((pll1_p - 1U) << RCU_PLLPOFFSET) |
((pll1_r - 1U) << RCU_PLLROFFSET));
RCU_PLLADDCTL &= ~RCU_PLLADDCTL_PLL1Q;
@ -920,7 +927,8 @@ ErrStatus rcu_pll2_config(uint32_t pll2_psc, uint32_t pll2_n, uint32_t pll2_p, u
/* check the function parameter */
if(CHECK_PLL2_PSC_VALID(pll2_psc) && CHECK_PLL2_N_VALID(pll2_n) &&
CHECK_PLL2_P_VALID(pll2_p) && CHECK_PLL2_R_VALID(pll2_q) &&
CHECK_PLL2_R_VALID(pll2_r)) {
CHECK_PLL2_R_VALID(pll2_r))
{
RCU_PLL2 = (pll2_psc | ((pll2_n - 1U) << RCU_PLLNOFFSET) | ((pll2_p - 1U) << RCU_PLLPOFFSET) |
((pll2_r - 1U) << RCU_PLLROFFSET));
RCU_PLLADDCTL &= ~RCU_PLLADDCTL_PLL2Q;
@ -1133,13 +1141,17 @@ uint32_t rcu_irc64mdiv_freq_get(void)
uint32_t irc64m_freq = 0U;
/* CK_IRC64MDIV = CK_IRC64M/1/2/4/8 */
if(RCU_IRC64M_DIV1 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV)) {
if(RCU_IRC64M_DIV1 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV))
{
irc64m_freq = IRC64M_VALUE;
} else if(RCU_IRC64M_DIV2 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV)) {
} else if(RCU_IRC64M_DIV2 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV))
{
irc64m_freq = IRC64M_VALUE / 2U;
} else if(RCU_IRC64M_DIV4 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV)) {
} else if(RCU_IRC64M_DIV4 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV))
{
irc64m_freq = IRC64M_VALUE / 4U;
} else if(RCU_IRC64M_DIV8 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV)) {
} else if(RCU_IRC64M_DIV8 == (RCU_ADDCTL1 & RCU_ADDCTL1_IRC64MDIV))
{
irc64m_freq = IRC64M_VALUE / 8U;
} else {
}
@ -1165,7 +1177,8 @@ uint32_t rcu_irc64mdiv_freq_get(void)
void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler)
{
/* configure the TIMERSEL bit and select the TIMER clock prescaler */
if(timer_clock_prescaler == RCU_TIMER_PSC_MUL2) {
if(timer_clock_prescaler == RCU_TIMER_PSC_MUL2)
{
RCU_CFG1 &= timer_clock_prescaler;
} else {
RCU_CFG1 |= timer_clock_prescaler;
@ -1196,7 +1209,8 @@ void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler)
*/
void rcu_spi_clock_config(spi_idx_enum spi_idx, uint32_t ck_spi)
{
switch(spi_idx) {
switch(spi_idx)
{
case IDX_SPI0:
/* reset the SPI0SEL bits and set according to ck_spi */
RCU_CFG5 &= ~RCU_CFG5_SPI0SEL;
@ -1246,7 +1260,8 @@ void rcu_spi_clock_config(spi_idx_enum spi_idx, uint32_t ck_spi)
*/
void rcu_sdio_clock_config(sdio_idx_enum sdio_idx, uint32_t ck_sdio)
{
switch(sdio_idx) {
switch(sdio_idx)
{
case IDX_SDIO0:
/* reset the SDIO0SEL bits and set according to ck_sdio */
RCU_CFG4 &= ~RCU_CFG4_SDIO0SEL;
@ -1310,7 +1325,8 @@ void rcu_tli_clock_div_config(uint32_t pll2_r_div)
*/
void rcu_usart_clock_config(usart_idx_enum usart_idx, uint32_t ck_usart)
{
switch(usart_idx) {
switch(usart_idx)
{
case IDX_USART0:
/* reset the USART0SEL bits and set according to ck_usart */
RCU_CFG1 &= ~RCU_CFG1_USART0SEL;
@ -1350,7 +1366,8 @@ void rcu_usart_clock_config(usart_idx_enum usart_idx, uint32_t ck_usart)
*/
void rcu_i2c_clock_config(i2c_idx_enum i2c_idx, uint32_t ck_i2c)
{
switch(i2c_idx) {
switch(i2c_idx)
{
case IDX_I2C0:
/* reset the I2C0SEL bits and set according to ck_i2c */
RCU_CFG0 &= ~RCU_CFG0_I2C0SEL;
@ -1390,7 +1407,8 @@ void rcu_i2c_clock_config(i2c_idx_enum i2c_idx, uint32_t ck_i2c)
*/
void rcu_can_clock_config(can_idx_enum can_idx, uint32_t ck_can)
{
switch(can_idx) {
switch(can_idx)
{
case IDX_CAN0:
/* reset the CAN0SEL bits and set according to ck_can */
RCU_CFG1 &= ~RCU_CFG1_CAN0SEL;
@ -1424,7 +1442,8 @@ void rcu_can_clock_config(can_idx_enum can_idx, uint32_t ck_can)
*/
void rcu_adc_clock_config(adc_idx_enum adc_idx, uint32_t ck_adc)
{
switch(adc_idx) {
switch(adc_idx)
{
case IDX_ADC0:
case IDX_ADC1:
/* reset the ADC0SEL/ADC1SEL bits and set according to ck_adc */
@ -1456,7 +1475,8 @@ void rcu_adc_clock_config(adc_idx_enum adc_idx, uint32_t ck_adc)
*/
void rcu_sai_clock_config(sai_idx_enum sai_idx, uint32_t ck_sai)
{
switch(sai_idx) {
switch(sai_idx)
{
case IDX_SAI0:
/* reset the SAI0SEL bits and set according to ck_sai */
RCU_CFG2 &= ~RCU_CFG2_SAI0SEL;
@ -1488,7 +1508,8 @@ void rcu_sai_clock_config(sai_idx_enum sai_idx, uint32_t ck_sai)
*/
void rcu_sai2_block_clock_config(sai2b_idx_enum sai2b_idx, uint32_t ck_sai2b)
{
switch(sai2b_idx) {
switch(sai2b_idx)
{
case IDX_SAI2B0:
/* reset the SAI2B0SEL bits and set according to ck_sai2b */
RCU_CFG2 &= ~RCU_CFG2_SAI2B0SEL;
@ -1591,7 +1612,8 @@ void rcu_per_clock_config(uint32_t ck_per)
*/
void rcu_usbhs_pll1qpsc_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usbhspsc)
{
switch(usbhs_idx) {
switch(usbhs_idx)
{
case IDX_USBHS0:
/* reset the USBHS0PSC bits and set according to ck_usbhspsc */
RCU_USBCLKCTL &= ~RCU_USBCLKCTL_USBHS0PSC;
@ -1621,7 +1643,8 @@ void rcu_usbhs_pll1qpsc_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usbhspsc)
*/
void rcu_usb48m_clock_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usb48m)
{
switch(usbhs_idx) {
switch(usbhs_idx)
{
case IDX_USBHS0:
/* reset the USB048MSEL bits and set according to ck_usb48m */
RCU_USBCLKCTL &= ~RCU_USBCLKCTL_USBHS048MSEL;
@ -1649,7 +1672,8 @@ void rcu_usb48m_clock_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usb48m)
*/
void rcu_usbhs_clock_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usbhs)
{
switch(usbhs_idx) {
switch(usbhs_idx)
{
case IDX_USBHS0:
/* reset the USBHS0SEL bits and set according to ck_usbhs */
RCU_USBCLKCTL &= ~RCU_USBCLKCTL_USBHS0SEL;
@ -1673,7 +1697,8 @@ void rcu_usbhs_clock_config(usbhs_idx_enum usbhs_idx, uint32_t ck_usbhs)
*/
void rcu_usbhs_clock_selection_enable(usbhs_idx_enum usbhs_idx)
{
switch(usbhs_idx) {
switch(usbhs_idx)
{
case IDX_USBHS0:
/* set the USB0SWEN bit */
RCU_USBCLKCTL |= RCU_USBCLKCTL_USBHS0SWEN;
@ -1695,7 +1720,8 @@ void rcu_usbhs_clock_selection_enable(usbhs_idx_enum usbhs_idx)
*/
void rcu_usbhs_clock_selection_disable(usbhs_idx_enum usbhs_idx)
{
switch(usbhs_idx) {
switch(usbhs_idx)
{
case IDX_USBHS0:
/* reset the USB0SWEN bit */
RCU_USBCLKCTL &= ~RCU_USBCLKCTL_USBHS0SWEN;
@ -1755,136 +1781,159 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
ErrStatus reval = ERROR;
FlagStatus osci_stat = RESET;
switch(osci) {
switch(osci)
{
/* wait HXTAL stable */
case RCU_HXTAL:
while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) {
while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
stb_cnt++;
}
/* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) {
if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB))
{
reval = SUCCESS;
}
break;
/* wait LXTAL stable */
case RCU_LXTAL:
while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) {
while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
stb_cnt++;
}
/* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) {
if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB))
{
reval = SUCCESS;
}
break;
/* wait IRC64M stable */
case RCU_IRC64M:
while((RESET == osci_stat) && (IRC64M_STARTUP_TIMEOUT != stb_cnt)) {
while((RESET == osci_stat) && (IRC64M_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_IRC64MSTB);
stb_cnt++;
}
/* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_IRC64MSTB)) {
if(RESET != rcu_flag_get(RCU_FLAG_IRC64MSTB))
{
reval = SUCCESS;
}
break;
/* wait IRC48M stable */
case RCU_IRC48M:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB);
stb_cnt++;
}
/* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)) {
if(RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB))
{
reval = SUCCESS;
}
break;
/* wait IRC32K stable */
case RCU_IRC32K:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_IRC32KSTB);
stb_cnt++;
}
/* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_IRC32KSTB)) {
if(RESET != rcu_flag_get(RCU_FLAG_IRC32KSTB))
{
reval = SUCCESS;
}
break;
/* wait LPIRC4M stable */
case RCU_LPIRC4M:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_LPIRC4MSTB);
stb_cnt++;
}
/* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_LPIRC4MSTB)) {
if(RESET != rcu_flag_get(RCU_FLAG_LPIRC4MSTB))
{
reval = SUCCESS;
}
break;
/* wait PLL0 stable */
case RCU_PLL0_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_PLL0STB);
stb_cnt++;
}
/* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_PLL0STB)) {
if(RESET != rcu_flag_get(RCU_FLAG_PLL0STB))
{
reval = SUCCESS;
}
break;
/* wait PLL1 stable */
case RCU_PLL1_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB);
stb_cnt++;
}
/* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)) {
if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB))
{
reval = SUCCESS;
}
break;
/* wait PLL2 stable */
case RCU_PLL2_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB);
stb_cnt++;
}
/* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)) {
if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB))
{
reval = SUCCESS;
}
break;
/* wait PLLUSBHS0 stable */
case RCU_PLLUSBHS0_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_PLLUSBHS0STB);
stb_cnt++;
}
/* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_PLLUSBHS0STB)) {
if(RESET != rcu_flag_get(RCU_FLAG_PLLUSBHS0STB))
{
reval = SUCCESS;
}
break;
/* wait PLLUSBHS1 stable */
case RCU_PLLUSBHS1_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt))
{
osci_stat = rcu_flag_get(RCU_FLAG_PLLUSBHS1STB);
stb_cnt++;
}
/* check whether flag is set */
if(RESET != rcu_flag_get(RCU_FLAG_PLLUSBHS1STB)) {
if(RESET != rcu_flag_get(RCU_FLAG_PLLUSBHS1STB))
{
reval = SUCCESS;
}
break;
@ -1955,7 +2004,8 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
{
uint32_t reg;
switch(osci) {
switch(osci)
{
/* enable HXTAL to bypass mode */
case RCU_HXTAL:
reg = RCU_CTL;
@ -1986,7 +2036,8 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
{
uint32_t reg;
switch(osci) {
switch(osci)
{
/* disable HXTAL to bypass mode */
case RCU_HXTAL:
reg = RCU_CTL;
@ -2157,7 +2208,8 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
irc64mdiv_freq = rcu_irc64mdiv_freq_get();
sws = GET_BITS(RCU_CFG0, 2, 3);
switch(sws) {
switch(sws)
{
/* IRC64MDIV is selected as CK_SYS */
case SEL_IRC64MDIV:
cksys_freq = irc64mdiv_freq;
@ -2177,16 +2229,19 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll0n = (GET_BITS(RCU_PLL0, 6U, 14U) + 1U);
pll0p = (GET_BITS(RCU_PLL0, 16U, 22U) + 1U);
if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U) {
if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL0FRA, 0U, 12U);
}
/* PLL clock source selection, HXTAL or IRC64MDIV */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) {
if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) {
} else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq;
} else {
ck_src = LPIRC4M_VALUE;
@ -2226,7 +2281,8 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
apb4_freq = ahb_freq >> clk_exp;
/* return the clocks frequency */
switch(clock) {
switch(clock)
{
case CK_SYS:
ck_freq = cksys_freq;
break;
@ -2252,23 +2308,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll0n = (GET_BITS(RCU_PLL0, 6U, 14U) + 1U);
pll0p = (GET_BITS(RCU_PLL0, 16U, 22U) + 1U);
if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U) {
if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL0FRA, 0U, 12U);
}
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) {
if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) {
} else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq;
} else {
ck_src = LPIRC4M_VALUE;
}
if((pll0psc != 0U) && (ck_src != 0U)) {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL0PEN) != 0U) {
if((pll0psc != 0U) && (ck_src != 0U))
{
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL0PEN) != 0U)
{
pll0p_freq = rcu_pll_clock_freq_cal(ck_src, pll0psc, pll0n, fracn, pll0p);
}
}
@ -2282,23 +2343,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll0n = (GET_BITS(RCU_PLL0, 6U, 14U) + 1U);
pll0r = (GET_BITS(RCU_PLL0, 24U, 30U) + 1U);
if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U) {
if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL0FRA, 0U, 12U);
}
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) {
if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) {
} else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq;
} else {
ck_src = LPIRC4M_VALUE;
}
if((pll0psc != 0U) && (ck_src != 0U)) {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL0REN) != 0U) {
if((pll0psc != 0U) && (ck_src != 0U))
{
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL0REN) != 0U)
{
pll0r_freq = rcu_pll_clock_freq_cal(ck_src, pll0psc, pll0n, fracn, pll0r);
}
}
@ -2312,23 +2378,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll0n = (GET_BITS(RCU_PLL0, 6U, 14U) + 1U);
pll0q = (GET_BITS(RCU_PLLADDCTL, 0U, 6U) + 1U);
if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U) {
if((RCU_PLL0FRA & RCU_PLL0FRA_PLL0FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL0FRA, 0U, 12U);
}
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) {
if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) {
} else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq;
} else {
ck_src = LPIRC4M_VALUE;
}
if((pll0psc != 0U) && (ck_src != 0U)) {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL0QEN) != 0U) {
if((pll0psc != 0U) && (ck_src != 0U))
{
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL0QEN) != 0U)
{
pll0q_freq = rcu_pll_clock_freq_cal(ck_src, pll0psc, pll0n, fracn, pll0q);
}
}
@ -2342,23 +2413,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll1n = (GET_BITS(RCU_PLL1, 6U, 14U) + 1U);
pll1p = (GET_BITS(RCU_PLL1, 16U, 22U) + 1U);
if((RCU_PLL1FRA & RCU_PLL1FRA_PLL1FRAEN) != 0U) {
if((RCU_PLL1FRA & RCU_PLL1FRA_PLL1FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL1FRA, 0U, 12U);
}
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) {
if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) {
} else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq;
} else {
ck_src = LPIRC4M_VALUE;
}
if((pll1psc != 0U) && (ck_src != 0U)) {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL1PEN) != 0U) {
if((pll1psc != 0U) && (ck_src != 0U))
{
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL1PEN) != 0U)
{
pll1p_freq = rcu_pll_clock_freq_cal(ck_src, pll1psc, pll1n, fracn, pll1p);
}
}
@ -2372,23 +2448,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll1n = (GET_BITS(RCU_PLL1, 6U, 14U) + 1U);
pll1r = (GET_BITS(RCU_PLL1, 24U, 30U) + 1U);
if((RCU_PLL1FRA & RCU_PLL1FRA_PLL1FRAEN) != 0U) {
if((RCU_PLL1FRA & RCU_PLL1FRA_PLL1FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL1FRA, 0U, 12U);
}
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) {
if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) {
} else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq;
} else {
ck_src = LPIRC4M_VALUE;
}
if((pll1psc != 0U) && (ck_src != 0U)) {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL1REN) != 0U) {
if((pll1psc != 0U) && (ck_src != 0U))
{
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL1REN) != 0U)
{
pll1r_freq = rcu_pll_clock_freq_cal(ck_src, pll1psc, pll1n, fracn, pll1r);
}
}
@ -2402,23 +2483,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll1n = (GET_BITS(RCU_PLL1, 6U, 14U) + 1U);
pll1q = (GET_BITS(RCU_PLLADDCTL, 8U, 14U) + 1U);
if((RCU_PLL1FRA & RCU_PLL1FRA_PLL1FRAEN) != 0U) {
if((RCU_PLL1FRA & RCU_PLL1FRA_PLL1FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL1FRA, 0U, 12U);
}
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) {
if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) {
} else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq;
} else {
ck_src = LPIRC4M_VALUE;
}
if((pll1psc != 0U) && (ck_src != 0U)) {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL1QEN) != 0U) {
if((pll1psc != 0U) && (ck_src != 0U))
{
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL1QEN) != 0U)
{
pll1q_freq = rcu_pll_clock_freq_cal(ck_src, pll1psc, pll1n, fracn, pll1q);
}
}
@ -2432,23 +2518,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll2n = (GET_BITS(RCU_PLL2, 6U, 14U) + 1U);
pll2p = (GET_BITS(RCU_PLL2, 16U, 22U) + 1U);
if((RCU_PLL2FRA & RCU_PLL2FRA_PLL2FRAEN) != 0U) {
if((RCU_PLL2FRA & RCU_PLL2FRA_PLL2FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL2FRA, 0U, 12U);
}
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) {
if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) {
} else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq;
} else {
ck_src = LPIRC4M_VALUE;
}
if((pll2psc != 0U) && (ck_src != 0U)) {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL2PEN) != 0U) {
if((pll2psc != 0U) && (ck_src != 0U))
{
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL2PEN) != 0U)
{
pll2p_freq = rcu_pll_clock_freq_cal(ck_src, pll2psc, pll2n, fracn, pll2p);
}
}
@ -2462,23 +2553,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll2n = (GET_BITS(RCU_PLL2, 6U, 14U) + 1U);
pll2r = (GET_BITS(RCU_PLL2, 24U, 30U) + 1U);
if((RCU_PLL2FRA & RCU_PLL2FRA_PLL2FRAEN) != 0U) {
if((RCU_PLL2FRA & RCU_PLL2FRA_PLL2FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL2FRA, 0U, 12U);
}
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) {
if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) {
} else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq;
} else {
ck_src = LPIRC4M_VALUE;
}
if((pll2psc != 0U) && (ck_src != 0U)) {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL2REN) != 0U) {
if((pll2psc != 0U) && (ck_src != 0U))
{
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL2REN) != 0U)
{
pll2r_freq = rcu_pll_clock_freq_cal(ck_src, pll2psc, pll2n, fracn, pll2r);
}
}
@ -2492,23 +2588,28 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
pll2n = (GET_BITS(RCU_PLL2, 6U, 14U) + 1U);
pll2q = (GET_BITS(RCU_PLLADDCTL, 16U, 22U) + 1U);
if((RCU_PLL2FRA & RCU_PLL2FRA_PLL2FRAEN) != 0U) {
if((RCU_PLL2FRA & RCU_PLL2FRA_PLL2FRAEN) != 0U)
{
fracn = GET_BITS(RCU_PLL2FRA, 0U, 12U);
}
/* PLL clock source selection (HXTAL, IRC64MDIV or LPIRC4M) */
pllsel = (RCU_PLLALL & RCU_PLLALL_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) {
if(RCU_PLLSRC_HXTAL == pllsel)
{
ck_src = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == pllsel) {
} else if(RCU_PLLSRC_IRC64MDIV == pllsel)
{
ck_src = irc64mdiv_freq;
} else {
ck_src = LPIRC4M_VALUE;
}
if((pll2psc != 0U) && (ck_src != 0U)) {
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL2QEN) != 0U) {
if((pll2psc != 0U) && (ck_src != 0U))
{
if((RCU_PLLADDCTL & RCU_PLLADDCTL_PLL2QEN) != 0U)
{
pll2q_freq = rcu_pll_clock_freq_cal(ck_src, pll2psc, pll2n, fracn, pll2q);
}
}
@ -2519,9 +2620,11 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
/* calculate peripheral clock frequency */
persel = (RCU_CFG1 & RCU_CFG1_PERSEL);
if(RCU_PERSRC_HXTAL == persel) {
if(RCU_PERSRC_HXTAL == persel)
{
per_freq = HXTAL_VALUE;
} else if(RCU_PLLSRC_IRC64MDIV == persel) {
} else if(RCU_PLLSRC_IRC64MDIV == persel)
{
per_freq = irc64mdiv_freq;
} else {
per_freq = LPIRC4M_VALUE;
@ -2531,13 +2634,17 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
break;
case CK_USART0:
/* calculate USART0 clock frequency */
if(RCU_USARTSRC_APB == (RCU_CFG1 & RCU_CFG1_USART0SEL)) {
if(RCU_USARTSRC_APB == (RCU_CFG1 & RCU_CFG1_USART0SEL))
{
usart_freq = apb2_freq;
} else if(RCU_USARTSRC_AHB == (RCU_CFG1 & RCU_CFG1_USART0SEL)) {
} else if(RCU_USARTSRC_AHB == (RCU_CFG1 & RCU_CFG1_USART0SEL))
{
usart_freq = ahb_freq;
} else if(RCU_USARTSRC_LXTAL == (RCU_CFG1 & RCU_CFG1_USART0SEL)) {
} else if(RCU_USARTSRC_LXTAL == (RCU_CFG1 & RCU_CFG1_USART0SEL))
{
usart_freq = LXTAL_VALUE;
} else if(RCU_USARTSRC_IRC64MDIV == (RCU_CFG1 & RCU_CFG1_USART0SEL)) {
} else if(RCU_USARTSRC_IRC64MDIV == (RCU_CFG1 & RCU_CFG1_USART0SEL))
{
usart_freq = irc64mdiv_freq;
} else {
}
@ -2546,13 +2653,17 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
break;
case CK_USART1:
/* calculate USART1 clock frequency */
if((RCU_USARTSRC_APB << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL)) {
if((RCU_USARTSRC_APB << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL))
{
usart_freq = apb1_freq;
} else if((RCU_USARTSRC_AHB << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL)) {
} else if((RCU_USARTSRC_AHB << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL))
{
usart_freq = ahb_freq;
} else if((RCU_USARTSRC_LXTAL << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL)) {
} else if((RCU_USARTSRC_LXTAL << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL))
{
usart_freq = LXTAL_VALUE;
} else if((RCU_USARTSRC_IRC64MDIV << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL)) {
} else if((RCU_USARTSRC_IRC64MDIV << 18U) == (RCU_CFG1 & RCU_CFG1_USART1SEL))
{
usart_freq = irc64mdiv_freq;
} else {
}
@ -2561,13 +2672,17 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
break;
case CK_USART2:
/* calculate USART2 clock frequency */
if((RCU_USARTSRC_APB << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL)) {
if((RCU_USARTSRC_APB << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL))
{
usart_freq = apb1_freq;
} else if((RCU_USARTSRC_AHB << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL)) {
} else if((RCU_USARTSRC_AHB << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL))
{
usart_freq = ahb_freq;
} else if((RCU_USARTSRC_LXTAL << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL)) {
} else if((RCU_USARTSRC_LXTAL << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL))
{
usart_freq = LXTAL_VALUE;
} else if((RCU_USARTSRC_IRC64MDIV << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL)) {
} else if((RCU_USARTSRC_IRC64MDIV << 20U) == (RCU_CFG1 & RCU_CFG1_USART2SEL))
{
usart_freq = irc64mdiv_freq;
} else {
}
@ -2576,13 +2691,17 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
break;
case CK_USART5:
/* calculate USART5 clock frequency */
if((RCU_USARTSRC_APB << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL)) {
if((RCU_USARTSRC_APB << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL))
{
usart_freq = apb2_freq;
} else if((RCU_USARTSRC_AHB << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL)) {
} else if((RCU_USARTSRC_AHB << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL))
{
usart_freq = ahb_freq;
} else if((RCU_USARTSRC_LXTAL << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL)) {
} else if((RCU_USARTSRC_LXTAL << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL))
{
usart_freq = LXTAL_VALUE;
} else if((RCU_USARTSRC_IRC64MDIV << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL)) {
} else if((RCU_USARTSRC_IRC64MDIV << 22U) == (RCU_CFG1 & RCU_CFG1_USART5SEL))
{
usart_freq = irc64mdiv_freq;
} else {
}
@ -2634,7 +2753,8 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
FlagStatus rcu_flag_get(rcu_flag_enum flag)
{
/* get the rcu flag */
if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) {
if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag))))
{
return SET;
} else {
return RESET;
@ -2722,7 +2842,8 @@ void rcu_interrupt_disable(rcu_int_enum interrupt)
FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
{
/* get the rcu interrupt flag */
if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) {
if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag))))
{
return SET;
} else {
return RESET;

15
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_rspdif.c
View File

@ -281,7 +281,8 @@ void rspdif_data_read(rspdif_data_struct *data_struct)
/* get data format */
data_struct->format = RSPDIF_CTL & RSPDIF_CTL_RXDF;
switch(data_struct->format) {
switch(data_struct->format)
{
/* data format 0 */
case RSPDIF_DATAFORMAT_LSB:
/* the preamble type */
@ -379,7 +380,8 @@ uint32_t rspdif_channel_status_get(void)
*/
FlagStatus rspdif_start_block_status_get(void)
{
if(RESET != (RSPDIF_CHSTAT & RSPDIF_CHSTAT_SOB)) {
if(RESET != (RSPDIF_CHSTAT & RSPDIF_CHSTAT_SOB))
{
return SET;
} else {
return RESET;
@ -426,7 +428,8 @@ uint32_t rspdif_high_threshold_get(void)
*/
FlagStatus rspdif_flag_get(uint16_t flag)
{
if(RESET != (RSPDIF_STAT & flag)) {
if(RESET != (RSPDIF_STAT & flag))
{
return SET;
} else {
return RESET;
@ -508,7 +511,8 @@ FlagStatus rspdif_interrupt_flag_get(uint16_t int_flag)
uint32_t reg1 = RSPDIF_STAT;
uint32_t reg2 = RSPDIF_INTEN;
switch(int_flag) {
switch(int_flag)
{
/* RSPDIF RX buffer is not empty interrupt */
case RSPDIF_INT_FLAG_RBNE:
reg1 = reg1 & RSPDIF_STAT_RBNE;
@ -558,7 +562,8 @@ FlagStatus rspdif_interrupt_flag_get(uint16_t int_flag)
break;
}
/*get RSPDIF interrupt flag status */
if((0U != reg1) && (0U != reg2)) {
if((0U != reg1) && (0U != reg2))
{
return SET;
} else {
return RESET;

87
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_rtc.c
View File

@ -79,7 +79,8 @@ ErrStatus rtc_deinit(void)
flag_status = RTC_STAT & RTC_STAT_WTWF;
} while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
if((uint32_t)RESET == flag_status) {
if((uint32_t)RESET == flag_status)
{
error_status = ERROR;
} else {
RTC_CTL &= ((uint32_t)~RTC_CTL_WTCS);
@ -91,7 +92,8 @@ ErrStatus rtc_deinit(void)
/* enter init mode */
error_status = rtc_init_mode_enter();
if(ERROR != error_status) {
if(ERROR != error_status)
{
/* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition.
in order to read calendar from shadow register, not the real registers being reset */
RTC_TIME = RTC_REGISTER_RESET;
@ -167,7 +169,8 @@ ErrStatus rtc_init(rtc_parameter_struct *rtc_initpara_struct)
/* 2nd: enter init mode */
error_status = rtc_init_mode_enter();
if(ERROR != error_status) {
if(ERROR != error_status)
{
RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->factor_asyn) | \
PSC_FACTOR_S(rtc_initpara_struct->factor_syn));
@ -203,7 +206,8 @@ ErrStatus rtc_init_mode_enter(void)
ErrStatus error_status = ERROR;
/* check whether it has been in init mode */
if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)) {
if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF))
{
RTC_STAT |= RTC_STAT_INITM;
/* wait until the INITF flag to be set */
@ -211,7 +215,8 @@ ErrStatus rtc_init_mode_enter(void)
flag_status = RTC_STAT & RTC_STAT_INITF;
} while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status));
if((uint32_t)RESET != flag_status) {
if((uint32_t)RESET != flag_status)
{
error_status = SUCCESS;
}
} else {
@ -244,7 +249,8 @@ ErrStatus rtc_register_sync_wait(void)
uint32_t flag_status = RESET;
ErrStatus error_status = ERROR;
if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)) {
if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD))
{
/* disable the write protection */
RTC_WPK = RTC_UNLOCK_KEY1;
RTC_WPK = RTC_UNLOCK_KEY2;
@ -257,7 +263,8 @@ ErrStatus rtc_register_sync_wait(void)
flag_status = RTC_STAT & RTC_STAT_RSYNF;
} while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
if((uint32_t)RESET != flag_status) {
if((uint32_t)RESET != flag_status)
{
error_status = SUCCESS;
}
@ -366,7 +373,8 @@ void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time)
ALRMTD_MN(rtc_alarm_time->alarm_minute) | \
ALRMTD_SC(rtc_alarm_time->alarm_second));
if(RTC_ALARM0 == rtc_alarm) {
if(RTC_ALARM0 == rtc_alarm)
{
RTC_ALRM0TD = (uint32_t)reg_alrmtd;
} else {
@ -411,7 +419,8 @@ void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint
/* 2nd: enter init mode */
if(ERROR != (rtc_init_mode_enter()))
{
if(RTC_ALARM0 == rtc_alarm) {
if(RTC_ALARM0 == rtc_alarm)
{
RTC_ALRM0SS = mask_subsecond | subsecond;
} else {
RTC_ALRM1SS = mask_subsecond | subsecond;
@ -444,7 +453,8 @@ void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time)
uint32_t reg_alrmtd = 0U;
/* get the value of RTC_ALRM0TD register */
if(RTC_ALARM0 == rtc_alarm) {
if(RTC_ALARM0 == rtc_alarm)
{
reg_alrmtd = RTC_ALRM0TD;
} else {
reg_alrmtd = RTC_ALRM1TD;
@ -467,7 +477,8 @@ void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time)
*/
uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm)
{
if(RTC_ALARM0 == rtc_alarm) {
if(RTC_ALARM0 == rtc_alarm)
{
return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC));
} else {
return ((uint32_t)(RTC_ALRM1SS & RTC_ALRM1SS_SSC));
@ -486,7 +497,8 @@ void rtc_alarm_enable(uint8_t rtc_alarm)
RTC_WPK = RTC_UNLOCK_KEY1;
RTC_WPK = RTC_UNLOCK_KEY2;
if(RTC_ALARM0 == rtc_alarm) {
if(RTC_ALARM0 == rtc_alarm)
{
RTC_CTL |= RTC_CTL_ALRM0EN;
} else {
RTC_CTL |= RTC_CTL_ALRM1EN;
@ -513,7 +525,8 @@ ErrStatus rtc_alarm_disable(uint8_t rtc_alarm)
RTC_WPK = RTC_UNLOCK_KEY2;
/* clear the state of alarm */
if(RTC_ALARM0 == rtc_alarm) {
if(RTC_ALARM0 == rtc_alarm)
{
RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN);
/* wait until ALRM0WF flag to be set after the alarm is disabled */
do {
@ -527,7 +540,8 @@ ErrStatus rtc_alarm_disable(uint8_t rtc_alarm)
} while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
}
if((uint32_t)RESET != flag_status) {
if((uint32_t)RESET != flag_status)
{
error_status = SUCCESS;
}
@ -600,7 +614,8 @@ void rtc_timestamp_internalevent_config(uint32_t mode)
RTC_WPK = RTC_UNLOCK_KEY1;
RTC_WPK = RTC_UNLOCK_KEY2;
if(mode == RTC_ITSEN_ENABLE) {
if(mode == RTC_ITSEN_ENABLE)
{
RTC_CTL |= RTC_CTL_ITSEN;
} else {
RTC_CTL &= ~(uint32_t)RTC_CTL_ITSEN;
@ -689,11 +704,13 @@ void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper)
RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT;
/* the tamper source is voltage level detection */
if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE) {
if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE)
{
RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT);
/* check if the tamper pin need precharge, if need, then configure the precharge time */
if(DISABLE == rtc_tamper->tamper_precharge_enable) {
if(DISABLE == rtc_tamper->tamper_precharge_enable)
{
RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU;
} else {
RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_precharge_time);
@ -704,18 +721,21 @@ void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper)
/* configure the tamper trigger */
RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS));
if(RTC_TAMPER_TRIGGER_LEVEL_LOW != rtc_tamper->tamper_trigger) {
if(RTC_TAMPER_TRIGGER_LEVEL_LOW != rtc_tamper->tamper_trigger)
{
RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS);
}
} else {
/* configure the tamper trigger */
RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS));
if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger) {
if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger)
{
RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS);
}
}
RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS;
if(DISABLE != rtc_tamper->tamper_with_timestamp) {
if(DISABLE != rtc_tamper->tamper_with_timestamp)
{
/* the tamper event also cause a time-stamp event */
RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS;
}
@ -758,7 +778,8 @@ void rtc_output_pin_select(uint32_t outputpin)
/* enter init mode */
error_status = rtc_init_mode_enter();
if(ERROR != error_status) {
if(ERROR != error_status)
{
RTC_CFG &= (uint32_t)(~RTC_CFG_OUT2EN);
RTC_CFG |= (uint32_t)(outputpin);
/* exit init mode */
@ -872,7 +893,8 @@ ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus)
/* check if the function of reference clock detection is disabled */
temp = RTC_CTL & RTC_CTL_REFEN;
if((RESET == flag_status) && (RESET == temp)) {
if((RESET == flag_status) && (RESET == temp))
{
RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus));
error_status = rtc_register_sync_wait();
}
@ -936,7 +958,8 @@ ErrStatus rtc_refclock_detection_enable(void)
/* enter init mode */
error_status = rtc_init_mode_enter();
if(ERROR != error_status) {
if(ERROR != error_status)
{
RTC_CTL |= (uint32_t)RTC_CTL_REFEN;
/* exit init mode */
rtc_init_mode_exit();
@ -965,7 +988,8 @@ ErrStatus rtc_refclock_detection_disable(void)
/* enter init mode */
error_status = rtc_init_mode_enter();
if(ERROR != error_status) {
if(ERROR != error_status)
{
RTC_CTL &= (uint32_t)~RTC_CTL_REFEN;
/* exit init mode */
rtc_init_mode_exit();
@ -1017,7 +1041,8 @@ ErrStatus rtc_wakeup_disable(void)
flag_status = RTC_STAT & RTC_STAT_WTWF;
} while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
if((uint32_t)RESET == flag_status) {
if((uint32_t)RESET == flag_status)
{
error_status = ERROR;
} else {
error_status = SUCCESS;
@ -1057,7 +1082,8 @@ ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock)
flag_status = RTC_STAT & RTC_STAT_WTWF;
} while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
if((uint32_t)RESET == flag_status) {
if((uint32_t)RESET == flag_status)
{
error_status = ERROR;
} else {
RTC_CTL &= (uint32_t)~ RTC_CTL_WTCS;
@ -1092,7 +1118,8 @@ ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer)
flag_status = RTC_STAT & RTC_STAT_WTWF;
} while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
if((uint32_t)RESET == flag_status) {
if((uint32_t)RESET == flag_status)
{
error_status = ERROR;
} else {
RTC_WUT = (uint32_t)wakeup_timer;
@ -1144,7 +1171,8 @@ ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t
flag_status = RTC_STAT & RTC_STAT_SCPF;
} while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
if((uint32_t)RESET == flag_status) {
if((uint32_t)RESET == flag_status)
{
RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus));
error_status = SUCCESS;
}
@ -1232,7 +1260,8 @@ FlagStatus rtc_flag_get(uint32_t flag)
{
FlagStatus flag_state = RESET;
if((uint32_t)RESET != (RTC_STAT & flag)) {
if((uint32_t)RESET != (RTC_STAT & flag))
{
flag_state = SET;
}
return flag_state;

18
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_rtdec.c
View File

@ -45,12 +45,14 @@ OF SUCH DAMAGE.
*/
void rtdec_deinit(uint32_t rtdec_periph)
{
if(RTDEC0 == rtdec_periph){
if(RTDEC0 == rtdec_periph)
{
/* reset RTDEC0 */
rcu_periph_reset_enable(RCU_RTDEC0RST);
rcu_periph_reset_disable(RCU_RTDEC0RST);
}
if(RTDEC1 == rtdec_periph) {
if(RTDEC1 == rtdec_periph)
{
/* reset RTDEC1 */
rcu_periph_reset_enable(RCU_RTDEC1RST);
rcu_periph_reset_disable(RCU_RTDEC1RST);
@ -113,7 +115,8 @@ ErrStatus rtdec_init(uint32_t rtdec_periph, uint32_t rtdec_area, rtdec_parameter
/* check the key CRC */
key_crc_reg = (uint8_t)GET_BITS(RTDEC_ARE_CFG(rtdec_periph, rtdec_area), 8U, 15U);
if(key_crc_reg != rtdec_struct->key_crc){
if(key_crc_reg != rtdec_struct->key_crc)
{
return ERROR;
}
@ -270,7 +273,8 @@ void rtdec_disable(uint32_t rtdec_periph, uint32_t rtdec_area)
*/
FlagStatus rtdec_flag_get(uint32_t rtdec_periph, uint32_t flag)
{
if(RESET != (RTDEC_INTF(rtdec_periph) & flag)){
if(RESET != (RTDEC_INTF(rtdec_periph) & flag))
{
return SET;
}else{
return RESET;
@ -340,7 +344,8 @@ FlagStatus rtdec_interrupt_flag_get(uint32_t rtdec_periph, uint32_t int_flag)
{
uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
switch(int_flag){
switch(int_flag)
{
/* RTDEC security error interrupt */
case RTDEC_INT_FLAG_SEC_ERROR:
interrupt_flag = RTDEC_INTF(rtdec_periph) & int_flag;
@ -360,7 +365,8 @@ FlagStatus rtdec_interrupt_flag_get(uint32_t rtdec_periph, uint32_t int_flag)
break;
}
/* get RTDEC interrupt flag status */
if(interrupt_flag && interrupt_enable){
if(interrupt_flag && interrupt_enable)
{
return SET;
}else{
return RESET;

24
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_sai.c
View File

@ -47,7 +47,8 @@ OF SUCH DAMAGE.
*/
void sai_deinit(uint32_t sai_periph)
{
switch(sai_periph) {
switch(sai_periph)
{
case SAI0:
/* reset SAI0 */
rcu_periph_reset_enable(RCU_SAI0RST);
@ -440,15 +441,20 @@ sai_fifo_state_enum sai_fifo_status_get(uint32_t sai_periph, uint32_t block)
{
sai_fifo_state_enum sai_fifo_state = FIFO_EMPTY;
if(SAI_FIFO_STAT_EMPTY == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT)) {
if(SAI_FIFO_STAT_EMPTY == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT))
{
sai_fifo_state = FIFO_EMPTY;
} else if(SAI_FIFO_STAT_QUARTER == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT)) {
} else if(SAI_FIFO_STAT_QUARTER == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT))
{
sai_fifo_state = FIFO_EMPTY_TO_1_4_FULL;
} else if(SAI_FIFO_STAT_HALF == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT)) {
} else if(SAI_FIFO_STAT_HALF == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT))
{
sai_fifo_state = FIFO_1_4_FULL_TO_1_2_FULL;
} else if(SAI_FIFO_STAT_THREE_QUARTER == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT)) {
} else if(SAI_FIFO_STAT_THREE_QUARTER == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT))
{
sai_fifo_state = FIFO_1_2_FULL_TO_3_4_FULL;
} else if(SAI_FIFO_STAT_NEARFULL == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT)) {
} else if(SAI_FIFO_STAT_NEARFULL == (SAI_STAT(sai_periph, block) & SAI_STAT_FFSTAT))
{
sai_fifo_state = FIFO_3_4_FULL_TO_FULL;
} else {
sai_fifo_state = FIFO_FULL;
@ -713,7 +719,8 @@ FlagStatus sai_interrupt_flag_get(uint32_t sai_periph, uint32_t block, uint32_t
{
uint32_t inten = 0U;
inten = SAI_INTEN(sai_periph, block) & interrupt;
if((RESET != (SAI_STAT(sai_periph, block) & interrupt)) && (RESET != inten)) {
if((RESET != (SAI_STAT(sai_periph, block) & interrupt)) && (RESET != inten))
{
return SET;
} else {
return RESET;
@ -762,7 +769,8 @@ void sai_interrupt_flag_clear(uint32_t sai_periph, uint32_t block, uint32_t inte
*/
FlagStatus sai_flag_get(uint32_t sai_periph, uint32_t block, uint32_t flag)
{
if(RESET != (SAI_STAT(sai_periph, block) & flag)) {
if(RESET != (SAI_STAT(sai_periph, block) & flag))
{
return SET;
} else {
return RESET;

12
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_sdio.c
View File

@ -45,7 +45,8 @@ OF SUCH DAMAGE.
*/
void sdio_deinit(uint32_t sdio_periph)
{
switch(sdio_periph) {
switch(sdio_periph)
{
/* reset SDIO0 */
case SDIO0:
rcu_periph_reset_enable(RCU_SDIO0RST);
@ -375,7 +376,8 @@ uint32_t sdio_response_get(uint32_t sdio_periph, uint32_t sdio_responsex)
uint32_t resp_content = 0U;
/* get the content of the last response */
switch(sdio_responsex) {
switch(sdio_responsex)
{
case SDIO_RESPONSE0:
resp_content = SDIO_RESP0(sdio_periph);
break;
@ -725,7 +727,8 @@ void sdio_idma_disable(uint32_t sdio_periph)
FlagStatus sdio_flag_get(uint32_t sdio_periph, uint32_t flag)
{
FlagStatus temp_flag = RESET;
if(RESET != (SDIO_STAT(sdio_periph) & flag)) {
if(RESET != (SDIO_STAT(sdio_periph) & flag))
{
temp_flag = SET;
}
return temp_flag;
@ -873,7 +876,8 @@ void sdio_interrupt_disable(uint32_t sdio_periph, uint32_t int_flag)
FlagStatus sdio_interrupt_flag_get(uint32_t sdio_periph, uint32_t int_flag)
{
FlagStatus temp_flag = RESET;
if(RESET != (SDIO_STAT(sdio_periph) & int_flag)) {
if(RESET != (SDIO_STAT(sdio_periph) & int_flag))
{
temp_flag = SET;
}
return temp_flag;

81
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_spi.c
View File

@ -64,7 +64,8 @@ OF SUCH DAMAGE.
*/
void spi_i2s_deinit(uint32_t spi_periph)
{
switch(spi_periph){
switch(spi_periph)
{
case SPI0:
/* reset SPI0 and I2S0 */
rcu_periph_reset_enable(RCU_SPI0RST);
@ -274,16 +275,19 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_
uint32_t spi3_5_clksel[7] = {CK_APB2, CK_PLL1Q, CK_PLL2Q, CK_IRC64MDIV, CK_LPIRC4M, CK_HXTAL, I2S_CKIN_VALUE};
/* judge whether the audiosample is 0 */
if(0U == i2s_audiosample){
if(0U == i2s_audiosample)
{
SPI_ERROR_HANDLE("the parameter can not be 0 \r\n");
}
/* get the I2S clock source */
switch(spi_periph){
switch(spi_periph)
{
case SPI0:
/* I2S0 clock source selection */
i2s_clk_sel = RCU_CFG5 & RCU_CFG5_SPI0SEL;
if(3U == i2s_clk_sel){
if(3U == i2s_clk_sel)
{
i2sclock = spi0_2_clksel[i2s_clk_sel];
}else{
i2sclock = rcu_clock_freq_get((rcu_clock_freq_enum)spi0_2_clksel[i2s_clk_sel]);
@ -292,7 +296,8 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_
case SPI1:
/* I2S1 clock source selection */
i2s_clk_sel = (RCU_CFG5 & RCU_CFG5_SPI1SEL) >> 4U;
if(3U == i2s_clk_sel){
if(3U == i2s_clk_sel)
{
i2sclock = spi0_2_clksel[i2s_clk_sel];
}else{
i2sclock = rcu_clock_freq_get((rcu_clock_freq_enum)spi0_2_clksel[i2s_clk_sel]);
@ -301,7 +306,8 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_
case SPI2:
/* I2S2 clock source selection */
i2s_clk_sel = (RCU_CFG5 & RCU_CFG5_SPI2SEL) >> 8U;
if(3U == i2s_clk_sel){
if(3U == i2s_clk_sel)
{
i2sclock = spi0_2_clksel[i2s_clk_sel];
}else{
i2sclock = rcu_clock_freq_get((rcu_clock_freq_enum)spi0_2_clksel[i2s_clk_sel]);
@ -310,7 +316,8 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_
case SPI5:
/* I2S5 clock source selection */
i2s_clk_sel = (RCU_CFG5 & RCU_CFG5_SPI5SEL) >> 20U;
if(3U > i2s_clk_sel){
if(3U > i2s_clk_sel)
{
i2sclock = rcu_clock_freq_get((rcu_clock_freq_enum)spi3_5_clksel[i2s_clk_sel]);
}else{
i2sclock = spi3_5_clksel[i2s_clk_sel];
@ -321,10 +328,12 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_
}
/* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
if(I2S_MCKOUT_ENABLE == i2s_mckout){
if(I2S_MCKOUT_ENABLE == i2s_mckout)
{
clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample);
}else{
if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat){
if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat)
{
clks = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample);
}else{
clks = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample);
@ -337,7 +346,8 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_
i2sdiv = ((clks - i2sof) / 2U);
/* set the default values */
if((i2sdiv < 2U) || (i2sdiv > 255U)){
if((i2sdiv < 2U) || (i2sdiv > 255U))
{
i2sdiv = 2U;
i2sof = 0U;
}
@ -386,7 +396,8 @@ void i2s_disable(uint32_t spi_periph)
*/
void spi_io_config(uint32_t spi_periph, uint32_t io_cfg)
{
if(SPI_IO_SWAP == io_cfg){
if(SPI_IO_SWAP == io_cfg)
{
SPI_CFG1(spi_periph) |= (uint32_t)SPI_CFG1_SWPMIO;
}
else{
@ -502,7 +513,8 @@ void spi_slave_receive_clock_delay_clear(uint32_t spi_periph)
*/
void spi_nss_output_control(uint32_t spi_periph, uint32_t nss_ctl)
{
if(SPI_NSS_HOLD_UNTIL_TRANS_END == nss_ctl){
if(SPI_NSS_HOLD_UNTIL_TRANS_END == nss_ctl)
{
SPI_CFG1(spi_periph) &= (uint32_t)(~SPI_CFG1_NSSCTL);
}
else{
@ -522,7 +534,8 @@ void spi_nss_output_control(uint32_t spi_periph, uint32_t nss_ctl)
*/
void spi_nss_polarity_set(uint32_t spi_periph, uint32_t polarity)
{
if(SPI_NSS_POLARITY_HIGH == polarity){
if(SPI_NSS_POLARITY_HIGH == polarity)
{
SPI_CFG1(spi_periph) |= (uint32_t)SPI_CFG1_NSSIOPL;
}
else{
@ -586,7 +599,8 @@ void spi_nss_internal_low(uint32_t spi_periph)
*/
void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma)
{
if(SPI_DMA_TRANSMIT == spi_dma){
if(SPI_DMA_TRANSMIT == spi_dma)
{
SPI_CFG0(spi_periph) |= (uint32_t)SPI_CFG0_DMATEN;
}else{
SPI_CFG0(spi_periph) |= (uint32_t)SPI_CFG0_DMAREN;
@ -605,7 +619,8 @@ void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma)
*/
void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma)
{
if(SPI_DMA_TRANSMIT == spi_dma){
if(SPI_DMA_TRANSMIT == spi_dma)
{
SPI_CFG0(spi_periph) &= (uint32_t)(~SPI_CFG0_DMATEN);
}else{
SPI_CFG0(spi_periph) &= (uint32_t)(~SPI_CFG0_DMAREN);
@ -671,7 +686,8 @@ uint32_t spi_i2s_data_receive(uint32_t spi_periph)
*/
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
{
if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){
if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction)
{
/* set the transmit only mode */
SPI_CFG1(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
}else{
@ -692,7 +708,8 @@ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_di
*/
void spi_master_transfer_start(uint32_t spi_periph, uint32_t transfer_start)
{
if(SPI_TRANS_START == transfer_start){
if(SPI_TRANS_START == transfer_start)
{
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_MSTART;
}else{
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_MSTART);
@ -814,7 +831,8 @@ void spi_crc_off(uint32_t spi_periph)
*/
uint32_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
{
if(SPI_CRC_TX == crc){
if(SPI_CRC_TX == crc)
{
return ((uint32_t)(SPI_TCRC(spi_periph)));
}else{
return ((uint32_t)(SPI_RCRC(spi_periph)));
@ -855,7 +873,8 @@ void spi_crc_full_size_disable(uint32_t spi_periph)
*/
void spi_tcrc_init_pattern(uint32_t spi_periph, uint32_t init_pattern)
{
if(init_pattern == SPI_TCRC_INIT_1){
if(init_pattern == SPI_TCRC_INIT_1)
{
SPI_CTL0(spi_periph) |= (uint32_t)(SPI_CTL0_TXCRCI);
}else{
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_TXCRCI);
@ -874,7 +893,8 @@ void spi_tcrc_init_pattern(uint32_t spi_periph, uint32_t init_pattern)
*/
void spi_rcrc_init_pattern(uint32_t spi_periph, uint32_t init_pattern)
{
if(init_pattern == SPI_RCRC_INIT_1){
if(init_pattern == SPI_RCRC_INIT_1)
{
SPI_CTL0(spi_periph) |= (uint32_t)(SPI_CTL0_RXCRCI);
}else{
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_RXCRCI);
@ -1037,7 +1057,8 @@ void spi_underrun_data_config(uint32_t spi_periph, uint32_t udata)
*/
void spi_suspend_mode_config(uint32_t spi_periph, uint32_t sus_mode)
{
if(SPI_AUTO_SUSPEND == sus_mode){
if(SPI_AUTO_SUSPEND == sus_mode)
{
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_MASP;
}else{
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_MASP);
@ -1089,7 +1110,8 @@ void spi_related_ios_af_disable(uint32_t spi_periph)
*/
void spi_af_gpio_control(uint32_t spi_periph, uint32_t ctl)
{
if(SPI_GPIO_CONTROL == ctl){
if(SPI_GPIO_CONTROL == ctl)
{
SPI_CFG1(spi_periph) |= (uint32_t)SPI_CFG1_AFCTL;
}else{
SPI_CFG1(spi_periph) &= (uint32_t)(~SPI_CFG1_AFCTL);
@ -1117,7 +1139,8 @@ void spi_af_gpio_control(uint32_t spi_periph, uint32_t ctl)
*/
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
{
switch(interrupt){
switch(interrupt)
{
/* SPI/I2S RP interrupt */
case SPI_I2S_INT_RP:
SPI_INT(spi_periph) |= (uint32_t)SPI_INT_RPIE;
@ -1188,7 +1211,8 @@ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
*/
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
{
switch(interrupt){
switch(interrupt)
{
/* SPI/I2S RP interrupt */
case SPI_I2S_INT_RP:
SPI_INT(spi_periph) &= (uint32_t)(~SPI_INT_RPIE);
@ -1264,7 +1288,8 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
uint32_t reg1 = SPI_STAT(spi_periph);
uint32_t reg2 = SPI_INT(spi_periph);
switch(interrupt){
switch(interrupt)
{
/* SPI/I2S RP interrupt */
case SPI_I2S_INT_FLAG_RP:
reg1 = reg1 & SPI_STAT_RP;
@ -1334,7 +1359,8 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
break;
}
/*get SPI/I2S interrupt flag status */
if(reg1 && reg2){
if(reg1 && reg2)
{
return SET;
}else{
return RESET;
@ -1373,7 +1399,8 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
*/
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
{
if(SPI_STAT(spi_periph) & flag){
if(SPI_STAT(spi_periph) & flag)
{
return SET;
}else{
return RESET;

24
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_syscfg.c
View File

@ -133,7 +133,8 @@ void syscfg_enet_phy_interface_config(uint32_t ethernet, uint32_t phy_interface)
/* read the value of SYSCFG_PMCFG register */
reg = SYSCFG_PMCFG;
/* configure the ENET media interface */
if(ENET0 == ethernet) {
if(ENET0 == ethernet)
{
reg &= ~SYSCFG_PMCFG_ENET0_PHY_SEL;
reg |= ENET0_MEDIA_INTERFACE(phy_interface);
} else {
@ -160,7 +161,8 @@ void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin)
uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin)));
uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin));
switch(exti_pin / EXTI_SS_JSTEP) {
switch(exti_pin / EXTI_SS_JSTEP)
{
case EXTISS0:
/* clear EXTI source line(0..3) */
SYSCFG_EXTISS0 &= clear_exti_mask;
@ -351,7 +353,8 @@ void syscfg_timer_input_source_select(timer_channel_input_enum timer_input)
uint32_t clear_timer_mask = ~((uint32_t)TIMER_IS_MASK << (TIMER_BIT_POS(timer_input)));
uint32_t config_timer_mask = (TIMER_SEL_VAL(timer_input) << TIMER_BIT_POS(timer_input));
switch(TIMER_REG_INDEX(timer_input)) {
switch(TIMER_REG_INDEX(timer_input))
{
case TIMERCISEL0:
/* clear TIMER channel input select */
SYSCFG_TIMERCISEL0 &= clear_timer_mask;
@ -454,7 +457,8 @@ void syscfg_pnmos_compensation_code_set(uint32_t mos, uint32_t code)
{
uint32_t value;
value = SYSCFG_CPSCCCFG;
if(NMOS_COMPENSATION == mos) {
if(NMOS_COMPENSATION == mos)
{
value &= ~SYSCFG_CPSCCCFG_NCPSCC;
value |= (code & 0x0FU);
} else {
@ -579,7 +583,8 @@ void syscfg_fpu_interrupt_disable(uint32_t fpu_int)
*/
FlagStatus syscfg_compensation_flag_get(uint32_t cps_flag)
{
if(SYSCFG_CPSCTL & cps_flag) {
if(SYSCFG_CPSCTL & cps_flag)
{
return SET;
} else {
return RESET;
@ -602,10 +607,12 @@ FlagStatus syscfg_compensation_flag_get(uint32_t cps_flag)
uint32_t syscfg_cpu_cache_status_get(uint32_t cache, uint32_t status)
{
uint32_t value = 0U;
switch(cache) {
switch(cache)
{
/* get ICACHE information */
case ICACHE_STATUS:
if(CPU_CACHE_ERROR_DETECTION == status) {
if(CPU_CACHE_ERROR_DETECTION == status)
{
/* return detection information */
value = (uint32_t)((SYSCFG_CPUICAC & SYSCFG_CPUICAC_CPU_ICDET) >> 28U);
} else {
@ -615,7 +622,8 @@ uint32_t syscfg_cpu_cache_status_get(uint32_t cache, uint32_t status)
break;
/* get DCACHE information */
case DCACHE_STATUS:
if(CPU_CACHE_ERROR_DETECTION == status) {
if(CPU_CACHE_ERROR_DETECTION == status)
{
/* return detection information */
value = (uint32_t)((SYSCFG_CPUDCAC & SYSCFG_CPUICAC_CPU_ICDET) >> 28U);
} else {

483
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_timer.c
View File

File diff suppressed because it is too large Load Diff

21
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_tli.c
View File

@ -146,7 +146,8 @@ void tli_init(tli_parameter_struct *tli_struct)
*/
void tli_dither_config(uint8_t dither_stat)
{
if(TLI_DITHER_ENABLE == dither_stat){
if(TLI_DITHER_ENABLE == dither_stat)
{
TLI_CTL |= TLI_CTL_DFEN;
} else {
TLI_CTL &= ~(TLI_CTL_DFEN);
@ -186,7 +187,8 @@ void tli_disable(void)
*/
void tli_reload_config(uint8_t reload_mod)
{
if(TLI_FRAME_BLANK_RELOAD_EN == reload_mod){
if(TLI_FRAME_BLANK_RELOAD_EN == reload_mod)
{
/* the layer configuration will be reloaded at frame blank */
TLI_RL |= TLI_RL_FBR;
} else {
@ -322,7 +324,8 @@ void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t o
line_num = (TLI_LXFTLN(layerx) & TLI_LXFTLN_FTLN);
layer_ppf = (TLI_LXPPF(layerx) & TLI_LXPPF_PPF);
/* the bytes of a line equal TLI_LXFLLEN_FLL bits value minus 3 */
switch(layer_ppf){
switch(layer_ppf)
{
case LAYER_PPF_ARGB8888:
/* each pixel includes 4bytes, when pixel format is ARGB8888 */
line_length = (((TLI_LXFLLEN(layerx) & TLI_LXFLLEN_FLL) -3U) / 4U);
@ -540,9 +543,11 @@ FlagStatus tli_interrupt_flag_get(uint32_t int_flag)
{
uint32_t state;
state = TLI_INTF;
if(state & int_flag){
if(state & int_flag)
{
state = TLI_INTEN;
if(state & int_flag){
if(state & int_flag)
{
return SET;
}
}
@ -584,12 +589,14 @@ FlagStatus tli_flag_get(uint32_t flag)
{
uint32_t stat;
/* choose which register to get flag or state */
if(flag >> 31U){
if(flag >> 31U)
{
stat = TLI_INTF;
}else{
stat = TLI_STAT;
}
if(flag & stat){
if(flag & stat)
{
return SET;
}else{
return RESET;

6
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_trigsel.c
View File

@ -275,7 +275,8 @@ void trigsel_deinit(void)
void trigsel_init(trigsel_periph_enum target_periph, trigsel_source_enum trigger_source)
{
/* if register write is enabled, set trigger source to target peripheral */
if (RESET == trigsel_register_lock_get(target_periph)){
if (RESET == trigsel_register_lock_get(target_periph))
{
TRIGSEL_TARGET_REG(target_periph) &= ~TRIGSEL_TARGET_PERIPH_MASK(target_periph);
TRIGSEL_TARGET_REG(target_periph) |= ((uint32_t)trigger_source << TRIGSEL_TARGET_PERIPH_SHIFT(target_periph)) & TRIGSEL_TARGET_PERIPH_MASK(target_periph);
}
@ -505,7 +506,8 @@ void trigsel_register_lock_set(trigsel_periph_enum target_periph)
*/
FlagStatus trigsel_register_lock_get(trigsel_periph_enum target_periph)
{
if(RESET != (TRIGSEL_TARGET_REG(target_periph) & TRIGSEL_TARGET_LK)){
if(RESET != (TRIGSEL_TARGET_REG(target_periph) & TRIGSEL_TARGET_LK))
{
return SET;
}else{
return RESET;

6
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_trng.c
View File

@ -364,7 +364,8 @@ void trng_health_tests_config(uint32_t adpo_threshold, uint8_t rep_threshold)
*/
FlagStatus trng_flag_get(trng_flag_enum flag)
{
if(RESET != (TRNG_STAT & flag)){
if(RESET != (TRNG_STAT & flag))
{
return SET;
}else{
return RESET;
@ -404,7 +405,8 @@ void trng_interrupt_disable(void)
*/
FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag)
{
if(RESET != (TRNG_STAT & int_flag)){
if(RESET != (TRNG_STAT & int_flag))
{
return SET;
}else{
return RESET;

36
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_usart.c
View File

@ -52,7 +52,8 @@ OF SUCH DAMAGE.
*/
void usart_deinit(uint32_t usart_periph)
{
switch(usart_periph){
switch(usart_periph)
{
case USART0:
/* reset USART0 */
rcu_periph_reset_enable(RCU_USART0RST);
@ -108,7 +109,8 @@ void usart_deinit(uint32_t usart_periph)
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
{
uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U;
switch(usart_periph){
switch(usart_periph)
{
/* get clock frequency */
case USART0:
/* get USART0 clock */
@ -146,7 +148,8 @@ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
break;
}
if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){
if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD)
{
/* oversampling by 8, configure the value of USART_BAUD */
udiv = ((2U * uclk) + baudval / 2U) / baudval;
intdiv = udiv & 0x0000fff0U;
@ -319,7 +322,8 @@ void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara)
{
USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
/* inverted or not the specified signal */
switch(invertpara){
switch(invertpara)
{
case USART_DINV_ENABLE:
USART_CTL1(usart_periph) |= USART_CTL1_DINV;
break;
@ -1342,7 +1346,8 @@ uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph)
*/
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
{
if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){
if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag))))
{
return SET;
}else{
return RESET;
@ -1374,11 +1379,14 @@ FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
*/
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
{
if(USART_FLAG_AM1 == flag){
if(USART_FLAG_AM1 == flag)
{
USART_INTC(usart_periph) |= USART_INTC_AMC1;
}else if(USART_FLAG_EPERR == flag){
}else if(USART_FLAG_EPERR == flag)
{
USART_CHC(usart_periph) &= (uint32_t)(~USART_CHC_EPERR);
}else if(USART_FLAG_TFE == flag){
}else if(USART_FLAG_TFE == flag)
{
USART_FCS(usart_periph) |= USART_FCS_TFEC;
}else{
USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag));
@ -1488,7 +1496,8 @@ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_
/* get the corresponding flag bit status */
flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
if(flagstatus && intenable){
if(flagstatus && intenable)
{
return SET;
}else{
return RESET;
@ -1522,11 +1531,14 @@ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_
*/
void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag)
{
if(USART_INT_FLAG_TFE == int_flag){
if(USART_INT_FLAG_TFE == int_flag)
{
USART_FCS(usart_periph) |= USART_FCS_TFEC;
}else if(USART_INT_FLAG_RFF == int_flag){
}else if(USART_INT_FLAG_RFF == int_flag)
{
USART_FCS(usart_periph) &= (uint32_t)(~USART_FCS_RFFIF);
}else if(USART_INT_FLAG_RFT == int_flag){
}else if(USART_INT_FLAG_RFT == int_flag)
{
USART_FCS(usart_periph) &= (uint32_t)(~USART_FCS_RFTIF);
}else{
USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(int_flag));

3
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_vref.c
View File

@ -100,7 +100,8 @@ void vref_high_impedance_mode_disable(void)
*/
FlagStatus vref_status_get(void)
{
if(RESET != (VREF_CS & (uint32_t)VREF_CS_VREFRDY)){
if(RESET != (VREF_CS & (uint32_t)VREF_CS_VREFRDY))
{
return SET;
}else{
return RESET;

3
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_wwdgt.c
View File

@ -112,7 +112,8 @@ void wwdgt_interrupt_enable(void)
*/
FlagStatus wwdgt_flag_get(void)
{
if (RESET != (WWDGT_STAT & WWDGT_STAT_EWIF)){
if (RESET != (WWDGT_STAT & WWDGT_STAT_EWIF))
{
return SET;
}

66
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/audio/Source/audio_core.c
View File

@ -569,7 +569,8 @@ static uint8_t audio_init (usb_dev *udev, uint8_t config_index)
usbd_ep_recev (udev, AD_OUT_EP, audio_handler.usb_rx_buffer, SPEAKER_OUT_MAX_PACKET);
/* initialize the audio output hardware layer */
if (USBD_OK != audio_out_fops.audio_init(USBD_SPEAKER_FREQ, DEFAULT_VOLUME)) {
if (USBD_OK != audio_out_fops.audio_init(USBD_SPEAKER_FREQ, DEFAULT_VOLUME))
{
return USBD_FAIL;
}
@ -610,7 +611,8 @@ static uint8_t audio_deinit (usb_dev *udev, uint8_t config_index)
usbd_ep_clear(udev, AD_OUT_EP);
/* deinitialize the audio output hardware layer */
if (USBD_OK != audio_out_fops.audio_deinit()) {
if (USBD_OK != audio_out_fops.audio_deinit())
{
return USBD_FAIL;
}
@ -635,7 +637,8 @@ static uint8_t audio_req_handler (usb_dev *udev, usb_req *req)
usb_transc *transc_in = &udev->dev.transc_in[0];
usb_transc *transc_out = &udev->dev.transc_out[0];
switch (req->bRequest) {
switch (req->bRequest)
{
case AD_REQ_GET_CUR:
transc_in->xfer_buf = audio_handler.audioctl;
transc_in->remain_len = req->wLength;
@ -644,7 +647,8 @@ static uint8_t audio_req_handler (usb_dev *udev, usb_req *req)
break;
case AD_REQ_SET_CUR:
if (req->wLength) {
if (req->wLength)
{
transc_out->xfer_buf = audio_handler.audioctl;
transc_out->remain_len = req->wLength;
@ -696,8 +700,10 @@ static uint8_t audio_set_intf(usb_dev *udev, usb_req *req)
{
udev->dev.class_core->alter_set = req->wValue;
if(0xFF != req->wValue){
if (req->wValue != 0){
if(0xFF != req->wValue)
{
if (req->wValue != 0)
{
/* deinit audio handler */
memset((void *)&audio_handler, 0, sizeof(usbd_audio_handler));
@ -739,11 +745,13 @@ static uint8_t audio_ctlx_out (usb_dev *udev)
#ifdef USE_USB_AD_SPEAKER
/* handles audio control requests data */
/* check if an audio_control request has been issued */
if (AD_REQ_SET_CUR == udev->dev.class_core->command) {
if (AD_REQ_SET_CUR == udev->dev.class_core->command)
{
/* in this driver, to simplify code, only SET_CUR request is managed */
/* check for which addressed unit the audio_control request has been issued */
if (AD_OUT_STREAMING_CTRL == audio_handler.audioctl_unit) {
if (AD_OUT_STREAMING_CTRL == audio_handler.audioctl_unit)
{
/* in this driver, to simplify code, only one unit is manage */
/* reset the audioctl_cmd variable to prevent re-entering this function */
@ -767,8 +775,10 @@ static uint8_t audio_ctlx_out (usb_dev *udev)
static uint8_t audio_data_in (usb_dev *udev, uint8_t ep_num)
{
#ifdef USE_USB_AD_MICPHONE
if(ep_num == EP_ID(AD_IN_EP)){
if(count_data < LENGTH_DATA){
if(ep_num == EP_ID(AD_IN_EP))
{
if(count_data < LENGTH_DATA)
{
/* Prepare next buffer to be sent: dummy data */
usbd_ep_send(udev, AD_IN_EP,(uint8_t*)&wavetestdata[count_data],MIC_IN_PACKET);
count_data += MIC_IN_PACKET;
@ -780,7 +790,8 @@ static uint8_t audio_data_in (usb_dev *udev, uint8_t ep_num)
#endif /* USE_USB_AD_MICPHONE */
#ifdef USE_USB_AD_SPEAKER
if(ep_num == EP_ID(AD_FEEDBACK_IN_EP)){
if(ep_num == EP_ID(AD_FEEDBACK_IN_EP))
{
/* calculate feedback actual freq */
audio_handler.actual_freq = usbd_audio_spk_get_feedback(udev);
get_feedback_fs_rate(audio_handler.actual_freq, audio_handler.feedback_freq);
@ -806,25 +817,30 @@ static uint8_t audio_data_out (usb_dev *udev, uint8_t ep_num)
/* get receive length */
usb_rx_length = ((usb_core_driver *)udev)->dev.transc_out[ep_num].xfer_count;
if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){
if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr)
{
audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr;
}else{
audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr;
}
/* free buffer enough to save rx data */
if(audio_handler.buf_free_size > usb_rx_length){
if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){
if(audio_handler.buf_free_size > usb_rx_length)
{
if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr)
{
tail_len = audio_handler.isoc_out_buff + TOTAL_OUT_BUF_SIZE - audio_handler.isoc_out_wrptr;
if(tail_len >= usb_rx_length){
if(tail_len >= usb_rx_length)
{
memcpy(audio_handler.isoc_out_wrptr, audio_handler.usb_rx_buffer, usb_rx_length);
/* increment the buffer pointer */
audio_handler.isoc_out_wrptr += usb_rx_length;
/* increment the Buffer pointer or roll it back when all buffers are full */
if(audio_handler.isoc_out_wrptr >= (audio_handler.isoc_out_buff + TOTAL_OUT_BUF_SIZE)){
if(audio_handler.isoc_out_wrptr >= (audio_handler.isoc_out_buff + TOTAL_OUT_BUF_SIZE))
{
/* all buffers are full: roll back */
audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff;
}
@ -851,18 +867,21 @@ static uint8_t audio_data_out (usb_dev *udev, uint8_t ep_num)
/* prepare out endpoint to receive next audio packet */
usbd_ep_recev (udev, AD_OUT_EP, audio_handler.usb_rx_buffer, SPEAKER_OUT_MAX_PACKET);
if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){
if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr)
{
audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr;
}else{
audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr;
}
if ((0U == audio_handler.play_flag) && (audio_handler.buf_free_size < TOTAL_OUT_BUF_SIZE/2)) {
if ((0U == audio_handler.play_flag) && (audio_handler.buf_free_size < TOTAL_OUT_BUF_SIZE/2))
{
/* enable start of streaming */
audio_handler.play_flag = 1U;
/* initialize the audio output hardware layer */
if (USBD_OK != audio_out_fops.audio_cmd(audio_handler.isoc_out_rdptr, SPEAKER_OUT_MAX_PACKET/2, AD_CMD_PLAY)) {
if (USBD_OK != audio_out_fops.audio_cmd(audio_handler.isoc_out_rdptr, SPEAKER_OUT_MAX_PACKET/2, AD_CMD_PLAY))
{
return USBD_FAIL;
}
@ -924,16 +943,19 @@ static uint32_t usbd_audio_spk_get_feedback(usb_dev *udev)
static uint32_t fb_freq;
/* calculate buffer free size */
if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){
if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr)
{
audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr;
}else{
audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr;
}
/* calculate feedback frequency */
if(audio_handler.buf_free_size <= (TOTAL_OUT_BUF_SIZE/4)){
if(audio_handler.buf_free_size <= (TOTAL_OUT_BUF_SIZE/4))
{
fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ) - FEEDBACK_FREQ_OFFSET;
}else if(audio_handler.buf_free_size >= (TOTAL_OUT_BUF_SIZE*3/4)){
}else if(audio_handler.buf_free_size >= (TOTAL_OUT_BUF_SIZE*3/4))
{
fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ) + FEEDBACK_FREQ_OFFSET;
}else{
fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ);

21
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/audio/Source/audio_out_itf.c
View File

@ -62,7 +62,8 @@ static uint8_t init (uint32_t audio_freq, uint32_t volume)
static uint32_t initialized = 0U;
/* check if the low layer has already been initialized */
if (0U == initialized) {
if (0U == initialized)
{
/* initialize GPIO */
codec_gpio_init();
@ -111,24 +112,28 @@ static uint8_t deinit (void)
static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd)
{
/* check the current state */
if ((AD_STATE_INACTIVE == audio_state) || (AD_STATE_ERROR == audio_state)) {
if ((AD_STATE_INACTIVE == audio_state) || (AD_STATE_ERROR == audio_state))
{
audio_state = AD_STATE_ERROR;
return AD_FAIL;
}
switch (cmd) {
switch (cmd)
{
/* process the play command */
case AD_CMD_PLAY:
/* if current state is active or stopped */
if ((AD_STATE_ACTIVE == audio_state) || \
(AD_STATE_STOPPED == audio_state) || \
(AD_STATE_PLAYING == audio_state)) {
(AD_STATE_PLAYING == audio_state))
{
audio_play((uint32_t)pbuf, size);
audio_state = AD_STATE_PLAYING;
return AD_OK;
} else if (AD_STATE_PAUSED == audio_state) {
} else if (AD_STATE_PAUSED == audio_state)
{
audio_pause_resume(AD_RESUME, (uint32_t)pbuf, (size/2));
audio_state = AD_STATE_PLAYING;
@ -139,7 +144,8 @@ static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd)
/* process the stop command */
case AD_CMD_STOP:
if (AD_STATE_PLAYING != audio_state) {
if (AD_STATE_PLAYING != audio_state)
{
/* unsupported command */
return AD_FAIL;
} else {
@ -151,7 +157,8 @@ static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd)
/* process the pause command */
case AD_CMD_PAUSE:
if (AD_STATE_PLAYING != audio_state) {
if (AD_STATE_PLAYING != audio_state)
{
/* unsupported command */
return AD_FAIL;
} else {

21
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/cdc/Source/cdc_acm_core.c
View File

@ -277,10 +277,12 @@ usb_class_core cdc_class = {
*/
uint8_t cdc_acm_check_ready(usb_dev *udev)
{
if(udev->dev.class_data[CDC_COM_INTERFACE] != NULL) {
if(udev->dev.class_data[CDC_COM_INTERFACE] != NULL)
{
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE];
if((1U == cdc->packet_receive) && (1U == cdc->packet_sent)) {
if((1U == cdc->packet_receive) && (1U == cdc->packet_sent))
{
return 0U;
}
}
@ -298,7 +300,8 @@ void cdc_acm_data_send(usb_dev *udev)
{
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE];
if(0U != cdc->receive_length) {
if(0U != cdc->receive_length)
{
cdc->packet_sent = 0U;
usbd_ep_send(udev, CDC_DATA_IN_EP, (uint8_t *)(cdc->data), cdc->receive_length);
@ -348,7 +351,8 @@ static uint8_t cdc_acm_init(usb_dev *udev, uint8_t config_index)
cdc_handler.packet_sent = 1U;
cdc_handler.receive_length = 0U;
cdc_handler.line_coding = (acm_line) {
cdc_handler.line_coding = (acm_line)
{
.dwDTERate = 115200,
.bCharFormat = 0,
.bParityType = 0,
@ -392,7 +396,8 @@ static uint8_t cdc_acm_req(usb_dev *udev, usb_req *req)
usb_transc *transc = NULL;
switch(req->bRequest) {
switch(req->bRequest)
{
case SEND_ENCAPSULATED_COMMAND:
/* no operation for this driver */
break;
@ -457,7 +462,8 @@ static uint8_t cdc_ctlx_out(usb_dev *udev)
{
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE];
if(NO_CMD != udev->dev.class_core->alter_set) {
if(NO_CMD != udev->dev.class_core->alter_set)
{
/* process the command data */
cdc->line_coding.dwDTERate = (uint32_t)((uint32_t)cdc->cmd[0] |
((uint32_t)cdc->cmd[1] << 8U) |
@ -487,7 +493,8 @@ static uint8_t cdc_acm_in(usb_dev *udev, uint8_t ep_num)
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE];
if((0U == transc->xfer_len % transc->max_len) && (0U != transc->xfer_len)) {
if((0U == transc->xfer_len % transc->max_len) && (0U != transc->xfer_len))
{
usbd_ep_send(udev, ep_num, NULL, 0U);
} else {
cdc->packet_sent = 1U;

84
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/dfu/Source/dfu_core.c
View File

@ -56,7 +56,8 @@ static void dfu_abort(usb_dev *udev, usb_req *req);
static void dfu_mode_leave(usb_dev *udev);
static uint8_t dfu_getstatus_complete(usb_dev *udev);
static void (*dfu_request_process[])(usb_dev *udev, usb_req *req) = {
static void (*dfu_request_process[])(usb_dev *udev, usb_req *req)=
{
[DFU_DETACH] = dfu_detach,
[DFU_DNLOAD] = dfu_dnload,
[DFU_UPLOAD] = dfu_upload,
@ -274,7 +275,8 @@ static uint8_t dfu_deinit(usb_dev *udev, uint8_t config_index)
*/
static uint8_t dfu_req_handler(usb_dev *udev, usb_req *req)
{
if(req->bRequest < DFU_REQ_MAX) {
if(req->bRequest < DFU_REQ_MAX)
{
dfu_request_process[req->bRequest](udev, req);
} else {
return USBD_FAIL;
@ -309,7 +311,8 @@ static void dfu_mode_leave(usb_dev *udev)
dfu->manifest_state = MANIFEST_COMPLETE;
if(dfu_config_desc.dfu_func.bmAttributes & 0x04U) {
if(dfu_config_desc.dfu_func.bmAttributes & 0x04U)
{
dfu->bState = STATE_DFU_MANIFEST_SYNC;
} else {
dfu->bState = STATE_DFU_MANIFEST_WAIT_RESET;
@ -334,18 +337,25 @@ static uint8_t dfu_getstatus_complete(usb_dev *udev)
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE];
if(STATE_DFU_DNBUSY == dfu->bState) {
if(STATE_DFU_DNBUSY == dfu->bState)
{
/* decode the special command */
if(0U == dfu->block_num) {
if(1U == dfu->data_len) {
if(GET_COMMANDS == dfu->buf[0]) {
if(0U == dfu->block_num)
{
if(1U == dfu->data_len)
{
if(GET_COMMANDS == dfu->buf[0])
{
/* no operation */
}
} else if(5U == dfu->data_len) {
if(SET_ADDRESS_POINTER == dfu->buf[0]) {
} else if(5U == dfu->data_len)
{
if(SET_ADDRESS_POINTER == dfu->buf[0])
{
/* set flash operation address */
dfu->base_addr = *(uint32_t *)(dfu->buf + 1U);
} else if(ERASE == dfu->buf[0]) {
} else if(ERASE == dfu->buf[0])
{
dfu->base_addr = *(uint32_t *)(dfu->buf + 1U);
dfu_mal_erase(dfu->base_addr);
@ -355,7 +365,8 @@ static uint8_t dfu_getstatus_complete(usb_dev *udev)
} else {
/* no operation */
}
} else if(dfu->block_num > 1U) { /* regular download command */
} else if(dfu->block_num > 1U)
{ /* regular download command */
/* decode the required address */
addr = (dfu->block_num - 2U) * TRANSFER_SIZE + dfu->base_addr;
@ -372,7 +383,8 @@ static uint8_t dfu_getstatus_complete(usb_dev *udev)
dfu->bState = STATE_DFU_DNLOAD_SYNC;
return USBD_OK;
} else if(STATE_DFU_MANIFEST == dfu->bState) { /* manifestation in progress */
} else if(STATE_DFU_MANIFEST == dfu->bState)
{ /* manifestation in progress */
/* start leaving DFU mode */
dfu_mode_leave(udev);
} else {
@ -393,7 +405,8 @@ static void dfu_detach(usb_dev *udev, usb_req *req)
{
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE];
switch(dfu->bState) {
switch(dfu->bState)
{
case STATE_DFU_IDLE:
case STATE_DFU_DNLOAD_SYNC:
case STATE_DFU_DNLOAD_IDLE:
@ -412,7 +425,8 @@ static void dfu_detach(usb_dev *udev, usb_req *req)
}
/* check the detach capability in the DFU functional descriptor */
if(dfu_config_desc.dfu_func.wDetachTimeOut & DFU_DETACH_MASK) {
if(dfu_config_desc.dfu_func.wDetachTimeOut & DFU_DETACH_MASK)
{
usbd_disconnect(udev);
usbd_connect(udev);
@ -434,10 +448,12 @@ static void dfu_dnload(usb_dev *udev, usb_req *req)
usb_transc *transc = &udev->dev.transc_out[0];
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE];
switch(dfu->bState) {
switch(dfu->bState)
{
case STATE_DFU_IDLE:
case STATE_DFU_DNLOAD_IDLE:
if(req->wLength > 0U) {
if(req->wLength > 0U)
{
/* update the global length and block number */
dfu->block_num = req->wValue;
dfu->data_len = req->wLength;
@ -472,12 +488,14 @@ static void dfu_upload(usb_dev *udev, usb_req *req)
usb_transc *transc = &udev->dev.transc_in[0];
if(req->wLength <= 0U) {
if(req->wLength <= 0U)
{
dfu->bState = STATE_DFU_IDLE;
return;
}
switch(dfu->bState) {
switch(dfu->bState)
{
case STATE_DFU_IDLE:
case STATE_DFU_UPLOAD_IDLE:
/* update the global length and block number */
@ -485,7 +503,8 @@ static void dfu_upload(usb_dev *udev, usb_req *req)
dfu->data_len = req->wLength;
/* DFU get command */
if(0U == dfu->block_num) {
if(0U == dfu->block_num)
{
/* update the state machine */
dfu->bState = (dfu->data_len > 3U) ? STATE_DFU_IDLE : STATE_DFU_UPLOAD_IDLE;
@ -497,7 +516,8 @@ static void dfu_upload(usb_dev *udev, usb_req *req)
/* send the status data over EP0 */
transc->xfer_buf = &(dfu->buf[0]);
transc->remain_len = 3U;
} else if(dfu->block_num > 1U) {
} else if(dfu->block_num > 1U)
{
dfu->bState = STATE_DFU_UPLOAD_IDLE;
/* change is accelerated */
@ -534,13 +554,17 @@ static void dfu_getstatus(usb_dev *udev, usb_req *req)
usb_transc *transc = &udev->dev.transc_in[0];
switch(dfu->bState) {
switch(dfu->bState)
{
case STATE_DFU_DNLOAD_SYNC:
if(0U != dfu->data_len) {
if(0U != dfu->data_len)
{
dfu->bState = STATE_DFU_DNBUSY;
if(0U == dfu->block_num) {
if(ERASE == dfu->buf[0]) {
if(0U == dfu->block_num)
{
if(ERASE == dfu->buf[0])
{
dfu_mal_getstatus(dfu->base_addr, CMD_ERASE, (uint8_t *)&dfu->bwPollTimeout0);
} else {
dfu_mal_getstatus(dfu->base_addr, CMD_WRITE, (uint8_t *)&dfu->bwPollTimeout0);
@ -552,11 +576,13 @@ static void dfu_getstatus(usb_dev *udev, usb_req *req)
break;
case STATE_DFU_MANIFEST_SYNC:
if(MANIFEST_IN_PROGRESS == dfu->manifest_state) {
if(MANIFEST_IN_PROGRESS == dfu->manifest_state)
{
dfu->bState = STATE_DFU_MANIFEST;
dfu->bwPollTimeout0 = 1U;
} else if((MANIFEST_COMPLETE == dfu->manifest_state) && \
(dfu_config_desc.dfu_func.bmAttributes & 0x04U)) {
(dfu_config_desc.dfu_func.bmAttributes & 0x04U))
{
dfu->bState = STATE_DFU_IDLE;
dfu->bwPollTimeout0 = 0U;
} else {
@ -583,7 +609,8 @@ static void dfu_clrstatus(usb_dev *udev, usb_req *req)
{
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE];
if(STATE_DFU_ERROR == dfu->bState) {
if(STATE_DFU_ERROR == dfu->bState)
{
dfu->bStatus = STATUS_OK;
dfu->bState = STATE_DFU_IDLE;
} else {
@ -622,7 +649,8 @@ static void dfu_abort(usb_dev *udev, usb_req *req)
{
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE];
switch(dfu->bState) {
switch(dfu->bState)
{
case STATE_DFU_IDLE:
case STATE_DFU_DNLOAD_SYNC:
case STATE_DFU_DNLOAD_IDLE:

42
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/dfu/Source/dfu_mal.c
View File

@ -69,9 +69,11 @@ uint8_t dfu_mal_init(void)
uint32_t mem_index = 0U;
/* initialize all supported memory medias */
for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) {
for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++)
{
/* check if the memory media exists */
if(NULL != tMALTab[mem_index]->mal_init) {
if(NULL != tMALTab[mem_index]->mal_init)
{
tMALTab[mem_index]->mal_init();
}
}
@ -90,9 +92,11 @@ uint8_t dfu_mal_deinit(void)
uint32_t mem_index = 0U;
/* deinitializes all supported memory medias */
for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) {
for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++)
{
/* check if the memory media exists */
if(NULL != tMALTab[mem_index]->mal_deinit) {
if(NULL != tMALTab[mem_index]->mal_deinit)
{
tMALTab[mem_index]->mal_deinit();
}
}
@ -110,9 +114,11 @@ uint8_t dfu_mal_erase(uint32_t addr)
{
uint32_t mem_index = dfu_mal_checkaddr(addr);
if(mem_index < MAX_USED_MEMORY_MEDIA) {
if(mem_index < MAX_USED_MEMORY_MEDIA)
{
/* check if the operation is supported */
if(NULL != tMALTab[mem_index]->mal_erase) {
if(NULL != tMALTab[mem_index]->mal_erase)
{
return tMALTab[mem_index]->mal_erase(addr);
} else {
return MAL_FAIL;
@ -134,9 +140,11 @@ uint8_t dfu_mal_write(uint8_t *buf, uint32_t addr, uint32_t len)
{
uint32_t mem_index = dfu_mal_checkaddr(addr);
if(mem_index < MAX_USED_MEMORY_MEDIA) {
if(mem_index < MAX_USED_MEMORY_MEDIA)
{
/* check if the operation is supported */
if(NULL != tMALTab[mem_index]->mal_write) {
if(NULL != tMALTab[mem_index]->mal_write)
{
return tMALTab[mem_index]->mal_write(buf, addr, len);
} else {
return MAL_FAIL;
@ -158,9 +166,11 @@ uint8_t *dfu_mal_read(uint8_t *buf, uint32_t addr, uint32_t len)
{
uint32_t mem_index = 0U;
if(mem_index < MAX_USED_MEMORY_MEDIA) {
if(mem_index < MAX_USED_MEMORY_MEDIA)
{
/* check if the operation is supported */
if(NULL != tMALTab[mem_index]->mal_read) {
if(NULL != tMALTab[mem_index]->mal_read)
{
return tMALTab[mem_index]->mal_read(buf, addr, len);
} else {
return buf;
@ -182,8 +192,10 @@ uint8_t dfu_mal_getstatus(uint32_t addr, uint8_t cmd, uint8_t *buffer)
{
uint32_t mem_index = dfu_mal_checkaddr(addr);
if(mem_index < MAX_USED_MEMORY_MEDIA) {
if(cmd & 0x01U) {
if(mem_index < MAX_USED_MEMORY_MEDIA)
{
if(cmd & 0x01U)
{
SET_POLLING_TIMEOUT(tMALTab[mem_index]->write_timeout);
} else {
SET_POLLING_TIMEOUT(tMALTab[mem_index]->erase_timeout);
@ -206,9 +218,11 @@ static uint8_t dfu_mal_checkaddr(uint32_t addr)
uint8_t mem_index = 0U;
/* check with all supported memories */
for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) {
for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++)
{
/* if the check address is supported, return the memory index */
if(MAL_OK == tMALTab[mem_index]->mal_checkaddr(addr)) {
if(MAL_OK == tMALTab[mem_index]->mal_checkaddr(addr))
{
return mem_index;
}
}

27
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/hid/Source/custom_hid_core.c
View File

@ -284,7 +284,8 @@ usb_class_core usbd_custom_hid_cb = {
*/
uint8_t custom_hid_itfop_register(usb_dev *udev, hid_fop_handler *hid_fop)
{
if(NULL != hid_fop) {
if(NULL != hid_fop)
{
udev->dev.user_data = hid_fop;
return USBD_OK;
@ -332,9 +333,12 @@ static uint8_t custom_hid_init(usb_dev *udev, uint8_t config_index)
udev->dev.class_data[CUSTOM_HID_INTERFACE] = (void *)&hid_handler;
if(udev->dev.user_data != NULL) {
for(uint8_t i = 0U; i < MAX_PERIPH_NUM; i++) {
if(((hid_fop_handler *)udev->dev.user_data)->periph_config[i] != NULL) {
if(udev->dev.user_data != NULL)
{
for(uint8_t i = 0U; i < MAX_PERIPH_NUM; i++)
{
if(((hid_fop_handler *)udev->dev.user_data)->periph_config[i] != NULL)
{
((hid_fop_handler *)udev->dev.user_data)->periph_config[i]();
}
}
@ -372,7 +376,8 @@ static uint8_t custom_hid_req_handler(usb_dev *udev, usb_req *req)
custom_hid_handler *hid = (custom_hid_handler *)udev->dev.class_data[CUSTOM_HID_INTERFACE];
switch(req->bRequest) {
switch(req->bRequest)
{
case GET_REPORT:
break;
@ -399,7 +404,8 @@ static uint8_t custom_hid_req_handler(usb_dev *udev, usb_req *req)
break;
case USB_GET_DESCRIPTOR:
if(USB_DESCTYPE_REPORT == (req->wValue >> 8U)) {
if(USB_DESCTYPE_REPORT == (req->wValue >> 8U))
{
transc->remain_len = USB_MIN(DESC_LEN_REPORT, req->wLength);
transc->xfer_buf = (uint8_t *)customhid_report_descriptor;
}
@ -435,9 +441,11 @@ static uint8_t custom_hid_data_out(usb_dev *udev, uint8_t ep_num)
{
custom_hid_handler *hid = (custom_hid_handler *)udev->dev.class_data[CUSTOM_HID_INTERFACE];
switch(hid->data[0]) {
switch(hid->data[0])
{
case 0x11U:
if(RESET != hid->data[1]) {
if(RESET != hid->data[1])
{
gd_eval_led_on(LED1);
} else {
gd_eval_led_off(LED1);
@ -445,7 +453,8 @@ static uint8_t custom_hid_data_out(usb_dev *udev, uint8_t ep_num)
break;
case 0x12U:
if(RESET != hid->data[1]) {
if(RESET != hid->data[1])
{
gd_eval_led_on(LED2);
} else {
gd_eval_led_off(LED2);

18
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/hid/Source/standard_hid_core.c
View File

@ -334,7 +334,8 @@ usb_class_core usbd_hid_cb = {
*/
uint8_t hid_itfop_register(usb_dev *udev, hid_fop_handler *hid_fop)
{
if(NULL != hid_fop) {
if(NULL != hid_fop)
{
udev->dev.user_data = (void *)hid_fop;
return USBD_OK;
@ -382,7 +383,8 @@ static uint8_t hid_init(usb_dev *udev, uint8_t config_index)
udev->dev.class_data[USBD_HID_INTERFACE] = (void *)&hid_handler;
if(NULL != udev->dev.user_data) {
if(NULL != udev->dev.user_data)
{
((hid_fop_handler *)udev->dev.user_data)->hid_itf_config();
}
@ -417,7 +419,8 @@ static uint8_t hid_req(usb_dev *udev, usb_req *req)
standard_hid_handler *hid = (standard_hid_handler *)udev->dev.class_data[USBD_HID_INTERFACE];
switch(req->bRequest) {
switch(req->bRequest)
{
case GET_REPORT:
/* no use for this driver */
break;
@ -447,12 +450,14 @@ static uint8_t hid_req(usb_dev *udev, usb_req *req)
break;
case USB_GET_DESCRIPTOR:
if(USB_DESCTYPE_REPORT == (req->wValue >> 8U)) {
if(USB_DESCTYPE_REPORT == (req->wValue >> 8U))
{
transc->remain_len = USB_MIN(USB_HID_REPORT_DESC_LEN, req->wLength);
transc->xfer_buf = (uint8_t *)hid_report_desc;
return REQ_SUPP;
} else if(USB_DESCTYPE_HID == (req->wValue >> 8U)) {
} else if(USB_DESCTYPE_HID == (req->wValue >> 8U))
{
transc->remain_len = USB_MIN(9U, req->wLength);
transc->xfer_buf = (uint8_t *)(&(hid_config_desc.hid_vendor));
}
@ -476,7 +481,8 @@ static uint8_t hid_data_in(usb_dev *udev, uint8_t ep_num)
{
standard_hid_handler *hid = (standard_hid_handler *)udev->dev.class_data[USBD_HID_INTERFACE];
if(0U != hid->data[2]) {
if(0U != hid->data[2])
{
hid->data[2] = 0x00U;
usbd_ep_send(udev, HID_IN_EP, hid->data, HID_IN_PACKET);

21
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/hid/Source/std_hid_mouse_core.c
View File

@ -232,7 +232,8 @@ usb_class_core usbd_hid_cb = {
*/
uint8_t hid_itfop_register(usb_dev *udev, mice_fop_handler *hid_fop)
{
if(NULL != hid_fop) {
if(NULL != hid_fop)
{
udev->dev.user_data = (void *)hid_fop;
return USBD_OK;
@ -253,8 +254,10 @@ uint8_t hid_report_send(usb_dev *udev, uint8_t *report, uint16_t len)
{
standard_mice_handler *hid = (standard_mice_handler *)udev->dev.class_data[USBD_HID_INTERFACE];
if(USBD_CONFIGURED == udev->dev.cur_status) {
if(1 == hid->prev_transfer_complete) {
if(USBD_CONFIGURED == udev->dev.cur_status)
{
if(1 == hid->prev_transfer_complete)
{
hid->prev_transfer_complete = 0U;
usbd_ep_send(udev, HID_IN_EP, report, len);
}
@ -283,7 +286,8 @@ static uint8_t hid_init(usb_dev *udev, uint8_t config_index)
udev->dev.class_data[USBD_HID_INTERFACE] = (void *)&mice_handler;
if(NULL != udev->dev.user_data) {
if(NULL != udev->dev.user_data)
{
((mice_fop_handler *)(udev->dev.user_data))->mice_itf_config();
}
@ -318,7 +322,8 @@ static uint8_t hid_req(usb_dev *udev, usb_req *req)
standard_mice_handler *hid = (standard_mice_handler *)udev->dev.class_data[USBD_HID_INTERFACE];
switch(req->bRequest) {
switch(req->bRequest)
{
case GET_REPORT:
/* no use for this driver */
break;
@ -348,7 +353,8 @@ static uint8_t hid_req(usb_dev *udev, usb_req *req)
break;
case USB_GET_DESCRIPTOR:
if(USB_DESCTYPE_REPORT == (req->wValue >> 8U)) {
if(USB_DESCTYPE_REPORT == (req->wValue >> 8U))
{
transc->remain_len = USB_MIN(USB_HID_REPORT_DESC_LEN, req->wLength);
transc->xfer_buf = (uint8_t *)hid_report_desc;
@ -374,7 +380,8 @@ static uint8_t hid_data_in(usb_dev *udev, uint8_t ep_num)
{
standard_mice_handler *hid = (standard_mice_handler *)udev->dev.class_data[USBD_HID_INTERFACE];
if(0U == hid->data[0]) {
if(0U == hid->data[0])
{
hid->prev_transfer_complete = 1U;
} else {
hid->data[0] = 0U;

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/iap/Source/usb_iap_core.c
View File

@ -316,7 +316,8 @@ static uint8_t iap_req_handler(usb_dev *udev, usb_req *req)
usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];
switch(req->bRequest) {
switch(req->bRequest)
{
case GET_REPORT:
/* no use for this driver */
break;
@ -344,7 +345,8 @@ static uint8_t iap_req_handler(usb_dev *udev, usb_req *req)
break;
case USB_GET_DESCRIPTOR:
if(USB_DESCTYPE_REPORT == (req->wValue >> 8U)) {
if(USB_DESCTYPE_REPORT == (req->wValue >> 8U))
{
transc->remain_len = USB_MIN(USB_DESC_LEN_IAP_REPORT, req->wLength);
transc->xfer_buf = (uint8_t *)iap_report_desc;
}
@ -368,8 +370,10 @@ static uint8_t iap_data_out(usb_dev *udev, uint8_t ep_num)
{
usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];
if(0x01U == iap->report_buf[0]) {
switch(iap->report_buf[1]) {
if(0x01U == iap->report_buf[0])
{
switch(iap->report_buf[1])
{
case IAP_DNLOAD:
iap_req_dnload(udev);
break;
@ -414,8 +418,10 @@ static void iap_req_dnload(usb_dev *udev)
{
usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];
if(0U != iap->transfer_times) {
if(1U == iap->transfer_times) {
if(0U != iap->transfer_times)
{
if(1U == iap->transfer_times)
{
iap_data_write(&iap->report_buf[2], iap->base_address, iap->file_length % TRANSFER_SIZE);
iap->dev_status[0] = 0x02U;
@ -455,14 +461,16 @@ static void iap_req_erase(usb_dev *udev)
iap->file_length |= (uint32_t)iap->report_buf[9] << 16U;
iap->file_length |= (uint32_t)iap->report_buf[10] << 24U;
if(0U == (iap->file_length % TRANSFER_SIZE)) {
if(0U == (iap->file_length % TRANSFER_SIZE))
{
iap->transfer_times = (uint16_t)(iap->file_length / TRANSFER_SIZE);
} else {
iap->transfer_times = (uint16_t)(iap->file_length / TRANSFER_SIZE + 1U);
}
/* check if the address is in protected area */
if(IS_PROTECTED_AREA(iap->base_address)) {
if(IS_PROTECTED_AREA(iap->base_address))
{
return;
}
@ -497,7 +505,8 @@ static void iap_req_optionbyte(usb_dev *udev, uint8_t option_num)
iap->option_byte[0] = 0x02U;
if(0x01U == option_num) {
if(0x01U == option_num)
{
address = OPT_BYTE_ADDR;
} else {
return;
@ -505,7 +514,8 @@ static void iap_req_optionbyte(usb_dev *udev, uint8_t option_num)
opt_count = REPORT_IN_COUNT / 4;
for(i = 0U; i < opt_count; i++) {
for(i = 0U; i < opt_count; i++)
{
ob = REG32(address + 4 * i);
iap->option_byte[1 + 4 * i] = (uint8_t)ob;

42
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/msc/Source/usbd_msc_bbb.c
View File

@ -56,7 +56,8 @@ void msc_bbb_init (usb_core_driver *udev)
msc->bbb_status = BBB_STATUS_NORMAL;
/* initializes the storage logic unit */
for(lun_num = 0U; lun_num < MEM_LUN_NUM; lun_num++) {
for(lun_num = 0U; lun_num < MEM_LUN_NUM; lun_num++)
{
usbd_mem_fops->mem_init(lun_num);
}
@ -111,9 +112,11 @@ void msc_bbb_data_in (usb_core_driver *udev, uint8_t ep_num)
{
usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE];
switch (msc->bbb_state) {
switch (msc->bbb_state)
{
case BBB_DATA_IN:
if (scsi_process_cmd (udev, msc->bbb_cbw.bCBWLUN, &msc->bbb_cbw.CBWCB[0]) < 0) {
if (scsi_process_cmd (udev, msc->bbb_cbw.bCBWLUN, &msc->bbb_cbw.CBWCB[0]) < 0)
{
msc_bbb_csw_send (udev, CSW_CMD_FAILED);
}
break;
@ -139,13 +142,15 @@ void msc_bbb_data_out (usb_core_driver *udev, uint8_t ep_num)
{
usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE];
switch (msc->bbb_state) {
switch (msc->bbb_state)
{
case BBB_IDLE:
msc_bbb_cbw_decode (udev);
break;
case BBB_DATA_OUT:
if (scsi_process_cmd (udev, msc->bbb_cbw.bCBWLUN, &msc->bbb_cbw.CBWCB[0]) < 0) {
if (scsi_process_cmd (udev, msc->bbb_cbw.bCBWLUN, &msc->bbb_cbw.CBWCB[0]) < 0)
{
msc_bbb_csw_send (udev, CSW_CMD_FAILED);
}
break;
@ -187,11 +192,13 @@ void msc_bbb_clrfeature (usb_core_driver *udev, uint8_t ep_num)
{
usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE];
if (BBB_STATUS_ERROR == msc->bbb_status)/* bad CBW signature */ {
if (BBB_STATUS_ERROR == msc->bbb_status)/* bad CBW signature */
{
usbd_ep_stall(udev, MSC_IN_EP);
msc->bbb_status = BBB_STATUS_NORMAL;
} else if((0x80U == (ep_num & 0x80U)) && (BBB_STATUS_RECOVERY != msc->bbb_status)) {
} else if((0x80U == (ep_num & 0x80U)) && (BBB_STATUS_RECOVERY != msc->bbb_status))
{
msc_bbb_csw_send (udev, CSW_CMD_FAILED);
} else {
@ -215,7 +222,8 @@ static void msc_bbb_cbw_decode (usb_core_driver *udev)
(BBB_CBW_SIGNATURE != msc->bbb_cbw.dCBWSignature)||
(msc->bbb_cbw.bCBWLUN > 1U) ||
(msc->bbb_cbw.bCBWCBLength < 1U) ||
(msc->bbb_cbw.bCBWCBLength > 16U)) {
(msc->bbb_cbw.bCBWCBLength > 16U))
{
/* illegal command handler */
scsi_sense_code (udev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB);
@ -223,14 +231,18 @@ static void msc_bbb_cbw_decode (usb_core_driver *udev)
msc_bbb_abort (udev);
} else {
if (scsi_process_cmd (udev, msc->bbb_cbw.bCBWLUN, &msc->bbb_cbw.CBWCB[0]) < 0) {
if (scsi_process_cmd (udev, msc->bbb_cbw.bCBWLUN, &msc->bbb_cbw.CBWCB[0]) < 0)
{
msc_bbb_abort (udev);
} else if ((BBB_DATA_IN != msc->bbb_state) &&
(BBB_DATA_OUT != msc->bbb_state) &&
(BBB_LAST_DATA_IN != msc->bbb_state)) { /* burst xfer handled internally */
if (msc->bbb_datalen > 0U) {
(BBB_LAST_DATA_IN != msc->bbb_state))
{ /* burst xfer handled internally */
if (msc->bbb_datalen > 0U)
{
msc_bbb_data_send (udev, msc->bbb_data, msc->bbb_datalen);
} else if (0U == msc->bbb_datalen) {
} else if (0U == msc->bbb_datalen)
{
msc_bbb_csw_send (udev, CSW_CMD_PASSED);
} else {
@ -274,13 +286,15 @@ static void msc_bbb_abort (usb_core_driver *udev)
if ((0U == msc->bbb_cbw.bmCBWFlags) &&
(0U != msc->bbb_cbw.dCBWDataTransferLength) &&
(BBB_STATUS_NORMAL == msc->bbb_status)) {
(BBB_STATUS_NORMAL == msc->bbb_status))
{
usbd_ep_stall(udev, MSC_OUT_EP);
}
usbd_ep_stall(udev, MSC_IN_EP);
if (msc->bbb_status == BBB_STATUS_ERROR) {
if (msc->bbb_status == BBB_STATUS_ERROR)
{
usbd_ep_recev (udev, MSC_OUT_EP, (uint8_t *)&msc->bbb_cbw, BBB_CBW_LENGTH);
}
}

9
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/msc/Source/usbd_msc_core.c
View File

@ -329,11 +329,13 @@ static uint8_t msc_core_req (usb_dev *udev, usb_req *req)
{
usb_transc *transc = &udev->dev.transc_in[0];
switch (req->bRequest) {
switch (req->bRequest)
{
case BBB_GET_MAX_LUN :
if((0U == req->wValue) &&
(1U == req->wLength) &&
(0x80U == (req->bmRequestType & 0x80U))) {
(0x80U == (req->bmRequestType & 0x80U)))
{
usbd_msc_maxlun = (uint8_t)usbd_mem_fops->mem_maxlun();
transc->xfer_buf = &usbd_msc_maxlun;
@ -346,7 +348,8 @@ static uint8_t msc_core_req (usb_dev *udev, usb_req *req)
case BBB_RESET :
if((0U == req->wValue) &&
(0U == req->wLength) &&
(0x80U != (req->bmRequestType & 0x80U))) {
(0x80U != (req->bmRequestType & 0x80U)))
{
msc_bbb_reset(udev);
} else {
return USBD_FAIL;

6
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/msc/Source/usbd_msc_efs.c
View File

@ -65,7 +65,8 @@ int8_t if_readBuf(hwInterface* file, uint32_t address, uint8_t* buf)
{
int8_t status = EFS_ERROR;
if (0U == usbd_mem_fops->mem_read(0U, buf, address, 1U)) {
if (0U == usbd_mem_fops->mem_read(0U, buf, address, 1U))
{
status = EFS_PASS;
}
@ -84,7 +85,8 @@ int8_t if_writeBuf(hwInterface* file, uint32_t address, uint8_t* buf)
{
int8_t status = EFS_ERROR;
if (0U == usbd_mem_fops->mem_write(0U, buf, address, 1U)) {
if (0U == usbd_mem_fops->mem_write(0U, buf, address, 1U))
{
status = EFS_PASS;
}

96
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/msc/Source/usbd_msc_scsi.c
View File

@ -70,7 +70,8 @@ static inline int8_t scsi_allow_medium_removal (usb_core_driver *udev, uint8_t l
*/
int8_t scsi_process_cmd(usb_core_driver *udev, uint8_t lun, uint8_t *params)
{
switch (params[0]) {
switch (params[0])
{
case SCSI_TEST_UNIT_READY:
return scsi_test_unit_ready (udev, lun, params);
@ -142,7 +143,8 @@ void scsi_sense_code (usb_core_driver *udev, uint8_t lun, uint8_t skey, uint8_t
msc->scsi_sense[msc->scsi_sense_tail].ASC = asc;
msc->scsi_sense_tail++;
if (SENSE_LIST_DEEPTH == msc->scsi_sense_tail) {
if (SENSE_LIST_DEEPTH == msc->scsi_sense_tail)
{
msc->scsi_sense_tail = 0U;
}
}
@ -160,13 +162,15 @@ static int8_t scsi_test_unit_ready (usb_core_driver *udev, uint8_t lun, uint8_t
usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE];
/* case 9 : Hi > D0 */
if (0U != msc->bbb_cbw.dCBWDataTransferLength) {
if (0U != msc->bbb_cbw.dCBWDataTransferLength)
{
scsi_sense_code (udev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB);
return -1;
}
if (0 != usbd_mem_fops->mem_ready(lun)) {
if (0 != usbd_mem_fops->mem_ready(lun))
{
scsi_sense_code(udev, lun, NOT_READY, MEDIUM_NOT_PRESENT);
return -1;
@ -226,7 +230,8 @@ static int8_t scsi_inquiry (usb_core_driver *udev, uint8_t lun, uint8_t *params)
usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE];
if (params[1] & 0x01U) {
if (params[1] & 0x01U)
{
page = (uint8_t *)msc_page00_inquiry_data;
len = INQUIRY_PAGE00_LENGTH;
@ -235,14 +240,16 @@ static int8_t scsi_inquiry (usb_core_driver *udev, uint8_t lun, uint8_t *params)
len = (uint16_t)(page[4] + 5U);
if (params[4] <= len) {
if (params[4] <= len)
{
len = params[4];
}
}
msc->bbb_datalen = len;
while (len) {
while (len)
{
len--;
msc->bbb_data[len] = page[len];
}
@ -298,7 +305,8 @@ static int8_t scsi_read_format_capacity (usb_core_driver *udev, uint8_t lun, uin
usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE];
for (i = 0U; i < 12U; i++) {
for (i = 0U; i < 12U; i++)
{
msc->bbb_data[i] = 0U;
}
@ -333,7 +341,8 @@ static int8_t scsi_mode_sense6 (usb_core_driver *udev, uint8_t lun, uint8_t *par
msc->bbb_datalen = len;
while (len) {
while (len)
{
len--;
msc->bbb_data[len] = msc_mode_sense6_data[len];
}
@ -356,7 +365,8 @@ static int8_t scsi_mode_sense10 (usb_core_driver *udev, uint8_t lun, uint8_t *pa
msc->bbb_datalen = len;
while (len) {
while (len)
{
len--;
msc->bbb_data[len] = msc_mode_sense10_data[len];
}
@ -377,20 +387,23 @@ static int8_t scsi_request_sense (usb_core_driver *udev, uint8_t lun, uint8_t *p
uint8_t i = 0U;
usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE];
for (i = 0U; i < REQUEST_SENSE_DATA_LEN; i++) {
for (i = 0U; i < REQUEST_SENSE_DATA_LEN; i++)
{
msc->bbb_data[i] = 0U;
}
msc->bbb_data[0] = 0x70U;
msc->bbb_data[7] = REQUEST_SENSE_DATA_LEN - 6U;
if ((msc->scsi_sense_head != msc->scsi_sense_tail)) {
if ((msc->scsi_sense_head != msc->scsi_sense_tail))
{
msc->bbb_data[2] = msc->scsi_sense[msc->scsi_sense_head].SenseKey;
msc->bbb_data[12] = msc->scsi_sense[msc->scsi_sense_head].ASC;
msc->bbb_data[13] = msc->scsi_sense[msc->scsi_sense_head].ASCQ;
msc->scsi_sense_head++;
if (msc->scsi_sense_head == SENSE_LIST_DEEPTH) {
if (msc->scsi_sense_head == SENSE_LIST_DEEPTH)
{
msc->scsi_sense_head = 0U;
}
}
@ -447,15 +460,18 @@ static int8_t scsi_read10 (usb_core_driver *udev, uint8_t lun, uint8_t *params)
{
usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE];
if (BBB_IDLE == msc->bbb_state) {
if (BBB_IDLE == msc->bbb_state)
{
/* direction is from device to host */
if (0x80U != (msc->bbb_cbw.bmCBWFlags & 0x80U)) {
if (0x80U != (msc->bbb_cbw.bmCBWFlags & 0x80U))
{
scsi_sense_code (udev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB);
return -1;
}
if (0 != usbd_mem_fops->mem_ready(lun)) {
if (0 != usbd_mem_fops->mem_ready(lun))
{
scsi_sense_code (udev, lun, NOT_READY, MEDIUM_NOT_PRESENT);
return -1;
@ -466,7 +482,8 @@ static int8_t scsi_read10 (usb_core_driver *udev, uint8_t lun, uint8_t *params)
msc->scsi_blk_len = (params[7] << 8U) | params[8];
if (scsi_check_address_range (udev, lun, msc->scsi_blk_addr, (uint16_t)msc->scsi_blk_len) < 0) {
if (scsi_check_address_range (udev, lun, msc->scsi_blk_addr, (uint16_t)msc->scsi_blk_len) < 0)
{
return -1; /* error */
}
@ -476,7 +493,8 @@ static int8_t scsi_read10 (usb_core_driver *udev, uint8_t lun, uint8_t *params)
msc->scsi_blk_len *= msc->scsi_blk_size[lun];
/* cases 4,5 : Hi <> Dn */
if (msc->bbb_cbw.dCBWDataTransferLength != msc->scsi_blk_len) {
if (msc->bbb_cbw.dCBWDataTransferLength != msc->scsi_blk_len)
{
scsi_sense_code (udev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB);
return -1;
@ -500,23 +518,27 @@ static int8_t scsi_write10 (usb_core_driver *udev, uint8_t lun, uint8_t *params)
{
usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE];
if (BBB_IDLE == msc->bbb_state) {
if (BBB_IDLE == msc->bbb_state)
{
/* case 8 : Hi <> Do */
if (0x80U == (msc->bbb_cbw.bmCBWFlags & 0x80U)) {
if (0x80U == (msc->bbb_cbw.bmCBWFlags & 0x80U))
{
scsi_sense_code (udev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB);
return -1;
}
/* check whether media is ready */
if (0 != usbd_mem_fops->mem_ready(lun)) {
if (0 != usbd_mem_fops->mem_ready(lun))
{
scsi_sense_code (udev, lun, NOT_READY, MEDIUM_NOT_PRESENT);
return -1;
}
/* check if media is write-protected */
if (0 != usbd_mem_fops->mem_protected(lun)) {
if (0 != usbd_mem_fops->mem_protected(lun))
{
scsi_sense_code (udev, lun, NOT_READY, WRITE_PROTECTED);
return -1;
@ -528,7 +550,8 @@ static int8_t scsi_write10 (usb_core_driver *udev, uint8_t lun, uint8_t *params)
msc->scsi_blk_len = (params[7] << 8U) | params[8];
/* check if LBA address is in the right range */
if (scsi_check_address_range (udev, lun, msc->scsi_blk_addr, (uint16_t)msc->scsi_blk_len) < 0) {
if (scsi_check_address_range (udev, lun, msc->scsi_blk_addr, (uint16_t)msc->scsi_blk_len) < 0)
{
return -1; /* error */
}
@ -536,7 +559,8 @@ static int8_t scsi_write10 (usb_core_driver *udev, uint8_t lun, uint8_t *params)
msc->scsi_blk_len *= msc->scsi_blk_size[lun];
/* cases 3,11,13 : Hn,Ho <> D0 */
if (msc->bbb_cbw.dCBWDataTransferLength != msc->scsi_blk_len) {
if (msc->bbb_cbw.dCBWDataTransferLength != msc->scsi_blk_len)
{
scsi_sense_code (udev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB);
return -1;
@ -568,13 +592,15 @@ static int8_t scsi_verify10 (usb_core_driver *udev, uint8_t lun, uint8_t *params
{
usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE];
if (0x02U == (params[1] & 0x02U)) {
if (0x02U == (params[1] & 0x02U))
{
scsi_sense_code (udev, lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
return -1; /* error, verify mode not supported*/
}
if (scsi_check_address_range (udev, lun, msc->scsi_blk_addr, (uint16_t)msc->scsi_blk_len) < 0) {
if (scsi_check_address_range (udev, lun, msc->scsi_blk_addr, (uint16_t)msc->scsi_blk_len) < 0)
{
return -1; /* error */
}
@ -596,7 +622,8 @@ static inline int8_t scsi_check_address_range (usb_core_driver *udev, uint8_t lu
{
usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE];
if ((blk_offset + blk_nbr) > msc->scsi_blk_nbr[lun]) {
if ((blk_offset + blk_nbr) > msc->scsi_blk_nbr[lun])
{
scsi_sense_code (udev, lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE);
return -1;
@ -621,7 +648,8 @@ static int8_t scsi_process_read (usb_core_driver *udev, uint8_t lun)
if (usbd_mem_fops->mem_read(lun,
msc->bbb_data,
msc->scsi_blk_addr,
(uint16_t)(len / msc->scsi_blk_size[lun])) < 0) {
(uint16_t)(len / msc->scsi_blk_size[lun])) < 0)
{
scsi_sense_code(udev, lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR);
return -1;
@ -635,7 +663,8 @@ static int8_t scsi_process_read (usb_core_driver *udev, uint8_t lun)
/* case 6 : Hi = Di */
msc->bbb_csw.dCSWDataResidue -= len;
if (0U == msc->scsi_blk_len) {
if (0U == msc->scsi_blk_len)
{
msc->bbb_state = BBB_LAST_DATA_IN;
}
@ -658,7 +687,8 @@ static int8_t scsi_process_write (usb_core_driver *udev, uint8_t lun)
if (usbd_mem_fops->mem_write (lun,
msc->bbb_data,
msc->scsi_blk_addr,
(uint16_t)(len / msc->scsi_blk_size[lun])) < 0) {
(uint16_t)(len / msc->scsi_blk_size[lun])) < 0)
{
scsi_sense_code(udev, lun, HARDWARE_ERROR, WRITE_FAULT);
return -1;
@ -670,7 +700,8 @@ static int8_t scsi_process_write (usb_core_driver *udev, uint8_t lun)
/* case 12 : Ho = Do */
msc->bbb_csw.dCSWDataResidue -= len;
if (0U == msc->scsi_blk_len) {
if (0U == msc->scsi_blk_len)
{
msc_bbb_csw_send (udev, CSW_CMD_PASSED);
} else {
/* prepare endpoint to receive next packet */
@ -715,7 +746,8 @@ static int8_t scsi_toc_cmd_read (usb_core_driver *udev, uint8_t lun, uint8_t *pa
msc->bbb_datalen = len;
while (len) {
while (len)
{
len--;
msc->bbb_data[len] = pPage[len];
}

3
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/class/printer/Source/printer_core.c
View File

@ -255,7 +255,8 @@ static uint8_t printer_req(usb_dev *udev, usb_req *req)
{
usb_transc *transc = &udev->dev.transc_in[0];
switch(req->bRequest) {
switch(req->bRequest)
{
case GET_DEVICE_ID:
transc->xfer_buf = (uint8_t *)PRINTER_DEVICE_ID;
transc->remain_len = DEVICE_ID_LEN;

21
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/core/Source/usbd_core.c
View File

@ -95,7 +95,8 @@ uint32_t usbd_ep_setup(usb_core_driver *udev, const usb_desc_ep *ep_desc)
uint16_t max_len = ep_desc->wMaxPacketSize;
/* set endpoint direction */
if(EP_DIR(ep_addr)) {
if(EP_DIR(ep_addr))
{
transc = &udev->dev.transc_in[EP_ID(ep_addr)];
transc->ep_addr.dir = 1U;
@ -129,7 +130,8 @@ uint32_t usbd_ep_clear(usb_core_driver *udev, uint8_t ep_addr)
{
usb_transc *transc;
if(EP_DIR(ep_addr)) {
if(EP_DIR(ep_addr))
{
transc = &udev->dev.transc_in[EP_ID(ep_addr)];
} else {
transc = &udev->dev.transc_out[ep_addr];
@ -162,7 +164,8 @@ uint32_t usbd_ep_recev(usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, ui
transc->xfer_len = len;
transc->xfer_count = 0U;
if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode)
{
transc->dma_addr = (uint32_t)pbuf;
}
@ -193,7 +196,8 @@ uint32_t usbd_ep_send(usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uin
transc->xfer_len = len;
transc->xfer_count = 0U;
if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode)
{
transc->dma_addr = (uint32_t)pbuf;
}
@ -217,7 +221,8 @@ uint32_t usbd_ep_stall(usb_core_driver *udev, uint8_t ep_addr)
{
usb_transc *transc = NULL;
if(EP_DIR(ep_addr)) {
if(EP_DIR(ep_addr))
{
transc = &udev->dev.transc_in[EP_ID(ep_addr)];
} else {
transc = &udev->dev.transc_out[ep_addr];
@ -244,7 +249,8 @@ uint32_t usbd_ep_stall_clear(usb_core_driver *udev, uint8_t ep_addr)
{
usb_transc *transc = NULL;
if(EP_DIR(ep_addr)) {
if(EP_DIR(ep_addr))
{
transc = &udev->dev.transc_in[EP_ID(ep_addr)];
} else {
transc = &udev->dev.transc_out[ep_addr];
@ -269,7 +275,8 @@ uint32_t usbd_ep_stall_clear(usb_core_driver *udev, uint8_t ep_addr)
*/
uint32_t usbd_fifo_flush(usb_core_driver *udev, uint8_t ep_addr)
{
if(EP_DIR(ep_addr)) {
if(EP_DIR(ep_addr))
{
(void)usb_txfifo_flush(&udev->regs, EP_ID(ep_addr));
} else {
(void)usb_rxfifo_flush(&udev->regs);

153
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/core/Source/usbd_enum.c
View File

@ -64,7 +64,8 @@ static uint8_t *_usb_other_speed_config_desc_get(usb_core_driver *udev, uint8_t
static uint8_t *_usb_qualifier_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len);
#endif
static usb_reqsta(*_std_dev_req[])(usb_core_driver *udev, usb_req *req) = {
static usb_reqsta(*_std_dev_req[])(usb_core_driver *udev, usb_req *req)=
{
[USB_GET_STATUS] = _usb_std_getstatus,
[USB_CLEAR_FEATURE] = _usb_std_clearfeature,
[USB_RESERVED2] = _usb_std_reserved,
@ -81,7 +82,8 @@ static usb_reqsta(*_std_dev_req[])(usb_core_driver *udev, usb_req *req) = {
};
/* get standard descriptor handler */
static uint8_t *(*std_desc_get[])(usb_core_driver *udev, uint8_t index, uint16_t *len) = {
static uint8_t *(*std_desc_get[])(usb_core_driver *udev, uint8_t index, uint16_t *len)=
{
[(uint8_t)USB_DESCTYPE_DEV - 1U] = _usb_dev_desc_get,
[(uint8_t)USB_DESCTYPE_CONFIG - 1U] = _usb_config_desc_get,
[(uint8_t)USB_DESCTYPE_STR - 1U] = _usb_str_desc_get,
@ -112,8 +114,10 @@ usb_reqsta usbd_standard_request(usb_core_driver *udev, usb_req *req)
*/
usb_reqsta usbd_class_request(usb_core_driver *udev, usb_req *req)
{
if((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) {
if(BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) {
if((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)
{
if(BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM)
{
/* call device class handle function */
return (usb_reqsta)udev->dev.class_core->req_proc(udev, req);
}
@ -171,8 +175,10 @@ void int_to_unicode(uint32_t value, uint8_t *pbuf, uint8_t len)
{
uint8_t index;
for(index = 0U; index < len; index++) {
if((value >> 28U) < 0x0AU) {
for(index = 0U; index < len; index++)
{
if((value >> 28U) < 0x0AU)
{
pbuf[2U * index] = (uint8_t)((value >> 28U) + '0');
} else {
pbuf[2U * index] = (uint8_t)((value >> 28U) + 'A' - 10U);
@ -192,7 +198,8 @@ void int_to_unicode(uint32_t value, uint8_t *pbuf, uint8_t len)
*/
void serial_string_get(uint16_t *unicode_str)
{
if((unicode_str[0] & 0x00FFU) != 6U) {
if((unicode_str[0] & 0x00FFU) != 6U)
{
uint32_t DeviceSerial0, DeviceSerial1, DeviceSerial2;
DeviceSerial0 = *(uint32_t *)DEVICE_ID1;
@ -201,14 +208,16 @@ void serial_string_get(uint16_t *unicode_str)
DeviceSerial0 += DeviceSerial2;
if(0U != DeviceSerial0) {
if(0U != DeviceSerial0)
{
int_to_unicode(DeviceSerial0, (uint8_t *) & (unicode_str[1]), 8U);
int_to_unicode(DeviceSerial1, (uint8_t *) & (unicode_str[9]), 4U);
}
} else {
uint32_t device_serial = *(uint32_t *)DEVICE_ID;
if(0U != device_serial) {
if(0U != device_serial)
{
unicode_str[1] = (uint16_t)(device_serial & 0x0000FFFFU);
unicode_str[2] = (uint16_t)((device_serial & 0xFFFF0000U) >> 16U);
@ -346,18 +355,22 @@ static usb_reqsta _usb_std_getstatus(usb_core_driver *udev, usb_req *req)
static uint8_t status[2] = {0};
switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) {
switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK)
{
case USB_RECPTYPE_DEV:
if(((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \
((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) {
((uint8_t)USBD_CONFIGURED == udev->dev.cur_status))
{
if(udev->dev.pm.power_mode) {
if(udev->dev.pm.power_mode)
{
status[0] = USB_STATUS_SELF_POWERED;
} else {
status[0] = 0U;
}
if(udev->dev.pm.dev_remote_wakeup) {
if(udev->dev.pm.dev_remote_wakeup)
{
status[0] |= USB_STATUS_REMOTE_WAKEUP;
} else {
status[0] = 0U;
@ -368,14 +381,17 @@ static usb_reqsta _usb_std_getstatus(usb_core_driver *udev, usb_req *req)
break;
case USB_RECPTYPE_ITF:
if(((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) && (recp <= USBD_ITF_MAX_NUM)) {
if(((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) && (recp <= USBD_ITF_MAX_NUM))
{
req_status = REQ_SUPP;
}
break;
case USB_RECPTYPE_EP:
if((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) {
if(0x80U == (recp & 0x80U)) {
if((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)
{
if(0x80U == (recp & 0x80U))
{
status[0] = udev->dev.transc_in[EP_ID(recp)].ep_stall;
} else {
status[0] = udev->dev.transc_out[recp].ep_stall;
@ -389,7 +405,8 @@ static usb_reqsta _usb_std_getstatus(usb_core_driver *udev, usb_req *req)
break;
}
if(REQ_SUPP == req_status) {
if(REQ_SUPP == req_status)
{
transc->xfer_buf = status;
transc->remain_len = 2U;
}
@ -408,13 +425,16 @@ static usb_reqsta _usb_std_clearfeature(usb_core_driver *udev, usb_req *req)
{
uint8_t ep = 0U;
switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) {
switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK)
{
case USB_RECPTYPE_DEV:
if(((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \
((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) {
((uint8_t)USBD_CONFIGURED == udev->dev.cur_status))
{
/* clear device remote wakeup feature */
if((uint16_t)USB_FEATURE_REMOTE_WAKEUP == req->wValue) {
if((uint16_t)USB_FEATURE_REMOTE_WAKEUP == req->wValue)
{
udev->dev.pm.dev_remote_wakeup = 0U;
return REQ_SUPP;
@ -429,9 +449,11 @@ static usb_reqsta _usb_std_clearfeature(usb_core_driver *udev, usb_req *req)
/* get endpoint address */
ep = BYTE_LOW(req->wIndex);
if((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) {
if((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)
{
/* clear endpoint halt feature */
if(((uint16_t)USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) {
if(((uint16_t)USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep)))
{
(void)usbd_ep_stall_clear(udev, ep);
(void)udev->dev.class_core->req_proc(udev, req);
@ -459,12 +481,15 @@ static usb_reqsta _usb_std_setfeature(usb_core_driver *udev, usb_req *req)
{
uint8_t ep = 0U;
switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) {
switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK)
{
case USB_RECPTYPE_DEV:
if(((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \
((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) {
((uint8_t)USBD_CONFIGURED == udev->dev.cur_status))
{
/* set device remote wakeup feature */
if((uint16_t)USB_FEATURE_REMOTE_WAKEUP == req->wValue) {
if((uint16_t)USB_FEATURE_REMOTE_WAKEUP == req->wValue)
{
udev->dev.pm.dev_remote_wakeup = 1U;
}
@ -479,9 +504,11 @@ static usb_reqsta _usb_std_setfeature(usb_core_driver *udev, usb_req *req)
/* get endpoint address */
ep = BYTE_LOW(req->wIndex);
if((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) {
if((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)
{
/* set endpoint halt feature */
if(((uint16_t)USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) {
if(((uint16_t)USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep)))
{
(void)usbd_ep_stall(udev, ep);
}
@ -505,13 +532,16 @@ static usb_reqsta _usb_std_setfeature(usb_core_driver *udev, usb_req *req)
*/
static usb_reqsta _usb_std_setaddress(usb_core_driver *udev, usb_req *req)
{
if((0U == req->wIndex) && (0U == req->wLength)) {
if((0U == req->wIndex) && (0U == req->wLength))
{
udev->dev.dev_addr = (uint8_t)(req->wValue) & 0x7FU;
if(udev->dev.cur_status != (uint8_t)USBD_CONFIGURED) {
if(udev->dev.cur_status != (uint8_t)USBD_CONFIGURED)
{
usbd_addr_set(udev, udev->dev.dev_addr);
if(udev->dev.dev_addr) {
if(udev->dev.dev_addr)
{
udev->dev.cur_status = (uint8_t)USBD_ADDRESSED;
} else {
udev->dev.cur_status = (uint8_t)USBD_DEFAULT;
@ -541,16 +571,19 @@ static usb_reqsta _usb_std_getdescriptor(usb_core_driver *udev, usb_req *req)
usb_transc *transc = &udev->dev.transc_in[0];
/* get device standard descriptor */
switch(req->bmRequestType & USB_RECPTYPE_MASK) {
switch(req->bmRequestType & USB_RECPTYPE_MASK)
{
case USB_RECPTYPE_DEV:
desc_type = BYTE_HIGH(req->wValue);
desc_index = BYTE_LOW(req->wValue);
switch(desc_type) {
switch(desc_type)
{
case USB_DESCTYPE_DEV:
transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *) & (transc->remain_len));
if(64U == req->wLength) {
if(64U == req->wLength)
{
transc->remain_len = 8U;
}
break;
@ -560,7 +593,8 @@ static usb_reqsta _usb_std_getdescriptor(usb_core_driver *udev, usb_req *req)
break;
case USB_DESCTYPE_STR:
if(desc_index < (uint8_t)STR_IDX_MAX) {
if(desc_index < (uint8_t)STR_IDX_MAX)
{
transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *) & (transc->remain_len));
}
break;
@ -604,9 +638,12 @@ static usb_reqsta _usb_std_getdescriptor(usb_core_driver *udev, usb_req *req)
break;
}
if((0U != transc->remain_len) && (0U != req->wLength)) {
if(transc->remain_len < req->wLength) {
if((transc->remain_len >= transc->max_len) && (0U == (transc->remain_len % transc->max_len))) {
if((0U != transc->remain_len) && (0U != req->wLength))
{
if(transc->remain_len < req->wLength)
{
if((transc->remain_len >= transc->max_len) && (0U == (transc->remain_len % transc->max_len)))
{
udev->dev.control.ctl_zlp = 1U;
}
} else {
@ -649,15 +686,18 @@ static usb_reqsta _usb_std_getconfiguration(usb_core_driver *udev, usb_req *req)
usb_reqsta req_status = REQ_NOTSUPP;
usb_transc *transc = &udev->dev.transc_in[0];
switch(udev->dev.cur_status) {
switch(udev->dev.cur_status)
{
case USBD_ADDRESSED:
if(USB_DEFAULT_CONFIG == udev->dev.config) {
if(USB_DEFAULT_CONFIG == udev->dev.config)
{
req_status = REQ_SUPP;
}
break;
case USBD_CONFIGURED:
if(udev->dev.config != USB_DEFAULT_CONFIG) {
if(udev->dev.config != USB_DEFAULT_CONFIG)
{
req_status = REQ_SUPP;
}
break;
@ -666,7 +706,8 @@ static usb_reqsta _usb_std_getconfiguration(usb_core_driver *udev, usb_req *req)
break;
}
if(REQ_SUPP == req_status) {
if(REQ_SUPP == req_status)
{
transc->xfer_buf = &(udev->dev.config);
transc->remain_len = 1U;
}
@ -688,10 +729,13 @@ static usb_reqsta _usb_std_setconfiguration(usb_core_driver *udev, usb_req *req)
config = (uint8_t)(req->wValue);
if(config <= USBD_CFG_MAX_NUM) {
switch(udev->dev.cur_status) {
if(config <= USBD_CFG_MAX_NUM)
{
switch(udev->dev.cur_status)
{
case USBD_ADDRESSED:
if(config) {
if(config)
{
(void)udev->dev.class_core->init(udev, config);
udev->dev.config = config;
@ -702,12 +746,14 @@ static usb_reqsta _usb_std_setconfiguration(usb_core_driver *udev, usb_req *req)
break;
case USBD_CONFIGURED:
if(USB_DEFAULT_CONFIG == config) {
if(USB_DEFAULT_CONFIG == config)
{
(void)udev->dev.class_core->deinit(udev, config);
udev->dev.config = config;
udev->dev.cur_status = (uint8_t)USBD_ADDRESSED;
} else if(config != udev->dev.config) {
} else if(config != udev->dev.config)
{
/* clear old configuration */
(void)udev->dev.class_core->deinit(udev, config);
@ -742,7 +788,8 @@ static usb_reqsta _usb_std_setconfiguration(usb_core_driver *udev, usb_req *req)
*/
static usb_reqsta _usb_std_getinterface(usb_core_driver *udev, usb_req *req)
{
switch(udev->dev.cur_status) {
switch(udev->dev.cur_status)
{
case USBD_DEFAULT:
break;
@ -750,7 +797,8 @@ static usb_reqsta _usb_std_getinterface(usb_core_driver *udev, usb_req *req)
break;
case USBD_CONFIGURED:
if(BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) {
if(BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM)
{
usb_transc *transc = &udev->dev.transc_in[0];
transc->xfer_buf = &(udev->dev.class_core->alter_set);
@ -776,7 +824,8 @@ static usb_reqsta _usb_std_getinterface(usb_core_driver *udev, usb_req *req)
*/
static usb_reqsta _usb_std_setinterface(usb_core_driver *udev, usb_req *req)
{
switch(udev->dev.cur_status) {
switch(udev->dev.cur_status)
{
case USBD_DEFAULT:
break;
@ -784,8 +833,10 @@ static usb_reqsta _usb_std_setinterface(usb_core_driver *udev, usb_req *req)
break;
case USBD_CONFIGURED:
if(BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) {
if(NULL != udev->dev.class_core->set_intf) {
if(BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM)
{
if(NULL != udev->dev.class_core->set_intf)
{
(void)udev->dev.class_core->set_intf(udev, req);
}

60
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/device/core/Source/usbd_transc.c
View File

@ -47,7 +47,8 @@ usbd_status usbd_ctl_send(usb_core_driver *udev)
(void)usbd_ep_send(udev, 0U, transc->xfer_buf, transc->remain_len);
if(transc->remain_len > transc->max_len) {
if(transc->remain_len > transc->max_len)
{
udev->dev.control.ctl_state = (uint8_t)USB_CTL_DATA_IN;
} else {
udev->dev.control.ctl_state = (uint8_t)USB_CTL_LAST_DATA_IN;
@ -68,7 +69,8 @@ usbd_status usbd_ctl_recev(usb_core_driver *udev)
(void)usbd_ep_recev(udev, 0U, transc->xfer_buf, transc->remain_len);
if(transc->remain_len > transc->max_len) {
if(transc->remain_len > transc->max_len)
{
udev->dev.control.ctl_state = (uint8_t)USB_CTL_DATA_OUT;
} else {
udev->dev.control.ctl_state = (uint8_t)USB_CTL_LAST_DATA_OUT;
@ -123,7 +125,8 @@ uint8_t usbd_setup_transc(usb_core_driver *udev)
usb_req req = udev->dev.control.req;
switch(req.bmRequestType & USB_REQTYPE_MASK) {
switch(req.bmRequestType & USB_REQTYPE_MASK)
{
/* standard device request */
case USB_REQTYPE_STRD:
reqstat = usbd_standard_request(udev, &req);
@ -143,18 +146,22 @@ uint8_t usbd_setup_transc(usb_core_driver *udev)
break;
}
if(REQ_SUPP == reqstat) {
if(0U == req.wLength) {
if(REQ_SUPP == reqstat)
{
if(0U == req.wLength)
{
(void)usbd_ctl_status_send(udev);
} else {
if(req.bmRequestType & 0x80U) {
if(req.bmRequestType & 0x80U)
{
(void)usbd_ctl_send(udev);
} else {
(void)usbd_ctl_recev(udev);
}
}
} else {
if(req.bmRequestType & 0x80U) {
if(req.bmRequestType & 0x80U)
{
usbd_ep_stall(udev, 0x80U);
usb_ctlep_startout(udev);
} else {
@ -175,15 +182,18 @@ uint8_t usbd_setup_transc(usb_core_driver *udev)
*/
uint8_t usbd_out_transc(usb_core_driver *udev, uint8_t ep_num)
{
if(0U == ep_num) {
if(0U == ep_num)
{
usb_transc *transc = &udev->dev.transc_out[0];
switch(udev->dev.control.ctl_state) {
switch(udev->dev.control.ctl_state)
{
case USB_CTL_DATA_OUT:
/* update transfer length */
transc->remain_len -= transc->max_len;
if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode)
{
transc->xfer_buf += transc->max_len;
}
@ -191,8 +201,10 @@ uint8_t usbd_out_transc(usb_core_driver *udev, uint8_t ep_num)
break;
case USB_CTL_LAST_DATA_OUT:
if(udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) {
if(udev->dev.class_core->ctlx_out != NULL) {
if(udev->dev.cur_status == (uint8_t)USBD_CONFIGURED)
{
if(udev->dev.class_core->ctlx_out != NULL)
{
(void)udev->dev.class_core->ctlx_out(udev);
}
}
@ -205,7 +217,8 @@ uint8_t usbd_out_transc(usb_core_driver *udev, uint8_t ep_num)
default:
break;
}
} else if((udev->dev.class_core->data_out != NULL) && (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED)) {
} else if((udev->dev.class_core->data_out != NULL) && (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED))
{
(void)udev->dev.class_core->data_out(udev, ep_num);
} else {
/* no operation */
@ -223,15 +236,18 @@ uint8_t usbd_out_transc(usb_core_driver *udev, uint8_t ep_num)
*/
uint8_t usbd_in_transc(usb_core_driver *udev, uint8_t ep_num)
{
if(0U == ep_num) {
if(0U == ep_num)
{
usb_transc *transc = &udev->dev.transc_in[0];
switch(udev->dev.control.ctl_state) {
switch(udev->dev.control.ctl_state)
{
case USB_CTL_DATA_IN:
/* update transfer length */
transc->remain_len -= transc->max_len;
if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode)
{
transc->xfer_buf += transc->max_len;
}
@ -240,13 +256,16 @@ uint8_t usbd_in_transc(usb_core_driver *udev, uint8_t ep_num)
case USB_CTL_LAST_DATA_IN:
/* last packet is MPS multiple, so send ZLP packet */
if(udev->dev.control.ctl_zlp) {
if(udev->dev.control.ctl_zlp)
{
(void)usbd_ep_send(udev, 0U, NULL, 0U);
udev->dev.control.ctl_zlp = 0U;
} else {
if(udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) {
if(udev->dev.class_core->ctlx_in != NULL) {
if(udev->dev.cur_status == (uint8_t)USBD_CONFIGURED)
{
if(udev->dev.class_core->ctlx_in != NULL)
{
(void)udev->dev.class_core->ctlx_in(udev);
}
}
@ -261,7 +280,8 @@ uint8_t usbd_in_transc(usb_core_driver *udev, uint8_t ep_num)
break;
}
} else {
if(((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) && (NULL != udev->dev.class_core->data_in)) {
if(((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) && (NULL != udev->dev.class_core->data_in))
{
(void)udev->dev.class_core->data_in(udev, ep_num);
}
}

6
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/driver/Include/drv_usb_dev.h
View File

@ -132,7 +132,8 @@ __STATIC_INLINE uint32_t usb_iepintnum_read (usb_core_driver *udev)
*/
__STATIC_INLINE void usb_rwkup_set (usb_core_driver *udev)
{
if (udev->dev.pm.dev_remote_wakeup) {
if (udev->dev.pm.dev_remote_wakeup)
{
/* enable remote wakeup signaling */
udev->regs.dr->DCTL |= DCTL_RWKUP;
}
@ -146,7 +147,8 @@ __STATIC_INLINE void usb_rwkup_set (usb_core_driver *udev)
*/
__STATIC_INLINE void usb_rwkup_reset (usb_core_driver *udev)
{
if (udev->dev.pm.dev_remote_wakeup) {
if (udev->dev.pm.dev_remote_wakeup)
{
/* disable remote wakeup signaling */
udev->regs.dr->DCTL &= ~DCTL_RWKUP;
}

4
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/driver/Include/drv_usb_host.h
View File

@ -59,8 +59,8 @@ __STATIC_INLINE uint8_t usb_frame_even (usb_core_driver *udev)
*/
__STATIC_INLINE void usb_phyclock_config (usb_core_driver *udev, uint8_t clock)
{
// udev->regs.hr->HCTL &= ~HCTL_CLKSEL;
// udev->regs.hr->HCTL |= clock;
/* udev->regs.hr->HCTL &= ~HCTL_CLKSEL;*/
/* udev->regs.hr->HCTL |= clock;*/
}
/*!

60
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/driver/Source/drv_usb_core.c
View File

@ -57,7 +57,8 @@ void usb_para_init(usb_core_driver *udev, uint32_t usb_periph, uint32_t usb_spee
usb_basic->core_speed = (uint8_t)USB_SPEED_FULL;
/* USB basic register address setting */
switch(usb_periph){
switch(usb_periph)
{
case USBHS0:
usb_basic->base_reg = (uint32_t)USBHS0_REG_BASE;
break;
@ -74,7 +75,8 @@ void usb_para_init(usb_core_driver *udev, uint32_t usb_periph, uint32_t usb_spee
/* set the device endpoint numbers */
usb_basic->num_ep = USBHS_MAX_EP_COUNT;
if (USB_SPEED_HIGH == usb_speed) {
if (USB_SPEED_HIGH == usb_speed)
{
#ifdef USB_EXTERNAL_ULPI_PHY_ENABLED
usb_basic->phy_itf = USB_ULPI_PHY_EXTERNAL;
#endif /* USB_EXTERNAL_ULPI_PHY_ENABLED */
@ -82,7 +84,8 @@ void usb_para_init(usb_core_driver *udev, uint32_t usb_periph, uint32_t usb_spee
#ifdef USB_EMBEDDED_HS_PHY_ENABLED
usb_basic->phy_itf = USB_EMBEDDED_PHY_HS;
#endif /* USB_EMBEDDED_HS_PHY_ENABLED */
} else if (USB_SPEED_FULL == usb_speed) {
} else if (USB_SPEED_FULL == usb_speed)
{
#ifdef USB_EMBEDDED_FS_PHY_ENABLED
usb_basic->phy_itf = USB_EMBEDDED_PHY_FS;
#endif /* USB_EMBEDDED_FS_PHY_ENABLED */
@ -111,7 +114,8 @@ void usb_para_init(usb_core_driver *udev, uint32_t usb_periph, uint32_t usb_spee
usb_status usb_basic_init (usb_core_basic *usb_basic, usb_core_regs *usb_regs)
{
/* assign main registers address */
*usb_regs = (usb_core_regs) {
*usb_regs = (usb_core_regs)
{
.gr = (usb_gr*) (usb_basic->base_reg + (uint32_t)USB_REG_OFFSET_CORE),
.hr = (usb_hr*) (usb_basic->base_reg + (uint32_t)USB_REG_OFFSET_HOST),
.dr = (usb_dr*) (usb_basic->base_reg + (uint32_t)USB_REG_OFFSET_DEV),
@ -121,7 +125,8 @@ usb_status usb_basic_init (usb_core_basic *usb_basic, usb_core_regs *usb_regs)
};
/* assign device endpoint registers address */
for (uint8_t i = 0U; i < usb_basic->num_ep; i++) {
for (uint8_t i = 0U; i < usb_basic->num_ep; i++)
{
usb_regs->er_in[i] = (usb_erin *) \
(usb_basic->base_reg + (uint32_t)USB_REG_OFFSET_EP_IN + (i * (uint32_t)USB_REG_OFFSET_EP));
@ -130,7 +135,8 @@ usb_status usb_basic_init (usb_core_basic *usb_basic, usb_core_regs *usb_regs)
}
/* assign host pipe registers address */
for (uint8_t i = 0U; i < usb_basic->num_pipe; i++) {
for (uint8_t i = 0U; i < usb_basic->num_pipe; i++)
{
usb_regs->pr[i] = (usb_pr *) \
(usb_basic->base_reg + (uint32_t)USB_REG_OFFSET_CH_INOUT + (i * (uint32_t)USB_REG_OFFSET_CH));
@ -154,12 +160,14 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs)
/* disable USB global interrupt */
usb_regs->gr->GAHBCS &= ~GAHBCS_GINTEN;
if (USB_ULPI_PHY_EXTERNAL == usb_basic.phy_itf) {
if (USB_ULPI_PHY_EXTERNAL == usb_basic.phy_itf)
{
usb_regs->gr->GCCFG &= ~GCCFG_PWRON;
usb_regs->gr->GUSBCS &= ~(GUSBCS_EMBPHY_HS | GUSBCS_EMBPHY_FS);
if (usb_basic.sof_enable) {
if (usb_basic.sof_enable)
{
usb_regs->gr->GCCFG |= GCCFG_SOFOEN;
}
@ -176,7 +184,8 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs)
/* soft reset the core */
usb_core_reset (usb_regs);
} else if (USB_EMBEDDED_PHY_HS == usb_basic.phy_itf) {
} else if (USB_EMBEDDED_PHY_HS == usb_basic.phy_itf)
{
usb_regs->gr->GUSBCS |= GUSBCS_EMBPHY_HS;
/* soft reset the core */
@ -200,12 +209,14 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs)
usb_regs->gr->GCCFG |= GCCFG_PWRON;
#endif /* VBUS_SENSING_ENABLED */
if (usb_basic.sof_enable) {
if (usb_basic.sof_enable)
{
usb_regs->gr->GCCFG |= GCCFG_SOFOEN;
}
usb_mdelay(20U);
} else if (USB_EMBEDDED_PHY_FS == usb_basic.phy_itf) {
} else if (USB_EMBEDDED_PHY_FS == usb_basic.phy_itf)
{
usb_regs->gr->GUSBCS |= GUSBCS_EMBPHY_FS;
/* soft reset the core */
@ -228,7 +239,8 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs)
#endif /* VBUS_SENSING_ENABLED */
/* enable SOF output */
if (usb_basic.sof_enable) {
if (usb_basic.sof_enable)
{
usb_regs->gr->GCCFG |= GCCFG_SOFOEN;
}
@ -237,7 +249,8 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs)
/* no operation */
}
if ((uint8_t)USB_USE_DMA == usb_basic.transfer_mode) {
if ((uint8_t)USB_USE_DMA == usb_basic.transfer_mode)
{
usb_regs->gr->GAHBCS &= ~GAHBCS_BURST;
usb_regs->gr->GAHBCS |= DMA_INCR8 | GAHBCS_DMAEN;
}
@ -275,7 +288,8 @@ usb_status usb_txfifo_write (usb_core_regs *usb_regs,
uint32_t word_count = (byte_count + 3U) / 4U;
__IO uint32_t *fifo = usb_regs->DFIFO[fifo_num];
while (word_count-- > 0U) {
while (word_count-- > 0U)
{
*fifo = *((__IO uint32_t *)src_buf);
src_buf += 4U;
@ -297,7 +311,8 @@ void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte
__IO uint32_t word_count = (byte_count + 3U) / 4U;
__IO uint32_t *fifo = usb_regs->DFIFO[0];
while (word_count-- > 0U) {
while (word_count-- > 0U)
{
*(__IO uint32_t *)dest_buf = *fifo;
dest_buf += 4U;
@ -318,7 +333,8 @@ usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num)
usb_regs->gr->GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF;
/* wait for Tx FIFO flush bit is set */
while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF) {
while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF)
{
/* no operation */
}
@ -339,7 +355,8 @@ usb_status usb_rxfifo_flush (usb_core_regs *usb_regs)
usb_regs->gr->GRSTCTL = GRSTCTL_RXFF;
/* wait for RX FIFO flush bit is set */
while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF) {
while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF)
{
/* no operation */
}
@ -361,12 +378,14 @@ void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size)
{
uint32_t tx_offset = usb_regs->gr->GRFLEN;
if (0U == fifo) {
if (0U == fifo)
{
usb_regs->gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)size << 16U) | tx_offset;
} else {
tx_offset += (usb_regs->gr->DIEP0TFLEN_HNPTFLEN) >> 16U;
for (uint8_t i = 0U; i < (fifo - 1U); i++) {
for (uint8_t i = 0U; i < (fifo - 1U); i++)
{
tx_offset += (usb_regs->gr->DIEPTFLEN[i] >> 16U);
}
@ -386,7 +405,8 @@ static void usb_core_reset (usb_core_regs *usb_regs)
usb_regs->gr->GRSTCTL |= GRSTCTL_CSRST;
/* wait for the core to be soft reset */
while (usb_regs->gr->GRSTCTL & GRSTCTL_CSRST) {
while (usb_regs->gr->GRSTCTL & GRSTCTL_CSRST)
{
/* no operation */
}

138
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/driver/Source/drv_usb_dev.c
View File

@ -80,9 +80,11 @@ usb_status usb_devcore_init (usb_core_driver *udev)
udev->regs.dr->DCFG &= ~DCFG_DS;
if (USB_EMBEDDED_PHY_HS == udev->bp.phy_itf) {
if (USB_EMBEDDED_PHY_HS == udev->bp.phy_itf)
{
udev->regs.dr->DCFG |= USB_SPEED_INP_HIGH;
} else if (USB_EMBEDDED_PHY_FS == udev->bp.phy_itf) {
} else if (USB_EMBEDDED_PHY_FS == udev->bp.phy_itf)
{
udev->regs.dr->DCFG |= USB_SPEED_INP_FULL;
} else {
/* no operation */
@ -92,7 +94,8 @@ usb_status usb_devcore_init (usb_core_driver *udev)
usb_set_rxfifo(&udev->regs, (uint16_t)RX_FIFO_SIZE);
/* set endpoint 0 to 3's TX FIFO length and RAM address */
for (i = 0U; i < USBHS_MAX_EP_COUNT; i++) {
for (i = 0U; i < USBHS_MAX_EP_COUNT; i++)
{
usb_set_txfifo(&udev->regs, i, USBHS_TX_FIFO_SIZE[i]);
}
@ -111,8 +114,10 @@ usb_status usb_devcore_init (usb_core_driver *udev)
udev->regs.dr->DAEPINTEN = 0U;
/* configure all IN/OUT endpoints */
for (i = 0U; i < udev->bp.num_ep; i++) {
if (udev->regs.er_in[i]->DIEPCTL & DEPCTL_EPEN) {
for (i = 0U; i < udev->bp.num_ep; i++)
{
if (udev->regs.er_in[i]->DIEPCTL & DEPCTL_EPEN)
{
udev->regs.er_in[i]->DIEPCTL |= DEPCTL_EPD | DEPCTL_SNAK;
} else {
udev->regs.er_in[i]->DIEPCTL = 0U;
@ -124,7 +129,8 @@ usb_status usb_devcore_init (usb_core_driver *udev)
/* clear all pending IN endpoint interrupts */
udev->regs.er_in[i]->DIEPINTF = 0xFFU;
if (udev->regs.er_out[i]->DOEPCTL & DEPCTL_EPEN) {
if (udev->regs.er_out[i]->DOEPCTL & DEPCTL_EPEN)
{
udev->regs.er_out[i]->DOEPCTL |= DEPCTL_EPD | DEPCTL_SNAK;
} else {
udev->regs.er_out[i]->DOEPCTL = 0U;
@ -142,7 +148,8 @@ usb_status usb_devcore_init (usb_core_driver *udev)
(void)usb_devint_enable (udev);
/* configure LPM function */
if(1U == udev->bp.lpm_enable){
if(1U == udev->bp.lpm_enable)
{
udev->dev.pm.lpm_state = LPM_L0;
udev->regs.gr->GLPMCFG = GLPMCFG_LPMEN | GLPMCFG_ACKLPM | GLPMCFG_BESLEN;
}
@ -168,7 +175,8 @@ usb_status usb_devint_enable (usb_core_driver *udev)
udev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE;
/* enable device_mode-related interrupts */
if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) {
if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode)
{
udev->regs.gr->GINTEN |= GINTEN_RXFNEIE;
}
@ -179,7 +187,8 @@ usb_status usb_devint_enable (usb_core_driver *udev)
udev->regs.gr->GINTEN |= GINTEN_SESIE | GINTEN_OTGIE;
#endif /* VBUS_SENSING_ENABLED */
if(1U == udev->bp.lpm_enable){
if(1U == udev->bp.lpm_enable)
{
udev->regs.gr->GINTEN |= GINTEN_LPMIE;
}
@ -204,12 +213,14 @@ usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc)
/* get the endpoint number */
uint8_t ep_num = transc->ep_addr.num;
if (ep_num) {
if (ep_num)
{
/* not endpoint 0 */
return USB_FAIL;
}
if (transc->ep_addr.dir) {
if (transc->ep_addr.dir)
{
reg_addr = &udev->regs.er_in[0]->DIEPCTL;
} else {
reg_addr = &udev->regs.er_out[0]->DOEPCTL;
@ -245,7 +256,8 @@ usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc)
uint8_t ep_num = transc->ep_addr.num;
/* enable endpoint interrupt number */
if (transc->ep_addr.dir) {
if (transc->ep_addr.dir)
{
reg_addr = &udev->regs.er_in[ep_num]->DIEPCTL;
epinten = 1U << ep_num;
@ -256,11 +268,13 @@ usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc)
}
/* if the endpoint is not active, need change the endpoint control register */
if (!(*reg_addr & DEPCTL_EPACT)) {
if (!(*reg_addr & DEPCTL_EPACT))
{
*reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM);
/* set endpoint maximum packet length */
if (0U == ep_num) {
if (0U == ep_num)
{
*reg_addr |= EP0_MAXLEN[enum_speed];
} else {
*reg_addr |= transc->max_len;
@ -271,7 +285,8 @@ usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc)
}
#ifdef USB_DEDICATED_EP1_ENABLED
if (1U == ep_num) {
if (1U == ep_num)
{
udev->regs.dr->DEP1INTEN |= epinten;
}
else
@ -298,7 +313,8 @@ usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc)
uint8_t ep_num = transc->ep_addr.num;
/* disable endpoint interrupt number */
if (transc->ep_addr.dir) {
if (transc->ep_addr.dir)
{
epinten = 1U << ep_num;
udev->regs.er_in[ep_num]->DIEPCTL &= ~DEPCTL_EPACT;
@ -309,7 +325,8 @@ usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc)
}
#ifdef USB_DEDICATED_EP1_ENABLED
if (1U == ep_num) {
if (1U == ep_num)
{
udev->regs.dr->DEP1INTEN &= ~epinten;
}
else
@ -340,12 +357,14 @@ usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc)
eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT);
/* zero length packet or endpoint 0 */
if (0U == transc->xfer_len) {
if (0U == transc->xfer_len)
{
/* set transfer packet count to 1 */
eplen |= 1U << 19U;
} else {
/* set transfer packet count */
if (0U == ep_num) {
if (0U == ep_num)
{
transc->xfer_len = USB_MIN(transc->xfer_len, transc->max_len);
eplen |= 1U << 19U;
@ -356,22 +375,26 @@ usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc)
/* set endpoint transfer length */
eplen |= transc->xfer_len;
if ((uint8_t)USB_EPTYPE_ISOC == transc->ep_type) {
if ((uint8_t)USB_EPTYPE_ISOC == transc->ep_type)
{
eplen |= DIEPLEN_MCNT & (1U << 29U);
}
}
udev->regs.er_in[ep_num]->DIEPLEN = eplen;
if ((uint8_t)USB_EPTYPE_ISOC == transc->ep_type) {
if (((udev->regs.dr->DSTAT & DSTAT_FNRSOF) >> 8U) & 0x01U) {
if ((uint8_t)USB_EPTYPE_ISOC == transc->ep_type)
{
if (((udev->regs.dr->DSTAT & DSTAT_FNRSOF) >> 8U) & 0x01U)
{
epctl |= DEPCTL_SEVNFRM;
} else {
epctl |= DEPCTL_SODDFRM;
}
}
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode)
{
udev->regs.er_in[ep_num]->DIEPDMAADDR = transc->dma_addr;
}
@ -380,10 +403,13 @@ usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc)
udev->regs.er_in[ep_num]->DIEPCTL = epctl;
if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) {
if (transc->ep_type != (uint8_t)USB_EPTYPE_ISOC) {
if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode)
{
if (transc->ep_type != (uint8_t)USB_EPTYPE_ISOC)
{
/* enable the TX FIFO empty interrupt for this endpoint */
if (transc->xfer_len > 0U) {
if (transc->xfer_len > 0U)
{
udev->regs.dr->DIEPFEINTEN |= 1U << ep_num;
}
} else {
@ -413,7 +439,8 @@ usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc)
eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT);
/* zero length packet or endpoint 0 */
if ((0U == transc->xfer_len) || (0U == ep_num)) {
if ((0U == transc->xfer_len) || (0U == ep_num))
{
/* set the transfer length to max packet size */
eplen |= transc->max_len;
@ -432,12 +459,15 @@ usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc)
udev->regs.er_out[ep_num]->DOEPLEN = eplen;
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode)
{
udev->regs.er_out[ep_num]->DOEPDMAADDR = transc->dma_addr;
}
if ((uint8_t)USB_EPTYPE_ISOC == transc->ep_type) {
if (transc->frame_num) {
if ((uint8_t)USB_EPTYPE_ISOC == transc->ep_type)
{
if (transc->frame_num)
{
epctl |= DEPCTL_SD1PID;
} else {
epctl |= DEPCTL_SD0PID;
@ -465,11 +495,13 @@ usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc)
uint8_t ep_num = transc->ep_addr.num;
if (transc->ep_addr.dir) {
if (transc->ep_addr.dir)
{
reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL);
/* set the endpoint disable bit */
if (*reg_addr & DEPCTL_EPEN) {
if (*reg_addr & DEPCTL_EPEN)
{
*reg_addr |= DEPCTL_EPD;
}
} else {
@ -496,7 +528,8 @@ usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc)
uint8_t ep_num = transc->ep_addr.num;
if (transc->ep_addr.dir) {
if (transc->ep_addr.dir)
{
reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL);
} else {
reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL);
@ -506,7 +539,8 @@ usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc)
*reg_addr &= ~DEPCTL_STALL;
/* reset data PID of the periodic endpoints */
if (((uint8_t)USB_EPTYPE_INTR == transc->ep_type) || ((uint8_t)USB_EPTYPE_BULK == transc->ep_type)) {
if (((uint8_t)USB_EPTYPE_INTR == transc->ep_type) || ((uint8_t)USB_EPTYPE_BULK == transc->ep_type))
{
*reg_addr |= DEPCTL_SD0PID;
}
@ -547,7 +581,8 @@ void usb_ctlep_startout (usb_core_driver *udev)
/* set OUT endpoint 0 receive length to 24 bytes, 1 packet and 3 setup packets */
udev->regs.er_out[0]->DOEPLEN = DOEP0_TLEN(8U * 3U) | DOEP0_PCNT(1U) | DOEP0_STPCNT(3U);
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode)
{
udev->regs.er_out[0]->DOEPDMAADDR = (uint32_t)&udev->dev.control.req;
/* endpoint enable */
@ -563,9 +598,12 @@ void usb_ctlep_startout (usb_core_driver *udev)
*/
void usb_rwkup_active (usb_core_driver *udev)
{
if (udev->dev.pm.dev_remote_wakeup) {
if (udev->regs.dr->DSTAT & DSTAT_SPST) {
if (udev->bp.low_power) {
if (udev->dev.pm.dev_remote_wakeup)
{
if (udev->regs.dr->DSTAT & DSTAT_SPST)
{
if (udev->bp.low_power)
{
/* ungate USB core clock */
*udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK);
}
@ -588,8 +626,10 @@ void usb_rwkup_active (usb_core_driver *udev)
*/
void usb_clock_active (usb_core_driver *udev)
{
if (udev->bp.low_power) {
if (udev->regs.dr->DSTAT & DSTAT_SPST) {
if (udev->bp.low_power)
{
if (udev->regs.dr->DSTAT & DSTAT_SPST)
{
/* un-gate USB Core clock */
*udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK);
}
@ -606,7 +646,8 @@ void usb_dev_suspend (usb_core_driver *udev)
{
__IO uint32_t devstat = udev->regs.dr->DSTAT;
if ((devstat & DSTAT_SPST) && (udev->bp.low_power)) {
if ((devstat & DSTAT_SPST) && (udev->bp.low_power))
{
/* switch-off the USB clocks */
*udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK;
@ -628,7 +669,8 @@ void usb_dev_stop (usb_core_driver *udev)
udev->dev.cur_status = 1U;
/* clear all interrupt flag and enable bits */
for (i = 0U; i < udev->bp.num_ep; i++) {
for (i = 0U; i < udev->bp.num_ep; i++)
{
udev->regs.er_in[i]->DIEPINTF = 0xFFU;
udev->regs.er_out[i]->DOEPINTF = 0xFFU;
}
@ -655,7 +697,8 @@ bcd_type usbd_bcd_detect (usb_core_driver *udev)
usb_mdelay(1000);
if (0U == (udev->regs.gr->GCCFG & GCCFG_DCDF)) {
if (0U == (udev->regs.gr->GCCFG & GCCFG_DCDF))
{
udev->regs.gr->GCCFG &= ~GCCFG_DCDEN;
return BCD_ERROR;
@ -666,13 +709,15 @@ bcd_type usbd_bcd_detect (usb_core_driver *udev)
udev->regs.gr->GCCFG |= GCCFG_PEMEN;
usb_mdelay(50);
if (udev->regs.gr->GCCFG & GCCFG_PDF) {
if (udev->regs.gr->GCCFG & GCCFG_PDF)
{
udev->regs.gr->GCCFG &= ~GCCFG_PEMEN;
usb_mdelay(20);
udev->regs.gr->GCCFG |= GCCFG_SDMEN;
usb_mdelay(50);
if (udev->regs.gr->GCCFG & GCCFG_SDF) {
if (udev->regs.gr->GCCFG & GCCFG_SDF)
{
udev->regs.gr->GCCFG &= ~GCCFG_SDMEN;
usb_mdelay(20);
@ -683,7 +728,8 @@ bcd_type usbd_bcd_detect (usb_core_driver *udev)
return BCD_CDP;
}
} else if (udev->regs.gr->GCCFG & GCCFG_PS2F) {
} else if (udev->regs.gr->GCCFG & GCCFG_PS2F)
{
udev->regs.gr->GCCFG &= ~GCCFG_PEMEN;
usb_mdelay(20);

74
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/driver/Source/drv_usb_host.c
View File

@ -60,7 +60,7 @@ usb_status usb_host_init (usb_core_driver *udev)
/* restart the PHY Clock */
*udev->regs.PWRCLKCTL = 0U;
// usb_port_reset (udev);
/* usb_port_reset (udev);*/
/* support HS, FS and LS */
udev->regs.hr->HCTL &= ~HCTL_SPDFSLS;
@ -102,7 +102,8 @@ usb_status usb_host_init (usb_core_driver *udev)
udev->regs.gr->GINTF = 0xBFFFFFFFU;
/* clear all pending host channel interrupts */
for (i = 0U; i < udev->bp.num_pipe; i++) {
for (i = 0U; i < udev->bp.num_pipe; i++)
{
udev->regs.pr[i]->HCHINTF = 0xFFFFFFFFU;
udev->regs.pr[i]->HCHINTEN = 0U;
}
@ -114,7 +115,8 @@ usb_status usb_host_init (usb_core_driver *udev)
udev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE;
/* enable host_mode-related interrupts */
if (USB_USE_FIFO == udev->bp.transfer_mode) {
if (USB_USE_FIFO == udev->bp.transfer_mode)
{
inten = GINTEN_RXFNEIE;
}
@ -147,11 +149,13 @@ void usb_portvbus_switch (usb_core_driver *udev, uint8_t state)
/* turn on the host port power. */
port = usb_port_read (udev);
if ((!(port & HPCS_PP)) && (1U == state)) {
if ((!(port & HPCS_PP)) && (1U == state))
{
port |= HPCS_PP;
}
if ((port & HPCS_PP) && (0U == state)) {
if ((port & HPCS_PP) && (0U == state))
{
port &= ~HPCS_PP;
}
@ -200,23 +204,28 @@ usb_status usb_pipe_init (usb_core_driver *udev, uint8_t pipe_num)
/* clear old interrupt conditions for this host channel */
udev->regs.pr[pipe_num]->HCHINTF = 0xFFFFFFFFU;
if (USB_USE_DMA == udev->bp.transfer_mode) {
if (USB_USE_DMA == udev->bp.transfer_mode)
{
pp_inten |= HCHINTEN_DMAERIE;
}
if (pp->ep.dir) {
if (pp->ep.dir)
{
pp_inten |= HCHINTEN_BBERIE;
}
/* enable channel interrupts required for this transfer */
switch (pp->ep.type) {
switch (pp->ep.type)
{
case USB_EPTYPE_CTRL:
case USB_EPTYPE_BULK:
pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE \
| HCHINTEN_DTERIE | HCHINTEN_NAKIE;
if (!pp->ep.dir) {
if (PORT_SPEED_HIGH == pp->dev_speed) {
if (!pp->ep.dir)
{
if (PORT_SPEED_HIGH == pp->dev_speed)
{
pp_inten |= HCHINTEN_NYETIE;
pp_inten |= HCHINTEN_ACKIE;
}
@ -231,7 +240,8 @@ usb_status usb_pipe_init (usb_core_driver *udev, uint8_t pipe_num)
case USB_EPTYPE_ISOC:
pp_inten |= HCHINTEN_REQOVRIE | HCHINTEN_ACKIE;
if (pp->ep.dir) {
if (pp->ep.dir)
{
pp_inten |= HCHINTEN_USBERIE;
}
break;
@ -284,10 +294,12 @@ usb_status usb_pipe_xfer (usb_core_driver *udev, uint8_t pipe_num)
uint16_t max_packet_len = pp->ep.mps;
/* compute the expected number of packets associated to the transfer */
if (pp->xfer_len > 0U) {
if (pp->xfer_len > 0U)
{
packet_count = (uint16_t)((pp->xfer_len + max_packet_len - 1U) / max_packet_len);
if (packet_count > HC_MAX_PACKET_COUNT) {
if (packet_count > HC_MAX_PACKET_COUNT)
{
packet_count = HC_MAX_PACKET_COUNT;
pp->xfer_len = (uint16_t)(packet_count * max_packet_len);
}
@ -295,20 +307,23 @@ usb_status usb_pipe_xfer (usb_core_driver *udev, uint8_t pipe_num)
packet_count = 1U;
}
if (pp->ep.dir) {
if (pp->ep.dir)
{
pp->xfer_len = (uint16_t)(packet_count * max_packet_len);
}
/* initialize the host channel transfer information */
udev->regs.pr[pipe_num]->HCHLEN = pp->xfer_len | pp->DPID | PIPE_XFER_PCNT(packet_count);
if (USB_USE_DMA == udev->bp.transfer_mode) {
if (USB_USE_DMA == udev->bp.transfer_mode)
{
udev->regs.pr[pipe_num]->HCHDMAADDR = (unsigned int)pp->xfer_buf;
}
pp_ctl = udev->regs.pr[pipe_num]->HCHCTL;
if (usb_frame_even(udev)) {
if (usb_frame_even(udev))
{
pp_ctl |= HCHCTL_ODDFRM;
} else {
pp_ctl &= ~HCHCTL_ODDFRM;
@ -320,16 +335,20 @@ usb_status usb_pipe_xfer (usb_core_driver *udev, uint8_t pipe_num)
udev->regs.pr[pipe_num]->HCHCTL = pp_ctl;
if (USB_USE_FIFO == udev->bp.transfer_mode) {
if ((0U == pp->ep.dir) && (pp->xfer_len > 0U)) {
switch (pp->ep.type) {
if (USB_USE_FIFO == udev->bp.transfer_mode)
{
if ((0U == pp->ep.dir) && (pp->xfer_len > 0U))
{
switch (pp->ep.type)
{
/* non-periodic transfer */
case USB_EPTYPE_CTRL:
case USB_EPTYPE_BULK:
dword_len = (uint16_t)((pp->xfer_len + 3U) / 4U);
/* check if there is enough space in FIFO space */
if (dword_len > (udev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) {
if (dword_len > (udev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS))
{
/* need to process data in nptxfempty interrupt */
udev->regs.gr->GINTEN |= GINTEN_NPTXFEIE;
}
@ -341,7 +360,8 @@ usb_status usb_pipe_xfer (usb_core_driver *udev, uint8_t pipe_num)
dword_len = (uint16_t)((pp->xfer_len + 3U) / 4U);
/* check if there is enough space in FIFO space */
if (dword_len > (udev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS)) {
if (dword_len > (udev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS))
{
/* need to process data in ptxfempty interrupt */
udev->regs.gr->GINTEN |= GINTEN_PTXFEIE;
}
@ -374,17 +394,20 @@ usb_status usb_pipe_halt (usb_core_driver *udev, uint8_t pipe_num)
pp_ctl |= HCHCTL_CEN | HCHCTL_CDIS;
switch (ep_type) {
switch (ep_type)
{
case USB_EPTYPE_CTRL:
case USB_EPTYPE_BULK:
if (0U == (udev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) {
if (0U == (udev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS))
{
pp_ctl &= ~HCHCTL_CEN;
}
break;
case USB_EPTYPE_INTR:
case USB_EPTYPE_ISOC:
if (0U == (udev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS)) {
if (0U == (udev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS))
{
pp_ctl &= ~HCHCTL_CEN;
}
break;
@ -436,7 +459,8 @@ void usb_host_stop (usb_core_driver *udev)
udev->regs.hr->HACHINT = 0xFFFFFFFFU;
/* flush out any leftover queued requests. */
for (i = 0U; i < udev->bp.num_pipe; i++) {
for (i = 0U; i < udev->bp.num_pipe; i++)
{
pp_ctl = udev->regs.pr[i]->HCHCTL;
pp_ctl &= ~(HCHCTL_CEN | HCHCTL_EPDIR);

165
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/driver/Source/drv_usbd_int.c
View File

@ -74,11 +74,13 @@ uint32_t usbd_int_dedicated_ep1out (usb_core_driver *udev)
oepintr &= udev->regs.dr->DOEP1INTEN;
/* transfer complete */
if (oepintr & DOEPINTF_TF) {
if (oepintr & DOEPINTF_TF)
{
/* clear the bit in DOEPINTn for this interrupt */
udev->regs.er_out[1]->DOEPINTF = DOEPINTF_TF;
if (USB_USE_DMA == udev->bp.transfer_mode) {
if (USB_USE_DMA == udev->bp.transfer_mode)
{
oeplen = udev->regs.er_out[1]->DOEPLEN;
/* ToDo : handle more than one single MPS size packet */
@ -110,7 +112,8 @@ uint32_t usbd_int_dedicated_ep1in (usb_core_driver *udev)
intr = udev->regs.er_in[1]->DIEPINTF & inten;
if (intr & DIEPINTF_TF) {
if (intr & DIEPINTF_TF)
{
udev->regs.dr->DIEPFEINTEN &= ~(0x1U << 1U);
udev->regs.er_in[1]->DIEPINTF = DIEPINTF_TF;
@ -119,7 +122,8 @@ uint32_t usbd_int_dedicated_ep1in (usb_core_driver *udev)
usbd_in_transc (udev, 1U);
}
if (intr & DIEPINTF_TXFE) {
if (intr & DIEPINTF_TXFE)
{
usbd_emptytxfifo_write(udev, 1U);
udev->regs.er_in[1]->DIEPINTF = DIEPINTF_TXFE;
@ -138,38 +142,46 @@ uint32_t usbd_int_dedicated_ep1in (usb_core_driver *udev)
*/
void usbd_isr (usb_core_driver *udev)
{
if (HOST_MODE != (udev->regs.gr->GINTF & GINTF_COPM)) {
if (HOST_MODE != (udev->regs.gr->GINTF & GINTF_COPM))
{
uint32_t intr = udev->regs.gr->GINTF;
intr &= udev->regs.gr->GINTEN;
/* there are no interrupts, avoid spurious interrupt */
if (!intr) {
if (!intr)
{
return;
}
/* OUT endpoints interrupts */
if (intr & GINTF_OEPIF) {
if (intr & GINTF_OEPIF)
{
(void)usbd_int_epout (udev);
}
/* IN endpoints interrupts */
if (intr & GINTF_IEPIF) {
if (intr & GINTF_IEPIF)
{
(void)usbd_int_epin (udev);
}
/* suspend interrupt */
if (intr & GINTF_SP) {
if (intr & GINTF_SP)
{
(void)usbd_int_suspend (udev);
}
/* wakeup interrupt */
if (intr & GINTF_WKUPIF) {
if (intr & GINTF_WKUPIF)
{
(void)usbd_int_wakeup (udev);
}
/* start of frame interrupt */
if (intr & GINTF_SOF) {
if (udev->dev.class_core->SOF) {
if (intr & GINTF_SOF)
{
if (udev->dev.class_core->SOF)
{
(void)udev->dev.class_core->SOF(udev);
}
@ -178,23 +190,28 @@ void usbd_isr (usb_core_driver *udev)
}
/* receive FIFO not empty interrupt */
if (intr & GINTF_RXFNEIF) {
if (intr & GINTF_RXFNEIF)
{
(void)usbd_int_rxfifo (udev);
}
/* USB reset interrupt */
if (intr & GINTF_RST) {
if (intr & GINTF_RST)
{
(void)usbd_int_reset (udev);
}
/* enumeration has been done interrupt */
if (intr & GINTF_ENUMFIF) {
if (intr & GINTF_ENUMFIF)
{
(void)usbd_int_enumfinish (udev);
}
/* incomplete synchronization IN transfer interrupt*/
if (intr & GINTF_ISOINCIF) {
if (NULL != udev->dev.class_core->incomplete_isoc_in) {
if (intr & GINTF_ISOINCIF)
{
if (NULL != udev->dev.class_core->incomplete_isoc_in)
{
(void)udev->dev.class_core->incomplete_isoc_in(udev);
}
@ -203,8 +220,10 @@ void usbd_isr (usb_core_driver *udev)
}
/* incomplete synchronization OUT transfer interrupt*/
if (intr & GINTF_ISOONCIF) {
if (NULL != udev->dev.class_core->incomplete_isoc_out) {
if (intr & GINTF_ISOONCIF)
{
if (NULL != udev->dev.class_core->incomplete_isoc_out)
{
(void)udev->dev.class_core->incomplete_isoc_out(udev);
}
@ -213,14 +232,16 @@ void usbd_isr (usb_core_driver *udev)
}
#if (1U == LPM_ENABLED)
if(intr & GINTF_LPMIF) {
if(intr & GINTF_LPMIF)
{
/* clear interrupt */
udev->regs.gr->GINTF = GINTF_LPMIF;
udev->dev.pm.BESL = (udev->regs.gr->GLPMCFG & GLPMCFG_BESL) >> 2U;
udev->dev.pm.dev_remote_wakeup = (udev->regs.gr->GLPMCFG & GLPMCFG_REW) >> 6U;
if(LPM_L0 == udev->dev.pm.lpm_state){
if(LPM_L0 == udev->dev.pm.lpm_state)
{
udev->dev.pm.lpm_state = LPM_L1;
usbd_int_lpm(udev, LPM_L1_ACTIVE);
}else{
@ -233,13 +254,16 @@ void usbd_isr (usb_core_driver *udev)
#ifdef VBUS_SENSING_ENABLED
/* session request interrupt */
if (intr & GINTF_SESIF) {
if (intr & GINTF_SESIF)
{
udev->regs.gr->GINTF = GINTF_SESIF;
}
/* OTG mode interrupt */
if (intr & GINTF_OTGIF) {
if(udev->regs.gr->GOTGINTF & GOTGINTF_SESEND) {
if (intr & GINTF_OTGIF)
{
if(udev->regs.gr->GOTGINTF & GOTGINTF_SESEND)
{
}
@ -261,16 +285,20 @@ static uint32_t usbd_int_epout (usb_core_driver *udev)
uint32_t epintnum = 0U;
uint8_t ep_num = 0U;
for (epintnum = usb_oepintnum_read (udev); epintnum; epintnum >>= 1U) {
if (epintnum & 0x01U) {
for (epintnum = usb_oepintnum_read (udev); epintnum; epintnum >>= 1U)
{
if (epintnum & 0x01U)
{
__IO uint32_t oepintr = usb_oepintr_read (udev, ep_num);
/* transfer complete interrupt */
if (oepintr & DOEPINTF_TF) {
if (oepintr & DOEPINTF_TF)
{
/* clear the bit in DOEPINTF for this interrupt */
udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_TF;
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode)
{
__IO uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN;
udev->dev.transc_out[ep_num].xfer_count = udev->dev.transc_out[ep_num].max_len - \
@ -280,15 +308,18 @@ static uint32_t usbd_int_epout (usb_core_driver *udev)
/* inform upper layer: data ready */
(void)usbd_out_transc (udev, ep_num);
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
if ((0U == ep_num) && ((uint8_t)USB_CTL_STATUS_OUT == udev->dev.control.ctl_state)) {
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode)
{
if ((0U == ep_num) && ((uint8_t)USB_CTL_STATUS_OUT == udev->dev.control.ctl_state))
{
usb_ctlep_startout (udev);
}
}
}
/* setup phase finished interrupt (control endpoints) */
if (oepintr & DOEPINTF_STPF) {
if (oepintr & DOEPINTF_STPF)
{
/* inform the upper layer that a setup packet is available */
(void)usbd_setup_transc (udev);
@ -313,24 +344,30 @@ static uint32_t usbd_int_epin (usb_core_driver *udev)
uint32_t epintnum = 0U;
uint8_t ep_num = 0U;
for (epintnum = usb_iepintnum_read (udev); epintnum; epintnum >>= 1U) {
if (epintnum & 0x1U) {
for (epintnum = usb_iepintnum_read (udev); epintnum; epintnum >>= 1U)
{
if (epintnum & 0x1U)
{
__IO uint32_t iepintr = usb_iepintr_read (udev, ep_num);
if (iepintr & DIEPINTF_TF) {
if (iepintr & DIEPINTF_TF)
{
udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TF;
/* data transmission is completed */
(void)usbd_in_transc (udev, ep_num);
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
if ((0U == ep_num) && ((uint8_t)USB_CTL_STATUS_IN == udev->dev.control.ctl_state)) {
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode)
{
if ((0U == ep_num) && ((uint8_t)USB_CTL_STATUS_IN == udev->dev.control.ctl_state))
{
usb_ctlep_startout (udev);
}
}
}
if (iepintr & DIEPINTF_TXFE) {
if (iepintr & DIEPINTF_TXFE)
{
usbd_emptytxfifo_write (udev, (uint32_t)ep_num);
udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TXFE;
@ -371,12 +408,14 @@ static uint32_t usbd_int_rxfifo (usb_core_driver *udev)
bcount = (devrxstat & GRSTATRP_BCOUNT) >> 4U;
data_PID = (uint8_t)((devrxstat & GRSTATRP_DPID) >> 15U);
switch ((devrxstat & GRSTATRP_RPCKST) >> 17U) {
switch ((devrxstat & GRSTATRP_RPCKST) >> 17U)
{
case RSTAT_GOUT_NAK:
break;
case RSTAT_DATA_UPDT:
if (bcount > 0U) {
if (bcount > 0U)
{
(void)usb_rxfifo_read (&udev->regs, transc->xfer_buf, (uint16_t)bcount);
transc->xfer_buf += bcount;
@ -393,7 +432,8 @@ static uint32_t usbd_int_rxfifo (usb_core_driver *udev)
break;
case RSTAT_SETUP_UPDT:
if ((0U == transc->ep_addr.num) && (8U == bcount) && (DPID_DATA0 == data_PID)) {
if ((0U == transc->ep_addr.num) && (8U == bcount) && (DPID_DATA0 == data_PID))
{
/* copy the setup packet received in FIFO into the setup buffer in RAM */
(void)usb_rxfifo_read (&udev->regs, (uint8_t *)&udev->dev.control.req, (uint16_t)bcount);
@ -427,7 +467,8 @@ static uint32_t usbd_int_reset (usb_core_driver *udev)
/* flush the TX FIFO */
(void)usb_txfifo_flush (&udev->regs, 0U);
for (i = 0U; i < udev->bp.num_ep; i++) {
for (i = 0U; i < udev->bp.num_ep; i++)
{
udev->regs.er_in[i]->DIEPINTF = 0xFFU;
udev->regs.er_out[i]->DOEPINTF = 0xFFU;
}
@ -461,14 +502,16 @@ static uint32_t usbd_int_reset (usb_core_driver *udev)
/* clear USB reset interrupt */
udev->regs.gr->GINTF = GINTF_RST;
udev->dev.transc_out[0] = (usb_transc) {
udev->dev.transc_out[0] = (usb_transc)
{
.ep_type = USB_EPTYPE_CTRL,
.max_len = USB_FS_EP0_MAX_LEN
};
(void)usb_transc_active (udev, &udev->dev.transc_out[0]);
udev->dev.transc_in[0] = (usb_transc) {
udev->dev.transc_in[0] = (usb_transc)
{
.ep_addr = {
.dir = 1U
},
@ -501,7 +544,8 @@ static uint32_t usbd_int_enumfinish (usb_core_driver *udev)
udev->regs.gr->GUSBCS &= ~GUSBCS_UTT;
/* set USB turn-around time based on device speed and PHY interface */
if ((uint8_t)USB_SPEED_HIGH == USB_SPEED[enum_speed]) {
if ((uint8_t)USB_SPEED_HIGH == USB_SPEED[enum_speed])
{
udev->bp.core_speed = (uint8_t)USB_SPEED_HIGH;
udev->regs.gr->GUSBCS |= 0x09U << 10U;
@ -532,7 +576,8 @@ static uint32_t usbd_int_suspend (usb_core_driver *udev)
udev->dev.backup_status = udev->dev.cur_status;
udev->dev.cur_status = (uint8_t)USBD_SUSPENDED;
if (low_power && suspend && is_configured) {
if (low_power && suspend && is_configured)
{
/* switch-off the OTG clocks */
*udev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK;
@ -558,13 +603,15 @@ static uint32_t usbd_int_wakeup(usb_core_driver *udev)
__IO uint8_t remote_wakeup = udev->dev.pm.dev_remote_wakeup;
#if (1U == LPM_ENABLED)
if(LPM_L1 == udev->dev.pm.lpm_state){
if(LPM_L1 == udev->dev.pm.lpm_state)
{
udev->dev.pm.lpm_state = LPM_L0;
usbd_int_lpm(udev, LPM_L0_ACTIVE);
}else
#endif /* LPM_ENABLED */
{
if(remote_wakeup && low_power){
if(remote_wakeup && low_power)
{
/* resume MCU CLK */
/* reset SLEEPDEEP bit of Cortex-M33 system control register */
@ -573,7 +620,8 @@ static uint32_t usbd_int_wakeup(usb_core_driver *udev)
usb_clock_active(udev);
if (USBD_SUSPENDED == udev->dev.cur_status) {
if (USBD_SUSPENDED == udev->dev.cur_status)
{
/* inform upper layer by the resume event */
udev->dev.cur_status = udev->dev.backup_status;
}
@ -605,14 +653,16 @@ static uint32_t usbd_int_lpm (usb_core_driver *udev, usb_lpm_type active_type)
__IO uint8_t suspend = (uint8_t)(udev->regs.dr->DSTAT & DSTAT_SPST);
__IO uint8_t is_configured = (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED)? 1U : 0U;
switch(active_type){
switch(active_type)
{
case LPM_L0_ACTIVE:
udev->dev.cur_status = udev->dev.backup_status;
/* switch-on the OTG clocks */
usb_clock_active(udev);
if(low_power){
if(low_power)
{
/* resume MCU CLK */
/* reset SLEEPDEEP bit of Cortex-M7 system control register */
@ -630,7 +680,8 @@ static uint32_t usbd_int_lpm (usb_core_driver *udev, usb_lpm_type active_type)
/* switch-off the OTG clocks */
*udev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK;
if(low_power){
if(low_power)
{
/* enter DEEP_SLEEP mode with LDO in low power mode */
pmu_to_deepsleepmode(WFI_CMD);
}
@ -659,17 +710,20 @@ static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num)
len = transc->xfer_len - transc->xfer_count;
/* get the data length to write */
if (len > transc->max_len) {
if (len > transc->max_len)
{
len = transc->max_len;
}
word_count = (len + 3U) / 4U;
while (((udev->regs.er_in[ep_num]->DIEPTFSTAT & DIEPTFSTAT_IEPTFS) >= word_count) && \
(transc->xfer_count < transc->xfer_len)) {
(transc->xfer_count < transc->xfer_len))
{
len = transc->xfer_len - transc->xfer_count;
if (len > transc->max_len) {
if (len > transc->max_len)
{
len = transc->max_len;
}
@ -682,7 +736,8 @@ static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num)
transc->xfer_buf += len;
transc->xfer_count += len;
if (transc->xfer_count == transc->xfer_len) {
if (transc->xfer_count == transc->xfer_len)
{
/* disable the device endpoint FIFO empty interrupt */
udev->regs.dr->DIEPFEINTEN &= ~(0x01U << ep_num);
}

186
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/driver/Source/drv_usbh_int.c
View File

@ -63,55 +63,66 @@ uint32_t usbh_isr (usb_core_driver *udev)
__IO uint32_t intr = 0U;
/* check if host mode */
if (HOST_MODE == (udev->regs.gr->GINTF & GINTF_COPM)) {
if (HOST_MODE == (udev->regs.gr->GINTF & GINTF_COPM))
{
intr = usb_coreintr_get(&udev->regs);
if (!intr) {
if (!intr)
{
return 0U;
}
if (intr & GINTF_SOF) {
if (intr & GINTF_SOF)
{
usbh_int_fop->SOF(udev->host.data);
/* clear interrupt */
udev->regs.gr->GINTF = GINTF_SOF;
}
if (intr & GINTF_RXFNEIF) {
if (intr & GINTF_RXFNEIF)
{
retval |= usbh_int_rxfifonoempty (udev);
}
if (intr & GINTF_NPTXFEIF) {
if (intr & GINTF_NPTXFEIF)
{
retval |= usbh_int_txfifoempty (udev, PIPE_NON_PERIOD);
}
if (intr & GINTF_PTXFEIF) {
if (intr & GINTF_PTXFEIF)
{
retval |= usbh_int_txfifoempty (udev, PIPE_PERIOD);
}
if (intr & GINTF_HCIF) {
if (intr & GINTF_HCIF)
{
retval |= usbh_int_pipe (udev);
}
if (intr & GINTF_HPIF) {
if (intr & GINTF_HPIF)
{
retval |= usbh_int_port (udev);
}
if (intr & GINTF_DISCIF) {
if (intr & GINTF_DISCIF)
{
usbh_int_fop->disconnect(udev->host.data);
/* clear interrupt */
udev->regs.gr->GINTF = GINTF_DISCIF;
}
if (intr & GINTF_ISOONCIF) {
if (intr & GINTF_ISOONCIF)
{
udev->regs.pr[0]->HCHCTL |= HCHCTL_CEN | HCHCTL_CDIS;
/* clear interrupt */
udev->regs.gr->GINTF = GINTF_ISOONCIF;
}
if (intr & GINTF_WKUPIF) {
if (intr & GINTF_WKUPIF)
{
/* clear interrupt */
udev->regs.gr->GINTF = GINTF_WKUPIF;
}
@ -164,7 +175,8 @@ static uint32_t usbh_int_port (usb_core_driver *udev)
port_state &= ~(HPCS_PE | HPCS_PCD | HPCS_PEDC);
/* port connect detected */
if (*udev->regs.HPCS & HPCS_PCD) {
if (*udev->regs.HPCS & HPCS_PCD)
{
port_state |= HPCS_PCD;
usbh_int_fop->connect(udev->host.data);
@ -173,17 +185,21 @@ static uint32_t usbh_int_port (usb_core_driver *udev)
}
/* port enable changed */
if (*udev->regs.HPCS & HPCS_PEDC) {
if (*udev->regs.HPCS & HPCS_PEDC)
{
port_state |= HPCS_PEDC;
if (*udev->regs.HPCS & HPCS_PE) {
if (*udev->regs.HPCS & HPCS_PE)
{
uint32_t port_speed = usb_curspeed_get(udev);
udev->host.connect_status = 1U;
if (PORT_SPEED_LOW == port_speed) {
if (PORT_SPEED_LOW == port_speed)
{
udev->regs.hr->HFT = 6000U;
} else if (PORT_SPEED_FULL == port_speed) {
} else if (PORT_SPEED_FULL == port_speed)
{
udev->regs.hr->HFT = 48000U;
} else {
}
@ -198,7 +214,8 @@ static uint32_t usbh_int_port (usb_core_driver *udev)
}
}
if (1U == port_reset) {
if (1U == port_reset)
{
usb_port_reset(udev);
}
@ -219,9 +236,12 @@ static uint32_t usbh_int_pipe (usb_core_driver *udev)
uint32_t pp_num = 0U;
uint32_t retval = 0U;
for (pp_num = 0U; pp_num < udev->bp.num_pipe; pp_num++) {
if ((udev->regs.hr->HACHINT & HACHINT_HACHINT) & (1U << pp_num)) {
if (udev->regs.pr[pp_num]->HCHCTL & HCHCTL_EPDIR) {
for (pp_num = 0U; pp_num < udev->bp.num_pipe; pp_num++)
{
if ((udev->regs.hr->HACHINT & HACHINT_HACHINT) & (1U << pp_num))
{
if (udev->regs.pr[pp_num]->HCHCTL & HCHCTL_EPDIR)
{
retval |= usbh_int_pipe_in (udev, pp_num);
} else {
retval |= usbh_int_pipe_out (udev, pp_num);
@ -253,9 +273,11 @@ static uint32_t usbh_int_pipe_in (usb_core_driver *udev, uint32_t pp_num)
uint8_t ep_type = (uint8_t)((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U);
if (intr_pp & HCHINTF_ACK) {
if (intr_pp & HCHINTF_ACK)
{
pp_reg->HCHINTF = HCHINTF_ACK;
} else if (intr_pp & HCHINTF_STALL) {
} else if (intr_pp & HCHINTF_STALL)
{
usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_STALL, PIPE_STALL);
pp_reg->HCHINTF = HCHINTF_NAK;
@ -263,17 +285,21 @@ static uint32_t usbh_int_pipe_in (usb_core_driver *udev, uint32_t pp_num)
else, the udev->host.pp_status = HC_STALL
will be overwritten by 'NAK' in code below */
intr_pp &= ~HCHINTF_NAK;
} else if (intr_pp & HCHINTF_DTER) {
} else if (intr_pp & HCHINTF_DTER)
{
usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_DTER, PIPE_DTGERR);
pp_reg->HCHINTF = HCHINTF_NAK;
} else {
/* no operation */
}
if (intr_pp & HCHINTF_REQOVR) {
if (intr_pp & HCHINTF_REQOVR)
{
usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_REQOVR, PIPE_REQOVR);
} else if (intr_pp & HCHINTF_TF) {
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
} else if (intr_pp & HCHINTF_TF)
{
if ((uint8_t)USB_USE_DMA == udev->bp.transfer_mode)
{
udev->host.backup_xfercount[pp_num] = pp->xfer_len - (pp_reg->HCHLEN & HCHLEN_TLEN);
}
@ -282,7 +308,8 @@ static uint32_t usbh_int_pipe_in (usb_core_driver *udev, uint32_t pp_num)
pp_reg->HCHINTF = HCHINTF_TF;
switch (ep_type) {
switch (ep_type)
{
case USB_EPTYPE_CTRL:
case USB_EPTYPE_BULK:
usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_XF);
@ -299,10 +326,12 @@ static uint32_t usbh_int_pipe_in (usb_core_driver *udev, uint32_t pp_num)
default:
break;
}
} else if (intr_pp & HCHINTF_CH) {
} else if (intr_pp & HCHINTF_CH)
{
pp_reg->HCHINTEN &= ~HCHINTEN_CHIE;
switch (pp->pp_status) {
switch (pp->pp_status)
{
case PIPE_XF:
pp->urb_state = URB_DONE;
break;
@ -326,19 +355,23 @@ static uint32_t usbh_int_pipe_in (usb_core_driver *udev, uint32_t pp_num)
case PIPE_BBERR:
case PIPE_REQOVR:
default:
if((uint8_t)USB_EPTYPE_INTR == ep_type) {
if((uint8_t)USB_EPTYPE_INTR == ep_type)
{
pp->data_toggle_in ^= 1U;
}
break;
}
pp_reg->HCHINTF = HCHINTF_CH;
} else if (intr_pp & HCHINTF_USBER) {
} else if (intr_pp & HCHINTF_USBER)
{
pp->err_count++;
usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_USBER, PIPE_TRACERR);
} else if (intr_pp & HCHINTF_NAK) {
} else if (intr_pp & HCHINTF_NAK)
{
pp_reg->HCHINTF = HCHINTF_NAK;
switch (ep_type) {
switch (ep_type)
{
case USB_EPTYPE_CTRL:
case USB_EPTYPE_BULK:
/* re-activate the channel */
@ -383,45 +416,60 @@ static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num)
uint32_t intr_pp = pp_reg->HCHINTF;
intr_pp &= pp_reg->HCHINTEN;
if (intr_pp & HCHINTF_ACK) {
if (1U == udev->host.pipe[pp_num].do_ping) {
if (intr_pp & HCHINTF_ACK)
{
if (1U == udev->host.pipe[pp_num].do_ping)
{
udev->host.pipe[pp_num].do_ping = 0;
pp->err_count = 0U;
usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_ACK, PIPE_NAK);
}
pp_reg->HCHINTF = HCHINTF_ACK;
} else if (intr_pp & HCHINTF_STALL) {
} else if (intr_pp & HCHINTF_STALL)
{
usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_STALL, PIPE_STALL);
} else if (intr_pp & HCHINTF_DTER) {
} else if (intr_pp & HCHINTF_DTER)
{
usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_DTER, PIPE_DTGERR);
pp_reg->HCHINTF = HCHINTF_NAK;
} else if (intr_pp & HCHINTF_REQOVR) {
} else if (intr_pp & HCHINTF_REQOVR)
{
usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_REQOVR, PIPE_REQOVR);
} else if (intr_pp & HCHINTF_TF) {
} else if (intr_pp & HCHINTF_TF)
{
pp->err_count = 0U;
usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_TF, PIPE_XF);
} else if (intr_pp & HCHINTF_NAK) {
if (0U == udev->host.pipe[pp_num].do_ping) {
if (1U == udev->host.pipe[pp_num].supp_ping) {
} else if (intr_pp & HCHINTF_NAK)
{
if (0U == udev->host.pipe[pp_num].do_ping)
{
if (1U == udev->host.pipe[pp_num].supp_ping)
{
udev->host.pipe[pp_num].do_ping = 1;
}
}
pp->err_count = 0U;
if(USB_USE_FIFO == udev->bp.transfer_mode) {
if(USB_USE_FIFO == udev->bp.transfer_mode)
{
usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_NAK);
} else {
pp_reg->HCHINTF = HCHINTF_NAK;
}
usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_NAK);
} else if (intr_pp & HCHINTF_USBER) {
} else if (intr_pp & HCHINTF_USBER)
{
pp->err_count++;
usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_USBER, PIPE_TRACERR);
} else if (intr_pp & HCHINTF_NYET) {
if (CTL_STATUS_OUT != uhost->control.ctl_state) {
if (0U == udev->host.pipe[pp_num].do_ping) {
if (1U == udev->host.pipe[pp_num].supp_ping) {
} else if (intr_pp & HCHINTF_NYET)
{
if (CTL_STATUS_OUT != uhost->control.ctl_state)
{
if (0U == udev->host.pipe[pp_num].do_ping)
{
if (1U == udev->host.pipe[pp_num].supp_ping)
{
udev->host.pipe[pp_num].do_ping = 1;
}
}
@ -432,14 +480,17 @@ static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num)
}
pp->err_count = 0U;
} else if (intr_pp & HCHINTF_CH) {
} else if (intr_pp & HCHINTF_CH)
{
udev->regs.pr[pp_num]->HCHINTEN &= ~HCHINTEN_CHIE;
switch (pp->pp_status) {
switch (pp->pp_status)
{
case PIPE_XF:
pp->urb_state = URB_DONE;
if ((uint8_t)USB_EPTYPE_BULK == ((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U)) {
if ((uint8_t)USB_EPTYPE_BULK == ((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U))
{
pp->data_toggle_out ^= 1U;
}
break;
@ -451,7 +502,8 @@ static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num)
case PIPE_NYET:
pp->urb_state = URB_DONE;
if ((uint8_t)USB_EPTYPE_BULK == ((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U)) {
if ((uint8_t)USB_EPTYPE_BULK == ((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U))
{
pp->data_toggle_out ^= 1U;
}
break;
@ -461,7 +513,8 @@ static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num)
break;
case PIPE_TRACERR:
if (3U == pp->err_count) {
if (3U == pp->err_count)
{
pp->urb_state = URB_ERROR;
pp->err_count = 0U;
}
@ -506,12 +559,14 @@ static uint32_t usbh_int_rxfifonoempty (usb_core_driver *udev)
rx_stat = udev->regs.gr->GRSTATP;
pp_num = (uint8_t)(rx_stat & GRSTATRP_CNUM);
switch ((rx_stat & GRSTATRP_RPCKST) >> 17U) {
switch ((rx_stat & GRSTATRP_RPCKST) >> 17U)
{
case GRXSTS_PKTSTS_IN:
count = (rx_stat & GRSTATRP_BCOUNT) >> 4U;
/* read the data into the host buffer. */
if ((NULL != udev->host.pipe[pp_num].xfer_buf) && (count > 0U)) {
if ((NULL != udev->host.pipe[pp_num].xfer_buf) && (count > 0U))
{
(void)usb_rxfifo_read (&udev->regs, udev->host.pipe[pp_num].xfer_buf, (uint16_t)count);
/* manage multiple transfer packet */
@ -522,7 +577,8 @@ static uint32_t usbh_int_rxfifonoempty (usb_core_driver *udev)
udev->host.backup_xfercount[pp_num] = xfer_count;
if (udev->regs.pr[pp_num]->HCHLEN & HCHLEN_PCNT) {
if (udev->regs.pr[pp_num]->HCHLEN & HCHLEN_PCNT)
{
/* re-activate the channel when more packets are expected */
uint32_t pp_ctl = udev->regs.pr[pp_num]->HCHCTL;
@ -540,7 +596,8 @@ static uint32_t usbh_int_rxfifonoempty (usb_core_driver *udev)
case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
count = (rx_stat & GRSTATRP_BCOUNT) >> 4U;
while (count > 0U) {
while (count > 0U)
{
rx_stat = udev->regs.gr->GRSTATP;
count--;
}
@ -575,9 +632,11 @@ static uint32_t usbh_int_txfifoempty (usb_core_driver *udev, usb_pipe_mode pp_mo
uint16_t word_count = 0U, len = 0U;
__IO uint32_t *txfiforeg = 0U, txfifostate = 0U;
if (PIPE_NON_PERIOD == pp_mode) {
if (PIPE_NON_PERIOD == pp_mode)
{
txfiforeg = &udev->regs.gr->HNPTFQSTAT;
} else if (PIPE_PERIOD == pp_mode) {
} else if (PIPE_PERIOD == pp_mode)
{
txfiforeg = &udev->regs.hr->HPTFQSTAT;
} else {
return 0U;
@ -589,14 +648,17 @@ static uint32_t usbh_int_txfifoempty (usb_core_driver *udev, usb_pipe_mode pp_mo
word_count = (uint16_t)(udev->host.pipe[pp_num].xfer_len + 3U) / 4U;
while (((txfifostate & TFQSTAT_TXFS) >= word_count) && (0U != udev->host.pipe[pp_num].xfer_len)) {
while (((txfifostate & TFQSTAT_TXFS) >= word_count) && (0U != udev->host.pipe[pp_num].xfer_len))
{
len = (uint16_t)(txfifostate & TFQSTAT_TXFS) * 4U;
if (len > udev->host.pipe[pp_num].xfer_len) {
if (len > udev->host.pipe[pp_num].xfer_len)
{
/* last packet */
len = (uint16_t)udev->host.pipe[pp_num].xfer_len;
if (PIPE_NON_PERIOD == pp_mode) {
if (PIPE_NON_PERIOD == pp_mode)
{
udev->regs.gr->GINTEN &= ~GINTEN_NPTXFEIE;
} else {
udev->regs.gr->GINTEN &= ~GINTEN_PTXFEIE;

96
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/class/cdc/Source/usbh_cdc_core.c
View File

@ -82,7 +82,8 @@ void cdc_data_send (usbh_host *uhost, uint8_t *data, uint16_t length)
{
usbh_cdc_handler *cdc = (usbh_cdc_handler *)uhost->active_class->class_data;
if (cdc->tx_param.cdc_cur_state == CDC_IDLE) {
if (cdc->tx_param.cdc_cur_state == CDC_IDLE)
{
cdc->tx_param.prxtx_buff = data;
cdc->tx_param.data_length = length;
cdc->tx_param.cdc_cur_state = CDC_SEND_DATA;
@ -101,7 +102,8 @@ void cdc_dummydata_send (usbh_host *uhost)
static uint8_t cdc_send_buf[17] = {0x43, 0x6F, 0x6E, 0x6E, 0x65, 0x63, 0x74, 0x69, 0x76, 0x69, 0x74, 0x79, 0x20, 0x6C, 0x69, 0x6E, 0x65};
if (cdc->tx_param.cdc_cur_state == CDC_IDLE) {
if (cdc->tx_param.cdc_cur_state == CDC_IDLE)
{
cdc->tx_param.prxtx_buff = cdc_send_buf;
cdc->tx_param.data_length = sizeof(cdc_send_buf);
cdc->tx_param.cdc_cur_state = CDC_SEND_DATA;
@ -148,10 +150,12 @@ usbh_status cdc_get_line_coding (usbh_host *uhost)
usbh_status status = USBH_BUSY;
usbh_cdc_handler *cdc = (usbh_cdc_handler *)uhost->active_class->class_data;
if (CTL_IDLE == uhost->control.ctl_state) {
if (CTL_IDLE == uhost->control.ctl_state)
{
usbh_control *usb_ctl = &uhost->control;
usb_ctl->setup.req = (usb_req) {
usb_ctl->setup.req = (usb_req)
{
.bmRequestType = USB_TRX_IN | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS,
.bRequest = GET_LINE_CODING,
.wValue = 0U,
@ -178,10 +182,12 @@ usbh_status cdc_set_line_coding (usbh_host *uhost)
usbh_status status = USBH_BUSY;
usbh_cdc_handler *cdc = (usbh_cdc_handler *)uhost->active_class->class_data;
if (CTL_IDLE == uhost->control.ctl_state) {
if (CTL_IDLE == uhost->control.ctl_state)
{
usbh_control *usb_ctl = &uhost->control;
usb_ctl->setup.req = (usb_req) {
usb_ctl->setup.req = (usb_req)
{
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS,
.bRequest = SET_LINE_CODING,
.wValue = 0U,
@ -207,10 +213,12 @@ usbh_status cdc_set_control_line_state (usbh_host *uhost)
{
usbh_status status = USBH_BUSY;
if (CTL_IDLE == uhost->control.ctl_state) {
if (CTL_IDLE == uhost->control.ctl_state)
{
usbh_control *usb_ctl = &uhost->control;
usb_ctl->setup.req = (usb_req) {
usb_ctl->setup.req = (usb_req)
{
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS,
.bRequest = SET_CONTROL_LINE_STATE,
.wValue = CDC_DEACTIVATE_CARRIER_SIGNAL_RTS | CDC_DEACTIVATE_SIGNAL_DTR,
@ -270,7 +278,8 @@ static usbh_status cdc_interface_init (usbh_host *uhost)
uint8_t interface = usbh_interface_find(&uhost->dev_prop, USB_CLASS_CDC, USB_CDC_SUBCLASS_ACM, USB_CDC_PROTOCOL_AT);
if (0xFFU == interface) {
if (0xFFU == interface)
{
uhost->usr_cb->dev_not_supported();
status = USBH_FAIL;
@ -286,7 +295,8 @@ static usbh_status cdc_interface_init (usbh_host *uhost)
usb_desc_ep *ep_desc = &uhost->dev_prop.cfg_desc_set.itf_desc_set[interface][0].ep_desc[0];
/* collect the notification endpoint address and length */
if (ep_desc->bEndpointAddress & 0x80U) {
if (ep_desc->bEndpointAddress & 0x80U)
{
cdc_handler.cmd_itf.ep_notify = ep_desc->bEndpointAddress;
cdc_handler.cmd_itf.ep_size_notify = ep_desc->wMaxPacketSize;
}
@ -307,7 +317,8 @@ static usbh_status cdc_interface_init (usbh_host *uhost)
ep_desc = &uhost->dev_prop.cfg_desc_set.itf_desc_set[interface][0].ep_desc[0];
if (ep_desc->bEndpointAddress & 0x80U) {
if (ep_desc->bEndpointAddress & 0x80U)
{
cdc_handler.data_itf.ep_in = ep_desc->bEndpointAddress;
cdc_handler.data_itf.ep_size_in = ep_desc->wMaxPacketSize;
} else {
@ -317,7 +328,8 @@ static usbh_status cdc_interface_init (usbh_host *uhost)
ep_desc = &uhost->dev_prop.cfg_desc_set.itf_desc_set[interface][0].ep_desc[1];
if (ep_desc->bEndpointAddress & 0x80U) {
if (ep_desc->bEndpointAddress & 0x80U)
{
cdc_handler.data_itf.ep_in = ep_desc->bEndpointAddress;
cdc_handler.data_itf.ep_size_in = ep_desc->wMaxPacketSize;
} else {
@ -368,7 +380,8 @@ static void cdc_interface_deinit (usbh_host *uhost)
usbh_cdc_handler *cdc = (usbh_cdc_handler *)uhost->active_class->class_data;
/* reset the channel as free */
if (cdc->cmd_itf.pipe_notify) {
if (cdc->cmd_itf.pipe_notify)
{
usb_pipe_halt (uhost->data, cdc->cmd_itf.pipe_notify);
usbh_pipe_free (uhost->data, cdc->cmd_itf.pipe_notify);
@ -376,7 +389,8 @@ static void cdc_interface_deinit (usbh_host *uhost)
}
/* reset the channel as free */
if (cdc->data_itf.pipe_out) {
if (cdc->data_itf.pipe_out)
{
usb_pipe_halt (uhost->data, cdc->data_itf.pipe_out);
usbh_pipe_free (uhost->data, cdc->data_itf.pipe_out);
@ -384,7 +398,8 @@ static void cdc_interface_deinit (usbh_host *uhost)
}
/* reset the channel as free */
if (cdc->data_itf.pipe_in) {
if (cdc->data_itf.pipe_in)
{
usb_pipe_halt (uhost->data, cdc->data_itf.pipe_in);
usbh_pipe_free (uhost->data, cdc->data_itf.pipe_in);
@ -405,12 +420,14 @@ static usbh_status cdc_class_request (usbh_host *uhost)
usbh_status class_req_status = USBH_BUSY;
usbh_cdc_handler *cdc = (usbh_cdc_handler *)uhost->active_class->class_data;
switch (cdc->req_state) {
switch (cdc->req_state)
{
case CDC_GET_LINE_CODING_RQUEST:
/* issue the get line coding request */
class_req_status = cdc_get_line_coding(uhost);
if (USBH_OK == class_req_status) {
if (USBH_OK == class_req_status)
{
cdc->req_state = CDC_SET_CONTROL_LINE_STATE_REQUEST;
}
break;
@ -419,11 +436,13 @@ static usbh_status cdc_class_request (usbh_host *uhost)
/* issue the set line coding request */
class_req_status = cdc_set_line_coding(uhost);
if (USBH_OK == class_req_status) {
if (USBH_OK == class_req_status)
{
cdc->req_state = CDC_GET_LINE_CODING_RQUEST;
}
if (USBH_NOT_SUPPORTED == class_req_status) {
if (USBH_NOT_SUPPORTED == class_req_status)
{
/* a clear feature should be issued here */
cdc->req_state = CDC_ERROR_STATE;
}
@ -433,7 +452,8 @@ static usbh_status cdc_class_request (usbh_host *uhost)
/* issue the set control line coding */
class_req_status = cdc_set_control_line_state(uhost);
if (USBH_OK == class_req_status) {
if (USBH_OK == class_req_status)
{
cdc->req_state = CDC_SET_CONTROL_LINE_STATE_REQUEST;
/* also set the state of receive CDCRxParam to IDLE */
@ -446,7 +466,8 @@ static usbh_status cdc_class_request (usbh_host *uhost)
case CDC_ERROR_STATE:
class_req_status = usbh_clrfeature(uhost, 0x00U, uhost->control.pipe_out_num);
if (USBH_OK == class_req_status) {
if (USBH_OK == class_req_status)
{
cdc->req_state = CDC_GET_LINE_CODING_RQUEST;
}
break;
@ -494,14 +515,17 @@ static void cdc_process_transmission(usbh_host *uhost)
urb_status_tx = usbh_urbstate_get(uhost->data, cdc->data_itf.pipe_out);
switch (cdc->tx_param.cdc_cur_state) {
switch (cdc->tx_param.cdc_cur_state)
{
case CDC_IDLE:
break;
case CDC_SEND_DATA:
if ((urb_status_tx == URB_DONE) || (urb_status_tx == URB_IDLE)) {
if ((urb_status_tx == URB_DONE) || (urb_status_tx == URB_IDLE))
{
/* check the data length is more then the usbh_cdc_handler.data_itf.length */
if (cdc->tx_param.data_length > cdc->data_itf.ep_size_out) {
if (cdc->tx_param.data_length > cdc->data_itf.ep_size_out)
{
len = cdc->data_itf.ep_size_out;
/* send the data */
@ -525,19 +549,22 @@ static void cdc_process_transmission(usbh_host *uhost)
case CDC_DATA_SENT:
/* check the status done for transmission */
if (urb_status_tx == URB_DONE) {
if (urb_status_tx == URB_DONE)
{
/* point to next chunk of data */
cdc->tx_param.prxtx_buff += len;
/* decrease the data length */
cdc->tx_param.data_length -= len;
if (cdc->tx_param.data_length == 0U) {
if (cdc->tx_param.data_length == 0U)
{
cdc->tx_param.cdc_cur_state = CDC_IDLE;
} else {
cdc->tx_param.cdc_cur_state = CDC_SEND_DATA;
}
} else if (urb_status_tx == URB_NOTREADY) {
} else if (urb_status_tx == URB_NOTREADY)
{
/* send the same data */
usbh_data_send (uhost->data,
(cdc->tx_param.prxtx_buff),
@ -562,13 +589,16 @@ static void cdc_process_reception(usbh_host *uhost)
usb_core_driver *udev = (usb_core_driver *)uhost->data;
usbh_cdc_handler *cdc = (usbh_cdc_handler *)uhost->active_class->class_data;
if (cdc->rx_enabled == 1) {
if (cdc->rx_enabled == 1)
{
usb_urb_state urb_status_rx = usbh_urbstate_get(udev, cdc->data_itf.pipe_in);
switch (cdc->rx_param.cdc_cur_state) {
switch (cdc->rx_param.cdc_cur_state)
{
case CDC_IDLE:
/* check the received length lesser then the remaining space available in the buffer */
if (cdc->rx_param.data_length < (cdc->rx_param.buffer_len - cdc->data_itf.ep_size_in)) {
if (cdc->rx_param.data_length < (cdc->rx_param.buffer_len - cdc->data_itf.ep_size_in))
{
/* receive the data */
usbh_data_recev(udev,
cdc->rx_param.pfill_buff,
@ -582,7 +612,8 @@ static void cdc_process_reception(usbh_host *uhost)
case CDC_GET_DATA:
/* check the last state of the device is URB_DONE */
if (urb_status_rx == URB_DONE) {
if (urb_status_rx == URB_DONE)
{
/* move the pointer as well as data length */
cdc->rx_param.data_length += udev->host.pipe[cdc->data_itf.pipe_in].xfer_count;
cdc->rx_param.pfill_buff += udev->host.pipe[cdc->data_itf.pipe_in].xfer_count;
@ -635,7 +666,8 @@ static void cdc_receive_data(usbh_host *uhost, cdc_xfer *cdc_data)
{
usbh_cdc_handler *cdc = (usbh_cdc_handler *)uhost->active_class->class_data;
if (cdc_data->pempty_buff < cdc_data->pfill_buff) {
if (cdc_data->pempty_buff < cdc_data->pfill_buff)
{
/* redirect the received data on the user out put system */
cdc->user_cb.receive(cdc_data->pempty_buff);

2
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/class/hid/Include/usbh_hid_keybd.h
View File

@ -38,7 +38,7 @@ OF SUCH DAMAGE.
#include "usb_conf.h"
#include "usbh_hid_core.h"
//#define AZERTY_KEYBOARD
/*#define AZERTY_KEYBOARD*/
#define QWERTY_KEYBOARD
#define KBD_LEFT_CTRL 0x01U

141
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/class/hid/Source/usbh_hid_core.c
View File

@ -78,8 +78,10 @@ usbh_status usbh_get_report (usbh_host *uhost,
{
usbh_status status = USBH_BUSY;
if (CTL_IDLE == uhost->control.ctl_state) {
uhost->control.setup.req = (usb_req) {
if (CTL_IDLE == uhost->control.ctl_state)
{
uhost->control.setup.req = (usb_req)
{
.bmRequestType = USB_TRX_IN | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS,
.bRequest = GET_REPORT,
.wValue = (report_type << 8U) | report_ID,
@ -115,8 +117,10 @@ usbh_status usbh_set_report (usb_core_driver *udev,
{
usbh_status status = USBH_BUSY;
if (CTL_IDLE == uhost->control.ctl_state) {
uhost->control.setup.req = (usb_req) {
if (CTL_IDLE == uhost->control.ctl_state)
{
uhost->control.setup.req = (usb_req)
{
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS,
.bRequest = SET_REPORT,
.wValue = (report_type << 8U) | report_ID,
@ -144,13 +148,16 @@ hid_type usbh_hid_device_type_get(usb_core_driver *udev, usbh_host *uhost)
hid_type type = HID_UNKNOWN;
uint8_t interface_protocol;
if (HOST_CLASS_HANDLER == uhost->cur_state) {
if (HOST_CLASS_HANDLER == uhost->cur_state)
{
interface_protocol = uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].itf_desc.bInterfaceProtocol;
if (USB_HID_PROTOCOL_KEYBOARD == interface_protocol) {
if (USB_HID_PROTOCOL_KEYBOARD == interface_protocol)
{
type = HID_KEYBOARD;
} else {
if (USB_HID_PROTOCOL_MOUSE == interface_protocol) {
if (USB_HID_PROTOCOL_MOUSE == interface_protocol)
{
type = HID_MOUSE;
}
}
@ -173,7 +180,8 @@ uint8_t usbh_hid_poll_interval_get (usb_core_driver *udev, usbh_host *uhost)
if ((HOST_CLASS_ENUM == uhost->cur_state) ||
(HOST_USER_INPUT == uhost->cur_state) ||
(HOST_CHECK_CLASS == uhost->cur_state) ||
(HOST_CLASS_HANDLER == uhost->cur_state)) {
(HOST_CLASS_HANDLER == uhost->cur_state))
{
return (uint8_t)(hid->poll);
} else {
return 0U;
@ -193,15 +201,19 @@ uint16_t usbh_hid_fifo_read (data_fifo *fifo, void *buf, uint16_t nbytes)
uint16_t i = 0U;
uint8_t *p = (uint8_t*) buf;
if (0U == fifo->lock) {
if (0U == fifo->lock)
{
fifo->lock = 1U;
for (i = 0U; i < nbytes; i++) {
if (fifo->tail != fifo->head) {
for (i = 0U; i < nbytes; i++)
{
if (fifo->tail != fifo->head)
{
*p++ = fifo->buf[fifo->tail];
fifo->tail++;
if (fifo->tail == fifo->size) {
if (fifo->tail == fifo->size)
{
fifo->tail = 0U;
}
} else {
@ -230,12 +242,15 @@ uint16_t usbh_hid_fifo_write (data_fifo *fifo, void *buf, uint16_t nbytes)
uint16_t i = 0U;
uint8_t *p = (uint8_t*) buf;
if (0U == fifo->lock) {
if (0U == fifo->lock)
{
fifo->lock = 1U;
for (i = 0U; i < nbytes; i++) {
for (i = 0U; i < nbytes; i++)
{
if ((fifo->head + 1U == fifo->tail) ||
((fifo->head + 1U == fifo->size) && (0U == fifo->tail))) {
((fifo->head + 1U == fifo->size) && (0U == fifo->tail)))
{
fifo->lock = 0U;
return i;
@ -243,7 +258,8 @@ uint16_t usbh_hid_fifo_write (data_fifo *fifo, void *buf, uint16_t nbytes)
fifo->buf[fifo->head] = *p++;
fifo->head++;
if (fifo->head == fifo->size) {
if (fifo->head == fifo->size)
{
fifo->head = 0U;
}
}
@ -300,7 +316,8 @@ static void usbh_hid_itf_deinit (usbh_host *uhost)
{
usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data;
if (0x00U != hid->pipe_in) {
if (0x00U != hid->pipe_in)
{
usb_pipe_halt (uhost->data, hid->pipe_in);
usbh_pipe_free (uhost->data, hid->pipe_in);
@ -309,7 +326,8 @@ static void usbh_hid_itf_deinit (usbh_host *uhost)
hid->pipe_in = 0U;
}
if (0x00U != hid->pipe_out) {
if (0x00U != hid->pipe_out)
{
usb_pipe_halt (uhost->data, hid->pipe_out);
usbh_pipe_free (uhost->data, hid->pipe_out);
@ -332,7 +350,8 @@ static usbh_status usbh_hid_itf_init (usbh_host *uhost)
interface = usbh_interface_find(&uhost->dev_prop, USB_HID_CLASS, USB_HID_SUBCLASS_BOOT_ITF, 0xFFU);
if (0xFFU == interface) {
if (0xFFU == interface)
{
uhost->usr_cb->dev_not_supported();
status = USBH_FAIL;
@ -346,10 +365,12 @@ static usbh_status usbh_hid_itf_init (usbh_host *uhost)
hid_handler.state = HID_ERROR;
uint8_t itf_protocol = uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].itf_desc.bInterfaceProtocol;
if (USB_HID_PROTOCOL_KEYBOARD == itf_protocol) {
if (USB_HID_PROTOCOL_KEYBOARD == itf_protocol)
{
hid_handler.init = usbh_hid_keybd_init;
hid_handler.machine = usbh_hid_keybrd_machine;
} else if (USB_HID_PROTOCOL_MOUSE == itf_protocol) {
} else if (USB_HID_PROTOCOL_MOUSE == itf_protocol)
{
hid_handler.init = usbh_hid_mouse_init;
hid_handler.machine = usbh_hid_mouse_machine;
} else {
@ -362,7 +383,8 @@ static usbh_status usbh_hid_itf_init (usbh_host *uhost)
hid_handler.len = uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].ep_desc[0].wMaxPacketSize;
hid_handler.poll = uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].ep_desc[0].bInterval;
if (hid_handler.poll < HID_MIN_POLL) {
if (hid_handler.poll < HID_MIN_POLL)
{
hid_handler.poll = HID_MIN_POLL;
}
@ -372,12 +394,14 @@ static usbh_status usbh_hid_itf_init (usbh_host *uhost)
ep_num = USB_MIN(uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].itf_desc.bNumEndpoints, USBH_MAX_EP_NUM);
/* decode endpoint IN and OUT address from interface descriptor */
for (num = 0U; num < ep_num; num++) {
for (num = 0U; num < ep_num; num++)
{
usb_desc_ep *ep_desc = &uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].ep_desc[num];
uint8_t ep_addr = ep_desc->bEndpointAddress;
if (ep_addr & 0x80U) {
if (ep_addr & 0x80U)
{
hid_handler.ep_in = ep_addr;
hid_handler.pipe_in = usbh_pipe_allocate (uhost->data, ep_addr);
@ -426,11 +450,13 @@ static usbh_status usbh_hid_class_req (usbh_host *uhost)
usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data;
/* handle HID control state machine */
switch (hid->ctl_state) {
switch (hid->ctl_state)
{
case HID_REQ_INIT:
case HID_REQ_GET_HID_DESC:
/* get HID descriptor */
if (USBH_OK == usbh_hid_desc_get (uhost, USB_HID_DESC_SIZE)) {
if (USBH_OK == usbh_hid_desc_get (uhost, USB_HID_DESC_SIZE))
{
usbh_hiddesc_parse(&hid->hid_desc, uhost->dev_prop.data);
hid->ctl_state = HID_REQ_GET_REPORT_DESC;
@ -439,7 +465,8 @@ static usbh_status usbh_hid_class_req (usbh_host *uhost)
case HID_REQ_GET_REPORT_DESC:
/* get report descriptor */
if (USBH_OK == usbh_hid_reportdesc_get(uhost, hid->hid_desc.wDescriptorLength)) {
if (USBH_OK == usbh_hid_reportdesc_get(uhost, hid->hid_desc.wDescriptorLength))
{
hid->ctl_state = HID_REQ_SET_IDLE;
}
break;
@ -448,10 +475,12 @@ static usbh_status usbh_hid_class_req (usbh_host *uhost)
class_req_status = usbh_set_idle (uhost, 0U, 0U);
/* set idle */
if (USBH_OK == class_req_status) {
if (USBH_OK == class_req_status)
{
hid->ctl_state = HID_REQ_SET_PROTOCOL;
} else {
if(USBH_NOT_SUPPORTED == class_req_status) {
if(USBH_NOT_SUPPORTED == class_req_status)
{
hid->ctl_state = HID_REQ_SET_PROTOCOL;
}
}
@ -459,7 +488,8 @@ static usbh_status usbh_hid_class_req (usbh_host *uhost)
case HID_REQ_SET_PROTOCOL:
/* set protocol */
if (USBH_OK == usbh_set_protocol (uhost, 0U)) {
if (USBH_OK == usbh_set_protocol (uhost, 0U))
{
hid->ctl_state = HID_REQ_IDLE;
/* all requests performed */
@ -486,7 +516,8 @@ static usbh_status usbh_hid_handle (usbh_host *uhost)
usbh_status status = USBH_OK;
usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data;
switch (hid->state) {
switch (hid->state)
{
case HID_INIT:
hid->init(uhost->data, uhost);
hid->state = HID_IDLE;
@ -499,7 +530,8 @@ static usbh_status usbh_hid_handle (usbh_host *uhost)
case HID_SYNC:
/* sync with start of even frame */
if (true == usb_frame_even(uhost->data)) {
if (true == usb_frame_even(uhost->data))
{
hid->state = HID_GET_DATA;
}
break;
@ -513,16 +545,20 @@ static usbh_status usbh_hid_handle (usbh_host *uhost)
break;
case HID_POLL:
if (URB_DONE == usbh_urbstate_get (uhost->data, hid->pipe_in)) {
if (0U == hid->data_ready) { /* handle data once */
if (URB_DONE == usbh_urbstate_get (uhost->data, hid->pipe_in))
{
if (0U == hid->data_ready)
{ /* handle data once */
usbh_hid_fifo_write(&hid->fifo, hid->pdata, hid->len);
hid->data_ready = 1U;
hid->machine(uhost->data, uhost);
}
} else {
if (URB_STALL == usbh_urbstate_get (uhost->data, hid->pipe_in)) { /* IN endpoint stalled */
if (URB_STALL == usbh_urbstate_get (uhost->data, hid->pipe_in))
{ /* IN endpoint stalled */
/* issue clear feature on interrupt in endpoint */
if (USBH_OK == (usbh_clrfeature (uhost, hid->ep_addr, hid->pipe_in))) {
if (USBH_OK == (usbh_clrfeature (uhost, hid->ep_addr, hid->pipe_in)))
{
/* change state to issue next in token */
hid->state = HID_GET_DATA;
}
@ -547,8 +583,10 @@ static usbh_status usbh_hid_reportdesc_get (usbh_host *uhost, uint16_t len)
{
usbh_status status = USBH_BUSY;
if (CTL_IDLE == uhost->control.ctl_state) {
uhost->control.setup.req = (usb_req) {
if (CTL_IDLE == uhost->control.ctl_state)
{
uhost->control.setup.req = (usb_req)
{
.bmRequestType = USB_TRX_IN | USB_RECPTYPE_ITF | USB_REQTYPE_STRD,
.bRequest = USB_GET_DESCRIPTOR,
.wValue = USBH_DESC(USB_DESCTYPE_REPORT),
@ -574,12 +612,15 @@ static usbh_status usbh_hid_sof(usbh_host *uhost)
{
usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data;
if (HID_POLL == hid->state) {
if (HID_POLL == hid->state)
{
uint32_t frame_count = usb_curframe_get (uhost->data);
if ((frame_count > hid->timer) && ((frame_count - hid->timer) >= hid->poll)) {
if ((frame_count > hid->timer) && ((frame_count - hid->timer) >= hid->poll))
{
hid->state = HID_GET_DATA;
} else if ((frame_count < hid->timer) && ((frame_count + 0x3FFFU - hid->timer) >= hid->poll)) {
} else if ((frame_count < hid->timer) && ((frame_count + 0x3FFFU - hid->timer) >= hid->poll))
{
hid->state = HID_GET_DATA;
} else {
/* no operation */
@ -600,8 +641,10 @@ static usbh_status usbh_hid_desc_get (usbh_host *uhost, uint16_t len)
{
usbh_status status = USBH_BUSY;
if (CTL_IDLE == uhost->control.ctl_state) {
uhost->control.setup.req = (usb_req) {
if (CTL_IDLE == uhost->control.ctl_state)
{
uhost->control.setup.req = (usb_req)
{
.bmRequestType = USB_TRX_IN | USB_RECPTYPE_ITF | USB_REQTYPE_STRD,
.bRequest = USB_GET_DESCRIPTOR,
.wValue = USBH_DESC(USB_DESCTYPE_HID),
@ -629,8 +672,10 @@ static usbh_status usbh_set_idle (usbh_host *uhost, uint8_t duration, uint8_t re
{
usbh_status status = USBH_BUSY;
if (CTL_IDLE == uhost->control.ctl_state) {
uhost->control.setup.req = (usb_req) {
if (CTL_IDLE == uhost->control.ctl_state)
{
uhost->control.setup.req = (usb_req)
{
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS,
.bRequest = SET_IDLE,
.wValue = (duration << 8U) | report_ID,
@ -657,8 +702,10 @@ static usbh_status usbh_set_protocol (usbh_host *uhost, uint8_t protocol)
{
usbh_status status = USBH_BUSY;
if (CTL_IDLE == uhost->control.ctl_state) {
uhost->control.setup.req = (usb_req) {
if (CTL_IDLE == uhost->control.ctl_state)
{
uhost->control.setup.req = (usb_req)
{
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS,
.bRequest = SET_PROTOCOL,
.wValue = !protocol,

27
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/class/hid/Source/usbh_hid_keybd.c
View File

@ -287,11 +287,13 @@ usbh_status usbh_hid_keybd_init (usb_core_driver *udev, usbh_host *uhost)
keybd_info.rctrl = keybd_info.rshift = 0U;
keybd_info.ralt = keybd_info.rgui = 0U;
for (uint32_t x = 0U; x < (sizeof(keybd_report_data) / sizeof(uint32_t)); x++) {
for (uint32_t x = 0U; x < (sizeof(keybd_report_data) / sizeof(uint32_t)); x++)
{
keybd_report_data[x] = 0U;
}
if (hid->len > (sizeof(keybd_report_data) / sizeof(uint32_t))) {
if (hid->len > (sizeof(keybd_report_data) / sizeof(uint32_t)))
{
hid->len = (sizeof(keybd_report_data) / sizeof(uint32_t));
}
@ -314,7 +316,8 @@ usbh_status usbh_hid_keybd_init (usb_core_driver *udev, usbh_host *uhost)
*/
hid_keybd_info *usbh_hid_keybd_info_get (usb_core_driver *udev, usbh_host *uhost)
{
if (USBH_OK == usbh_hid_keybrd_decode(udev, uhost)) {
if (USBH_OK == usbh_hid_keybrd_decode(udev, uhost))
{
return &keybd_info;
} else {
return NULL;
@ -330,7 +333,8 @@ hid_keybd_info *usbh_hid_keybd_info_get (usb_core_driver *udev, usbh_host *uhost
uint8_t usbh_hid_ascii_code_get (hid_keybd_info *info)
{
uint8_t output;
if ((1U == info->lshift) || (info->rshift)) {
if ((1U == info->lshift) || (info->rshift))
{
output = hid_keybrd_shiftkey[hid_keybrd_codes[info->keys[0]]];
} else {
output = hid_keybrd_key[hid_keybrd_codes[info->keys[0]]];
@ -352,10 +356,12 @@ void usbh_hid_keybrd_machine (usb_core_driver *udev, usbh_host *uhost)
k_pinfo = usbh_hid_keybd_info_get(udev, uhost);
if (k_pinfo != NULL) {
if (k_pinfo != NULL)
{
char c = usbh_hid_ascii_code_get(k_pinfo);
if (c != 0U) {
if (c != 0U)
{
usr_keybrd_process_data(c);
}
}
@ -372,12 +378,14 @@ static usbh_status usbh_hid_keybrd_decode (usb_core_driver *udev, usbh_host *uho
{
usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data;
if (0U == hid->len) {
if (0U == hid->len)
{
return USBH_FAIL;
}
/* fill report */
if (usbh_hid_fifo_read (&hid->fifo, &keybd_report_data, hid->len) == hid->len) {
if (usbh_hid_fifo_read (&hid->fifo, &keybd_report_data, hid->len) == hid->len)
{
keybd_info.lctrl = (uint8_t)hid_item_read((hid_report_item *)&imp_0_lctrl, 0U);
keybd_info.lshift = (uint8_t)hid_item_read((hid_report_item *)&imp_0_lshift, 0U);
keybd_info.lalt = (uint8_t)hid_item_read((hid_report_item *)&imp_0_lalt, 0U);
@ -387,7 +395,8 @@ static usbh_status usbh_hid_keybrd_decode (usb_core_driver *udev, usbh_host *uho
keybd_info.ralt = (uint8_t)hid_item_read((hid_report_item *)&imp_0_ralt, 0U);
keybd_info.rgui = (uint8_t)hid_item_read((hid_report_item *)&imp_0_rgui, 0U);
for (uint8_t x = 0U; x < sizeof(keybd_info.keys); x++) {
for (uint8_t x = 0U; x < sizeof(keybd_info.keys); x++)
{
keybd_info.keys[x] = (uint8_t)hid_item_read((hid_report_item *)&imp_0_key_array, x);
}

17
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/class/hid/Source/usbh_hid_mouse.c
View File

@ -34,7 +34,7 @@ OF SUCH DAMAGE.
#include "usbh_hid_mouse.h"
#include "usbh_hid_parser.h"
//#include "usbh_hid_usr.h"
/*#include "usbh_hid_usr.h"*/
hid_mouse_info mouse_info;
uint32_t mouse_report_data[2];
@ -137,7 +137,8 @@ usbh_status usbh_hid_mouse_init (usb_core_driver *udev, usbh_host *uhost)
mouse_report_data[0] = 0U;
if(hid->len > sizeof(mouse_report_data)) {
if(hid->len > sizeof(mouse_report_data))
{
hid->len = sizeof(mouse_report_data);
}
@ -159,7 +160,8 @@ usbh_status usbh_hid_mouse_init (usb_core_driver *udev, usbh_host *uhost)
*/
hid_mouse_info *usbh_hid_mouse_info_get (usb_core_driver *udev, usbh_host *uhost)
{
if(usbh_hid_mouse_decode(udev, uhost)== USBH_OK) {
if(usbh_hid_mouse_decode(udev, uhost)== USBH_OK)
{
return &mouse_info;
} else {
return NULL;
@ -179,7 +181,8 @@ void usbh_hid_mouse_machine (usb_core_driver *udev, usbh_host *uhost)
m_pinfo = usbh_hid_mouse_info_get(udev, uhost);
if (NULL != m_pinfo) {
if (NULL != m_pinfo)
{
/* handle mouse data position */
usr_mouse_process_data(&mouse_info);
}
@ -196,12 +199,14 @@ static usbh_status usbh_hid_mouse_decode(usb_core_driver *udev, usbh_host *uhost
{
usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data;
if (0U == hid->len) {
if (0U == hid->len)
{
return USBH_FAIL;
}
/* fill report */
if (usbh_hid_fifo_read(&hid->fifo, &mouse_report_data, hid->len) == hid->len) {
if (usbh_hid_fifo_read(&hid->fifo, &mouse_report_data, hid->len) == hid->len)
{
/* decode report */
mouse_info.x = (uint8_t)hid_item_read((hid_report_item *)&prop_x, 0U);
mouse_info.y = (uint8_t)hid_item_read((hid_report_item *)&prop_y, 0U);

36
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/class/hid/Source/usbh_hid_parser.c
View File

@ -51,9 +51,11 @@ uint32_t hid_item_read (hid_report_item *ri, uint8_t ndx)
/* get the logical value of the item */
/* if this is an array, wee may need to offset ri->data.*/
if (ri->count > 0U) {
if (ri->count > 0U)
{
/* if APP tries to read outside of the array. */
if (ri->count <= ndx) {
if (ri->count <= ndx)
{
return(0U);
}
@ -67,28 +69,33 @@ uint32_t hid_item_read (hid_report_item *ri, uint8_t ndx)
}
/* read data bytes in little endian order */
for (uint32_t x = 0U; x < ((ri->size & 0x7U) ? (ri->size / 8U) + 1U : (ri->size / 8U)); x++) {
for (uint32_t x = 0U; x < ((ri->size & 0x7U) ? (ri->size / 8U) + 1U : (ri->size / 8U)); x++)
{
val=(uint32_t)((uint32_t)(*data) << (x * 8U));
}
val=(val >> shift) & ((1U << ri->size) - 1U);
if ((val < ri->logical_min) || (val > ri->logical_max)) {
if ((val < ri->logical_min) || (val > ri->logical_max))
{
return(0U);
}
/* convert logical value to physical value */
/* see if the number is negative or not. */
if ((ri->sign) && (val & (1U << (ri->size - 1U)))) {
if ((ri->sign) && (val & (1U << (ri->size - 1U))))
{
/* yes, so sign extend value to 32 bits. */
uint32_t vs = (uint32_t)((0xffffffffU & ~((1U << (ri->size)) - 1U)) | val);
if (1U == ri->resolution) {
if (1U == ri->resolution)
{
return((uint32_t)vs);
}
return((uint32_t)(vs * ri->resolution));
} else {
if (1U == ri->resolution) {
if (1U == ri->resolution)
{
return(val);
}
@ -111,14 +118,17 @@ uint32_t hid_item_write(hid_report_item *ri, uint32_t value, uint8_t ndx)
uint8_t *data = ri->data;
uint8_t shift = ri->shift;
if ((value < ri->physical_min) || (value > ri->physical_max)) {
if ((value < ri->physical_min) || (value > ri->physical_max))
{
return(1U);
}
/* if this is an array, wee may need to offset ri->data.*/
if (ri->count > 0U) {
if (ri->count > 0U)
{
/* if APP tries to read outside of the array. */
if (ri->count >= ndx) {
if (ri->count >= ndx)
{
return(0U);
}
@ -132,7 +142,8 @@ uint32_t hid_item_write(hid_report_item *ri, uint32_t value, uint8_t ndx)
}
/* convert physical value to logical value. */
if (1U != ri->resolution) {
if (1U != ri->resolution)
{
value = value / ri->resolution;
}
@ -140,7 +151,8 @@ uint32_t hid_item_write(hid_report_item *ri, uint32_t value, uint8_t ndx)
mask = (1U << ri->size) - 1U;
value = (value & mask) << shift;
for (uint32_t x = 0U; x < ((ri->size & 0x7U) ? (ri->size / 8U) + 1U : (ri->size / 8U)); x++) {
for (uint32_t x = 0U; x < ((ri->size & 0x7U) ? (ri->size / 8U) + 1U : (ri->size / 8U)); x++)
{
*(ri->data + x) = (uint8_t)((*(ri->data+x) & ~(mask>>(x* 8U))) | ((value >> (x * 8U)) & (mask >> (x * 8U))));
}

96
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/class/msc/Source/usbh_msc_bbb.c
View File

@ -70,7 +70,8 @@ usbh_status usbh_msc_bot_process(usbh_host *uhost, uint8_t lun)
usb_urb_state urb_status = URB_IDLE;
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
switch(msc->bot.state) {
switch(msc->bot.state)
{
case BOT_SEND_CBW:
msc->bot.cbw.field.bCBWLUN = lun;
msc->bot.state = BOT_SEND_CBW_WAIT;
@ -84,9 +85,12 @@ usbh_status usbh_msc_bot_process(usbh_host *uhost, uint8_t lun)
case BOT_SEND_CBW_WAIT:
urb_status = usbh_urbstate_get(uhost->data, msc->pipe_out);
if(URB_DONE == urb_status) {
if(0U != msc->bot.cbw.field.dCBWDataTransferLength) {
if(USB_TRX_IN == (msc->bot.cbw.field.bmCBWFlags & USB_TRX_MASK)) {
if(URB_DONE == urb_status)
{
if(0U != msc->bot.cbw.field.dCBWDataTransferLength)
{
if(USB_TRX_IN == (msc->bot.cbw.field.bmCBWFlags & USB_TRX_MASK))
{
msc->bot.state = BOT_DATA_IN;
} else {
msc->bot.state = BOT_DATA_OUT;
@ -95,10 +99,12 @@ usbh_status usbh_msc_bot_process(usbh_host *uhost, uint8_t lun)
msc->bot.state = BOT_RECEIVE_CSW;
}
} else if(URB_NOTREADY == urb_status) {
} else if(URB_NOTREADY == urb_status)
{
msc->bot.state = BOT_SEND_CBW;
} else {
if(URB_STALL == urb_status) {
if(URB_STALL == urb_status)
{
msc->bot.state = BOT_ERROR_OUT;
}
}
@ -117,15 +123,18 @@ usbh_status usbh_msc_bot_process(usbh_host *uhost, uint8_t lun)
urb_status = usbh_urbstate_get(uhost->data, msc->pipe_in);
/* BOT DATA IN stage */
if(URB_DONE == urb_status) {
if(msc->bot.cbw.field.dCBWDataTransferLength > msc->ep_size_in) {
if(URB_DONE == urb_status)
{
if(msc->bot.cbw.field.dCBWDataTransferLength > msc->ep_size_in)
{
msc->bot.pbuf += msc->ep_size_in;
msc->bot.cbw.field.dCBWDataTransferLength -= msc->ep_size_in;
} else {
msc->bot.cbw.field.dCBWDataTransferLength = 0U;
}
if(msc->bot.cbw.field.dCBWDataTransferLength > 0U) {
if(msc->bot.cbw.field.dCBWDataTransferLength > 0U)
{
usbh_data_recev(uhost->data,
msc->bot.pbuf,
msc->pipe_in,
@ -133,7 +142,8 @@ usbh_status usbh_msc_bot_process(usbh_host *uhost, uint8_t lun)
} else {
msc->bot.state = BOT_RECEIVE_CSW;
}
} else if(URB_STALL == urb_status) {
} else if(URB_STALL == urb_status)
{
/* this is data stage stall condition */
msc->bot.state = BOT_ERROR_IN;
} else {
@ -153,15 +163,18 @@ usbh_status usbh_msc_bot_process(usbh_host *uhost, uint8_t lun)
case BOT_DATA_OUT_WAIT:
/* BOT DATA OUT stage */
urb_status = usbh_urbstate_get(uhost->data, msc->pipe_out);
if(URB_DONE == urb_status) {
if(msc->bot.cbw.field.dCBWDataTransferLength > msc->ep_size_out) {
if(URB_DONE == urb_status)
{
if(msc->bot.cbw.field.dCBWDataTransferLength > msc->ep_size_out)
{
msc->bot.pbuf += msc->ep_size_out;
msc->bot.cbw.field.dCBWDataTransferLength -= msc->ep_size_out;
} else {
msc->bot.cbw.field.dCBWDataTransferLength = 0; /* reset this value and keep in same state */
}
if(msc->bot.cbw.field.dCBWDataTransferLength > 0) {
if(msc->bot.cbw.field.dCBWDataTransferLength > 0)
{
usbh_data_send(uhost->data,
msc->bot.pbuf,
msc->pipe_out,
@ -169,9 +182,11 @@ usbh_status usbh_msc_bot_process(usbh_host *uhost, uint8_t lun)
} else {
msc->bot.state = BOT_RECEIVE_CSW;
}
} else if(URB_NOTREADY == urb_status) {
} else if(URB_NOTREADY == urb_status)
{
msc->bot.state = BOT_DATA_OUT;
} else if(URB_STALL == urb_status) {
} else if(URB_STALL == urb_status)
{
msc->bot.state = BOT_ERROR_OUT;
} else {
/* no operation */
@ -192,17 +207,20 @@ usbh_status usbh_msc_bot_process(usbh_host *uhost, uint8_t lun)
urb_status = usbh_urbstate_get(uhost->data, msc->pipe_in);
/* decode CSW */
if(URB_DONE == urb_status) {
if(URB_DONE == urb_status)
{
msc->bot.state = BOT_SEND_CBW;
msc->bot.cmd_state = BOT_CMD_SEND;
csw_status = usbh_msc_csw_decode(uhost);
if(BOT_CSW_CMD_PASSED == csw_status) {
if(BOT_CSW_CMD_PASSED == csw_status)
{
status = USBH_OK;
} else {
status = USBH_FAIL;
}
} else if(URB_STALL == urb_status) {
} else if(URB_STALL == urb_status)
{
msc->bot.state = BOT_ERROR_IN;
} else {
/* no operation */
@ -212,9 +230,11 @@ usbh_status usbh_msc_bot_process(usbh_host *uhost, uint8_t lun)
case BOT_ERROR_IN:
error = usbh_msc_bot_abort(uhost, USBH_MSC_DIR_IN);
if(USBH_OK == error) {
if(USBH_OK == error)
{
msc->bot.state = BOT_RECEIVE_CSW;
} else if(USBH_UNRECOVERED_ERROR == status) {
} else if(USBH_UNRECOVERED_ERROR == status)
{
/* this means that there is a stall error limit, do reset recovery */
msc->bot.state = BOT_UNRECOVERED_ERROR;
} else {
@ -225,13 +245,15 @@ usbh_status usbh_msc_bot_process(usbh_host *uhost, uint8_t lun)
case BOT_ERROR_OUT:
status = usbh_msc_bot_abort(uhost, USBH_MSC_DIR_OUT);
if(USBH_OK == status) {
if(USBH_OK == status)
{
uint8_t toggle = usbh_pipe_toggle_get(uhost->data, msc->pipe_out);
usbh_pipe_toggle_set(uhost->data, msc->pipe_out, 1U - toggle);
usbh_pipe_toggle_set(uhost->data, msc->pipe_in, 0U);
msc->bot.state = BOT_ERROR_IN;
} else {
if(USBH_UNRECOVERED_ERROR == status) {
if(USBH_UNRECOVERED_ERROR == status)
{
msc->bot.state = BOT_UNRECOVERED_ERROR;
}
}
@ -239,7 +261,8 @@ usbh_status usbh_msc_bot_process(usbh_host *uhost, uint8_t lun)
case BOT_UNRECOVERED_ERROR:
status = usbh_msc_bot_reset(uhost);
if(USBH_OK == status) {
if(USBH_OK == status)
{
msc->bot.state = BOT_SEND_CBW;
}
break;
@ -263,7 +286,8 @@ usbh_status usbh_msc_bot_abort(usbh_host *uhost, uint8_t direction)
usbh_status status = USBH_BUSY;
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
switch(direction) {
switch(direction)
{
case USBH_MSC_DIR_IN :
/* send clrfeture command on bulk IN endpoint */
status = usbh_clrfeature(uhost,
@ -295,8 +319,10 @@ usbh_status usbh_msc_bot_reset(usbh_host *uhost)
{
usbh_status status = USBH_BUSY;
if(CTL_IDLE == uhost->control.ctl_state) {
uhost->control.setup.req = (usb_req) {
if(CTL_IDLE == uhost->control.ctl_state)
{
uhost->control.setup.req = (usb_req)
{
.bmRequestType = USB_TRX_OUT | USB_REQTYPE_CLASS | USB_RECPTYPE_ITF,
.bRequest = BBB_RESET,
.wValue = 0U,
@ -324,21 +350,27 @@ bot_csw_status usbh_msc_csw_decode(usbh_host *uhost)
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
/* checking if the transfer length is different than 13 */
if(BBB_CSW_LENGTH != usbh_xfercount_get(uhost->data, msc->pipe_in)) {
if(BBB_CSW_LENGTH != usbh_xfercount_get(uhost->data, msc->pipe_in))
{
status = BOT_CSW_PHASE_ERROR;
} else {
/* CSW length is correct */
/* check validity of the CSW Signature and CSWStatus */
if(BBB_CSW_SIGNATURE == msc->bot.csw.field.dCSWSignature) {
if(BBB_CSW_SIGNATURE == msc->bot.csw.field.dCSWSignature)
{
/* check condition 1. dCSWSignature is equal to 53425355h */
if(msc->bot.csw.field.dCSWTag == msc->bot.cbw.field.dCBWTag) {
if(msc->bot.csw.field.dCSWTag == msc->bot.cbw.field.dCBWTag)
{
/* check condition 3. dCSWTag matches the dCBWTag from the corresponding CBW */
if(0U == msc->bot.csw.field.bCSWStatus) {
if(0U == msc->bot.csw.field.bCSWStatus)
{
status = BOT_CSW_CMD_PASSED;
} else if(1U == msc->bot.csw.field.bCSWStatus) {
} else if(1U == msc->bot.csw.field.bCSWStatus)
{
status = BOT_CSW_CMD_FAILED;
} else if(2U == msc->bot.csw.field.bCSWStatus) {
} else if(2U == msc->bot.csw.field.bCSWStatus)
{
status = BOT_CSW_PHASE_ERROR;
} else {
/* no operation */

147
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/class/msc/Source/usbh_msc_core.c
View File

@ -68,7 +68,8 @@ usbh_status usbh_msc_lun_info_get(usbh_host *uhost, uint8_t lun, msc_lun *info)
{
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
if(HOST_CLASS_HANDLER == uhost->cur_state) {
if(HOST_CLASS_HANDLER == uhost->cur_state)
{
memcpy(info, &msc->unit[lun], sizeof(msc_lun));
return USBH_OK;
@ -99,7 +100,8 @@ usbh_status usbh_msc_read(usbh_host *uhost,
if((0U == udev->host.connect_status) ||
(HOST_CLASS_HANDLER != uhost->cur_state) ||
(MSC_IDLE != msc->unit[lun].state)) {
(MSC_IDLE != msc->unit[lun].state))
{
return USBH_FAIL;
}
@ -111,8 +113,10 @@ usbh_status usbh_msc_read(usbh_host *uhost,
timeout = uhost->control.timer;
while(USBH_BUSY == usbh_msc_rdwr_process(uhost, lun)) {
if(((uhost->control.timer - timeout) > (1000U * length)) || (0U == udev->host.connect_status)) {
while(USBH_BUSY == usbh_msc_rdwr_process(uhost, lun))
{
if(((uhost->control.timer - timeout) > (1000U * length)) || (0U == udev->host.connect_status))
{
msc->state = MSC_IDLE;
return USBH_FAIL;
}
@ -145,7 +149,8 @@ usbh_status usbh_msc_write(usbh_host *uhost,
if((0U == udev->host.connect_status) ||
(HOST_CLASS_HANDLER != uhost->cur_state) ||
(MSC_IDLE != msc->unit[lun].state)) {
(MSC_IDLE != msc->unit[lun].state))
{
return USBH_FAIL;
}
@ -157,8 +162,10 @@ usbh_status usbh_msc_write(usbh_host *uhost,
timeout = uhost->control.timer;
while(USBH_BUSY == usbh_msc_rdwr_process(uhost, lun)) {
if(((uhost->control.timer - timeout) > (1000U * length)) || (0U == udev->host.connect_status)) {
while(USBH_BUSY == usbh_msc_rdwr_process(uhost, lun))
{
if(((uhost->control.timer - timeout) > (1000U * length)) || (0U == udev->host.connect_status))
{
msc->state = MSC_IDLE;
return USBH_FAIL;
}
@ -179,14 +186,16 @@ static void usbh_msc_itf_deinit(usbh_host *uhost)
{
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
if(msc->pipe_out) {
if(msc->pipe_out)
{
usb_pipe_halt(uhost->data, msc->pipe_out);
usbh_pipe_free(uhost->data, msc->pipe_out);
msc->pipe_out = 0U;
}
if(msc->pipe_in) {
if(msc->pipe_in)
{
usb_pipe_halt(uhost->data, msc->pipe_in);
usbh_pipe_free(uhost->data, msc->pipe_in);
@ -206,7 +215,8 @@ static usbh_status usbh_msc_itf_init(usbh_host *uhost)
uint8_t interface = usbh_interface_find(&uhost->dev_prop, MSC_CLASS, USB_MSC_SUBCLASS_SCSI, MSC_PROTOCOL);
if(0xFFU == interface) {
if(0xFFU == interface)
{
uhost->usr_cb->dev_not_supported();
status = USBH_FAIL;
@ -221,7 +231,8 @@ static usbh_status usbh_msc_itf_init(usbh_host *uhost)
usb_desc_ep *ep_desc = &uhost->dev_prop.cfg_desc_set.itf_desc_set[interface][0].ep_desc[0];
if(ep_desc->bEndpointAddress & 0x80) {
if(ep_desc->bEndpointAddress & 0x80)
{
msc_handler.ep_in = ep_desc->bEndpointAddress;
msc_handler.ep_size_in = ep_desc->wMaxPacketSize;
} else {
@ -231,7 +242,8 @@ static usbh_status usbh_msc_itf_init(usbh_host *uhost)
ep_desc = &uhost->dev_prop.cfg_desc_set.itf_desc_set[interface][0].ep_desc[1];
if(ep_desc->bEndpointAddress & 0x80) {
if(ep_desc->bEndpointAddress & 0x80)
{
msc_handler.ep_in = ep_desc->bEndpointAddress;
msc_handler.ep_size_in = ep_desc->wMaxPacketSize;
} else {
@ -278,21 +290,25 @@ static usbh_status usbh_msc_req(usbh_host *uhost)
usbh_status status = USBH_BUSY;
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
switch(msc->req_state) {
switch(msc->req_state)
{
case MSC_REQ_IDLE:
case MSC_REQ_GET_MAX_LUN:
/* issue Get_MaxLun request */
status = usbh_msc_maxlun_get(uhost, (uint8_t *)&msc->max_lun);
if(USBH_OK == status) {
if(USBH_OK == status)
{
msc->max_lun = ((uint8_t)msc->max_lun > MSC_MAX_SUPPORTED_LUN) ? MSC_MAX_SUPPORTED_LUN : (uint8_t)msc->max_lun + 1U;
for(uint8_t i = 0U; i < msc->max_lun; i++) {
for(uint8_t i = 0U; i < msc->max_lun; i++)
{
msc->unit[i].prev_ready_state = USBH_FAIL;
msc->unit[i].state_changed = 0U;
}
} else {
if(USBH_NOT_SUPPORTED == status) {
if(USBH_NOT_SUPPORTED == status)
{
msc->max_lun = 0U;
status = USBH_OK;
}
@ -301,7 +317,8 @@ static usbh_status usbh_msc_req(usbh_host *uhost)
case MSC_REQ_ERROR:
/* issue clear feature request */
if(USBH_OK == usbh_clrfeature(uhost, 0x00U, uhost->control.pipe_out_num)) {
if(USBH_OK == usbh_clrfeature(uhost, 0x00U, uhost->control.pipe_out_num))
{
msc->req_state = msc->prev_req_state;
}
break;
@ -327,12 +344,15 @@ static usbh_status usbh_msc_handle(usbh_host *uhost)
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
switch(msc->state) {
switch(msc->state)
{
case MSC_INIT:
if(msc->cur_lun < msc->max_lun) {
if(msc->cur_lun < msc->max_lun)
{
msc->unit[msc->cur_lun].error = MSC_NOT_READY;
switch(msc->unit[msc->cur_lun].state) {
switch(msc->unit[msc->cur_lun].state)
{
case MSC_INIT:
msc->unit[msc->cur_lun].state = MSC_READ_INQUIRY;
msc->timer = uhost->control.timer;
@ -341,12 +361,15 @@ static usbh_status usbh_msc_handle(usbh_host *uhost)
case MSC_READ_INQUIRY:
scsi_status = usbh_msc_scsi_inquiry(uhost, msc->cur_lun, &msc->unit[msc->cur_lun].inquiry);
if(USBH_OK == scsi_status) {
if(USBH_OK == scsi_status)
{
msc->unit[msc->cur_lun].state = MSC_TEST_UNIT_READY;
} else if(scsi_status == USBH_FAIL) {
} else if(scsi_status == USBH_FAIL)
{
msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE;
} else {
if(scsi_status == USBH_UNRECOVERED_ERROR) {
if(scsi_status == USBH_UNRECOVERED_ERROR)
{
msc->unit[msc->cur_lun].state = MSC_IDLE;
msc->unit[msc->cur_lun].error = MSC_ERROR;
}
@ -357,8 +380,10 @@ static usbh_status usbh_msc_handle(usbh_host *uhost)
/* issue SCSI command TestUnitReady */
ready_status = usbh_msc_test_unitready(uhost, msc->cur_lun);
if(USBH_OK == ready_status) {
if(USBH_OK != msc->unit[msc->cur_lun].prev_ready_state) {
if(USBH_OK == ready_status)
{
if(USBH_OK != msc->unit[msc->cur_lun].prev_ready_state)
{
msc->unit[msc->cur_lun].state_changed = 1U;
} else {
msc->unit[msc->cur_lun].state_changed = 0U;
@ -367,8 +392,10 @@ static usbh_status usbh_msc_handle(usbh_host *uhost)
msc->unit[msc->cur_lun].state = MSC_READ_CAPACITY10;
msc->unit[msc->cur_lun].error = MSC_OK;
msc->unit[msc->cur_lun].prev_ready_state = USBH_OK;
} else if(USBH_FAIL == ready_status) {
if(USBH_FAIL != msc->unit[msc->cur_lun].prev_ready_state) {
} else if(USBH_FAIL == ready_status)
{
if(USBH_FAIL != msc->unit[msc->cur_lun].prev_ready_state)
{
msc->unit[msc->cur_lun].state_changed = 1U;
} else {
msc->unit[msc->cur_lun].state_changed = 0U;
@ -378,7 +405,8 @@ static usbh_status usbh_msc_handle(usbh_host *uhost)
msc->unit[msc->cur_lun].error = MSC_NOT_READY;
msc->unit[msc->cur_lun].prev_ready_state = USBH_FAIL;
} else {
if(USBH_UNRECOVERED_ERROR == ready_status) {
if(USBH_UNRECOVERED_ERROR == ready_status)
{
msc->unit[msc->cur_lun].state = MSC_IDLE;
msc->unit[msc->cur_lun].error = MSC_ERROR;
}
@ -389,16 +417,20 @@ static usbh_status usbh_msc_handle(usbh_host *uhost)
/* issue READ_CAPACITY10 SCSI command */
scsi_status = usbh_msc_read_capacity10(uhost, msc->cur_lun, &msc->unit[msc->cur_lun].capacity);
if(USBH_OK == scsi_status) {
if(1U == msc->unit[msc->cur_lun].state_changed) {
if(USBH_OK == scsi_status)
{
if(1U == msc->unit[msc->cur_lun].state_changed)
{
}
msc->unit[msc->cur_lun].state = MSC_IDLE;
msc->unit[msc->cur_lun].error = MSC_OK;
msc->cur_lun ++;
} else if(USBH_FAIL == scsi_status) {
} else if(USBH_FAIL == scsi_status)
{
msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE;
} else {
if(USBH_UNRECOVERED_ERROR == scsi_status) {
if(USBH_UNRECOVERED_ERROR == scsi_status)
{
msc->unit[msc->cur_lun].state = MSC_IDLE;
msc->unit[msc->cur_lun].error = MSC_ERROR;
}
@ -408,9 +440,12 @@ static usbh_status usbh_msc_handle(usbh_host *uhost)
case MSC_REQUEST_SENSE:
/* issue RequestSense SCSI command for receive error code */
scsi_status = usbh_msc_request_sense(uhost, msc->cur_lun, &msc->unit[msc->cur_lun].sense);
if(USBH_OK == scsi_status) {
if((UNIT_ATTENTION == msc->unit[msc->cur_lun].sense.SenseKey) || (NOT_READY == msc->unit[msc->cur_lun].sense.SenseKey)) {
if((uhost->control.timer - msc->timer) < 10000U) {
if(USBH_OK == scsi_status)
{
if((UNIT_ATTENTION == msc->unit[msc->cur_lun].sense.SenseKey) || (NOT_READY == msc->unit[msc->cur_lun].sense.SenseKey))
{
if((uhost->control.timer - msc->timer) < 10000U)
{
msc->unit[msc->cur_lun].state = MSC_TEST_UNIT_READY;
break;
}
@ -418,10 +453,12 @@ static usbh_status usbh_msc_handle(usbh_host *uhost)
msc->unit[msc->cur_lun].state = MSC_IDLE;
msc->cur_lun++;
} else if(USBH_FAIL == scsi_status) {
} else if(USBH_FAIL == scsi_status)
{
msc->unit[msc->cur_lun].state = MSC_UNRECOVERED_ERROR;
} else {
if(MSC_UNRECOVERED_ERROR == scsi_status) {
if(MSC_UNRECOVERED_ERROR == scsi_status)
{
msc->unit[msc->cur_lun].state = MSC_IDLE;
msc->unit[msc->cur_lun].error = MSC_ERROR;
}
@ -464,8 +501,10 @@ static usbh_status usbh_msc_maxlun_get(usbh_host *uhost, uint8_t *maxlun)
{
usbh_status status = USBH_BUSY;
if(CTL_IDLE == uhost->control.ctl_state) {
uhost->control.setup.req = (usb_req) {
if(CTL_IDLE == uhost->control.ctl_state)
{
uhost->control.setup.req = (usb_req)
{
.bmRequestType = USB_TRX_IN | USB_REQTYPE_CLASS | USB_RECPTYPE_ITF,
.bRequest = BBB_GET_MAX_LUN,
.wValue = 0U,
@ -495,17 +534,21 @@ static usbh_status usbh_msc_rdwr_process(usbh_host *uhost, uint8_t lun)
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
/* switch MSC REQ state machine */
switch(msc->unit[lun].state) {
switch(msc->unit[lun].state)
{
case MSC_READ:
scsi_status = usbh_msc_read10(uhost, lun, NULL, 0U, 0U);
if(USBH_OK == scsi_status) {
if(USBH_OK == scsi_status)
{
msc->unit[lun].state = MSC_IDLE;
error = USBH_OK;
} else if(USBH_FAIL == scsi_status) {
} else if(USBH_FAIL == scsi_status)
{
msc->unit[lun].state = MSC_REQUEST_SENSE;
} else {
if(USBH_UNRECOVERED_ERROR == scsi_status) {
if(USBH_UNRECOVERED_ERROR == scsi_status)
{
msc->unit[lun].state = MSC_UNRECOVERED_ERROR;
error = USBH_FAIL;
}
@ -515,13 +558,16 @@ static usbh_status usbh_msc_rdwr_process(usbh_host *uhost, uint8_t lun)
case MSC_WRITE:
scsi_status = usbh_msc_write10(uhost, lun, NULL, 0U, 0U);
if(USBH_OK == scsi_status) {
if(USBH_OK == scsi_status)
{
msc->unit[lun].state = MSC_IDLE;
error = USBH_OK;
} else if(USBH_FAIL == scsi_status) {
} else if(USBH_FAIL == scsi_status)
{
msc->unit[lun].state = MSC_REQUEST_SENSE;
} else {
if(USBH_UNRECOVERED_ERROR == scsi_status) {
if(USBH_UNRECOVERED_ERROR == scsi_status)
{
msc->unit[lun].state = MSC_UNRECOVERED_ERROR;
error = USBH_FAIL;
}
@ -531,16 +577,19 @@ static usbh_status usbh_msc_rdwr_process(usbh_host *uhost, uint8_t lun)
case MSC_REQUEST_SENSE:
scsi_status = usbh_msc_request_sense(uhost, lun, &msc->unit[lun].sense);
if(USBH_OK == scsi_status) {
if(USBH_OK == scsi_status)
{
msc->unit[lun].state = MSC_IDLE;
msc->unit[lun].error = MSC_ERROR;
error = USBH_FAIL;
}
if(USBH_FAIL == scsi_status) {
if(USBH_FAIL == scsi_status)
{
} else {
if(USBH_UNRECOVERED_ERROR == scsi_status) {
if(USBH_UNRECOVERED_ERROR == scsi_status)
{
msc->unit[lun].state = MSC_UNRECOVERED_ERROR;
error = USBH_FAIL;
}

54
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/class/msc/Source/usbh_msc_fatfs.c
View File

@ -50,7 +50,8 @@ DSTATUS disk_initialize(BYTE drv)
{
usb_core_driver *udev = (usb_core_driver *)usb_host_msc.data;
if(udev->host.connect_status) {
if(udev->host.connect_status)
{
state &= ~STA_NOINIT;
}
@ -65,7 +66,8 @@ DSTATUS disk_initialize(BYTE drv)
*/
DSTATUS disk_status(BYTE drv)
{
if(drv) {
if(drv)
{
return STA_NOINIT; /* supports only single drive */
}
@ -86,25 +88,30 @@ DRESULT disk_read(BYTE drv, BYTE *buff, DWORD sector, UINT count)
BYTE status = USBH_OK;
usb_core_driver *udev = (usb_core_driver *)usb_host_msc.data;
if(drv || (!count)) {
if(drv || (!count))
{
return RES_PARERR;
}
if(state & STA_NOINIT) {
if(state & STA_NOINIT)
{
return RES_NOTRDY;
}
if(udev->host.connect_status) {
if(udev->host.connect_status)
{
do {
status = usbh_msc_read(&usb_host_msc, drv, sector, buff, count);
if(!udev->host.connect_status) {
if(!udev->host.connect_status)
{
return RES_ERROR;
}
} while(status == USBH_BUSY);
}
if(status == USBH_OK) {
if(status == USBH_OK)
{
return RES_OK;
}
@ -127,29 +134,35 @@ DRESULT disk_write(BYTE drv, const BYTE *buff, DWORD sector, UINT count)
BYTE status = USBH_OK;
usb_core_driver *udev = (usb_core_driver *)usb_host_msc.data;
if((!count) || drv) {
if((!count) || drv)
{
return RES_PARERR;
}
if(state & STA_NOINIT) {
if(state & STA_NOINIT)
{
return RES_NOTRDY;
}
if(state & STA_PROTECT) {
if(state & STA_PROTECT)
{
return RES_WRPRT;
}
if(udev->host.connect_status) {
if(udev->host.connect_status)
{
do {
status = usbh_msc_write(&usb_host_msc, drv, sector, (BYTE *)buff, count);
if(!udev->host.connect_status) {
if(!udev->host.connect_status)
{
return RES_ERROR;
}
} while(status == USBH_BUSY);
}
if(status == USBH_OK) {
if(status == USBH_OK)
{
return RES_OK;
}
@ -171,17 +184,20 @@ DRESULT disk_ioctl(BYTE drv, BYTE ctrl, void *buff)
DRESULT res = RES_OK;
msc_lun info;
if(drv) {
if(drv)
{
return RES_PARERR;
}
res = RES_ERROR;
if(state & STA_NOINIT) {
if(state & STA_NOINIT)
{
return RES_NOTRDY;
}
switch(ctrl) {
switch(ctrl)
{
/* make sure that no pending write process */
case CTRL_SYNC:
res = RES_OK;
@ -189,7 +205,8 @@ DRESULT disk_ioctl(BYTE drv, BYTE ctrl, void *buff)
/* get number of sectors on the disk (dword) */
case GET_SECTOR_COUNT:
if(USBH_OK == usbh_msc_lun_info_get(&usb_host_msc, drv, &info)) {
if(USBH_OK == usbh_msc_lun_info_get(&usb_host_msc, drv, &info))
{
*(DWORD *)buff = (DWORD)info.capacity.block_nbr;
res = RES_OK;
}
@ -197,7 +214,8 @@ DRESULT disk_ioctl(BYTE drv, BYTE ctrl, void *buff)
/* get r/w sector size (word) */
case GET_SECTOR_SIZE:
if(USBH_OK == usbh_msc_lun_info_get(&usb_host_msc, drv, &info)) {
if(USBH_OK == usbh_msc_lun_info_get(&usb_host_msc, drv, &info))
{
*(WORD *)buff = (DWORD)info.capacity.block_size;
res = RES_OK;
}

39
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/class/msc/Source/usbh_msc_scsi.c
View File

@ -50,7 +50,8 @@ usbh_status usbh_msc_scsi_inquiry(usbh_host *uhost, uint8_t lun, scsi_std_inquir
usbh_status error = USBH_FAIL;
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
switch(msc->bot.cmd_state) {
switch(msc->bot.cmd_state)
{
case BOT_CMD_SEND:
/* prepare the CBW and relevant field*/
msc->bot.cbw.field.dCBWDataTransferLength = STANDARD_INQUIRY_DATA_LEN;
@ -72,14 +73,16 @@ usbh_status usbh_msc_scsi_inquiry(usbh_host *uhost, uint8_t lun, scsi_std_inquir
case BOT_CMD_WAIT:
error = usbh_msc_bot_process(uhost, lun);
if(USBH_OK == error) {
if(USBH_OK == error)
{
memset(inquiry, 0U, sizeof(scsi_std_inquiry_data));
/* assign inquiry data */
inquiry->device_type = msc->bot.pbuf[0] & 0x1FU;
inquiry->peripheral_qualifier = msc->bot.pbuf[0] >> 5U;
if(0x80U == ((uint32_t)msc->bot.pbuf[1] & 0x80U)) {
if(0x80U == ((uint32_t)msc->bot.pbuf[1] & 0x80U))
{
inquiry->removable_media = 1U;
} else {
inquiry->removable_media = 0U;
@ -111,7 +114,8 @@ usbh_status usbh_msc_test_unitready(usbh_host *uhost, uint8_t lun)
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
switch(msc->bot.cmd_state) {
switch(msc->bot.cmd_state)
{
case BOT_CMD_SEND:
/* prepare the CBW and relevant field */
msc->bot.cbw.field.dCBWDataTransferLength = CBW_LENGTH_TEST_UNIT_READY;
@ -151,7 +155,8 @@ usbh_status usbh_msc_read_capacity10(usbh_host *uhost, uint8_t lun, scsi_capacit
usbh_status status = USBH_FAIL;
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
switch(msc->bot.cmd_state) {
switch(msc->bot.cmd_state)
{
case BOT_CMD_SEND:
/* prepare the CBW and relevant field */
msc->bot.cbw.field.dCBWDataTransferLength = READ_CAPACITY10_DATA_LEN;
@ -171,7 +176,8 @@ usbh_status usbh_msc_read_capacity10(usbh_host *uhost, uint8_t lun, scsi_capacit
case BOT_CMD_WAIT:
status = usbh_msc_bot_process(uhost, lun);
if(USBH_OK == status) {
if(USBH_OK == status)
{
capacity->block_nbr = msc->bot.pbuf[3] | \
((uint32_t)msc->bot.pbuf[2] << 8U) | \
((uint32_t)msc->bot.pbuf[1] << 16U) | \
@ -201,7 +207,8 @@ usbh_status usbh_msc_mode_sense6(usbh_host *uhost, uint8_t lun)
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
switch(msc->bot.cmd_state) {
switch(msc->bot.cmd_state)
{
case BOT_CMD_SEND:
/* prepare the CBW and relevant field */
msc->bot.cbw.field.dCBWDataTransferLength = XFER_LEN_MODE_SENSE6;
@ -223,8 +230,10 @@ usbh_status usbh_msc_mode_sense6(usbh_host *uhost, uint8_t lun)
case BOT_CMD_WAIT:
status = usbh_msc_bot_process(uhost, lun);
if(USBH_OK == status) {
if(msc->bot.data[2] & MASK_MODE_SENSE_WRITE_PROTECT) {
if(USBH_OK == status)
{
if(msc->bot.data[2] & MASK_MODE_SENSE_WRITE_PROTECT)
{
} else {
@ -253,7 +262,8 @@ usbh_status usbh_msc_request_sense(usbh_host *uhost, uint8_t lun, msc_scsi_sense
usbh_status status = USBH_FAIL;
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
switch(msc->bot.cmd_state) {
switch(msc->bot.cmd_state)
{
case BOT_CMD_SEND:
/* prepare the CBW and relevant field */
msc->bot.cbw.field.dCBWDataTransferLength = ALLOCATION_LENGTH_REQUEST_SENSE;
@ -276,7 +286,8 @@ usbh_status usbh_msc_request_sense(usbh_host *uhost, uint8_t lun, msc_scsi_sense
case BOT_CMD_WAIT:
status = usbh_msc_bot_process(uhost, lun);
if(USBH_OK == status) {
if(USBH_OK == status)
{
/* get sense data */
sense_data->SenseKey = msc->bot.pbuf[2] & 0x0FU;
sense_data->ASC = msc->bot.pbuf[12];
@ -306,7 +317,8 @@ usbh_status usbh_msc_write10(usbh_host *uhost, uint8_t lun, uint8_t *data_buf, u
usbh_status status = USBH_FAIL;
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
switch(msc->bot.cmd_state) {
switch(msc->bot.cmd_state)
{
case BOT_CMD_SEND:
msc->bot.cbw.field.dCBWDataTransferLength = sector_num * msc->unit[lun].capacity.block_size;
msc->bot.cbw.field.bmCBWFlags = USB_TRX_OUT;
@ -359,7 +371,8 @@ usbh_status usbh_msc_read10(usbh_host *uhost, uint8_t lun, uint8_t *data_buf, ui
usbh_status status = USBH_FAIL;
usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data;
switch(msc->bot.cmd_state) {
switch(msc->bot.cmd_state)
{
case BOT_CMD_SEND:
/* prepare the CBW and relevant field */
msc->bot.cbw.field.dCBWDataTransferLength = sector_num * msc->unit[lun].capacity.block_size;

4
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/core/Include/usbh_core.h
View File

@ -234,11 +234,11 @@ typedef struct _usbh_host
void *data; /*!< used for... */
//#if USB_LOW_POWER
/*#if USB_LOW_POWER*/
uint8_t suspend_flag; /*!< host suspend flag */
uint8_t dev_supp_remote_wkup; /*!< record device remote wakeup function */
uint8_t wakeup_mode; /*!< record wakeup mode */
//#endif /* USB_LOW_POWER*/
/*#endif /* USB_LOW_POWER*/
} usbh_host;
/*!

6
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/core/Include/usbh_pipe.h
View File

@ -53,7 +53,8 @@ OF SUCH DAMAGE.
*/
__STATIC_INLINE void usbh_pipe_toggle_set (usb_core_driver *udev, uint8_t pp_num, uint8_t toggle)
{
if (udev->host.pipe[pp_num].ep.dir) {
if (udev->host.pipe[pp_num].ep.dir)
{
udev->host.pipe[pp_num].data_toggle_in = toggle;
} else {
udev->host.pipe[pp_num].data_toggle_out = toggle;
@ -69,7 +70,8 @@ __STATIC_INLINE void usbh_pipe_toggle_set (usb_core_driver *udev, uint8_t pp_num
*/
__STATIC_INLINE uint8_t usbh_pipe_toggle_get (usb_core_driver *udev, uint8_t pp_num)
{
if (udev->host.pipe[pp_num].ep.dir) {
if (udev->host.pipe[pp_num].ep.dir)
{
return udev->host.pipe[pp_num].data_toggle_in;
} else {
return udev->host.pipe[pp_num].data_toggle_out;

135
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/core/Source/usbh_core.c
View File

@ -79,7 +79,8 @@ void usbh_init(usbh_host *uhost, usb_core_driver *udev, usbh_user_cb *user_cb)
udev->host.connect_status = 0U;
for(uint8_t i = 0U; i < USBHS_MAX_TX_FIFOS; i++) {
for(uint8_t i = 0U; i < USBHS_MAX_TX_FIFOS; i++)
{
udev->host.pipe[i].err_count = 0U;
udev->host.pipe[i].pp_status = PIPE_IDLE;
udev->host.backup_xfercount[i] = 0U;
@ -116,8 +117,10 @@ usbh_status usbh_class_register(usbh_host *uhost, usbh_class *puclass)
{
usbh_status status = USBH_OK;
if(NULL != puclass) {
if(uhost->class_num < USBH_MAX_SUPPORTED_CLASS) {
if(NULL != puclass)
{
if(uhost->class_num < USBH_MAX_SUPPORTED_CLASS)
{
uhost->uclass[uhost->class_num++] = puclass;
} else {
status = USBH_FAIL;
@ -169,15 +172,19 @@ void usbh_core_task(usbh_host *uhost)
usb_core_driver *udev = (usb_core_driver *)uhost->data;
/* check for host port events */
if(((0U == udev->host.connect_status) || (0U == udev->host.port_enabled)) && (HOST_DEFAULT != uhost->cur_state)) {
if(uhost->cur_state != HOST_DEV_DETACHED) {
if(((0U == udev->host.connect_status) || (0U == udev->host.port_enabled)) && (HOST_DEFAULT != uhost->cur_state))
{
if(uhost->cur_state != HOST_DEV_DETACHED)
{
uhost->cur_state = HOST_DEV_DETACHED;
}
}
switch(uhost->cur_state) {
switch(uhost->cur_state)
{
case HOST_DEFAULT:
if(udev->host.connect_status) {
if(udev->host.connect_status)
{
uhost->cur_state = HOST_DETECT_DEV_SPEED;
usb_mdelay(100U);
@ -189,7 +196,8 @@ void usbh_core_task(usbh_host *uhost)
break;
case HOST_DETECT_DEV_SPEED:
if(udev->host.port_enabled) {
if(udev->host.port_enabled)
{
uhost->cur_state = HOST_DEV_ATTACHED;
uhost->dev_prop.speed = usb_curspeed_get(udev);
@ -224,7 +232,8 @@ void usbh_core_task(usbh_host *uhost)
case HOST_ENUM:
/* check for enumeration status */
if(USBH_OK == usbh_enum_task(uhost)) {
if(USBH_OK == usbh_enum_task(uhost))
{
/* the function shall return USBH_OK when full enumeration is complete */
/* user callback for end of device basic enumeration */
@ -234,7 +243,8 @@ void usbh_core_task(usbh_host *uhost)
uhost->cur_state = HOST_SUSPENDED;
/* judge device remote wakup function */
if((uhost->dev_prop.cfg_desc_set.cfg_desc.bmAttributes) & (1U << 5)) {
if((uhost->dev_prop.cfg_desc_set.cfg_desc.bmAttributes) & (1U << 5))
{
uhost->dev_supp_remote_wkup = 1;
} else {
uhost->dev_supp_remote_wkup = 0;
@ -246,8 +256,10 @@ void usbh_core_task(usbh_host *uhost)
break;
case HOST_SET_WAKEUP_FEATURE:
if((uhost->dev_prop.cfg_desc_set.cfg_desc.bmAttributes) & (1U << 5)) {
if(usbh_setdevfeature(uhost, FEATURE_SELECTOR_REMOTEWAKEUP, 0U) == USBH_OK) {
if((uhost->dev_prop.cfg_desc_set.cfg_desc.bmAttributes) & (1U << 5))
{
if(usbh_setdevfeature(uhost, FEATURE_SELECTOR_REMOTEWAKEUP, 0U) == USBH_OK)
{
uhost->cur_state = HOST_CHECK_CLASS;
}
} else {
@ -256,20 +268,24 @@ void usbh_core_task(usbh_host *uhost)
break;
case HOST_CHECK_CLASS:
if(0U == uhost->class_num) {
if(0U == uhost->class_num)
{
uhost->cur_state = HOST_ERROR;
} else {
uhost->active_class = NULL;
uint8_t itf_class = uhost->dev_prop.cfg_desc_set.itf_desc_set[0][0].itf_desc.bInterfaceClass;
for(uint8_t index = 0U; index < uhost->class_num; index++) {
if((uhost->uclass[index]->class_code == itf_class) || (0xFFU == itf_class)) {
for(uint8_t index = 0U; index < uhost->class_num; index++)
{
if((uhost->uclass[index]->class_code == itf_class) || (0xFFU == itf_class))
{
uhost->active_class = uhost->uclass[index];
}
}
if(uhost->active_class != NULL) {
if(uhost->active_class != NULL)
{
uhost->cur_state = HOST_USER_INPUT;
} else {
uhost->cur_state = HOST_ERROR;
@ -279,8 +295,10 @@ void usbh_core_task(usbh_host *uhost)
case HOST_USER_INPUT:
/* the function should return user response true to move to class state */
if(USBH_USER_RESP_OK == uhost->usr_cb->dev_user_input()) {
if((USBH_OK == uhost->active_class->class_init(uhost))) {
if(USBH_USER_RESP_OK == uhost->usr_cb->dev_user_input())
{
if((USBH_OK == uhost->active_class->class_init(uhost)))
{
uhost->cur_state = HOST_CLASS_ENUM;
}
}
@ -288,9 +306,11 @@ void usbh_core_task(usbh_host *uhost)
#if USB_LOW_POWER
case HOST_SUSPENDED:
if(uhost->dev_supp_remote_wkup) {
if(uhost->dev_supp_remote_wkup)
{
/* send set feature command*/
if(USBH_OK == usbh_setdevfeature(uhost, FEATURE_SELECTOR_REMOTEWAKEUP, 0U)) {
if(USBH_OK == usbh_setdevfeature(uhost, FEATURE_SELECTOR_REMOTEWAKEUP, 0U))
{
usb_hwp_suspend(udev);
@ -318,12 +338,15 @@ void usbh_core_task(usbh_host *uhost)
case HOST_WAKEUP:
/* judge suspend status */
if(0 == uhost->suspend_flag) {
if(0 == uhost->suspend_flag)
{
usb_hwp_resume(udev);
usb_mdelay(500U);
if(uhost->dev_supp_remote_wkup) {
if(USBH_OK == usbh_clrdevfeature(uhost, FEATURE_SELECTOR_DEV, 0U)) {
if(uhost->dev_supp_remote_wkup)
{
if(USBH_OK == usbh_clrdevfeature(uhost, FEATURE_SELECTOR_DEV, 0U))
{
/* user callback for initialization */
uhost->usr_cb->dev_init();
uhost->cur_state = HOST_CHECK_CLASS;
@ -339,7 +362,8 @@ void usbh_core_task(usbh_host *uhost)
/* process class standard control requests state machine */
status = uhost->active_class->class_requests(uhost);
if(USBH_OK == status) {
if(USBH_OK == status)
{
uhost->cur_state = HOST_CLASS_HANDLER;
} else {
usbh_error_handler(uhost, status);
@ -387,11 +411,13 @@ void usbh_core_task(usbh_host *uhost)
void usbh_error_handler(usbh_host *uhost, usbh_status err_type)
{
/* error unrecovered or not supported device speed */
if((USBH_SPEED_UNKNOWN_ERROR == err_type) || (USBH_UNRECOVERED_ERROR == err_type)) {
if((USBH_SPEED_UNKNOWN_ERROR == err_type) || (USBH_UNRECOVERED_ERROR == err_type))
{
uhost->usr_cb->dev_error();
uhost->cur_state = HOST_ERROR;
} else if(USBH_APPLY_DEINIT == err_type) {
} else if(USBH_APPLY_DEINIT == err_type)
{
uhost->cur_state = HOST_ERROR;
/* user callback for initialization */
@ -414,8 +440,10 @@ static uint8_t usbh_sof(usbh_host *uhost)
/* update timer variable */
uhost->control.timer++;
if(NULL != uhost->active_class) {
if(NULL != uhost->active_class->class_sof) {
if(NULL != uhost->active_class)
{
if(NULL != uhost->active_class->class_sof)
{
uhost->active_class->class_sof(uhost);
}
}
@ -497,10 +525,12 @@ static usbh_status usbh_enum_task(usbh_host *uhost)
static uint8_t index_mfc_str = 0U, index_prod_str = 0U, index_serial_str = 0U;
switch(uhost->enum_state) {
switch(uhost->enum_state)
{
case ENUM_DEFAULT:
/* get device descriptor for only 1st 8 bytes : to get ep0 maxpacketsize */
if(USBH_OK == usbh_devdesc_get(uhost, 8U)) {
if(USBH_OK == usbh_devdesc_get(uhost, 8U))
{
uhost->control.max_len = uhost->dev_prop.dev_desc.bMaxPacketSize0;
/* modify control channels configuration for maximum packet size */
@ -520,7 +550,8 @@ static usbh_status usbh_enum_task(usbh_host *uhost)
case ENUM_GET_DEV_DESC:
/* get full device descriptor */
if(USBH_OK == usbh_devdesc_get(uhost, USB_DEV_DESC_LEN)) {
if(USBH_OK == usbh_devdesc_get(uhost, USB_DEV_DESC_LEN))
{
uhost->usr_cb->dev_devdesc_assigned(&uhost->dev_prop.dev_desc);
index_mfc_str = uhost->dev_prop.dev_desc.iManufacturer;
@ -533,7 +564,8 @@ static usbh_status usbh_enum_task(usbh_host *uhost)
case ENUM_SET_ADDR:
/* set address */
if(USBH_OK == usbh_setaddress(uhost, USBH_DEV_ADDR)) {
if(USBH_OK == usbh_setaddress(uhost, USBH_DEV_ADDR))
{
usb_mdelay(2U);
uhost->dev_prop.addr = USBH_DEV_ADDR;
@ -558,14 +590,16 @@ static usbh_status usbh_enum_task(usbh_host *uhost)
case ENUM_GET_CFG_DESC:
/* get standard configuration descriptor */
if(USBH_OK == usbh_cfgdesc_get(uhost, USB_CFG_DESC_LEN)) {
if(USBH_OK == usbh_cfgdesc_get(uhost, USB_CFG_DESC_LEN))
{
uhost->enum_state = ENUM_GET_CFG_DESC_SET;
}
break;
case ENUM_GET_CFG_DESC_SET:
/* get full configure descriptor (config, interface, endpoints) */
if(USBH_OK == usbh_cfgdesc_get(uhost, uhost->dev_prop.cfg_desc_set.cfg_desc.wTotalLength)) {
if(USBH_OK == usbh_cfgdesc_get(uhost, uhost->dev_prop.cfg_desc_set.cfg_desc.wTotalLength))
{
/* user callback for configuration descriptors available */
uhost->usr_cb->dev_cfgdesc_assigned(&uhost->dev_prop.cfg_desc_set.cfg_desc,
&uhost->dev_prop.cfg_desc_set.itf_desc_set[0][0].itf_desc,
@ -576,33 +610,39 @@ static usbh_status usbh_enum_task(usbh_host *uhost)
break;
case ENUM_GET_STR_DESC:
if(index_mfc_str) {
if(index_mfc_str)
{
if(USBH_OK == usbh_strdesc_get(uhost,
uhost->dev_prop.dev_desc.iManufacturer,
str_buf,
0xFFU)) {
0xFFU))
{
/* user callback for manufacturing string */
uhost->usr_cb->dev_mfc_str(str_buf);
index_mfc_str = 0U;
}
} else {
if(index_prod_str) {
if(index_prod_str)
{
/* check that product string is available */
if(USBH_OK == usbh_strdesc_get(uhost,
uhost->dev_prop.dev_desc.iProduct,
str_buf,
0xFFU)) {
0xFFU))
{
uhost->usr_cb->dev_prod_str(str_buf);
index_prod_str = 0U;
}
} else {
if(index_serial_str) {
if(index_serial_str)
{
if(USBH_OK == usbh_strdesc_get(uhost,
uhost->dev_prop.dev_desc.iSerialNumber,
str_buf,
0xFFU)) {
0xFFU))
{
uhost->usr_cb->dev_seral_str(str_buf);
#ifndef USB_MTP
uhost->enum_state = ENUM_SET_CONFIGURATION;
@ -625,12 +665,16 @@ static usbh_status usbh_enum_task(usbh_host *uhost)
#ifdef USB_MTP
case ENUM_GET_MTP_STR:
if(interface < uhost->dev_prop.cfg_desc_set.cfg_desc.bNumInterfaces) {
if(interface < uhost->dev_prop.cfg_desc_set.cfg_desc.bNumInterfaces)
{
index_itf_str = uhost->dev_prop.cfg_desc_set.itf_desc_set[interface][0].itf_desc.iInterface;
if(index_itf_str != 0U) {
if(USBH_OK == usbh_strdesc_get(uhost, index_itf_str, str_buf, 0xFFU)) {
if(0U == strcmp((const char *)str_buf, "MTP")) {
if(index_itf_str != 0U)
{
if(USBH_OK == usbh_strdesc_get(uhost, index_itf_str, str_buf, 0xFFU))
{
if(0U == strcmp((const char *)str_buf, "MTP"))
{
uhost->dev_prop.cur_itf = interface;
uhost->enum_state = ENUM_SET_CONFIGURATION;
@ -650,7 +694,8 @@ static usbh_status usbh_enum_task(usbh_host *uhost)
#endif
case ENUM_SET_CONFIGURATION:
if(USBH_OK == usbh_setcfg(uhost, (uint16_t)uhost->dev_prop.cfg_desc_set.cfg_desc.bConfigurationValue)) {
if(USBH_OK == usbh_setcfg(uhost, (uint16_t)uhost->dev_prop.cfg_desc_set.cfg_desc.bConfigurationValue))
{
uhost->enum_state = ENUM_DEV_CONFIGURED;
}
break;

132
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/core/Source/usbh_enum.c
View File

@ -74,8 +74,10 @@ usbh_status usbh_devdesc_get(usbh_host *uhost, uint8_t len)
usbh_control *usb_ctl = &uhost->control;
if(CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
if(CTL_IDLE == usb_ctl->ctl_state)
{
usb_ctl->setup.req = (usb_req)
{
.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD,
.bRequest = USB_GET_DESCRIPTOR,
.wValue = USBH_DESC(USB_DESCTYPE_DEV),
@ -88,7 +90,8 @@ usbh_status usbh_devdesc_get(usbh_host *uhost, uint8_t len)
status = usbh_ctl_handler(uhost);
if(USBH_OK == status) {
if(USBH_OK == status)
{
/* commands successfully sent and response received */
usbh_devdesc_parse(&uhost->dev_prop.dev_desc, uhost->dev_prop.data, (uint16_t)len);
}
@ -117,8 +120,10 @@ usbh_status usbh_cfgdesc_get(usbh_host *uhost, uint16_t len)
pdata = uhost->dev_prop.data;
#endif
if(CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
if(CTL_IDLE == usb_ctl->ctl_state)
{
usb_ctl->setup.req = (usb_req)
{
.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD,
.bRequest = USB_GET_DESCRIPTOR,
.wValue = USBH_DESC(USB_DESCTYPE_CONFIG),
@ -131,8 +136,10 @@ usbh_status usbh_cfgdesc_get(usbh_host *uhost, uint16_t len)
status = usbh_ctl_handler(uhost);
if(USBH_OK == status) {
if(len <= USB_CFG_DESC_LEN) {
if(USBH_OK == status)
{
if(len <= USB_CFG_DESC_LEN)
{
usbh_cfgdesc_parse(&uhost->dev_prop.cfg_desc_set.cfg_desc, pdata);
} else {
usbh_cfgset_parse(&uhost->dev_prop, pdata);
@ -160,8 +167,10 @@ usbh_status usbh_strdesc_get(usbh_host *uhost,
usbh_control *usb_ctl = &uhost->control;
if(CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
if(CTL_IDLE == usb_ctl->ctl_state)
{
usb_ctl->setup.req = (usb_req)
{
.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD,
.bRequest = USB_GET_DESCRIPTOR,
.wValue = USBH_DESC(USB_DESCTYPE_STR) | str_index,
@ -174,7 +183,8 @@ usbh_status usbh_strdesc_get(usbh_host *uhost,
status = usbh_ctl_handler(uhost);
if(USBH_OK == status) {
if(USBH_OK == status)
{
/* commands successfully sent and response received */
usbh_strdesc_parse(uhost->dev_prop.data, buf, len);
}
@ -195,8 +205,10 @@ usbh_status usbh_setaddress(usbh_host *uhost, uint8_t dev_addr)
usbh_control *usb_ctl = &uhost->control;
if(CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
if(CTL_IDLE == usb_ctl->ctl_state)
{
usb_ctl->setup.req = (usb_req)
{
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD,
.bRequest = USB_SET_ADDRESS,
.wValue = (uint16_t)dev_addr,
@ -225,8 +237,10 @@ usbh_status usbh_setcfg(usbh_host *uhost, uint16_t config_index)
usbh_control *usb_ctl = &uhost->control;
if(CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
if(CTL_IDLE == usb_ctl->ctl_state)
{
usb_ctl->setup.req = (usb_req)
{
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD,
.bRequest = USB_SET_CONFIGURATION,
.wValue = config_index,
@ -256,8 +270,10 @@ usbh_status usbh_setinterface(usbh_host *uhost, uint8_t itf_num, uint8_t set)
usbh_control *usb_ctl = &uhost->control;
if(CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
if(CTL_IDLE == usb_ctl->ctl_state)
{
usb_ctl->setup.req = (usb_req)
{
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_STRD,
.bRequest = USB_SET_INTERFACE,
.wValue = set,
@ -287,8 +303,10 @@ usbh_status usbh_setdevfeature(usbh_host *uhost, uint8_t feature_selector, uint1
usbh_control *usb_ctl = &uhost->control;
if(CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
if(CTL_IDLE == usb_ctl->ctl_state)
{
usb_ctl->setup.req = (usb_req)
{
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD,
.bRequest = USB_SET_FEATURE,
.wValue = feature_selector,
@ -318,8 +336,10 @@ usbh_status usbh_clrdevfeature(usbh_host *uhost, uint8_t feature_selector, uint1
usbh_control *usb_ctl = &uhost->control;
if(CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
if(CTL_IDLE == usb_ctl->ctl_state)
{
usb_ctl->setup.req = (usb_req)
{
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD,
.bRequest = USB_CLEAR_FEATURE,
.wValue = feature_selector,
@ -349,8 +369,10 @@ usbh_status usbh_clrfeature(usbh_host *uhost, uint8_t ep_addr, uint8_t pp_num)
usbh_control *usb_ctl = &uhost->control;
usb_core_driver *udev = (usb_core_driver *)uhost->data;
if(CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
if(CTL_IDLE == usb_ctl->ctl_state)
{
usb_ctl->setup.req = (usb_req)
{
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_EP | USB_REQTYPE_STRD,
.bRequest = USB_CLEAR_FEATURE,
.wValue = FEATURE_SELECTOR_EP,
@ -358,7 +380,8 @@ usbh_status usbh_clrfeature(usbh_host *uhost, uint8_t ep_addr, uint8_t pp_num)
.wLength = 0U
};
if(EP_ID(ep_addr) == udev->host.pipe[pp_num].ep.num) {
if(EP_ID(ep_addr) == udev->host.pipe[pp_num].ep.num)
{
usbh_pipe_toggle_set(udev, pp_num, 0U);
} else {
return USBH_FAIL;
@ -401,7 +424,8 @@ usbh_status usbh_interface_select(usb_dev_prop *udev, uint8_t interface)
{
usbh_status status = USBH_OK;
if(interface < udev->cfg_desc_set.cfg_desc.bNumInterfaces) {
if(interface < udev->cfg_desc_set.cfg_desc.bNumInterfaces)
{
udev->cur_itf = interface;
} else {
status = USBH_FAIL;
@ -427,12 +451,14 @@ uint8_t usbh_interface_find(usb_dev_prop *udev, uint8_t main_class, uint8_t sub_
pif = (usb_desc_itf *)0;
while(if_ix < udev->cfg_desc_set.cfg_desc.bNumInterfaces) {
while(if_ix < udev->cfg_desc_set.cfg_desc.bNumInterfaces)
{
pif = &udev->cfg_desc_set.itf_desc_set[if_ix][0].itf_desc;
if(((pif->bInterfaceClass == main_class) || (0xFFU == main_class)) &&
((pif->bInterfaceSubClass == sub_class) || (0xFFU == sub_class)) &&
((pif->bInterfaceProtocol == protocol) || (0xFFU == protocol))) {
((pif->bInterfaceProtocol == protocol) || (0xFFU == protocol)))
{
return if_ix;
}
@ -458,10 +484,12 @@ uint8_t usbh_interfaceindex_find(usb_dev_prop *udev, uint8_t interface_number, u
pif = (usb_desc_itf *)0;
while(if_ix < USBH_MAX_INTERFACES_NUM) {
while(if_ix < USBH_MAX_INTERFACES_NUM)
{
pif = &udev->cfg_desc_set.itf_desc_set[if_ix][alt_settings].itf_desc;
if((pif->bInterfaceNumber == interface_number) && (pif->bAlternateSetting == alt_settings)) {
if((pif->bInterfaceNumber == interface_number) && (pif->bAlternateSetting == alt_settings))
{
return if_ix;
}
@ -481,7 +509,8 @@ uint8_t usbh_interfaceindex_find(usb_dev_prop *udev, uint8_t interface_number, u
*/
static void usbh_devdesc_parse(usb_desc_dev *dev_desc, uint8_t *buf, uint16_t len)
{
*dev_desc = (usb_desc_dev) {
*dev_desc = (usb_desc_dev)
{
.header = {
.bLength = *(uint8_t *)(buf + 0U),
.bDescriptorType = *(uint8_t *)(buf + 1U)
@ -494,7 +523,8 @@ static void usbh_devdesc_parse(usb_desc_dev *dev_desc, uint8_t *buf, uint16_t le
.bMaxPacketSize0 = *(uint8_t *)(buf + 7U)
};
if(len > 8U) {
if(len > 8U)
{
/* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */
dev_desc->idVendor = BYTE_SWAP(buf + 8U);
dev_desc->idProduct = BYTE_SWAP(buf + 10U);
@ -516,7 +546,8 @@ static void usbh_devdesc_parse(usb_desc_dev *dev_desc, uint8_t *buf, uint16_t le
static void usbh_cfgdesc_parse(usb_desc_config *cfg_desc, uint8_t *buf)
{
/* parse configuration descriptor */
*cfg_desc = (usb_desc_config) {
*cfg_desc = (usb_desc_config)
{
.header = {
.bLength = *(uint8_t *)(buf + 0U),
.bDescriptorType = *(uint8_t *)(buf + 1U),
@ -556,17 +587,21 @@ static void usbh_cfgset_parse(usb_dev_prop *udev, uint8_t *buf)
cfg = &udev->cfg_desc_set.cfg_desc;
ptr = USB_CFG_DESC_LEN;
if(cfg->bNumInterfaces > USBH_MAX_INTERFACES_NUM) {
if(cfg->bNumInterfaces > USBH_MAX_INTERFACES_NUM)
{
return;
}
while(ptr < cfg->wTotalLength) {
while(ptr < cfg->wTotalLength)
{
pdesc = usbh_nextdesc_get((uint8_t *)pdesc, &ptr);
if(pdesc->bDescriptorType == USB_DESCTYPE_ITF) {
if(pdesc->bDescriptorType == USB_DESCTYPE_ITF)
{
itf_index = *(((uint8_t *)pdesc) + 2U);
if(pre_itf_index != itf_index) {
if(pre_itf_index != itf_index)
{
alt_setting = 0U;
}
@ -574,11 +609,13 @@ static void usbh_cfgset_parse(usb_dev_prop *udev, uint8_t *buf)
alt_setting++;
if((*((uint8_t *)pdesc + 3U)) < 3U) {
if((*((uint8_t *)pdesc + 3U)) < 3U)
{
usbh_itfdesc_parse(&itf_value, (uint8_t *)pdesc);
/* parse endpoint descriptors relative to the current interface */
if(itf_value.bNumEndpoints > USBH_MAX_EP_NUM) {
if(itf_value.bNumEndpoints > USBH_MAX_EP_NUM)
{
return;
}
@ -587,14 +624,17 @@ static void usbh_cfgset_parse(usb_dev_prop *udev, uint8_t *buf)
/* store the previous interface index */
pre_itf_index = itf_index;
if(0U == itf_value.bNumEndpoints) {
if(0U == itf_value.bNumEndpoints)
{
continue;
}
for(ep_index = 0U; ep_index < itf_value.bNumEndpoints;) {
for(ep_index = 0U; ep_index < itf_value.bNumEndpoints;)
{
pdesc = usbh_nextdesc_get((void *)pdesc, &ptr);
if(pdesc->bDescriptorType == USB_DESCTYPE_EP) {
if(pdesc->bDescriptorType == USB_DESCTYPE_EP)
{
ep = &itf->ep_desc[ep_index];
usbh_epdesc_parse(ep, (uint8_t *)pdesc);
@ -616,7 +656,8 @@ static void usbh_cfgset_parse(usb_dev_prop *udev, uint8_t *buf)
*/
static void usbh_itfdesc_parse(usb_desc_itf *itf_desc, uint8_t *buf)
{
*itf_desc = (usb_desc_itf) {
*itf_desc = (usb_desc_itf)
{
.header = {
.bLength = *(uint8_t *)(buf + 0U),
.bDescriptorType = *(uint8_t *)(buf + 1U),
@ -641,7 +682,8 @@ static void usbh_itfdesc_parse(usb_desc_itf *itf_desc, uint8_t *buf)
*/
static void usbh_epdesc_parse(usb_desc_ep *ep_desc, uint8_t *buf)
{
*ep_desc = (usb_desc_ep) {
*ep_desc = (usb_desc_ep)
{
.header = {
.bLength = *(uint8_t *)(buf + 0U),
.bDescriptorType = *(uint8_t *)(buf + 1U)
@ -671,7 +713,8 @@ static void usbh_strdesc_parse(uint8_t *psrc, uint8_t *pdest, uint16_t len)
*/
/* check which is lower size, the size of string or the length of bytes read from the device */
if(USB_DESCTYPE_STR == psrc[1]) {
if(USB_DESCTYPE_STR == psrc[1])
{
/* make sure the descriptor is string type */
/* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */
@ -679,7 +722,8 @@ static void usbh_strdesc_parse(uint8_t *psrc, uint8_t *pdest, uint16_t len)
psrc += 2U; /* adjust the offset ignoring the string len and descriptor type */
for(index = 0U; index < str_len; index += 2U) {
for(index = 0U; index < str_len; index += 2U)
{
/* copy only the string and ignore the unicode id, hence add the src */
*pdest = psrc[index];

33
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_usbhs_library/host/core/Source/usbh_pipe.c
View File

@ -60,7 +60,8 @@ uint8_t usbh_pipe_create(usb_core_driver *udev,
pp->ep.type = ep_type;
pp->ep.mps = ep_mpl;
if (((USB_EPTYPE_BULK == pp->ep.type) || (USB_EPTYPE_CTRL == pp->ep.type))) {
if (((USB_EPTYPE_BULK == pp->ep.type) || (USB_EPTYPE_CTRL == pp->ep.type)))
{
pp->supp_ping = (uint8_t)(pp->dev_speed == PORT_SPEED_HIGH);
}
@ -87,19 +88,23 @@ uint8_t usbh_pipe_update(usb_core_driver *udev,
{
usb_pipe *pp = &udev->host.pipe[pp_num];
if((pp->dev_addr != dev_addr) && (dev_addr)) {
if((pp->dev_addr != dev_addr) && (dev_addr))
{
pp->dev_addr = dev_addr;
}
if((pp->dev_speed != dev_speed) && (dev_speed)) {
if((pp->dev_speed != dev_speed) && (dev_speed))
{
pp->dev_speed = dev_speed;
if (((USB_EPTYPE_BULK == pp->ep.type) || (USB_EPTYPE_CTRL == pp->ep.type))) {
if (((USB_EPTYPE_BULK == pp->ep.type) || (USB_EPTYPE_CTRL == pp->ep.type)))
{
pp->supp_ping = (uint8_t)(pp->dev_speed == PORT_SPEED_HIGH);
}
}
if((pp->ep.mps != ep_mpl) && (ep_mpl)) {
if((pp->ep.mps != ep_mpl) && (ep_mpl))
{
pp->ep.mps = ep_mpl;
}
@ -119,7 +124,8 @@ uint8_t usbh_pipe_allocate(usb_core_driver *udev, uint8_t ep_addr)
{
uint16_t pp_num = usbh_freepipe_get(udev);
if(HC_ERROR != pp_num) {
if(HC_ERROR != pp_num)
{
udev->host.pipe[pp_num].in_used = 1U;
udev->host.pipe[pp_num].ep.dir = EP_DIR(ep_addr);
udev->host.pipe[pp_num].ep.num = EP_ID(ep_addr);
@ -137,7 +143,8 @@ uint8_t usbh_pipe_allocate(usb_core_driver *udev, uint8_t ep_addr)
*/
uint8_t usbh_pipe_free(usb_core_driver *udev, uint8_t pp_num)
{
if(pp_num < HC_MAX) {
if(pp_num < HC_MAX)
{
udev->host.pipe[pp_num].in_used = 0U;
}
@ -154,8 +161,10 @@ uint8_t usbh_pipe_delete(usb_core_driver *udev)
{
uint8_t pp_num = 0U;
for(pp_num = 2U; pp_num < HC_MAX; pp_num++) {
udev->host.pipe[pp_num] = (usb_pipe) {
for(pp_num = 2U; pp_num < HC_MAX; pp_num++)
{
udev->host.pipe[pp_num] = (usb_pipe)
{
0
};
}
@ -173,8 +182,10 @@ static uint16_t usbh_freepipe_get(usb_core_driver *udev)
{
uint8_t pp_num = 0U;
for(pp_num = 0U; pp_num < HC_MAX; pp_num++) {
if(0U == udev->host.pipe[pp_num].in_used) {
for(pp_num = 0U; pp_num < HC_MAX; pp_num++)
{
if(0U == udev->host.pipe[pp_num].in_used)
{
return (uint16_t)pp_num;
}
}

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