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[IFX]Add psoc6 bsp

This commit is contained in:
Rbb666 2023-02-03 11:50:39 +08:00 committed by guo
parent 9fbf63441e
commit db5ed9c576
651 changed files with 85234 additions and 2567 deletions
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5
.github/workflows/action.yml vendored
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@ -52,6 +52,11 @@ jobs:
- {RTT_BSP: "at91/at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "Infineon/psoc6-cy8ckit-062S2-43012", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "Infineon/psoc6-cy8ckit-062-BLE", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "Infineon/psoc6-cy8ckit-062s4", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "Infineon/psoc6-cy8ckit-062-WIFI-BT", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "Infineon/psoc6-cy8cproto-062S3-4343W", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "Infineon/psoc6-evaluationkit-062S2", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "ft32/ft32f072xb-starter", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "n32/n32g43xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "n32/n32g45xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm"}

3
bsp/Infineon/README.md
View File

@ -8,6 +8,9 @@ PSOC6 系列 BSP 目前支持情况如下表所示：
| [psoc6-cy8ckit-062S2-43012](psoc6-cy8ckit-062S2-43012) | Infineon 官方 CY8CKIT-062-BLE PSoC 6 BLE Pioneer Kit 开发板 |
| [psoc6-cy8cproto-062S3-4343W](psoc6-cy8cproto-062S3-4343W) | Infineon 官方 PSoC™ 62S3 Wi-Fi BT Prototyping Kit 开发板 |
| [psoc6-evaluationkit-062S2](psoc6-evaluationkit-062S2) | RT-Thread 联合 Infineon 推出的评估开发板 |
| [psoc6-cy8ckit-062-BLE](psoc6-cy8ckit-062-BLE) | Infineon 官方 psoc6-cy8ckit-062-BLE 开发板 |
| [psoc6-cy8ckit-062-WIFI-BT](psoc6-cy8ckit-062-WIFI-BT) | Infineon 官方 psoc6-cy8ckit-062-WIFI-BT 开发板 |
| [psoc6-cy8ckit-062s4](psoc6-cy8ckit-062s4) | Infineon 官方 psoc6-cy8ckit-062s4 开发板 |
可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：

6
bsp/Infineon/libraries/HAL_Drivers/drv_gpio.c
View File

@ -22,12 +22,12 @@
static const struct pin_irq_map pin_irq_map[] =
{
{CYHAL_PORT_0, ioss_interrupts_gpio_0_IRQn},
#ifndef SOC_CY8C6245LQI_S3D72
#if !defined(SOC_CY8C6245LQI_S3D72) && !defined(SOC_CY8C6244LQI_S4D92)
{CYHAL_PORT_1, ioss_interrupts_gpio_1_IRQn},
#endif
{CYHAL_PORT_2, ioss_interrupts_gpio_2_IRQn},
{CYHAL_PORT_3, ioss_interrupts_gpio_3_IRQn},
#ifndef SOC_CY8C6245LQI_S3D72
#if !defined(SOC_CY8C6245LQI_S3D72) && !defined(SOC_CY8C6244LQI_S4D92)
{CYHAL_PORT_4, ioss_interrupts_gpio_4_IRQn},
#endif
{CYHAL_PORT_5, ioss_interrupts_gpio_5_IRQn},
@ -38,7 +38,7 @@ static const struct pin_irq_map pin_irq_map[] =
{CYHAL_PORT_10, ioss_interrupts_gpio_10_IRQn},
{CYHAL_PORT_11, ioss_interrupts_gpio_11_IRQn},
{CYHAL_PORT_12, ioss_interrupts_gpio_12_IRQn},
#ifndef SOC_CY8C6245LQI_S3D72
#if !defined(SOC_CY8C6245LQI_S3D72) && !defined(SOC_CY8C6244LQI_S4D92)
{CYHAL_PORT_13, ioss_interrupts_gpio_13_IRQn},
#endif
{CYHAL_PORT_14, ioss_interrupts_gpio_14_IRQn},

25
bsp/Infineon/libraries/HAL_Drivers/uart_config.h
View File

@ -20,12 +20,12 @@ extern "C"
#endif
#ifdef BSP_USING_UART0
/* UART0 device driver structure */
cy_stc_sysint_t UART0_SCB_IRQ_cfg =
{
.intrSrc = (IRQn_Type) scb_0_interrupt_IRQn,
.intrPriority = (7u),
};
/* UART0 device driver structure */
cy_stc_sysint_t UART0_SCB_IRQ_cfg =
{
.intrSrc = (IRQn_Type)scb_0_interrupt_IRQn,
.intrPriority = (7u),
};
#endif
#ifdef BSP_USING_UART1
/* UART1 device driver structure */
@ -102,6 +102,18 @@ cy_stc_sysint_t UART0_SCB_IRQ_cfg =
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#if defined(SOC_CY8C6244LQI_S4D92)
#define UART2_CONFIG \
{ \
.name = "uart2", \
.tx_pin = P3_1, \
.rx_pin = P3_0, \
.usart_x = SCB2, \
.intrSrc = scb_2_interrupt_IRQn, \
.userIsr = uart_isr_callback(uart2), \
.UART_SCB_IRQ_cfg = &UART2_SCB_IRQ_cfg, \
}
#else
#define UART2_CONFIG \
{ \
.name = "uart2", \
@ -112,6 +124,7 @@ cy_stc_sysint_t UART0_SCB_IRQ_cfg =
.userIsr = uart_isr_callback(uart2), \
.UART_SCB_IRQ_cfg = &UART2_SCB_IRQ_cfg, \
}
#endif /* SOC_CY8C6244LQI_S4D92 */
void uart2_isr_callback(void);
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */

41
bsp/Infineon/libraries/IFX_PSOC6_HAL/SConscript
View File

@ -54,6 +54,29 @@ if GetDepend(['SOC_CY8C624ALQI_S2D42']):
src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_68_qfn.c']
src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
if GetDepend(['SOC_CY8C6247BZI_D54']):
src += ['mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c']
src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_01.c']
src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_124_bga.c']
src += ['mtb-pdl-cat1/drivers/source/cy_flash.c']
src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
if GetDepend(['SOC_CY8C6347BZI_BLD53']):
src += ['mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c']
src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_01.c']
src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_116_bga_ble.c']
src += ['mtb-pdl-cat1/drivers/source/cy_flash.c']
src += ['mtb-pdl-cat1/drivers/source/cy_ble_clk.c']
src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
if GetDepend(['SOC_CY8C6244LQI_S4D92']):
src += ['mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c']
src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_04.c']
src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_04_68_qfn.c']
src += ['mtb-pdl-cat1/drivers/source/cy_flash.c']
src += ['mtb-pdl-cat1/drivers/source/cy_ble_clk.c']
src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
if GetDepend(['RT_USING_SERIAL']):
src += ['retarget-io/cy_retarget_io.c']
src += ['mtb-hal-cat1/source/cyhal_uart.c']
@ -149,6 +172,24 @@ if GetDepend(['SOC_CY8C624ALQI_S2D42']):
path += [cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include']
path += [cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include']
if GetDepend(['SOC_CY8C6247BZI_D54']):
path += [cwd + '/psoc6cm0p']
path += [cwd + '/capsense']
path += [cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include']
path += [cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include']
if GetDepend(['SOC_CY8C6347BZI_BLD53']):
path += [cwd + '/psoc6cm0p']
path += [cwd + '/capsense']
path += [cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include']
path += [cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include']
if GetDepend(['SOC_CY8C6244LQI_S4D92']):
path += [cwd + '/psoc6cm0p']
path += [cwd + '/capsense']
path += [cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include']
path += [cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include']
group = DefineGroup('Libraries', src, depend=[''], CPPPATH=path)
Return('group')

181
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
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@ -1,181 +0,0 @@
/*******************************************************************************
* File Name: cycfg_dmas.c
*
* Description:
* DMA configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5972
* mtb-pdl-cat1 2.4.0.14850
* personalities 6.0.0.0
* udd 3.0.0.2024
*
********************************************************************************
* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_dmas.h"
const cy_stc_dma_descriptor_config_t TxDma_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_4CYC,
.interruptType = CY_DMA_DESCR,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_ENABLED,
.triggerInType = CY_DMA_1ELEMENT,
.dataSize = CY_DMA_BYTE,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_WORD,
.descriptorType = CY_DMA_SINGLE_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 1,
.dstXincrement = 0,
.xCount = 1,
.srcYincrement = 1,
.dstYincrement = 1,
.yCount = 1,
.nextDescriptor = NULL,
};
cy_stc_dma_descriptor_t TxDma_Descriptor_0 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
const cy_stc_dma_channel_config_t TxDma_channelConfig =
{
.descriptor = &TxDma_Descriptor_0,
.preemptable = false,
.priority = 3,
.enable = false,
.bufferable = false,
};
const cy_stc_dma_crc_config_t TxDma_crcConfig =
{
.dataReverse = false,
.dataXor = 0,
.reminderReverse = false,
.reminderXor = 0,
.polynomial = 79764919,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t TxDma_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 0U,
.channel_num = TxDma_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t RxDma_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_4CYC,
.interruptType = CY_DMA_1ELEMENT,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_ENABLED,
.triggerInType = CY_DMA_1ELEMENT,
.dataSize = CY_DMA_BYTE,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_WORD,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMA_SINGLE_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 0,
.dstXincrement = 1,
.xCount = 1,
.srcYincrement = 1,
.dstYincrement = 1,
.yCount = 1,
.nextDescriptor = &RxDma_Descriptor_1,
};
const cy_stc_dma_descriptor_config_t RxDma_Descriptor_1_config =
{
.retrigger = CY_DMA_RETRIG_4CYC,
.interruptType = CY_DMA_DESCR,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_ENABLED,
.triggerInType = CY_DMA_1ELEMENT,
.dataSize = CY_DMA_BYTE,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_WORD,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMA_SINGLE_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 0,
.dstXincrement = 1,
.xCount = 1,
.srcYincrement = 1,
.dstYincrement = 1,
.yCount = 1,
.nextDescriptor = &RxDma_Descriptor_0,
};
cy_stc_dma_descriptor_t RxDma_Descriptor_0 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
cy_stc_dma_descriptor_t RxDma_Descriptor_1 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
const cy_stc_dma_channel_config_t RxDma_channelConfig =
{
.descriptor = &RxDma_Descriptor_0,
.preemptable = false,
.priority = 3,
.enable = false,
.bufferable = false,
};
const cy_stc_dma_crc_config_t RxDma_crcConfig =
{
.dataReverse = false,
.dataXor = 0,
.reminderReverse = false,
.reminderXor = 0,
.polynomial = 79764919,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t RxDma_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 0U,
.channel_num = RxDma_CHANNEL,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_dmas(void)
{
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&TxDma_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&RxDma_obj);
#endif //defined (CY_USING_HAL)
}

76
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
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@ -1,76 +0,0 @@
/*******************************************************************************
* File Name: cycfg_dmas.h
*
* Description:
* DMA configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5972
* mtb-pdl-cat1 2.4.0.14850
* personalities 6.0.0.0
* udd 3.0.0.2024
*
********************************************************************************
* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_DMAS_H)
#define CYCFG_DMAS_H
#include "cycfg_notices.h"
#include "cy_dma.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
#endif
#define TxDma_ENABLED 1U
#define TxDma_HW DW0
#define TxDma_CHANNEL 26U
#define TxDma_IRQ cpuss_interrupts_dw0_26_IRQn
#define RxDma_ENABLED 1U
#define RxDma_HW DW0
#define RxDma_CHANNEL 27U
#define RxDma_IRQ cpuss_interrupts_dw0_27_IRQn
extern const cy_stc_dma_descriptor_config_t TxDma_Descriptor_0_config;
extern cy_stc_dma_descriptor_t TxDma_Descriptor_0;
extern const cy_stc_dma_channel_config_t TxDma_channelConfig;
extern const cy_stc_dma_crc_config_t TxDma_crcConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t TxDma_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t RxDma_Descriptor_0_config;
extern const cy_stc_dma_descriptor_config_t RxDma_Descriptor_1_config;
extern cy_stc_dma_descriptor_t RxDma_Descriptor_0;
extern cy_stc_dma_descriptor_t RxDma_Descriptor_1;
extern const cy_stc_dma_channel_config_t RxDma_channelConfig;
extern const cy_stc_dma_crc_config_t RxDma_crcConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t RxDma_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_dmas(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_DMAS_H */

66
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
View File

@ -1,66 +0,0 @@
/*******************************************************************************
* File Name: cycfg_peripherals.c
*
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5972
* mtb-pdl-cat1 2.4.0.13881
* personalities 6.0.0.0
* udd 3.0.0.1974
*
********************************************************************************
* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include <rtthread.h>
#include "cycfg_peripherals.h"
cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};
void init_cycfg_peripherals(void)
{
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
#ifdef BSP_USING_UART0
/* UART0 Device Clock*/
Cy_SysClk_PeriphAssignDivider(PCLK_SCB0_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
#endif
#ifdef BSP_USING_UART1
/* UART1 Device Clock*/
Cy_SysClk_PeriphAssignDivider(PCLK_SCB1_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
#endif
#ifdef BSP_USING_UART2
/* UART2 Device Clock*/
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
#endif
#if defined(BSP_USING_UART3) || defined(BSP_USING_HW_I2C3)
/* UART3 Device Clock*/
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
#endif
#ifdef BSP_USING_UART4
/* UART4 Device Clock*/
Cy_SysClk_PeriphAssignDivider(PCLK_SCB4_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
#endif
#ifdef BSP_USING_UART5
/* UART5 Device Clock*/
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
#endif
}

20
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
View File

@ -1,20 +0,0 @@
[Device=CY8C624ABZI-S2D44]
[Blocks]
# WIFI
# CYBSP_WIFI_SDIO
sdhc[0]
# CYBSP_WIFI_SDIO_D0
ioss[0].port[2].pin[0]
# CYBSP_WIFI_SDIO_D1
ioss[0].port[2].pin[1]
# CYBSP_WIFI_SDIO_D2
ioss[0].port[2].pin[2]
# CYBSP_WIFI_SDIO_D3
ioss[0].port[2].pin[3]
# CYBSP_WIFI_SDIO_CMD
ioss[0].port[2].pin[4]
# CYBSP_WIFI_SDIO_CLK
ioss[0].port[2].pin[5]
# CYBSP_WIFI_WL_REG_ON
ioss[0].port[2].pin[6]

7
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/dependencies-v1.txt
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@ -1,7 +0,0 @@
capsense
core-lib
core-make
mtb-hal-cat1
mtb-pdl-cat1
psoc6cm0p
recipe-make-cat1a

7
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/dependencies-v2.txt
View File

@ -1,7 +0,0 @@
capsense
core-lib
core-make
mtb-hal-cat1
mtb-pdl-cat1
psoc6cm0p
recipe-make-cat1a

7
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/dependencies-v3.txt
View File

@ -1,7 +0,0 @@
capsense
core-lib
core-make
mtb-hal-cat1
mtb-pdl-cat1
psoc6cm0p
recipe-make-cat1a

1
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/version.xml
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@ -1 +0,0 @@
<version>3.1.0.27308</version>

735
bsp/Infineon/psoc6-cy8ckit-062-BLE/.config Normal file
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@ -0,0 +1,735 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=8
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
#
# kservice optimization
#
CONFIG_RT_KSERVICE_USING_STDLIB=y
# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_DM is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart5"
CONFIG_RT_VER_NUM=0x50000
# CONFIG_RT_USING_CACHE is not set
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
# CONFIG_RT_USING_CPU_FFS is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
CONFIG_RT_USING_MSH=y
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
# CONFIG_RT_USING_DFS is not set
# CONFIG_RT_USING_FAL is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_UNAMED_PIPE_NUMBER=64
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
# CONFIG_RT_USING_RANDOM is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_FDT is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_LCD is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_DEV_BUS is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
#
# Using USB
#
# CONFIG_RT_USING_USB is not set
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# C/C++ and POSIX layer
#
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
# CONFIG_RT_USING_POSIX_TIMER is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Interprocess Communication (IPC)
#
# CONFIG_RT_USING_POSIX_PIPE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
#
# Socket is in the 'Network' category
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
# CONFIG_RT_USING_AT is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LWIP is not set
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_IOTSHARP_SDK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
# CONFIG_PKG_USING_HM is not set
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
# CONFIG_PKG_USING_ZFTP is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_LIBSODIUM is not set
# CONFIG_PKG_USING_LIBHYDROGEN is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
#
# JSON: JavaScript Object Notation, a lightweight data-interchange format
#
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PARSON is not set
#
# XML: Extensible Markup Language
#
# CONFIG_PKG_USING_SIMPLE_XML is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_LUATOS_SOC is not set
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
# CONFIG_PKG_USING_PIKASCRIPT is not set
# CONFIG_PKG_USING_RTT_RUST is not set
#
# multimedia packages
#
#
# LVGL: powerful and easy-to-use embedded GUI library
#
# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
#
# u8g2: a monochrome graphic library
#
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_GUIENGINE is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
# CONFIG_PKG_USING_FDT is not set
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
#
# system packages
#
#
# enhanced kernel services
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_PERF_COUNTER is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_MCUBOOT is not set
# CONFIG_PKG_USING_TINYUSB is not set
# CONFIG_PKG_USING_CHERRYUSB is not set
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
#
# Kendryte SDK
#
# CONFIG_PKG_USING_K210_SDK is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_MULTI_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
#
# project laboratory
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_CMATRIX is not set
# CONFIG_PKG_USING_SL is not set
# CONFIG_PKG_USING_CAL is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_HEATSHRINK is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
# CONFIG_PKG_USING_CONTROLLER is not set
# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
# CONFIG_PKG_USING_MFBD is not set
# CONFIG_PKG_USING_SLCAN2RTT is not set
# CONFIG_PKG_USING_SOEM is not set
# CONFIG_PKG_USING_QPARAM is not set
#
# Arduino libraries
#
# CONFIG_PKG_USING_RTDUINO is not set
#
# Sensor libraries
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
#
# Display libraries
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
#
# Timing libraries
#
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
#
# Project libraries
#
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
#
# Hardware Drivers Config
#
CONFIG_SOC_CY8C6347BZI_BLD53=y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_USB_TO_USART=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
# CONFIG_BSP_USING_UART0 is not set
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
CONFIG_BSP_USING_UART5=y
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_SDMMC is not set
# CONFIG_BSP_USING_HW_I2C is not set
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_RTC is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_DAC is not set
# CONFIG_BSP_USING_TIM is not set

247
bsp/Infineon/psoc6-cy8ckit-062-BLE/.cproject Normal file
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bsp/Infineon/psoc6-cy8ckit-062-BLE/.gitignore vendored Normal file
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*.pyc
*.map
*.dblite
*.elf
*.bin
*.hex
*.axf
*.exe
*.pdb
*.idb
*.ilk
*.old
build
Debug
documentation/html
packages/
*~
*.o
*.obj
*.out
*.bak
*.dep
*.lib
*.i
*.d
.DS_Stor*
.config 3
.config 4
.config 5
Midea-X1
*.uimg
GPATH
GRTAGS
GTAGS
.vscode
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h

28
bsp/Infineon/psoc6-cy8ckit-062-BLE/.project Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>project</name>
<comment />
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>com.cypress.studio.app.cymodusnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources />
</projectDescription>

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bsp/Infineon/psoc6-cy8ckit-062-BLE/.settings/.rtmenus Normal file
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14
bsp/Infineon/psoc6-cy8ckit-062-BLE/.settings/language.settings.xml Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1283879096433011140" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
</extension>
</configuration>
</project>

3
bsp/Infineon/psoc6-cy8ckit-062-BLE/.settings/org.eclipse.core.runtime.prefs Normal file
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@ -0,0 +1,3 @@
content-types/enabled=true
content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
eclipse.preferences.version=1

20
bsp/Infineon/psoc6-cy8ckit-062-BLE/.settings/projcfg.ini Normal file
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#RT-Thread Studio Project Configuration
#Thu Feb 02 15:45:05 CST 2023
project_type=rt-thread
chip_name=CY8C6347BZI_BLD53
os_branch=full
example_name=
os_version=latest
selected_rtt_version=latest
cfg_version=v3.0
board_base_nano_proj=False
is_use_scons_build=True
output_project_path=C\:\\Users\\Qianchen\\Downloads\\rt-thread-master\\rt-thread-master\\bsp\\Infineon\\psoc6-cy8ckit-062-BLE\\dist
project_base_bsp=true
hardware_adapter=KitProg3
project_name=1111
is_base_example_project=False
board_name=psoc6-cy8ckit-062S2-43012
device_vendor=Infineon
bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0
bsp_version=1.0.0

65
bsp/Infineon/psoc6-cy8ckit-062-BLE/.settings/project.DAPLink.Debug.rttlaunch Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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58
bsp/Infineon/psoc6-cy8ckit-062-BLE/.settings/project.OpenOCD.Debug.rttlaunch Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
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<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
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<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
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<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
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21
bsp/Infineon/psoc6-cy8ckit-062-BLE/Kconfig Normal file
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@ -0,0 +1,21 @@
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../libraries/Kconfig"
source "board/Kconfig"

210
bsp/Infineon/psoc6-cy8ckit-062-BLE/LICENSE Normal file
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@ -0,0 +1,210 @@
CYPRESS END USER LICENSE AGREEMENT
PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE
DOWNLOADING, INSTALLING, COPYING, OR USING THIS SOFTWARE AND ACCOMPANYING
DOCUMENTATION. BY DOWNLOADING, INSTALLING, COPYING OR USING THE SOFTWARE,
YOU ARE AGREEING TO BE BOUND BY THIS AGREEMENT. IF YOU DO NOT AGREE TO ALL
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# Infineon Psoc6-CY8ckit-062-BLE 说明
## 简介
本文档为 `RT-Thread` 为 ` Psoc6-CY8ckit-062-BLE`开发板提供的 BSP (板级支持包) 说明。
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
- 进阶使用方法
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 `RT-Thread` 驱动更多板载资源。
## 开发板介绍
` Psoc6-CY8ckit-062-BLE` 是英飞凌推出的一款32位双核CPU子系统（ ARM Cortex-M4 和 ARM Cortex-M0）的开发板，具有单周期乘法的150-MHz Arm Cortex-M4F CPU (浮点和存储器保护单元)，100-MHz Cortex M0+ CPU，带单周期乘法和MPU，可以充分发挥 PSoC6 双核芯片性能。
开发板外观详细信息：[CY8CKIT-062-BLE - Infineon Technologies](https://www.infineon.com/cms/en/product/evaluation-boards/cy8ckit-062-ble/)
该开发板核心 **板载资源** 如下：
- MCU：CY8C6347BZI_BLD53，Cortex-M4主频 150MHz，Cortex-M0主频 100MHz，1MB Flash 和 288KB SRAM
MCU手册更多详细信息请参考文档 [PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet (infineon.com)](https://www.infineon.com/dgdl/Infineon-PSOC_6_MCU_CY8C62X8_CY8C62XA-DataSheet-v17_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee7d03a70b1)
- 开发环境：ModusToolbox 2.0/MDK V5
PSoC® Creator™ 下载链接 [ModusToolbox™ Software - Infineon Technologies](https://www.infineon.com/cms/en/design-support/tools/sdk/modustoolbox-software/)
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| :----------: | :----------: | :------: |
| USB 转串口 | 支持 | UART5 |
| GPIO | 支持 | — |
| UART | 支持 | UART0-5 |
## 快速上手
本 BSP 是以 `MDK V5` 和 `RT-Thread Studio` 为开发环境（编译器：ARMClang / GCC），接下来介绍如何将系统运行起来。
### 使用 MDK V5 开发
#### 硬件连接
使用数据线连接开发板到 PC。
#### 编译下载
1、配置工程：
首先打开 MDK ，若没有安装 `Infineon-PSoC6` 的芯片支持包会提示在线安装，根据提示安装即可。若受网络问题，可以进入 [keil](https://www.keil.com/dd2/pack) 官网下载安装包，离线安装。
![mdk_package](./figures/mdk_package.png)
2、 编译此工程：在安装好芯片支持包后，在 `MDK`工程中进行编译。
3、下载此工程：
工程默认配置使用板载 `DAP-LINK` 使用 `SWD` 方式下载程序，使用数据线连接开发板，编译之后直接点击下载按钮即可。
### 使用 RT-Thread Studio 开发
#### 导入工程
* 首先打开 `RT-Thread Studio` 开发工具，点加左上角文件—>导入—> RT-Thread Studio项目到工作空间中。
![](./figures/studio1.png)
* 接着选择 `Psoc6-CY8ckit-062-BLE` 开发板支持包的目录，进行导入。
![](./figures/studio2.png)
#### 编译下载
* 点击 IDE 左上角的构建选项进行工程的编译。
![](./figures/studio3-build.png)
* 当编译无错误警告时，点击 `Debug` 或 `Download` 选项进行调试/下载。
注：若点击下载并下载成功后串口终端无显示信息，请手动按下复位按键进行重启运行。
![](./figures/studio4-download.png)
## 运行结果
下载程序成功之后，系统会自动运行。打开终端工具串口助手，选择波特率为 115200。复位设备后，LED 将会以 500HZ 的频率闪烁，而且在终端上可以看到 `RT-Thread` 的输出信息：
注：推荐使用串口调试助手如：`MobaXterm`
```
\ | /
- RT - Thread Operating System
/ | \ 4.1.1 build Jul 25 2022 18:03:35
2006 - 2022 Copyright by RT-Thread team
msh >
```
## 联系人
维护人:
- [Rbb666](https://github.com/Rbb666)

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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
IFX_library = 'IFX_PSOC6_HAL'
rtconfig.BSP_LIBRARY_TYPE = IFX_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, IFX_library, 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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import rtconfig
from building import *
import os
cwd = GetCurrentDir()
path = [cwd]
src = Glob('*.c')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
group = group + SConscript(os.path.join(item, 'SConscript'))
Return('group')

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-06-29 Rbb666 first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "drv_gpio.h"
#define LED_PIN GET_PIN(13, 7)
int main(void)
{
rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
for (;;)
{
rt_pin_write(LED_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}

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menu "Hardware Drivers Config"
config SOC_CY8C6347BZI_BLD53
bool
select SOC_SERIES_IFX_PSOC63
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_USB_TO_USART
bool "Enable USB TO USART (uart5)"
select BSP_USING_UART
select BSP_USING_UART5
default y
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "Enable UART0"
default n
config BSP_USING_UART1
bool "Enable UART1"
default n
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_USING_UART3
bool "Enable UART3"
default n
config BSP_USING_UART4
bool "Enable UART4"
default n
config BSP_USING_UART5
bool "Enable UART5"
default y
endif
menuconfig BSP_USING_PWM
bool "Enable PWM"
default n
select RT_USING_PWM
if BSP_USING_PWM
menuconfig BSP_USING_PWM0
bool "Enable timer0 output pwm"
default n
if BSP_USING_PWM0
menuconfig BSP_USING_PWM0_CH3
bool "Enable PWM0 channel3"
default n
if BSP_USING_PWM0_CH3
config BSP_USING_PWM0_PORT13
bool "Enable PWM0-PORT13 output pwm"
default n
endif
menuconfig BSP_USING_PWM0_CH7
bool "Enable PWM0 channel7"
default n
if BSP_USING_PWM0_CH7
config BSP_USING_PWM0_PORT2
bool "Enable PWM0-PORT2 output pwm"
default n
endif
if BSP_USING_PWM0_CH7
config BSP_USING_PWM0_PORT5
bool "Enable PWM0-PORT5 output pwm"
default n
endif
if BSP_USING_PWM0_CH7
config BSP_USING_PWM0_PORT7
bool "Enable PWM0-PORT7 output pwm"
default n
endif
if BSP_USING_PWM0_CH7
config BSP_USING_PWM0_PORT9
bool "Enable PWM0-PORT9 output pwm"
default n
endif
if BSP_USING_PWM0_CH7
config BSP_USING_PWM0_PORT10
bool "Enable PWM0-PORT10 output pwm"
default n
endif
if BSP_USING_PWM0_CH7
config BSP_USING_PWM0_PORT12
bool "Enable PWM0-PORT12 output pwm"
default n
endif
endif
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
select RT_USING_SPI
default n
if BSP_USING_SPI
menuconfig BSP_USING_SPI3
bool "Enable SPI3 BUS"
default n
if BSP_USING_SPI3
config BSP_USING_SPI3_SAMPLE
bool "Enable SPI3 BUS Sample"
default n
endif
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
endif
config BSP_USING_SDMMC
bool "Enable SDMMC (sd card)"
default n
select RT_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
if BSP_USING_SDMMC
config BSP_USING_SDIO1
bool "Enable SDIO1 (sd card)"
default n
endif
menuconfig BSP_USING_HW_I2C
bool "Enable Hardware I2C Bus"
default n
select RT_USING_I2C
select RT_USING_PIN
if BSP_USING_HW_I2C
config BSP_USING_HW_I2C3
bool "Enable I2C3 Bus (User I2C)"
default n
if BSP_USING_HW_I2C3
comment "Notice: P6_0 --> 48; P6_1 --> 49"
config BSP_I2C3_SCL_PIN
int "i2c3 SCL pin number"
range 1 113
default 48
config BSP_I2C3_SDA_PIN
int "i2c3 SDA pin number"
range 1 113
default 49
endif
config BSP_USING_HW_I2C6
bool "Enable I2C6 Bus (User I2C)"
default n
if BSP_USING_HW_I2C6
comment "Notice: P13_0 --> 48; P13_1 --> 49"
config BSP_I2C6_SCL_PIN
int "i2c6 SCL pin number"
range 1 113
default 104
config BSP_I2C6_SDA_PIN
int "i2c6 SDA pin number"
range 1 113
default 105
endif
endif
menuconfig BSP_USING_I2C
bool "Enable Software I2C Bus"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C
config BSP_USING_I2C1
bool "Enable I2C1 Bus (User I2C)"
default n
if BSP_USING_I2C1
comment "Notice: P13_1 --> 105; P13_2 --> 106"
config BSP_I2C1_SCL_PIN
int "i2c1 SCL pin number"
range 1 113
default 105
config BSP_I2C1_SDA_PIN
int "i2c1 SDA pin number"
range 1 113
default 106
endif
endif
menuconfig BSP_USING_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
if BSP_USING_RTC
choice
prompt "Select clock source"
default BSP_RTC_USING_LSE
config BSP_RTC_USING_LSE
bool "RTC USING LSE"
config BSP_RTC_USING_LSI
bool "RTC USING LSI"
endchoice
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
menuconfig BSP_USING_DAC
bool "Enable DAC"
default n
select RT_USING_DAC
if BSP_USING_DAC
config BSP_USING_DAC1
bool "Enable DAC1"
default n
config BSP_USING_DAC2
bool "Enable DAC2"
default n
endif
menuconfig BSP_USING_TIM
bool "Enable timer"
default n
select RT_USING_HWTIMER
if BSP_USING_TIM
config BSP_USING_TIM1
bool "Enable TIM1"
default n
config BSP_USING_TIM2
bool "Enable TIM2"
default n
endif
endmenu
endmenu

40
bsp/Infineon/psoc6-cy8ckit-062-BLE/board/SConscript Normal file
View File

@ -0,0 +1,40 @@
import os
import rtconfig
from building import *
Import('SDK_LIB')
objs = []
cwd = GetCurrentDir()
list = os.listdir(cwd)
# add general drivers
src = Split('''
board.c
''')
if GetDepend(['BSP_USING_SPI3_SAMPLE']):
src += Glob('ports/spi_sample.c')
if GetDepend(['BSP_USING_RW007']):
src += Glob('ports/drv_rw007.c')
if GetDepend(['BSP_USING_SLIDER']):
src += Glob('ports/slider_sample.c')
path = [cwd]
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB
if rtconfig.PLATFORM in ['gcc']:
src += [startup_path_prefix +
'/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S']
elif rtconfig.PLATFORM in ['armclang']:
src += [startup_path_prefix +
'/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S']
CPPDEFINES = ['CY8C6347BZI_BLD53', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1', 'COMPONENT_BSP_DESIGN_MODUS']
group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path, CPPDEFINES=CPPDEFINES)
Return('group')

25
bsp/Infineon/psoc6-cy8ckit-062-BLE/board/board.c Normal file
View File

@ -0,0 +1,25 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-06-29 Rbb666 first version
*/
#include "board.h"
void cy_bsp_all_init(void)
{
cy_rslt_t result;
/* Initialize the device and board peripherals */
result = cybsp_init();
/* Board init failed. Stop program execution */
if (result != CY_RSLT_SUCCESS)
{
CY_ASSERT(0);
}
}

51
bsp/Infineon/psoc6-cy8ckit-062-BLE/board/board.h Normal file
View File

@ -0,0 +1,51 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-06-29 Rbb666 first version
* 2022-07-26 Rbb666 Add Flash Config
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <rtthread.h>
#include "drv_common.h"
#include "drv_gpio.h"
#include "cy_result.h"
#include "cybsp_types.h"
#include "cyhal.h"
#include "cybsp.h"
#ifdef BSP_USING_USBD
#include "cy_usb_dev.h"
#include "cy_usb_dev_hid.h"
#include "cycfg_usbdev.h"
#endif
/*SRAM CONFIG*/
#define IFX_SRAM_SIZE (277)
#define IFX_SRAM_END (0x08002000 + IFX_SRAM_SIZE * 1024)
#ifdef __ARMCC_VERSION
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#define HEAP_END IFX_SRAM_END
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern unsigned int __end__;
extern unsigned int __HeapLimit;
#define HEAP_BEGIN (void*)&__end__
#define HEAP_END (void*)&__HeapLimit
#endif
void cy_bsp_all_init(void);
#endif

494
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf → bsp/Infineon/psoc6-cy8ckit-062-BLE/board/linker_scripts/link.icf
View File

@ -1,247 +1,247 @@
/*******************************************************************************
* \file cy8c6xxa_cm4_dual.icf
* \version 2.91
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x080FF7FF;
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x101FFFFF;
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/**** End of ICF editor section. ###ICF###*/
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*/
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
define block RO {first section .intvec, readonly};
define block cy_xip { section .cy_xip };
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block CM0P_RO };
/* Flash - Cortex-M4 application */
place in IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
"cy_xip" : place at start of EROM1_region { block cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_m0p_image,
section .cy_app_signature,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00200000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */
/*******************************************************************************
* \file cy8c6xx7_cm4_dual.icf
* \version 2.91
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF;
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF;
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/**** End of ICF editor section. ###ICF###*/
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*/
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
define block RO {first section .intvec, readonly};
define block cy_xip { section .cy_xip };
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block CM0P_RO };
/* Flash - Cortex-M4 application */
place in IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
"cy_xip" : place at start of EROM1_region { block cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_m0p_image,
section .cy_app_signature,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00100000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */

65
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld → bsp/Infineon/psoc6-cy8ckit-062-BLE/board/linker_scripts/link.ld
View File

@ -1,5 +1,5 @@
/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.ld
* \file cy8c6xx7_cm4_dual.ld
* \version 2.91
*
* Linker file for the GNU C compiler.
@ -70,8 +70,8 @@ MEMORY
* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0xFD800
flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x200000
ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800
flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
@ -176,6 +176,35 @@ SECTIONS
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
/* section information for utest */
. = ALIGN(4);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
/* section information for initialization */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
} > flash
@ -195,7 +224,7 @@ SECTIONS
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */
.copy.table :
{
. = ALIGN(4);
@ -213,33 +242,11 @@ SECTIONS
__copy_table_end__ = .;
} > flash
/* setction information for finsh shell begin */
FSymTab :
{
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
} > flash
VSymTab :
{
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
} > flash
rti_fn :
{
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
} > flash
/* setction information for finsh shell end */
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */
.zero.table :
{
. = ALIGN(4);
@ -439,7 +446,7 @@ SECTIONS
/* The following symbols used by the cymcuelftool. */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00200000;
__cy_memory_0_length = 0x00100000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */

554
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct → bsp/Infineon/psoc6-cy8ckit-062-BLE/board/linker_scripts/link.sct
View File

@ -1,277 +1,277 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file cy8c6xxa_cm4_dual.sct
;* \version 2.91
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at
;*
;* http://www.apache.org/licenses/LICENSE-2.0
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM
#define RAM_START 0x08002000
#define RAM_SIZE 0x000FD800
; Flash
#define FLASH_START 0x10000000
#define FLASH_SIZE 0x00200000
; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200
; External memory
#define XIP_START 0x18000000
#define XIP_SIZE 0x08000000
; eFuse
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE
{
.cy_m0p_image +0 FLASH_CM0P_SIZE
{
* (.cy_m0p_image)
}
}
; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS RAM_START UNINIT
{
* (RESET_RAM, +FIRST)
}
RW_RAM_DATA +0
{
* (.cy_ramfunc)
* (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
; device startup.
RW_IRAM1 +0 UNINIT
{
* (.noinit)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{
}
; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{
}
; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required
; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{
* (.cy_app_signature)
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
.cy_em_eeprom +0
{
* (.cy_em_eeprom)
}
}
; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{
.cy_sflash_user_data +0
{
* (.cy_sflash_user_data)
}
}
; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{
.cy_sflash_nar +0
{
* (.cy_sflash_nar)
}
}
; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{
.cy_sflash_public_key +0
{
* (.cy_sflash_public_key)
}
}
; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{
.cy_toc_part2 +0
{
* (.cy_toc_part2)
}
}
; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{
.cy_rtoc_part2 +0
{
* (.cy_rtoc_part2)
}
}
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE
{
cy_xip +0
{
* (.cy_xip)
}
}
; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE
{
.cy_efuse +0
{
* (.cy_efuse)
}
}
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
#define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00200000
#define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200
/* Supervisory Flash */
#define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200
/* XIP */
#define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200
/* eFuse */
#define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1
/* [] END OF FILE */
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.91
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at
;*
;* http://www.apache.org/licenses/LICENSE-2.0
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM
#define RAM_START 0x08002000
#define RAM_SIZE 0x00045800
; Flash
#define FLASH_START 0x10000000
#define FLASH_SIZE 0x00100000
; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200
; External memory
#define XIP_START 0x18000000
#define XIP_SIZE 0x08000000
; eFuse
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE
{
.cy_m0p_image +0 FLASH_CM0P_SIZE
{
* (.cy_m0p_image)
}
}
; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS RAM_START UNINIT
{
* (RESET_RAM, +FIRST)
}
RW_RAM_DATA +0
{
* (.cy_ramfunc)
* (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
; device startup.
RW_IRAM1 +0 UNINIT
{
* (.noinit)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{
}
; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{
}
; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required
; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{
* (.cy_app_signature)
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
.cy_em_eeprom +0
{
* (.cy_em_eeprom)
}
}
; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{
.cy_sflash_user_data +0
{
* (.cy_sflash_user_data)
}
}
; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{
.cy_sflash_nar +0
{
* (.cy_sflash_nar)
}
}
; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{
.cy_sflash_public_key +0
{
* (.cy_sflash_public_key)
}
}
; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{
.cy_toc_part2 +0
{
* (.cy_toc_part2)
}
}
; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{
.cy_rtoc_part2 +0
{
* (.cy_rtoc_part2)
}
}
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE
{
cy_xip +0
{
* (.cy_xip)
}
}
; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE
{
.cy_efuse +0
{
* (.cy_efuse)
}
}
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
#define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200
/* Supervisory Flash */
#define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200
/* XIP */
#define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200
/* eFuse */
#define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1
/* [] END OF FILE */

67
bsp/Infineon/psoc6-cy8ckit-062-BLE/board/ports/drv_rw007.c Normal file
View File

@ -0,0 +1,67 @@
#include <rtthread.h>
#include <rtdbg.h>
#ifdef BSP_USING_RW007
#include <rtdevice.h>
#include <drv_spi.h>
#include <board.h>
#include <spi_wifi_rw007.h>
extern void spi_wifi_isr(int vector);
static void rw007_gpio_init(void)
{
/* Configure IO */
rt_pin_mode(IFX_RW007_RST_PIN, PIN_MODE_OUTPUT);
rt_pin_mode(IFX_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN);
/* Reset rw007 and config mode */
rt_pin_write(IFX_RW007_RST_PIN, PIN_LOW);
rt_thread_delay(rt_tick_from_millisecond(100));
rt_pin_write(IFX_RW007_RST_PIN, PIN_HIGH);
/* Wait rw007 ready(exit busy stat) */
while (!rt_pin_read(IFX_RW007_INT_BUSY_PIN))
{
rt_thread_delay(5);
}
rt_thread_delay(rt_tick_from_millisecond(200));
rt_pin_mode(IFX_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP);
}
static struct rt_spi_device rw007_dev;
int wifi_spi_device_init(void)
{
char sn_version[32];
uint32_t cs_pin = IFX_RW007_CS_PIN;
rw007_gpio_init();
rt_hw_spi_device_attach(IFX_RW007_SPI_BUS_NAME, "wspi", cs_pin);
rt_hw_wifi_init("wspi");
rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP);
rw007_sn_get(sn_version);
rt_kprintf("\nrw007 sn: [%s]\n", sn_version);
rw007_version_get(sn_version);
rt_kprintf("rw007 ver: [%s]\n\n", sn_version);
return 0;
}
INIT_APP_EXPORT(wifi_spi_device_init);
static void int_wifi_irq(void *p)
{
((void)p);
spi_wifi_isr(0);
}
void spi_wifi_hw_init(void)
{
rt_pin_attach_irq(IFX_RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0);
rt_pin_irq_enable(IFX_RW007_INT_BUSY_PIN, RT_TRUE);
}
#endif /* BSP_USING_RW007 */

37
bsp/Infineon/psoc6-cy8ckit-062-BLE/board/ports/fal_cfg.h Normal file
View File

@ -0,0 +1,37 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-07-27 Rbb666 first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
extern const struct fal_flash_dev ifx_onchip_flash_32k;
extern const struct fal_flash_dev ifx_onchip_flash_256k;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&ifx_onchip_flash_32k, \
&ifx_onchip_flash_256k, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash_32k", 0, IFX_EFLASH_SIZE, 0}, \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash_256k", 0, IFX_FLASH_SIZE, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

243
bsp/Infineon/psoc6-cy8ckit-062-BLE/board/ports/slider_sample.c Normal file
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@ -0,0 +1,243 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-07-28 Rbb666 first version
*/
#include <rtthread.h>
#include "drv_common.h"
#ifdef BSP_USING_SLIDER
#include "cycfg_capsense.h"
#define CAPSENSE_INTR_PRIORITY (7u)
#define EZI2C_INTR_PRIORITY (6u)
/* Allowed duty cycle for maximum brightness */
#define LED_MAX_BRIGHTNESS (100u)
/* Allowed duty cycle for minimum brightness*/
#define LED_MIN_BRIGHTNESS (0u)
#define GET_DUTY_CYCLE(x) (1 * 1000 * 1000 - x * 10 * 1000)
typedef enum
{
LED_OFF,
LED_ON
} led_state_t;
typedef struct
{
led_state_t state;
uint32_t brightness;
} led_data_t;
static rt_sem_t trans_done_semphr = RT_NULL;
#ifndef RT_USING_PWM
#error You need enable PWM to use this sample
#else
#define PWM_DEV_NAME "pwm0"
#define PWM_DEV_CHANNEL 3
static struct rt_device_pwm *pwm_dev;
#endif
static void capsense_isr(void)
{
/* enter interrupt */
rt_interrupt_enter();
Cy_CapSense_InterruptHandler(CYBSP_CSD_HW, &cy_capsense_context);
/* leave interrupt */
rt_interrupt_leave();
}
void capsense_callback(cy_stc_active_scan_sns_t *ptrActiveScan)
{
rt_sem_release(trans_done_semphr);
}
static uint32_t initialize_capsense(void)
{
uint32_t status = CYRET_SUCCESS;
/* CapSense interrupt configuration parameters */
static const cy_stc_sysint_t capSense_intr_config =
{
.intrSrc = csd_interrupt_IRQn,
.intrPriority = CAPSENSE_INTR_PRIORITY,
};
/* Capture the CSD HW block and initialize it to the default state. */
status = Cy_CapSense_Init(&cy_capsense_context);
if (CYRET_SUCCESS != status)
{
return status;
}
/* Initialize CapSense interrupt */
cyhal_system_set_isr(csd_interrupt_IRQn, csd_interrupt_IRQn, CAPSENSE_INTR_PRIORITY, &capsense_isr);
NVIC_ClearPendingIRQ(capSense_intr_config.intrSrc);
NVIC_EnableIRQ(capSense_intr_config.intrSrc);
/* Initialize the CapSense firmware modules. */
status = Cy_CapSense_Enable(&cy_capsense_context);
if (CYRET_SUCCESS != status)
{
return status;
}
/* Assign a callback function to indicate end of CapSense scan. */
status = Cy_CapSense_RegisterCallback(CY_CAPSENSE_END_OF_SCAN_E,
capsense_callback, &cy_capsense_context);
if (CYRET_SUCCESS != status)
{
return status;
}
return status;
}
void Slider_Init(void)
{
cy_rslt_t result;
result = initialize_capsense();
if (CYRET_SUCCESS != result)
{
/* Halt the CPU if CapSense initialization failed */
RT_ASSERT(0);
}
/* Initiate first scan */
Cy_CapSense_ScanAllWidgets(&cy_capsense_context);
trans_done_semphr = rt_sem_create("slider_sem", 1, RT_IPC_FLAG_PRIO);
if (trans_done_semphr == RT_NULL)
{
rt_kprintf("create transform done semphr failed.\n");
RT_ASSERT(0);
return;
}
#ifdef BSP_USING_PWM0_PORT13
/* Initiate PWM*/
pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
if (pwm_dev == RT_NULL)
{
rt_kprintf("PWM init failed! can't find %s device!\n", PWM_DEV_NAME);
RT_ASSERT(0);
}
/*default period:1ms pulse:0*/
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, 1 * 1000 * 1000, 1 * 1000 * 1000);
rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
#endif
}
void update_led_state(led_data_t *ledData)
{
if (ledData->brightness >= 0)
{
uint32_t brightness = (ledData->brightness < LED_MIN_BRIGHTNESS) ? LED_MIN_BRIGHTNESS : ledData->brightness;
/* Drive the LED with brightness */
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, 1 * 1000 * 1000, GET_DUTY_CYCLE(brightness));
}
}
static void process_touch(void)
{
cy_stc_capsense_touch_t *slider_touch_info;
uint16_t slider_pos;
uint8_t slider_touch_status;
bool led_update_req = false;
static uint16_t slider_pos_prev;
static led_data_t led_data = {LED_ON, LED_MAX_BRIGHTNESS};
/* Get slider status */
slider_touch_info = Cy_CapSense_GetTouchInfo(
CY_CAPSENSE_LINEARSLIDER0_WDGT_ID, &cy_capsense_context);
slider_touch_status = slider_touch_info->numPosition;
slider_pos = slider_touch_info->ptrPosition->x;
/* Detect the new touch on slider */
if ((RT_NULL != slider_touch_status) &&
(slider_pos != slider_pos_prev))
{
led_data.brightness = (slider_pos * 100)
/ cy_capsense_context.ptrWdConfig[CY_CAPSENSE_LINEARSLIDER0_WDGT_ID].xResolution;
led_update_req = true;
}
#ifndef RT_USING_PWM
#error You need enable PWM to use this sample
#else
/* Update the LED state if requested */
if (led_update_req)
{
update_led_state(&led_data);
}
#endif
slider_pos_prev = slider_pos;
}
static void Slider_thread_entry(void *parameter)
{
Slider_Init();
for (;;)
{
rt_sem_take(trans_done_semphr, RT_WAITING_FOREVER);
/* Process all widgets */
Cy_CapSense_ProcessAllWidgets(&cy_capsense_context);
/* Process touch input */
process_touch();
/* Establishes synchronized operation between the CapSense
* middleware and the CapSense Tuner tool.
*/
Cy_CapSense_RunTuner(&cy_capsense_context);
/* Initiate next scan */
Cy_CapSense_ScanAllWidgets(&cy_capsense_context);
rt_thread_mdelay(50);
}
}
int Slider_ctrl_sample(void)
{
rt_err_t ret = RT_EOK;
rt_thread_t thread = rt_thread_create("slider_th",
Slider_thread_entry,
RT_NULL,
1024,
25,
10);
if (thread != RT_NULL)
{
rt_thread_startup(thread);
}
else
{
ret = RT_ERROR;
}
return ret;
}
MSH_CMD_EXPORT(Slider_ctrl_sample, Slider sample to ctrl led);
#endif

84
bsp/Infineon/psoc6-cy8ckit-062-BLE/board/ports/spi_sample.c Normal file
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@ -0,0 +1,84 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-07-19 Rbbb666 first version
*/
#include "board.h"
#if defined(BSP_USING_SPI3_SAMPLE)
#include <drv_spi.h>
#define SPI_NAME "spi30"
static struct rt_spi_device *spi_dev = RT_NULL;
/* attach spi5 device */
static int rt_spi_device_init(void)
{
struct rt_spi_configuration cfg;
rt_hw_spi_device_attach("spi3", "spi30", NULL);
cfg.data_width = 8;
cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB | RT_SPI_NO_CS;
cfg.max_hz = 1 *1000 *1000;
spi_dev = (struct rt_spi_device *)rt_device_find(SPI_NAME);
if (RT_NULL == spi_dev)
{
rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME);
return RT_ERROR;
}
rt_spi_configure(spi_dev, &cfg);
return RT_EOK;
}
INIT_APP_EXPORT(rt_spi_device_init);
/* spi5 loopback mode test case */
static int spi_sample(int argc, char **argv)
{
rt_uint8_t t_buf[8], r_buf[8];
int i = 0;
static struct rt_spi_message msg1;
if (argc != 9)
{
rt_kprintf("Please Usage:\n");
rt_kprintf("spi_sample 1 2 3 4 5 6 7 8\n");
return -RT_ERROR;
}
for (i = 0; i < 8; i++)
{
t_buf[i] = atoi(argv[i+1]);
}
msg1.send_buf = &t_buf;
msg1.recv_buf = &r_buf;
msg1.length = sizeof(t_buf);
msg1.cs_take = 1;
msg1.cs_release = 0;
msg1.next = RT_NULL;
rt_spi_transfer_message(spi_dev, &msg1);
rt_kprintf("spi rbuf : ");
for (i = 0; i < sizeof(t_buf); i++)
{
rt_kprintf("%x ", r_buf[i]);
}
rt_kprintf("\nspi loopback mode test over!\n");
return RT_EOK;
}
MSH_CMD_EXPORT(spi_sample, spi loopback test);
#endif /* BSP_USING_SPI3 */

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26
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/SConscript Normal file
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@ -0,0 +1,26 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = []
group = []
CPPPATH = []
if rtconfig.PLATFORM in ['iccarm']:
print("\nThe current project does not support IAR build\n")
Return('group')
elif rtconfig.PLATFORM in ['gcc', 'armclang']:
src += Glob(cwd + '/TARGET_CY8CKIT-062-BLE/*.c')
src += Glob(cwd + '/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/*.c')
src += Glob(cwd + '/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/*.c')
CPPPATH = [ cwd + '/TARGET_CY8CKIT-062-BLE',
cwd + '/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource']
if rtconfig.PLATFORM in ['gcc']:
src += [cwd + '/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S']
elif rtconfig.PLATFORM in ['armclang']:
src += [cwd + '/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S']
group = DefineGroup('libs', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

1
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/.cyignore Normal file
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@ -0,0 +1 @@
docs

10
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
View File

@ -4,13 +4,13 @@
* Description:
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5972
* mtb-pdl-cat1 2.4.0.13881
* personalities 6.0.0.0
* udd 3.0.0.1974
* Tools Package 2.4.0.5721
* mtb-pdl-cat1 3.0.0.10651
* personalities 5.0.0.0
* udd 3.0.0.1377
*
********************************************************************************
* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*

52
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h Normal file
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@ -0,0 +1,52 @@
/*******************************************************************************
* File Name: cycfg.h
*
* Description:
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5721
* mtb-pdl-cat1 3.0.0.10651
* personalities 5.0.0.0
* udd 3.0.0.1377
*
********************************************************************************
* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_H)
#define CYCFG_H
#if defined(__cplusplus)
extern "C" {
#endif
#include "cycfg_notices.h"
#include "cycfg_system.h"
#include "cycfg_clocks.h"
#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
void init_cycfg_all(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_H */

10
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
View File

@ -4,13 +4,13 @@
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5972
* mtb-pdl-cat1 2.4.0.13881
* personalities 6.0.0.0
* udd 3.0.0.1974
* Tools Package 2.4.0.5721
* mtb-pdl-cat1 3.0.0.10651
* personalities 5.0.0.0
* udd 3.0.0.1377
*
********************************************************************************
* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*

44
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c
View File

@ -2,12 +2,12 @@
* File Name: cycfg_capsense.c
*
* Description:
* CAPSENSE Middleware configuration
* CapSense Middleware configuration
* This file should not be modified. It was automatically generated by
* CapSense Configurator 4.0.0.6195
* CapSense Configurator 4.0.0.5943
*
********************************************************************************
* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company)
* Copyright 2021, Cypress Semiconductor Corporation (an Infineon company)
* or an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
@ -140,7 +140,7 @@ static const cy_stc_capsense_common_config_t cy_capsense_commonConfig =
.bistEn = CY_CAPSENSE_DISABLE,
#endif
.positionFilterEn = CY_CAPSENSE_DISABLE,
.periDividerType = (uint8_t)CY_CAPSENSE_PERI_DIV_TYPE,
.periDividerType = CY_CAPSENSE_PERI_DIV_TYPE,
.periDividerIndex = CY_CAPSENSE_PERI_DIV_INDEX,
.analogWakeupDelay = 25u,
.ssIrefSource = CY_CAPSENSE_IREF_SRSS,
@ -427,47 +427,47 @@ static const cy_stc_capsense_pin_config_t cy_capsense_pinConfig[CY_CAPSENSE_PIN_
{
{ /* Button0_Rx0 */
.ptrPin = &cy_capsense_pinConfig[0u],
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_RX_E,
.type = CY_CAPSENSE_ELTD_TYPE_MUT_RX_E,
.numPins = 1u,
},
{ /* Button0_Tx */
.ptrPin = &cy_capsense_pinConfig[1u],
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_TX_E,
.type = CY_CAPSENSE_ELTD_TYPE_MUT_TX_E,
.numPins = 1u,
},
{ /* Button1_Rx0 */
.ptrPin = &cy_capsense_pinConfig[2u],
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_RX_E,
.type = CY_CAPSENSE_ELTD_TYPE_MUT_RX_E,
.numPins = 1u,
},
{ /* Button1_Tx */
.ptrPin = &cy_capsense_pinConfig[3u],
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_TX_E,
.type = CY_CAPSENSE_ELTD_TYPE_MUT_TX_E,
.numPins = 1u,
},
{ /* LinearSlider0_Sns0 */
.ptrPin = &cy_capsense_pinConfig[4u],
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
.type = CY_CAPSENSE_ELTD_TYPE_SELF_E,
.numPins = 1u,
},
{ /* LinearSlider0_Sns1 */
.ptrPin = &cy_capsense_pinConfig[5u],
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
.type = CY_CAPSENSE_ELTD_TYPE_SELF_E,
.numPins = 1u,
},
{ /* LinearSlider0_Sns2 */
.ptrPin = &cy_capsense_pinConfig[6u],
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
.type = CY_CAPSENSE_ELTD_TYPE_SELF_E,
.numPins = 1u,
},
{ /* LinearSlider0_Sns3 */
.ptrPin = &cy_capsense_pinConfig[7u],
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
.type = CY_CAPSENSE_ELTD_TYPE_SELF_E,
.numPins = 1u,
},
{ /* LinearSlider0_Sns4 */
.ptrPin = &cy_capsense_pinConfig[8u],
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
.type = CY_CAPSENSE_ELTD_TYPE_SELF_E,
.numPins = 1u,
},
};
@ -529,7 +529,7 @@ static const cy_stc_capsense_widget_config_t cy_capsense_widgetConfig[CY_CAPSENS
#else
.senseMethod = CY_CAPSENSE_SENSE_METHOD_CSX_E,
#endif
.wdType = (uint8_t)CY_CAPSENSE_WD_BUTTON_E,
.wdType = CY_CAPSENSE_WD_BUTTON_E,
},
{ /* Button1 */
.ptrWdContext = &cy_capsense_tuner.widgetContext[1u],
@ -585,7 +585,7 @@ static const cy_stc_capsense_widget_config_t cy_capsense_widgetConfig[CY_CAPSENS
#else
.senseMethod = CY_CAPSENSE_SENSE_METHOD_CSX_E,
#endif
.wdType = (uint8_t)CY_CAPSENSE_WD_BUTTON_E,
.wdType = CY_CAPSENSE_WD_BUTTON_E,
},
{ /* LinearSlider0 */
.ptrWdContext = &cy_capsense_tuner.widgetContext[2u],
@ -641,7 +641,7 @@ static const cy_stc_capsense_widget_config_t cy_capsense_widgetConfig[CY_CAPSENS
#else
.senseMethod = CY_CAPSENSE_SENSE_METHOD_CSD_E,
#endif
.wdType = (uint8_t)CY_CAPSENSE_WD_LINEAR_SLIDER_E,
.wdType = CY_CAPSENSE_WD_LINEAR_SLIDER_E,
},
};
@ -687,8 +687,8 @@ cy_stc_capsense_tuner_t cy_capsense_tuner =
.rowSnsClk = 16u,
.gestureDetected = 0u,
.gestureDirection = 0u,
.xDelta = 0,
.yDelta = 0,
.xDelta = 0u,
.yDelta = 0u,
.noiseTh = 40u,
.nNoiseTh = 40u,
.hysteresis = 10u,
@ -719,8 +719,8 @@ cy_stc_capsense_tuner_t cy_capsense_tuner =
.rowSnsClk = 16u,
.gestureDetected = 0u,
.gestureDirection = 0u,
.xDelta = 0,
.yDelta = 0,
.xDelta = 0u,
.yDelta = 0u,
.noiseTh = 40u,
.nNoiseTh = 40u,
.hysteresis = 10u,
@ -751,8 +751,8 @@ cy_stc_capsense_tuner_t cy_capsense_tuner =
.rowSnsClk = 16u,
.gestureDetected = 0u,
.gestureDirection = 0u,
.xDelta = 0,
.yDelta = 0,
.xDelta = 0u,
.yDelta = 0u,
.noiseTh = 40u,
.nNoiseTh = 40u,
.hysteresis = 10u,

6
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h
View File

@ -2,12 +2,12 @@
* File Name: cycfg_capsense.h
*
* Description:
* CAPSENSE Middleware configuration
* CapSense Middleware configuration
* This file should not be modified. It was automatically generated by
* CapSense Configurator 4.0.0.6195
* CapSense Configurator 4.0.0.5943
*
********************************************************************************
* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company)
* Copyright 2021, Cypress Semiconductor Corporation (an Infineon company)
* or an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*

10
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h
View File

@ -2,16 +2,12 @@
* File Name: cycfg_capsense_defines.h
*
* Description:
* CAPSENSE configuration defines.
*
* Note: This file is required for the CAPSENSE Middleware Library to build
* successfully.
*
* CapSense configuration defines.
* This file should not be modified. It was automatically generated by
* CapSense Configurator 4.0.0.6195
* CapSense Configurator 4.0.0.5943
*
********************************************************************************
* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company)
* Copyright 2021, Cypress Semiconductor Corporation (an Infineon company)
* or an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*

6
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_tuner_regmap.h → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_tuner_regmap.h
View File

@ -2,12 +2,12 @@
* File Name: cycfg_capsense_tuner_regmap.h
*
* Description:
* CAPSENSE Tuner register map configuration.
* CapSense Tuner register map configuration.
* This file should not be modified. It was automatically generated by
* CapSense Configurator 4.0.0.6195
* CapSense Configurator 4.0.0.5943
*
********************************************************************************
* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company)
* Copyright 2021, Cypress Semiconductor Corporation (an Infineon company)
* or an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*

34
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -4,13 +4,13 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5972
* mtb-pdl-cat1 2.4.0.13881
* personalities 6.0.0.0
* udd 3.0.0.1974
* Tools Package 2.4.0.5721
* mtb-pdl-cat1 3.0.0.10651
* personalities 5.0.0.0
* udd 3.0.0.1377
*
********************************************************************************
* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
@ -26,33 +26,23 @@
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include <rtthread.h>
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CLK_PWM_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CLK_PWM_HW,
.channel_num = CLK_PWM_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
};
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void)
{
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);

14
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -4,13 +4,13 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5972
* mtb-pdl-cat1 2.4.0.13881
* personalities 6.0.0.0
* udd 3.0.0.1974
* Tools Package 2.4.0.5721
* mtb-pdl-cat1 3.0.0.10651
* personalities 5.0.0.0
* udd 3.0.0.1377
*
********************************************************************************
* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
@ -40,10 +40,6 @@
extern "C" {
#endif
#define CLK_PWM_ENABLED 1U
#define CLK_PWM_HW CY_SYSCLK_DIV_16_BIT
#define CLK_PWM_NUM 0U
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
#define CYBSP_CS_CLK_DIV_ENABLED CYBSP_CSD_CLK_DIV_ENABLED
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT

14
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
View File

@ -5,13 +5,13 @@
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5972
* mtb-pdl-cat1 2.4.0.13881
* personalities 6.0.0.0
* udd 3.0.0.1974
* Tools Package 2.4.0.5721
* mtb-pdl-cat1 3.0.0.10651
* personalities 5.0.0.0
* udd 3.0.0.1377
*
********************************************************************************
* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
@ -32,8 +32,8 @@
#define CYCFG_NOTICES_H
#ifdef CY_SUPPORTS_DEVICE_VALIDATION
#ifndef CY8C624ABZI_S2D44
#error "Unexpected target MCU; expected CY8C624ABZI-S2D44. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
#ifndef CY8C6347BZI_BLD53
#error "Unexpected target MCU; expected CY8C6347BZI-BLD53. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
#endif
#endif

53
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c Normal file
View File

@ -0,0 +1,53 @@
/*******************************************************************************
* File Name: cycfg_peripherals.c
*
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5721
* mtb-pdl-cat1 3.0.0.10651
* personalities 5.0.0.0
* udd 3.0.0.1377
*
********************************************************************************
* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_peripherals.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BLE_obj =
{
.type = CYHAL_RSC_BLESS,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};
void init_cycfg_peripherals(void)
{
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BLE_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
}

101
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h Normal file
View File

@ -0,0 +1,101 @@
/*******************************************************************************
* File Name: cycfg_peripherals.h
*
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5721
* mtb-pdl-cat1 3.0.0.10651
* personalities 5.0.0.0
* udd 3.0.0.1377
*
********************************************************************************
* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_PERIPHERALS_H)
#define CYCFG_PERIPHERALS_H
#include "cycfg_notices.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_sysclk.h"
#include "cy_csd.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define CYBSP_BLE_ENABLED 1U
#define CY_BLE_CORE_CORTEX_M4 4U
#define CY_BLE_CORE_CORTEX_M0P 0U
#define CY_BLE_CORE_DUAL 255U
#ifndef CY_BLE_CORE
#define CY_BLE_CORE 4U
#endif
#define CY_BLE_IRQ bless_interrupt_IRQn
#define CYBSP_CSD_ENABLED 1U
#define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 100000000u
#define CY_CAPSENSE_PERI_CLK 100000000u
#define CY_CAPSENSE_VDDA_MV 3300u
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
#define CY_CAPSENSE_PERI_DIV_INDEX 0u
#define Cmod_PORT GPIO_PRT7
#define CintA_PORT GPIO_PRT7
#define CintB_PORT GPIO_PRT7
#define Button0_Rx0_PORT GPIO_PRT8
#define Button0_Tx_PORT GPIO_PRT1
#define Button1_Rx0_PORT GPIO_PRT8
#define Button1_Tx_PORT GPIO_PRT1
#define LinearSlider0_Sns0_PORT GPIO_PRT8
#define LinearSlider0_Sns1_PORT GPIO_PRT8
#define LinearSlider0_Sns2_PORT GPIO_PRT8
#define LinearSlider0_Sns3_PORT GPIO_PRT8
#define LinearSlider0_Sns4_PORT GPIO_PRT8
#define Cmod_PIN 7u
#define CintA_PIN 1u
#define CintB_PIN 2u
#define Button0_Rx0_PIN 1u
#define Button0_Tx_PIN 0u
#define Button1_Rx0_PIN 2u
#define Button1_Tx_PIN 0u
#define LinearSlider0_Sns0_PIN 3u
#define LinearSlider0_Sns1_PIN 4u
#define LinearSlider0_Sns2_PIN 5u
#define LinearSlider0_Sns3_PIN 6u
#define LinearSlider0_Sns4_PIN 7u
#define Cmod_PORT_NUM 7u
#define CintA_PORT_NUM 7u
#define CintB_PORT_NUM 7u
#define CYBSP_CSD_HW CSD0
#define CYBSP_CSD_IRQ csd_interrupt_IRQn
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BLE_obj;
#endif //defined (CY_USING_HAL)
extern cy_stc_csd_context_t cy_csd_0_context;
void init_cycfg_peripherals(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_PERIPHERALS_H */

115
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -4,13 +4,13 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5972
* mtb-pdl-cat1 2.4.0.13881
* personalities 6.0.0.0
* udd 3.0.0.1974
* Tools Package 2.4.0.5721
* mtb-pdl-cat1 3.0.0.10651
* personalities 5.0.0.0
* udd 3.0.0.1377
*
********************************************************************************
* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
@ -29,74 +29,6 @@
#include "cycfg_pins.h"
#define CYBSP_SDHC_IO1_PORT GPIO_PRT13
#define CYBSP_SDHC_IO1_PORT_NUM 13U
#define CYBSP_SDHC_IO1_PIN 1U
#ifndef ioss_0_port_13_pin_1_HSIOM
#define ioss_0_port_13_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SDHC_IO1_HSIOM ioss_0_port_13_pin_1_HSIOM
#define CYBSP_SDHC_IO2_PORT GPIO_PRT13
#define CYBSP_SDHC_IO2_PORT_NUM 13U
#define CYBSP_SDHC_IO2_PIN 2U
#ifndef ioss_0_port_13_pin_2_HSIOM
#define ioss_0_port_13_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SDHC_IO2_HSIOM ioss_0_port_13_pin_2_HSIOM
const cy_stc_gpio_pin_config_t CYBSP_SDHC_IO1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
.hsiom = CYBSP_SDHC_IO1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SDHC_IO1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SDHC_IO1_PORT_NUM,
.channel_num = CYBSP_SDHC_IO1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SDHC_IO2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
.hsiom = CYBSP_SDHC_IO2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SDHC_IO2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SDHC_IO2_PORT_NUM,
.channel_num = CYBSP_SDHC_IO2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
{
.outVal = 1,
@ -145,11 +77,11 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
.channel_num = CYBSP_WCO_OUT_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_CSD_RX_HSIOM,
.hsiom = CYBSP_CSD_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
@ -162,11 +94,11 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_RX_obj =
const cyhal_resource_inst_t CYBSP_CSD_TX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_RX_PORT_NUM,
.channel_num = CYBSP_CSD_RX_PIN,
.block_num = CYBSP_CSD_TX_PORT_NUM,
.channel_num = CYBSP_CSD_TX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
@ -482,31 +414,6 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t SMART_IO_OUTPUT_PIN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = P9_1_TCPWM1_LINE_COMPL20,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t SMART_IO_OUTPUT_PIN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = 9U,
.channel_num = 1U,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void)
{
@ -521,7 +428,7 @@ void init_cycfg_pins(void)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);

851
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h Normal file
View File

@ -0,0 +1,851 @@
/*******************************************************************************
* File Name: cycfg_pins.h
*
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5721
* mtb-pdl-cat1 3.0.0.10651
* personalities 5.0.0.0
* udd 3.0.0.1377
*
********************************************************************************
* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_PINS_H)
#define CYCFG_PINS_H
#include "cycfg_notices.h"
#include "cy_gpio.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cycfg_routing.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define CYBSP_WCO_IN_ENABLED 1U
#define CYBSP_WCO_IN_PORT GPIO_PRT0
#define CYBSP_WCO_IN_PORT_NUM 0U
#define CYBSP_WCO_IN_PIN 0U
#define CYBSP_WCO_IN_NUM 0U
#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_0_HSIOM
#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN P0_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_ENABLED 1U
#define CYBSP_WCO_OUT_PORT GPIO_PRT0
#define CYBSP_WCO_OUT_PORT_NUM 0U
#define CYBSP_WCO_OUT_PIN 1U
#define CYBSP_WCO_OUT_NUM 1U
#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_1_HSIOM
#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT P0_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_D7 (P0_2)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_LED_RGB_RED (P0_3)
#define CYBSP_USER_LED3 CYBSP_LED_RGB_RED
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SW2 (P0_4)
#define CYBSP_USER_BTN CYBSP_SW2
#define CYBSP_USER_BTN1 CYBSP_SW2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A0 (P10_0)
#define CYBSP_J2_1 CYBSP_A0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A1 (P10_1)
#define CYBSP_J2_3 CYBSP_A1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A2 (P10_2)
#define CYBSP_J2_5 CYBSP_A2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A3 (P10_3)
#define CYBSP_J2_7 CYBSP_A3
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A4 (P10_4)
#define CYBSP_J2_9 CYBSP_A4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A5 (P10_5)
#define CYBSP_J2_11 CYBSP_A5
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A6 (P10_6)
#define CYBSP_J2_13 CYBSP_A6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_FRAM_SSEL (P11_0)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_LED_RGB_BLUE (P11_1)
#define CYBSP_USER_LED5 CYBSP_LED_RGB_BLUE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SS (P11_2)
#define CYBSP_QSPI_FLASH_SSEL CYBSP_QSPI_SS
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D3 (P11_3)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D2 (P11_4)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D1 (P11_5)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D0 (P11_6)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK (P11_7)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SPI_MOSI (P12_0)
#define CYBSP_D11 CYBSP_SPI_MOSI
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SPI_MISO (P12_1)
#define CYBSP_D12 CYBSP_SPI_MISO
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SPI_CLK (P12_2)
#define CYBSP_D13 CYBSP_SPI_CLK
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SPI_CS (P12_3)
#define CYBSP_D10 CYBSP_SPI_CS
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_D8 (P13_0)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_D9 (P13_1)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_J2_19 (P13_6)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_LED9 (P13_7)
#define CYBSP_USER_LED2 CYBSP_LED9
#define CYBSP_J2_20 CYBSP_LED9
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_TX_ENABLED 1U
#define CYBSP_CS_TX_ENABLED CYBSP_CSD_TX_ENABLED
#define CYBSP_CSD_TX_PORT GPIO_PRT1
#define CYBSP_CS_TX_PORT CYBSP_CSD_TX_PORT
#define CYBSP_CSD_TX_PORT_NUM 1U
#define CYBSP_CS_TX_PORT_NUM CYBSP_CSD_TX_PORT_NUM
#define CYBSP_CSD_TX_PIN 0U
#define CYBSP_CS_TX_PIN CYBSP_CSD_TX_PIN
#define CYBSP_CSD_TX_NUM 0U
#define CYBSP_CS_TX_NUM CYBSP_CSD_TX_NUM
#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_TX_DRIVEMODE CYBSP_CSD_TX_DRIVEMODE
#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
#define CYBSP_CS_TX_INIT_DRIVESTATE CYBSP_CSD_TX_INIT_DRIVESTATE
#ifndef ioss_0_port_1_pin_0_HSIOM
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
#define CYBSP_CS_TX_HSIOM CYBSP_CSD_TX_HSIOM
#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_CS_TX_IRQ CYBSP_CSD_TX_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_PORT_PIN P1_0
#define CYBSP_CS_TX_HAL_PORT_PIN CYBSP_CSD_TX_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX P1_0
#define CYBSP_CS_TX CYBSP_CSD_TX
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_TX_HAL_IRQ CYBSP_CSD_TX_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_TX_HAL_DIR CYBSP_CSD_TX_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_TX_HAL_DRIVEMODE CYBSP_CSD_TX_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_LED_RGB_GREEN (P1_1)
#define CYBSP_USER_LED4 CYBSP_LED_RGB_GREEN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_LED8 (P1_5)
#define CYBSP_USER_LED CYBSP_LED8
#define CYBSP_USER_LED1 CYBSP_LED8
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_DEBUG_UART_RX (P5_0)
#define CYBSP_D0 CYBSP_DEBUG_UART_RX
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_DEBUG_UART_TX (P5_1)
#define CYBSP_D1 CYBSP_DEBUG_UART_TX
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_D2 (P5_2)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_D3 (P5_3)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_D4 (P5_4)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_D5 (P5_5)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_D6 (P5_6)
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2C_SCL (P6_0)
#define CYBSP_D15 CYBSP_I2C_SCL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2C_SDA (P6_1)
#define CYBSP_D14 CYBSP_I2C_SDA
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A7 (P6_2)
#define CYBSP_J2_15 CYBSP_A7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_J2_17 (P6_3)
#endif //defined (CY_USING_HAL)
#define CYBSP_SWO_ENABLED 1U
#define CYBSP_SWO_PORT GPIO_PRT6
#define CYBSP_SWO_PORT_NUM 6U
#define CYBSP_SWO_PIN 4U
#define CYBSP_SWO_NUM 4U
#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_SWO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_4_HSIOM
#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_PORT_PIN P6_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO P6_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_SWDIO_ENABLED 1U
#define CYBSP_SWDIO_PORT GPIO_PRT6
#define CYBSP_SWDIO_PORT_NUM 6U
#define CYBSP_SWDIO_PIN 6U
#define CYBSP_SWDIO_NUM 6U
#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_SWDIO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_6_HSIOM
#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO P6_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
#endif //defined (CY_USING_HAL)
#define CYBSP_SWDCK_ENABLED 1U
#define CYBSP_SWDCK_PORT GPIO_PRT6
#define CYBSP_SWDCK_PORT_NUM 6U
#define CYBSP_SWDCK_PIN 7U
#define CYBSP_SWDCK_NUM 7U
#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
#define CYBSP_SWDCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_7_HSIOM
#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK P6_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
#endif //defined (CY_USING_HAL)
#define CYBSP_CINA_ENABLED 1U
#define CYBSP_CINA_PORT GPIO_PRT7
#define CYBSP_CINA_PORT_NUM 7U
#define CYBSP_CINA_PIN 1U
#define CYBSP_CINA_NUM 1U
#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CINA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_1_HSIOM
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_PORT_PIN P7_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA P7_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CINB_ENABLED 1U
#define CYBSP_CINB_PORT GPIO_PRT7
#define CYBSP_CINB_PORT_NUM 7U
#define CYBSP_CINB_PIN 2U
#define CYBSP_CINB_NUM 2U
#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CINB_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_2_HSIOM
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_PORT_PIN P7_2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB P7_2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CMOD_ENABLED 1U
#define CYBSP_CMOD_PORT GPIO_PRT7
#define CYBSP_CMOD_PORT_NUM 7U
#define CYBSP_CMOD_PIN 7U
#define CYBSP_CMOD_NUM 7U
#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CMOD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_7_HSIOM
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_PORT_PIN P7_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD P7_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_ENABLED 1U
#define CYBSP_CS_BTN0_ENABLED CYBSP_CSD_BTN0_ENABLED
#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
#define CYBSP_CS_BTN0_PORT CYBSP_CSD_BTN0_PORT
#define CYBSP_CSD_BTN0_PORT_NUM 8U
#define CYBSP_CS_BTN0_PORT_NUM CYBSP_CSD_BTN0_PORT_NUM
#define CYBSP_CSD_BTN0_PIN 1U
#define CYBSP_CS_BTN0_PIN CYBSP_CSD_BTN0_PIN
#define CYBSP_CSD_BTN0_NUM 1U
#define CYBSP_CS_BTN0_NUM CYBSP_CSD_BTN0_NUM
#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_BTN0_DRIVEMODE CYBSP_CSD_BTN0_DRIVEMODE
#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
#define CYBSP_CS_BTN0_INIT_DRIVESTATE CYBSP_CSD_BTN0_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_1_HSIOM
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
#define CYBSP_CS_BTN0_HSIOM CYBSP_CSD_BTN0_HSIOM
#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CS_BTN0_IRQ CYBSP_CSD_BTN0_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
#define CYBSP_CS_BTN0_HAL_PORT_PIN CYBSP_CSD_BTN0_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0 P8_1
#define CYBSP_CS_BTN0 CYBSP_CSD_BTN0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_BTN0_HAL_IRQ CYBSP_CSD_BTN0_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_BTN0_HAL_DIR CYBSP_CSD_BTN0_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_BTN0_HAL_DRIVEMODE CYBSP_CSD_BTN0_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_ENABLED 1U
#define CYBSP_CS_BTN1_ENABLED CYBSP_CSD_BTN1_ENABLED
#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
#define CYBSP_CS_BTN1_PORT CYBSP_CSD_BTN1_PORT
#define CYBSP_CSD_BTN1_PORT_NUM 8U
#define CYBSP_CS_BTN1_PORT_NUM CYBSP_CSD_BTN1_PORT_NUM
#define CYBSP_CSD_BTN1_PIN 2U
#define CYBSP_CS_BTN1_PIN CYBSP_CSD_BTN1_PIN
#define CYBSP_CSD_BTN1_NUM 2U
#define CYBSP_CS_BTN1_NUM CYBSP_CSD_BTN1_NUM
#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_BTN1_DRIVEMODE CYBSP_CSD_BTN1_DRIVEMODE
#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
#define CYBSP_CS_BTN1_INIT_DRIVESTATE CYBSP_CSD_BTN1_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_2_HSIOM
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
#define CYBSP_CS_BTN1_HSIOM CYBSP_CSD_BTN1_HSIOM
#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CS_BTN1_IRQ CYBSP_CSD_BTN1_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
#define CYBSP_CS_BTN1_HAL_PORT_PIN CYBSP_CSD_BTN1_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1 P8_2
#define CYBSP_CS_BTN1 CYBSP_CSD_BTN1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_BTN1_HAL_IRQ CYBSP_CSD_BTN1_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_BTN1_HAL_DIR CYBSP_CSD_BTN1_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_BTN1_HAL_DRIVEMODE CYBSP_CSD_BTN1_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_ENABLED 1U
#define CYBSP_CS_SLD0_ENABLED CYBSP_CSD_SLD0_ENABLED
#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
#define CYBSP_CS_SLD0_PORT CYBSP_CSD_SLD0_PORT
#define CYBSP_CSD_SLD0_PORT_NUM 8U
#define CYBSP_CS_SLD0_PORT_NUM CYBSP_CSD_SLD0_PORT_NUM
#define CYBSP_CSD_SLD0_PIN 3U
#define CYBSP_CS_SLD0_PIN CYBSP_CSD_SLD0_PIN
#define CYBSP_CSD_SLD0_NUM 3U
#define CYBSP_CS_SLD0_NUM CYBSP_CSD_SLD0_NUM
#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_SLD0_DRIVEMODE CYBSP_CSD_SLD0_DRIVEMODE
#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
#define CYBSP_CS_SLD0_INIT_DRIVESTATE CYBSP_CSD_SLD0_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_3_HSIOM
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
#define CYBSP_CS_SLD0_HSIOM CYBSP_CSD_SLD0_HSIOM
#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CS_SLD0_IRQ CYBSP_CSD_SLD0_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
#define CYBSP_CS_SLD0_HAL_PORT_PIN CYBSP_CSD_SLD0_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0 P8_3
#define CYBSP_CS_SLD0 CYBSP_CSD_SLD0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_SLD0_HAL_IRQ CYBSP_CSD_SLD0_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_SLD0_HAL_DIR CYBSP_CSD_SLD0_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_SLD0_HAL_DRIVEMODE CYBSP_CSD_SLD0_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_ENABLED 1U
#define CYBSP_CS_SLD1_ENABLED CYBSP_CSD_SLD1_ENABLED
#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
#define CYBSP_CS_SLD1_PORT CYBSP_CSD_SLD1_PORT
#define CYBSP_CSD_SLD1_PORT_NUM 8U
#define CYBSP_CS_SLD1_PORT_NUM CYBSP_CSD_SLD1_PORT_NUM
#define CYBSP_CSD_SLD1_PIN 4U
#define CYBSP_CS_SLD1_PIN CYBSP_CSD_SLD1_PIN
#define CYBSP_CSD_SLD1_NUM 4U
#define CYBSP_CS_SLD1_NUM CYBSP_CSD_SLD1_NUM
#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_SLD1_DRIVEMODE CYBSP_CSD_SLD1_DRIVEMODE
#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
#define CYBSP_CS_SLD1_INIT_DRIVESTATE CYBSP_CSD_SLD1_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_4_HSIOM
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
#define CYBSP_CS_SLD1_HSIOM CYBSP_CSD_SLD1_HSIOM
#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CS_SLD1_IRQ CYBSP_CSD_SLD1_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
#define CYBSP_CS_SLD1_HAL_PORT_PIN CYBSP_CSD_SLD1_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1 P8_4
#define CYBSP_CS_SLD1 CYBSP_CSD_SLD1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_SLD1_HAL_IRQ CYBSP_CSD_SLD1_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_SLD1_HAL_DIR CYBSP_CSD_SLD1_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_SLD1_HAL_DRIVEMODE CYBSP_CSD_SLD1_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_ENABLED 1U
#define CYBSP_CS_SLD2_ENABLED CYBSP_CSD_SLD2_ENABLED
#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
#define CYBSP_CS_SLD2_PORT CYBSP_CSD_SLD2_PORT
#define CYBSP_CSD_SLD2_PORT_NUM 8U
#define CYBSP_CS_SLD2_PORT_NUM CYBSP_CSD_SLD2_PORT_NUM
#define CYBSP_CSD_SLD2_PIN 5U
#define CYBSP_CS_SLD2_PIN CYBSP_CSD_SLD2_PIN
#define CYBSP_CSD_SLD2_NUM 5U
#define CYBSP_CS_SLD2_NUM CYBSP_CSD_SLD2_NUM
#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_SLD2_DRIVEMODE CYBSP_CSD_SLD2_DRIVEMODE
#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
#define CYBSP_CS_SLD2_INIT_DRIVESTATE CYBSP_CSD_SLD2_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_5_HSIOM
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
#define CYBSP_CS_SLD2_HSIOM CYBSP_CSD_SLD2_HSIOM
#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CS_SLD2_IRQ CYBSP_CSD_SLD2_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
#define CYBSP_CS_SLD2_HAL_PORT_PIN CYBSP_CSD_SLD2_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2 P8_5
#define CYBSP_CS_SLD2 CYBSP_CSD_SLD2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_SLD2_HAL_IRQ CYBSP_CSD_SLD2_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_SLD2_HAL_DIR CYBSP_CSD_SLD2_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_SLD2_HAL_DRIVEMODE CYBSP_CSD_SLD2_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_ENABLED 1U
#define CYBSP_CS_SLD3_ENABLED CYBSP_CSD_SLD3_ENABLED
#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
#define CYBSP_CS_SLD3_PORT CYBSP_CSD_SLD3_PORT
#define CYBSP_CSD_SLD3_PORT_NUM 8U
#define CYBSP_CS_SLD3_PORT_NUM CYBSP_CSD_SLD3_PORT_NUM
#define CYBSP_CSD_SLD3_PIN 6U
#define CYBSP_CS_SLD3_PIN CYBSP_CSD_SLD3_PIN
#define CYBSP_CSD_SLD3_NUM 6U
#define CYBSP_CS_SLD3_NUM CYBSP_CSD_SLD3_NUM
#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_SLD3_DRIVEMODE CYBSP_CSD_SLD3_DRIVEMODE
#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
#define CYBSP_CS_SLD3_INIT_DRIVESTATE CYBSP_CSD_SLD3_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_6_HSIOM
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
#define CYBSP_CS_SLD3_HSIOM CYBSP_CSD_SLD3_HSIOM
#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CS_SLD3_IRQ CYBSP_CSD_SLD3_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
#define CYBSP_CS_SLD3_HAL_PORT_PIN CYBSP_CSD_SLD3_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3 P8_6
#define CYBSP_CS_SLD3 CYBSP_CSD_SLD3
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_SLD3_HAL_IRQ CYBSP_CSD_SLD3_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_SLD3_HAL_DIR CYBSP_CSD_SLD3_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_SLD3_HAL_DRIVEMODE CYBSP_CSD_SLD3_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_ENABLED 1U
#define CYBSP_CS_SLD4_ENABLED CYBSP_CSD_SLD4_ENABLED
#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
#define CYBSP_CS_SLD4_PORT CYBSP_CSD_SLD4_PORT
#define CYBSP_CSD_SLD4_PORT_NUM 8U
#define CYBSP_CS_SLD4_PORT_NUM CYBSP_CSD_SLD4_PORT_NUM
#define CYBSP_CSD_SLD4_PIN 7U
#define CYBSP_CS_SLD4_PIN CYBSP_CSD_SLD4_PIN
#define CYBSP_CSD_SLD4_NUM 7U
#define CYBSP_CS_SLD4_NUM CYBSP_CSD_SLD4_NUM
#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CS_SLD4_DRIVEMODE CYBSP_CSD_SLD4_DRIVEMODE
#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
#define CYBSP_CS_SLD4_INIT_DRIVESTATE CYBSP_CSD_SLD4_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_7_HSIOM
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
#define CYBSP_CS_SLD4_HSIOM CYBSP_CSD_SLD4_HSIOM
#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CS_SLD4_IRQ CYBSP_CSD_SLD4_IRQ
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
#define CYBSP_CS_SLD4_HAL_PORT_PIN CYBSP_CSD_SLD4_HAL_PORT_PIN
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4 P8_7
#define CYBSP_CS_SLD4 CYBSP_CSD_SLD4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_CS_SLD4_HAL_IRQ CYBSP_CSD_SLD4_HAL_IRQ
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_CS_SLD4_HAL_DIR CYBSP_CSD_SLD4_HAL_DIR
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_CS_SLD4_HAL_DRIVEMODE CYBSP_CSD_SLD4_HAL_DRIVEMODE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A8 (P9_0)
#define CYBSP_J2_2 CYBSP_A8
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A9 (P9_1)
#define CYBSP_J2_4 CYBSP_A9
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A10 (P9_2)
#define CYBSP_J2_6 CYBSP_A10
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A11 (P9_3)
#define CYBSP_J2_8 CYBSP_A11
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A12 (P9_4)
#define CYBSP_J2_10 CYBSP_A12
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A13 (P9_5)
#define CYBSP_J2_12 CYBSP_A13
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_A15 (P9_6)
#define CYBSP_J2_16 CYBSP_A15
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_J2_18 (P9_7)
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
#define CYBSP_CS_TX_config CYBSP_CSD_TX_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
#define CYBSP_CS_TX_obj CYBSP_CSD_TX_obj
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWO_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CINA_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CINB_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
#define CYBSP_CS_BTN0_config CYBSP_CSD_BTN0_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
#define CYBSP_CS_BTN0_obj CYBSP_CSD_BTN0_obj
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
#define CYBSP_CS_BTN1_config CYBSP_CSD_BTN1_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
#define CYBSP_CS_BTN1_obj CYBSP_CSD_BTN1_obj
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
#define CYBSP_CS_SLD0_config CYBSP_CSD_SLD0_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
#define CYBSP_CS_SLD0_obj CYBSP_CSD_SLD0_obj
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
#define CYBSP_CS_SLD1_config CYBSP_CSD_SLD1_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
#define CYBSP_CS_SLD1_obj CYBSP_CSD_SLD1_obj
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
#define CYBSP_CS_SLD2_config CYBSP_CSD_SLD2_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
#define CYBSP_CS_SLD2_obj CYBSP_CSD_SLD2_obj
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
#define CYBSP_CS_SLD3_config CYBSP_CSD_SLD3_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
#define CYBSP_CS_SLD3_obj CYBSP_CSD_SLD3_obj
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
#define CYBSP_CS_SLD4_config CYBSP_CSD_SLD4_config
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
#define CYBSP_CS_SLD4_obj CYBSP_CSD_SLD4_obj
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_PINS_H */

0
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

0
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
View File

44
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c Normal file
View File

@ -0,0 +1,44 @@
/*******************************************************************************
* File Name: cycfg_routing.c
*
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5721
* mtb-pdl-cat1 3.0.0.10651
* personalities 5.0.0.0
* udd 3.0.0.1377
*
********************************************************************************
* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_routing.h"
#include "cy_device_headers.h"
void init_cycfg_routing(void)
{
HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
}

10
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -4,13 +4,13 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5972
* mtb-pdl-cat1 2.4.0.13881
* personalities 6.0.0.0
* udd 3.0.0.1974
* Tools Package 2.4.0.5721
* mtb-pdl-cat1 3.0.0.10651
* personalities 5.0.0.0
* udd 3.0.0.1377
*
********************************************************************************
* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*

58
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -4,13 +4,13 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5972
* mtb-pdl-cat1 2.4.0.14850
* personalities 6.0.0.0
* udd 3.0.0.2024
* Tools Package 2.4.0.5721
* mtb-pdl-cat1 3.0.0.10651
* personalities 5.0.0.0
* udd 3.0.0.1377
*
********************************************************************************
* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
@ -40,7 +40,7 @@
#define CY_CFG_SYSCLK_CLKALTSYSTICK_FREQUENCY 32768
#define CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS ((0)/1000000.0)*32768
#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF
#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_WCO
#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
#define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0
#define CY_CFG_SYSCLK_FLL_ENABLED 1
@ -78,9 +78,6 @@
#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM 0UL
#define CY_CFG_SYSCLK_CLKPATH5_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM 0UL
#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0
#define CY_CFG_SYSCLK_PLL0_ENABLED 1
@ -168,14 +165,6 @@
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 5U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if (!defined(CY_DEVICE_SECURE))
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
@ -671,7 +660,7 @@ __STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
#if (!defined(CY_DEVICE_SECURE))
__STATIC_INLINE void Cy_SysClk_ClkBakInit()
{
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
}
#endif //(!defined(CY_DEVICE_SECURE))
#if (!defined(CY_DEVICE_SECURE))
@ -745,12 +734,6 @@ __STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
}
#endif //(!defined(CY_DEVICE_SECURE))
#if (!defined(CY_DEVICE_SECURE))
__STATIC_INLINE void Cy_SysClk_ClkPath5Init()
{
Cy_SysClk_ClkPathSetSource(5U, CY_CFG_SYSCLK_CLKPATH5_SOURCE);
}
#endif //(!defined(CY_DEVICE_SECURE))
#if (!defined(CY_DEVICE_SECURE))
__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
{
@ -800,24 +783,11 @@ __STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
__STATIC_INLINE void init_cycfg_power(void)
{
/* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
#if CY_CFG_SYSCLK_WCO_ENABLED
uint32_t wcoTrim = Cy_SysLib_GetWcoTrim();
if (CY_SYSLIB_SUCCESS != Cy_SysLib_ResetBackupDomain())
{
Cy_SysLib_DelayUs(1U);
if (CY_SYSLIB_SUCCESS != Cy_SysLib_GetResetStatus())
{
cycfg_ClockStartupError(CY_CFG_PWR_BKP_ERROR);
}
}
Cy_SysLib_SetWcoTrim(wcoTrim);
#else /* CY_CFG_SYSCLK_WCO_ENABLED */
(void) Cy_SysLib_ResetBackupDomain();
#endif /* CY_CFG_SYSCLK_WCO_ENABLED */
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
@ -1205,8 +1175,4 @@ void init_cycfg_system(void)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj);
#endif //defined (CY_USING_HAL)
}

15
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -4,13 +4,13 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* Tools Package 2.4.0.5972
* mtb-pdl-cat1 2.4.0.13881
* personalities 6.0.0.0
* udd 3.0.0.1974
* Tools Package 2.4.0.5721
* mtb-pdl-cat1 3.0.0.10651
* personalities 5.0.0.0
* udd 3.0.0.1377
*
********************************************************************************
* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
@ -34,6 +34,7 @@
#include "cy_sysclk.h"
#include "cy_pra.h"
#include "cy_pra_cfg.h"
#include "cy_ble_clk.h"
#include "cy_systick.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
@ -64,7 +65,6 @@ extern "C" {
#define srss_0_clock_0_pathmux_2_ENABLED 1U
#define srss_0_clock_0_pathmux_3_ENABLED 1U
#define srss_0_clock_0_pathmux_4_ENABLED 1U
#define srss_0_clock_0_pathmux_5_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
#define srss_0_clock_0_pll_0_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
@ -102,9 +102,6 @@ extern "C" {
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_system(void);

0
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
View File

4
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list Normal file
View File

@ -0,0 +1,4 @@
[Device=CY8C6347BZI-BLD53]
[Blocks]
# Nothing needs to be reserved for this device

0
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
View File

6
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
View File

@ -29,7 +29,7 @@
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>2</SlaveSlot>
@ -43,7 +43,7 @@
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>3</SlaveSlot>
@ -57,7 +57,7 @@
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
</SlotConfigs>
</Configuration>

647
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus Normal file
View File

@ -0,0 +1,647 @@
<?xml version="1.0" encoding="UTF-8"?>
<Design version="12" xmlns="http://cypress.com/xsd/cydesignfile_v3">
<ToolInfo version="2.4.0.5721"/>
<Devices>
<Device mpn="CY8C6347BZI-BLD53">
<BlockConfig>
<Block location="bless[0]">
<Alias value="CYBSP_BLE"/>
<Personality template="mxs40ble" version="1.1">
<Param id="BleSharing" value="0"/>
<Param id="ExtPaLnaEnable" value="false"/>
</Personality>
</Block>
<Block location="cpuss[0].dap[0]">
<Personality template="mxs40dap" version="1.0">
<Param id="dbgMode" value="SWD"/>
<Param id="traceEnable" value="false"/>
</Personality>
</Block>
<Block location="csd[0].csd[0]">
<Alias value="CYBSP_CSD"/>
<Personality template="mxs40csd" version="2.0">
<Param id="CapSenseEnable" value="true"/>
<Param id="CapSenseCore" value="4"/>
<Param id="SensorCount" value="12"/>
<Param id="CapacitorCount" value="3"/>
<Param id="SensorName0" value="Cmod"/>
<Param id="SensorName1" value="CintA"/>
<Param id="SensorName2" value="CintB"/>
<Param id="SensorName3" value="Button0_Rx0"/>
<Param id="SensorName4" value="Button0_Tx"/>
<Param id="SensorName5" value="Button1_Rx0"/>
<Param id="SensorName6" value="Button1_Tx"/>
<Param id="SensorName7" value="LinearSlider0_Sns0"/>
<Param id="SensorName8" value="LinearSlider0_Sns1"/>
<Param id="SensorName9" value="LinearSlider0_Sns2"/>
<Param id="SensorName10" value="LinearSlider0_Sns3"/>
<Param id="SensorName11" value="LinearSlider0_Sns4"/>
<Param id="CapSenseConfigurator" value="0"/>
<Param id="CapSenseTuner" value="0"/>
<Param id="CsdAdcEnable" value="false"/>
<Param id="numChannels" value="1"/>
<Param id="resolution" value="CY_CSDADC_RESOLUTION_10BIT"/>
<Param id="range" value="CY_CSDADC_RANGE_VDDA"/>
<Param id="acqTime" value="10"/>
<Param id="autoCalibrInterval" value="30"/>
<Param id="vref" value="-1"/>
<Param id="operClkDivider" value="1"/>
<Param id="azTime" value="5"/>
<Param id="csdInitTime" value="25"/>
<Param id="inFlash" value="true"/>
<Param id="CsdIdacEnable" value="false"/>
<Param id="CsdIdacAselect" value="CY_CSDIDAC_GPIO"/>
<Param id="CsdIdacBselect" value="CY_CSDIDAC_DISABLED"/>
<Param id="csdIdacInitTime" value="25"/>
<Param id="idacInFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[0].pin[0]">
<Alias value="CYBSP_WCO_IN"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[0].pin[1]">
<Alias value="CYBSP_WCO_OUT"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[0].pin[2]">
<Alias value="CYBSP_D7"/>
</Block>
<Block location="ioss[0].port[0].pin[3]">
<Alias value="CYBSP_LED_RGB_RED"/>
<Alias value="CYBSP_USER_LED3"/>
</Block>
<Block location="ioss[0].port[0].pin[4]">
<Alias value="CYBSP_SW2"/>
<Alias value="CYBSP_USER_BTN"/>
<Alias value="CYBSP_USER_BTN1"/>
</Block>
<Block location="ioss[0].port[10].pin[0]">
<Alias value="CYBSP_A0"/>
<Alias value="CYBSP_J2_1"/>
</Block>
<Block location="ioss[0].port[10].pin[1]">
<Alias value="CYBSP_A1"/>
<Alias value="CYBSP_J2_3"/>
</Block>
<Block location="ioss[0].port[10].pin[2]">
<Alias value="CYBSP_A2"/>
<Alias value="CYBSP_J2_5"/>
</Block>
<Block location="ioss[0].port[10].pin[3]">
<Alias value="CYBSP_A3"/>
<Alias value="CYBSP_J2_7"/>
</Block>
<Block location="ioss[0].port[10].pin[4]">
<Alias value="CYBSP_A4"/>
<Alias value="CYBSP_J2_9"/>
</Block>
<Block location="ioss[0].port[10].pin[5]">
<Alias value="CYBSP_A5"/>
<Alias value="CYBSP_J2_11"/>
</Block>
<Block location="ioss[0].port[10].pin[6]">
<Alias value="CYBSP_A6"/>
<Alias value="CYBSP_J2_13"/>
</Block>
<Block location="ioss[0].port[11].pin[0]">
<Alias value="CYBSP_QSPI_FRAM_SSEL"/>
</Block>
<Block location="ioss[0].port[11].pin[1]">
<Alias value="CYBSP_LED_RGB_BLUE"/>
<Alias value="CYBSP_USER_LED5"/>
</Block>
<Block location="ioss[0].port[11].pin[2]">
<Alias value="CYBSP_QSPI_SS"/>
<Alias value="CYBSP_QSPI_FLASH_SSEL"/>
</Block>
<Block location="ioss[0].port[11].pin[3]">
<Alias value="CYBSP_QSPI_D3"/>
</Block>
<Block location="ioss[0].port[11].pin[4]">
<Alias value="CYBSP_QSPI_D2"/>
</Block>
<Block location="ioss[0].port[11].pin[5]">
<Alias value="CYBSP_QSPI_D1"/>
</Block>
<Block location="ioss[0].port[11].pin[6]">
<Alias value="CYBSP_QSPI_D0"/>
</Block>
<Block location="ioss[0].port[11].pin[7]">
<Alias value="CYBSP_QSPI_SCK"/>
</Block>
<Block location="ioss[0].port[12].pin[0]">
<Alias value="CYBSP_SPI_MOSI"/>
<Alias value="CYBSP_D11"/>
</Block>
<Block location="ioss[0].port[12].pin[1]">
<Alias value="CYBSP_SPI_MISO"/>
<Alias value="CYBSP_D12"/>
</Block>
<Block location="ioss[0].port[12].pin[2]">
<Alias value="CYBSP_SPI_CLK"/>
<Alias value="CYBSP_D13"/>
</Block>
<Block location="ioss[0].port[12].pin[3]">
<Alias value="CYBSP_SPI_CS"/>
<Alias value="CYBSP_D10"/>
</Block>
<Block location="ioss[0].port[13].pin[0]">
<Alias value="CYBSP_D8"/>
</Block>
<Block location="ioss[0].port[13].pin[1]">
<Alias value="CYBSP_D9"/>
</Block>
<Block location="ioss[0].port[13].pin[6]">
<Alias value="CYBSP_J2_19"/>
</Block>
<Block location="ioss[0].port[13].pin[7]">
<Alias value="CYBSP_LED9"/>
<Alias value="CYBSP_USER_LED2"/>
<Alias value="CYBSP_J2_20"/>
</Block>
<Block location="ioss[0].port[1].pin[0]">
<Alias value="CYBSP_CSD_TX"/>
<Alias value="CYBSP_CS_TX"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[1].pin[1]">
<Alias value="CYBSP_LED_RGB_GREEN"/>
<Alias value="CYBSP_USER_LED4"/>
</Block>
<Block location="ioss[0].port[1].pin[5]">
<Alias value="CYBSP_LED8"/>
<Alias value="CYBSP_USER_LED"/>
<Alias value="CYBSP_USER_LED1"/>
</Block>
<Block location="ioss[0].port[5].pin[0]">
<Alias value="CYBSP_DEBUG_UART_RX"/>
<Alias value="CYBSP_D0"/>
</Block>
<Block location="ioss[0].port[5].pin[1]">
<Alias value="CYBSP_DEBUG_UART_TX"/>
<Alias value="CYBSP_D1"/>
</Block>
<Block location="ioss[0].port[5].pin[2]">
<Alias value="CYBSP_D2"/>
</Block>
<Block location="ioss[0].port[5].pin[3]">
<Alias value="CYBSP_D3"/>
</Block>
<Block location="ioss[0].port[5].pin[4]">
<Alias value="CYBSP_D4"/>
</Block>
<Block location="ioss[0].port[5].pin[5]">
<Alias value="CYBSP_D5"/>
</Block>
<Block location="ioss[0].port[5].pin[6]">
<Alias value="CYBSP_D6"/>
</Block>
<Block location="ioss[0].port[6].pin[0]">
<Alias value="CYBSP_I2C_SCL"/>
<Alias value="CYBSP_D15"/>
</Block>
<Block location="ioss[0].port[6].pin[1]">
<Alias value="CYBSP_I2C_SDA"/>
<Alias value="CYBSP_D14"/>
</Block>
<Block location="ioss[0].port[6].pin[2]">
<Alias value="CYBSP_A7"/>
<Alias value="CYBSP_J2_15"/>
</Block>
<Block location="ioss[0].port[6].pin[3]">
<Alias value="CYBSP_J2_17"/>
</Block>
<Block location="ioss[0].port[6].pin[4]">
<Alias value="CYBSP_SWO"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[6].pin[6]">
<Alias value="CYBSP_SWDIO"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[6].pin[7]">
<Alias value="CYBSP_SWDCK"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[7].pin[1]">
<Alias value="CYBSP_CINA"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[7].pin[2]">
<Alias value="CYBSP_CINB"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[7].pin[7]">
<Alias value="CYBSP_CMOD"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[8].pin[1]">
<Alias value="CYBSP_CSD_BTN0"/>
<Alias value="CYBSP_CS_BTN0"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[8].pin[2]">
<Alias value="CYBSP_CSD_BTN1"/>
<Alias value="CYBSP_CS_BTN1"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[8].pin[3]">
<Alias value="CYBSP_CSD_SLD0"/>
<Alias value="CYBSP_CS_SLD0"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[8].pin[4]">
<Alias value="CYBSP_CSD_SLD1"/>
<Alias value="CYBSP_CS_SLD1"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[8].pin[5]">
<Alias value="CYBSP_CSD_SLD2"/>
<Alias value="CYBSP_CS_SLD2"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[8].pin[6]">
<Alias value="CYBSP_CSD_SLD3"/>
<Alias value="CYBSP_CS_SLD3"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[8].pin[7]">
<Alias value="CYBSP_CSD_SLD4"/>
<Alias value="CYBSP_CS_SLD4"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[9].pin[0]">
<Alias value="CYBSP_A8"/>
<Alias value="CYBSP_J2_2"/>
</Block>
<Block location="ioss[0].port[9].pin[1]">
<Alias value="CYBSP_A9"/>
<Alias value="CYBSP_J2_4"/>
</Block>
<Block location="ioss[0].port[9].pin[2]">
<Alias value="CYBSP_A10"/>
<Alias value="CYBSP_J2_6"/>
</Block>
<Block location="ioss[0].port[9].pin[3]">
<Alias value="CYBSP_A11"/>
<Alias value="CYBSP_J2_8"/>
</Block>
<Block location="ioss[0].port[9].pin[4]">
<Alias value="CYBSP_A12"/>
<Alias value="CYBSP_J2_10"/>
</Block>
<Block location="ioss[0].port[9].pin[5]">
<Alias value="CYBSP_A13"/>
<Alias value="CYBSP_J2_12"/>
</Block>
<Block location="ioss[0].port[9].pin[6]">
<Alias value="CYBSP_A15"/>
<Alias value="CYBSP_J2_16"/>
</Block>
<Block location="ioss[0].port[9].pin[7]">
<Alias value="CYBSP_J2_18"/>
</Block>
<Block location="peri[0].div_8[0]">
<Alias value="CYBSP_CSD_CLK_DIV"/>
<Alias value="CYBSP_CS_CLK_DIV"/>
<Personality template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="256"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="srss[0].clock[0]">
<Personality template="mxs40sysclocks" version="1.2"/>
</Block>
<Block location="srss[0].clock[0].altsystickclk[0]">
<Personality template="mxs40altsystick" version="1.0">
<Param id="sourceClock" value="lfclk"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].bakclk[0]">
<Personality template="mxs40bakclk" version="1.0">
<Param id="sourceClock" value="wco"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].fastclk[0]">
<Personality template="mxs40fastclk" version="1.0">
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].fll[0]">
<Personality template="mxs40fll" version="2.0">
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="100.000"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[0]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].ilo[0]">
<Personality template="mxs40ilo" version="1.0">
<Param id="hibernate" value="true"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].imo[0]">
<Personality template="mxs40imo" version="1.0">
<Param id="trim" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].lfclk[0]">
<Personality template="mxs40lfclk" version="1.1">
<Param id="sourceClock" value="wco"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pathmux[0]">
<Personality template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pathmux[1]">
<Personality template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pathmux[2]">
<Personality template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pathmux[3]">
<Personality template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pathmux[4]">
<Personality template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].periclk[0]">
<Personality template="mxs40periclk" version="1.0">
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pll[0]">
<Personality template="mxs40pll" version="2.0">
<Param id="lowFrequencyMode" value="false"/>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="48.000"/>
<Param id="optimization" value="MinPower"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].slowclk[0]">
<Personality template="mxs40slowclk" version="1.0">
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].timerclk[0]">
<Personality template="mxs40timerclk" version="1.0">
<Param id="sourceClock" value="imo"/>
<Param id="timerDivider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].wco[0]">
<Personality template="mxs40wco" version="1.0">
<Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
<Param id="clockLostDetection" value="false"/>
<Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
<Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
<Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
<Param id="accuracyPpm" value="150"/>
</Personality>
</Block>
<Block location="srss[0].power[0]">
<Personality template="mxs40power" version="1.3">
<Param id="pwrMode" value="LDO_1_1"/>
<Param id="actPwrMode" value="LP"/>
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
<Param id="pmicEnable" value="false"/>
<Param id="backupSrc" value="VDDD"/>
<Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
<Param id="deepsleepLatency" value="0"/>
<Param id="vddaMv" value="3300"/>
<Param id="vdddMv" value="3300"/>
<Param id="vBackupMv" value="3300"/>
<Param id="vddNsMv" value="3300"/>
<Param id="vddio0Mv" value="3300"/>
<Param id="vddio1Mv" value="3300"/>
</Personality>
</Block>
</BlockConfig>
<Netlist>
<Net>
<Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
<Port name="ioss[0].port[6].pin[7].digital_in[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swdio_tms[0]"/>
<Port name="ioss[0].port[6].pin[6].digital_inout[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
<Port name="ioss[0].port[6].pin[4].digital_out[0]"/>
</Net>
<Net>
<Port name="csd[0].csd[0].clock[0]"/>
<Port name="peri[0].div_8[0].clk[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[0].pin[0].analog[0]"/>
<Port name="srss[0].clock[0].wco[0].wco_in[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[0].pin[1].analog[0]"/>
<Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
</Net>
<Mux name="sense" location="csd[0].csd[0]">
<Arm>
<Port name="ioss[0].port[7].pin[7].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[7].pin[1].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[7].pin[2].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[1].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[1].pin[0].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[2].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[1].pin[0].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[3].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[4].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[5].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[6].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[7].analog[0]"/>
</Arm>
</Mux>
</Netlist>
</Device>
</Devices>
<ConfiguratorData/>
</Design>

544
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct
View File

@ -1,272 +1,272 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file cy8c6xxa_cm0plus.sct
;* \version 2.91
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at
;*
;* http://www.apache.org/licenses/LICENSE-2.0
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM
#define RAM_START 0x08000000
#define RAM_SIZE 0x00002000
; Flash
#define FLASH_START 0x10000000
#define FLASH_SIZE 0x00002000
; The size of the stack section at the end of CM0+ SRAM
#define STACK_SIZE 0x00001000
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200
; External memory
#define XIP_START 0x18000000
#define XIP_SIZE 0x08000000
; eFuse
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
; Public RAM
; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
; This region is used to place objects that require full access from both cores.
; Uncomment the following lines, define the region size and uncomment placement of
; .cy_sharedmem section below.
; #define PUBLIC_RAM_SIZE %REGION_SIZE%
; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
; Cortex-M0+ application flash area
LR_IROM1 FLASH_START FLASH_SIZE
{
.cy_app_header +0
{
* (.cy_app_header)
}
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS RAM_START UNINIT
{
* (RESET_RAM, +FIRST)
}
RW_RAM_DATA +0
{
* (.cy_ramfunc)
* (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
; device startup.
RW_IRAM1 +0 UNINIT
{
* (.noinit)
}
; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
;RW_IRAM2 PUBLIC_RAM_START UNINIT
;{
; * (.cy_sharedmem)
;}
; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{
}
; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
.cy_em_eeprom +0
{
* (.cy_em_eeprom)
}
}
; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{
.cy_sflash_user_data +0
{
* (.cy_sflash_user_data)
}
}
; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{
.cy_sflash_nar +0
{
* (.cy_sflash_nar)
}
}
; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{
.cy_sflash_public_key +0
{
* (.cy_sflash_public_key)
}
}
; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{
.cy_toc_part2 +0
{
* (.cy_toc_part2)
}
}
; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{
.cy_rtoc_part2 +0
{
* (.cy_rtoc_part2)
}
}
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE
{
cy_xip +0
{
* (.cy_xip)
}
}
; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE
{
.cy_efuse +0
{
* (.cy_efuse)
}
}
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
#define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00200000
#define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200
/* Supervisory Flash */
#define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200
/* XIP */
#define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200
/* eFuse */
#define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1
/* [] END OF FILE */
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file cy8c6xx7_cm0plus.sct
;* \version 2.91
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at
;*
;* http://www.apache.org/licenses/LICENSE-2.0
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM
#define RAM_START 0x08000000
#define RAM_SIZE 0x00002000
; Flash
#define FLASH_START 0x10000000
#define FLASH_SIZE 0x00002000
; The size of the stack section at the end of CM0+ SRAM
#define STACK_SIZE 0x00001000
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200
; External memory
#define XIP_START 0x18000000
#define XIP_SIZE 0x08000000
; eFuse
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
; Public RAM
; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
; This region is used to place objects that require full access from both cores.
; Uncomment the following lines, define the region size and uncomment placement of
; .cy_sharedmem section below.
; #define PUBLIC_RAM_SIZE %REGION_SIZE%
; #define PUBLIC_RAM_START (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
; Cortex-M0+ application flash area
LR_IROM1 FLASH_START FLASH_SIZE
{
.cy_app_header +0
{
* (.cy_app_header)
}
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS RAM_START UNINIT
{
* (RESET_RAM, +FIRST)
}
RW_RAM_DATA +0
{
* (.cy_ramfunc)
* (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
; device startup.
RW_IRAM1 +0 UNINIT
{
* (.noinit)
}
; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
;RW_IRAM2 PUBLIC_RAM_START UNINIT
;{
; * (.cy_sharedmem)
;}
; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{
}
; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
.cy_em_eeprom +0
{
* (.cy_em_eeprom)
}
}
; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{
.cy_sflash_user_data +0
{
* (.cy_sflash_user_data)
}
}
; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{
.cy_sflash_nar +0
{
* (.cy_sflash_nar)
}
}
; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{
.cy_sflash_public_key +0
{
* (.cy_sflash_public_key)
}
}
; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{
.cy_toc_part2 +0
{
* (.cy_toc_part2)
}
}
; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{
.cy_rtoc_part2 +0
{
* (.cy_rtoc_part2)
}
}
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE
{
cy_xip +0
{
* (.cy_xip)
}
}
; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE
{
.cy_efuse +0
{
* (.cy_efuse)
}
}
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
#define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200
/* Supervisory Flash */
#define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200
/* XIP */
#define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200
/* eFuse */
#define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1
/* [] END OF FILE */

271
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.s Normal file
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;/**************************************************************************//**
; * @file startup_psoc6_01_cm0plus.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0plus Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base|
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External interrupts Description
DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0
DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1
DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2
DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3
DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4
DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5
DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6
DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7
DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8
DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9
DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10
DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11
DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12
DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13
DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14
DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15
DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16
DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17
DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18
DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19
DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20
DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21
DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22
DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23
DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24
DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25
DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26
DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27
DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28
DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29
DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30
DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
EXPORT __ramVectors
AREA RESET_RAM, READWRITE, NOINIT
__ramVectors SPACE __Vectors_Size
AREA |.text|, CODE, READONLY
; Weak function for startup customization
;
; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
; because this function is executed as the first instruction in the ResetHandler.
; The PDL is also not initialized to use the proper register offsets.
; The user of this function is responsible for initializing the PDL and resources before using them.
;
Cy_OnResetUser PROC
EXPORT Cy_OnResetUser [WEAK]
BX LR
ENDP
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
; Define strong function for startup customization
BL Cy_OnResetUser
; Disable global interrupts
CPSID I
; Copy vectors from ROM to RAM
LDR r1, =__Vectors
LDR r0, =__ramVectors
LDR r2, =__Vectors_Size
Vectors_Copy
LDR r3, [r1]
STR r3, [r0]
ADDS r0, r0, #4
ADDS r1, r1, #4
SUBS r2, r2, #1
CMP r2, #0
BNE Vectors_Copy
; Update Vector Table Offset Register. */
LDR r0, =__ramVectors
LDR r1, =0xE000ED08
STR r0, [r1]
dsb 0xF
LDR R0, =__main
BLX R0
; Should never get here
B .
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
Cy_SysLib_FaultHandler PROC
EXPORT Cy_SysLib_FaultHandler [WEAK]
B .
ENDP
HardFault_Handler PROC
EXPORT HardFault_Handler [WEAK]
movs r0, #4
mov r1, LR
tst r0, r1
beq L_MSP
mrs r0, PSP
bl L_API_call
L_MSP
mrs r0, MSP
L_API_call
bl Cy_SysLib_FaultHandler
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT Default_Handler [WEAK]
EXPORT NvicMux0_IRQHandler [WEAK]
EXPORT NvicMux1_IRQHandler [WEAK]
EXPORT NvicMux2_IRQHandler [WEAK]
EXPORT NvicMux3_IRQHandler [WEAK]
EXPORT NvicMux4_IRQHandler [WEAK]
EXPORT NvicMux5_IRQHandler [WEAK]
EXPORT NvicMux6_IRQHandler [WEAK]
EXPORT NvicMux7_IRQHandler [WEAK]
EXPORT NvicMux8_IRQHandler [WEAK]
EXPORT NvicMux9_IRQHandler [WEAK]
EXPORT NvicMux10_IRQHandler [WEAK]
EXPORT NvicMux11_IRQHandler [WEAK]
EXPORT NvicMux12_IRQHandler [WEAK]
EXPORT NvicMux13_IRQHandler [WEAK]
EXPORT NvicMux14_IRQHandler [WEAK]
EXPORT NvicMux15_IRQHandler [WEAK]
EXPORT NvicMux16_IRQHandler [WEAK]
EXPORT NvicMux17_IRQHandler [WEAK]
EXPORT NvicMux18_IRQHandler [WEAK]
EXPORT NvicMux19_IRQHandler [WEAK]
EXPORT NvicMux20_IRQHandler [WEAK]
EXPORT NvicMux21_IRQHandler [WEAK]
EXPORT NvicMux22_IRQHandler [WEAK]
EXPORT NvicMux23_IRQHandler [WEAK]
EXPORT NvicMux24_IRQHandler [WEAK]
EXPORT NvicMux25_IRQHandler [WEAK]
EXPORT NvicMux26_IRQHandler [WEAK]
EXPORT NvicMux27_IRQHandler [WEAK]
EXPORT NvicMux28_IRQHandler [WEAK]
EXPORT NvicMux29_IRQHandler [WEAK]
EXPORT NvicMux30_IRQHandler [WEAK]
EXPORT NvicMux31_IRQHandler [WEAK]
NvicMux0_IRQHandler
NvicMux1_IRQHandler
NvicMux2_IRQHandler
NvicMux3_IRQHandler
NvicMux4_IRQHandler
NvicMux5_IRQHandler
NvicMux6_IRQHandler
NvicMux7_IRQHandler
NvicMux8_IRQHandler
NvicMux9_IRQHandler
NvicMux10_IRQHandler
NvicMux11_IRQHandler
NvicMux12_IRQHandler
NvicMux13_IRQHandler
NvicMux14_IRQHandler
NvicMux15_IRQHandler
NvicMux16_IRQHandler
NvicMux17_IRQHandler
NvicMux18_IRQHandler
NvicMux19_IRQHandler
NvicMux20_IRQHandler
NvicMux21_IRQHandler
NvicMux22_IRQHandler
NvicMux23_IRQHandler
NvicMux24_IRQHandler
NvicMux25_IRQHandler
NvicMux26_IRQHandler
NvicMux27_IRQHandler
NvicMux28_IRQHandler
NvicMux29_IRQHandler
NvicMux30_IRQHandler
NvicMux31_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IMPORT __use_two_region_memory
END
; [] END OF FILE

285
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_01_cm0plus.S Normal file
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/**************************************************************************//**
* @file startup_psoc6_01_cm0plus.S
* @brief CMSIS Core Device Startup File for
* ARMCM0plus Device Series
* @version V5.00
* @date 02. March 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Address of the NMI handler */
#define CY_NMI_HANLDER_ADDR 0x0000000D
/* The CPU VTOR register */
#define CY_CPU_VTOR_ADDR 0xE000ED08
.syntax unified
.section __STACK, __stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00001000
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.equ __StackTop, . - Stack_Size
.section __HEAP, __heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000400
#endif
.globl __HeapBase
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.section __VECT, ___Vectors
.align 2
.globl ___Vectors
___Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long CY_NMI_HANLDER_ADDR /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts Description */
.long NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */
.long NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */
.long NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */
.long NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */
.long NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */
.long NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */
.long NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */
.long NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */
.long NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */
.long NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */
.long NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */
.long NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */
.long NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */
.long NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */
.long NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */
.long NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */
.long NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */
.long NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */
.long NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */
.long NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */
.long NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */
.long NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */
.long NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */
.long NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */
.long NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */
.long NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */
.long NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */
.long NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */
.long NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */
.long NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */
.long NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */
.long NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */
.equ __VectorsSize, . - ___Vectors
.section __RAMVECTORS, ___ramVectors
.align 2
.globl ___ramVectors
___ramVectors:
.space __VectorsSize
.text
.thumb_func
.align 2
/* Reset handler */
.globl Reset_Handler
Reset_Handler:
bl Cy_OnResetUser
cpsid i
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r0, =___ramVectors
ldr r1, =___Vectors
ldr r2, =__VectorsSize
bl _memcpy
ldr r0, =segment$start$__DATA
ldr r1, =segment$end$__TEXT
ldr r2, =section$start$__DATA$__zerofill
sub r2, r0
bl _memcpy
ldr r0, =section$start$__DATA$__zerofill
eor r1, r1
ldr r2, =section$end$__DATA$__zerofill
sub r2, r0
bl _memset
/* Update Vector Table Offset Register. */
ldr r0, =___ramVectors
ldr r1, =CY_CPU_VTOR_ADDR
str r0, [r1]
dsb 0xF
bl _HeapInit
#ifndef __NO_SYSTEM_INIT
bl _SystemInit
#endif
bl _main
/* Should never get here */
b .
.pool
.text
.thumb
.thumb_func
.align 2
/* Device startup customization */
.weak_definition Cy_OnResetUser
.global Cy_OnResetUser, Cy_OnResetUser
Cy_OnResetUser:
bx lr
.text
.align 1
.thumb_func
.weak_reference Default_Handler
Default_Handler:
b .
.text
.thumb_func
.align 2
.weak_definition Cy_SysLib_FaultHandler
Cy_SysLib_FaultHandler:
b .
.text
.thumb_func
.align 2
Fault_Handler:
/* Storing LR content for Creator call stack trace */
push {LR}
movs r0, #4
mov r1, LR
tst r0, r1
beq .L_MSP
mrs r0, PSP
b .L_API_call
.L_MSP:
mrs r0, MSP
.L_API_call:
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
adds r0, r0, #4
bl Cy_SysLib_FaultHandler
b .
.macro def_fault_Handler fault_handler_name
.weak_definition \fault_handler_name
.set \fault_handler_name, Fault_Handler
.endm
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak_definition \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_fault_Handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */
def_irq_handler NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */
def_irq_handler NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */
def_irq_handler NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */
def_irq_handler NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */
def_irq_handler NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */
def_irq_handler NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */
def_irq_handler NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */
def_irq_handler NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */
def_irq_handler NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */
def_irq_handler NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */
def_irq_handler NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */
def_irq_handler NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */
def_irq_handler NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */
def_irq_handler NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */
def_irq_handler NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */
def_irq_handler NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */
def_irq_handler NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */
def_irq_handler NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */
def_irq_handler NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */
def_irq_handler NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */
def_irq_handler NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */
def_irq_handler NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */
def_irq_handler NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */
def_irq_handler NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */
def_irq_handler NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */
def_irq_handler NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */
def_irq_handler NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */
def_irq_handler NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */
def_irq_handler NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */
def_irq_handler NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */
def_irq_handler NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */
.end
/* [] END OF FILE */

8
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
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@ -1,5 +1,5 @@
/***************************************************************************//**
* \file cy8c6xxa_cm0plus.ld
* \file cy8c6xx7_cm0plus.ld
* \version 2.91
*
* Linker file for the GNU C compiler.
@ -189,7 +189,7 @@ SECTIONS
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */
.copy.table :
{
. = ALIGN(4);
@ -211,7 +211,7 @@ SECTIONS
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */
.zero.table :
{
. = ALIGN(4);
@ -415,7 +415,7 @@ SECTIONS
/* The following symbols used by the cymcuelftool. */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00200000;
__cy_memory_0_length = 0x00100000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */

404
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S Normal file
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@ -0,0 +1,404 @@
/**************************************************************************//**
* @file startup_psoc6_01_cm0plus.S
* @brief CMSIS Core Device Startup File for
* ARMCM0plus Device Series
* @version V5.00
* @date 02. March 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Address of the NMI handler */
#define CY_NMI_HANLDER_ADDR 0x0000000D
/* The CPU VTOR register */
#define CY_CPU_VTOR_ADDR 0xE000ED08
/* Copy flash vectors and data section to RAM */
#define __STARTUP_COPY_MULTIPLE
/* Clear single BSS section */
#define __STARTUP_CLEAR_BSS
.syntax unified
.arch armv6-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00001000
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000400
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long CY_NMI_HANLDER_ADDR /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts Description */
.long NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */
.long NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */
.long NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */
.long NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */
.long NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */
.long NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */
.long NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */
.long NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */
.long NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */
.long NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */
.long NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */
.long NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */
.long NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */
.long NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */
.long NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */
.long NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */
.long NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */
.long NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */
.long NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */
.long NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */
.long NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */
.long NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */
.long NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */
.long NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */
.long NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */
.long NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */
.long NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */
.long NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */
.long NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */
.long NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */
.long NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */
.long NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */
.size __Vectors, . - __Vectors
.equ __VectorsSize, . - __Vectors
.section .ram_vectors
.align 2
.globl __ramVectors
__ramVectors:
.space __VectorsSize
.size __ramVectors, . - __ramVectors
.text
.thumb
.thumb_func
.align 2
/*
* Device startup customization
*
* Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
* because this function is executed as the first instruction in the ResetHandler.
* The PDL is also not initialized to use the proper register offsets.
* The user of this function is responsible for initializing the PDL and resources before using them.
*/
.weak Cy_OnResetUser
.func Cy_OnResetUser, Cy_OnResetUser
.type Cy_OnResetUser, %function
Cy_OnResetUser:
bx lr
.size Cy_OnResetUser, . - Cy_OnResetUser
.endfunc
/* Reset handler */
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
bl Cy_OnResetUser
cpsid i
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
blt .L_loop0_0_done
ldr r0, [r1, r3]
str r0, [r2, r3]
b .L_loop0_0
.L_loop0_0_done:
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .L_loop1_done
.L_loop1:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
.L_loop1_done:
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
blt .L_loop2_0_done
str r0, [r1, r2]
b .L_loop2_0
.L_loop2_0_done:
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
subs r2, r1
ble .L_loop3_done
.L_loop3:
subs r2, #4
str r0, [r1, r2]
bgt .L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
/* Update Vector Table Offset Register. */
ldr r0, =__ramVectors
ldr r1, =CY_CPU_VTOR_ADDR
str r0, [r1]
dsb 0xF
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
bl main
/* Should never get here */
b .
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
.weak Cy_SysLib_FaultHandler
.type Cy_SysLib_FaultHandler, %function
Cy_SysLib_FaultHandler:
b .
.size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
.type Fault_Handler, %function
Fault_Handler:
/* Storing LR content for Creator call stack trace */
push {LR}
movs r0, #4
mov r1, LR
tst r0, r1
beq .L_MSP
mrs r0, PSP
b .L_API_call
.L_MSP:
mrs r0, MSP
.L_API_call:
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
adds r0, r0, #4
bl Cy_SysLib_FaultHandler
b .
.size Fault_Handler, . - Fault_Handler
.macro def_fault_Handler fault_handler_name
.weak \fault_handler_name
.set \fault_handler_name, Fault_Handler
.endm
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_fault_Handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */
def_irq_handler NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */
def_irq_handler NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */
def_irq_handler NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */
def_irq_handler NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */
def_irq_handler NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */
def_irq_handler NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */
def_irq_handler NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */
def_irq_handler NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */
def_irq_handler NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */
def_irq_handler NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */
def_irq_handler NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */
def_irq_handler NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */
def_irq_handler NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */
def_irq_handler NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */
def_irq_handler NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */
def_irq_handler NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */
def_irq_handler NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */
def_irq_handler NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */
def_irq_handler NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */
def_irq_handler NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */
def_irq_handler NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */
def_irq_handler NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */
def_irq_handler NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */
def_irq_handler NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */
def_irq_handler NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */
def_irq_handler NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */
def_irq_handler NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */
def_irq_handler NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */
def_irq_handler NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */
def_irq_handler NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */
def_irq_handler NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */
.end
/* [] END OF FILE */

506
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
View File

@ -1,253 +1,253 @@
/*******************************************************************************
* \file cy8c6xxa_cm0plus.icf
* \version 2.91
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM0+ core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF;
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF;
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
/* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of
* .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__
* and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region.
*/
/*
define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
*/
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block RO {first section .intvec, readonly};
define block cy_xip { section .cy_xip };
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application */
".cy_app_header" : place at start of IROM1_region { section .cy_app_header };
place in IROM1_region { block RO };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
"cy_xip" : place at start of EROM1_region { block cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
/* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/
/*
place at start of IRAM2_region { section .cy_sharedmem };
*/
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_header,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00200000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */
/*******************************************************************************
* \file cy8c6xx7_cm0plus.icf
* \version 2.91
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM0+ core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF;
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF;
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
/* Public RAM
* This is an unprotected public RAM region, with the placed .cy_sharedmem section.
* This region is used to place objects that require full access from both cores.
* Uncomment the following lines, define region size, and uncomment the placement of
* .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__
* and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region.
*/
/*
define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
*/
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block RO {first section .intvec, readonly};
define block cy_xip { section .cy_xip };
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application */
".cy_app_header" : place at start of IROM1_region { section .cy_app_header };
place in IROM1_region { block RO };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
"cy_xip" : place at start of EROM1_region { block cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
/* Public RAM
*To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
*/
/*
place at start of IRAM2_region { section .cy_sharedmem };
*/
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_header,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00100000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */

427
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.s Normal file
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;/**************************************************************************//**
; * @file startup_psoc6_01_cm0plus.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0plus Device Series
; * @version V5.00
; * @date 08. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec_ram:DATA:NOROOT(2)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
EXTERN __iar_data_init3
EXTERN __iar_dynamic_initialization
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
PUBLIC __ramVectors
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD 0x0000000D ; NMI_Handler is defined in ROM code
DCD HardFault_Handler
DCD 0
DCD 0
DCD 0
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD 0
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External interrupts Description
DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0
DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1
DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2
DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3
DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4
DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5
DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6
DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7
DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8
DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9
DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10
DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11
DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12
DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13
DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14
DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15
DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16
DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17
DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18
DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19
DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20
DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21
DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22
DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23
DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24
DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25
DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26
DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27
DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28
DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29
DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30
DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
SECTION .intvec_ram:DATA:REORDER:NOROOT(2)
__ramVectors
DS32 __Vectors_Size
THUMB
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default handlers
;;
PUBWEAK Default_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Default_Handler
B Default_Handler
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Weak function for startup customization
;;
;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
;; because this function is executed as the first instruction in the ResetHandler.
;; The PDL is also not initialized to use the proper register offsets.
;; The user of this function is responsible for initializing the PDL and resources before using them.
;;
PUBWEAK Cy_OnResetUser
SECTION .text:CODE:REORDER:NOROOT(2)
Cy_OnResetUser
BX LR
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Define strong version to return zero for
;; __iar_program_start to skip data sections
;; initialization.
;;
PUBLIC __low_level_init
SECTION .text:CODE:REORDER:NOROOT(2)
__low_level_init
MOVS R0, #0
BX LR
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
; Define strong function for startup customization
LDR R0, =Cy_OnResetUser
BLX R0
; Disable global interrupts
CPSID I
; Copy vectors from ROM to RAM
LDR r1, =__vector_table
LDR r0, =__ramVectors
LDR r2, =__Vectors_Size
intvec_copy
LDR r3, [r1]
STR r3, [r0]
ADDS r0, r0, #4
ADDS r1, r1, #4
SUBS r2, r2, #1
CMP r2, #0
BNE intvec_copy
; Update Vector Table Offset Register
LDR r0, =__ramVectors
LDR r1, =0xE000ED08
STR r0, [r1]
dsb
; Initialize data sections
LDR R0, =__iar_data_init3
BLX R0
; --manual_dynamic_initialization
BL __iar_dynamic_initialization
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BLX R0
; Should never get here
Cy_Main_Exited
B Cy_Main_Exited
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK Cy_SysLib_FaultHandler
SECTION .text:CODE:REORDER:NOROOT(1)
Cy_SysLib_FaultHandler
B Cy_SysLib_FaultHandler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
IMPORT Cy_SysLib_FaultHandler
movs r0, #4
mov r1, LR
tst r0, r1
beq L_MSP
mrs r0, PSP
b L_API_call
L_MSP
mrs r0, MSP
L_API_call
; Storing LR content for Creator call stack trace
push {LR}
bl Cy_SysLib_FaultHandler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
; External interrupts
PUBWEAK NvicMux0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux0_IRQHandler
B NvicMux0_IRQHandler
PUBWEAK NvicMux1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux1_IRQHandler
B NvicMux1_IRQHandler
PUBWEAK NvicMux2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux2_IRQHandler
B NvicMux2_IRQHandler
PUBWEAK NvicMux3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux3_IRQHandler
B NvicMux3_IRQHandler
PUBWEAK NvicMux4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux4_IRQHandler
B NvicMux4_IRQHandler
PUBWEAK NvicMux5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux5_IRQHandler
B NvicMux5_IRQHandler
PUBWEAK NvicMux6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux6_IRQHandler
B NvicMux6_IRQHandler
PUBWEAK NvicMux7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux7_IRQHandler
B NvicMux7_IRQHandler
PUBWEAK NvicMux8_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux8_IRQHandler
B NvicMux8_IRQHandler
PUBWEAK NvicMux9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux9_IRQHandler
B NvicMux9_IRQHandler
PUBWEAK NvicMux10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux10_IRQHandler
B NvicMux10_IRQHandler
PUBWEAK NvicMux11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux11_IRQHandler
B NvicMux11_IRQHandler
PUBWEAK NvicMux12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux12_IRQHandler
B NvicMux12_IRQHandler
PUBWEAK NvicMux13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux13_IRQHandler
B NvicMux13_IRQHandler
PUBWEAK NvicMux14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux14_IRQHandler
B NvicMux14_IRQHandler
PUBWEAK NvicMux15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux15_IRQHandler
B NvicMux15_IRQHandler
PUBWEAK NvicMux16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux16_IRQHandler
B NvicMux16_IRQHandler
PUBWEAK NvicMux17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux17_IRQHandler
B NvicMux17_IRQHandler
PUBWEAK NvicMux18_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux18_IRQHandler
B NvicMux18_IRQHandler
PUBWEAK NvicMux19_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux19_IRQHandler
B NvicMux19_IRQHandler
PUBWEAK NvicMux20_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux20_IRQHandler
B NvicMux20_IRQHandler
PUBWEAK NvicMux21_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux21_IRQHandler
B NvicMux21_IRQHandler
PUBWEAK NvicMux22_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux22_IRQHandler
B NvicMux22_IRQHandler
PUBWEAK NvicMux23_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux23_IRQHandler
B NvicMux23_IRQHandler
PUBWEAK NvicMux24_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux24_IRQHandler
B NvicMux24_IRQHandler
PUBWEAK NvicMux25_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux25_IRQHandler
B NvicMux25_IRQHandler
PUBWEAK NvicMux26_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux26_IRQHandler
B NvicMux26_IRQHandler
PUBWEAK NvicMux27_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux27_IRQHandler
B NvicMux27_IRQHandler
PUBWEAK NvicMux28_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux28_IRQHandler
B NvicMux28_IRQHandler
PUBWEAK NvicMux29_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux29_IRQHandler
B NvicMux29_IRQHandler
PUBWEAK NvicMux30_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux30_IRQHandler
B NvicMux30_IRQHandler
PUBWEAK NvicMux31_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux31_IRQHandler
B NvicMux31_IRQHandler
END
; [] END OF FILE

4
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/system_psoc6_cm0plus.c → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM0P/system_psoc6_cm0plus.c
View File

@ -60,7 +60,7 @@
/**
* Holds the system core clock,
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
* which is the system clock frequency supplied to the SysTick timer and the
* processor core clock.
* This variable implements CMSIS Core global variable.
@ -125,7 +125,7 @@ uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
* Function Name: SystemInit
****************************************************************************//**
*
* Initializes the system on CAT1A:
* Initializes the system:
* - Restores FLL registers to the default state.
* - Unlocks and disables WDT.
* - Calls Cy_PDL_Init() function to define the driver library.

277
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct Normal file
View File

@ -0,0 +1,277 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.91
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at
;*
;* http://www.apache.org/licenses/LICENSE-2.0
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM
#define RAM_START 0x08002000
#define RAM_SIZE 0x00045800
; Flash
#define FLASH_START 0x10000000
#define FLASH_SIZE 0x00100000
; The size of the stack section at the end of CM4 SRAM
#define STACK_SIZE 0x00001000
; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
; More about CM0+ prebuilt images, see here:
; https://github.com/cypresssemiconductorco/psoc6cm0p
; The size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200
; External memory
#define XIP_START 0x18000000
#define XIP_SIZE 0x08000000
; eFuse
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE
{
.cy_m0p_image +0 FLASH_CM0P_SIZE
{
* (.cy_m0p_image)
}
}
; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
{
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS RAM_START UNINIT
{
* (RESET_RAM, +FIRST)
}
RW_RAM_DATA +0
{
* (.cy_ramfunc)
* (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
; device startup.
RW_IRAM1 +0 UNINIT
{
* (.noinit)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
{
}
; Stack region growing down
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
{
}
; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required
; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{
* (.cy_app_signature)
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
.cy_em_eeprom +0
{
* (.cy_em_eeprom)
}
}
; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{
.cy_sflash_user_data +0
{
* (.cy_sflash_user_data)
}
}
; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{
.cy_sflash_nar +0
{
* (.cy_sflash_nar)
}
}
; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{
.cy_sflash_public_key +0
{
* (.cy_sflash_public_key)
}
}
; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{
.cy_toc_part2 +0
{
* (.cy_toc_part2)
}
}
; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{
.cy_rtoc_part2 +0
{
* (.cy_rtoc_part2)
}
}
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE
{
cy_xip +0
{
* (.cy_xip)
}
}
; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE
{
.cy_efuse +0
{
* (.cy_efuse)
}
}
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
#define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000
#define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200
/* Supervisory Flash */
#define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200
/* XIP */
#define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200
/* eFuse */
#define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1
/* [] END OF FILE */

191
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.s → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.s
View File

@ -1,5 +1,5 @@
;/**************************************************************************//**
; * @file startup_psoc6_02_cm4.s
; * @file startup_psoc6_01_cm4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device Series
; * @version V5.00
@ -79,6 +79,8 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$
DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)
DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms)
DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt
DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0
DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1
DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2
@ -103,15 +105,7 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$
DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5
DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6
DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7
DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9
DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10
DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11
DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12
DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0
DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1
DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2
DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3
DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0
DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1
DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2
@ -128,19 +122,6 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$
DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13
DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14
DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15
DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16
DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17
DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18
DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19
DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20
DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21
DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22
DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23
DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24
DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25
DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26
DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27
DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28
DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0
DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1
DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2
@ -157,24 +138,10 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$
DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13
DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14
DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15
DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16
DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17
DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18
DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19
DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20
DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21
DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22
DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23
DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24
DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25
DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26
DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27
DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28
DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0
DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1
DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt
DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt
DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault
DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0
DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1
DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0
@ -211,19 +178,31 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$
DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21
DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22
DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23
DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0
DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1
DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2
DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3
DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4
DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5
DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6
DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7
DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8
DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9
DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10
DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11
DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12
DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13
DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14
DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15
DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt
DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt
DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt
DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt
DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt
DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
DCD usb_interrupt_hi_IRQHandler ; USB Interrupt
DCD usb_interrupt_med_IRQHandler ; USB Interrupt
DCD usb_interrupt_lo_IRQHandler ; USB Interrupt
DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc
DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else
DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used
DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else
DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs
__Vectors_End
@ -378,6 +357,8 @@ Default_Handler PROC
EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK]
EXPORT srss_interrupt_backup_IRQHandler [WEAK]
EXPORT srss_interrupt_IRQHandler [WEAK]
EXPORT pass_interrupt_ctbs_IRQHandler [WEAK]
EXPORT bless_interrupt_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK]
@ -402,15 +383,7 @@ Default_Handler PROC
EXPORT scb_5_interrupt_IRQHandler [WEAK]
EXPORT scb_6_interrupt_IRQHandler [WEAK]
EXPORT scb_7_interrupt_IRQHandler [WEAK]
EXPORT scb_9_interrupt_IRQHandler [WEAK]
EXPORT scb_10_interrupt_IRQHandler [WEAK]
EXPORT scb_11_interrupt_IRQHandler [WEAK]
EXPORT scb_12_interrupt_IRQHandler [WEAK]
EXPORT csd_interrupt_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dmac_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dmac_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK]
@ -427,19 +400,6 @@ Default_Handler PROC
EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK]
@ -456,24 +416,10 @@ Default_Handler PROC
EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK]
EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK]
EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK]
EXPORT cpuss_interrupt_fm_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK]
@ -510,19 +456,31 @@ Default_Handler PROC
EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK]
EXPORT udb_interrupts_0_IRQHandler [WEAK]
EXPORT udb_interrupts_1_IRQHandler [WEAK]
EXPORT udb_interrupts_2_IRQHandler [WEAK]
EXPORT udb_interrupts_3_IRQHandler [WEAK]
EXPORT udb_interrupts_4_IRQHandler [WEAK]
EXPORT udb_interrupts_5_IRQHandler [WEAK]
EXPORT udb_interrupts_6_IRQHandler [WEAK]
EXPORT udb_interrupts_7_IRQHandler [WEAK]
EXPORT udb_interrupts_8_IRQHandler [WEAK]
EXPORT udb_interrupts_9_IRQHandler [WEAK]
EXPORT udb_interrupts_10_IRQHandler [WEAK]
EXPORT udb_interrupts_11_IRQHandler [WEAK]
EXPORT udb_interrupts_12_IRQHandler [WEAK]
EXPORT udb_interrupts_13_IRQHandler [WEAK]
EXPORT udb_interrupts_14_IRQHandler [WEAK]
EXPORT udb_interrupts_15_IRQHandler [WEAK]
EXPORT pass_interrupt_sar_IRQHandler [WEAK]
EXPORT audioss_0_interrupt_i2s_IRQHandler [WEAK]
EXPORT audioss_0_interrupt_pdm_IRQHandler [WEAK]
EXPORT audioss_1_interrupt_i2s_IRQHandler [WEAK]
EXPORT audioss_interrupt_i2s_IRQHandler [WEAK]
EXPORT audioss_interrupt_pdm_IRQHandler [WEAK]
EXPORT profile_interrupt_IRQHandler [WEAK]
EXPORT smif_interrupt_IRQHandler [WEAK]
EXPORT usb_interrupt_hi_IRQHandler [WEAK]
EXPORT usb_interrupt_med_IRQHandler [WEAK]
EXPORT usb_interrupt_lo_IRQHandler [WEAK]
EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK]
EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK]
EXPORT sdhc_1_interrupt_wakeup_IRQHandler [WEAK]
EXPORT sdhc_1_interrupt_general_IRQHandler [WEAK]
EXPORT pass_interrupt_dacs_IRQHandler [WEAK]
ioss_interrupts_gpio_0_IRQHandler
ioss_interrupts_gpio_1_IRQHandler
@ -547,6 +505,8 @@ srss_interrupt_mcwdt_0_IRQHandler
srss_interrupt_mcwdt_1_IRQHandler
srss_interrupt_backup_IRQHandler
srss_interrupt_IRQHandler
pass_interrupt_ctbs_IRQHandler
bless_interrupt_IRQHandler
cpuss_interrupts_ipc_0_IRQHandler
cpuss_interrupts_ipc_1_IRQHandler
cpuss_interrupts_ipc_2_IRQHandler
@ -571,15 +531,7 @@ scb_4_interrupt_IRQHandler
scb_5_interrupt_IRQHandler
scb_6_interrupt_IRQHandler
scb_7_interrupt_IRQHandler
scb_9_interrupt_IRQHandler
scb_10_interrupt_IRQHandler
scb_11_interrupt_IRQHandler
scb_12_interrupt_IRQHandler
csd_interrupt_IRQHandler
cpuss_interrupts_dmac_0_IRQHandler
cpuss_interrupts_dmac_1_IRQHandler
cpuss_interrupts_dmac_2_IRQHandler
cpuss_interrupts_dmac_3_IRQHandler
cpuss_interrupts_dw0_0_IRQHandler
cpuss_interrupts_dw0_1_IRQHandler
cpuss_interrupts_dw0_2_IRQHandler
@ -596,19 +548,6 @@ cpuss_interrupts_dw0_12_IRQHandler
cpuss_interrupts_dw0_13_IRQHandler
cpuss_interrupts_dw0_14_IRQHandler
cpuss_interrupts_dw0_15_IRQHandler
cpuss_interrupts_dw0_16_IRQHandler
cpuss_interrupts_dw0_17_IRQHandler
cpuss_interrupts_dw0_18_IRQHandler
cpuss_interrupts_dw0_19_IRQHandler
cpuss_interrupts_dw0_20_IRQHandler
cpuss_interrupts_dw0_21_IRQHandler
cpuss_interrupts_dw0_22_IRQHandler
cpuss_interrupts_dw0_23_IRQHandler
cpuss_interrupts_dw0_24_IRQHandler
cpuss_interrupts_dw0_25_IRQHandler
cpuss_interrupts_dw0_26_IRQHandler
cpuss_interrupts_dw0_27_IRQHandler
cpuss_interrupts_dw0_28_IRQHandler
cpuss_interrupts_dw1_0_IRQHandler
cpuss_interrupts_dw1_1_IRQHandler
cpuss_interrupts_dw1_2_IRQHandler
@ -625,24 +564,10 @@ cpuss_interrupts_dw1_12_IRQHandler
cpuss_interrupts_dw1_13_IRQHandler
cpuss_interrupts_dw1_14_IRQHandler
cpuss_interrupts_dw1_15_IRQHandler
cpuss_interrupts_dw1_16_IRQHandler
cpuss_interrupts_dw1_17_IRQHandler
cpuss_interrupts_dw1_18_IRQHandler
cpuss_interrupts_dw1_19_IRQHandler
cpuss_interrupts_dw1_20_IRQHandler
cpuss_interrupts_dw1_21_IRQHandler
cpuss_interrupts_dw1_22_IRQHandler
cpuss_interrupts_dw1_23_IRQHandler
cpuss_interrupts_dw1_24_IRQHandler
cpuss_interrupts_dw1_25_IRQHandler
cpuss_interrupts_dw1_26_IRQHandler
cpuss_interrupts_dw1_27_IRQHandler
cpuss_interrupts_dw1_28_IRQHandler
cpuss_interrupts_fault_0_IRQHandler
cpuss_interrupts_fault_1_IRQHandler
cpuss_interrupt_crypto_IRQHandler
cpuss_interrupt_fm_IRQHandler
cpuss_interrupts_cm4_fp_IRQHandler
cpuss_interrupts_cm0_cti_0_IRQHandler
cpuss_interrupts_cm0_cti_1_IRQHandler
cpuss_interrupts_cm4_cti_0_IRQHandler
@ -679,19 +604,31 @@ tcpwm_1_interrupts_20_IRQHandler
tcpwm_1_interrupts_21_IRQHandler
tcpwm_1_interrupts_22_IRQHandler
tcpwm_1_interrupts_23_IRQHandler
udb_interrupts_0_IRQHandler
udb_interrupts_1_IRQHandler
udb_interrupts_2_IRQHandler
udb_interrupts_3_IRQHandler
udb_interrupts_4_IRQHandler
udb_interrupts_5_IRQHandler
udb_interrupts_6_IRQHandler
udb_interrupts_7_IRQHandler
udb_interrupts_8_IRQHandler
udb_interrupts_9_IRQHandler
udb_interrupts_10_IRQHandler
udb_interrupts_11_IRQHandler
udb_interrupts_12_IRQHandler
udb_interrupts_13_IRQHandler
udb_interrupts_14_IRQHandler
udb_interrupts_15_IRQHandler
pass_interrupt_sar_IRQHandler
audioss_0_interrupt_i2s_IRQHandler
audioss_0_interrupt_pdm_IRQHandler
audioss_1_interrupt_i2s_IRQHandler
audioss_interrupt_i2s_IRQHandler
audioss_interrupt_pdm_IRQHandler
profile_interrupt_IRQHandler
smif_interrupt_IRQHandler
usb_interrupt_hi_IRQHandler
usb_interrupt_med_IRQHandler
usb_interrupt_lo_IRQHandler
sdhc_0_interrupt_wakeup_IRQHandler
sdhc_0_interrupt_general_IRQHandler
sdhc_1_interrupt_wakeup_IRQHandler
sdhc_1_interrupt_general_IRQHandler
pass_interrupt_dacs_IRQHandler
B .
ENDP

131
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_02_cm4.S → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/TOOLCHAIN_A_Clang/startup_psoc6_01_cm4.S
View File

@ -1,5 +1,5 @@
/**************************************************************************//**
* @file startup_psoc6_02_cm4.S
* @file startup_psoc6_01_cm4.S
* @brief CMSIS Core Device Startup File for
* ARMCM4 Device Series
* @version V5.00
@ -103,6 +103,8 @@ ___Vectors:
.long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
.long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
.long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
.long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
.long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
.long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
.long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
.long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
@ -127,15 +129,7 @@ ___Vectors:
.long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
.long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
.long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
.long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
.long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
.long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
.long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
.long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
.long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
.long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
.long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
.long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
.long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
.long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
.long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
@ -152,19 +146,6 @@ ___Vectors:
.long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
.long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
.long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
.long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
.long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
.long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
.long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
.long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
.long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
.long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
.long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
.long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
.long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
.long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
.long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
.long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
.long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
.long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
.long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
@ -181,24 +162,10 @@ ___Vectors:
.long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
.long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
.long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
.long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
.long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
.long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
.long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
.long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
.long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
.long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
.long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
.long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
.long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
.long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
.long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
.long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
.long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
.long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
.long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
.long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
.long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
.long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
.long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
.long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
@ -235,19 +202,31 @@ ___Vectors:
.long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
.long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
.long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
.long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
.long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
.long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
.long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
.long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
.long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
.long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
.long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
.long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
.long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
.long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
.long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
.long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
.long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
.long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
.long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
.long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
.long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
.long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
.long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
.long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
.long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
.long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
.long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
.long usb_interrupt_hi_IRQHandler /* USB Interrupt */
.long usb_interrupt_med_IRQHandler /* USB Interrupt */
.long usb_interrupt_lo_IRQHandler /* USB Interrupt */
.long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
.long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
.long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
.long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
.long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
.equ __VectorsSize, . - ___Vectors
@ -358,10 +337,9 @@ Fault_Handler:
b .L_API_call
.L_MSP:
mrs r0, MSP
.L_API_call:
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
adds r0, r0, #4
nop
.L_API_call:
bl Cy_SysLib_FaultHandler
b .
@ -413,6 +391,8 @@ Fault_Handler:
def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
@ -437,15 +417,7 @@ Fault_Handler:
def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
@ -462,19 +434,6 @@ Fault_Handler:
def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
@ -491,24 +450,10 @@ Fault_Handler:
def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
@ -545,19 +490,31 @@ Fault_Handler:
def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
.end

443
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld Normal file
View File

@ -0,0 +1,443 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.ld
* \version 2.91
*
* Linker file for the GNU C compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = 0x1000;
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*/
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800
flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
SECTIONS
{
/* Cortex-M0+ application flash image area */
.cy_m0p_image ORIGIN(flash) :
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash
/* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
/* Cortex-M4 application flash area */
.text ORIGIN(flash) + FLASH_CM0P_SIZE :
{
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
} > flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash
__etext = . ;
.ramVectors (NOLOAD) : ALIGN(8)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram
.data __ram_vectors_end__ :
{
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
__data_end__ = .;
} > ram AT>flash
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
KEEP(*(.stack*))
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Used for the digital signature of the secure application and the Bootloader SDK application.
* The size of the section depends on the required data size. */
.cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
{
KEEP(*(.cy_app_signature))
} > flash
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{
KEEP(*(.cy_rtoc_part2))
} > sflash_rtoc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
cy_xip :
{
__cy_xip_start = .;
KEEP(*(.cy_xip))
__cy_xip_end = .;
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
/* These sections are used for additional metadata (silicon revision,
* Silicon/JTAG ID, etc.) storage.
*/
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00100000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
__cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
__cy_memory_2_start = 0x16000000;
__cy_memory_2_length = 0x8000;
__cy_memory_2_row_size = 0x200;
/* XIP */
__cy_memory_3_start = 0x18000000;
__cy_memory_3_length = 0x08000000;
__cy_memory_3_row_size = 0x200;
/* eFuse */
__cy_memory_4_start = 0x90700000;
__cy_memory_4_length = 0x100000;
__cy_memory_4_row_size = 1;
/* EOF */

132
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S
View File

@ -1,5 +1,5 @@
/**************************************************************************//**
* @file startup_psoc6_02_cm4.S
* @file startup_psoc6_01_cm4.S
* @brief CMSIS Core Device Startup File for
* ARMCM4 Device Series
* @version V5.00
@ -115,6 +115,8 @@ __Vectors:
.long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
.long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
.long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
.long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
.long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
.long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
.long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
.long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
@ -139,15 +141,7 @@ __Vectors:
.long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
.long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
.long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
.long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
.long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
.long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
.long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
.long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
.long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
.long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
.long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
.long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
.long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
.long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
.long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
@ -164,19 +158,6 @@ __Vectors:
.long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
.long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
.long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
.long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
.long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
.long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
.long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
.long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
.long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
.long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
.long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
.long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
.long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
.long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
.long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
.long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
.long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
.long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
.long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
@ -193,24 +174,10 @@ __Vectors:
.long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
.long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
.long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
.long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
.long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
.long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
.long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
.long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
.long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
.long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
.long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
.long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
.long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
.long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
.long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
.long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
.long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
.long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
.long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
.long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
.long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
.long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
.long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
.long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
@ -247,19 +214,31 @@ __Vectors:
.long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
.long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
.long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
.long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
.long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
.long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
.long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
.long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
.long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
.long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
.long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
.long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
.long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
.long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
.long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
.long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
.long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
.long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
.long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
.long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
.long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
.long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
.long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
.long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
.long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
.long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
.long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
.long usb_interrupt_hi_IRQHandler /* USB Interrupt */
.long usb_interrupt_med_IRQHandler /* USB Interrupt */
.long usb_interrupt_lo_IRQHandler /* USB Interrupt */
.long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
.long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
.long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
.long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
.long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
.size __Vectors, . - __Vectors
@ -450,7 +429,7 @@ Reset_Handler:
bl __libc_init_array
/* Execute main application */
bl entry
bl entry
/* Call C/C++ static destructors */
bl __libc_fini_array
@ -490,9 +469,9 @@ Fault_Handler:
b .L_API_call
.L_MSP:
mrs r0, MSP
.L_API_call:
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
adds r0, r0, #4
.L_API_call:
bl Cy_SysLib_FaultHandler
b .
.size Fault_Handler, . - Fault_Handler
@ -545,6 +524,8 @@ Fault_Handler:
def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
@ -569,15 +550,7 @@ Fault_Handler:
def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
@ -594,19 +567,6 @@ Fault_Handler:
def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
@ -623,24 +583,10 @@ Fault_Handler:
def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
@ -677,19 +623,31 @@ Fault_Handler:
def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
.end

247
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf Normal file
View File

@ -0,0 +1,247 @@
/*******************************************************************************
* \file cy8c6xx7_cm4_dual.icf
* \version 2.91
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF;
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF;
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x16000FFF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/**** End of ICF editor section. ###ICF###*/
/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
* https://github.com/cypresssemiconductorco/psoc6cm0p
*/
/* The size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
define block RO {first section .intvec, readonly};
define block cy_xip { section .cy_xip };
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block CM0P_RO };
/* Flash - Cortex-M4 application */
place in IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
"cy_xip" : place at start of EROM1_region { block cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_m0p_image,
section .cy_app_signature,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00100000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */

368
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.s → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.s
View File

@ -1,5 +1,5 @@
;/**************************************************************************//**
; * @file startup_psoc6_02_cm4.s
; * @file startup_psoc6_01_cm4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device Series
; * @version V5.00
@ -104,6 +104,8 @@ __vector_table_0x1c
DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)
DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms)
DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt
DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0
DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1
DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2
@ -128,15 +130,7 @@ __vector_table_0x1c
DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5
DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6
DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7
DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9
DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10
DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11
DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12
DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0
DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1
DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2
DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3
DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0
DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1
DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2
@ -153,19 +147,6 @@ __vector_table_0x1c
DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13
DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14
DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15
DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16
DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17
DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18
DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19
DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20
DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21
DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22
DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23
DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24
DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25
DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26
DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27
DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28
DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0
DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1
DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2
@ -182,24 +163,10 @@ __vector_table_0x1c
DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13
DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14
DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15
DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16
DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17
DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18
DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19
DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20
DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21
DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22
DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23
DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24
DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25
DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26
DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27
DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28
DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0
DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1
DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt
DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt
DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault
DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0
DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1
DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0
@ -236,19 +203,31 @@ __vector_table_0x1c
DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21
DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22
DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23
DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0
DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1
DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2
DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3
DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4
DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5
DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6
DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7
DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8
DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9
DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10
DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11
DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12
DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13
DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14
DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15
DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt
DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt
DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt
DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt
DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt
DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
DCD usb_interrupt_hi_IRQHandler ; USB Interrupt
DCD usb_interrupt_med_IRQHandler ; USB Interrupt
DCD usb_interrupt_lo_IRQHandler ; USB Interrupt
DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc
DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else
DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used
DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else
DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs
__Vectors_End
@ -548,6 +527,16 @@ srss_interrupt_backup_IRQHandler
srss_interrupt_IRQHandler
B srss_interrupt_IRQHandler
PUBWEAK pass_interrupt_ctbs_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
pass_interrupt_ctbs_IRQHandler
B pass_interrupt_ctbs_IRQHandler
PUBWEAK bless_interrupt_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
bless_interrupt_IRQHandler
B bless_interrupt_IRQHandler
PUBWEAK cpuss_interrupts_ipc_0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_ipc_0_IRQHandler
@ -668,51 +657,11 @@ scb_6_interrupt_IRQHandler
scb_7_interrupt_IRQHandler
B scb_7_interrupt_IRQHandler
PUBWEAK scb_9_interrupt_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
scb_9_interrupt_IRQHandler
B scb_9_interrupt_IRQHandler
PUBWEAK scb_10_interrupt_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
scb_10_interrupt_IRQHandler
B scb_10_interrupt_IRQHandler
PUBWEAK scb_11_interrupt_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
scb_11_interrupt_IRQHandler
B scb_11_interrupt_IRQHandler
PUBWEAK scb_12_interrupt_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
scb_12_interrupt_IRQHandler
B scb_12_interrupt_IRQHandler
PUBWEAK csd_interrupt_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
csd_interrupt_IRQHandler
B csd_interrupt_IRQHandler
PUBWEAK cpuss_interrupts_dmac_0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dmac_0_IRQHandler
B cpuss_interrupts_dmac_0_IRQHandler
PUBWEAK cpuss_interrupts_dmac_1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dmac_1_IRQHandler
B cpuss_interrupts_dmac_1_IRQHandler
PUBWEAK cpuss_interrupts_dmac_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dmac_2_IRQHandler
B cpuss_interrupts_dmac_2_IRQHandler
PUBWEAK cpuss_interrupts_dmac_3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dmac_3_IRQHandler
B cpuss_interrupts_dmac_3_IRQHandler
PUBWEAK cpuss_interrupts_dw0_0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw0_0_IRQHandler
@ -793,71 +742,6 @@ cpuss_interrupts_dw0_14_IRQHandler
cpuss_interrupts_dw0_15_IRQHandler
B cpuss_interrupts_dw0_15_IRQHandler
PUBWEAK cpuss_interrupts_dw0_16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw0_16_IRQHandler
B cpuss_interrupts_dw0_16_IRQHandler
PUBWEAK cpuss_interrupts_dw0_17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw0_17_IRQHandler
B cpuss_interrupts_dw0_17_IRQHandler
PUBWEAK cpuss_interrupts_dw0_18_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw0_18_IRQHandler
B cpuss_interrupts_dw0_18_IRQHandler
PUBWEAK cpuss_interrupts_dw0_19_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw0_19_IRQHandler
B cpuss_interrupts_dw0_19_IRQHandler
PUBWEAK cpuss_interrupts_dw0_20_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw0_20_IRQHandler
B cpuss_interrupts_dw0_20_IRQHandler
PUBWEAK cpuss_interrupts_dw0_21_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw0_21_IRQHandler
B cpuss_interrupts_dw0_21_IRQHandler
PUBWEAK cpuss_interrupts_dw0_22_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw0_22_IRQHandler
B cpuss_interrupts_dw0_22_IRQHandler
PUBWEAK cpuss_interrupts_dw0_23_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw0_23_IRQHandler
B cpuss_interrupts_dw0_23_IRQHandler
PUBWEAK cpuss_interrupts_dw0_24_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw0_24_IRQHandler
B cpuss_interrupts_dw0_24_IRQHandler
PUBWEAK cpuss_interrupts_dw0_25_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw0_25_IRQHandler
B cpuss_interrupts_dw0_25_IRQHandler
PUBWEAK cpuss_interrupts_dw0_26_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw0_26_IRQHandler
B cpuss_interrupts_dw0_26_IRQHandler
PUBWEAK cpuss_interrupts_dw0_27_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw0_27_IRQHandler
B cpuss_interrupts_dw0_27_IRQHandler
PUBWEAK cpuss_interrupts_dw0_28_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw0_28_IRQHandler
B cpuss_interrupts_dw0_28_IRQHandler
PUBWEAK cpuss_interrupts_dw1_0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw1_0_IRQHandler
@ -938,71 +822,6 @@ cpuss_interrupts_dw1_14_IRQHandler
cpuss_interrupts_dw1_15_IRQHandler
B cpuss_interrupts_dw1_15_IRQHandler
PUBWEAK cpuss_interrupts_dw1_16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw1_16_IRQHandler
B cpuss_interrupts_dw1_16_IRQHandler
PUBWEAK cpuss_interrupts_dw1_17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw1_17_IRQHandler
B cpuss_interrupts_dw1_17_IRQHandler
PUBWEAK cpuss_interrupts_dw1_18_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw1_18_IRQHandler
B cpuss_interrupts_dw1_18_IRQHandler
PUBWEAK cpuss_interrupts_dw1_19_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw1_19_IRQHandler
B cpuss_interrupts_dw1_19_IRQHandler
PUBWEAK cpuss_interrupts_dw1_20_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw1_20_IRQHandler
B cpuss_interrupts_dw1_20_IRQHandler
PUBWEAK cpuss_interrupts_dw1_21_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw1_21_IRQHandler
B cpuss_interrupts_dw1_21_IRQHandler
PUBWEAK cpuss_interrupts_dw1_22_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw1_22_IRQHandler
B cpuss_interrupts_dw1_22_IRQHandler
PUBWEAK cpuss_interrupts_dw1_23_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw1_23_IRQHandler
B cpuss_interrupts_dw1_23_IRQHandler
PUBWEAK cpuss_interrupts_dw1_24_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw1_24_IRQHandler
B cpuss_interrupts_dw1_24_IRQHandler
PUBWEAK cpuss_interrupts_dw1_25_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw1_25_IRQHandler
B cpuss_interrupts_dw1_25_IRQHandler
PUBWEAK cpuss_interrupts_dw1_26_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw1_26_IRQHandler
B cpuss_interrupts_dw1_26_IRQHandler
PUBWEAK cpuss_interrupts_dw1_27_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw1_27_IRQHandler
B cpuss_interrupts_dw1_27_IRQHandler
PUBWEAK cpuss_interrupts_dw1_28_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_dw1_28_IRQHandler
B cpuss_interrupts_dw1_28_IRQHandler
PUBWEAK cpuss_interrupts_fault_0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_fault_0_IRQHandler
@ -1023,11 +842,6 @@ cpuss_interrupt_crypto_IRQHandler
cpuss_interrupt_fm_IRQHandler
B cpuss_interrupt_fm_IRQHandler
PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_cm4_fp_IRQHandler
B cpuss_interrupts_cm4_fp_IRQHandler
PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
cpuss_interrupts_cm0_cti_0_IRQHandler
@ -1208,25 +1022,100 @@ tcpwm_1_interrupts_22_IRQHandler
tcpwm_1_interrupts_23_IRQHandler
B tcpwm_1_interrupts_23_IRQHandler
PUBWEAK udb_interrupts_0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_0_IRQHandler
B udb_interrupts_0_IRQHandler
PUBWEAK udb_interrupts_1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_1_IRQHandler
B udb_interrupts_1_IRQHandler
PUBWEAK udb_interrupts_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_2_IRQHandler
B udb_interrupts_2_IRQHandler
PUBWEAK udb_interrupts_3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_3_IRQHandler
B udb_interrupts_3_IRQHandler
PUBWEAK udb_interrupts_4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_4_IRQHandler
B udb_interrupts_4_IRQHandler
PUBWEAK udb_interrupts_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_5_IRQHandler
B udb_interrupts_5_IRQHandler
PUBWEAK udb_interrupts_6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_6_IRQHandler
B udb_interrupts_6_IRQHandler
PUBWEAK udb_interrupts_7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_7_IRQHandler
B udb_interrupts_7_IRQHandler
PUBWEAK udb_interrupts_8_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_8_IRQHandler
B udb_interrupts_8_IRQHandler
PUBWEAK udb_interrupts_9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_9_IRQHandler
B udb_interrupts_9_IRQHandler
PUBWEAK udb_interrupts_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_10_IRQHandler
B udb_interrupts_10_IRQHandler
PUBWEAK udb_interrupts_11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_11_IRQHandler
B udb_interrupts_11_IRQHandler
PUBWEAK udb_interrupts_12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_12_IRQHandler
B udb_interrupts_12_IRQHandler
PUBWEAK udb_interrupts_13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_13_IRQHandler
B udb_interrupts_13_IRQHandler
PUBWEAK udb_interrupts_14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_14_IRQHandler
B udb_interrupts_14_IRQHandler
PUBWEAK udb_interrupts_15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
udb_interrupts_15_IRQHandler
B udb_interrupts_15_IRQHandler
PUBWEAK pass_interrupt_sar_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
pass_interrupt_sar_IRQHandler
B pass_interrupt_sar_IRQHandler
PUBWEAK audioss_0_interrupt_i2s_IRQHandler
PUBWEAK audioss_interrupt_i2s_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
audioss_0_interrupt_i2s_IRQHandler
B audioss_0_interrupt_i2s_IRQHandler
audioss_interrupt_i2s_IRQHandler
B audioss_interrupt_i2s_IRQHandler
PUBWEAK audioss_0_interrupt_pdm_IRQHandler
PUBWEAK audioss_interrupt_pdm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
audioss_0_interrupt_pdm_IRQHandler
B audioss_0_interrupt_pdm_IRQHandler
PUBWEAK audioss_1_interrupt_i2s_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
audioss_1_interrupt_i2s_IRQHandler
B audioss_1_interrupt_i2s_IRQHandler
audioss_interrupt_pdm_IRQHandler
B audioss_interrupt_pdm_IRQHandler
PUBWEAK profile_interrupt_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
@ -1253,25 +1142,10 @@ usb_interrupt_med_IRQHandler
usb_interrupt_lo_IRQHandler
B usb_interrupt_lo_IRQHandler
PUBWEAK sdhc_0_interrupt_wakeup_IRQHandler
PUBWEAK pass_interrupt_dacs_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
sdhc_0_interrupt_wakeup_IRQHandler
B sdhc_0_interrupt_wakeup_IRQHandler
PUBWEAK sdhc_0_interrupt_general_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
sdhc_0_interrupt_general_IRQHandler
B sdhc_0_interrupt_general_IRQHandler
PUBWEAK sdhc_1_interrupt_wakeup_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
sdhc_1_interrupt_wakeup_IRQHandler
B sdhc_1_interrupt_wakeup_IRQHandler
PUBWEAK sdhc_1_interrupt_general_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
sdhc_1_interrupt_general_IRQHandler
B sdhc_1_interrupt_general_IRQHandler
pass_interrupt_dacs_IRQHandler
B pass_interrupt_dacs_IRQHandler
END

4
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/system_psoc6_cm4.c
View File

@ -60,7 +60,7 @@
/**
* Holds the system core clock,
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
* which is the system clock frequency supplied to the SysTick timer and the
* processor core clock.
* This variable implements CMSIS Core global variable.
@ -124,7 +124,7 @@ uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
* Function Name: SystemInit
****************************************************************************//**
* \cond
* Initializes the system on CAT1A:
* Initializes the system:
* - Restores FLL registers to the default state for single core devices.
* - Unlocks and disables WDT.
* - Calls Cy_PDL_Init() function to define the driver library.

0
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/EULA → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/EULA
View File

0
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/LICENSE → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/LICENSE
View File

73
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/README.md Normal file
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@ -0,0 +1,73 @@
# CY8CKIT-062-BLE BSP
## Overview
The PSoC 6 BLE Pioneer Kit is a low-cost hardware platform that enables design and debug of the PSoC 63 Line (CY8C6347BZI-BLD53).
![](docs/html/board.png)
To use code from the BSP, simply include a reference to `cybsp.h`.
## Features
### Kit Features:
* BLE v5.0
* Serial memory interface
* PDM-PCM digital microphone interface
* Industry-leading CAPSENSE
### Kit Contents:
* CY8CKIT-062-BLE evaluation board
* E-Ink display shield with an ultra-low-power 2.7" E-ink display, thermistor, 6-axis motion sensor, and digital microphone
* USB cable
## BSP Configuration
The BSP has a few hooks that allow its behavior to be configured. Some of these items are enabled by default while others must be explicitly enabled. Items enabled by default are specified in the CY8CKIT-062-BLE.mk file. The items that are enabled can be changed by creating a custom BSP or by editing the application makefile.
Components:
* Device specific category reference (e.g.: CAT1) - This component, enabled by default, pulls in any device specific code for this board.
* BSP_DESIGN_MODUS - This component, enabled by default, causes the Configurator generated code for this specific BSP to be included. This should not be used at the same time as the CUSTOM_DESIGN_MODUS component.
* CUSTOM_DESIGN_MODUS - This component, disabled by default, causes the Configurator generated code from the application to be included. This assumes that the application provides configurator generated code. This should not be used at the same time as the BSP_DESIGN_MODUS component.
Defines:
* CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip if it has one.
* CY_USING_HAL - This define, enabled by default, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers.
### Clock Configuration
| Clock | Source | Output Frequency |
|----------|-----------|------------------|
| FLL | IMO | 100.0 MHz |
| PLL | IMO | 48.0 MHz |
| CLK_HF0 | CLK_PATH0 | 100 MHz |
### Power Configuration
* System Active Power Mode: LP
* System Idle Power Mode: Deep Sleep
* VDDA Voltage: 3300 mV
* VDDD Voltage: 3300 mV
See the [BSP Setttings][settings] for additional board specific configuration settings.
## API Reference Manual
The CY8CKIT-062-BLE Board Support Package provides a set of APIs to configure, initialize and use the board resources.
See the [BSP API Reference Manual][api] for the complete list of the provided interfaces.
## More information
* [CY8CKIT-062-BLE BSP API Reference Manual][api]
* [CY8CKIT-062-BLE Documentation](http://www.cypress.com/documentation/development-kitsboards/psoc-6-ble-pioneer-kit)
* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com)
* [Infineon GitHub](https://github.com/infineon)
* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment)
[api]: https://infineon.github.io/TARGET_CY8CKIT-062-BLE/html/modules.html
[settings]: https://infineon.github.io/TARGET_CY8CKIT-062-BLE/html/md_bsp_settings.html
---
© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2021.

89
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/RELEASE.md Normal file
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@ -0,0 +1,89 @@
# CY8CKIT-062-BLE BSP Release Notes
The PSoC 6 BLE Pioneer Kit is a low-cost hardware platform that enables design and debug of the PSoC 63 Line (CY8C6347BZI-BLD53).
NOTE: BSPs are versioned by family. This means that version 1.2.0 of any BSP in a family (eg: PSoC™ 6) will have the same software maturity level. However, not all updates are necessarily applicable for each BSP in the family so not all version numbers will exist for each board. Additionally, new BSPs may not start at version 1.0.0. In the event of adding a common feature across all BSPs, the libraries are assigned the same version number. For example if BSP_A is at v1.3.0 and BSP_B is at v1.2.0, the event will trigger a version update to v1.4.0 for both BSP_A and BSP_B. This allows the common feature to be tracked in a consistent way.
### What's Included?
The CY8CKIT-062-BLE library includes the following:
* BSP specific makefile to configure the build process for the board
* cybsp.c/h files to initialize the board and any system peripherals
* cybsp_types.h file describing basic board setup
* CM4 Linker script & startup code for GCC, IAR, and ARM toolchains
* CM0+ Linker script & startup code for GCC, IAR, and ARM toolchains
* Configurator design files (and generated code) to setup board specific peripherals
* .lib file references for all dependent libraries
* API documentation
### What Changed?
#### v3.0.0
* Updated to HAL dependency to v2.0.0
* Updated CAPSENSE™ dependency to v3.0.0
* Regenerated code with Configurators from ModusToolbox™ v2.4.0
#### v2.3.0
* Add new connectivity components for easier board customization
* Simplify BT configuration settings for boards that support it
* Minor branding updates
#### v2.2.0
* Updated PSoC™ 64 linker sections to match secure policy settings
* Minor documentation updates
#### v2.1.0
* Added component CAT1 to all boards
* Added new components for connectivity chips
* Added BT configuration settings for boards that support it
* Minor documentation updates
#### v2.0.1
* Minor update to better handle when to include the SCL library in the build
#### v2.0.0
* Updated design files and GeneratedSource with ModusToolbox™ 2.2 release
* Migrated pin definitions into design.modus file
* Updated clock frequencies to 100 MHz (fast) / 50 MHz (slow)
* Updated MPNs on some boards to non-obsolete parts
* Switched psoc6pdl dependency to new mtb-pdl
* Switched psoc6hal dependency to new mtb-hal
* Switched psoc6make dependency to new core-make & recipe-make-cat1a
NOTE: This version requires ModusToolbox™ tools 2.2 or later. This version is not backwards compatible with 1.X versions. Additional manual steps must be taken to successfully update a design using a 1.x version of the BSP to this version.
#### v1.3.0
* Minor update for documentation & branding
* Updated design files to use latest personality files
* Initialize VDDA voltage if set in configurator
NOTE: This requires psoc6hal 1.3.0 or later
#### v1.2.1
* Added 43012/4343W/43438 component to appropriate BSPs
* Added multi-image policy for secure (064) BSPs
#### v1.2.0
* Standardize version numbering for all boards in a family
* Moved UDB SDIO implementation into its own library udb-sdio-whd library
* Added call to setup HAL SysPM driver (requires HAL 1.2.0 or later)
* Updated documentation
NOTE: This requires psoc6hal 1.2.0 or later
#### v1.1.0
* Updated linker scripts and startup code for the CM0+ and CM4 cores. The files are now in core specific directories.
* Minor updates to avoid potential warnings on some toolchains
#### v1.0.1
* Added pin references for the board's J2 Header (for appropriate boards)
#### v1.0.0
* Initial release
### Supported Software and Tools
This version of the CY8CKIT-062-BLE BSP was validated for compatibility with the following Software and Tools:
| Software and Tools | Version |
| :--- | :----: |
| ModusToolbox™ Software Environment | 2.4.0 |
| GCC Compiler | 10.3.1 |
| IAR Compiler | 8.4 |
| ARM Compiler | 6.11 |
Minimum required ModusToolbox™ Software Environment: v2.4.0
### More information
* [CY8CKIT-062-BLE BSP API Reference Manual][api]
* [CY8CKIT-062-BLE Documentation](http://www.cypress.com/documentation/development-kitsboards/psoc-6-ble-pioneer-kit)
* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com)
* [Infineon GitHub](https://github.com/infineon)
* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment)
[api]: https://infineon.github.io/TARGET_CY8CKIT-062-BLE/html/modules.html
---
© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2021.

8
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/cybsp.c → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/cybsp.c
View File

@ -59,7 +59,6 @@ cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
#endif // if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
#if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
//--------------------------------------------------------------------------------------------------
// cybsp_register_sysclk_pm_callback
//
@ -87,9 +86,6 @@ static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
}
#endif // if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
//--------------------------------------------------------------------------------------------------
// cybsp_init
//--------------------------------------------------------------------------------------------------
@ -122,11 +118,7 @@ cy_rslt_t cybsp_init(void)
if (CY_RSLT_SUCCESS == result)
{
#if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
result = cybsp_register_custom_sysclk_pm_callback();
#else
result = cybsp_register_sysclk_pm_callback();
#endif
}
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

13
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/cybsp.h → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/cybsp.h
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@ -77,19 +77,6 @@ cy_rslt_t cybsp_init(void);
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void);
#endif // defined(CYBSP_WIFI_CAPABLE)
#if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
//--------------------------------------------------------------------------------------------------
// cybsp_register_custom_sysclk_pm_callback
//
// Registers a power management callback that prepares the clock system for entering deep sleep mode
// and restore the clocks upon wakeup from deep sleep. The application should implement this
// function and define `CYBSP_CUSTOM_SYSCLK_PM_CALLBACK` if it needs to replace the default SysClk
// DeepSleep callback behavior with application specific logic.
// NOTE: This is called automatically as part of \ref cybsp_init
//--------------------------------------------------------------------------------------------------
cy_rslt_t cybsp_register_custom_sysclk_pm_callback(void);
#endif // defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
/** \} group_bsp_functions */
#ifdef __cplusplus

4
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/cybsp_doc.h → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/cybsp_doc.h
View File

@ -24,11 +24,7 @@
#include "cyhal_pin_package.h"
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
/** test */
#include "cycfg.h"
#elif defined(COMPONENT_CAT4) /* CAT4 does not have configurators so the BSP defines pins in a
* non-generated header */
#include "cybsp_pins.h"
#endif
#if defined(__cplusplus)

0
bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/cybsp_types.h → bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/cybsp_types.h
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15
bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/docs/api_reference_manual.html Normal file
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@ -0,0 +1,15 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>Redirect to API Reference Manual main page after 0 seconds</title>
<noscript>
<meta http-equiv="refresh" content="0; URL=html/index.html">
</noscript>
<meta name="keywords" content="automatic redirection">
</head>
<body onLoad="window.location='html/index.html' " >
<h2>
If the automatic redirection is failing, click the following link to open <a href="html/index.html">API Reference Manual</a>.
</h2>
</body>
</html>

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