diff --git a/.ignore_format.yml b/.ignore_format.yml index bfaca4cf00..6622a90397 100644 --- a/.ignore_format.yml +++ b/.ignore_format.yml @@ -12,6 +12,7 @@ dir_path: - components/net/lwip-2.0.3 - components/net/lwip-2.1.2 - bsp/mm32f327x/Libraries +- bsp/fm33lc026/libraries - bsp/stm32/libraries/STM32F0xx_HAL - bsp/stm32/libraries/STM32F2xx_HAL - bsp/stm32/libraries/STM32F4xx_HAL diff --git a/bsp/Copyright_Notice.md b/bsp/Copyright_Notice.md index 206b65d448..8ec2687a75 100644 --- a/bsp/Copyright_Notice.md +++ b/bsp/Copyright_Notice.md @@ -125,6 +125,17 @@ Path: - bsp/essemi/es32f0654/libraries/CMSIS/Include - bsp/essemi/es8p508x/libraries/CMSIS +###fm33lc026 + +License: Mulan PSL v1 + +Copyright: Copyright (c) [2019] [Fudan Microelectronics] + +Path: + +- bsp/fm33lc026\libraries\FM33LC0xx_FL_Driver +- bsp/fm33lc026\libraries\FM + ### frdm-k64f License: bsd-new diff --git a/bsp/fm33lc026/.config b/bsp/fm33lc026/.config new file mode 100644 index 0000000000..2a4776e552 --- /dev/null +++ b/bsp/fm33lc026/.config @@ -0,0 +1,541 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=500 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart4" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +CONFIG_ARCH_ARM=y +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M0=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_LIBC_USING_TIME is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +CONFIG_SOC_FAMILY_FM33=y +CONFIG_SOC_SERIES_FM33LC0XX=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_FM33LC0XX=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_USING_UART1=y +CONFIG_BSP_USING_UART4=y +# CONFIG_BSP_USING_UART5 is not set diff --git a/bsp/fm33lc026/Kconfig b/bsp/fm33lc026/Kconfig new file mode 100644 index 0000000000..7d18ba6dc4 --- /dev/null +++ b/bsp/fm33lc026/Kconfig @@ -0,0 +1,22 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "libraries/Kconfig" +source "board/Kconfig" + diff --git a/bsp/fm33lc026/README.md b/bsp/fm33lc026/README.md new file mode 100644 index 0000000000..0232ef3b7e --- /dev/null +++ b/bsp/fm33lc026/README.md @@ -0,0 +1,46 @@ +# FM33LC026 # + +## 1. 简介 + +[FM33LC026](开发者论坛：http://www.fmdevelopers.com.cn/forum.php)是复旦微的MCU，使用 Cortex-M0 内核。该BSP基于FM026开发调试，LC0XX系列通用，重新选择型号即可，可能需要改变部分引脚定义。 +FM33LC0xxx系列低功耗MCU，基于ARM Cortex-M0内核，集成大容量嵌入式闪存，具备丰富的模拟和数字外设，并具有优异的低功耗特性。FM33LC0xxx系列包含三个子系列，分别为支持无晶振USB FS device的FM33LC0xxU系列，和不支持USB的FM33LC0xxN系列，以及FM33LC0x4NR系列。 +主要资源如下： + +| 硬件 | 描述 | +| -- | -- | +|CPU| Cortex-M0| +|主频| 64MHz | +|SRAM| 24KB | +|Flash| 128KB | + +## 2. 编译说明 + +只适配了MDK5，使用MDK5编译。 + +| IDE/编译器 | 已测试版本 | +| -- | -- | +| MDK5 | MDK5.27 | + +## 3. 烧写及执行 + +下载程序：使用 J-Link 工具。 + +### 3.1 配置和仿真 + +工程已经默认使能了RT-Thread UART驱动。若想进一步配置工程请 +使用ENV工具。 + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | USART0/1/4/5 | + +## 5. 联系人信息 + +维护人： + +- [jqj96](https://github.com/jqj96) + +## 6. 参考 + diff --git a/bsp/fm33lc026/SConscript b/bsp/fm33lc026/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/fm33lc026/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/fm33lc026/SConstruct b/bsp/fm33lc026/SConstruct new file mode 100644 index 0000000000..9a333a067a --- /dev/null +++ b/bsp/fm33lc026/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map rt-thread.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +fm33_library = 'FM33LC0xx_FL_Driver' +rtconfig.BSP_LIBRARY_TYPE = fm33_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, fm33_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/fm33lc026/applications/SConscript b/bsp/fm33lc026/applications/SConscript new file mode 100644 index 0000000000..5efd37ed23 --- /dev/null +++ b/bsp/fm33lc026/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/fm33lc026/applications/main.c b/bsp/fm33lc026/applications/main.c new file mode 100644 index 0000000000..1d8b1905c4 --- /dev/null +++ b/bsp/fm33lc026/applications/main.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-27 Jiao first version + */ + +#include +#include "board.h" + +int main(void) +{ + FL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + FL_GPIO_SetOutputPin(GPIOD, FL_GPIO_PIN_4); + GPIO_InitStruct.pin = FL_GPIO_PIN_4; + GPIO_InitStruct.mode = FL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.pull = FL_DISABLE; + FL_GPIO_Init(GPIOD, &GPIO_InitStruct); + while (1) + { + FL_GPIO_SetOutputPin(GPIOD, FL_GPIO_PIN_4); + rt_thread_mdelay(500); + FL_GPIO_ResetOutputPin(GPIOD, FL_GPIO_PIN_4); + rt_thread_mdelay(500); + } + +} diff --git a/bsp/fm33lc026/board/Kconfig b/bsp/fm33lc026/board/Kconfig new file mode 100644 index 0000000000..4a08e2ca23 --- /dev/null +++ b/bsp/fm33lc026/board/Kconfig @@ -0,0 +1,38 @@ +menu "Hardware Drivers Config" + +config SOC_FM33LC0XX + bool + select SOC_SERIES_FM33LC0XX + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default n + + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_USING_UART4 + bool "Enable UART4" + default n + + config BSP_USING_UART5 + bool "Enable UART5" + default y + endif + source "libraries/HAL_Drivers/Kconfig" + +endmenu + + +endmenu diff --git a/bsp/fm33lc026/board/SConscript b/bsp/fm33lc026/board/SConscript new file mode 100644 index 0000000000..560310ab0a --- /dev/null +++ b/bsp/fm33lc026/board/SConscript @@ -0,0 +1,29 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +''') + +path = [cwd] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/FM/FM33xx/Source/Templates/gcc/startup_fm33lc0xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/FM/FM33xx/Source/Templates/ARM/startup_fm33lc0xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/FM/FM33xx/Source/Templates/iar/startup_fm33lc0xx.s'] + +# FM33LC0XX +# You can select chips from the list above +CPPDEFINES = ['FM33LC0XX'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/bsp/fm33lc026/board/board.c b/bsp/fm33lc026/board/board.c new file mode 100644 index 0000000000..fe2cceeccd --- /dev/null +++ b/bsp/fm33lc026/board/board.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-27 Jiao first version + */ + +#include "board.h" + +FL_ErrorStatus FL_UART_GPIO_Init(UART_Type *UARTx) +{ + FL_ErrorStatus status = FL_FAIL; + FL_GPIO_InitTypeDef GPIO_InitStruct; + if (UARTx == UART0) + { + GPIO_InitStruct.pin = FL_GPIO_PIN_13; + GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL; + GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.pull = FL_DISABLE; + GPIO_InitStruct.remapPin = FL_DISABLE; + + status = FL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.pin = FL_GPIO_PIN_14; + GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL; + GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.pull = FL_DISABLE; + GPIO_InitStruct.remapPin = FL_DISABLE; + + status = FL_GPIO_Init(GPIOA, &GPIO_InitStruct); + } + else if (UARTx == UART1) + { + GPIO_InitStruct.pin = FL_GPIO_PIN_13; + GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL; + GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.pull = FL_DISABLE; + GPIO_InitStruct.remapPin = FL_DISABLE; + + status = FL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.pin = FL_GPIO_PIN_14; + GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL; + GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.pull = FL_DISABLE; + GPIO_InitStruct.remapPin = FL_DISABLE; + + status = FL_GPIO_Init(GPIOB, &GPIO_InitStruct); + } + else if (UARTx == UART4) + { + GPIO_InitStruct.pin = FL_GPIO_PIN_0; + GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL; + GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.pull = FL_DISABLE; + GPIO_InitStruct.remapPin = FL_DISABLE; + + status = FL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.pin = FL_GPIO_PIN_1; + GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL; + GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.pull = FL_DISABLE; + GPIO_InitStruct.remapPin = FL_DISABLE; + + status = FL_GPIO_Init(GPIOA, &GPIO_InitStruct); + } + return status; +} + + + +static void RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLL_R, uint32_t PLL_DB, uint32_t PLL_O) +{ + MODIFY_REG(RCC->PLLCR, RCC_PLLCR_DB_Msk | RCC_PLLCR_REFPRSC_Msk | RCC_PLLCR_OSEL_Msk | RCC_PLLCR_INSEL_Msk, + (PLL_DB << RCC_PLLCR_DB_Pos) | PLL_R | PLL_O | Source); +} + +static void RCHFInit(uint32_t clock) +{ + switch (clock) + { + case FL_RCC_RCHF_FREQUENCY_8MHZ: + FL_RCC_RCHF_WriteTrimValue(RCHF8M_TRIM); + break; + + case FL_RCC_RCHF_FREQUENCY_16MHZ: + FL_RCC_RCHF_WriteTrimValue(RCHF16M_TRIM); + break; + + case FL_RCC_RCHF_FREQUENCY_24MHZ: + FL_RCC_RCHF_WriteTrimValue(RCHF24M_TRIM); + break; + + default: + FL_RCC_RCHF_WriteTrimValue(RCHF8M_TRIM); + break; + } + + FL_RCC_RCHF_SetFrequency(clock); +} + +void SelRCHFToPLL(uint32_t rchf, uint32_t clock) +{ + uint32_t div = FL_RCC_PLL_PSC_DIV8; + + if (clock > 64) + { + return; + } + + RCHFInit(rchf); + + switch (rchf) + { + case FL_RCC_RCHF_FREQUENCY_16MHZ: + div = FL_RCC_PLL_PSC_DIV16; + break; + + case FL_RCC_RCHF_FREQUENCY_24MHZ: + div = FL_RCC_PLL_PSC_DIV24; + break; + + default: + break; + } + + if (clock <= 24) + { + FL_FLASH_SetReadWait(FLASH, FL_FLASH_READ_WAIT_0CYCLE); + } + + else + { + if ((clock > 24) && (clock <= 48)) + { + FL_FLASH_SetReadWait(FLASH, FL_FLASH_READ_WAIT_1CYCLE); + } + + else + { + FL_FLASH_SetReadWait(FLASH, FL_FLASH_READ_WAIT_1CYCLE); + } + } + + RCC_PLL_ConfigDomain_SYS(FL_RCC_PLL_CLK_SOURCE_RCHF, div, clock, FL_RCC_PLL_OUTPUT_X1); + FL_RCC_PLL_Enable(); + + while (FL_RCC_IsActiveFlag_PLLReady() != FL_SET); + + FL_RCC_SetAHBPrescaler(FL_RCC_AHBCLK_PSC_DIV1); + FL_RCC_SetAPB1Prescaler(FL_RCC_APB1CLK_PSC_DIV1); + FL_RCC_SetAPB2Prescaler(FL_RCC_APB2CLK_PSC_DIV1); + FL_RCC_SetSystemClockSource(FL_RCC_SYSTEM_CLK_SOURCE_PLL); +} diff --git a/bsp/fm33lc026/board/board.h b/bsp/fm33lc026/board/board.h new file mode 100644 index 0000000000..cd33a31e08 --- /dev/null +++ b/bsp/fm33lc026/board/board.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-27 Jiao first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "fm33lc0xx_fl.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Include/core_cm0plus.h b/bsp/fm33lc026/libraries/FM/FM33xx/Include/core_cm0plus.h new file mode 100644 index 0000000000..e39c6f33ff --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Include/core_cm0plus.h @@ -0,0 +1,1000 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.00 + * @date 29. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/* Common defines in core_*.h files + - #define __ASM Compiler keyword for asm + - #define __INLINE Compiler keyword for inline + - #define __STATIC_INLINE Compiler keyword for static inline + - #define __NO_RETURN function that never returns + - #define __USED function or variable that is not optimized away + - #define __WEAK weak function or variable + - #define __UNALIGNED_UINT32 pointer to unaligned uint32_t variable + */ +#if defined ( __CC_ARM ) /* ARM Compiler 4/5 */ + #define __ASM __asm + #define __INLINE __inline + #define __STATIC_INLINE static __inline + #define __NO_RETURN __declspec(noreturn) + #define __USED __attribute__((used)) + #define __WEAK __attribute__((weak)) + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler 6 */ + #define __ASM __asm + #define __INLINE __inline + #define __STATIC_INLINE static __inline + #define __NO_RETURN __attribute__((noreturn)) + #define __USED __attribute__((used)) + #define __WEAK __attribute__((weak)) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + +#elif defined ( __GNUC__ ) /* GNU Compiler */ + #define __ASM __asm + #define __INLINE inline + #define __STATIC_INLINE static inline + #define __NO_RETURN __attribute__((noreturn)) + #define __USED __attribute__((used)) + #define __WEAK __attribute__((weak)) + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + +#elif defined ( __ICCARM__ ) /* IAR Compiler */ + #define __ASM __asm + #define __INLINE inline + #define __STATIC_INLINE static inline + #define __NO_RETURN __noreturn + #define __USED + #define __WEAK __weak +// struct __packed T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + +#elif defined ( __TI_ARM__ ) /* TI ARM Compiler */ + #define __ASM __asm + #define __INLINE inline + #define __STATIC_INLINE static inline + #define __NO_RETURN __attribute__((noreturn)) + #define __USED __attribute__((used)) + #define __WEAK __attribute__((weak)) + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + +#elif defined ( __TASKING__ ) /* TASKING Compiler */ + #define __ASM __asm + #define __INLINE inline + #define __STATIC_INLINE static inline + #define __NO_RETURN __attribute__((noreturn)) + #define __USED __attribute__((used)) + #define __WEAK __attribute__((weak)) + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + +#elif defined ( __CSMC__ ) /* COSMIC Compiler */ + #define __packed + #define __ASM _asm + #define __INLINE inline + #define __STATIC_INLINE static inline + #define __NO_RETURN + #define __USED + #define __WEAK + #define __UNALIGNED_UINT32(x) (*x) + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cminstr.h" /* Core Instruction Access */ +#include "core_cmfunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be nagative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be nagative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be nagative. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be nagative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be nagative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Include/core_cmFunc.h b/bsp/fm33lc026/libraries/FM/FM33xx/Include/core_cmFunc.h new file mode 100644 index 0000000000..b6ad0a4c5f --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Include/core_cmFunc.h @@ -0,0 +1,664 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Set Base Priority with condition + + This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Set Base Priority with condition + + This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Include/core_cmInstr.h b/bsp/fm33lc026/libraries/FM/FM33xx/Include/core_cmInstr.h new file mode 100644 index 0000000000..fca425c51d --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Include/core_cmInstr.h @@ -0,0 +1,916 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0) + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0) + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0) + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end + + result = value; // r will be reversed bits of v; first get LSB of v + for (value >>= 1; value; value >>= 1) + { + result <<= 1; + result |= value & 1; + s--; + } + result <<= s; // shift when v's highest bits are zero + return(result); +} +#endif + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end + + result = value; // r will be reversed bits of v; first get LSB of v + for (value >>= 1; value; value >>= 1) + { + result <<= 1; + result |= value & 1; + s--; + } + result <<= s; // shift when v's highest bits are zero +#endif + return(result); +} + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33_assert.h b/bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33_assert.h new file mode 100644 index 0000000000..63b5620081 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33_assert.h @@ -0,0 +1,41 @@ +/** + **************************************************************************************************** + * @file fm33_assert.h + * @author FMSH Application Team + * @brief Assert function define + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +#ifndef __FM33_ASSERT_H +#define __FM33_ASSERT_H +#include "fm33xx.h" +#ifdef __cplusplus + extern "C" { +#endif + + +#ifdef USE_FULL_ASSERT +#define assert_param(expr) do{if((expr) == 0)for(;;);}while(0) +#else +#define assert_param(expr) ((void)0U) +#endif + +#ifdef __cplusplus +} +#endif + + +#endif + diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33lc0xx.h b/bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33lc0xx.h new file mode 100644 index 0000000000..1d8974cfb0 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33lc0xx.h @@ -0,0 +1,795 @@ + +/****************************************************************************************************//** + * @file FM33LC0XX.h + * + * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for + * FM33LC0XX from Keil. + * + * @version V0.0.1 + * @date 13. august 2019 + * + * @note Generated with SVDConv V2.87e + * from CMSIS SVD File 'FM33LC0XX.SVD' Version 1.0, + * + * @par ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontroller, but can be equally used for other + * suitable processor architectures. This file can be freely distributed. + * Modifications to this file shall be clearly marked. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + *******************************************************************************************************/ + + +/** @addtogroup Keil + * @{ + */ + +/** @addtogroup FM33LC0XX + * @{ + */ + +#ifndef __FM33LC0XX_H +#define __FM33LC0XX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Configuration of the Cortex-M0 Processor and Core Peripherals + */ +#define __CM0_REV 0x0100U /*!< Cortex-M0 Core Revision */ +#define __MPU_PRESENT 0U /*!< MPU present or not */ +#define __VTOR_PRESENT 1U /*!< VTOR present or not */ +#define __NVIC_PRIO_BITS 2U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + + +/** + * @brief FM33LC0XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum { +/****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NMI_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/****** FM33LC0XX specific Interrupt Numbers ******************************************************************/ + WWDT_IRQn = 0, /*!< 0 Window WatchDog Interrupt */ + SVD_IRQn = 1, /*!< 1 SVD Interrupt */ + RTC_IRQn = 2, /*!< 2 RTC Interrupt */ + FLASH_IRQn = 3, /*!< 3 FLASH global Interrupt */ + LFDET_IRQn = 4, /*!< 4 LFDET Interrupt */ + ADC_IRQn = 5, /*!< 5 ADC Interrupt */ + IWDT_IRQn = 6, /*!< 6 IWDT Interrupt */ + SPI1_IRQn = 7, /*!< 7 SPI1 Interrupt */ + SPI2_IRQn = 8, /*!< 8 SPI2 Interrupt */ + LCD_IRQn = 9, /*!< 9 LCD Interrupt */ + UART0_IRQn = 10, /*!< 10 UART0 global Interrupt */ + UART1_IRQn = 11, /*!< 11 UART1 global Interrupt */ + UART4_IRQn = 12, /*!< 12 UART4 global Interrupt */ + UART5_IRQn = 13, /*!< 13 UART5 global Interrupt */ + HFDET_IRQn = 14, /*!< 14 HFDET Interrupt */ + U7816_IRQn = 15, /*!< 15 U7816 Interrupt */ + LPUART1_IRQn = 16, /*!< 16 LPUART1 Interrupt */ + I2C_IRQn = 17, /*!< 17 I2C global Interrupt */ + USB_IRQn = 18, /*!< 18 USB Interrupt */ + AES_IRQn = 19, /*!< 19 AES Interrupt */ + LPTIM_IRQn = 20, /*!< 20 LPTIM Interrupt */ + DMA_IRQn = 21, /*!< 21 DMA Interrupt */ + WKUP_IRQn = 22, /*!< 22 WKUP Interrupt */ + OPAx_IRQn = 23, /*!< 23 OPAx Interrupt */ + BSTIM_IRQn = 24, /*!< 24 BSTIM Interrupt */ + COMPx_IRQn = 25, /*!< 25 COMPx Interrupt */ + GPTIM0_IRQn = 26, /*!< 26 GTIM0 global Interrupt */ + GPTIM1_IRQn = 27, /*!< 27 GTIM1 global Interrupt */ + ATIM_IRQn = 28, /*!< 28 ATIM global Interrupt */ + VREF_IRQn = 29, /*!< 29 VREF Interrupt */ + GPIO_IRQn = 30, /*!< 30 GPIO Interrupt */ + LPUART0_IRQn = 31 /*!< 31 LPUART0 Interrupt */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + + +#include "core_cm0plus.h" /*!< Cortex-M0 processor and core peripherals */ +#include "system_fm33lc0xx.h" /*!< FM33LC0XX System */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC Control Register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Config Register, Address offset: 0x0C */ + __IO uint32_t SMTR; /*!< ADC Sampling Time Register, Address offset: 0x10 */ + __IO uint32_t CHER; /*!< ADC Channel Enable Register, Address offset: 0x14 */ + __IO uint32_t DR; /*!< ADC Data Register, Address offset: 0x18 */ + __IO uint32_t SAMPT; /*!< ADC Calibration Register, Address offset: 0x1C */ + __IO uint32_t HLTR; /*!< ADC analog watchdog Threshold Register, Address offset: 0x20 */ +} ADC_Type; + +typedef struct +{ + __IO uint32_t CR; /*!< AES Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t DIR; /*!< AES Data Input Register, Address offset: 0x0C */ + __IO uint32_t DOR; /*!< AES Data Output Register, Address offset: 0x10 */ + __IO uint32_t KEY0; /*!< AES Key Register 0, Address offset: 0x14 */ + __IO uint32_t KEY1; /*!< AES Key Register 1, Address offset: 0x18 */ + __IO uint32_t KEY2; /*!< AES Key Register 2, Address offset: 0x1C */ + __IO uint32_t KEY3; /*!< AES Key Register 3, Address offset: 0x20 */ + __IO uint32_t KEY4; /*!< AES Key Register 4, Address offset: 0x24 */ + __IO uint32_t KEY5; /*!< AES Key Register 5, Address offset: 0x28 */ + __IO uint32_t KEY6; /*!< AES Key Register 6, Address offset: 0x2C */ + __IO uint32_t KEY7; /*!< AES Key Register 7, Address offset: 0x30 */ + __IO uint32_t IVR0; /*!< AES Initial Vector Register 0, Address offset: 0x34 */ + __IO uint32_t IVR1; /*!< AES Initial Vector Register 1, Address offset: 0x38 */ + __IO uint32_t IVR2; /*!< AES Initial Vector Register 2, Address offset: 0x3C */ + __IO uint32_t IVR3; /*!< AES Initial Vector Register 3, Address offset: 0x40 */ +} AES_Type; + +typedef struct +{ + __IO uint32_t CR1; /*!< ATIM Control Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< ATIM Control Register2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< ATIM Slave Mode Control Register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< ATIM DMA and Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< ATIM Interrupt Status Register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< ATIM Event Generation Register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< ATIM Capture/Compare Mode Register1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< ATIM Capture/Compare Mode Register2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< ATIM Capture/Compare Enable Register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< ATIM Counter Register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< ATIM Prescaler Register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< ATIM Auto-Reload Register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< ATIM Repetition Counter Register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< ATIM Capture/Compare Register1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< ATIM Capture/Compare Register2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< ATIM Capture/Compare Register3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< ATIM Capture/Compare Register4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< ATIM Break and Deadtime Register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< ATIM DMA Control Register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< ATIM DMA Access Register, Address offset: 0x4C */ + __IO uint32_t RSV0; /*!< RESERVED REGISTER0, Address offset: 0x50 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER1, Address offset: 0x54 */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER2, Address offset: 0x58 */ + __IO uint32_t RSV3; /*!< RESERVED REGISTER3, Address offset: 0x5C */ + __IO uint32_t BKCR; /*!< ATIM Break Control Register, Address offset: 0x60 */ +} ATIM_Type; + +typedef struct +{ + __IO uint32_t CR1; /*!< BSTIM Control Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< BSTIM Control Register2, Address offset: 0x04 */ + __IO uint32_t RSV0; /*!< RESERVED REGISTER0, Address offset: 0x08 */ + __IO uint32_t IER; /*!< BSTIM Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< BSTIM Interrupt Status Register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< BSTIM Event Generation Register, Address offset: 0x14 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER1, Address offset: 0x18 */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER2, Address offset: 0x1C */ + __IO uint32_t RSV3; /*!< RESERVED REGISTER3, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< BSTIM Counter Register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< BSTIM Prescaler Register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< BSTIM Auto-Reload Register, Address offset: 0x2C */ +} BSTIM32_Type; + +typedef struct +{ + __IO uint32_t CR; /*!< ComparatorControl Register 1, Address offset: 0x00 */ + +} COMP_Type; + +typedef struct +{ + __IO uint32_t ICR; /*!< Comparator Interrupt Config Register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< Comparator Interrupt Status Register, Address offset: 0x0C */ +} COMP_COMMON_Type; + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< CRC Control Register, Address offset: 0x04 */ + __IO uint32_t LFSR; /*!< CRC Linear Feedback Shift Register, Address offset: 0x08 */ + __IO uint32_t XOR; /*!< CRC output XOR Register, Address offset: 0x0C */ + __IO uint32_t RSV0; /*!< RESERVED REGISTER0, Address offset: 0x10 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER1, Address offset: 0x14 */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER2, Address offset: 0x18 */ + __IO uint32_t POLY; /*!< CRC Polynominal Register, Address offset: 0x1C */ +} CRC_Type; + +typedef struct +{ + __IO uint32_t RSV; + __IO uint32_t CR; /*!< Debug Configuration Register */ + __IO uint32_t HDFR; /*!< HardFault Flag Register*/ + +} DBG_Type; + +typedef struct +{ + __IO uint32_t GCR; /*!< DMA Global Control Register , Address offset: 0x00 */ + __IO uint32_t CH0CR; /*!< Channel 0 Control Register , Address offset: 0x04 */ + __IO uint32_t CH0MAD; /*!< Channel 0 Memory Address Register , Address offset: 0x08 */ + __IO uint32_t CH1CR; /*!< Channel 1 Control Register , Address offset: 0x0C */ + __IO uint32_t CH1MAD; /*!< Channel 1 Memory Address Register , Address offset: 0x10 */ + __IO uint32_t CH2CR; /*!< Channel 2 Control Register , Address offset: 0x14 */ + __IO uint32_t CH2MAD; /*!< Channel 2 Memory Address Register , Address offset: 0x18 */ + __IO uint32_t CH3CR; /*!< Channel 3 Control Register , Address offset: 0x1C */ + __IO uint32_t CH3MAD; /*!< Channel 3 Memory Address Register , Address offset: 0x20 */ + __IO uint32_t CH4CR; /*!< Channel 4 Control Register , Address offset: 0x24 */ + __IO uint32_t CH4MAD; /*!< Channel 4 Memory Address Register , Address offset: 0x28 */ + __IO uint32_t CH5CR; /*!< Channel 5 Control Register , Address offset: 0x2C */ + __IO uint32_t CH5MAD; /*!< Channel 5 Memory Address Register , Address offset: 0x30 */ + __IO uint32_t CH6CR; /*!< Channel 6 Control Register , Address offset: 0x34 */ + __IO uint32_t CH6MAD; /*!< Channel 6 Memory Address Register , Address offset: 0x38 */ + __IO uint32_t CH7CR; /*!< Channel 7 Control Register , Address offset: 0x3C */ + __IO uint32_t CH7FLSAD; /*!< Channel 7 Flash Address Register , Address offset: 0x40 */ + __IO uint32_t CH7RAMAD; /*!< Channel 7 RAM Address Register , Address offset: 0x44 */ + __IO uint32_t ISR; /*!< DMA Interrupt Status Register , Address offset: 0x48 */ +} DMA_Type; + +typedef struct +{ + __IO uint32_t IER; /*!< XTLF Oscillation Fail Detection Interrupt Enable Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< XTLF Oscillation Fail Detection Interrupt Status Register, Address offset: 0x04 */ +}FDET_Type; + + +typedef struct +{ + __IO uint32_t RDCR; /*!< Flash Read Control Register, Address offset: 0x00 */ + __IO uint32_t PFCR; /*!< Flash Prefetch Control Register, Address offset: 0x04 */ + __I uint32_t OPTBR; /*!< Flash Option Bytes Register, Address offset: 0x08 */ + __IO uint32_t ACLOCK1; /*!< Flash Application Code Lock Register 1, Address offset: 0x0C */ + __IO uint32_t ACLOCK2; /*!< Flash Application Code Lock Register 2, Address offset: 0x10 */ + __IO uint32_t EPCR; /*!< Flash Erase/Program Control Register, Address offset: 0x14 */ + __IO uint32_t KEY; /*!< Flash Key Register, Address offset: 0x18 */ + __IO uint32_t IER; /*!< Flash Interrupt Enable Register, Address offset: 0x1C */ + __IO uint32_t ISR; /*!< Flash Interrupt Status Register, Address offset: 0x20 */ +} FLASH_Type; + +typedef struct +{ + __IO uint32_t INEN; /*!< Input Enable Register */ + __IO uint32_t PUEN; /*!< Pull-Up Enable Register */ + __IO uint32_t ODEN; /*!< Open-Drain Enable Register */ + __IO uint32_t FCR; /*!< Function Control Register */ + __IO uint32_t DO; /*!< Data Output Register */ + __O uint32_t DSET; /*!< Data Set Register */ + __O uint32_t DRST; /*!< Data Reset Register */ + __I uint32_t DIN; /*!< Data Input RegisterR */ + __IO uint32_t DFS; /*!< Digital Function Select */ + __IO uint32_t RSV; /*!< RESERVED REGISTER */ + __IO uint32_t ANEN; /*!< Analog channel Enable Register */ +} GPIO_Type; + +typedef struct +{ + __IO uint32_t EXTISEL; /*!< External Interrupt input Select Register */ + __IO uint32_t EXTIEDS; /*!< External Interrupt Edge Select and Enable Register */ + __IO uint32_t EXTIDF; /*!< External Interrupt Digital Filter Register */ + __IO uint32_t EXTIISR; /*!< External Interrupt and Status Register */ + __IO uint32_t EXTIDI; /*!< External Interrupt Data Input Register */ + __IO uint32_t RSV0[59]; /*!< RESERVED REGISTER */ + __IO uint32_t FOUTSEL; /*!< Frequency Output Select Register */ + __IO uint32_t RSV1[63]; /*!< RESERVED REGISTER */ + __IO uint32_t PINWKEN; /*!< Wakeup Enable Register */ +} GPIO_COMMON_Type; + +typedef struct +{ + __IO uint32_t CR1; /*!< GPTIM Control Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< GPTIM Control Register2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< GPTIM Slave Mode Control Register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< GPTIM DMA and Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< GPTIM Interrupt Status Register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< GPTIM EVENT GENERATE REGISTER, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< GPTIM Capture/Compare Mode Register1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< GPTIM Capture/Compare Mode Register2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< GPTIM Capture/Compare Enable Register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< GPTIM Counter Register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< GPTIM Prescaler Register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< GPTIM Auto-Reload Register, Address offset: 0x2C */ + __IO uint32_t RSV0; /*!< RESERVED REGISTER0, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< GPTIM Capture/Compare Register1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< GPTIM Capture/Compare Register2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< GPTIM Capture/Compare Register3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< GPTIM Capture/Compare Register4, Address offset: 0x40 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER1, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< GPTIM DMA CONTROL REGISTER, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< GPTIM DMA access Register, Address offset: 0x4C */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER2, Address offset: 0x50 */ + __IO uint32_t RSV3; /*!< RESERVED REGISTER3, Address offset: 0x54 */ + __IO uint32_t RSV4; /*!< RESERVED REGISTER4, Address offset: 0x58 */ + __IO uint32_t RSV5; /*!< RESERVED REGISTER5, Address offset: 0x5C */ + __IO uint32_t ITRSEL; /*!< GPTIM Internal Trigger Select Register, Address offset: 0x60 */ +} GPTIM_Type; + +typedef struct +{ + __IO uint32_t END; /*!< Dividend Register, Address offset: 0x00 */ + __IO uint32_t SOR; /*!< Divisor Regsiter, Address offset: 0x04 */ + __IO uint32_t QUOT; /*!< Quotient Register, Address offset: 0x08 */ + __IO uint32_t REMD; /*!< Reminder Register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< Status Register, Address offset: 0x10 */ +} DIV_Type; + + +typedef struct +{ + __IO uint32_t MSPCFGR; /*!< I2C Master Config Register, Address offset: 0x00 */ + __IO uint32_t MSPCR; /*!< I2C Master Control Register, Address offset: 0x04 */ + __IO uint32_t MSPIER; /*!< I2C Master Intterupt Enable Register, Address offset: 0x08 */ + __IO uint32_t MSPISR; /*!< I2C Master Interrupt Status Register, Address offset: 0x0C */ + __IO uint32_t MSPSR; /*!< I2C Master Status Register, Address offset: 0x10 */ + __IO uint32_t MSPBGR; /*!< I2C Master Baud rate Generator Register, Address offset: 0x14 */ + __IO uint32_t MSPBUF; /*!< I2C Master transfer Buffer, Address offset: 0x18 */ + __IO uint32_t MSPTCR; /*!< I2C Master Timing Control Register, Address offset: 0x1C */ + __IO uint32_t MSPTOR; /*!< I2C Master Time-Out Register, Address offset: 0x20 */ + __IO uint32_t SSPCR; /*!< I2C Slave Control Register, Address offset: 0x24 */ + __IO uint32_t SSPIER; /*!< I2C Slave Interrupt Enable Register, Address offset: 0x28 */ + __IO uint32_t SSPISR; /*!< I2C Slave Interrupt Status Register, Address offset: 0x2C */ + __IO uint32_t SSPSR; /*!< I2C Slave Status Register, Address offset: 0x30 */ + __IO uint32_t SSPBUF; /*!< I2C Slave transfer Buffer, Address offset: 0x34 */ + __IO uint32_t SSPADR; /*!< I2C Slave Address Register, Address offset: 0x38 */ +} I2C_Type; + +typedef struct +{ + __IO uint32_t SERV; /*!< IWDT Service Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< IWDT Config Register, Address offset: 0x04 */ + __I uint32_t CNT; /*!< IWDT Counter Register, Address offset: 0x08 */ + __IO uint32_t WIN; /*!< IWDT Window Register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< IWDT Status Register, Address offset: 0x10 */ + __IO uint32_t ISR; /*!< IWDT Status Register, Address offset: 0x10 */ +} IWDT_Type; + +typedef struct +{ + __IO uint32_t CR; /*!< LCD Control Register, Address offset: 0x00 */ + __IO uint32_t TEST; /*!< LCD test Register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< LCD Frequency Control Register, Address offset: 0x08 */ + __IO uint32_t FLKT; /*!< LCD Flick Time Register, Address offset: 0x0C */ + __IO uint32_t RSV0; /*!< NULL, Address offset: 0x10 */ + __IO uint32_t IER; /*!< LCD Interrupt Enable Register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< LCD Interrupt Status Register, Address offset: 0x18 */ + __IO uint32_t RSV1; /*!< NULL, Address offset: 0x1C */ + __IO uint32_t RSV2; /*!< NULL, Address offset: 0x20 */ + __IO uint32_t DATA0; /*!< LCD data buffer registers 0, Address offset: 0x24 */ + __IO uint32_t DATA1; /*!< LCD data buffer registers 1, Address offset: 0x28 */ + __IO uint32_t DATA2; /*!< LCD data buffer registers 2, Address offset: 0x2C */ + __IO uint32_t DATA3; /*!< LCD data buffer registers 3, Address offset: 0x30 */ + __IO uint32_t DATA4; /*!< LCD data buffer registers 4, Address offset: 0x34 */ + __IO uint32_t DATA5; /*!< LCD data buffer registers 5, Address offset: 0x38 */ + __IO uint32_t DATA6; /*!< LCD data buffer registers 6, Address offset: 0x3C */ + __IO uint32_t DATA7; /*!< LCD data buffer registers 7, Address offset: 0x40 */ + __IO uint32_t RSV3; /*!< NULL, Address offset: 0x44 */ + __IO uint32_t RSV4; /*!< NULL, Address offset: 0x48 */ + __IO uint32_t RSV5; /*!< NULL, Address offset: 0x4C */ + __IO uint32_t COMEN; /*!< LCD COM Enable Register, Address offset: 0x50 */ + __IO uint32_t SEGEN0; /*!< LCD SEG Enable Register0, Address offset: 0x54 */ +} LCD_Type; + +typedef struct +{ + __IO uint32_t CFGR; /*!< LPTIM Config Register, Address offset: 0x00 */ + __IO uint32_t CNT; /*!< LPTIM Counter Register, Address offset: 0x04 */ + __IO uint32_t CCSR; /*!< LPTIM Capture/Compare Control and Status Register, Address offset: 0x08 */ + __IO uint32_t ARR; /*!< LPTIM Auto-Reload Register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable Register, Address offset: 0x10 */ + __IO uint32_t ISR; /*!< LPTIM Interrupt Status Register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< LPTIM Control Register, Address offset: 0x18 */ + __IO uint32_t RSV; /*!< RESERVED REGISTER, Address offset: 0x1C */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare Register1, Address offset: 0x20 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare Register2, Address offset: 0x24 */ +} LPTIM32_Type; + +typedef struct +{ + __IO uint32_t CSR; /*!< LPUART Control Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< LPUART Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< LPUART Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t BMR; /*!< LPUART Baud rate Modulation Register, Address offset: 0x0C */ + __IO uint32_t RXBUF; /*!< LPUART Receive Buffer Register, Address offset: 0x10 */ + __IO uint32_t TXBUF; /*!< LPUART Transmit Buffer Register, Address offset: 0x14 */ + __IO uint32_t DMR; /*!< LPUART data Matching Register, Address offset: 0x18 */ +} LPUART_Type; + + +typedef struct +{ + __IO uint32_t CR; /*!< OPA Control Register */ + __IO uint32_t CALR; /*!< OPA Calibration Register */ + __IO uint32_t IER; /*!< OPA Interrupt Enable Register */ + __IO uint32_t ISR; /*!< OPA Interrupt Status Register */ +} OPA_Type; + +typedef struct +{ + __IO uint32_t CR; /*!< Power Management Control Register */ + __IO uint32_t WKTR; /*!< Wakeup Time Register */ + __IO uint32_t WKFR; /*!< Wakeup Source Flags Register */ + __IO uint32_t IER; /*!< PMU Interrupt Enable Register */ + __IO uint32_t ISR; /*!< PMU Interrupt and Status Register */ +} PMU_Type; + +typedef struct +{ + __IO uint32_t LKPCR; /*!< Lockup reset Control Register , Address offset: 0x00 */ + __IO uint32_t SOFTRST; /*!< Software Reset Register , Address offset: 0x04 */ + __IO uint32_t RSTFR; /*!< Reset Flag Register , Address offset: 0x08 */ + __IO uint32_t SYSCLKCR; /*!< System Clock Control Register , Address offset: 0x0C */ + __IO uint32_t RCHFCR; /*!< RCHF Control Register , Address offset: 0x10 */ + __IO uint32_t RCHFTR; /*!< RCHF Trim Register , Address offset: 0x14 */ + __IO uint32_t PLLCR; /*!< PLL Control Register , Address offset: 0x18 */ + __IO uint32_t LPOSCCR; /*!< LPOSC Control Register , Address offset: 0x1C */ + __IO uint32_t LPOSCTR; /*!< LPOSC Trim Register , Address offset: 0x20 */ + __IO uint32_t XTLFCR; /*!< XTLF CONFIG REGISTER , Address offset: 0x24 */ + __IO uint32_t PCLKCR1; /*!< Peripheral bus Clock Control Register1 , Address offset: 0x28 */ + __IO uint32_t PCLKCR2; /*!< Peripheral bus Clock Control Register2 , Address offset: 0x2C */ + __IO uint32_t PCLKCR3; /*!< Peripheral bus Clock Control Register3 , Address offset: 0x30 */ + __IO uint32_t PCLKCR4; /*!< Peripheral bus Clock Control Register4 , Address offset: 0x34 */ + __IO uint32_t LSCLKSEL; /*!< LSCLK Select Register , Address offset: 0x38 */ + __IO uint32_t RSV0; /*!< RESERVED REGISTER 1 , Address offset: 0x3C */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER 2 , Address offset: 0x40 */ + __IO uint32_t AHBMCR; /*!< AHB Master Control Register , Address offset: 0x44 */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER 3 , Address offset: 0x48 */ + __IO uint32_t RSV3; /*!< RESERVED REGISTER 4 , Address offset: 0x4C */ + __IO uint32_t PRSTEN; /*!< Peripheral Reset Enable Register , Address offset: 0x50 */ + __IO uint32_t AHBRSTCR; /*!< AHB Peripherals Reset Control Register , Address offset: 0x54 */ + __IO uint32_t APBRSTCR1; /*!< APB Peripherals Reset Control Register1 , Address offset: 0x58 */ + __IO uint32_t APBRSTCR2; /*!< APB Peripherals Reset Control Register2 , Address offset: 0x5C */ + __IO uint32_t XTHFCR; /*!< XTHF Control Register , Address offset: 0x60 */ + __IO uint32_t RCMFCR; /*!< RCMF Control Register , Address offset: 0x64 */ + __IO uint32_t RCMFTR; /*!< RCHF Trim Register , Address offset: 0x68 */ + __IO uint32_t OPCCR1; /*!< Peripheral Operation Clock Control Register1, Address offset: 0x6C */ + __IO uint32_t OPCCR2; /*!< Peripheral Operation Clock Control Register2, Address offset: 0x70 */ + __IO uint32_t PHYCR; /*!< PHY Control Register , Address offset: 0x74 */ + __IO uint32_t PHYBCKCR; /*!< PHY BCK Control Register , Address offset: 0x78 */ +} RCC_Type; + + +typedef struct +{ + __IO uint32_t PDRCR; /*!< PDR Control Register */ + __IO uint32_t BORCR; /*!< BOR Control Register */ +} RMU_Type; + +typedef struct +{ + __IO uint32_t CR; /*!< RNG CONTROL REGISTER, */ +} RNGCTL_Type; + +typedef struct +{ + __IO uint32_t RSV0; /*!< RESERVED REGISTER, Address offset: 0x00 */ + __IO uint32_t DOR; /*!< RNG OUTPUT REGISTER, Address offset: 0x04 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x08 */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER, Address offset: 0x0C */ + __IO uint32_t SR; /*!< RNG FLAG REGISTER, Address offset: 0x10 */ + __IO uint32_t CRCCR; /*!< RNG CRC CONTROL REGISTER, Address offset: 0x14 */ + __IO uint32_t CRCDIR; /*!< RNG CRC INPUT REGISTER, Address offset: 0x18 */ + __IO uint32_t CRCSR; /*!< RNG CRC FLAG REGISTER, Address offset: 0x1C */ +} RNG_Type; + +typedef struct +{ + __IO uint32_t WER; /*!< RTC Write Enable Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< RTC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< RTC Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t BCDSEC; /*!< RTC SECOND IN BCD REGISTER, Address offset: 0x0C */ + __IO uint32_t BCDMIN; /*!< RTC MINITE IN BCD REGISTER, Address offset: 0x10 */ + __IO uint32_t BCDHOUR; /*!< RTC HOUR IN BCD REGISTER, Address offset: 0x14 */ + __IO uint32_t BCDDAY; /*!< RTC DAY IN BCD REGISTER, Address offset: 0x18 */ + __IO uint32_t BCDWEEK; /*!< RTC WEEK IN BCD REGISTER, Address offset: 0x1C */ + __IO uint32_t BCDMONTH; /*!< RTC MONTH IN BCD REGISTER, Address offset: 0x20 */ + __IO uint32_t BCDYEAR; /*!< RTC YEAR IN BCD REGISTER, Address offset: 0x24 */ + __IO uint32_t ALARM; /*!< RTC Alarm Register, Address offset: 0x28 */ + __IO uint32_t TMSEL; /*!< RTC Time Mark Select, Address offset: 0x2C */ + __IO uint32_t ADJUST; /*!< RTC time Adjust Register, Address offset: 0x30 */ + __IO uint32_t ADSIGN; /*!< RTC time Adjust Sign Register, Address offset: 0x34 */ + __IO uint32_t RSV0; /*!< NULL, Address offset: 0x38 */ + __IO uint32_t SBSCNT; /*!< RTC Sub-Second Counter, Address offset: 0x3C */ + __IO uint32_t RSV1[12]; /*!< NULL, Address offset: 0x40 */ + __IO uint32_t BKR0; /*!< RTC BACKUP REGISTER0, Address offset: 0x70 */ + __IO uint32_t BKR1; /*!< RTC BACKUP REGISTER1, Address offset: 0x74 */ + __IO uint32_t BKR2; /*!< RTC BACKUP REGISTER2, Address offset: 0x78 */ + __IO uint32_t BKR3; /*!< RTC BACKUP REGISTER3, Address offset: 0x7C */ + __IO uint32_t BKR4; /*!< RTC BACKUP REGISTER4, Address offset: 0x80 */ + __IO uint32_t BKR5; /*!< RTC BACKUP REGISTER5, Address offset: 0x84 */ + __IO uint32_t BKR6; /*!< RTC BACKUP REGISTER6, Address offset: 0x88 */ + __IO uint32_t BKR7; /*!< RTC BACKUP REGISTER7, Address offset: 0x8C */ +} RTC_Type; + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI1 Control Register1 */ + __IO uint32_t CR2; /*!< SPI1 Control Register2 */ + __IO uint32_t CR3; /*!< SPI1 Control Register3 */ + __IO uint32_t IER; /*!< SPI1 Interrupt Enable Register */ + __IO uint32_t ISR; /*!< SPI1 Status Register */ + __IO uint32_t TXBUF; /*!< SPI1 Transmit Buffer */ + __IO uint32_t RXBUF; /*!< SPI1 Receive Buffer */ +} SPI_Type; + + +typedef struct +{ + __IO uint32_t CFGR; /*!< SVD Config Register, Address offset: 0x24 */ + __IO uint32_t CR; /*!< SVD Control Register, Address offset: 0x28 */ + __IO uint32_t IER; /*!< SVD Interrupt Enable Register, Address offset: 0x2C */ + __IO uint32_t ISR; /*!< SVD Interrupt Status Register, Address offset: 0x30 */ + __IO uint32_t VSR; /*!< SVD reference Voltage Select Register, Address offset: 0x34 */ +} SVD_Type; + +typedef struct +{ + __IO uint32_t CR; /*!< U7816 Control Register, Address offset: 0x00 */ + __IO uint32_t FFR; /*!< U7816 Frame Format Register, Address offset: 0x04 */ + __IO uint32_t EGTR; /*!< U7816 Extra Guard Time Register, Address offset: 0x08 */ + __IO uint32_t PSC; /*!< U7816 Prescaler Register, Address offset: 0x0C */ + __IO uint32_t BGR; /*!< U7816 Baud rate Generator Register, Address offset: 0x10 */ + __IO uint32_t RXBUF; /*!< U7816 Receive Buffer, Address offset: 0x14 */ + __IO uint32_t TXBUF; /*!< U7816 Transmit Buffer, Address offset: 0x18 */ + __IO uint32_t IER; /*!< U7816 Interrupt Enable Register, Address offset: 0x1C */ + __IO uint32_t ISR; /*!< U7816 Interrupt Status Register, Address offset: 0x20 */ +} U7816_Type; + +typedef struct +{ + __IO uint32_t RSV0; /*!< RESERVED REGISTER0, Address offset: 0x00 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER1, Address offset: 0x04 */ + __IO uint32_t GAHBCFG; /*!< USB AHB Global Config Register, Address offset: 0x08 */ + __IO uint32_t GUSBCFG; /*!< USB Global Config Register, Address offset: 0x0C */ + __IO uint32_t GRSTCTL; /*!< USB Global Reset Control Register, Address offset: 0x10 */ + __IO uint32_t GINTSTS; /*!< USB Global Interrupt Status Register, Address offset: 0x14 */ + __IO uint32_t GINTMSK; /*!< USB Global Interrupt Mask Register, Address offset: 0x18 */ + __IO uint32_t GRXSTSR; /*!< USB Receive Status Debug Read Register, Address offset: 0x1C */ + __IO uint32_t GRXSTSP; /*!< USB Receive Status and Pop Register, Address offset: 0x20 */ + __IO uint32_t GRXFSIZ; /*!< USB Receive FIFO size Register, Address offset: 0x24 */ + __IO uint32_t GNPTXFSIZ; /*!< USB Non-Periodic Transmit FIFO size Register, Address offset: 0x28 */ + __IO uint32_t RSV2[10]; /*!< Reserved */ + __IO uint32_t GLPMCFG; /*!< USB Low-Power-Mode config Register, Address offset: 0x54 */ + __IO uint32_t RSV3[490]; /*!< Reserved */ + __IO uint32_t DCFG; /*!< USB Device Config Register, Address offset: 0x800*/ + __IO uint32_t DCTL; /*!< USB Device Control Register, Address offset: 0x804*/ + __IO uint32_t DSTS; /*!< USB Device Status Register, Address offset: 0x808*/ + __IO uint32_t DIEPMSK; /*!< USB Device In Endpoint Interrupt Mask Register, Address offset: 0x810*/ + __IO uint32_t DOEPMSK; /*!< USB Device OUT Endpoint Interrupt Mask Registe, Address offset: 0x814*/ + __IO uint32_t DAINT; /*!< USB Device All Endpoint Interrupt Register, Address offset: 0x818*/ + __IO uint32_t DAINTMSK; /*!< USB Device All Endpoint Interrupt Mask Register, Address offset: 0x81C*/ + __IO uint32_t RSV4[5]; /*!< Reserved */ + __IO uint32_t DIEPEMPMSK; /*!< USB Device IN endpoint FIFO empty interrupt Mask Register,Address offset: 0x834 */ + __IO uint32_t RSV5[50]; /*!< Reserved */ + __IO uint32_t DIEPCTL0; /*!< USB Device In Endpoint 0 Control Register, Address offset: 0x900*/ + __IO uint32_t RSV6; /*!< Reserved */ + __IO uint32_t DIEPINT0; /*!< USB Device In Endpoint 0 Interrupt Register, Address offset: 0x908*/ + __IO uint32_t RSV7; /*!< Reserved */ + __IO uint32_t DIEPTSIZ0; /*!< USB Device IN Endpoint 0 Transfer Size Register, Address offset: 0x910*/ + __IO uint32_t RSV8; /*!< Reserved */ + __IO uint32_t DTXFSTS0; /*!< USB Device In Endpoint 0 Tranmit FIFO Status Register,Address offset: 0x918 */ + __IO uint32_t RSV9; /*!< Reserved */ + __IO uint32_t DIEPCTL1; /*!< USB Device In Endpoint 1 Control Register, Address offset: 0x920*/ + __IO uint32_t RSV10; /*!< Reserved */ + __IO uint32_t DIEPINT1; /*!< USB Device In Endpoint 1 Interrupt Register, Address offset: 0x928*/ + __IO uint32_t RSV11; /*!< Reserved */ + __IO uint32_t DIEPTSIZ1; /*!< USB Device IN Endpoint 1 Transfer Size Register, Address offset: 0x930*/ + __IO uint32_t RSV12; /*!< Reserved */ + __IO uint32_t DTXFSTS1; /*!< USB Device In Endpoint 1 Tranmit FIFO Status Register,Address offset: 0x938 */ + __IO uint32_t RSV13; /*!< Reserved */ + __IO uint32_t DIEPCTL2; /*!< USB Device In Endpoint 2 Control Register, Address offset: 0x940*/ + __IO uint32_t RSV14; /*!< Reserved */ + __IO uint32_t DIEPINT2; /*!< USB Device In Endpoint 2 Interrupt Register, Address offset: 0x948*/ + __IO uint32_t RSV15; /*!< Reserved */ + __IO uint32_t DIEPTSIZ2; /*!< USB Device In Endpoint 2 Tranmit FIFO Status Register,Address offset: 0x950 */ + __IO uint32_t RSV16; /*!< Reserved */ + __IO uint32_t DTXFSTS2; /*!< USB Device In Endpoint 2 Tranmit FIFO Status Register,Address offset: 0x958 */ + __IO uint32_t RSV17[105]; /*!< Reserved */ + __IO uint32_t DOEPCTL0; /*!< USB Device Out Endpoint 0 Control Register, Address offset: 0xB00*/ + __IO uint32_t RSV18; /*!< Reserved */ + __IO uint32_t DOEPINT0; /*!< USB Device Out Endpoint 0 Interrupt Register, Address offset: 0xB08*/ + __IO uint32_t RSV19; /*!< Reserved */ + __IO uint32_t DOEPTSIZ0; /*!< USB Device Out Endpoint 0 Transfer Size Register, Address offset: 0xB10*/ + __IO uint32_t RSV20; /*!< Reserved */ + __IO uint32_t RSV21; /*!< Reserved */ + __IO uint32_t RSV22; /*!< Reserved */ + __IO uint32_t DOEPCTL1; /*!< USB Device Out Endpoint 1 Control Register, Address offset: 0xB20*/ + __IO uint32_t RSV23; /*!< Reserved */ + __IO uint32_t DOEPINT1; /*!< USB Device Out Endpoint 1 Interrupt Register, Address offset: 0xB28*/ + __IO uint32_t RSV24; /*!< Reserved */ + __IO uint32_t DOEPTSIZ1; /*!< USB Device Out Endpoint 1 Transfer Size Register, Address offset: 0xB30*/ + __IO uint32_t RSV25; /*!< Reserved */ + __IO uint32_t RSV26; /*!< Reserved */ + __IO uint32_t RSV27; /*!< Reserved */ + __IO uint32_t DOEPCTL2; /*!< USB Device Out Endpoint 2 Control Register, Address offset: 0xB40*/ + __IO uint32_t RSV28; /*!< Reserved */ + __IO uint32_t DOEPINT2; /*!< USB Device Out Endpoint 2 Interrupt Register, Address offset: 0xB48*/ + __IO uint32_t RSV29; /*!< Reserved */ + __IO uint32_t DOEPTSIZ2; /*!< USB Device Out Endpoint 2 Transfer Size Register, Address offset: 0xB50*/ + __IO uint32_t RSV30[171]; /*!< Reserved */ + __IO uint32_t PCGCCTL; /*!< USB Power Control Global Control Register, Address offset: 0xE00*/ +} USB_Type; + +typedef struct +{ + __IO uint32_t IRCR; /*!< Infrared modulation Control Register */ +} UART_COMMON_Type; + +typedef struct +{ + __IO uint32_t CSR; /*!< UART Control Status Register */ + __IO uint32_t IER; /*!< UART Interrupt Enable Register */ + __IO uint32_t ISR; /*!< UART Interrupt Status Register */ + __IO uint32_t TODR; /*!< UART Time-Out and Delay Register */ + __IO uint32_t RXBUF; /*!< UART Receive Buffer */ + __IO uint32_t TXBUF; /*!< UART Transmit Buffer */ + __IO uint32_t BGR; /*!< UART Baud rate Generator Register */ +} UART_Type; + + +typedef struct +{ + __IO uint32_t CR; /*!< VREF Control Register */ + __IO uint32_t SR; /*!< VREF Status Register */ + __IO uint32_t IER; /*!< VREF Interrupt Enable Register */ + __IO uint32_t BUFCR; /*!< VREF Interrupt Enable Register */ +} VREF_Type; + +typedef struct +{ + __IO uint32_t CR; /*!< WWDT Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< WWDT Config Register, Address offset: 0x04 */ + __IO uint32_t CNT; /*!< WWDT Counter Register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< WWDT Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< WWDT Interrupt Status Register, Address offset: 0x10 */ + __IO uint32_t PSC; /*!< WWDT Prescaler Register, Address offset: 0x14 */ +} WWDT_Type; + + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE 0x00000000UL /*!< FLASH(up to 1 MB) base address in the alias region */ +#define SRAM_BASE 0x20000000UL +#define PERIPH_BASE 0x40000000UL + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +/*!< Peripheral memory map */ +#define DBG_BASE (PERIPH_BASE + 0x00000000UL) +#define PMU_BASE (PERIPH_BASE + 0x00000100UL) +#define RCC_BASE (PERIPH_BASE + 0x00000200UL) +#define DMA_BASE (PERIPH_BASE + 0x00000400UL) +#define GPIOA_BASE (PERIPH_BASE + 0x00000C00UL) +#define GPIOB_BASE (PERIPH_BASE + 0x00000C40UL) +#define GPIOC_BASE (PERIPH_BASE + 0x00000C80UL) +#define GPIOD_BASE (PERIPH_BASE + 0x00000CC0UL) +#define GPIO_COMMON_BASE (PERIPH_BASE + 0x00000D00UL) +#define FLASH_R_BASE (PERIPH_BASE + 0x00001000UL) +#define U7816_BASE (PERIPH_BASE + 0x00010000UL) +#define LPUART0_BASE (PERIPH_BASE + 0x00010400UL) +#define SPI2_BASE (PERIPH_BASE + 0x00010800UL) +#define LCD_BASE (PERIPH_BASE + 0x00010C00UL) +#define RTC_BASE (PERIPH_BASE + 0x00011000UL) +#define IWDT_BASE (PERIPH_BASE + 0x00011400UL) +#define WWDT_BASE (PERIPH_BASE + 0x00011800UL) +#define UART0_BASE (PERIPH_BASE + 0x00011C00UL) +#define UART1_BASE (PERIPH_BASE + 0x00012000UL) +#define I2C_BASE (PERIPH_BASE + 0x00012400UL) +#define LPTIM32_BASE (PERIPH_BASE + 0x00013400UL) +#define GPTIM0_BASE (PERIPH_BASE + 0x00013800UL) +#define GPTIM1_BASE (PERIPH_BASE + 0x00013C00UL) +#define CRC_BASE (PERIPH_BASE + 0x00018000UL) +#define LPUART1_BASE (PERIPH_BASE + 0x00018400UL) +#define SPI1_BASE (PERIPH_BASE + 0x00018C00UL) +#define DIVAS_BASE (PERIPH_BASE + 0x00019000UL) +#define UART_COMMON_BASE (PERIPH_BASE + 0x00019C00UL) +#define UART4_BASE (PERIPH_BASE + 0x0001A000UL) +#define UART5_BASE (PERIPH_BASE + 0x0001A400UL) +#define RMU_BASE (PERIPH_BASE + 0x0001A800UL) +#define VREF_BASE (PERIPH_BASE + 0x0001A80CUL) +#define SVD_BASE (PERIPH_BASE + 0x0001A824UL) +#define FDET_BASE (PERIPH_BASE + 0x0001A838UL) +#define OPA1_BASE (PERIPH_BASE + 0x0001A844UL) +#define OPA2_BASE (PERIPH_BASE + 0x0001A854UL) +#define RNGCTL_BASE (PERIPH_BASE + 0x0001A868UL) +#define COMP1_BASE (PERIPH_BASE + 0x0001A870UL) +#define COMP2_BASE (PERIPH_BASE + 0x0001A874UL) +#define COMP_COMMON_BASE (PERIPH_BASE + 0x0001A878UL) +#define ADC_BASE (PERIPH_BASE + 0x0001AC00UL) +#define AES_BASE (PERIPH_BASE + 0x0001B800UL) +#define RNG_BASE (PERIPH_BASE + 0x0001BC00UL) +#define ATIM_BASE (PERIPH_BASE + 0x0001B000UL) +#define BSTIM32_BASE (PERIPH_BASE + 0x0001B400UL) +#define USB_BASE (PERIPH_BASE + 0x10000000UL) +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define DBG ((DBG_Type *) DBG_BASE) +#define PMU ((PMU_Type *) PMU_BASE) +#define VREF ((VREF_Type *) VREF_BASE) +#define RCC ((RCC_Type *) RCC_BASE) +#define RMU ((RMU_Type *) RMU_BASE) +#define DMA ((DMA_Type *) DMA_BASE) +#define GPIOA ((GPIO_Type *) GPIOA_BASE) +#define GPIOB ((GPIO_Type *) GPIOB_BASE) +#define GPIOC ((GPIO_Type *) GPIOC_BASE) +#define GPIOD ((GPIO_Type *) GPIOD_BASE) +#define GPIO ((GPIO_COMMON_Type *) GPIO_COMMON_BASE) +#define FLASH ((FLASH_Type *) FLASH_R_BASE) +#define CRC ((CRC_Type *) CRC_BASE) +#define LPUART0 ((LPUART_Type *) LPUART0_BASE) +#define LPUART1 ((LPUART_Type *) LPUART1_BASE) +#define SPI1 ((SPI_Type *) SPI1_BASE) +#define SPI2 ((SPI_Type *) SPI2_BASE) +#define LCD ((LCD_Type *) LCD_BASE) +#define RTC ((RTC_Type *) RTC_BASE) +#define IWDT ((IWDT_Type *) IWDT_BASE) +#define WWDT ((WWDT_Type *) WWDT_BASE) +#define U7816 ((U7816_Type *) U7816_BASE) +#define UART ((UART_COMMON_Type *) UART_COMMON_BASE) +#define UART0 ((UART_Type *) UART0_BASE) +#define UART1 ((UART_Type *) UART1_BASE) +#define UART4 ((UART_Type *) UART4_BASE) +#define UART5 ((UART_Type *) UART5_BASE) +#define I2C ((I2C_Type *) I2C_BASE) +#define FDET ((FDET_Type *) FDET_BASE) +#define SVD ((SVD_Type *) SVD_BASE) +#define OPA1 ((OPA_Type *) OPA1_BASE) +#define OPA2 ((OPA_Type *) OPA2_BASE) +#define LPTIM32 ((LPTIM32_Type *) LPTIM32_BASE) +#define AES ((AES_Type *) AES_BASE) +#define RNG ((RNG_Type *) RNG_BASE) +#define RNGCTL ((RNGCTL_Type *) RNGCTL_BASE) +#define ATIM ((ATIM_Type *) ATIM_BASE) +#define GPTIM0 ((GPTIM_Type *) GPTIM0_BASE) +#define GPTIM1 ((GPTIM_Type *) GPTIM1_BASE) +#define BSTIM32 ((BSTIM32_Type *) BSTIM32_BASE) +#define ADC ((ADC_Type *) ADC_BASE) +#define COMP1 ((COMP_Type *) COMP1_BASE) +#define COMP2 ((COMP_Type *) COMP2_BASE) +#define COMP ((COMP_COMMON_Type*)COMP_COMMON_BASE) +#define DIV ((DIV_Type *) DIVAS_BASE) +#define USB ((USB_Type *) USB_BASE) +/* ================================================================================ */ +/* ================ Peripheral include ================ */ +/* ================================================================================ */ + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group FM33LC0XX */ +/** @} */ /* End of group Keil */ + +#ifdef __cplusplus +} +#endif + +#endif /* FM33LC0XX_H */ diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33lg0xx.h b/bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33lg0xx.h new file mode 100644 index 0000000000..d45f47b1fc --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33lg0xx.h @@ -0,0 +1,1122 @@ +/**************************************************************************************************** * @file FM33LG0XX.h + * + * @brief CMSIS CORTEX-M0 Peripheral Access Layer Header File for + * FM33LG0XX from Keil. + * + * @version V0.0.1 + * @date 14 july 2020 + * + * @note Generated with SVDConv V2.87e + * from CMSIS SVD File 'FM33LG0XX.SVD' Version 1.0, + * + * @par ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontroller, but can be equally used for other + * suitable processor architectures. This file can be freely distributed. + * Modifications to this file shall be clearly marked. + * + * THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + *******************************************************************************************************/ + + +/** @addtogroup Keil + * @{ + */ + +/** @addtogroup FM33LG0XX + * @{ + */ + +#ifndef __FM33LG0XX_H +#define __FM33LG0XX_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#define __RCHF_INITIAL_CLOCK (8000000) /* Value of the Internal RC HIGH oscillator in Hz */ +#define __RCLP_CLOCK (32000) /* Value of the Internal RC LOW oscillator in Hz */ +#define __XTHF_CLOCK (8000000) /* Value of the EXTERNAL oscillator in Hz */ +#define __XTLF_CLOCK (32768) /* Value of the EXTERNAL oscillator in Hz */ + +/** + * @brief Configuration of the Cortex-M0 Processor and Core Peripherals + */ +#define __CM0_REV 0x0100U /*!< Cortex-M0 Core Revision */ +#define __MPU_PRESENT 1U /*!< MPU present or not */ +#define __VTOR_PRESENT 1U /*!< VTOR present or not */ +#define __NVIC_PRIO_BITS 2U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +/* ------------------------- Interrupt Number Definition ------------------------ */ + +/** + * @brief FM33LG0XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +typedef enum { +/****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/ + Reset_IRQn = -15, /*!< 1 复位向量 */ + NMI_IRQn = -14, /*!< 2 WKUPx中断、低功耗模式错误中断 */ + HardFault_IRQn = -13, /*!< 3 HardFault中断向量 */ + SVC_IRQn = -5, /*!< 11 SVCall系统服务请求 */ + PendSV_IRQn = -2, /*!< 14 可挂起系统服务请求 */ + SysTick_IRQn = -1, /*!< 15 内部定时器中断向量 */ + +/* -------------------- FM33LG0XX specific Interrupt Numbers --------------------*/ + WWDT_IRQn = 0, /*!< 0 窗口看门狗或独立看门狗中断 */ + SVD_IRQn = 1, /*!< 1 电源监测报警中断 */ + RTCx_IRQn = 2, /*!< 2 实时时钟中断 */ + FLASH_IRQn = 3, /*!< 3 NVMIF中断 */ + FDET_IRQn = 4, /*!< 4 XTLF或XTHF停振检测中断、系统时钟选择错误中断 */ + ADC_IRQn = 5, /*!< 5 ADC转换完成中断 */ + DAC_IRQn = 6, /*!< 6 DAC中断 */ + SPI0_IRQn = 7, /*!< 7 SPI0中断 */ + SPI1_IRQn = 8, /*!< 8 SPI1中断 */ + SPI2_IRQn = 9, /*!< 9 SPI2中断 */ + UART0_IRQn = 10, /*!< 10 UART0中断 */ + UART1_IRQn = 11, /*!< 11 UART1中断 */ + UART3_IRQn = 12, /*!< 12 UART3中断 */ + UART4_IRQn = 13, /*!< 13 UART4中断 */ + UART5_IRQn = 14, /*!< 14 UART5中断 */ + U7816_IRQn = 15, /*!< 15 U7816中断 */ + LPUARTx_IRQn = 16, /*!< 16 LPUART0/1/2中断 */ + I2C_IRQn = 17, /*!< 17 I2C中断 */ + CCL_IRQn = 18, /*!< 18 时钟校准中断 */ + AES_IRQn = 19, /*!< 19 AES中断 */ + LPTIMx_IRQn = 20, /*!< 20 LPTIM16或LPTIM32中断 */ + DMA_IRQn = 21, /*!< 21 DMA中断 */ + WKUPx_IRQn = 22, /*!< 22 WKUP引脚中断 */ + LUT_IRQn = 23, /*!< 23 LUT中断 */ + BSTIM_IRQn = 24, /*!< 24 BSTIM16或BSTIM32中断 */ + COMPx_IRQn = 25, /*!< 25 COMPx中断 */ + GPTIM01_IRQn = 26, /*!< 26 通用定时器0,1中断 */ + GPTIM2_IRQn = 27, /*!< 27 通用定时器2中断 */ + ATIM_IRQn = 28, /*!< 28 高级定时器中断 */ + VREF_IRQn = 29, /*!< 29 1.2V内部基准电压建立中断、VREF_VREG中断 */ + GPIO_IRQn = 30, /*!< 30 外部引脚中断 */ + CAN_IRQn = 31, /*!< 31 CAN2.0中断 */ + +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +#include "core_cm0plus.h" /*!< Cortex-M0 processor and core peripherals */ +#include "system_fm33lg0xx.h" /*!< FM33LG0XX System */ + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +//#elif defined(__GNUC__) +///* anonymous unions are enabled by default */ +//#elif defined(__TMS470__) +///* anonymous unions are enabled by default */ +//#elif defined(__TASKING__) +// #pragma warning 586 +#else +#warning Not supported compiler type +#endif + + +/* ================================================================================ */ +/* ================ FLS ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t RDCR; /*!< Flash Read Control Register, Address offset: 0x00 */ + __IO uint32_t PFCR; /*!< Flash Prefetch Control Register, Address offset: 0x04 */ + __I uint32_t OPTBR; /*!< Flash Option Bytes Register, Address offset: 0x08 */ + __IO uint32_t ACLOCK1; /*!< Flash Application Code Lock Register1, Address offset: 0x0C */ + __IO uint32_t ACLOCK2; /*!< Flash Application Code Lock Register2, Address offset: 0x10 */ + __IO uint32_t EPCR; /*!< Flash Erase/Program Control Register, Address offset: 0x14 */ + __O uint32_t KEY; /*!< Flash Key Register, Address offset: 0x18 */ + __IO uint32_t IER; /*!< Flash Interrupt Enable Register, Address offset: 0x1C */ + __IO uint32_t ISR; /*!< Flash Interrupt Status Register, Address offset: 0x20 */ +}FLASH_Type; + + +/* ================================================================================ */ +/* ================ PMU ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< Power Management Control Register, Address offset: 0x00 */ + __IO uint32_t WKTR; /*!< Wakeup Time Register, Address offset: 0x04 */ + __IO uint32_t WKFR; /*!< Wakeup Source Flags Register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< PMU Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< PMU Interrupt and Status Register, Address offset: 0x10 */ + __IO uint32_t RSV1[9]; /*!< RESERVED REGISTER, Address offset: 0x14 */ + __IO uint32_t ULPB_TR; /*!< ULPBG trim Register, Address offset: 0x38 */ + __IO uint32_t VREFP_CR; /*!< VREFP Control Register, Address offset: 0x3C */ + __IO uint32_t VREFP_CFGR; /*!< VREFP Config Register, Address offset: 0x40 */ + __IO uint32_t VREFP_ISR; /*!< VREFP Interrupt Status Register, Address offset: 0x44 */ + __IO uint32_t VREFP_TR; /*!< VREFP Trim Register, Address offset: 0x48 */ +}PMU_Type; + +/* ================================================================================ */ +/* ================ VREFP ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< VREFP Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< VREFP Config Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< VREFP Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t TR; /*!< VREFP Trim Register, Address offset: 0x0C */ +}VREFP_Type; + +/* ================================================================================ */ +/* ================ VREF ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< VREF Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< VREF Config Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< VREF Status Register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< VREF Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t BUFCR; /*!< Buffer Control Register, Address offset: 0x10 */ +}VREF_Type; + + +/* ================================================================================ */ +/* ================ VAO ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t RSV1[512]; /*!< RESERVED REGISTER, Address offset: 0x00 */ + __IO uint32_t RSTCR; /*!< VBAT Reset Control Register, Address offset: 0x800 */ + __IO uint32_t XTLFCR; /*!< XTLF Control Register, Address offset: 0x804 */ + __IO uint32_t XTLFPR; /*!< XTLF Power Register, Address offset: 0x808 */ + __IO uint32_t FDIER; /*!< XTLF Oscillation Fail Detection Interrupt Enable Register,Address offset: 0x80C */ + __IO uint32_t FDISR; /*!< XTLF Oscillation Fail Detection Interrupt Status Register,Address offset: 0x810 */ + __IO uint32_t RSV2[251]; /*!< RESERVED REGISTER, Address offset: 0x814 */ + __IO uint32_t INEN; /*!< VAO IO Input Enable Register, Address offset: 0xC00 */ + __IO uint32_t PUEN; /*!< VAO IO Pull-up Enable Register, Address offset: 0xC04 */ + __IO uint32_t ODEN; /*!< VAO IO Open Drain Enable Register, Address offset: 0xC08 */ + __IO uint32_t FCR; /*!< VAO IO Function Control Register, Address offset: 0xC0C */ + __IO uint32_t DOR; /*!< VAO IO Data Output Register, Address offset: 0xC10 */ + __I uint32_t DIR; /*!< VAO IO Data Input Register, Address offset: 0xC14 */ + __IO uint32_t VILR; /*!< VAO IO Voltage Input Low Register, Address offset: 0xC18 */ +}VAO_Type; + + +/* ================================================================================ */ +/* ================ CDIF ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< , Address offset: 0x00 */ + __IO uint32_t PRSC; /*!< , Address offset: 0x04 */ +}CDIF_Type; + + +/* ================================================================================ */ +/* ================ RMU ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t PDRCR; /*!< PDR Control Register, Address offset: 0x00 */ + __IO uint32_t BORCR; /*!< BOR Control Register, Address offset: 0x04 */ + __IO uint32_t LKPCR; /*!< Reset Config Register, Address offset: 0x08 */ + __O uint32_t SOFTRST; /*!< Software Reset Register, Address offset: 0x0C */ + __IO uint32_t RSTFR; /*!< Reset Flag Register, Address offset: 0x10 */ + __O uint32_t PRSTEN; /*!< Peripheral Reset Enable Register, Address offset: 0x14 */ + __IO uint32_t AHBRSTCR; /*!< AHB Peripherals Reset Register, Address offset: 0x18 */ + __IO uint32_t APBRSTCR1; /*!< APB Peripherals Reset Register1, Address offset: 0x1C */ + __IO uint32_t APBRSTCR2; /*!< APB Peripherals Reset Register2, Address offset: 0x20 */ +}RMU_Type; + + +/* ================================================================================ */ +/* ================ IWDT ================ */ +/* ================================================================================ */ + +typedef struct +{ + __O uint32_t SERV; /*!< IWDT Service Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< IWDT Config Register, Address offset: 0x04 */ + __I uint32_t CNT; /*!< IWDT Counter Register, Address offset: 0x08 */ + __IO uint32_t WIN; /*!< IWDT Window Register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< IWDT Interrupt Enable Register, Address offset: 0x10 */ + __IO uint32_t ISR; /*!< IWDT Interrupt Status Register, Address offset: 0x14 */ +}IWDT_Type; + + +/* ================================================================================ */ +/* ================ WWDT ================ */ +/* ================================================================================ */ + +typedef struct +{ + __O uint32_t CR; /*!< WWDT Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< WWDT Config Register, Address offset: 0x04 */ + __I uint32_t CNT; /*!< WWDT Counter Register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< WWDT Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< WWDT Interrupt Status Register, Address offset: 0x10 */ + __I uint32_t PSC; /*!< WWDT Prescaler Register, Address offset: 0x14 */ +}WWDT_Type; + + +/* ================================================================================ */ +/* ================ CMU ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t SYSCLKCR; /*!< System Clock Control Register, Address offset: 0x00 */ + __IO uint32_t RCHFCR; /*!< RCHF Control Register, Address offset: 0x04 */ + __IO uint32_t RCHFTR; /*!< RCHF Trim Register, Address offset: 0x08 */ + __IO uint32_t PLLCR; /*!< PLL Control Register, Address offset: 0x0C */ + __IO uint32_t RCLPCR; /*!< RCLP Control Register, Address offset: 0x10 */ + __IO uint32_t RCLPTR; /*!< RCLP Trim Register, Address offset: 0x14 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x18 */ + __IO uint32_t LSCLKSEL; /*!< LSCLK Select Register, Address offset: 0x1C */ + __IO uint32_t XTHFCR; /*!< XTHF Control Register, Address offset: 0x20 */ + __IO uint32_t RCLFCR; /*!< RCLF Control Register, Address offset: 0x24 */ + __IO uint32_t RCLFTR; /*!< RCLF Trim Register, Address offset: 0x28 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x2C */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x30 */ + __IO uint32_t PCLKCR1; /*!< Peripheral bus Clock Control Register1, Address offset: 0x34 */ + __IO uint32_t PCLKCR2; /*!< Peripheral bus Clock Control Register2, Address offset: 0x38 */ + __IO uint32_t PCLKCR3; /*!< Peripheral bus Clock Control Register3, Address offset: 0x3C */ + __IO uint32_t PCLKCR4; /*!< Peripheral bus Clock Control Register4, Address offset: 0x40 */ + __IO uint32_t OPCCR1; /*!< Peripheral Clock Config Register1, Address offset: 0x44 */ + __IO uint32_t OPCCR2; /*!< Peripheral Clock Config Register 2, Address offset: 0x48 */ + __IO uint32_t OPCCR3; /*!< Peripheral Clock Config Register 3, Address offset: 0x4C */ + __IO uint32_t AHBMCR; /*!< AHB Master Control Register, Address offset: 0x50 */ + __IO uint32_t CCCR; /*!< Clock Calibration Control Register, Address offset: 0x54 */ + __IO uint32_t CCFR; /*!< Clock Calibration Config Register, Address offset: 0x58 */ + __I uint32_t CCNR; /*!< Clock Calibration Counter Register, Address offset: 0x5C */ + __IO uint32_t CCISR; /*!< Clock Calibration Interrupt Status Register, Address offset: 0x60 */ +}CMU_Type; + + +/* ================================================================================ */ +/* ================ SVD ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CFGR; /*!< SVD Config Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< SVD Control Register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< SVD Interrupt Enable Register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< SVD Interrupt Status Register, Address offset: 0x0C */ + __IO uint32_t VSR; /*!< SVD reference Voltage Select Register, Address offset: 0x10 */ +}SVD_Type; + + +/* ================================================================================ */ +/* ================ AES ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< AES Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t DIR; /*!< AES Data Input Register, Address offset: 0x0C */ + __I uint32_t DOR; /*!< AES Data Output Register, Address offset: 0x10 */ + __IO uint32_t KEY0; /*!< AES Key Register 0, Address offset: 0x14 */ + __IO uint32_t KEY1; /*!< AES Key Register 1, Address offset: 0x18 */ + __IO uint32_t KEY2; /*!< AES Key Register 2, Address offset: 0x1C */ + __IO uint32_t KEY3; /*!< AES Key Register 3, Address offset: 0x20 */ + __IO uint32_t KEY4; /*!< AES Key Register 4, Address offset: 0x24 */ + __IO uint32_t KEY5; /*!< AES Key Register 5, Address offset: 0x28 */ + __IO uint32_t KEY6; /*!< AES Key Register 6, Address offset: 0x2C */ + __IO uint32_t KEY7; /*!< AES Key Register 7, Address offset: 0x30 */ + __IO uint32_t IVR0; /*!< AES Initial Vector Register 0, Address offset: 0x34 */ + __IO uint32_t IVR1; /*!< AES Initial Vector Register 1, Address offset: 0x38 */ + __IO uint32_t IVR2; /*!< AES Initial Vector Register 2, Address offset: 0x3C */ + __IO uint32_t IVR3; /*!< AES Initial Vector Register 3, Address offset: 0x40 */ + __IO uint32_t H0; /*!< AES MultH parameter Register 0, Address offset: 0x44 */ + __IO uint32_t H1; /*!< AES MultH parameter Register 1, Address offset: 0x48 */ + __IO uint32_t H2; /*!< AES MultH parameter Register 2, Address offset: 0x4C */ + __IO uint32_t H3; /*!< AES MultH parameter Register 3, Address offset: 0x50 */ +}AES_Type; + + +/* ================================================================================ */ +/* ================ RNG ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< Random Number Generator Control Register, Address offset: 0x00 */ + __I uint32_t DOR; /*!< Random Number Generator Data Output Register, Address offset: 0x04 */ + __IO uint32_t RSV1[2]; /*!< RESERVED REGISTER, Address offset: 0x08 */ + __IO uint32_t SR; /*!< Random Number Generator Status Register, Address offset: 0x10 */ + __IO uint32_t CRCCR; /*!< CRC Control Register, Address offset: 0x14 */ + __IO uint32_t CRCDIR; /*!< CRC Data input Register, Address offset: 0x18 */ + __IO uint32_t CRCSR; /*!< CRC Status Register, Address offset: 0x1C */ +}RNG_Type; + + +/* ================================================================================ */ +/* ================ OPA ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< OPA1 Control Register, Address offset: 0x00 */ + __IO uint32_t CALR; /*!< OPA1 Calibration Register, Address offset: 0x04 */ + __I uint32_t COR; /*!< OPA1 Calibration Output Register, Address offset: 0x08 */ +}OPA_Type; + + +/* ================================================================================ */ +/* ================ COMP ================ */ +/* ================================================================================ */ +typedef struct +{ + __IO uint32_t CR; /*!< ComparatorControl Register 1, Address offset: 0x00 */ + +} COMP_Type; + +typedef struct +{ + __IO uint32_t ICR; /*!< Comparator Interrupt Config Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< Comparator Interrupt Status Register, Address offset: 0x10 */ + __IO uint32_t BUFCR; /*!< Comparator Buffer Control Register, Address offset: 0x14 */ +}COMP_COMMON_Type; + + +/* ================================================================================ */ +/* ================ CALC ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t OPRD; /*!< Operand Register, Address offset: 0x00 */ + __IO uint32_t DIVSOR; /*!< Divisor Regsiter, Address offset: 0x04 */ + __I uint32_t QUOT; /*!< Quotient Register, Address offset: 0x08 */ + __I uint32_t REMD; /*!< Reminder Register, Address offset: 0x0C */ + __I uint32_t ROOT; /*!< Root Register, Address offset: 0x10 */ + __I uint32_t SR; /*!< Status Register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x18 */ +}DIVAS_Type; + + +/* ================================================================================ */ +/* ================ I2C ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t MSPCFGR; /*!< I2C Master Config Register, Address offset: 0x00 */ + __IO uint32_t MSPCR; /*!< I2C Master Control Register, Address offset: 0x04 */ + __IO uint32_t MSPIER; /*!< I2C Master Intterupt Enable Register, Address offset: 0x08 */ + __IO uint32_t MSPISR; /*!< I2C Master Interrupt Status Register, Address offset: 0x0C */ + __IO uint32_t MSPSR; /*!< I2C Master Status Register, Address offset: 0x10 */ + __IO uint32_t MSPBGR; /*!< I2C Master Baud rate Generator Register, Address offset: 0x14 */ + __IO uint32_t MSPBUF; /*!< I2C Master transfer Buffer, Address offset: 0x18 */ + __IO uint32_t MSPTCR; /*!< I2C Master Timing Control Register, Address offset: 0x1C */ + __IO uint32_t MSPTOR; /*!< I2C Master Time-Out Register, Address offset: 0x20 */ + __IO uint32_t SSPCR; /*!< I2C Slave Control Register, Address offset: 0x24 */ + __IO uint32_t SSPIER; /*!< I2C Slave Interrupt Enable Register, Address offset: 0x28 */ + __IO uint32_t SSPISR; /*!< I2C Slave Interrupt Status Register, Address offset: 0x2C */ + __I uint32_t SSPSR; /*!< I2C Slave Status Register, Address offset: 0x30 */ + __IO uint32_t SSPBUF; /*!< I2C Slave transfer Buffer, Address offset: 0x34 */ + __IO uint32_t SSPADR; /*!< I2C Slave Address Register, Address offset: 0x38 */ +}I2C_Type; + + +/* ================================================================================ */ +/* ================ UART_COMMON ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t IRCR; /*!< Infrared modulation Control Register, Address offset: 0x00 */ +}UART_COMMON_Type; + + +/* ================================================================================ */ +/* ================ UARTx ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CSR; /*!< UARTx Control Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< UARTx Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< UARTx Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t TODR; /*!< UARTx Time-Out and Delay Register, Address offset: 0x0C */ + __I uint32_t RXBUF; /*!< UARTx Receive Buffer, Address offset: 0x10 */ + __O uint32_t TXBUF; /*!< UARTx Transmit Buffer, Address offset: 0x14 */ + __IO uint32_t BGR; /*!< UARTx Baud rate Generator Register, Address offset: 0x18 */ +}UART_Type; + + +/* ================================================================================ */ +/* ================ LPUARTx ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CSR; /*!< LPUARTx Control Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< LPUARTx Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< LPUARTx Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t BMR; /*!< LPUARTx Baud rate Modulation Register, Address offset: 0x0C */ + __I uint32_t RXBUF; /*!< LPUARTx Receive Buffer Register, Address offset: 0x10 */ + __IO uint32_t TXBUF; /*!< LPUARTx Transmit Buffer Register, Address offset: 0x14 */ + __IO uint32_t DMR; /*!< LPUARTx data Matching Register, Address offset: 0x18 */ +}LPUART_Type; + + +/* ================================================================================ */ +/* ================ SPIx ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPIxControl Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPIxControl Register2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Control Register3, Address offset: 0x08 */ + __IO uint32_t IER; /*!< SPIxInterrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< SPIxStatus Register, Address offset: 0x10 */ + __O uint32_t TXBUF; /*!< SPIxTransmit Buffer, Address offset: 0x14 */ + __I uint32_t RXBUF; /*!< SPIxReceive Buffer, Address offset: 0x18 */ +}SPI_Type; + + +/* ================================================================================ */ +/* ================ U7816 ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< 7816 Control Register, Address offset: 0x00 */ + __IO uint32_t FFR; /*!< 7816 Frame Format Control Register, Address offset: 0x04 */ + __IO uint32_t EGTR; /*!< 7816 Extra Guard Time Register, Address offset: 0x08 */ + __IO uint32_t PSC; /*!< 7816 Clock Output Divider Register, Address offset: 0x0C */ + __IO uint32_t BGR; /*!< 7816 Prescaler Register, Address offset: 0x10 */ + __IO uint32_t RXBUF; /*!< 7816 data RX Buffer, Address offset: 0x14 */ + __IO uint32_t TXBUF; /*!< 7816 data TX Buffer, Address offset: 0x18 */ + __IO uint32_t IER; /*!< 7816 Interrupt Enable Register, Address offset: 0x1C */ + __IO uint32_t ISR; /*!< 7816 Interrupt Status Register, Address offset: 0x20 */ +}U7816_Type; + + +/* ================================================================================ */ +/* ================ CAN ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< CAN Control Register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN mode select register, Address offset: 0x04 */ + __IO uint32_t BRPR; /*!< CAN Baud rate Prescaler Register, Address offset: 0x08 */ + __IO uint32_t BTR; /*!< CAN Bit Timing Register, Address offset: 0x0C */ + __I uint32_t ECR; /*!< CAN Error Counter Register, Address offset: 0x10 */ + __IO uint32_t ESR; /*!< CAN Error Status Register, Address offset: 0x14 */ + __I uint32_t SR; /*!< CAN Status Register, Address offset: 0x18 */ + __I uint32_t ISR; /*!< CAN Interrupt Status Register, Address offset: 0x1C */ + __IO uint32_t IER; /*!< CAN Interrupt Enable Register, Address offset: 0x20 */ + __IO uint32_t ICR; /*!< CAN Interrupt Clear Register, Address offset: 0x24 */ + __IO uint32_t RSV1[2]; /*!< RESERVED REGISTER, Address offset: 0x28 */ + __O uint32_t TXFIDR; /*!< CAN TX FIFO ID Register, Address offset: 0x30 */ + __O uint32_t TXFDLCR; /*!< CAN TX FIFO DLC Register, Address offset: 0x34 */ + __O uint32_t TXFDW1R; /*!< CAN TX FIFO Data Word1 Register, Address offset: 0x38 */ + __O uint32_t TXFDW2R; /*!< CAN TX FIFO Data Word2 Register, Address offset: 0x3C */ + __O uint32_t HPBIDR; /*!< CAN TX HPB ID Register, Address offset: 0x40 */ + __O uint32_t HPBDLCR; /*!< CAN TX HPB DLC Register, Address offset: 0x44 */ + __O uint32_t HPBDW1R; /*!< CAN TX HPB Data Word1 Register, Address offset: 0x48 */ + __O uint32_t HPBDW2R; /*!< CAN TX HPB Data Word2 Register, Address offset: 0x4C */ + __O uint32_t RXFIDR; /*!< CAN RX FIFO ID Register, Address offset: 0x50 */ + __O uint32_t RXFDLCR; /*!< CAN RX FIFO DLC Register, Address offset: 0x54 */ + __O uint32_t RXFDW1R; /*!< CAN RX FIFO Data Word1 Register, Address offset: 0x58 */ + __O uint32_t RXFDW2R; /*!< CAN RX FIFO Data Word2 Register, Address offset: 0x5C */ + __IO uint32_t AFR; /*!< Acceptance Filter Register, Address offset: 0x60 */ + __IO uint32_t AFMR0; /*!< Acceptance Filter Mask Register0, Address offset: 0x64 */ + __IO uint32_t AFIR0; /*!< Acceptance Filter ID Register0, Address offset: 0x68 */ + __IO uint32_t AFMR1; /*!< Acceptance Filter Mask Register1, Address offset: 0x6C */ + __IO uint32_t AFIR1; /*!< Acceptance Filter ID Register1, Address offset: 0x70 */ + __IO uint32_t AFMR2; /*!< Acceptance Filter Mask Register2, Address offset: 0x74 */ + __IO uint32_t AFIR2; /*!< Acceptance Filter ID Register2, Address offset: 0x78 */ + __IO uint32_t AFMR3; /*!< Acceptance Filter Mask Register3, Address offset: 0x7C */ + __IO uint32_t AFIR3; /*!< Acceptance Filter ID Register3, Address offset: 0x80 */ +}CAN_Type; + + +/* ================================================================================ */ +/* ================ DMA ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t GCR; /*!< DMA Global Control Register, Address offset: 0x00 */ + __IO uint32_t CH0CR; /*!< Channel 0 Control Register, Address offset: 0x04 */ + __IO uint32_t CH0MAR; /*!< Channel 0 Memory Address Register, Address offset: 0x08 */ + __IO uint32_t CH1CR; /*!< Channel 1 Control Register, Address offset: 0x0C */ + __IO uint32_t CH1MAR; /*!< Channel 1 Memory Address Register, Address offset: 0x10 */ + __IO uint32_t CH2CR; /*!< Channel 2 Control Register, Address offset: 0x14 */ + __IO uint32_t CH2MAR; /*!< Channel 2 Memory Address Register, Address offset: 0x18 */ + __IO uint32_t CH3CR; /*!< Channel 3 Control Register, Address offset: 0x1C */ + __IO uint32_t CH3MAR; /*!< Channel 3 Memory Address Register, Address offset: 0x20 */ + __IO uint32_t CH4CR; /*!< Channel 4 Control Register, Address offset: 0x24 */ + __IO uint32_t CH4MAR; /*!< Channel 4 Memory Address Register, Address offset: 0x28 */ + __IO uint32_t CH5CR; /*!< Channel 5 Control Register, Address offset: 0x2C */ + __IO uint32_t CH5MAR; /*!< Channel 5 Memory Address Register, Address offset: 0x30 */ + __IO uint32_t CH6CR; /*!< Channel 6 Control Register, Address offset: 0x34 */ + __IO uint32_t CH6MAR; /*!< Channel 6 Memory Address Register, Address offset: 0x38 */ + __IO uint32_t CH7CR; /*!< Channel 11 Control Register, Address offset: 0x3C */ + __IO uint32_t CH7FLSAD; /*!< Channel 11 Flash Address Register, Address offset: 0x40 */ + __IO uint32_t CH7RAMAD; /*!< Channel 11 RAM Address Register, Address offset: 0x44 */ + __IO uint32_t ISR; /*!< DMA Interrupt Status Register, Address offset: 0x48 */ +}DMA_Type; + + +/* ================================================================================ */ +/* ================ CRC ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x04 */ + __IO uint32_t LFSR; /*!< CRC Linear Feedback Shift Register, Address offset: 0x08 */ + __IO uint32_t XOR; /*!< CRC output XOR Register, Address offset: 0x0C */ + __IO uint32_t RSV1[3]; /*!< RESERVED REGISTER, Address offset: 0x10 */ + __IO uint32_t POLY; /*!< CRC Polynominal Register, Address offset: 0x1C */ +}CRC_Type; + + +/* ================================================================================ */ +/* ================ ATIM ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR1; /*!< ATIM Control Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< ATIM Control Register2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< ATIM Slave Mode Control Register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< ATIM DMA and Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< ATIM Interrupt Status Register, Address offset: 0x10 */ + __O uint32_t EGR; /*!< ATIM Event Generation Register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< ATIM Capture/Compare Mode Register1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< ATIM Capture/Compare Mode Register2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< ATIM Capture/Compare Enable Register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< ATIM Counter Register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< ATIM Prescaler Register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< ATIM Auto-Reload Register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< ATIM Repetition Counter Register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< ATIM Capture/Compare Register1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< ATIM Capture/Compare Register2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< ATIM Capture/Compare Register3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< ATIM Capture/Compare Register4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< ATIM Break and Deadtime Register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< ATIM DMA Control Register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< ATIM DMA Access Register, Address offset: 0x4C */ + __IO uint32_t RSV1[4]; /*!< RESERVED REGISTER, Address offset: 0x50 */ + __IO uint32_t BKCR; /*!< ATIM Break Control Register, Address offset: 0x60 */ +}ATIM_Type; + + +/* ================================================================================ */ +/* ================ GPTIMx ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR1; /*!< GPTIMx Control Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< GPTIMx Control Register2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< GPTIMx Slave Mode Control Register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< GPTIMx DMA and Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x10 */ + __O uint32_t EGR; /*!< GPTIMx Event Generation Register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< GPTIMx Capture/Compare Mode Register1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< GPTIMx Capture/Compare Mode Register2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< GPTIMx Capture/Compare Enable Register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< GPTIMx Counter Register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< GPTIMx Prescaler Register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< GPTIMx Auto-Reload Register, Address offset: 0x2C */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< GPTIMx Capture/Compare Register1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< GPTIMx Capture/Compare Register2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< GPTIMx Capture/Compare Register3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< GPTIMx Capture/Compare Register4, Address offset: 0x40 */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< GPTIMx DMA Control Register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< GPTIMx DMA access Register, Address offset: 0x4C */ + __IO uint32_t RSV3[4]; /*!< RESERVED REGISTER, Address offset: 0x50 */ + __IO uint32_t ITRSEL; /*!< GPTIMx Internal Trigger Select Register, Address offset: 0x60 */ +}GPTIM_Type; + + +/* ================================================================================ */ +/* ================ BSTIM32 ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR1; /*!< BSTIM Control Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< BSTIM Control Register2, Address offset: 0x04 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x08 */ + __IO uint32_t IER; /*!< BSTIM Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< BSTIM Interrupt Status Register, Address offset: 0x10 */ + __O uint32_t EGR; /*!< BSTIM Event Generation Register, Address offset: 0x14 */ + __IO uint32_t RSV2[3]; /*!< RESERVED REGISTER, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< BSTIM Counter Register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< BSTIM Prescaler Register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< BSTIM Auto-Reload Register, Address offset: 0x2C */ +}BSTIM32_Type; + + +/* ================================================================================ */ +/* ================ BSTIM16 ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR1; /*!< BSTIM Control Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< BSTIM Control Register2, Address offset: 0x04 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x08 */ + __IO uint32_t IER; /*!< BSTIM Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< BSTIM Interrupt Status Register, Address offset: 0x10 */ + __O uint32_t EGR; /*!< BSTIM Event Generation Register, Address offset: 0x14 */ + __IO uint32_t RSV2[3]; /*!< RESERVED REGISTER, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< BSTIM Counter Register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< BSTIM Prescaler Register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< BSTIM Auto-Reload Register, Address offset: 0x2C */ +}BSTIM16_Type; + + +/* ================================================================================ */ +/* ================ LPTIM32 ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CFGR; /*!< LPTIM32 Config Register, Address offset: 0x00 */ + __I uint32_t CNT; /*!< LPTIM32 Counter Register, Address offset: 0x04 */ + __IO uint32_t CCSR; /*!< LPTIM32 Capture/Compare Control and Status Register, Address offset: 0x08 */ + __IO uint32_t ARR; /*!< LPTIM32 Auto-Reload Register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< LPTIM32 Interrupt Enable Register, Address offset: 0x10 */ + __IO uint32_t ISR; /*!< LPTIM32 Interrupt Status Register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< LPTIM32 Control Register, Address offset: 0x18 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x1C */ + __IO uint32_t CCR1; /*!< LPTIM32 Capture/Compare Register1, Address offset: 0x20 */ + __IO uint32_t CCR2; /*!< LPTIM32 Capture/Compare Register2, Address offset: 0x24 */ + __IO uint32_t CCR3; /*!< LPTIM32 Capture/Compare Register3, Address offset: 0x28 */ + __IO uint32_t CCR4; /*!< LPTIM32 Capture/Compare Register4, Address offset: 0x2C */ +}LPTIM32_Type; + + +/* ================================================================================ */ +/* ================ LPTIM16 ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CFGR; /*!< LPTIM Config Register, Address offset: 0x00 */ + __I uint32_t CNT; /*!< LPTIM Counter Register, Address offset: 0x04 */ + __IO uint32_t CCSR; /*!< LPTIM Capture/Compare Control and Status Register, Address offset: 0x08 */ + __IO uint32_t ARR; /*!< LPTIM Auto-Reload Register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable Register, Address offset: 0x10 */ + __IO uint32_t ISR; /*!< LPTIM Interrupt Status Register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< LPTIM Control Register, Address offset: 0x18 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x1C */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare Register1, Address offset: 0x20 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare Register2, Address offset: 0x24 */ +}LPTIM16_Type; + + +/* ================================================================================ */ +/* ================ RTCA ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t WER; /*!< RTC Write Enable Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< RTC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< RTC Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t BCDSEC; /*!< BCD format time second registers, Address offset: 0x0C */ + __IO uint32_t BCDMIN; /*!< BCD format time minute registers, Address offset: 0x10 */ + __IO uint32_t BCDHOUR; /*!< BCD format time hour registers, Address offset: 0x14 */ + __IO uint32_t BCDDAY; /*!< BCD format time day registers, Address offset: 0x18 */ + __IO uint32_t BCDWEEK; /*!< BCD format time week registers, Address offset: 0x1C */ + __IO uint32_t BCDMONTH; /*!< BCD format time month registers, Address offset: 0x20 */ + __IO uint32_t BCDYEAR; /*!< BCD format time year registers, Address offset: 0x24 */ + __IO uint32_t ALARM; /*!< RTCA Alarm Register, Address offset: 0x28 */ + __IO uint32_t TMSEL; /*!< RTCA Time Mark Select, Address offset: 0x2C */ + __IO uint32_t ADJUST; /*!< RTCA time Adjust Register, Address offset: 0x30 */ + __IO uint32_t ADSIGN; /*!< RTCA time Adjust Sign Register, Address offset: 0x34 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x38 */ + __IO uint32_t SBSCNT; /*!< RTCA Sub-Second Counter, Address offset: 0x3C */ + __IO uint32_t CR; /*!< RTCA Control Register, Address offset: 0x40 */ +}RTCA_Type; + + +/* ================================================================================ */ +/* ================ RTCB ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t WER; /*!< RTCBWrite Enable Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< RTCBInterrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< RTCBInterrupt Status Register, Address offset: 0x08 */ + __IO uint32_t BCDSEC; /*!< BCD format time second registers, Address offset: 0x0C */ + __IO uint32_t BCDMIN; /*!< BCD format time minute registers, Address offset: 0x10 */ + __IO uint32_t BCDHOUR; /*!< BCD format time hour registers, Address offset: 0x14 */ + __IO uint32_t BCDDAY; /*!< BCD format time day registers, Address offset: 0x18 */ + __IO uint32_t BCDWEEK; /*!< BCD format time week registers, Address offset: 0x1C */ + __IO uint32_t BCDMONTH; /*!< BCD format time month registers, Address offset: 0x20 */ + __IO uint32_t BCDYEAR; /*!< BCD format time year registers, Address offset: 0x24 */ + __IO uint32_t ALARM; /*!< Alarm Register, Address offset: 0x28 */ + __IO uint32_t TMSEL; /*!< RTCB Time Mark Select, Address offset: 0x2C */ + __IO uint32_t ADJR; /*!< RTCB time Adjust Register, Address offset: 0x30 */ + __IO uint32_t RSV1[3]; /*!< RESERVED REGISTER, Address offset: 0x34 */ + __IO uint32_t CR; /*!< RTCB Control Register, Address offset: 0x40 */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER, Address offset: 0x44 */ + __IO uint32_t STPCR; /*!< RTCB Time Stamp Control Register, Address offset: 0x48 */ + __IO uint32_t STPCLKRR; /*!< RTC Time Stamp Clock Record Register, Address offset: 0x4C */ + __IO uint32_t STPCALRR; /*!< RTCB Time Stamp Calendar Record Register, Address offset: 0x50 */ + __IO uint32_t RSV3[7]; /*!< RESERVED REGISTER, Address offset: 0x54 */ + __IO uint32_t BKR0; /*!< RTCBBackup Register0, Address offset: 0x70 */ + __IO uint32_t BKR1; /*!< RTCB Backup Register1, Address offset: 0x74 */ + __IO uint32_t BKR2; /*!< RTCB Backup Register2, Address offset: 0x78 */ + __IO uint32_t BKR3; /*!< RTCB Backup Register3, Address offset: 0x7C */ + __IO uint32_t BKR4; /*!< RTCB Backup Register4, Address offset: 0x80 */ +}RTCB_Type; + + +/* ================================================================================ */ +/* ================ LCD ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD Control Register, Address offset: 0x00 */ + __IO uint32_t TEST; /*!< LCD test Register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< LCD Frequency Control Register, Address offset: 0x08 */ + __IO uint32_t FLKT; /*!< LCD Flick Time Register, Address offset: 0x0C */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x10 */ + __IO uint32_t IER; /*!< LCD Interrupt Enable Register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< LCD Interrupt Status Register, Address offset: 0x18 */ + __IO uint32_t RSV2[2]; /*!< RESERVED REGISTER, Address offset: 0x1C */ + __IO uint32_t DATA0; /*!< LCD data buffer registers 0, Address offset: 0x24 */ + __IO uint32_t DATA1; /*!< LCD data buffer registers 1, Address offset: 0x28 */ + __IO uint32_t DATA2; /*!< LCD data buffer registers 2, Address offset: 0x2C */ + __IO uint32_t DATA3; /*!< LCD data buffer registers 3, Address offset: 0x30 */ + __IO uint32_t DATA4; /*!< LCD data buffer registers 4, Address offset: 0x34 */ + __IO uint32_t DATA5; /*!< LCD data buffer registers 5, Address offset: 0x38 */ + __IO uint32_t DATA6; /*!< LCD data buffer registers 6, Address offset: 0x3C */ + __IO uint32_t DATA7; /*!< LCD data buffer registers 7, Address offset: 0x40 */ + __IO uint32_t DATA8; /*!< LCD data buffer registers 8, Address offset: 0x44 */ + __IO uint32_t DATA9; /*!< LCD data buffer registers 9, Address offset: 0x48 */ + __IO uint32_t RSV3; /*!< RESERVED REGISTER, Address offset: 0x4C */ + __IO uint32_t COMEN; /*!< LCD COM Enable Register, Address offset: 0x50 */ + __IO uint32_t SEGEN0; /*!< LCD SEG Enable Register0, Address offset: 0x54 */ + __IO uint32_t SEGEN1; /*!< LCD SEG Enable Register 1, Address offset: 0x58 */ +}LCD_Type; + + +/* ================================================================================ */ +/* ================ ADC ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR1; /*!< ADC Control Register, Address offset: 0x08 */ + __IO uint32_t CR2; /*!< ADC Control Register, Address offset: 0x0C */ + __IO uint32_t CALR; /*!< ADC Calibration Register, Address offset: 0x10 */ + __IO uint32_t CFGR1; /*!< ADC Config Register1, Address offset: 0x14 */ + __IO uint32_t CFGR2; /*!< ADC Config Register2, Address offset: 0x18 */ + __IO uint32_t SMTR; /*!< ADC Sampling Time Register, Address offset: 0x1C */ + __IO uint32_t CHER; /*!< ADC Channel Enable Register, Address offset: 0x20 */ + __IO uint32_t DCR; /*!< ADC Differential Channel Control Register, Address offset: 0x24 */ + __I uint32_t DR; /*!< ADC Data Register, Address offset: 0x28 */ + __IO uint32_t HLTR; /*!< ADC analog watchdog Threshold Register, Address offset: 0x2C */ +}ADC_Type; + + +/* ================================================================================ */ +/* ================ DAC ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR1; /*!< DAC Control Register, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< DAC Control Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< DAC Config Register, Address offset: 0x08 */ + __O uint32_t SWTRGR; /*!< DAC Software Trigger Register, Address offset: 0x0C */ + __IO uint32_t DHR; /*!< DAC Data Holding Register, Address offset: 0x10 */ + __IO uint32_t ISR; /*!< DAC Interrupt Status Register, Address offset: 0x14 */ + __IO uint32_t IER; /*!< DAC Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t SHTR; /*!< DAC Sample Hold Time Register, Address offset: 0x1C */ +}DAC_Type; + + +/* ================================================================================ */ +/* ================ PGL ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< PGL Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR0; /*!< PGL Config Register0, Address offset: 0x04 */ + __IO uint32_t CFGR1; /*!< PGL Config Register1, Address offset: 0x08 */ + __IO uint32_t CFGR2; /*!< PGL Config Register2, Address offset: 0x0C */ + __IO uint32_t CFGR3; /*!< PGL Config Register3, Address offset: 0x10 */ + __IO uint32_t IER; /*!< PGL Interrupt Enable Register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< PGL Interrupt Status Register, Address offset: 0x18 */ + __IO uint32_t LUT0; /*!< Look Up Table0, Address offset: 0x1C */ + __IO uint32_t LUT1; /*!< Look Up Table1, Address offset: 0x20 */ + __IO uint32_t LUT2; /*!< Look Up Table2, Address offset: 0x24 */ + __IO uint32_t LUT3; /*!< Look Up Table3, Address offset: 0x28 */ +}PGL_Type; + + +/* ================================================================================ */ +/* ================ GPIO ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t INEN; /*!< GPIOx Input Enable Register, Address offset: 0x00 */ + __IO uint32_t PUEN; /*!< GPIOx Pull-Up Enable Register, Address offset: 0x04 */ + __IO uint32_t ODEN; /*!< GPIOx Open-Drain Enable Register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< GPIOx Function Control Register, Address offset: 0x0C */ + __IO uint32_t DO; /*!< GPIOx Data Output Register, Address offset: 0x10 */ + __O uint32_t DSET; /*!< GPIOx Data Set Register, Address offset: 0x14 */ + __O uint32_t DRST; /*!< GPIOx Data Reset Register, Address offset: 0x18 */ + __I uint32_t DIN; /*!< GPIOx Data Input Register, Address offset: 0x1C */ + __IO uint32_t DFS; /*!< GPIOx Digital Function Select, Address offset: 0x20 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x24 */ + __IO uint32_t ANEN; /*!< GPIOx Analog channel Enable Register, Address offset: 0x28 */ + __IO uint32_t VILR; /*!< GPIOx Voltage Input Low Register, Address offset: 0x2C */ +}GPIO_Type; + + +/* ================================================================================ */ +/* ================ GPIO_COMMON ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t EXTISEL0; /*!< External Interrupt Input Select Register0, Address offset: 0x00 */ + __IO uint32_t EXTISEL1; /*!< External Interrupt Input Select Register1, Address offset: 0x04 */ + __IO uint32_t EXTIEDS0; /*!< External Interrupt Edge Select and Enable Register0, Address offset: 0x08 */ + __IO uint32_t EXTIEDS1; /*!< External Interrupt Edge Select and Enable Register1, Address offset: 0x0C */ + __IO uint32_t EXTIDF; /*!< External Interrupt Digital Filter Register, Address offset: 0x10 */ + __IO uint32_t EXTIISR; /*!< External Interrupt and Status Register, Address offset: 0x14 */ + __I uint32_t EXTIDI; /*!< External Interrupt Data Input Register, Address offset: 0x18 */ + __IO uint32_t RSV1[9]; /*!< RESERVED REGISTER, Address offset: 0x1C */ + __IO uint32_t FOUTSEL; /*!< Frequency Output Select Register, Address offset: 0x100 */ + __IO uint32_t RSV2[63]; /*!< RESERVED REGISTER, Address offset: 0x104 */ + __IO uint32_t PINWKEN; /*!< Wakeup Enable Register, Address offset: 0x200 */ +}GPIO_COMMON_Type; + + +/* ================================================================================ */ +/* ================ DBG ================ */ +/* ================================================================================ */ + +typedef struct +{ + __I uint32_t SYSCFG; /*!< , Address offset: 0x00 */ + __IO uint32_t CR; /*!< , Address offset: 0x04 */ + __IO uint32_t HDFR; /*!< , Address offset: 0x08 */ +}DBG_Type; + + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + +/* ================================================================================ */ +/* ================ CPU memory map ================ */ +/* ================================================================================ */ + + +/* Peripheral and SRAM base address */ + +#define FLASH_BASE (( uint32_t)0x00000000) +#define SRAM_BASE (( uint32_t)0x20000000) +#define PERIPH_BASE (( uint32_t)0x40000000) + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +/* Peripheral memory map */ + +#define FLASH_R_BASE (PERIPH_BASE +0x00001000) +#define PMU_BASE (PERIPH_BASE +0x00002000) +#define VREFP_BASE (PERIPH_BASE +0x0000203C) +#define VREF_BASE (PERIPH_BASE +0x0001A400) +#define VAO_BASE (PERIPH_BASE +0x0001F000) +#define CDIF_BASE (PERIPH_BASE +0x0001E000) +#define RMU_BASE (PERIPH_BASE +0x00002800) +#define IWDT_BASE (PERIPH_BASE +0x00011400) +#define WWDT_BASE (PERIPH_BASE +0x00011800) +#define CMU_BASE (PERIPH_BASE +0x00002400) +#define SVD_BASE (PERIPH_BASE +0x00012800) +#define AES_BASE (PERIPH_BASE +0x00013800) +#define RNG_BASE (PERIPH_BASE +0x00013C00) +#define OPA_BASE (PERIPH_BASE +0x0001A000) +#define COMP1_BASE (PERIPH_BASE +0x00015400) +#define COMP2_BASE (PERIPH_BASE +0x00015404) +#define COMP3_BASE (PERIPH_BASE +0x00015408) +#define COMP_COMMON_BASE (PERIPH_BASE +0x0001540C) +#define DIVAS_BASE (PERIPH_BASE +0x00019C00) +#define I2C_BASE (PERIPH_BASE +0x00012400) +#define UART_COMMON_BASE (PERIPH_BASE +0x00017C00) +#define UART0_BASE (PERIPH_BASE +0x00012000) +#define UART1_BASE (PERIPH_BASE +0x00016800) +#define UART3_BASE (PERIPH_BASE +0x00017000) +#define UART4_BASE (PERIPH_BASE +0x00017400) +#define UART5_BASE (PERIPH_BASE +0x00017800) +#define LPUART0_BASE (PERIPH_BASE +0x00014000) +#define LPUART1_BASE (PERIPH_BASE +0x00014400) +#define LPUART2_BASE (PERIPH_BASE +0x00015000) +#define SPI0_BASE (PERIPH_BASE +0x00010400) +#define SPI1_BASE (PERIPH_BASE +0x00010800) +#define SPI2_BASE (PERIPH_BASE +0x00014800) +#define U7816_BASE (PERIPH_BASE +0x00011C00) +#define CAN_BASE (PERIPH_BASE +0x00019400) +#define DMA_BASE (PERIPH_BASE +0x00000400) +#define CRC_BASE (PERIPH_BASE +0x00010000) +#define ATIM_BASE (PERIPH_BASE +0x00013000) +#define GPTIM0_BASE (PERIPH_BASE +0x00014C00) +#define GPTIM1_BASE (PERIPH_BASE +0x00016400) +#define GPTIM2_BASE (PERIPH_BASE +0x00018000) +#define BSTIM32_BASE (PERIPH_BASE +0x00016000) +#define BSTIM16_BASE (PERIPH_BASE +0x00018C00) +#define LPTIM32_BASE (PERIPH_BASE +0x00013400) +#define LPTIM16_BASE (PERIPH_BASE +0x00018800) +#define RTCA_BASE (PERIPH_BASE +0x00011000) +#define RTCB_BASE (PERIPH_BASE +0x0001F000) +#define LCD_BASE (PERIPH_BASE +0x00010C00) +#define ADC_BASE (PERIPH_BASE +0x00015C00) +#define DAC_BASE (PERIPH_BASE +0x00019800) +#define PGL_BASE (PERIPH_BASE +0x00016C00) +#define GPIOA_BASE (PERIPH_BASE +0x00000C00) +#define GPIOB_BASE (PERIPH_BASE +0x00000C40) +#define GPIOC_BASE (PERIPH_BASE +0x00000C80) +#define GPIOD_BASE (PERIPH_BASE +0x00000CC0) +#define GPIOE_BASE (PERIPH_BASE +0x00000D00) +#define GPIO_COMMON_BASE (PERIPH_BASE +0x00000DC0) +#define DBG_BASE (PERIPH_BASE +0x00000000) + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define FLASH ((FLASH_Type *) FLASH_R_BASE ) +#define PMU ((PMU_Type *) PMU_BASE ) +#define VREFP ((VREFP_Type *) VREFP_BASE ) +#define VREF ((VREF_Type *) VREF_BASE ) +#define VAO ((VAO_Type *) VAO_BASE ) +#define CDIF ((CDIF_Type *) CDIF_BASE ) +#define RMU ((RMU_Type *) RMU_BASE ) +#define IWDT ((IWDT_Type *) IWDT_BASE ) +#define WWDT ((WWDT_Type *) WWDT_BASE ) +#define CMU ((CMU_Type *) CMU_BASE ) +#define SVD ((SVD_Type *) SVD_BASE ) +#define AES ((AES_Type *) AES_BASE ) +#define RNG ((RNG_Type *) RNG_BASE ) +#define OPA ((OPA_Type *) OPA_BASE ) +#define COMP1 ((COMP_Type *) COMP1_BASE ) +#define COMP2 ((COMP_Type *) COMP2_BASE ) +#define COMP3 ((COMP_Type *) COMP3_BASE ) +#define COMP_COMMON ((COMP_COMMON_Type *)COMP_COMMON_BASE ) +#define DIVAS ((DIVAS_Type *) DIVAS_BASE ) +#define I2C ((I2C_Type *) I2C_BASE ) +#define UART_COMMON ((UART_COMMON_Type *) UART_COMMON_BASE ) +#define UART0 ((UART_Type *) UART0_BASE ) +#define UART1 ((UART_Type *) UART1_BASE ) +#define UART3 ((UART_Type *) UART3_BASE ) +#define UART4 ((UART_Type *) UART4_BASE ) +#define UART5 ((UART_Type *) UART5_BASE ) +#define LPUART0 ((LPUART_Type *) LPUART0_BASE ) +#define LPUART1 ((LPUART_Type *) LPUART1_BASE ) +#define LPUART2 ((LPUART_Type *) LPUART2_BASE ) +#define SPI0 ((SPI_Type *) SPI0_BASE ) +#define SPI1 ((SPI_Type *) SPI1_BASE ) +#define SPI2 ((SPI_Type *) SPI2_BASE ) +#define U7816 ((U7816_Type *) U7816_BASE ) +#define CAN ((CAN_Type *) CAN_BASE ) +#define DMA ((DMA_Type *) DMA_BASE ) +#define CRC ((CRC_Type *) CRC_BASE ) +#define ATIM ((ATIM_Type *) ATIM_BASE ) +#define GPTIM0 ((GPTIM_Type *) GPTIM0_BASE ) +#define GPTIM1 ((GPTIM_Type *) GPTIM1_BASE ) +#define GPTIM2 ((GPTIM_Type *) GPTIM2_BASE ) +#define BSTIM32 ((BSTIM32_Type *) BSTIM32_BASE ) +#define BSTIM16 ((BSTIM16_Type *) BSTIM16_BASE ) +#define LPTIM32 ((LPTIM32_Type *) LPTIM32_BASE ) +#define LPTIM16 ((LPTIM16_Type *) LPTIM16_BASE ) +#define RTCA ((RTCA_Type *) RTCA_BASE ) +#define RTCB ((RTCB_Type *) RTCB_BASE ) +#define LCD ((LCD_Type *) LCD_BASE ) +#define ADC ((ADC_Type *) ADC_BASE ) +#define DAC ((DAC_Type *) DAC_BASE ) +#define PGL ((PGL_Type *) PGL_BASE ) +#define GPIOA ((GPIO_Type *) GPIOA_BASE ) +#define GPIOB ((GPIO_Type *) GPIOB_BASE ) +#define GPIOC ((GPIO_Type *) GPIOC_BASE ) +#define GPIOD ((GPIO_Type *) GPIOD_BASE ) +#define GPIOE ((GPIO_Type *) GPIOE_BASE ) +#define GPIO ((GPIO_COMMON_Type *) GPIO_COMMON_BASE ) +#define DBG ((DBG_Type *) DBG_BASE ) + +/* ================================================================================ */ +/* ================ Peripheral include ================ */ +/* ================================================================================ */ + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group FM33LG0XX */ +/** @} */ /* End of group Keil */ + +#ifdef __cplusplus +} +#endif + +#endif /* FM33LG0XX_H */ + diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33xx.h b/bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33xx.h new file mode 100644 index 0000000000..cb9458888e --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Include/fm33xx.h @@ -0,0 +1,110 @@ +/** + **************************************************************************************************** + * @file fm33xx.h + * @author FMSH Application Team + * @brief Header file of FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +#ifndef __FM33xx_H +#define __FM33xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + + +/** + * @brief FM33 Family + */ +#if !defined (FM33xx) +#define FM33xx +#endif /* FM33XX */ +/** + * @brief CMSIS Device version number + */ +#define __FM33x0xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __FM33x0xx_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __FM33x0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __FM33x0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __FM33x0xx_CMSIS_VERSION ((__FM33x0xx_CMSIS_VERSION_MAIN << 24)\ + |(__FM33x0xx_CMSIS_VERSION_SUB1 << 16)\ + |(__FM33x0xx_CMSIS_VERSION_SUB2 << 8 )\ + |(__FM33x0xx_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ +#if defined(FM33L0XX) + #include "fm33l0xx.h" +#elif defined(FM33LC0XX) + #include "fm33lc0xx.h" +#elif defined(FM33LG0XX) + #include "fm33lg0xx.h" +#else + #error "Please select first the target FM33x0xx device used in your application (in FM33xxx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_macro + * @{ + */ + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __FM33xx_H */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT Fudan Microelectronics *****END OF FILE****/ diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Include/system_fm33lc0xx.h b/bsp/fm33lc026/libraries/FM/FM33xx/Include/system_fm33lc0xx.h new file mode 100644 index 0000000000..b947abb8b4 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Include/system_fm33lc0xx.h @@ -0,0 +1,155 @@ +/**************************************************************************//** + * @file system_fm33lc0xx.h + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for + * Device FM33LC0XX + * @version V2.00 + * @date 15. March 2021 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef SYSTEM_FM33LC0XX_H +#define SYSTEM_FM33LC0XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "fm33lc0xx.h" + +#define USE_LSCLK_CLOCK_SRC_XTLF + +//#define SYSCLK_SRC_RC4M +//#define SYSCLK_SRC_XTHF +#define SYSCLK_SRC_RCHF +//#define SYSCLK_SRC_PLL + + + +//#define USE_PLL_CLOCK_SRC_RCHF +//#define USE_PLL_CLOCK_SRC_XTHF + + +#if ((!defined(SYSCLK_SRC_RC4M)) && (!defined(SYSCLK_SRC_XTHF))&&(!defined(SYSCLK_SRC_PLL))&&(!defined(SYSCLK_SRC_RCHF))) + #error "Must select a clock source form the SYSCLK_SRC_RC4M or SYSCLK_SRC_XTHF or SYSCLK_SRC_PLL or SYSCLK_SRC_RCHF as the master clock." +#elif (((defined(SYSCLK_SRC_RC4M)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RCHF))))||\ + ((defined(SYSCLK_SRC_XTHF)) && ((defined(SYSCLK_SRC_RC4M))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RCHF))))||\ + ((defined(SYSCLK_SRC_PLL)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_RC4M))||(defined(SYSCLK_SRC_RCHF))))||\ + ((defined(SYSCLK_SRC_RCHF)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RC4M))))) + #error "Only one clock source can be selected as the master clock." +#endif + +#if defined(SYSCLK_SRC_PLL) && !defined(USE_PLL_CLOCK_SRC_RCHF) && !defined(USE_PLL_CLOCK_SRC_XTHF) + #error "You have chosen to enable the PLL, so you need to specify the clock source for the PLL.." +#elif defined(SYSCLK_SRC_PLL) && (defined(USE_PLL_CLOCK_SRC_RCHF) && defined(USE_PLL_CLOCK_SRC_XTHF)) + #error "Please select one of the USE_PLL_CLOCK_SRC_RCHF and USE_PLL_CLOCK_SRC_XTHF in your application" +#endif + +#if !defined (XTHF_VALUE) + #define XTHF_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* XTHF_VALUE */ + +#if !defined (XTLF_VALUE) + #define XTLF_VALUE ((uint32_t)32768U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* XTLF_VALUE */ + + +#define LDT_CHECK(_N_VALUE_, _T_VALUE_) \ + ((((_N_VALUE_ >> 16) & 0xffff) == \ + ((~_N_VALUE_) & 0xffff)) ? _N_VALUE_ : _T_VALUE_) + +#define LPOSC_LDT_TRIM (*(uint32_t *)0x1FFFFB20) // LPOSC 常温校准值 +#define RCHF8M_LDT_TRIM (*(uint32_t *)0x1FFFFB40) // RC8M 常温校准值 +#define RCHF16M_LDT_TRIM (*(uint32_t *)0x1FFFFB3C) // RC16M 常温校准值 +#define RCHF24M_LDT_TRIM (*(uint32_t *)0x1FFFFB38) // RC24M 常温校准值 +#define RCMF4M_LDT_TRIM (*(uint32_t *)0x1FFFFB44) // RCMF 常温校准值 + +#define LPOSC_TRIM (LDT_CHECK(LPOSC_LDT_TRIM, 0x80) & 0xff) +#define RCMF4M_TRIM (LDT_CHECK(RCMF4M_LDT_TRIM, 0x40) & 0x7f) +#define RCHF8M_TRIM (LDT_CHECK(RCHF8M_LDT_TRIM, 0x40) & 0x7f) +#define RCHF16M_TRIM (LDT_CHECK(RCHF16M_LDT_TRIM, 0x40) & 0x7f) +#define RCHF24M_TRIM (LDT_CHECK(RCHF24M_LDT_TRIM, 0x40) & 0x7f) + + +#define __SYSTEM_CLOCK (8000000) + + +/** + * @brief FL NVIC Init Sturcture definition + */ +typedef struct +{ + /* 中断抢占优先级 */ + uint32_t preemptPriority; + +}NVIC_ConfigTypeDef; + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern uint32_t SystemCoreClock; +void SystemCoreClockUpdate (void); +/** + * @brief NVIC_Init config NVIC + * + * @param NVIC_configStruct configParams + * + * @param IRQn Interrupt number + * + * @retval None + */ +void NVIC_Init(NVIC_ConfigTypeDef *NVIC_configStruct,IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_FM33LC0XX_H */ diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Include/system_fm33lg0xx.h b/bsp/fm33lc026/libraries/FM/FM33xx/Include/system_fm33lg0xx.h new file mode 100644 index 0000000000..b2737a3e79 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Include/system_fm33lg0xx.h @@ -0,0 +1,101 @@ +/**************************************************************************//** + * @file system_FM33LG0XX.h + * @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for + * Device FM33LG0XX + * @version V1.02 + * @date 31-8-2018 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef SYSTEM_FM33LG0XX_H +#define SYSTEM_FM33LG0XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "fm33lg0xx.h" + + +#if !defined (XTHF_VALUE) + #define XTHF_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* XTHF_VALUE */ + +#if !defined (XTLF_VALUE) + #define XTLF_VALUE ((uint32_t)32768U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* XTLF_VALUE */ + + +#define __SYSTEM_CLOCK (8000000) +#define DELAY_US (__SYSTEM_CLOCK/1000000) +#define DELAY_MS (__SYSTEM_CLOCK/1000) + + +#define Do_DelayStart() { \ + uint32_t LastTick = SysTick->VAL; do { + +#define While_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)VAL)&0xFFFFFF)>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; 0: WWDT + DCD SVD_IRQHandler ; 1: SVD + DCD RTC_IRQHandler ; 2: RTC + DCD FLASH_IRQHandler ; 3: FLASH + DCD LFDET_IRQHandler ; 4: LFDET + DCD ADC_IRQHandler ; 5: ADC + DCD IWDT_IRQHandler ; 6: IWDT + DCD SPI1_IRQHandler ; 7: SPI1 + DCD SPI2_IRQHandler ; 8: SPI2 + DCD LCD_IRQHandler ; 9: LCD + DCD UART0_IRQHandler ; 10: UART0 + DCD UART1_IRQHandler ; 11: UART1 + DCD UART4_IRQHandler ; 12: UART4 + DCD UART5_IRQHandler ; 13: UART5 + DCD HFDET_IRQHandler ; 14: HFDET + DCD U7816_IRQHandler ; 15: U7816 + DCD LPUART1_IRQHandler ; 16: LPUART1 + DCD I2C_IRQHandler ; 17: I2C + DCD USB_IRQHandler ; 18: USB + DCD AES_IRQHandler ; 19: AES + DCD LPTIM_IRQHandler ; 20: LPTIM + DCD DMA_IRQHandler ; 21: DMA + DCD WKUP_IRQHandler ; 22: WKUP + DCD OPAx_IRQHandler ; 23: OPAx + DCD BSTIM_IRQHandler ; 24: BSTIM + DCD COMPx_IRQHandler ; 25: COMPx + DCD GPTIM0_IRQHandler ; 26: GPTIM0 + DCD GPTIM1_IRQHandler ; 27: GPTIM1 + DCD ATIM_IRQHandler ; 28: ATIM + DCD VREF_IRQHandler ; 29: VREF + DCD GPIO_IRQHandler ; 30: GPIO + DCD LPUART0_IRQHandler ; 31: LPUART0 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LPUART0_IRQHandler [WEAK] + EXPORT GPIO_IRQHandler [WEAK] + EXPORT VREF_IRQHandler [WEAK] + EXPORT ATIM_IRQHandler [WEAK] + EXPORT GPTIM1_IRQHandler [WEAK] + EXPORT GPTIM0_IRQHandler [WEAK] + EXPORT COMPx_IRQHandler [WEAK] + EXPORT BSTIM_IRQHandler [WEAK] + EXPORT OPAx_IRQHandler [WEAK] + EXPORT WKUP_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT LPTIM_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT U7816_IRQHandler [WEAK] + EXPORT HFDET_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT IWDT_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT LFDET_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT SVD_IRQHandler [WEAK] + EXPORT WWDT_IRQHandler [WEAK] + +LPUART0_IRQHandler +GPIO_IRQHandler +VREF_IRQHandler +ATIM_IRQHandler +GPTIM1_IRQHandler +GPTIM0_IRQHandler +COMPx_IRQHandler +BSTIM_IRQHandler +OPAx_IRQHandler +WKUP_IRQHandler +DMA_IRQHandler +LPTIM_IRQHandler +AES_IRQHandler +USB_IRQHandler +I2C_IRQHandler +LPUART1_IRQHandler +U7816_IRQHandler +HFDET_IRQHandler +UART5_IRQHandler +UART4_IRQHandler +UART1_IRQHandler +UART0_IRQHandler +LCD_IRQHandler +SPI2_IRQHandler +SPI1_IRQHandler +IWDT_IRQHandler +ADC_IRQHandler +LFDET_IRQHandler +FLASH_IRQHandler +RTC_IRQHandler +SVD_IRQHandler +WWDT_IRQHandler + + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END + + *****END OF FILE***** \ No newline at end of file diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/ARM/startup_fm33lg0xx.s b/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/ARM/startup_fm33lg0xx.s new file mode 100644 index 0000000000..6e78416d53 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/ARM/startup_fm33lg0xx.s @@ -0,0 +1,233 @@ +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000800 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000800 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: WWDT + DCD SVD_IRQHandler ; 1: SVD + DCD RTC_IRQHandler ; 2: RTC + DCD FLASH_IRQHandler ; 3: FLASH + DCD FDET_IRQHandler ; 4: LFDET + DCD ADC_IRQHandler ; 5: ADC + DCD DAC_IRQHandler ; 6: DAC + DCD SPI0_IRQHandler ; 7: SPI0 + DCD SPI1_IRQHandler ; 8: SPI1 + DCD SPI2_IRQHandler ; 9: SPI2 + DCD UART0_IRQHandler ; 10: UART0 + DCD UART1_IRQHandler ; 11: UART1 + DCD UART3_IRQHandler ; 12: UART3 + DCD UART4_IRQHandler ; 13: UART4 + DCD UART5_IRQHandler ; 14: UART5 + DCD U7816_IRQHandler ; 15: U7816 + DCD LPUARTx_IRQHandler ; 16: LPUART + DCD I2C_IRQHandler ; 17: I2C + DCD CCL_IRQHandler ; 18: CCL + DCD AES_IRQHandler ; 19: AES + DCD LPTIM_IRQHandler ; 20: LPTIM + DCD DMA_IRQHandler ; 21: DMA + DCD WKUPx_IRQHandler ; 22: WKUP + DCD LUT_IRQHandler ; 23: LUT + DCD BSTIM_IRQHandler ; 24: BSTIM + DCD COMPx_IRQHandler ; 25: COMPx + DCD GPTIM0_1_IRQHandler ; 26: GPTIM0_1 + DCD GPTIM2_IRQHandler ; 27: GPTIM2 + DCD ATIM_IRQHandler ; 28: ATIM + DCD VREF_IRQHandler ; 29: VREF + DCD GPIO_IRQHandler ; 30: GPIO + DCD CAN_IRQHandler ; 31: CAN +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT CAN_IRQHandler [WEAK] + EXPORT GPIO_IRQHandler [WEAK] + EXPORT VREF_IRQHandler [WEAK] + EXPORT ATIM_IRQHandler [WEAK] + EXPORT GPTIM2_IRQHandler [WEAK] + EXPORT GPTIM0_1_IRQHandler [WEAK] + EXPORT COMPx_IRQHandler [WEAK] + EXPORT BSTIM_IRQHandler [WEAK] + EXPORT LUT_IRQHandler [WEAK] + EXPORT WKUPx_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT LPTIM_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT CCL_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT LPUARTx_IRQHandler [WEAK] + EXPORT U7816_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FDET_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT SVD_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + +CAN_IRQHandler +GPIO_IRQHandler +VREF_IRQHandler +ATIM_IRQHandler +GPTIM2_IRQHandler +GPTIM0_1_IRQHandler +COMPx_IRQHandler +BSTIM_IRQHandler +LUT_IRQHandler +WKUPx_IRQHandler +DMA_IRQHandler +LPTIM_IRQHandler +AES_IRQHandler +CCL_IRQHandler +I2C_IRQHandler +LPUARTx_IRQHandler +U7816_IRQHandler +UART5_IRQHandler +UART4_IRQHandler +UART3_IRQHandler +UART1_IRQHandler +UART0_IRQHandler +SPI2_IRQHandler +SPI1_IRQHandler +SPI0_IRQHandler +DAC_IRQHandler +ADC_IRQHandler +FDET_IRQHandler +FLASH_IRQHandler +RTC_IRQHandler +SVD_IRQHandler +WDT_IRQHandler + + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END + + *****END OF FILE***** \ No newline at end of file diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/gcc/linker/fm33lc01x_flash.ld b/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/gcc/linker/fm33lc01x_flash.ld new file mode 100644 index 0000000000..ccaa0b1758 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/gcc/linker/fm33lc01x_flash.ld @@ -0,0 +1,131 @@ +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20006000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Stack_Size = 0x400; /* amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 24K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + + /* system stack */ + PROVIDE (_stack_base = _estack - _Stack_Size); /* _estack is top of stack*/ + ASSERT ((_stack_base > end), "Error: No room left for the stack") + /* _estack is top of stack*/ + + /* left ram for heap */ + PROVIDE (heap_start = _end); + PROVIDE (heap_end = _stack_base); + PROVIDE (heap_len = heap_end - heap_start); + ASSERT ((heap_len > _Min_Heap_Size), "Error: No room left for the heap") + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/gcc/linker/fm33lc02x_flash.ld b/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/gcc/linker/fm33lc02x_flash.ld new file mode 100644 index 0000000000..ca38c861d7 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/gcc/linker/fm33lc02x_flash.ld @@ -0,0 +1,131 @@ +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20006000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Stack_Size = 0x400; /* amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 24K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + + /* system stack */ + PROVIDE (_stack_base = _estack - _Stack_Size); /* _estack is top of stack*/ + ASSERT ((_stack_base > end), "Error: No room left for the stack") + /* _estack is top of stack*/ + + /* left ram for heap */ + PROVIDE (heap_start = _end); + PROVIDE (heap_end = _stack_base); + PROVIDE (heap_len = heap_end - heap_start); + ASSERT ((heap_len > _Min_Heap_Size), "Error: No room left for the heap") + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/gcc/linker/fm33lc04x_flash.ld b/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/gcc/linker/fm33lc04x_flash.ld new file mode 100644 index 0000000000..6f639493a0 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/gcc/linker/fm33lc04x_flash.ld @@ -0,0 +1,131 @@ +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20006000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Stack_Size = 0x400; /* amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 24K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + + /* system stack */ + PROVIDE (_stack_base = _estack - _Stack_Size); /* _estack is top of stack*/ + ASSERT ((_stack_base > end), "Error: No room left for the stack") + /* _estack is top of stack*/ + + /* left ram for heap */ + PROVIDE (heap_start = _end); + PROVIDE (heap_end = _stack_base); + PROVIDE (heap_len = heap_end - heap_start); + ASSERT ((heap_len > _Min_Heap_Size), "Error: No room left for the heap") + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/gcc/startup_fm33lc0xx.s b/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/gcc/startup_fm33lc0xx.s new file mode 100644 index 0000000000..c85bd44c89 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/gcc/startup_fm33lc0xx.s @@ -0,0 +1,250 @@ + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ +// bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .global g_pfnVectors +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + /* External Interrupts */ + .word WWDT_IRQHandler /* 0: WWDT */ + .word SVD_IRQHandler /* 1: SVD */ + .word RTC_IRQHandler /* 2: RTC */ + .word FLASH_IRQHandler /* 3: FLASH */ + .word LFDET_IRQHandler /* 4: LFDET */ + .word ADC_IRQHandler /* 5: ADC */ + .word IWDT_IRQHandler /* 6: IWDT */ + .word SPI1_IRQHandler /* 7: SPI1 */ + .word SPI2_IRQHandler /* 8: SPI2 */ + .word LCD_IRQHandler /* 9: LCD */ + .word UART0_IRQHandler /* 10: UART0 */ + .word UART1_IRQHandler /* 11: UART1 */ + .word UART4_IRQHandler /* 12: UART4 */ + .word UART5_IRQHandler /* 13: UART5 */ + .word HFDET_IRQHandler /* 14: HFDET */ + .word U7816_IRQHandler /* 15: U7816 */ + .word LPUART1_IRQHandler /* 16: LPUART1 */ + .word I2C_IRQHandler /* 17: I2C */ + .word USB_IRQHandler /* 18: USB */ + .word AES_IRQHandler /* 19: AES */ + .word LPTIM_IRQHandler /* 20: LPTIM */ + .word DMA_IRQHandler /* 21: DMA */ + .word WKUP_IRQHandler /* 22: WKUP */ + .word OPAx_IRQHandler /* 23: OPAx */ + .word BSTIM_IRQHandler /* 24: BSTIM */ + .word COMPx_IRQHandler /* 25: COMPx */ + .word GPTIM0_IRQHandler /* 26: GPTIM0 */ + .word GPTIM1_IRQHandler /* 27: GPTIM1 */ + .word ATIM_IRQHandler /* 28: ATIM */ + .word VREF_IRQHandler /* 39: VREF */ + .word GPIO_IRQHandler /* 30: GPIO */ + .word LPUART0_IRQHandler /* 31: LPUART0 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak SVD_IRQHandler + .thumb_set SVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak LFDET_IRQHandler + .thumb_set LFDET_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak IWDT_IRQHandler + .thumb_set IWDT_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak HFDET_IRQHandler + .thumb_set HFDET_IRQHandler,Default_Handler + + .weak U7816_IRQHandler + .thumb_set U7816_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak LPTIM_IRQHandler + .thumb_set LPTIM_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak WKUP_IRQHandler + .thumb_set WKUP_IRQHandler,Default_Handler + + .weak OPAx_IRQHandler + .thumb_set OPAx_IRQHandler,Default_Handler + + .weak BSTIM_IRQHandler + .thumb_set BSTIM_IRQHandler,Default_Handler + + .weak COMPx_IRQHandler + .thumb_set COMPx_IRQHandler,Default_Handler + + .weak GPTIM0_IRQHandler + .thumb_set GPTIM0_IRQHandler,Default_Handler + + .weak GPTIM1_IRQHandler + .thumb_set GPTIM1_IRQHandler,Default_Handler + + .weak ATIM_IRQHandler + .thumb_set ATIM_IRQHandler,Default_Handler + + .weak VREF_IRQHandler + .thumb_set VREF_IRQHandler,Default_Handler + + .weak GPIO_IRQHandler + .thumb_set GPIO_IRQHandler,Default_Handler + + .weak LPUART0_IRQHandler + .thumb_set LPUART0_IRQHandler,Default_Handler + diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/iar/startup_fm33lc0xx.s b/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/iar/startup_fm33lc0xx.s new file mode 100644 index 0000000000..bb38b791ef --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/iar/startup_fm33lc0xx.s @@ -0,0 +1,313 @@ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; 0: WWDT + DCD SVD_IRQHandler ; 1: SVD + DCD RTC_IRQHandler ; 2: RTC + DCD FLASH_IRQHandler ; 3: FLASH + DCD LFDET_IRQHandler ; 4: LFDET + DCD ADC_IRQHandler ; 5: ADC + DCD IWDT_IRQHandler ; 6: IWDT + DCD SPI1_IRQHandler ; 7: SPI1 + DCD SPI2_IRQHandler ; 8: SPI2 + DCD LCD_IRQHandler ; 9: LCD + DCD UART0_IRQHandler ; 10: UART0 + DCD UART1_IRQHandler ; 11: UART1 + DCD UART4_IRQHandler ; 12: UART4 + DCD UART5_IRQHandler ; 13: UART5 + DCD HFDET_IRQHandler ; 14: HFDET + DCD U7816_IRQHandler ; 15: U7816 + DCD LPUART1_IRQHandler ; 16: LPUART1 + DCD I2C_IRQHandler ; 17: I2C + DCD USB_IRQHandler ; 18: USB + DCD AES_IRQHandler ; 19: AES + DCD LPTIM_IRQHandler ; 20: LPTIM + DCD DMA_IRQHandler ; 21: DMA + DCD WKUP_IRQHandler ; 22: WKUP + DCD OPAx_IRQHandler ; 23: OPAx + DCD BSTIM_IRQHandler ; 24: BSTIM + DCD COMPx_IRQHandler ; 25: COMPx + DCD GPTIM0_IRQHandler ; 26: GPTIM0 + DCD GPTIM1_IRQHandler ; 27: GPTIM1 + DCD ATIM_IRQHandler ; 28: ATIM + DCD VREF_IRQHandler ; 29: VREF + DCD GPIO_IRQHandler ; 30: GPIO + DCD LPUART0_IRQHandler ; 31: LPUART0 +__Vectors_End + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDT_IRQHandler + B WWDT_IRQHandler + + + PUBWEAK SVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SVD_IRQHandler + B SVD_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK LFDET_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LFDET_IRQHandler + B LFDET_IRQHandler + + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK IWDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +IWDT_IRQHandler + B IWDT_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK HFDET_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HFDET_IRQHandler + B HFDET_IRQHandler + + + PUBWEAK U7816_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U7816_IRQHandler + B U7816_IRQHandler + + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AES_IRQHandler + B AES_IRQHandler + + + PUBWEAK LPTIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM_IRQHandler + B LPTIM_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WKUP_IRQHandler + B WKUP_IRQHandler + + PUBWEAK OPAx_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OPAx_IRQHandler + B OPAx_IRQHandler + + + + PUBWEAK OPA1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OPA1_IRQHandler + B OPA1_IRQHandler + + + PUBWEAK BSTIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BSTIM_IRQHandler + B BSTIM_IRQHandler + + + PUBWEAK COMPx_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMPx_IRQHandler + B COMPx_IRQHandler + + + + PUBWEAK OPA2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OPA2_IRQHandler + B OPA2_IRQHandler + + + PUBWEAK GPTIM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPTIM0_IRQHandler + B GPTIM0_IRQHandler + + + PUBWEAK GPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPTIM1_IRQHandler + B GPTIM1_IRQHandler + + + PUBWEAK ATIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ATIM_IRQHandler + B ATIM_IRQHandler + + + PUBWEAK VREF_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +VREF_IRQHandler + B VREF_IRQHandler + + + PUBWEAK GPIO_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIO_IRQHandler + B GPIO_IRQHandler + + + PUBWEAK LPUART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART0_IRQHandler + B LPUART0_IRQHandler + END \ No newline at end of file diff --git a/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/iar/startup_fm33lg0xx.s b/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/iar/startup_fm33lg0xx.s new file mode 100644 index 0000000000..4004ec6326 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM/FM33xx/Source/Templates/iar/startup_fm33lg0xx.s @@ -0,0 +1,299 @@ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: WWDT + DCD SVD_IRQHandler ; 1: SVD + DCD RTC_IRQHandler ; 2: RTC + DCD FLASH_IRQHandler ; 3: FLASH + DCD FDET_IRQHandler ; 4: LFDET + DCD ADC_IRQHandler ; 5: ADC + DCD DAC_IRQHandler ; 6: DAC + DCD SPI0_IRQHandler ; 7: SPI0 + DCD SPI1_IRQHandler ; 8: SPI1 + DCD SPI2_IRQHandler ; 9: SPI2 + DCD UART0_IRQHandler ; 10: UART0 + DCD UART1_IRQHandler ; 11: UART1 + DCD UART3_IRQHandler ; 12: UART3 + DCD UART4_IRQHandler ; 13: UART4 + DCD UART5_IRQHandler ; 14: UART5 + DCD U7816_IRQHandler ; 15: U7816 + DCD LPUARTx_IRQHandler ; 16: LPUART + DCD I2C_IRQHandler ; 17: I2C + DCD CCL_IRQHandler ; 18: CCL + DCD AES_IRQHandler ; 19: AES + DCD LPTIM_IRQHandler ; 20: LPTIM + DCD DMA_IRQHandler ; 21: DMA + DCD WKUPx_IRQHandler ; 22: WKUP + DCD LUT_IRQHandler ; 23: LUT + DCD BSTIM_IRQHandler ; 24: BSTIM + DCD COMPx_IRQHandler ; 25: COMPx + DCD GPTIM0_1_IRQHandler ; 26: GPTIM0_1 + DCD GPTIM2_IRQHandler ; 27: GPTIM2 + DCD ATIM_IRQHandler ; 28: ATIM + DCD VREF_IRQHandler ; 29: VREF + DCD GPIO_IRQHandler ; 30: GPIO + DCD CAN_IRQHandler ; 31: CAN +__Vectors_End + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WDT_IRQHandler + B WDT_IRQHandler + + + PUBWEAK SVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SVD_IRQHandler + B SVD_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK FDET_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDET_IRQHandler + B FDET_IRQHandler + + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DAC_IRQHandler + B DAC_IRQHandler + + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + + PUBWEAK U7816_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +U7816_IRQHandler + B U7816_IRQHandler + + + PUBWEAK LPUARTx_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUARTx_IRQHandler + B LPUARTx_IRQHandler + + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + PUBWEAK CCL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CCL_IRQHandler + B CCL_IRQHandler + + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AES_IRQHandler + B AES_IRQHandler + + + PUBWEAK LPTIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM_IRQHandler + B LPTIM_IRQHandler + + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + + PUBWEAK WKUPx_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WKUPx_IRQHandler + B WKUPx_IRQHandler + + PUBWEAK LUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LUT_IRQHandler + B LUT_IRQHandler + + + PUBWEAK BSTIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BSTIM_IRQHandler + B BSTIM_IRQHandler + + + PUBWEAK COMPx_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMPx_IRQHandler + B COMPx_IRQHandler + + + PUBWEAK GPTIM0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPTIM0_1_IRQHandler + B GPTIM0_1_IRQHandler + + + PUBWEAK GPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPTIM2_IRQHandler + B GPTIM2_IRQHandler + + + PUBWEAK ATIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ATIM_IRQHandler + B ATIM_IRQHandler + + + PUBWEAK VREF_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +VREF_IRQHandler + B VREF_IRQHandler + + + PUBWEAK GPIO_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIO_IRQHandler + B GPIO_IRQHandler + + + PUBWEAK CAN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN_IRQHandler + B CAN_IRQHandler + END \ No newline at end of file diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/core_cm0plus.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000..e39c6f33ff --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1000 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.00 + * @date 29. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/* Common defines in core_*.h files + - #define __ASM Compiler keyword for asm + - #define __INLINE Compiler keyword for inline + - #define __STATIC_INLINE Compiler keyword for static inline + - #define __NO_RETURN function that never returns + - #define __USED function or variable that is not optimized away + - #define __WEAK weak function or variable + - #define __UNALIGNED_UINT32 pointer to unaligned uint32_t variable + */ +#if defined ( __CC_ARM ) /* ARM Compiler 4/5 */ + #define __ASM __asm + #define __INLINE __inline + #define __STATIC_INLINE static __inline + #define __NO_RETURN __declspec(noreturn) + #define __USED __attribute__((used)) + #define __WEAK __attribute__((weak)) + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler 6 */ + #define __ASM __asm + #define __INLINE __inline + #define __STATIC_INLINE static __inline + #define __NO_RETURN __attribute__((noreturn)) + #define __USED __attribute__((used)) + #define __WEAK __attribute__((weak)) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + +#elif defined ( __GNUC__ ) /* GNU Compiler */ + #define __ASM __asm + #define __INLINE inline + #define __STATIC_INLINE static inline + #define __NO_RETURN __attribute__((noreturn)) + #define __USED __attribute__((used)) + #define __WEAK __attribute__((weak)) + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + +#elif defined ( __ICCARM__ ) /* IAR Compiler */ + #define __ASM __asm + #define __INLINE inline + #define __STATIC_INLINE static inline + #define __NO_RETURN __noreturn + #define __USED + #define __WEAK __weak +// struct __packed T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + +#elif defined ( __TI_ARM__ ) /* TI ARM Compiler */ + #define __ASM __asm + #define __INLINE inline + #define __STATIC_INLINE static inline + #define __NO_RETURN __attribute__((noreturn)) + #define __USED __attribute__((used)) + #define __WEAK __attribute__((weak)) + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + +#elif defined ( __TASKING__ ) /* TASKING Compiler */ + #define __ASM __asm + #define __INLINE inline + #define __STATIC_INLINE static inline + #define __NO_RETURN __attribute__((noreturn)) + #define __USED __attribute__((used)) + #define __WEAK __attribute__((weak)) + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + +#elif defined ( __CSMC__ ) /* COSMIC Compiler */ + #define __packed + #define __ASM _asm + #define __INLINE inline + #define __STATIC_INLINE static inline + #define __NO_RETURN + #define __USED + #define __WEAK + #define __UNALIGNED_UINT32(x) (*x) + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cminstr.h" /* Core Instruction Access */ +#include "core_cmfunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be nagative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be nagative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be nagative. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be nagative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be nagative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/core_cmFunc.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000000..b6ad0a4c5f --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,664 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Set Base Priority with condition + + This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Set Base Priority with condition + + This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/core_cmInstr.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000000..fca425c51d --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,916 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0) + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0) + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0) + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end + + result = value; // r will be reversed bits of v; first get LSB of v + for (value >>= 1; value; value >>= 1) + { + result <<= 1; + result |= value & 1; + s--; + } + result <<= s; // shift when v's highest bits are zero + return(result); +} +#endif + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end + + result = value; // r will be reversed bits of v; first get LSB of v + for (value >>= 1; value; value >>= 1) + { + result <<= 1; + result |= value & 1; + s--; + } + result <<= s; // shift when v's highest bits are zero +#endif + return(result); +} + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33_assert.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33_assert.h new file mode 100644 index 0000000000..63b5620081 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33_assert.h @@ -0,0 +1,41 @@ +/** + **************************************************************************************************** + * @file fm33_assert.h + * @author FMSH Application Team + * @brief Assert function define + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +#ifndef __FM33_ASSERT_H +#define __FM33_ASSERT_H +#include "fm33xx.h" +#ifdef __cplusplus + extern "C" { +#endif + + +#ifdef USE_FULL_ASSERT +#define assert_param(expr) do{if((expr) == 0)for(;;);}while(0) +#else +#define assert_param(expr) ((void)0U) +#endif + +#ifdef __cplusplus +} +#endif + + +#endif + diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33lc0xx.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33lc0xx.h new file mode 100644 index 0000000000..1d8974cfb0 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33lc0xx.h @@ -0,0 +1,795 @@ + +/****************************************************************************************************//** + * @file FM33LC0XX.h + * + * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for + * FM33LC0XX from Keil. + * + * @version V0.0.1 + * @date 13. august 2019 + * + * @note Generated with SVDConv V2.87e + * from CMSIS SVD File 'FM33LC0XX.SVD' Version 1.0, + * + * @par ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontroller, but can be equally used for other + * suitable processor architectures. This file can be freely distributed. + * Modifications to this file shall be clearly marked. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + *******************************************************************************************************/ + + +/** @addtogroup Keil + * @{ + */ + +/** @addtogroup FM33LC0XX + * @{ + */ + +#ifndef __FM33LC0XX_H +#define __FM33LC0XX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Configuration of the Cortex-M0 Processor and Core Peripherals + */ +#define __CM0_REV 0x0100U /*!< Cortex-M0 Core Revision */ +#define __MPU_PRESENT 0U /*!< MPU present or not */ +#define __VTOR_PRESENT 1U /*!< VTOR present or not */ +#define __NVIC_PRIO_BITS 2U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + + +/** + * @brief FM33LC0XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum { +/****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NMI_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/****** FM33LC0XX specific Interrupt Numbers ******************************************************************/ + WWDT_IRQn = 0, /*!< 0 Window WatchDog Interrupt */ + SVD_IRQn = 1, /*!< 1 SVD Interrupt */ + RTC_IRQn = 2, /*!< 2 RTC Interrupt */ + FLASH_IRQn = 3, /*!< 3 FLASH global Interrupt */ + LFDET_IRQn = 4, /*!< 4 LFDET Interrupt */ + ADC_IRQn = 5, /*!< 5 ADC Interrupt */ + IWDT_IRQn = 6, /*!< 6 IWDT Interrupt */ + SPI1_IRQn = 7, /*!< 7 SPI1 Interrupt */ + SPI2_IRQn = 8, /*!< 8 SPI2 Interrupt */ + LCD_IRQn = 9, /*!< 9 LCD Interrupt */ + UART0_IRQn = 10, /*!< 10 UART0 global Interrupt */ + UART1_IRQn = 11, /*!< 11 UART1 global Interrupt */ + UART4_IRQn = 12, /*!< 12 UART4 global Interrupt */ + UART5_IRQn = 13, /*!< 13 UART5 global Interrupt */ + HFDET_IRQn = 14, /*!< 14 HFDET Interrupt */ + U7816_IRQn = 15, /*!< 15 U7816 Interrupt */ + LPUART1_IRQn = 16, /*!< 16 LPUART1 Interrupt */ + I2C_IRQn = 17, /*!< 17 I2C global Interrupt */ + USB_IRQn = 18, /*!< 18 USB Interrupt */ + AES_IRQn = 19, /*!< 19 AES Interrupt */ + LPTIM_IRQn = 20, /*!< 20 LPTIM Interrupt */ + DMA_IRQn = 21, /*!< 21 DMA Interrupt */ + WKUP_IRQn = 22, /*!< 22 WKUP Interrupt */ + OPAx_IRQn = 23, /*!< 23 OPAx Interrupt */ + BSTIM_IRQn = 24, /*!< 24 BSTIM Interrupt */ + COMPx_IRQn = 25, /*!< 25 COMPx Interrupt */ + GPTIM0_IRQn = 26, /*!< 26 GTIM0 global Interrupt */ + GPTIM1_IRQn = 27, /*!< 27 GTIM1 global Interrupt */ + ATIM_IRQn = 28, /*!< 28 ATIM global Interrupt */ + VREF_IRQn = 29, /*!< 29 VREF Interrupt */ + GPIO_IRQn = 30, /*!< 30 GPIO Interrupt */ + LPUART0_IRQn = 31 /*!< 31 LPUART0 Interrupt */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + + +#include "core_cm0plus.h" /*!< Cortex-M0 processor and core peripherals */ +#include "system_fm33lc0xx.h" /*!< FM33LC0XX System */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC Control Register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Config Register, Address offset: 0x0C */ + __IO uint32_t SMTR; /*!< ADC Sampling Time Register, Address offset: 0x10 */ + __IO uint32_t CHER; /*!< ADC Channel Enable Register, Address offset: 0x14 */ + __IO uint32_t DR; /*!< ADC Data Register, Address offset: 0x18 */ + __IO uint32_t SAMPT; /*!< ADC Calibration Register, Address offset: 0x1C */ + __IO uint32_t HLTR; /*!< ADC analog watchdog Threshold Register, Address offset: 0x20 */ +} ADC_Type; + +typedef struct +{ + __IO uint32_t CR; /*!< AES Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t DIR; /*!< AES Data Input Register, Address offset: 0x0C */ + __IO uint32_t DOR; /*!< AES Data Output Register, Address offset: 0x10 */ + __IO uint32_t KEY0; /*!< AES Key Register 0, Address offset: 0x14 */ + __IO uint32_t KEY1; /*!< AES Key Register 1, Address offset: 0x18 */ + __IO uint32_t KEY2; /*!< AES Key Register 2, Address offset: 0x1C */ + __IO uint32_t KEY3; /*!< AES Key Register 3, Address offset: 0x20 */ + __IO uint32_t KEY4; /*!< AES Key Register 4, Address offset: 0x24 */ + __IO uint32_t KEY5; /*!< AES Key Register 5, Address offset: 0x28 */ + __IO uint32_t KEY6; /*!< AES Key Register 6, Address offset: 0x2C */ + __IO uint32_t KEY7; /*!< AES Key Register 7, Address offset: 0x30 */ + __IO uint32_t IVR0; /*!< AES Initial Vector Register 0, Address offset: 0x34 */ + __IO uint32_t IVR1; /*!< AES Initial Vector Register 1, Address offset: 0x38 */ + __IO uint32_t IVR2; /*!< AES Initial Vector Register 2, Address offset: 0x3C */ + __IO uint32_t IVR3; /*!< AES Initial Vector Register 3, Address offset: 0x40 */ +} AES_Type; + +typedef struct +{ + __IO uint32_t CR1; /*!< ATIM Control Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< ATIM Control Register2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< ATIM Slave Mode Control Register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< ATIM DMA and Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< ATIM Interrupt Status Register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< ATIM Event Generation Register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< ATIM Capture/Compare Mode Register1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< ATIM Capture/Compare Mode Register2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< ATIM Capture/Compare Enable Register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< ATIM Counter Register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< ATIM Prescaler Register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< ATIM Auto-Reload Register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< ATIM Repetition Counter Register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< ATIM Capture/Compare Register1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< ATIM Capture/Compare Register2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< ATIM Capture/Compare Register3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< ATIM Capture/Compare Register4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< ATIM Break and Deadtime Register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< ATIM DMA Control Register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< ATIM DMA Access Register, Address offset: 0x4C */ + __IO uint32_t RSV0; /*!< RESERVED REGISTER0, Address offset: 0x50 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER1, Address offset: 0x54 */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER2, Address offset: 0x58 */ + __IO uint32_t RSV3; /*!< RESERVED REGISTER3, Address offset: 0x5C */ + __IO uint32_t BKCR; /*!< ATIM Break Control Register, Address offset: 0x60 */ +} ATIM_Type; + +typedef struct +{ + __IO uint32_t CR1; /*!< BSTIM Control Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< BSTIM Control Register2, Address offset: 0x04 */ + __IO uint32_t RSV0; /*!< RESERVED REGISTER0, Address offset: 0x08 */ + __IO uint32_t IER; /*!< BSTIM Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< BSTIM Interrupt Status Register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< BSTIM Event Generation Register, Address offset: 0x14 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER1, Address offset: 0x18 */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER2, Address offset: 0x1C */ + __IO uint32_t RSV3; /*!< RESERVED REGISTER3, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< BSTIM Counter Register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< BSTIM Prescaler Register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< BSTIM Auto-Reload Register, Address offset: 0x2C */ +} BSTIM32_Type; + +typedef struct +{ + __IO uint32_t CR; /*!< ComparatorControl Register 1, Address offset: 0x00 */ + +} COMP_Type; + +typedef struct +{ + __IO uint32_t ICR; /*!< Comparator Interrupt Config Register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< Comparator Interrupt Status Register, Address offset: 0x0C */ +} COMP_COMMON_Type; + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< CRC Control Register, Address offset: 0x04 */ + __IO uint32_t LFSR; /*!< CRC Linear Feedback Shift Register, Address offset: 0x08 */ + __IO uint32_t XOR; /*!< CRC output XOR Register, Address offset: 0x0C */ + __IO uint32_t RSV0; /*!< RESERVED REGISTER0, Address offset: 0x10 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER1, Address offset: 0x14 */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER2, Address offset: 0x18 */ + __IO uint32_t POLY; /*!< CRC Polynominal Register, Address offset: 0x1C */ +} CRC_Type; + +typedef struct +{ + __IO uint32_t RSV; + __IO uint32_t CR; /*!< Debug Configuration Register */ + __IO uint32_t HDFR; /*!< HardFault Flag Register*/ + +} DBG_Type; + +typedef struct +{ + __IO uint32_t GCR; /*!< DMA Global Control Register , Address offset: 0x00 */ + __IO uint32_t CH0CR; /*!< Channel 0 Control Register , Address offset: 0x04 */ + __IO uint32_t CH0MAD; /*!< Channel 0 Memory Address Register , Address offset: 0x08 */ + __IO uint32_t CH1CR; /*!< Channel 1 Control Register , Address offset: 0x0C */ + __IO uint32_t CH1MAD; /*!< Channel 1 Memory Address Register , Address offset: 0x10 */ + __IO uint32_t CH2CR; /*!< Channel 2 Control Register , Address offset: 0x14 */ + __IO uint32_t CH2MAD; /*!< Channel 2 Memory Address Register , Address offset: 0x18 */ + __IO uint32_t CH3CR; /*!< Channel 3 Control Register , Address offset: 0x1C */ + __IO uint32_t CH3MAD; /*!< Channel 3 Memory Address Register , Address offset: 0x20 */ + __IO uint32_t CH4CR; /*!< Channel 4 Control Register , Address offset: 0x24 */ + __IO uint32_t CH4MAD; /*!< Channel 4 Memory Address Register , Address offset: 0x28 */ + __IO uint32_t CH5CR; /*!< Channel 5 Control Register , Address offset: 0x2C */ + __IO uint32_t CH5MAD; /*!< Channel 5 Memory Address Register , Address offset: 0x30 */ + __IO uint32_t CH6CR; /*!< Channel 6 Control Register , Address offset: 0x34 */ + __IO uint32_t CH6MAD; /*!< Channel 6 Memory Address Register , Address offset: 0x38 */ + __IO uint32_t CH7CR; /*!< Channel 7 Control Register , Address offset: 0x3C */ + __IO uint32_t CH7FLSAD; /*!< Channel 7 Flash Address Register , Address offset: 0x40 */ + __IO uint32_t CH7RAMAD; /*!< Channel 7 RAM Address Register , Address offset: 0x44 */ + __IO uint32_t ISR; /*!< DMA Interrupt Status Register , Address offset: 0x48 */ +} DMA_Type; + +typedef struct +{ + __IO uint32_t IER; /*!< XTLF Oscillation Fail Detection Interrupt Enable Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< XTLF Oscillation Fail Detection Interrupt Status Register, Address offset: 0x04 */ +}FDET_Type; + + +typedef struct +{ + __IO uint32_t RDCR; /*!< Flash Read Control Register, Address offset: 0x00 */ + __IO uint32_t PFCR; /*!< Flash Prefetch Control Register, Address offset: 0x04 */ + __I uint32_t OPTBR; /*!< Flash Option Bytes Register, Address offset: 0x08 */ + __IO uint32_t ACLOCK1; /*!< Flash Application Code Lock Register 1, Address offset: 0x0C */ + __IO uint32_t ACLOCK2; /*!< Flash Application Code Lock Register 2, Address offset: 0x10 */ + __IO uint32_t EPCR; /*!< Flash Erase/Program Control Register, Address offset: 0x14 */ + __IO uint32_t KEY; /*!< Flash Key Register, Address offset: 0x18 */ + __IO uint32_t IER; /*!< Flash Interrupt Enable Register, Address offset: 0x1C */ + __IO uint32_t ISR; /*!< Flash Interrupt Status Register, Address offset: 0x20 */ +} FLASH_Type; + +typedef struct +{ + __IO uint32_t INEN; /*!< Input Enable Register */ + __IO uint32_t PUEN; /*!< Pull-Up Enable Register */ + __IO uint32_t ODEN; /*!< Open-Drain Enable Register */ + __IO uint32_t FCR; /*!< Function Control Register */ + __IO uint32_t DO; /*!< Data Output Register */ + __O uint32_t DSET; /*!< Data Set Register */ + __O uint32_t DRST; /*!< Data Reset Register */ + __I uint32_t DIN; /*!< Data Input RegisterR */ + __IO uint32_t DFS; /*!< Digital Function Select */ + __IO uint32_t RSV; /*!< RESERVED REGISTER */ + __IO uint32_t ANEN; /*!< Analog channel Enable Register */ +} GPIO_Type; + +typedef struct +{ + __IO uint32_t EXTISEL; /*!< External Interrupt input Select Register */ + __IO uint32_t EXTIEDS; /*!< External Interrupt Edge Select and Enable Register */ + __IO uint32_t EXTIDF; /*!< External Interrupt Digital Filter Register */ + __IO uint32_t EXTIISR; /*!< External Interrupt and Status Register */ + __IO uint32_t EXTIDI; /*!< External Interrupt Data Input Register */ + __IO uint32_t RSV0[59]; /*!< RESERVED REGISTER */ + __IO uint32_t FOUTSEL; /*!< Frequency Output Select Register */ + __IO uint32_t RSV1[63]; /*!< RESERVED REGISTER */ + __IO uint32_t PINWKEN; /*!< Wakeup Enable Register */ +} GPIO_COMMON_Type; + +typedef struct +{ + __IO uint32_t CR1; /*!< GPTIM Control Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< GPTIM Control Register2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< GPTIM Slave Mode Control Register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< GPTIM DMA and Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< GPTIM Interrupt Status Register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< GPTIM EVENT GENERATE REGISTER, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< GPTIM Capture/Compare Mode Register1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< GPTIM Capture/Compare Mode Register2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< GPTIM Capture/Compare Enable Register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< GPTIM Counter Register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< GPTIM Prescaler Register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< GPTIM Auto-Reload Register, Address offset: 0x2C */ + __IO uint32_t RSV0; /*!< RESERVED REGISTER0, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< GPTIM Capture/Compare Register1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< GPTIM Capture/Compare Register2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< GPTIM Capture/Compare Register3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< GPTIM Capture/Compare Register4, Address offset: 0x40 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER1, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< GPTIM DMA CONTROL REGISTER, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< GPTIM DMA access Register, Address offset: 0x4C */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER2, Address offset: 0x50 */ + __IO uint32_t RSV3; /*!< RESERVED REGISTER3, Address offset: 0x54 */ + __IO uint32_t RSV4; /*!< RESERVED REGISTER4, Address offset: 0x58 */ + __IO uint32_t RSV5; /*!< RESERVED REGISTER5, Address offset: 0x5C */ + __IO uint32_t ITRSEL; /*!< GPTIM Internal Trigger Select Register, Address offset: 0x60 */ +} GPTIM_Type; + +typedef struct +{ + __IO uint32_t END; /*!< Dividend Register, Address offset: 0x00 */ + __IO uint32_t SOR; /*!< Divisor Regsiter, Address offset: 0x04 */ + __IO uint32_t QUOT; /*!< Quotient Register, Address offset: 0x08 */ + __IO uint32_t REMD; /*!< Reminder Register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< Status Register, Address offset: 0x10 */ +} DIV_Type; + + +typedef struct +{ + __IO uint32_t MSPCFGR; /*!< I2C Master Config Register, Address offset: 0x00 */ + __IO uint32_t MSPCR; /*!< I2C Master Control Register, Address offset: 0x04 */ + __IO uint32_t MSPIER; /*!< I2C Master Intterupt Enable Register, Address offset: 0x08 */ + __IO uint32_t MSPISR; /*!< I2C Master Interrupt Status Register, Address offset: 0x0C */ + __IO uint32_t MSPSR; /*!< I2C Master Status Register, Address offset: 0x10 */ + __IO uint32_t MSPBGR; /*!< I2C Master Baud rate Generator Register, Address offset: 0x14 */ + __IO uint32_t MSPBUF; /*!< I2C Master transfer Buffer, Address offset: 0x18 */ + __IO uint32_t MSPTCR; /*!< I2C Master Timing Control Register, Address offset: 0x1C */ + __IO uint32_t MSPTOR; /*!< I2C Master Time-Out Register, Address offset: 0x20 */ + __IO uint32_t SSPCR; /*!< I2C Slave Control Register, Address offset: 0x24 */ + __IO uint32_t SSPIER; /*!< I2C Slave Interrupt Enable Register, Address offset: 0x28 */ + __IO uint32_t SSPISR; /*!< I2C Slave Interrupt Status Register, Address offset: 0x2C */ + __IO uint32_t SSPSR; /*!< I2C Slave Status Register, Address offset: 0x30 */ + __IO uint32_t SSPBUF; /*!< I2C Slave transfer Buffer, Address offset: 0x34 */ + __IO uint32_t SSPADR; /*!< I2C Slave Address Register, Address offset: 0x38 */ +} I2C_Type; + +typedef struct +{ + __IO uint32_t SERV; /*!< IWDT Service Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< IWDT Config Register, Address offset: 0x04 */ + __I uint32_t CNT; /*!< IWDT Counter Register, Address offset: 0x08 */ + __IO uint32_t WIN; /*!< IWDT Window Register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< IWDT Status Register, Address offset: 0x10 */ + __IO uint32_t ISR; /*!< IWDT Status Register, Address offset: 0x10 */ +} IWDT_Type; + +typedef struct +{ + __IO uint32_t CR; /*!< LCD Control Register, Address offset: 0x00 */ + __IO uint32_t TEST; /*!< LCD test Register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< LCD Frequency Control Register, Address offset: 0x08 */ + __IO uint32_t FLKT; /*!< LCD Flick Time Register, Address offset: 0x0C */ + __IO uint32_t RSV0; /*!< NULL, Address offset: 0x10 */ + __IO uint32_t IER; /*!< LCD Interrupt Enable Register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< LCD Interrupt Status Register, Address offset: 0x18 */ + __IO uint32_t RSV1; /*!< NULL, Address offset: 0x1C */ + __IO uint32_t RSV2; /*!< NULL, Address offset: 0x20 */ + __IO uint32_t DATA0; /*!< LCD data buffer registers 0, Address offset: 0x24 */ + __IO uint32_t DATA1; /*!< LCD data buffer registers 1, Address offset: 0x28 */ + __IO uint32_t DATA2; /*!< LCD data buffer registers 2, Address offset: 0x2C */ + __IO uint32_t DATA3; /*!< LCD data buffer registers 3, Address offset: 0x30 */ + __IO uint32_t DATA4; /*!< LCD data buffer registers 4, Address offset: 0x34 */ + __IO uint32_t DATA5; /*!< LCD data buffer registers 5, Address offset: 0x38 */ + __IO uint32_t DATA6; /*!< LCD data buffer registers 6, Address offset: 0x3C */ + __IO uint32_t DATA7; /*!< LCD data buffer registers 7, Address offset: 0x40 */ + __IO uint32_t RSV3; /*!< NULL, Address offset: 0x44 */ + __IO uint32_t RSV4; /*!< NULL, Address offset: 0x48 */ + __IO uint32_t RSV5; /*!< NULL, Address offset: 0x4C */ + __IO uint32_t COMEN; /*!< LCD COM Enable Register, Address offset: 0x50 */ + __IO uint32_t SEGEN0; /*!< LCD SEG Enable Register0, Address offset: 0x54 */ +} LCD_Type; + +typedef struct +{ + __IO uint32_t CFGR; /*!< LPTIM Config Register, Address offset: 0x00 */ + __IO uint32_t CNT; /*!< LPTIM Counter Register, Address offset: 0x04 */ + __IO uint32_t CCSR; /*!< LPTIM Capture/Compare Control and Status Register, Address offset: 0x08 */ + __IO uint32_t ARR; /*!< LPTIM Auto-Reload Register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable Register, Address offset: 0x10 */ + __IO uint32_t ISR; /*!< LPTIM Interrupt Status Register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< LPTIM Control Register, Address offset: 0x18 */ + __IO uint32_t RSV; /*!< RESERVED REGISTER, Address offset: 0x1C */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare Register1, Address offset: 0x20 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare Register2, Address offset: 0x24 */ +} LPTIM32_Type; + +typedef struct +{ + __IO uint32_t CSR; /*!< LPUART Control Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< LPUART Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< LPUART Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t BMR; /*!< LPUART Baud rate Modulation Register, Address offset: 0x0C */ + __IO uint32_t RXBUF; /*!< LPUART Receive Buffer Register, Address offset: 0x10 */ + __IO uint32_t TXBUF; /*!< LPUART Transmit Buffer Register, Address offset: 0x14 */ + __IO uint32_t DMR; /*!< LPUART data Matching Register, Address offset: 0x18 */ +} LPUART_Type; + + +typedef struct +{ + __IO uint32_t CR; /*!< OPA Control Register */ + __IO uint32_t CALR; /*!< OPA Calibration Register */ + __IO uint32_t IER; /*!< OPA Interrupt Enable Register */ + __IO uint32_t ISR; /*!< OPA Interrupt Status Register */ +} OPA_Type; + +typedef struct +{ + __IO uint32_t CR; /*!< Power Management Control Register */ + __IO uint32_t WKTR; /*!< Wakeup Time Register */ + __IO uint32_t WKFR; /*!< Wakeup Source Flags Register */ + __IO uint32_t IER; /*!< PMU Interrupt Enable Register */ + __IO uint32_t ISR; /*!< PMU Interrupt and Status Register */ +} PMU_Type; + +typedef struct +{ + __IO uint32_t LKPCR; /*!< Lockup reset Control Register , Address offset: 0x00 */ + __IO uint32_t SOFTRST; /*!< Software Reset Register , Address offset: 0x04 */ + __IO uint32_t RSTFR; /*!< Reset Flag Register , Address offset: 0x08 */ + __IO uint32_t SYSCLKCR; /*!< System Clock Control Register , Address offset: 0x0C */ + __IO uint32_t RCHFCR; /*!< RCHF Control Register , Address offset: 0x10 */ + __IO uint32_t RCHFTR; /*!< RCHF Trim Register , Address offset: 0x14 */ + __IO uint32_t PLLCR; /*!< PLL Control Register , Address offset: 0x18 */ + __IO uint32_t LPOSCCR; /*!< LPOSC Control Register , Address offset: 0x1C */ + __IO uint32_t LPOSCTR; /*!< LPOSC Trim Register , Address offset: 0x20 */ + __IO uint32_t XTLFCR; /*!< XTLF CONFIG REGISTER , Address offset: 0x24 */ + __IO uint32_t PCLKCR1; /*!< Peripheral bus Clock Control Register1 , Address offset: 0x28 */ + __IO uint32_t PCLKCR2; /*!< Peripheral bus Clock Control Register2 , Address offset: 0x2C */ + __IO uint32_t PCLKCR3; /*!< Peripheral bus Clock Control Register3 , Address offset: 0x30 */ + __IO uint32_t PCLKCR4; /*!< Peripheral bus Clock Control Register4 , Address offset: 0x34 */ + __IO uint32_t LSCLKSEL; /*!< LSCLK Select Register , Address offset: 0x38 */ + __IO uint32_t RSV0; /*!< RESERVED REGISTER 1 , Address offset: 0x3C */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER 2 , Address offset: 0x40 */ + __IO uint32_t AHBMCR; /*!< AHB Master Control Register , Address offset: 0x44 */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER 3 , Address offset: 0x48 */ + __IO uint32_t RSV3; /*!< RESERVED REGISTER 4 , Address offset: 0x4C */ + __IO uint32_t PRSTEN; /*!< Peripheral Reset Enable Register , Address offset: 0x50 */ + __IO uint32_t AHBRSTCR; /*!< AHB Peripherals Reset Control Register , Address offset: 0x54 */ + __IO uint32_t APBRSTCR1; /*!< APB Peripherals Reset Control Register1 , Address offset: 0x58 */ + __IO uint32_t APBRSTCR2; /*!< APB Peripherals Reset Control Register2 , Address offset: 0x5C */ + __IO uint32_t XTHFCR; /*!< XTHF Control Register , Address offset: 0x60 */ + __IO uint32_t RCMFCR; /*!< RCMF Control Register , Address offset: 0x64 */ + __IO uint32_t RCMFTR; /*!< RCHF Trim Register , Address offset: 0x68 */ + __IO uint32_t OPCCR1; /*!< Peripheral Operation Clock Control Register1, Address offset: 0x6C */ + __IO uint32_t OPCCR2; /*!< Peripheral Operation Clock Control Register2, Address offset: 0x70 */ + __IO uint32_t PHYCR; /*!< PHY Control Register , Address offset: 0x74 */ + __IO uint32_t PHYBCKCR; /*!< PHY BCK Control Register , Address offset: 0x78 */ +} RCC_Type; + + +typedef struct +{ + __IO uint32_t PDRCR; /*!< PDR Control Register */ + __IO uint32_t BORCR; /*!< BOR Control Register */ +} RMU_Type; + +typedef struct +{ + __IO uint32_t CR; /*!< RNG CONTROL REGISTER, */ +} RNGCTL_Type; + +typedef struct +{ + __IO uint32_t RSV0; /*!< RESERVED REGISTER, Address offset: 0x00 */ + __IO uint32_t DOR; /*!< RNG OUTPUT REGISTER, Address offset: 0x04 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x08 */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER, Address offset: 0x0C */ + __IO uint32_t SR; /*!< RNG FLAG REGISTER, Address offset: 0x10 */ + __IO uint32_t CRCCR; /*!< RNG CRC CONTROL REGISTER, Address offset: 0x14 */ + __IO uint32_t CRCDIR; /*!< RNG CRC INPUT REGISTER, Address offset: 0x18 */ + __IO uint32_t CRCSR; /*!< RNG CRC FLAG REGISTER, Address offset: 0x1C */ +} RNG_Type; + +typedef struct +{ + __IO uint32_t WER; /*!< RTC Write Enable Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< RTC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< RTC Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t BCDSEC; /*!< RTC SECOND IN BCD REGISTER, Address offset: 0x0C */ + __IO uint32_t BCDMIN; /*!< RTC MINITE IN BCD REGISTER, Address offset: 0x10 */ + __IO uint32_t BCDHOUR; /*!< RTC HOUR IN BCD REGISTER, Address offset: 0x14 */ + __IO uint32_t BCDDAY; /*!< RTC DAY IN BCD REGISTER, Address offset: 0x18 */ + __IO uint32_t BCDWEEK; /*!< RTC WEEK IN BCD REGISTER, Address offset: 0x1C */ + __IO uint32_t BCDMONTH; /*!< RTC MONTH IN BCD REGISTER, Address offset: 0x20 */ + __IO uint32_t BCDYEAR; /*!< RTC YEAR IN BCD REGISTER, Address offset: 0x24 */ + __IO uint32_t ALARM; /*!< RTC Alarm Register, Address offset: 0x28 */ + __IO uint32_t TMSEL; /*!< RTC Time Mark Select, Address offset: 0x2C */ + __IO uint32_t ADJUST; /*!< RTC time Adjust Register, Address offset: 0x30 */ + __IO uint32_t ADSIGN; /*!< RTC time Adjust Sign Register, Address offset: 0x34 */ + __IO uint32_t RSV0; /*!< NULL, Address offset: 0x38 */ + __IO uint32_t SBSCNT; /*!< RTC Sub-Second Counter, Address offset: 0x3C */ + __IO uint32_t RSV1[12]; /*!< NULL, Address offset: 0x40 */ + __IO uint32_t BKR0; /*!< RTC BACKUP REGISTER0, Address offset: 0x70 */ + __IO uint32_t BKR1; /*!< RTC BACKUP REGISTER1, Address offset: 0x74 */ + __IO uint32_t BKR2; /*!< RTC BACKUP REGISTER2, Address offset: 0x78 */ + __IO uint32_t BKR3; /*!< RTC BACKUP REGISTER3, Address offset: 0x7C */ + __IO uint32_t BKR4; /*!< RTC BACKUP REGISTER4, Address offset: 0x80 */ + __IO uint32_t BKR5; /*!< RTC BACKUP REGISTER5, Address offset: 0x84 */ + __IO uint32_t BKR6; /*!< RTC BACKUP REGISTER6, Address offset: 0x88 */ + __IO uint32_t BKR7; /*!< RTC BACKUP REGISTER7, Address offset: 0x8C */ +} RTC_Type; + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI1 Control Register1 */ + __IO uint32_t CR2; /*!< SPI1 Control Register2 */ + __IO uint32_t CR3; /*!< SPI1 Control Register3 */ + __IO uint32_t IER; /*!< SPI1 Interrupt Enable Register */ + __IO uint32_t ISR; /*!< SPI1 Status Register */ + __IO uint32_t TXBUF; /*!< SPI1 Transmit Buffer */ + __IO uint32_t RXBUF; /*!< SPI1 Receive Buffer */ +} SPI_Type; + + +typedef struct +{ + __IO uint32_t CFGR; /*!< SVD Config Register, Address offset: 0x24 */ + __IO uint32_t CR; /*!< SVD Control Register, Address offset: 0x28 */ + __IO uint32_t IER; /*!< SVD Interrupt Enable Register, Address offset: 0x2C */ + __IO uint32_t ISR; /*!< SVD Interrupt Status Register, Address offset: 0x30 */ + __IO uint32_t VSR; /*!< SVD reference Voltage Select Register, Address offset: 0x34 */ +} SVD_Type; + +typedef struct +{ + __IO uint32_t CR; /*!< U7816 Control Register, Address offset: 0x00 */ + __IO uint32_t FFR; /*!< U7816 Frame Format Register, Address offset: 0x04 */ + __IO uint32_t EGTR; /*!< U7816 Extra Guard Time Register, Address offset: 0x08 */ + __IO uint32_t PSC; /*!< U7816 Prescaler Register, Address offset: 0x0C */ + __IO uint32_t BGR; /*!< U7816 Baud rate Generator Register, Address offset: 0x10 */ + __IO uint32_t RXBUF; /*!< U7816 Receive Buffer, Address offset: 0x14 */ + __IO uint32_t TXBUF; /*!< U7816 Transmit Buffer, Address offset: 0x18 */ + __IO uint32_t IER; /*!< U7816 Interrupt Enable Register, Address offset: 0x1C */ + __IO uint32_t ISR; /*!< U7816 Interrupt Status Register, Address offset: 0x20 */ +} U7816_Type; + +typedef struct +{ + __IO uint32_t RSV0; /*!< RESERVED REGISTER0, Address offset: 0x00 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER1, Address offset: 0x04 */ + __IO uint32_t GAHBCFG; /*!< USB AHB Global Config Register, Address offset: 0x08 */ + __IO uint32_t GUSBCFG; /*!< USB Global Config Register, Address offset: 0x0C */ + __IO uint32_t GRSTCTL; /*!< USB Global Reset Control Register, Address offset: 0x10 */ + __IO uint32_t GINTSTS; /*!< USB Global Interrupt Status Register, Address offset: 0x14 */ + __IO uint32_t GINTMSK; /*!< USB Global Interrupt Mask Register, Address offset: 0x18 */ + __IO uint32_t GRXSTSR; /*!< USB Receive Status Debug Read Register, Address offset: 0x1C */ + __IO uint32_t GRXSTSP; /*!< USB Receive Status and Pop Register, Address offset: 0x20 */ + __IO uint32_t GRXFSIZ; /*!< USB Receive FIFO size Register, Address offset: 0x24 */ + __IO uint32_t GNPTXFSIZ; /*!< USB Non-Periodic Transmit FIFO size Register, Address offset: 0x28 */ + __IO uint32_t RSV2[10]; /*!< Reserved */ + __IO uint32_t GLPMCFG; /*!< USB Low-Power-Mode config Register, Address offset: 0x54 */ + __IO uint32_t RSV3[490]; /*!< Reserved */ + __IO uint32_t DCFG; /*!< USB Device Config Register, Address offset: 0x800*/ + __IO uint32_t DCTL; /*!< USB Device Control Register, Address offset: 0x804*/ + __IO uint32_t DSTS; /*!< USB Device Status Register, Address offset: 0x808*/ + __IO uint32_t DIEPMSK; /*!< USB Device In Endpoint Interrupt Mask Register, Address offset: 0x810*/ + __IO uint32_t DOEPMSK; /*!< USB Device OUT Endpoint Interrupt Mask Registe, Address offset: 0x814*/ + __IO uint32_t DAINT; /*!< USB Device All Endpoint Interrupt Register, Address offset: 0x818*/ + __IO uint32_t DAINTMSK; /*!< USB Device All Endpoint Interrupt Mask Register, Address offset: 0x81C*/ + __IO uint32_t RSV4[5]; /*!< Reserved */ + __IO uint32_t DIEPEMPMSK; /*!< USB Device IN endpoint FIFO empty interrupt Mask Register,Address offset: 0x834 */ + __IO uint32_t RSV5[50]; /*!< Reserved */ + __IO uint32_t DIEPCTL0; /*!< USB Device In Endpoint 0 Control Register, Address offset: 0x900*/ + __IO uint32_t RSV6; /*!< Reserved */ + __IO uint32_t DIEPINT0; /*!< USB Device In Endpoint 0 Interrupt Register, Address offset: 0x908*/ + __IO uint32_t RSV7; /*!< Reserved */ + __IO uint32_t DIEPTSIZ0; /*!< USB Device IN Endpoint 0 Transfer Size Register, Address offset: 0x910*/ + __IO uint32_t RSV8; /*!< Reserved */ + __IO uint32_t DTXFSTS0; /*!< USB Device In Endpoint 0 Tranmit FIFO Status Register,Address offset: 0x918 */ + __IO uint32_t RSV9; /*!< Reserved */ + __IO uint32_t DIEPCTL1; /*!< USB Device In Endpoint 1 Control Register, Address offset: 0x920*/ + __IO uint32_t RSV10; /*!< Reserved */ + __IO uint32_t DIEPINT1; /*!< USB Device In Endpoint 1 Interrupt Register, Address offset: 0x928*/ + __IO uint32_t RSV11; /*!< Reserved */ + __IO uint32_t DIEPTSIZ1; /*!< USB Device IN Endpoint 1 Transfer Size Register, Address offset: 0x930*/ + __IO uint32_t RSV12; /*!< Reserved */ + __IO uint32_t DTXFSTS1; /*!< USB Device In Endpoint 1 Tranmit FIFO Status Register,Address offset: 0x938 */ + __IO uint32_t RSV13; /*!< Reserved */ + __IO uint32_t DIEPCTL2; /*!< USB Device In Endpoint 2 Control Register, Address offset: 0x940*/ + __IO uint32_t RSV14; /*!< Reserved */ + __IO uint32_t DIEPINT2; /*!< USB Device In Endpoint 2 Interrupt Register, Address offset: 0x948*/ + __IO uint32_t RSV15; /*!< Reserved */ + __IO uint32_t DIEPTSIZ2; /*!< USB Device In Endpoint 2 Tranmit FIFO Status Register,Address offset: 0x950 */ + __IO uint32_t RSV16; /*!< Reserved */ + __IO uint32_t DTXFSTS2; /*!< USB Device In Endpoint 2 Tranmit FIFO Status Register,Address offset: 0x958 */ + __IO uint32_t RSV17[105]; /*!< Reserved */ + __IO uint32_t DOEPCTL0; /*!< USB Device Out Endpoint 0 Control Register, Address offset: 0xB00*/ + __IO uint32_t RSV18; /*!< Reserved */ + __IO uint32_t DOEPINT0; /*!< USB Device Out Endpoint 0 Interrupt Register, Address offset: 0xB08*/ + __IO uint32_t RSV19; /*!< Reserved */ + __IO uint32_t DOEPTSIZ0; /*!< USB Device Out Endpoint 0 Transfer Size Register, Address offset: 0xB10*/ + __IO uint32_t RSV20; /*!< Reserved */ + __IO uint32_t RSV21; /*!< Reserved */ + __IO uint32_t RSV22; /*!< Reserved */ + __IO uint32_t DOEPCTL1; /*!< USB Device Out Endpoint 1 Control Register, Address offset: 0xB20*/ + __IO uint32_t RSV23; /*!< Reserved */ + __IO uint32_t DOEPINT1; /*!< USB Device Out Endpoint 1 Interrupt Register, Address offset: 0xB28*/ + __IO uint32_t RSV24; /*!< Reserved */ + __IO uint32_t DOEPTSIZ1; /*!< USB Device Out Endpoint 1 Transfer Size Register, Address offset: 0xB30*/ + __IO uint32_t RSV25; /*!< Reserved */ + __IO uint32_t RSV26; /*!< Reserved */ + __IO uint32_t RSV27; /*!< Reserved */ + __IO uint32_t DOEPCTL2; /*!< USB Device Out Endpoint 2 Control Register, Address offset: 0xB40*/ + __IO uint32_t RSV28; /*!< Reserved */ + __IO uint32_t DOEPINT2; /*!< USB Device Out Endpoint 2 Interrupt Register, Address offset: 0xB48*/ + __IO uint32_t RSV29; /*!< Reserved */ + __IO uint32_t DOEPTSIZ2; /*!< USB Device Out Endpoint 2 Transfer Size Register, Address offset: 0xB50*/ + __IO uint32_t RSV30[171]; /*!< Reserved */ + __IO uint32_t PCGCCTL; /*!< USB Power Control Global Control Register, Address offset: 0xE00*/ +} USB_Type; + +typedef struct +{ + __IO uint32_t IRCR; /*!< Infrared modulation Control Register */ +} UART_COMMON_Type; + +typedef struct +{ + __IO uint32_t CSR; /*!< UART Control Status Register */ + __IO uint32_t IER; /*!< UART Interrupt Enable Register */ + __IO uint32_t ISR; /*!< UART Interrupt Status Register */ + __IO uint32_t TODR; /*!< UART Time-Out and Delay Register */ + __IO uint32_t RXBUF; /*!< UART Receive Buffer */ + __IO uint32_t TXBUF; /*!< UART Transmit Buffer */ + __IO uint32_t BGR; /*!< UART Baud rate Generator Register */ +} UART_Type; + + +typedef struct +{ + __IO uint32_t CR; /*!< VREF Control Register */ + __IO uint32_t SR; /*!< VREF Status Register */ + __IO uint32_t IER; /*!< VREF Interrupt Enable Register */ + __IO uint32_t BUFCR; /*!< VREF Interrupt Enable Register */ +} VREF_Type; + +typedef struct +{ + __IO uint32_t CR; /*!< WWDT Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< WWDT Config Register, Address offset: 0x04 */ + __IO uint32_t CNT; /*!< WWDT Counter Register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< WWDT Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< WWDT Interrupt Status Register, Address offset: 0x10 */ + __IO uint32_t PSC; /*!< WWDT Prescaler Register, Address offset: 0x14 */ +} WWDT_Type; + + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE 0x00000000UL /*!< FLASH(up to 1 MB) base address in the alias region */ +#define SRAM_BASE 0x20000000UL +#define PERIPH_BASE 0x40000000UL + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +/*!< Peripheral memory map */ +#define DBG_BASE (PERIPH_BASE + 0x00000000UL) +#define PMU_BASE (PERIPH_BASE + 0x00000100UL) +#define RCC_BASE (PERIPH_BASE + 0x00000200UL) +#define DMA_BASE (PERIPH_BASE + 0x00000400UL) +#define GPIOA_BASE (PERIPH_BASE + 0x00000C00UL) +#define GPIOB_BASE (PERIPH_BASE + 0x00000C40UL) +#define GPIOC_BASE (PERIPH_BASE + 0x00000C80UL) +#define GPIOD_BASE (PERIPH_BASE + 0x00000CC0UL) +#define GPIO_COMMON_BASE (PERIPH_BASE + 0x00000D00UL) +#define FLASH_R_BASE (PERIPH_BASE + 0x00001000UL) +#define U7816_BASE (PERIPH_BASE + 0x00010000UL) +#define LPUART0_BASE (PERIPH_BASE + 0x00010400UL) +#define SPI2_BASE (PERIPH_BASE + 0x00010800UL) +#define LCD_BASE (PERIPH_BASE + 0x00010C00UL) +#define RTC_BASE (PERIPH_BASE + 0x00011000UL) +#define IWDT_BASE (PERIPH_BASE + 0x00011400UL) +#define WWDT_BASE (PERIPH_BASE + 0x00011800UL) +#define UART0_BASE (PERIPH_BASE + 0x00011C00UL) +#define UART1_BASE (PERIPH_BASE + 0x00012000UL) +#define I2C_BASE (PERIPH_BASE + 0x00012400UL) +#define LPTIM32_BASE (PERIPH_BASE + 0x00013400UL) +#define GPTIM0_BASE (PERIPH_BASE + 0x00013800UL) +#define GPTIM1_BASE (PERIPH_BASE + 0x00013C00UL) +#define CRC_BASE (PERIPH_BASE + 0x00018000UL) +#define LPUART1_BASE (PERIPH_BASE + 0x00018400UL) +#define SPI1_BASE (PERIPH_BASE + 0x00018C00UL) +#define DIVAS_BASE (PERIPH_BASE + 0x00019000UL) +#define UART_COMMON_BASE (PERIPH_BASE + 0x00019C00UL) +#define UART4_BASE (PERIPH_BASE + 0x0001A000UL) +#define UART5_BASE (PERIPH_BASE + 0x0001A400UL) +#define RMU_BASE (PERIPH_BASE + 0x0001A800UL) +#define VREF_BASE (PERIPH_BASE + 0x0001A80CUL) +#define SVD_BASE (PERIPH_BASE + 0x0001A824UL) +#define FDET_BASE (PERIPH_BASE + 0x0001A838UL) +#define OPA1_BASE (PERIPH_BASE + 0x0001A844UL) +#define OPA2_BASE (PERIPH_BASE + 0x0001A854UL) +#define RNGCTL_BASE (PERIPH_BASE + 0x0001A868UL) +#define COMP1_BASE (PERIPH_BASE + 0x0001A870UL) +#define COMP2_BASE (PERIPH_BASE + 0x0001A874UL) +#define COMP_COMMON_BASE (PERIPH_BASE + 0x0001A878UL) +#define ADC_BASE (PERIPH_BASE + 0x0001AC00UL) +#define AES_BASE (PERIPH_BASE + 0x0001B800UL) +#define RNG_BASE (PERIPH_BASE + 0x0001BC00UL) +#define ATIM_BASE (PERIPH_BASE + 0x0001B000UL) +#define BSTIM32_BASE (PERIPH_BASE + 0x0001B400UL) +#define USB_BASE (PERIPH_BASE + 0x10000000UL) +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define DBG ((DBG_Type *) DBG_BASE) +#define PMU ((PMU_Type *) PMU_BASE) +#define VREF ((VREF_Type *) VREF_BASE) +#define RCC ((RCC_Type *) RCC_BASE) +#define RMU ((RMU_Type *) RMU_BASE) +#define DMA ((DMA_Type *) DMA_BASE) +#define GPIOA ((GPIO_Type *) GPIOA_BASE) +#define GPIOB ((GPIO_Type *) GPIOB_BASE) +#define GPIOC ((GPIO_Type *) GPIOC_BASE) +#define GPIOD ((GPIO_Type *) GPIOD_BASE) +#define GPIO ((GPIO_COMMON_Type *) GPIO_COMMON_BASE) +#define FLASH ((FLASH_Type *) FLASH_R_BASE) +#define CRC ((CRC_Type *) CRC_BASE) +#define LPUART0 ((LPUART_Type *) LPUART0_BASE) +#define LPUART1 ((LPUART_Type *) LPUART1_BASE) +#define SPI1 ((SPI_Type *) SPI1_BASE) +#define SPI2 ((SPI_Type *) SPI2_BASE) +#define LCD ((LCD_Type *) LCD_BASE) +#define RTC ((RTC_Type *) RTC_BASE) +#define IWDT ((IWDT_Type *) IWDT_BASE) +#define WWDT ((WWDT_Type *) WWDT_BASE) +#define U7816 ((U7816_Type *) U7816_BASE) +#define UART ((UART_COMMON_Type *) UART_COMMON_BASE) +#define UART0 ((UART_Type *) UART0_BASE) +#define UART1 ((UART_Type *) UART1_BASE) +#define UART4 ((UART_Type *) UART4_BASE) +#define UART5 ((UART_Type *) UART5_BASE) +#define I2C ((I2C_Type *) I2C_BASE) +#define FDET ((FDET_Type *) FDET_BASE) +#define SVD ((SVD_Type *) SVD_BASE) +#define OPA1 ((OPA_Type *) OPA1_BASE) +#define OPA2 ((OPA_Type *) OPA2_BASE) +#define LPTIM32 ((LPTIM32_Type *) LPTIM32_BASE) +#define AES ((AES_Type *) AES_BASE) +#define RNG ((RNG_Type *) RNG_BASE) +#define RNGCTL ((RNGCTL_Type *) RNGCTL_BASE) +#define ATIM ((ATIM_Type *) ATIM_BASE) +#define GPTIM0 ((GPTIM_Type *) GPTIM0_BASE) +#define GPTIM1 ((GPTIM_Type *) GPTIM1_BASE) +#define BSTIM32 ((BSTIM32_Type *) BSTIM32_BASE) +#define ADC ((ADC_Type *) ADC_BASE) +#define COMP1 ((COMP_Type *) COMP1_BASE) +#define COMP2 ((COMP_Type *) COMP2_BASE) +#define COMP ((COMP_COMMON_Type*)COMP_COMMON_BASE) +#define DIV ((DIV_Type *) DIVAS_BASE) +#define USB ((USB_Type *) USB_BASE) +/* ================================================================================ */ +/* ================ Peripheral include ================ */ +/* ================================================================================ */ + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group FM33LC0XX */ +/** @} */ /* End of group Keil */ + +#ifdef __cplusplus +} +#endif + +#endif /* FM33LC0XX_H */ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33lg0xx.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33lg0xx.h new file mode 100644 index 0000000000..d45f47b1fc --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33lg0xx.h @@ -0,0 +1,1122 @@ +/**************************************************************************************************** * @file FM33LG0XX.h + * + * @brief CMSIS CORTEX-M0 Peripheral Access Layer Header File for + * FM33LG0XX from Keil. + * + * @version V0.0.1 + * @date 14 july 2020 + * + * @note Generated with SVDConv V2.87e + * from CMSIS SVD File 'FM33LG0XX.SVD' Version 1.0, + * + * @par ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontroller, but can be equally used for other + * suitable processor architectures. This file can be freely distributed. + * Modifications to this file shall be clearly marked. + * + * THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + *******************************************************************************************************/ + + +/** @addtogroup Keil + * @{ + */ + +/** @addtogroup FM33LG0XX + * @{ + */ + +#ifndef __FM33LG0XX_H +#define __FM33LG0XX_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#define __RCHF_INITIAL_CLOCK (8000000) /* Value of the Internal RC HIGH oscillator in Hz */ +#define __RCLP_CLOCK (32000) /* Value of the Internal RC LOW oscillator in Hz */ +#define __XTHF_CLOCK (8000000) /* Value of the EXTERNAL oscillator in Hz */ +#define __XTLF_CLOCK (32768) /* Value of the EXTERNAL oscillator in Hz */ + +/** + * @brief Configuration of the Cortex-M0 Processor and Core Peripherals + */ +#define __CM0_REV 0x0100U /*!< Cortex-M0 Core Revision */ +#define __MPU_PRESENT 1U /*!< MPU present or not */ +#define __VTOR_PRESENT 1U /*!< VTOR present or not */ +#define __NVIC_PRIO_BITS 2U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +/* ------------------------- Interrupt Number Definition ------------------------ */ + +/** + * @brief FM33LG0XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +typedef enum { +/****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/ + Reset_IRQn = -15, /*!< 1 复位向量 */ + NMI_IRQn = -14, /*!< 2 WKUPx中断、低功耗模式错误中断 */ + HardFault_IRQn = -13, /*!< 3 HardFault中断向量 */ + SVC_IRQn = -5, /*!< 11 SVCall系统服务请求 */ + PendSV_IRQn = -2, /*!< 14 可挂起系统服务请求 */ + SysTick_IRQn = -1, /*!< 15 内部定时器中断向量 */ + +/* -------------------- FM33LG0XX specific Interrupt Numbers --------------------*/ + WWDT_IRQn = 0, /*!< 0 窗口看门狗或独立看门狗中断 */ + SVD_IRQn = 1, /*!< 1 电源监测报警中断 */ + RTCx_IRQn = 2, /*!< 2 实时时钟中断 */ + FLASH_IRQn = 3, /*!< 3 NVMIF中断 */ + FDET_IRQn = 4, /*!< 4 XTLF或XTHF停振检测中断、系统时钟选择错误中断 */ + ADC_IRQn = 5, /*!< 5 ADC转换完成中断 */ + DAC_IRQn = 6, /*!< 6 DAC中断 */ + SPI0_IRQn = 7, /*!< 7 SPI0中断 */ + SPI1_IRQn = 8, /*!< 8 SPI1中断 */ + SPI2_IRQn = 9, /*!< 9 SPI2中断 */ + UART0_IRQn = 10, /*!< 10 UART0中断 */ + UART1_IRQn = 11, /*!< 11 UART1中断 */ + UART3_IRQn = 12, /*!< 12 UART3中断 */ + UART4_IRQn = 13, /*!< 13 UART4中断 */ + UART5_IRQn = 14, /*!< 14 UART5中断 */ + U7816_IRQn = 15, /*!< 15 U7816中断 */ + LPUARTx_IRQn = 16, /*!< 16 LPUART0/1/2中断 */ + I2C_IRQn = 17, /*!< 17 I2C中断 */ + CCL_IRQn = 18, /*!< 18 时钟校准中断 */ + AES_IRQn = 19, /*!< 19 AES中断 */ + LPTIMx_IRQn = 20, /*!< 20 LPTIM16或LPTIM32中断 */ + DMA_IRQn = 21, /*!< 21 DMA中断 */ + WKUPx_IRQn = 22, /*!< 22 WKUP引脚中断 */ + LUT_IRQn = 23, /*!< 23 LUT中断 */ + BSTIM_IRQn = 24, /*!< 24 BSTIM16或BSTIM32中断 */ + COMPx_IRQn = 25, /*!< 25 COMPx中断 */ + GPTIM01_IRQn = 26, /*!< 26 通用定时器0,1中断 */ + GPTIM2_IRQn = 27, /*!< 27 通用定时器2中断 */ + ATIM_IRQn = 28, /*!< 28 高级定时器中断 */ + VREF_IRQn = 29, /*!< 29 1.2V内部基准电压建立中断、VREF_VREG中断 */ + GPIO_IRQn = 30, /*!< 30 外部引脚中断 */ + CAN_IRQn = 31, /*!< 31 CAN2.0中断 */ + +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +#include "core_cm0plus.h" /*!< Cortex-M0 processor and core peripherals */ +#include "system_fm33lg0xx.h" /*!< FM33LG0XX System */ + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +//#elif defined(__GNUC__) +///* anonymous unions are enabled by default */ +//#elif defined(__TMS470__) +///* anonymous unions are enabled by default */ +//#elif defined(__TASKING__) +// #pragma warning 586 +#else +#warning Not supported compiler type +#endif + + +/* ================================================================================ */ +/* ================ FLS ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t RDCR; /*!< Flash Read Control Register, Address offset: 0x00 */ + __IO uint32_t PFCR; /*!< Flash Prefetch Control Register, Address offset: 0x04 */ + __I uint32_t OPTBR; /*!< Flash Option Bytes Register, Address offset: 0x08 */ + __IO uint32_t ACLOCK1; /*!< Flash Application Code Lock Register1, Address offset: 0x0C */ + __IO uint32_t ACLOCK2; /*!< Flash Application Code Lock Register2, Address offset: 0x10 */ + __IO uint32_t EPCR; /*!< Flash Erase/Program Control Register, Address offset: 0x14 */ + __O uint32_t KEY; /*!< Flash Key Register, Address offset: 0x18 */ + __IO uint32_t IER; /*!< Flash Interrupt Enable Register, Address offset: 0x1C */ + __IO uint32_t ISR; /*!< Flash Interrupt Status Register, Address offset: 0x20 */ +}FLASH_Type; + + +/* ================================================================================ */ +/* ================ PMU ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< Power Management Control Register, Address offset: 0x00 */ + __IO uint32_t WKTR; /*!< Wakeup Time Register, Address offset: 0x04 */ + __IO uint32_t WKFR; /*!< Wakeup Source Flags Register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< PMU Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< PMU Interrupt and Status Register, Address offset: 0x10 */ + __IO uint32_t RSV1[9]; /*!< RESERVED REGISTER, Address offset: 0x14 */ + __IO uint32_t ULPB_TR; /*!< ULPBG trim Register, Address offset: 0x38 */ + __IO uint32_t VREFP_CR; /*!< VREFP Control Register, Address offset: 0x3C */ + __IO uint32_t VREFP_CFGR; /*!< VREFP Config Register, Address offset: 0x40 */ + __IO uint32_t VREFP_ISR; /*!< VREFP Interrupt Status Register, Address offset: 0x44 */ + __IO uint32_t VREFP_TR; /*!< VREFP Trim Register, Address offset: 0x48 */ +}PMU_Type; + +/* ================================================================================ */ +/* ================ VREFP ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< VREFP Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< VREFP Config Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< VREFP Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t TR; /*!< VREFP Trim Register, Address offset: 0x0C */ +}VREFP_Type; + +/* ================================================================================ */ +/* ================ VREF ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< VREF Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< VREF Config Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< VREF Status Register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< VREF Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t BUFCR; /*!< Buffer Control Register, Address offset: 0x10 */ +}VREF_Type; + + +/* ================================================================================ */ +/* ================ VAO ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t RSV1[512]; /*!< RESERVED REGISTER, Address offset: 0x00 */ + __IO uint32_t RSTCR; /*!< VBAT Reset Control Register, Address offset: 0x800 */ + __IO uint32_t XTLFCR; /*!< XTLF Control Register, Address offset: 0x804 */ + __IO uint32_t XTLFPR; /*!< XTLF Power Register, Address offset: 0x808 */ + __IO uint32_t FDIER; /*!< XTLF Oscillation Fail Detection Interrupt Enable Register,Address offset: 0x80C */ + __IO uint32_t FDISR; /*!< XTLF Oscillation Fail Detection Interrupt Status Register,Address offset: 0x810 */ + __IO uint32_t RSV2[251]; /*!< RESERVED REGISTER, Address offset: 0x814 */ + __IO uint32_t INEN; /*!< VAO IO Input Enable Register, Address offset: 0xC00 */ + __IO uint32_t PUEN; /*!< VAO IO Pull-up Enable Register, Address offset: 0xC04 */ + __IO uint32_t ODEN; /*!< VAO IO Open Drain Enable Register, Address offset: 0xC08 */ + __IO uint32_t FCR; /*!< VAO IO Function Control Register, Address offset: 0xC0C */ + __IO uint32_t DOR; /*!< VAO IO Data Output Register, Address offset: 0xC10 */ + __I uint32_t DIR; /*!< VAO IO Data Input Register, Address offset: 0xC14 */ + __IO uint32_t VILR; /*!< VAO IO Voltage Input Low Register, Address offset: 0xC18 */ +}VAO_Type; + + +/* ================================================================================ */ +/* ================ CDIF ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< , Address offset: 0x00 */ + __IO uint32_t PRSC; /*!< , Address offset: 0x04 */ +}CDIF_Type; + + +/* ================================================================================ */ +/* ================ RMU ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t PDRCR; /*!< PDR Control Register, Address offset: 0x00 */ + __IO uint32_t BORCR; /*!< BOR Control Register, Address offset: 0x04 */ + __IO uint32_t LKPCR; /*!< Reset Config Register, Address offset: 0x08 */ + __O uint32_t SOFTRST; /*!< Software Reset Register, Address offset: 0x0C */ + __IO uint32_t RSTFR; /*!< Reset Flag Register, Address offset: 0x10 */ + __O uint32_t PRSTEN; /*!< Peripheral Reset Enable Register, Address offset: 0x14 */ + __IO uint32_t AHBRSTCR; /*!< AHB Peripherals Reset Register, Address offset: 0x18 */ + __IO uint32_t APBRSTCR1; /*!< APB Peripherals Reset Register1, Address offset: 0x1C */ + __IO uint32_t APBRSTCR2; /*!< APB Peripherals Reset Register2, Address offset: 0x20 */ +}RMU_Type; + + +/* ================================================================================ */ +/* ================ IWDT ================ */ +/* ================================================================================ */ + +typedef struct +{ + __O uint32_t SERV; /*!< IWDT Service Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< IWDT Config Register, Address offset: 0x04 */ + __I uint32_t CNT; /*!< IWDT Counter Register, Address offset: 0x08 */ + __IO uint32_t WIN; /*!< IWDT Window Register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< IWDT Interrupt Enable Register, Address offset: 0x10 */ + __IO uint32_t ISR; /*!< IWDT Interrupt Status Register, Address offset: 0x14 */ +}IWDT_Type; + + +/* ================================================================================ */ +/* ================ WWDT ================ */ +/* ================================================================================ */ + +typedef struct +{ + __O uint32_t CR; /*!< WWDT Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< WWDT Config Register, Address offset: 0x04 */ + __I uint32_t CNT; /*!< WWDT Counter Register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< WWDT Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< WWDT Interrupt Status Register, Address offset: 0x10 */ + __I uint32_t PSC; /*!< WWDT Prescaler Register, Address offset: 0x14 */ +}WWDT_Type; + + +/* ================================================================================ */ +/* ================ CMU ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t SYSCLKCR; /*!< System Clock Control Register, Address offset: 0x00 */ + __IO uint32_t RCHFCR; /*!< RCHF Control Register, Address offset: 0x04 */ + __IO uint32_t RCHFTR; /*!< RCHF Trim Register, Address offset: 0x08 */ + __IO uint32_t PLLCR; /*!< PLL Control Register, Address offset: 0x0C */ + __IO uint32_t RCLPCR; /*!< RCLP Control Register, Address offset: 0x10 */ + __IO uint32_t RCLPTR; /*!< RCLP Trim Register, Address offset: 0x14 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x18 */ + __IO uint32_t LSCLKSEL; /*!< LSCLK Select Register, Address offset: 0x1C */ + __IO uint32_t XTHFCR; /*!< XTHF Control Register, Address offset: 0x20 */ + __IO uint32_t RCLFCR; /*!< RCLF Control Register, Address offset: 0x24 */ + __IO uint32_t RCLFTR; /*!< RCLF Trim Register, Address offset: 0x28 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x2C */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x30 */ + __IO uint32_t PCLKCR1; /*!< Peripheral bus Clock Control Register1, Address offset: 0x34 */ + __IO uint32_t PCLKCR2; /*!< Peripheral bus Clock Control Register2, Address offset: 0x38 */ + __IO uint32_t PCLKCR3; /*!< Peripheral bus Clock Control Register3, Address offset: 0x3C */ + __IO uint32_t PCLKCR4; /*!< Peripheral bus Clock Control Register4, Address offset: 0x40 */ + __IO uint32_t OPCCR1; /*!< Peripheral Clock Config Register1, Address offset: 0x44 */ + __IO uint32_t OPCCR2; /*!< Peripheral Clock Config Register 2, Address offset: 0x48 */ + __IO uint32_t OPCCR3; /*!< Peripheral Clock Config Register 3, Address offset: 0x4C */ + __IO uint32_t AHBMCR; /*!< AHB Master Control Register, Address offset: 0x50 */ + __IO uint32_t CCCR; /*!< Clock Calibration Control Register, Address offset: 0x54 */ + __IO uint32_t CCFR; /*!< Clock Calibration Config Register, Address offset: 0x58 */ + __I uint32_t CCNR; /*!< Clock Calibration Counter Register, Address offset: 0x5C */ + __IO uint32_t CCISR; /*!< Clock Calibration Interrupt Status Register, Address offset: 0x60 */ +}CMU_Type; + + +/* ================================================================================ */ +/* ================ SVD ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CFGR; /*!< SVD Config Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< SVD Control Register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< SVD Interrupt Enable Register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< SVD Interrupt Status Register, Address offset: 0x0C */ + __IO uint32_t VSR; /*!< SVD reference Voltage Select Register, Address offset: 0x10 */ +}SVD_Type; + + +/* ================================================================================ */ +/* ================ AES ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< AES Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t DIR; /*!< AES Data Input Register, Address offset: 0x0C */ + __I uint32_t DOR; /*!< AES Data Output Register, Address offset: 0x10 */ + __IO uint32_t KEY0; /*!< AES Key Register 0, Address offset: 0x14 */ + __IO uint32_t KEY1; /*!< AES Key Register 1, Address offset: 0x18 */ + __IO uint32_t KEY2; /*!< AES Key Register 2, Address offset: 0x1C */ + __IO uint32_t KEY3; /*!< AES Key Register 3, Address offset: 0x20 */ + __IO uint32_t KEY4; /*!< AES Key Register 4, Address offset: 0x24 */ + __IO uint32_t KEY5; /*!< AES Key Register 5, Address offset: 0x28 */ + __IO uint32_t KEY6; /*!< AES Key Register 6, Address offset: 0x2C */ + __IO uint32_t KEY7; /*!< AES Key Register 7, Address offset: 0x30 */ + __IO uint32_t IVR0; /*!< AES Initial Vector Register 0, Address offset: 0x34 */ + __IO uint32_t IVR1; /*!< AES Initial Vector Register 1, Address offset: 0x38 */ + __IO uint32_t IVR2; /*!< AES Initial Vector Register 2, Address offset: 0x3C */ + __IO uint32_t IVR3; /*!< AES Initial Vector Register 3, Address offset: 0x40 */ + __IO uint32_t H0; /*!< AES MultH parameter Register 0, Address offset: 0x44 */ + __IO uint32_t H1; /*!< AES MultH parameter Register 1, Address offset: 0x48 */ + __IO uint32_t H2; /*!< AES MultH parameter Register 2, Address offset: 0x4C */ + __IO uint32_t H3; /*!< AES MultH parameter Register 3, Address offset: 0x50 */ +}AES_Type; + + +/* ================================================================================ */ +/* ================ RNG ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< Random Number Generator Control Register, Address offset: 0x00 */ + __I uint32_t DOR; /*!< Random Number Generator Data Output Register, Address offset: 0x04 */ + __IO uint32_t RSV1[2]; /*!< RESERVED REGISTER, Address offset: 0x08 */ + __IO uint32_t SR; /*!< Random Number Generator Status Register, Address offset: 0x10 */ + __IO uint32_t CRCCR; /*!< CRC Control Register, Address offset: 0x14 */ + __IO uint32_t CRCDIR; /*!< CRC Data input Register, Address offset: 0x18 */ + __IO uint32_t CRCSR; /*!< CRC Status Register, Address offset: 0x1C */ +}RNG_Type; + + +/* ================================================================================ */ +/* ================ OPA ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< OPA1 Control Register, Address offset: 0x00 */ + __IO uint32_t CALR; /*!< OPA1 Calibration Register, Address offset: 0x04 */ + __I uint32_t COR; /*!< OPA1 Calibration Output Register, Address offset: 0x08 */ +}OPA_Type; + + +/* ================================================================================ */ +/* ================ COMP ================ */ +/* ================================================================================ */ +typedef struct +{ + __IO uint32_t CR; /*!< ComparatorControl Register 1, Address offset: 0x00 */ + +} COMP_Type; + +typedef struct +{ + __IO uint32_t ICR; /*!< Comparator Interrupt Config Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< Comparator Interrupt Status Register, Address offset: 0x10 */ + __IO uint32_t BUFCR; /*!< Comparator Buffer Control Register, Address offset: 0x14 */ +}COMP_COMMON_Type; + + +/* ================================================================================ */ +/* ================ CALC ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t OPRD; /*!< Operand Register, Address offset: 0x00 */ + __IO uint32_t DIVSOR; /*!< Divisor Regsiter, Address offset: 0x04 */ + __I uint32_t QUOT; /*!< Quotient Register, Address offset: 0x08 */ + __I uint32_t REMD; /*!< Reminder Register, Address offset: 0x0C */ + __I uint32_t ROOT; /*!< Root Register, Address offset: 0x10 */ + __I uint32_t SR; /*!< Status Register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x18 */ +}DIVAS_Type; + + +/* ================================================================================ */ +/* ================ I2C ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t MSPCFGR; /*!< I2C Master Config Register, Address offset: 0x00 */ + __IO uint32_t MSPCR; /*!< I2C Master Control Register, Address offset: 0x04 */ + __IO uint32_t MSPIER; /*!< I2C Master Intterupt Enable Register, Address offset: 0x08 */ + __IO uint32_t MSPISR; /*!< I2C Master Interrupt Status Register, Address offset: 0x0C */ + __IO uint32_t MSPSR; /*!< I2C Master Status Register, Address offset: 0x10 */ + __IO uint32_t MSPBGR; /*!< I2C Master Baud rate Generator Register, Address offset: 0x14 */ + __IO uint32_t MSPBUF; /*!< I2C Master transfer Buffer, Address offset: 0x18 */ + __IO uint32_t MSPTCR; /*!< I2C Master Timing Control Register, Address offset: 0x1C */ + __IO uint32_t MSPTOR; /*!< I2C Master Time-Out Register, Address offset: 0x20 */ + __IO uint32_t SSPCR; /*!< I2C Slave Control Register, Address offset: 0x24 */ + __IO uint32_t SSPIER; /*!< I2C Slave Interrupt Enable Register, Address offset: 0x28 */ + __IO uint32_t SSPISR; /*!< I2C Slave Interrupt Status Register, Address offset: 0x2C */ + __I uint32_t SSPSR; /*!< I2C Slave Status Register, Address offset: 0x30 */ + __IO uint32_t SSPBUF; /*!< I2C Slave transfer Buffer, Address offset: 0x34 */ + __IO uint32_t SSPADR; /*!< I2C Slave Address Register, Address offset: 0x38 */ +}I2C_Type; + + +/* ================================================================================ */ +/* ================ UART_COMMON ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t IRCR; /*!< Infrared modulation Control Register, Address offset: 0x00 */ +}UART_COMMON_Type; + + +/* ================================================================================ */ +/* ================ UARTx ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CSR; /*!< UARTx Control Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< UARTx Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< UARTx Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t TODR; /*!< UARTx Time-Out and Delay Register, Address offset: 0x0C */ + __I uint32_t RXBUF; /*!< UARTx Receive Buffer, Address offset: 0x10 */ + __O uint32_t TXBUF; /*!< UARTx Transmit Buffer, Address offset: 0x14 */ + __IO uint32_t BGR; /*!< UARTx Baud rate Generator Register, Address offset: 0x18 */ +}UART_Type; + + +/* ================================================================================ */ +/* ================ LPUARTx ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CSR; /*!< LPUARTx Control Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< LPUARTx Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< LPUARTx Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t BMR; /*!< LPUARTx Baud rate Modulation Register, Address offset: 0x0C */ + __I uint32_t RXBUF; /*!< LPUARTx Receive Buffer Register, Address offset: 0x10 */ + __IO uint32_t TXBUF; /*!< LPUARTx Transmit Buffer Register, Address offset: 0x14 */ + __IO uint32_t DMR; /*!< LPUARTx data Matching Register, Address offset: 0x18 */ +}LPUART_Type; + + +/* ================================================================================ */ +/* ================ SPIx ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPIxControl Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPIxControl Register2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Control Register3, Address offset: 0x08 */ + __IO uint32_t IER; /*!< SPIxInterrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< SPIxStatus Register, Address offset: 0x10 */ + __O uint32_t TXBUF; /*!< SPIxTransmit Buffer, Address offset: 0x14 */ + __I uint32_t RXBUF; /*!< SPIxReceive Buffer, Address offset: 0x18 */ +}SPI_Type; + + +/* ================================================================================ */ +/* ================ U7816 ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< 7816 Control Register, Address offset: 0x00 */ + __IO uint32_t FFR; /*!< 7816 Frame Format Control Register, Address offset: 0x04 */ + __IO uint32_t EGTR; /*!< 7816 Extra Guard Time Register, Address offset: 0x08 */ + __IO uint32_t PSC; /*!< 7816 Clock Output Divider Register, Address offset: 0x0C */ + __IO uint32_t BGR; /*!< 7816 Prescaler Register, Address offset: 0x10 */ + __IO uint32_t RXBUF; /*!< 7816 data RX Buffer, Address offset: 0x14 */ + __IO uint32_t TXBUF; /*!< 7816 data TX Buffer, Address offset: 0x18 */ + __IO uint32_t IER; /*!< 7816 Interrupt Enable Register, Address offset: 0x1C */ + __IO uint32_t ISR; /*!< 7816 Interrupt Status Register, Address offset: 0x20 */ +}U7816_Type; + + +/* ================================================================================ */ +/* ================ CAN ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< CAN Control Register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN mode select register, Address offset: 0x04 */ + __IO uint32_t BRPR; /*!< CAN Baud rate Prescaler Register, Address offset: 0x08 */ + __IO uint32_t BTR; /*!< CAN Bit Timing Register, Address offset: 0x0C */ + __I uint32_t ECR; /*!< CAN Error Counter Register, Address offset: 0x10 */ + __IO uint32_t ESR; /*!< CAN Error Status Register, Address offset: 0x14 */ + __I uint32_t SR; /*!< CAN Status Register, Address offset: 0x18 */ + __I uint32_t ISR; /*!< CAN Interrupt Status Register, Address offset: 0x1C */ + __IO uint32_t IER; /*!< CAN Interrupt Enable Register, Address offset: 0x20 */ + __IO uint32_t ICR; /*!< CAN Interrupt Clear Register, Address offset: 0x24 */ + __IO uint32_t RSV1[2]; /*!< RESERVED REGISTER, Address offset: 0x28 */ + __O uint32_t TXFIDR; /*!< CAN TX FIFO ID Register, Address offset: 0x30 */ + __O uint32_t TXFDLCR; /*!< CAN TX FIFO DLC Register, Address offset: 0x34 */ + __O uint32_t TXFDW1R; /*!< CAN TX FIFO Data Word1 Register, Address offset: 0x38 */ + __O uint32_t TXFDW2R; /*!< CAN TX FIFO Data Word2 Register, Address offset: 0x3C */ + __O uint32_t HPBIDR; /*!< CAN TX HPB ID Register, Address offset: 0x40 */ + __O uint32_t HPBDLCR; /*!< CAN TX HPB DLC Register, Address offset: 0x44 */ + __O uint32_t HPBDW1R; /*!< CAN TX HPB Data Word1 Register, Address offset: 0x48 */ + __O uint32_t HPBDW2R; /*!< CAN TX HPB Data Word2 Register, Address offset: 0x4C */ + __O uint32_t RXFIDR; /*!< CAN RX FIFO ID Register, Address offset: 0x50 */ + __O uint32_t RXFDLCR; /*!< CAN RX FIFO DLC Register, Address offset: 0x54 */ + __O uint32_t RXFDW1R; /*!< CAN RX FIFO Data Word1 Register, Address offset: 0x58 */ + __O uint32_t RXFDW2R; /*!< CAN RX FIFO Data Word2 Register, Address offset: 0x5C */ + __IO uint32_t AFR; /*!< Acceptance Filter Register, Address offset: 0x60 */ + __IO uint32_t AFMR0; /*!< Acceptance Filter Mask Register0, Address offset: 0x64 */ + __IO uint32_t AFIR0; /*!< Acceptance Filter ID Register0, Address offset: 0x68 */ + __IO uint32_t AFMR1; /*!< Acceptance Filter Mask Register1, Address offset: 0x6C */ + __IO uint32_t AFIR1; /*!< Acceptance Filter ID Register1, Address offset: 0x70 */ + __IO uint32_t AFMR2; /*!< Acceptance Filter Mask Register2, Address offset: 0x74 */ + __IO uint32_t AFIR2; /*!< Acceptance Filter ID Register2, Address offset: 0x78 */ + __IO uint32_t AFMR3; /*!< Acceptance Filter Mask Register3, Address offset: 0x7C */ + __IO uint32_t AFIR3; /*!< Acceptance Filter ID Register3, Address offset: 0x80 */ +}CAN_Type; + + +/* ================================================================================ */ +/* ================ DMA ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t GCR; /*!< DMA Global Control Register, Address offset: 0x00 */ + __IO uint32_t CH0CR; /*!< Channel 0 Control Register, Address offset: 0x04 */ + __IO uint32_t CH0MAR; /*!< Channel 0 Memory Address Register, Address offset: 0x08 */ + __IO uint32_t CH1CR; /*!< Channel 1 Control Register, Address offset: 0x0C */ + __IO uint32_t CH1MAR; /*!< Channel 1 Memory Address Register, Address offset: 0x10 */ + __IO uint32_t CH2CR; /*!< Channel 2 Control Register, Address offset: 0x14 */ + __IO uint32_t CH2MAR; /*!< Channel 2 Memory Address Register, Address offset: 0x18 */ + __IO uint32_t CH3CR; /*!< Channel 3 Control Register, Address offset: 0x1C */ + __IO uint32_t CH3MAR; /*!< Channel 3 Memory Address Register, Address offset: 0x20 */ + __IO uint32_t CH4CR; /*!< Channel 4 Control Register, Address offset: 0x24 */ + __IO uint32_t CH4MAR; /*!< Channel 4 Memory Address Register, Address offset: 0x28 */ + __IO uint32_t CH5CR; /*!< Channel 5 Control Register, Address offset: 0x2C */ + __IO uint32_t CH5MAR; /*!< Channel 5 Memory Address Register, Address offset: 0x30 */ + __IO uint32_t CH6CR; /*!< Channel 6 Control Register, Address offset: 0x34 */ + __IO uint32_t CH6MAR; /*!< Channel 6 Memory Address Register, Address offset: 0x38 */ + __IO uint32_t CH7CR; /*!< Channel 11 Control Register, Address offset: 0x3C */ + __IO uint32_t CH7FLSAD; /*!< Channel 11 Flash Address Register, Address offset: 0x40 */ + __IO uint32_t CH7RAMAD; /*!< Channel 11 RAM Address Register, Address offset: 0x44 */ + __IO uint32_t ISR; /*!< DMA Interrupt Status Register, Address offset: 0x48 */ +}DMA_Type; + + +/* ================================================================================ */ +/* ================ CRC ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x04 */ + __IO uint32_t LFSR; /*!< CRC Linear Feedback Shift Register, Address offset: 0x08 */ + __IO uint32_t XOR; /*!< CRC output XOR Register, Address offset: 0x0C */ + __IO uint32_t RSV1[3]; /*!< RESERVED REGISTER, Address offset: 0x10 */ + __IO uint32_t POLY; /*!< CRC Polynominal Register, Address offset: 0x1C */ +}CRC_Type; + + +/* ================================================================================ */ +/* ================ ATIM ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR1; /*!< ATIM Control Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< ATIM Control Register2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< ATIM Slave Mode Control Register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< ATIM DMA and Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< ATIM Interrupt Status Register, Address offset: 0x10 */ + __O uint32_t EGR; /*!< ATIM Event Generation Register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< ATIM Capture/Compare Mode Register1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< ATIM Capture/Compare Mode Register2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< ATIM Capture/Compare Enable Register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< ATIM Counter Register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< ATIM Prescaler Register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< ATIM Auto-Reload Register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< ATIM Repetition Counter Register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< ATIM Capture/Compare Register1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< ATIM Capture/Compare Register2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< ATIM Capture/Compare Register3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< ATIM Capture/Compare Register4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< ATIM Break and Deadtime Register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< ATIM DMA Control Register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< ATIM DMA Access Register, Address offset: 0x4C */ + __IO uint32_t RSV1[4]; /*!< RESERVED REGISTER, Address offset: 0x50 */ + __IO uint32_t BKCR; /*!< ATIM Break Control Register, Address offset: 0x60 */ +}ATIM_Type; + + +/* ================================================================================ */ +/* ================ GPTIMx ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR1; /*!< GPTIMx Control Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< GPTIMx Control Register2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< GPTIMx Slave Mode Control Register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< GPTIMx DMA and Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x10 */ + __O uint32_t EGR; /*!< GPTIMx Event Generation Register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< GPTIMx Capture/Compare Mode Register1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< GPTIMx Capture/Compare Mode Register2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< GPTIMx Capture/Compare Enable Register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< GPTIMx Counter Register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< GPTIMx Prescaler Register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< GPTIMx Auto-Reload Register, Address offset: 0x2C */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< GPTIMx Capture/Compare Register1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< GPTIMx Capture/Compare Register2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< GPTIMx Capture/Compare Register3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< GPTIMx Capture/Compare Register4, Address offset: 0x40 */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< GPTIMx DMA Control Register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< GPTIMx DMA access Register, Address offset: 0x4C */ + __IO uint32_t RSV3[4]; /*!< RESERVED REGISTER, Address offset: 0x50 */ + __IO uint32_t ITRSEL; /*!< GPTIMx Internal Trigger Select Register, Address offset: 0x60 */ +}GPTIM_Type; + + +/* ================================================================================ */ +/* ================ BSTIM32 ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR1; /*!< BSTIM Control Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< BSTIM Control Register2, Address offset: 0x04 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x08 */ + __IO uint32_t IER; /*!< BSTIM Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< BSTIM Interrupt Status Register, Address offset: 0x10 */ + __O uint32_t EGR; /*!< BSTIM Event Generation Register, Address offset: 0x14 */ + __IO uint32_t RSV2[3]; /*!< RESERVED REGISTER, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< BSTIM Counter Register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< BSTIM Prescaler Register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< BSTIM Auto-Reload Register, Address offset: 0x2C */ +}BSTIM32_Type; + + +/* ================================================================================ */ +/* ================ BSTIM16 ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR1; /*!< BSTIM Control Register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< BSTIM Control Register2, Address offset: 0x04 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x08 */ + __IO uint32_t IER; /*!< BSTIM Interrupt Enable Register, Address offset: 0x0C */ + __IO uint32_t ISR; /*!< BSTIM Interrupt Status Register, Address offset: 0x10 */ + __O uint32_t EGR; /*!< BSTIM Event Generation Register, Address offset: 0x14 */ + __IO uint32_t RSV2[3]; /*!< RESERVED REGISTER, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< BSTIM Counter Register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< BSTIM Prescaler Register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< BSTIM Auto-Reload Register, Address offset: 0x2C */ +}BSTIM16_Type; + + +/* ================================================================================ */ +/* ================ LPTIM32 ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CFGR; /*!< LPTIM32 Config Register, Address offset: 0x00 */ + __I uint32_t CNT; /*!< LPTIM32 Counter Register, Address offset: 0x04 */ + __IO uint32_t CCSR; /*!< LPTIM32 Capture/Compare Control and Status Register, Address offset: 0x08 */ + __IO uint32_t ARR; /*!< LPTIM32 Auto-Reload Register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< LPTIM32 Interrupt Enable Register, Address offset: 0x10 */ + __IO uint32_t ISR; /*!< LPTIM32 Interrupt Status Register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< LPTIM32 Control Register, Address offset: 0x18 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x1C */ + __IO uint32_t CCR1; /*!< LPTIM32 Capture/Compare Register1, Address offset: 0x20 */ + __IO uint32_t CCR2; /*!< LPTIM32 Capture/Compare Register2, Address offset: 0x24 */ + __IO uint32_t CCR3; /*!< LPTIM32 Capture/Compare Register3, Address offset: 0x28 */ + __IO uint32_t CCR4; /*!< LPTIM32 Capture/Compare Register4, Address offset: 0x2C */ +}LPTIM32_Type; + + +/* ================================================================================ */ +/* ================ LPTIM16 ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CFGR; /*!< LPTIM Config Register, Address offset: 0x00 */ + __I uint32_t CNT; /*!< LPTIM Counter Register, Address offset: 0x04 */ + __IO uint32_t CCSR; /*!< LPTIM Capture/Compare Control and Status Register, Address offset: 0x08 */ + __IO uint32_t ARR; /*!< LPTIM Auto-Reload Register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable Register, Address offset: 0x10 */ + __IO uint32_t ISR; /*!< LPTIM Interrupt Status Register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< LPTIM Control Register, Address offset: 0x18 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x1C */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare Register1, Address offset: 0x20 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare Register2, Address offset: 0x24 */ +}LPTIM16_Type; + + +/* ================================================================================ */ +/* ================ RTCA ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t WER; /*!< RTC Write Enable Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< RTC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< RTC Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t BCDSEC; /*!< BCD format time second registers, Address offset: 0x0C */ + __IO uint32_t BCDMIN; /*!< BCD format time minute registers, Address offset: 0x10 */ + __IO uint32_t BCDHOUR; /*!< BCD format time hour registers, Address offset: 0x14 */ + __IO uint32_t BCDDAY; /*!< BCD format time day registers, Address offset: 0x18 */ + __IO uint32_t BCDWEEK; /*!< BCD format time week registers, Address offset: 0x1C */ + __IO uint32_t BCDMONTH; /*!< BCD format time month registers, Address offset: 0x20 */ + __IO uint32_t BCDYEAR; /*!< BCD format time year registers, Address offset: 0x24 */ + __IO uint32_t ALARM; /*!< RTCA Alarm Register, Address offset: 0x28 */ + __IO uint32_t TMSEL; /*!< RTCA Time Mark Select, Address offset: 0x2C */ + __IO uint32_t ADJUST; /*!< RTCA time Adjust Register, Address offset: 0x30 */ + __IO uint32_t ADSIGN; /*!< RTCA time Adjust Sign Register, Address offset: 0x34 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x38 */ + __IO uint32_t SBSCNT; /*!< RTCA Sub-Second Counter, Address offset: 0x3C */ + __IO uint32_t CR; /*!< RTCA Control Register, Address offset: 0x40 */ +}RTCA_Type; + + +/* ================================================================================ */ +/* ================ RTCB ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t WER; /*!< RTCBWrite Enable Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< RTCBInterrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< RTCBInterrupt Status Register, Address offset: 0x08 */ + __IO uint32_t BCDSEC; /*!< BCD format time second registers, Address offset: 0x0C */ + __IO uint32_t BCDMIN; /*!< BCD format time minute registers, Address offset: 0x10 */ + __IO uint32_t BCDHOUR; /*!< BCD format time hour registers, Address offset: 0x14 */ + __IO uint32_t BCDDAY; /*!< BCD format time day registers, Address offset: 0x18 */ + __IO uint32_t BCDWEEK; /*!< BCD format time week registers, Address offset: 0x1C */ + __IO uint32_t BCDMONTH; /*!< BCD format time month registers, Address offset: 0x20 */ + __IO uint32_t BCDYEAR; /*!< BCD format time year registers, Address offset: 0x24 */ + __IO uint32_t ALARM; /*!< Alarm Register, Address offset: 0x28 */ + __IO uint32_t TMSEL; /*!< RTCB Time Mark Select, Address offset: 0x2C */ + __IO uint32_t ADJR; /*!< RTCB time Adjust Register, Address offset: 0x30 */ + __IO uint32_t RSV1[3]; /*!< RESERVED REGISTER, Address offset: 0x34 */ + __IO uint32_t CR; /*!< RTCB Control Register, Address offset: 0x40 */ + __IO uint32_t RSV2; /*!< RESERVED REGISTER, Address offset: 0x44 */ + __IO uint32_t STPCR; /*!< RTCB Time Stamp Control Register, Address offset: 0x48 */ + __IO uint32_t STPCLKRR; /*!< RTC Time Stamp Clock Record Register, Address offset: 0x4C */ + __IO uint32_t STPCALRR; /*!< RTCB Time Stamp Calendar Record Register, Address offset: 0x50 */ + __IO uint32_t RSV3[7]; /*!< RESERVED REGISTER, Address offset: 0x54 */ + __IO uint32_t BKR0; /*!< RTCBBackup Register0, Address offset: 0x70 */ + __IO uint32_t BKR1; /*!< RTCB Backup Register1, Address offset: 0x74 */ + __IO uint32_t BKR2; /*!< RTCB Backup Register2, Address offset: 0x78 */ + __IO uint32_t BKR3; /*!< RTCB Backup Register3, Address offset: 0x7C */ + __IO uint32_t BKR4; /*!< RTCB Backup Register4, Address offset: 0x80 */ +}RTCB_Type; + + +/* ================================================================================ */ +/* ================ LCD ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD Control Register, Address offset: 0x00 */ + __IO uint32_t TEST; /*!< LCD test Register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< LCD Frequency Control Register, Address offset: 0x08 */ + __IO uint32_t FLKT; /*!< LCD Flick Time Register, Address offset: 0x0C */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x10 */ + __IO uint32_t IER; /*!< LCD Interrupt Enable Register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< LCD Interrupt Status Register, Address offset: 0x18 */ + __IO uint32_t RSV2[2]; /*!< RESERVED REGISTER, Address offset: 0x1C */ + __IO uint32_t DATA0; /*!< LCD data buffer registers 0, Address offset: 0x24 */ + __IO uint32_t DATA1; /*!< LCD data buffer registers 1, Address offset: 0x28 */ + __IO uint32_t DATA2; /*!< LCD data buffer registers 2, Address offset: 0x2C */ + __IO uint32_t DATA3; /*!< LCD data buffer registers 3, Address offset: 0x30 */ + __IO uint32_t DATA4; /*!< LCD data buffer registers 4, Address offset: 0x34 */ + __IO uint32_t DATA5; /*!< LCD data buffer registers 5, Address offset: 0x38 */ + __IO uint32_t DATA6; /*!< LCD data buffer registers 6, Address offset: 0x3C */ + __IO uint32_t DATA7; /*!< LCD data buffer registers 7, Address offset: 0x40 */ + __IO uint32_t DATA8; /*!< LCD data buffer registers 8, Address offset: 0x44 */ + __IO uint32_t DATA9; /*!< LCD data buffer registers 9, Address offset: 0x48 */ + __IO uint32_t RSV3; /*!< RESERVED REGISTER, Address offset: 0x4C */ + __IO uint32_t COMEN; /*!< LCD COM Enable Register, Address offset: 0x50 */ + __IO uint32_t SEGEN0; /*!< LCD SEG Enable Register0, Address offset: 0x54 */ + __IO uint32_t SEGEN1; /*!< LCD SEG Enable Register 1, Address offset: 0x58 */ +}LCD_Type; + + +/* ================================================================================ */ +/* ================ ADC ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR1; /*!< ADC Control Register, Address offset: 0x08 */ + __IO uint32_t CR2; /*!< ADC Control Register, Address offset: 0x0C */ + __IO uint32_t CALR; /*!< ADC Calibration Register, Address offset: 0x10 */ + __IO uint32_t CFGR1; /*!< ADC Config Register1, Address offset: 0x14 */ + __IO uint32_t CFGR2; /*!< ADC Config Register2, Address offset: 0x18 */ + __IO uint32_t SMTR; /*!< ADC Sampling Time Register, Address offset: 0x1C */ + __IO uint32_t CHER; /*!< ADC Channel Enable Register, Address offset: 0x20 */ + __IO uint32_t DCR; /*!< ADC Differential Channel Control Register, Address offset: 0x24 */ + __I uint32_t DR; /*!< ADC Data Register, Address offset: 0x28 */ + __IO uint32_t HLTR; /*!< ADC analog watchdog Threshold Register, Address offset: 0x2C */ +}ADC_Type; + + +/* ================================================================================ */ +/* ================ DAC ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR1; /*!< DAC Control Register, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< DAC Control Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< DAC Config Register, Address offset: 0x08 */ + __O uint32_t SWTRGR; /*!< DAC Software Trigger Register, Address offset: 0x0C */ + __IO uint32_t DHR; /*!< DAC Data Holding Register, Address offset: 0x10 */ + __IO uint32_t ISR; /*!< DAC Interrupt Status Register, Address offset: 0x14 */ + __IO uint32_t IER; /*!< DAC Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t SHTR; /*!< DAC Sample Hold Time Register, Address offset: 0x1C */ +}DAC_Type; + + +/* ================================================================================ */ +/* ================ PGL ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t CR; /*!< PGL Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR0; /*!< PGL Config Register0, Address offset: 0x04 */ + __IO uint32_t CFGR1; /*!< PGL Config Register1, Address offset: 0x08 */ + __IO uint32_t CFGR2; /*!< PGL Config Register2, Address offset: 0x0C */ + __IO uint32_t CFGR3; /*!< PGL Config Register3, Address offset: 0x10 */ + __IO uint32_t IER; /*!< PGL Interrupt Enable Register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< PGL Interrupt Status Register, Address offset: 0x18 */ + __IO uint32_t LUT0; /*!< Look Up Table0, Address offset: 0x1C */ + __IO uint32_t LUT1; /*!< Look Up Table1, Address offset: 0x20 */ + __IO uint32_t LUT2; /*!< Look Up Table2, Address offset: 0x24 */ + __IO uint32_t LUT3; /*!< Look Up Table3, Address offset: 0x28 */ +}PGL_Type; + + +/* ================================================================================ */ +/* ================ GPIO ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t INEN; /*!< GPIOx Input Enable Register, Address offset: 0x00 */ + __IO uint32_t PUEN; /*!< GPIOx Pull-Up Enable Register, Address offset: 0x04 */ + __IO uint32_t ODEN; /*!< GPIOx Open-Drain Enable Register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< GPIOx Function Control Register, Address offset: 0x0C */ + __IO uint32_t DO; /*!< GPIOx Data Output Register, Address offset: 0x10 */ + __O uint32_t DSET; /*!< GPIOx Data Set Register, Address offset: 0x14 */ + __O uint32_t DRST; /*!< GPIOx Data Reset Register, Address offset: 0x18 */ + __I uint32_t DIN; /*!< GPIOx Data Input Register, Address offset: 0x1C */ + __IO uint32_t DFS; /*!< GPIOx Digital Function Select, Address offset: 0x20 */ + __IO uint32_t RSV1; /*!< RESERVED REGISTER, Address offset: 0x24 */ + __IO uint32_t ANEN; /*!< GPIOx Analog channel Enable Register, Address offset: 0x28 */ + __IO uint32_t VILR; /*!< GPIOx Voltage Input Low Register, Address offset: 0x2C */ +}GPIO_Type; + + +/* ================================================================================ */ +/* ================ GPIO_COMMON ================ */ +/* ================================================================================ */ + +typedef struct +{ + __IO uint32_t EXTISEL0; /*!< External Interrupt Input Select Register0, Address offset: 0x00 */ + __IO uint32_t EXTISEL1; /*!< External Interrupt Input Select Register1, Address offset: 0x04 */ + __IO uint32_t EXTIEDS0; /*!< External Interrupt Edge Select and Enable Register0, Address offset: 0x08 */ + __IO uint32_t EXTIEDS1; /*!< External Interrupt Edge Select and Enable Register1, Address offset: 0x0C */ + __IO uint32_t EXTIDF; /*!< External Interrupt Digital Filter Register, Address offset: 0x10 */ + __IO uint32_t EXTIISR; /*!< External Interrupt and Status Register, Address offset: 0x14 */ + __I uint32_t EXTIDI; /*!< External Interrupt Data Input Register, Address offset: 0x18 */ + __IO uint32_t RSV1[9]; /*!< RESERVED REGISTER, Address offset: 0x1C */ + __IO uint32_t FOUTSEL; /*!< Frequency Output Select Register, Address offset: 0x100 */ + __IO uint32_t RSV2[63]; /*!< RESERVED REGISTER, Address offset: 0x104 */ + __IO uint32_t PINWKEN; /*!< Wakeup Enable Register, Address offset: 0x200 */ +}GPIO_COMMON_Type; + + +/* ================================================================================ */ +/* ================ DBG ================ */ +/* ================================================================================ */ + +typedef struct +{ + __I uint32_t SYSCFG; /*!< , Address offset: 0x00 */ + __IO uint32_t CR; /*!< , Address offset: 0x04 */ + __IO uint32_t HDFR; /*!< , Address offset: 0x08 */ +}DBG_Type; + + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + +/* ================================================================================ */ +/* ================ CPU memory map ================ */ +/* ================================================================================ */ + + +/* Peripheral and SRAM base address */ + +#define FLASH_BASE (( uint32_t)0x00000000) +#define SRAM_BASE (( uint32_t)0x20000000) +#define PERIPH_BASE (( uint32_t)0x40000000) + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +/* Peripheral memory map */ + +#define FLASH_R_BASE (PERIPH_BASE +0x00001000) +#define PMU_BASE (PERIPH_BASE +0x00002000) +#define VREFP_BASE (PERIPH_BASE +0x0000203C) +#define VREF_BASE (PERIPH_BASE +0x0001A400) +#define VAO_BASE (PERIPH_BASE +0x0001F000) +#define CDIF_BASE (PERIPH_BASE +0x0001E000) +#define RMU_BASE (PERIPH_BASE +0x00002800) +#define IWDT_BASE (PERIPH_BASE +0x00011400) +#define WWDT_BASE (PERIPH_BASE +0x00011800) +#define CMU_BASE (PERIPH_BASE +0x00002400) +#define SVD_BASE (PERIPH_BASE +0x00012800) +#define AES_BASE (PERIPH_BASE +0x00013800) +#define RNG_BASE (PERIPH_BASE +0x00013C00) +#define OPA_BASE (PERIPH_BASE +0x0001A000) +#define COMP1_BASE (PERIPH_BASE +0x00015400) +#define COMP2_BASE (PERIPH_BASE +0x00015404) +#define COMP3_BASE (PERIPH_BASE +0x00015408) +#define COMP_COMMON_BASE (PERIPH_BASE +0x0001540C) +#define DIVAS_BASE (PERIPH_BASE +0x00019C00) +#define I2C_BASE (PERIPH_BASE +0x00012400) +#define UART_COMMON_BASE (PERIPH_BASE +0x00017C00) +#define UART0_BASE (PERIPH_BASE +0x00012000) +#define UART1_BASE (PERIPH_BASE +0x00016800) +#define UART3_BASE (PERIPH_BASE +0x00017000) +#define UART4_BASE (PERIPH_BASE +0x00017400) +#define UART5_BASE (PERIPH_BASE +0x00017800) +#define LPUART0_BASE (PERIPH_BASE +0x00014000) +#define LPUART1_BASE (PERIPH_BASE +0x00014400) +#define LPUART2_BASE (PERIPH_BASE +0x00015000) +#define SPI0_BASE (PERIPH_BASE +0x00010400) +#define SPI1_BASE (PERIPH_BASE +0x00010800) +#define SPI2_BASE (PERIPH_BASE +0x00014800) +#define U7816_BASE (PERIPH_BASE +0x00011C00) +#define CAN_BASE (PERIPH_BASE +0x00019400) +#define DMA_BASE (PERIPH_BASE +0x00000400) +#define CRC_BASE (PERIPH_BASE +0x00010000) +#define ATIM_BASE (PERIPH_BASE +0x00013000) +#define GPTIM0_BASE (PERIPH_BASE +0x00014C00) +#define GPTIM1_BASE (PERIPH_BASE +0x00016400) +#define GPTIM2_BASE (PERIPH_BASE +0x00018000) +#define BSTIM32_BASE (PERIPH_BASE +0x00016000) +#define BSTIM16_BASE (PERIPH_BASE +0x00018C00) +#define LPTIM32_BASE (PERIPH_BASE +0x00013400) +#define LPTIM16_BASE (PERIPH_BASE +0x00018800) +#define RTCA_BASE (PERIPH_BASE +0x00011000) +#define RTCB_BASE (PERIPH_BASE +0x0001F000) +#define LCD_BASE (PERIPH_BASE +0x00010C00) +#define ADC_BASE (PERIPH_BASE +0x00015C00) +#define DAC_BASE (PERIPH_BASE +0x00019800) +#define PGL_BASE (PERIPH_BASE +0x00016C00) +#define GPIOA_BASE (PERIPH_BASE +0x00000C00) +#define GPIOB_BASE (PERIPH_BASE +0x00000C40) +#define GPIOC_BASE (PERIPH_BASE +0x00000C80) +#define GPIOD_BASE (PERIPH_BASE +0x00000CC0) +#define GPIOE_BASE (PERIPH_BASE +0x00000D00) +#define GPIO_COMMON_BASE (PERIPH_BASE +0x00000DC0) +#define DBG_BASE (PERIPH_BASE +0x00000000) + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define FLASH ((FLASH_Type *) FLASH_R_BASE ) +#define PMU ((PMU_Type *) PMU_BASE ) +#define VREFP ((VREFP_Type *) VREFP_BASE ) +#define VREF ((VREF_Type *) VREF_BASE ) +#define VAO ((VAO_Type *) VAO_BASE ) +#define CDIF ((CDIF_Type *) CDIF_BASE ) +#define RMU ((RMU_Type *) RMU_BASE ) +#define IWDT ((IWDT_Type *) IWDT_BASE ) +#define WWDT ((WWDT_Type *) WWDT_BASE ) +#define CMU ((CMU_Type *) CMU_BASE ) +#define SVD ((SVD_Type *) SVD_BASE ) +#define AES ((AES_Type *) AES_BASE ) +#define RNG ((RNG_Type *) RNG_BASE ) +#define OPA ((OPA_Type *) OPA_BASE ) +#define COMP1 ((COMP_Type *) COMP1_BASE ) +#define COMP2 ((COMP_Type *) COMP2_BASE ) +#define COMP3 ((COMP_Type *) COMP3_BASE ) +#define COMP_COMMON ((COMP_COMMON_Type *)COMP_COMMON_BASE ) +#define DIVAS ((DIVAS_Type *) DIVAS_BASE ) +#define I2C ((I2C_Type *) I2C_BASE ) +#define UART_COMMON ((UART_COMMON_Type *) UART_COMMON_BASE ) +#define UART0 ((UART_Type *) UART0_BASE ) +#define UART1 ((UART_Type *) UART1_BASE ) +#define UART3 ((UART_Type *) UART3_BASE ) +#define UART4 ((UART_Type *) UART4_BASE ) +#define UART5 ((UART_Type *) UART5_BASE ) +#define LPUART0 ((LPUART_Type *) LPUART0_BASE ) +#define LPUART1 ((LPUART_Type *) LPUART1_BASE ) +#define LPUART2 ((LPUART_Type *) LPUART2_BASE ) +#define SPI0 ((SPI_Type *) SPI0_BASE ) +#define SPI1 ((SPI_Type *) SPI1_BASE ) +#define SPI2 ((SPI_Type *) SPI2_BASE ) +#define U7816 ((U7816_Type *) U7816_BASE ) +#define CAN ((CAN_Type *) CAN_BASE ) +#define DMA ((DMA_Type *) DMA_BASE ) +#define CRC ((CRC_Type *) CRC_BASE ) +#define ATIM ((ATIM_Type *) ATIM_BASE ) +#define GPTIM0 ((GPTIM_Type *) GPTIM0_BASE ) +#define GPTIM1 ((GPTIM_Type *) GPTIM1_BASE ) +#define GPTIM2 ((GPTIM_Type *) GPTIM2_BASE ) +#define BSTIM32 ((BSTIM32_Type *) BSTIM32_BASE ) +#define BSTIM16 ((BSTIM16_Type *) BSTIM16_BASE ) +#define LPTIM32 ((LPTIM32_Type *) LPTIM32_BASE ) +#define LPTIM16 ((LPTIM16_Type *) LPTIM16_BASE ) +#define RTCA ((RTCA_Type *) RTCA_BASE ) +#define RTCB ((RTCB_Type *) RTCB_BASE ) +#define LCD ((LCD_Type *) LCD_BASE ) +#define ADC ((ADC_Type *) ADC_BASE ) +#define DAC ((DAC_Type *) DAC_BASE ) +#define PGL ((PGL_Type *) PGL_BASE ) +#define GPIOA ((GPIO_Type *) GPIOA_BASE ) +#define GPIOB ((GPIO_Type *) GPIOB_BASE ) +#define GPIOC ((GPIO_Type *) GPIOC_BASE ) +#define GPIOD ((GPIO_Type *) GPIOD_BASE ) +#define GPIOE ((GPIO_Type *) GPIOE_BASE ) +#define GPIO ((GPIO_COMMON_Type *) GPIO_COMMON_BASE ) +#define DBG ((DBG_Type *) DBG_BASE ) + +/* ================================================================================ */ +/* ================ Peripheral include ================ */ +/* ================================================================================ */ + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group FM33LG0XX */ +/** @} */ /* End of group Keil */ + +#ifdef __cplusplus +} +#endif + +#endif /* FM33LG0XX_H */ + diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33xx.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33xx.h new file mode 100644 index 0000000000..cb9458888e --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/fm33xx.h @@ -0,0 +1,110 @@ +/** + **************************************************************************************************** + * @file fm33xx.h + * @author FMSH Application Team + * @brief Header file of FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +#ifndef __FM33xx_H +#define __FM33xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + + +/** + * @brief FM33 Family + */ +#if !defined (FM33xx) +#define FM33xx +#endif /* FM33XX */ +/** + * @brief CMSIS Device version number + */ +#define __FM33x0xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __FM33x0xx_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __FM33x0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __FM33x0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __FM33x0xx_CMSIS_VERSION ((__FM33x0xx_CMSIS_VERSION_MAIN << 24)\ + |(__FM33x0xx_CMSIS_VERSION_SUB1 << 16)\ + |(__FM33x0xx_CMSIS_VERSION_SUB2 << 8 )\ + |(__FM33x0xx_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ +#if defined(FM33L0XX) + #include "fm33l0xx.h" +#elif defined(FM33LC0XX) + #include "fm33lc0xx.h" +#elif defined(FM33LG0XX) + #include "fm33lg0xx.h" +#else + #error "Please select first the target FM33x0xx device used in your application (in FM33xxx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_macro + * @{ + */ + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __FM33xx_H */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT Fudan Microelectronics *****END OF FILE****/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/system_fm33lc0xx.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/system_fm33lc0xx.h new file mode 100644 index 0000000000..b947abb8b4 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/system_fm33lc0xx.h @@ -0,0 +1,155 @@ +/**************************************************************************//** + * @file system_fm33lc0xx.h + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for + * Device FM33LC0XX + * @version V2.00 + * @date 15. March 2021 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef SYSTEM_FM33LC0XX_H +#define SYSTEM_FM33LC0XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "fm33lc0xx.h" + +#define USE_LSCLK_CLOCK_SRC_XTLF + +//#define SYSCLK_SRC_RC4M +//#define SYSCLK_SRC_XTHF +#define SYSCLK_SRC_RCHF +//#define SYSCLK_SRC_PLL + + + +//#define USE_PLL_CLOCK_SRC_RCHF +//#define USE_PLL_CLOCK_SRC_XTHF + + +#if ((!defined(SYSCLK_SRC_RC4M)) && (!defined(SYSCLK_SRC_XTHF))&&(!defined(SYSCLK_SRC_PLL))&&(!defined(SYSCLK_SRC_RCHF))) + #error "Must select a clock source form the SYSCLK_SRC_RC4M or SYSCLK_SRC_XTHF or SYSCLK_SRC_PLL or SYSCLK_SRC_RCHF as the master clock." +#elif (((defined(SYSCLK_SRC_RC4M)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RCHF))))||\ + ((defined(SYSCLK_SRC_XTHF)) && ((defined(SYSCLK_SRC_RC4M))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RCHF))))||\ + ((defined(SYSCLK_SRC_PLL)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_RC4M))||(defined(SYSCLK_SRC_RCHF))))||\ + ((defined(SYSCLK_SRC_RCHF)) && ((defined(SYSCLK_SRC_XTHF))||(defined(SYSCLK_SRC_PLL))||(defined(SYSCLK_SRC_RC4M))))) + #error "Only one clock source can be selected as the master clock." +#endif + +#if defined(SYSCLK_SRC_PLL) && !defined(USE_PLL_CLOCK_SRC_RCHF) && !defined(USE_PLL_CLOCK_SRC_XTHF) + #error "You have chosen to enable the PLL, so you need to specify the clock source for the PLL.." +#elif defined(SYSCLK_SRC_PLL) && (defined(USE_PLL_CLOCK_SRC_RCHF) && defined(USE_PLL_CLOCK_SRC_XTHF)) + #error "Please select one of the USE_PLL_CLOCK_SRC_RCHF and USE_PLL_CLOCK_SRC_XTHF in your application" +#endif + +#if !defined (XTHF_VALUE) + #define XTHF_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* XTHF_VALUE */ + +#if !defined (XTLF_VALUE) + #define XTLF_VALUE ((uint32_t)32768U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* XTLF_VALUE */ + + +#define LDT_CHECK(_N_VALUE_, _T_VALUE_) \ + ((((_N_VALUE_ >> 16) & 0xffff) == \ + ((~_N_VALUE_) & 0xffff)) ? _N_VALUE_ : _T_VALUE_) + +#define LPOSC_LDT_TRIM (*(uint32_t *)0x1FFFFB20) // LPOSC 常温校准值 +#define RCHF8M_LDT_TRIM (*(uint32_t *)0x1FFFFB40) // RC8M 常温校准值 +#define RCHF16M_LDT_TRIM (*(uint32_t *)0x1FFFFB3C) // RC16M 常温校准值 +#define RCHF24M_LDT_TRIM (*(uint32_t *)0x1FFFFB38) // RC24M 常温校准值 +#define RCMF4M_LDT_TRIM (*(uint32_t *)0x1FFFFB44) // RCMF 常温校准值 + +#define LPOSC_TRIM (LDT_CHECK(LPOSC_LDT_TRIM, 0x80) & 0xff) +#define RCMF4M_TRIM (LDT_CHECK(RCMF4M_LDT_TRIM, 0x40) & 0x7f) +#define RCHF8M_TRIM (LDT_CHECK(RCHF8M_LDT_TRIM, 0x40) & 0x7f) +#define RCHF16M_TRIM (LDT_CHECK(RCHF16M_LDT_TRIM, 0x40) & 0x7f) +#define RCHF24M_TRIM (LDT_CHECK(RCHF24M_LDT_TRIM, 0x40) & 0x7f) + + +#define __SYSTEM_CLOCK (8000000) + + +/** + * @brief FL NVIC Init Sturcture definition + */ +typedef struct +{ + /* 中断抢占优先级 */ + uint32_t preemptPriority; + +}NVIC_ConfigTypeDef; + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern uint32_t SystemCoreClock; +void SystemCoreClockUpdate (void); +/** + * @brief NVIC_Init config NVIC + * + * @param NVIC_configStruct configParams + * + * @param IRQn Interrupt number + * + * @retval None + */ +void NVIC_Init(NVIC_ConfigTypeDef *NVIC_configStruct,IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_FM33LC0XX_H */ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/system_fm33lg0xx.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/system_fm33lg0xx.h new file mode 100644 index 0000000000..b2737a3e79 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/system_fm33lg0xx.h @@ -0,0 +1,101 @@ +/**************************************************************************//** + * @file system_FM33LG0XX.h + * @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for + * Device FM33LG0XX + * @version V1.02 + * @date 31-8-2018 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef SYSTEM_FM33LG0XX_H +#define SYSTEM_FM33LG0XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "fm33lg0xx.h" + + +#if !defined (XTHF_VALUE) + #define XTHF_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* XTHF_VALUE */ + +#if !defined (XTLF_VALUE) + #define XTLF_VALUE ((uint32_t)32768U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* XTLF_VALUE */ + + +#define __SYSTEM_CLOCK (8000000) +#define DELAY_US (__SYSTEM_CLOCK/1000000) +#define DELAY_MS (__SYSTEM_CLOCK/1000) + + +#define Do_DelayStart() { \ + uint32_t LastTick = SysTick->VAL; do { + +#define While_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)VAL)&0xFFFFFF)PLLCR >> 1) & 0x1) + { + case 0: + switch ((RCC->RCHFCR >> 16) & 0xf) + { + case 1: // 16M + clock = 16000000; + break; + + case 2: // 24M + clock = 24000000; + break; + + case 0: // 8M + default: + clock = 8000000; + break; + } + break; + + case 1: + clock = XTHF_VALUE; + break; + } + + // 分频 + switch ((RCC->PLLCR >> 0x4) & 0x7) + { + case 0: // 不分频 + clock /= 1; + break; + + case 1: // 2分频 + clock /= 2; + break; + + case 2: // 4分频 + clock /= 4; + break; + + case 3: // 8分频 + clock /= 8; + break; + + case 4: // 12分频 + clock /= 12; + break; + + case 5: // 16分频 + clock /= 16; + break; + + case 6: // 24分频 + clock /= 24; + break; + + case 7: // 32分频 + clock /= 32; + break; + } + + // 倍频比 + clock = clock * (((RCC->PLLCR >> 16) & 0x7f) + 1); + + // 输出选择 + if ((RCC->PLLCR >> 3) & 0x1) + { + clock *= 2; + } + + return clock; +} + +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + switch ((RCC->SYSCLKCR >> 0) & 0x7) + { + case 1: // XTHF + SystemCoreClock = XTHF_VALUE; + break; + + case 2: // PLL + SystemCoreClock = SystemPLLClockUpdate(); + break; + + case 4: // RCMF + switch ((RCC->RCMFCR >> 16) & 0x3) + { + case 0: // 不分频 + SystemCoreClock = 4000000; + break; + + case 1: // 4分频 + SystemCoreClock = 1000000; + break; + + case 2: // 8分频 + SystemCoreClock = 500000; + break; + + case 3: // 16分频 + SystemCoreClock = 250000; + break; + } + break; + + case 5: // LSCLK + case 6: // LPOSC + SystemCoreClock = 32768; + break; + + case 7: // USBBCK + switch ((RCC->SYSCLKCR >> 3) & 0x1) + { + case 0: // USBBCK 48M + SystemCoreClock = 48000000; + break; + + case 1: // USBBCK 120M 2分频 + SystemCoreClock = 60000000; + break; + } + break; + + default: + switch ((RCC->RCHFCR >> 16) & 0xf) + { + case 1: // 16M + SystemCoreClock = 16000000; + break; + + case 2: // 24M + SystemCoreClock = 24000000; + break; + + case 0: // 8M + default: + SystemCoreClock = 8000000; + break; + } + break; + } +} + +/** + * @brief NVIC_Init config NVIC + * + * @param NVIC_configStruct configParams + * + * @param IRQn Interrupt number + * + * @retval None + */ +void NVIC_Init(NVIC_ConfigTypeDef *NVIC_configStruct,IRQn_Type IRQn) +{ + /* Params Check */ + if(NVIC_configStruct->preemptPriority>3) + { + NVIC_configStruct->preemptPriority = 3; + } + + NVIC_DisableIRQ(IRQn); + NVIC_SetPriority(IRQn,NVIC_configStruct->preemptPriority); + NVIC_EnableIRQ(IRQn); +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + uint32_t temp; + + /* */ + RCC->PLLCR = (uint32_t)0x00000000U; + RCC->SYSCLKCR = (uint32_t)0x0A000000U; + /* PAD RCC*/ + RCC->PCLKCR1 |= (0x1U << 7U); + #ifdef USE_LSCLK_CLOCK_SRC_XTLF + GPIOD->FCR |= 0x3C0000; + /* XTLF*/ + RCC->XTLFCR = (uint32_t)(0x00000000U); + /* XTLF*/ + RCC->XTLFCR |= (uint32_t)(0x00000005U<<8); + for(temp = 2000;temp>0;temp--); + /* LSCLKXTLF*/ + RCC->LSCLKSEL = 0xAA; + /* LSCXTLF*/ + RCC->SYSCLKCR |= 0x8000000U; + #else + RCC->SYSCLKCR &= 0x7FFFFFFU; + RCC->LSCLKSEL = 0x55; + #endif + /*PDR*/ + RMU->PDRCR |=0x01; + /*BOR*/ + RMU->BORCR &=0xFE; + + /* DEBUG IWDT WWDT */ + DBG->CR =0x03; + + RCC->RCHFTR = RCHF24M_TRIM; + RCC->RCMFTR = RCMF4M_TRIM; + RCC->LPOSCTR = LPOSC_TRIM; + + GPIOD->PUEN |= 0x3 << 7; + + /* DMA Flash Channel: Flash->RAM */ + RCC->PCLKCR2 |= 0x1 << 4; + DMA->CH7CR |= 0x1 << 10; + RCC->PCLKCR2 &= ~(0x1 << 4); +} + + + diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/system_fm33lg0xx.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/system_fm33lg0xx.c new file mode 100644 index 0000000000..786a5119ff --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/system_fm33lg0xx.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_.c + * @brief CMSIS Cortex-M# Device Peripheral Access Layer Source File for + * Device + * @version V3.10 + * @date 23. November 2012 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THES + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#include "fm33lg0xx.h" +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +/* ToDo: add here your necessary defines for device initialization + following is an example for different system frequencies */ + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/* ToDo: initialize SystemCoreClock with the system core clock frequency value + achieved after system intitialization. + This means system core clock frequency after call to SystemInit() */ +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + +} +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + +} + + + diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl.h new file mode 100644 index 0000000000..3614e6ae9b --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl.h @@ -0,0 +1,289 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl.h + * @author FMSH Application Team + * @brief Header file of FL Driver Library + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_H +#define __FM33LC0XX_FL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Select FM33LC0XX Device + */ +#if !defined (FM33LC0XX) +#define FM33LC0XX +#endif /* FM33LC0XX */ + +/* Defines -------------------------------------------------------------------------------------------*/ + +/** + * @brief List of drivers to be used. + * + * @note Uncomment following lines to disable specified driver. + */ + +#ifndef MFANG + +#define FL_ADC_DRIVER_ENABLED +#define FL_AES_DRIVER_ENABLED +#define FL_ATIM_DRIVER_ENABLED +#define FL_BSTIM32_DRIVER_ENABLED +#define FL_COMP_DRIVER_ENABLED +#define FL_CRC_DRIVER_ENABLED +#define FL_DIVAS_DRIVER_ENABLED +#define FL_DMA_DRIVER_ENABLED +#define FL_EXTI_DRIVER_ENABLED +#define FL_FLASH_DRIVER_ENABLED +#define FL_GPIO_DRIVER_ENABLED +#define FL_GPTIM_DRIVER_ENABLED +#define FL_I2C_DRIVER_ENABLED +#define FL_IWDT_DRIVER_ENABLED +#define FL_LCD_DRIVER_ENABLED +#define FL_LPTIM32_DRIVER_ENABLED +#define FL_LPUART_DRIVER_ENABLED +#define FL_OPA_DRIVER_ENABLED +#define FL_PMU_DRIVER_ENABLED +#define FL_RCC_DRIVER_ENABLED +#define FL_RMU_DRIVER_ENABLED +#define FL_RNG_DRIVER_ENABLED +#define FL_RTC_DRIVER_ENABLED +#define FL_SPI_DRIVER_ENABLED +#define FL_SVD_DRIVER_ENABLED +#define FL_U7816_DRIVER_ENABLED +#define FL_UART_DRIVER_ENABLED +#define FL_VREF_DRIVER_ENABLED +#define FL_WWDT_DRIVER_ENABLED + +#endif + +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33xx.h" +#include "fm33_assert.h" +#include +#include +#include + +/* Macros ---------------------------------------------------------------------------------------------*/ +/** @defgroup FL_Private_Macros FL Driver Library Private Macros + * @{ + */ + +/** + * @brief FM33LC0xx FL Driver Library version number + */ +#define __FM33LC0xx_FL_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __FM33LC0xx_FL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __FM33LC0xx_FL_VERSION_SUB2 (0x01) /*!< [15:0] sub2 version */ +#define __FM33LC0xx_FL_VERSION ((__FM33LC0xx_FL_VERSION_MAIN << 24)\ + |(__FM33LC0xx_FL_VERSION_SUB1 << 16)\ + |(__FM33LC0xx_FL_VERSION_SUB2)) + +/** + * @brief Macros used by delay support functions + */ +#define FL_DELAY_US (SystemCoreClock/1000000) +#define FL_DELAY_MS (SystemCoreClock/1000) + +/** + * @} + */ + +/* Types ----------------------------------------------------------------------------------------------*/ +/** @defgroup FL_ET_Return FL Exported Return Type Defines + * @{ + */ + +typedef enum +{ + FL_RESET = 0U, + FL_SET = !FL_RESET +} FL_FlagStatus, FL_ITStatus; + +typedef enum +{ + FL_DISABLE = 0U, + FL_ENABLE = !FL_DISABLE +} FL_FunState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == FL_DISABLE) || ((STATE) == FL_ENABLE)) + +typedef enum +{ + FL_FAIL = 0U, + FL_PASS = !FL_FAIL +} FL_ErrorStatus; + +/** + * @} + */ + +/* Exported Functions ---------------------------------------------------------------------------------*/ +/** @defgroup FL_EF_DELAY Exported FL Driver Library Delay Support Functions + * @{ + */ + +/** + * @} + */ + +/** @defgroup FL_EF_INIT Exported FL Driver Library Init Functions + * @{ + */ + +void FL_Init(void); + +/** + * @} + */ + +/* Post Includes --------------------------------------------------------------------------------------*/ +/** + * @brief Include peripheral's header file + */ + +#if defined(USE_FULL_ASSERT) +#include "fm33_assert.h" +#endif /* USE_FULL_ASSERT */ + +#if defined(FL_ADC_DRIVER_ENABLED) +#include "fm33lc0xx_fl_adc.h" +#endif /* FL_ADC_DRIVER_ENABLED */ + +#if defined(FL_AES_DRIVER_ENABLED) +#include "fm33lc0xx_fl_aes.h" +#endif /* FL_AES_DRIVER_ENABLED */ + +#if defined(FL_ATIM_DRIVER_ENABLED) +#include "fm33lc0xx_fl_atim.h" +#endif /* FL_ATIM_DRIVER_ENABLED */ + +#if defined(FL_BSTIM32_DRIVER_ENABLED) +#include "fm33lc0xx_fl_bstim32.h" +#endif /* FL_BSTIM32_DRIVER_ENABLED */ + +#if defined(FL_COMP_DRIVER_ENABLED) +#include "fm33lc0xx_fl_comp.h" +#endif /* FL_COMP_DRIVER_ENABLED */ + +#if defined(FL_CRC_DRIVER_ENABLED) +#include "fm33lc0xx_fl_crc.h" +#endif /* FL_CRC_DRIVER_ENABLED */ + +#if defined(FL_DIVAS_DRIVER_ENABLED) +#include "fm33lc0xx_fl_divas.h" +#endif /* FL_DIVAS_DRIVER_ENABLED */ + +#if defined(FL_DMA_DRIVER_ENABLED) +#include "fm33lc0xx_fl_dma.h" +#endif /* FL_DMA_DRIVER_ENABLED */ + +#if defined(FL_EXTI_DRIVER_ENABLED) +#include "fm33lc0xx_fl_exti.h" +#endif /* FL_EXTI_DRIVER_ENABLED */ + +#if defined(FL_FLASH_DRIVER_ENABLED) +#include "fm33lc0xx_fl_flash.h" +#endif /* FL_FLASH_DRIVER_ENABLED */ + +#if defined(FL_GPIO_DRIVER_ENABLED) +#include "fm33lc0xx_fl_gpio.h" +#endif /* FL_GPIO_DRIVER_ENABLED */ + +#if defined(FL_GPTIM_DRIVER_ENABLED) +#include "fm33lc0xx_fl_gptim.h" +#endif /* FL_GPTIM_DRIVER_ENABLED */ + +#if defined(FL_I2C_DRIVER_ENABLED) +#include "fm33lc0xx_fl_i2c.h" +#endif /* FL_I2C_DRIVER_ENABLED */ + +#if defined(FL_IWDT_DRIVER_ENABLED) +#include "fm33lc0xx_fl_iwdt.h" +#endif /* FL_IWDT_DRIVER_ENABLED */ + +#if defined(FL_LCD_DRIVER_ENABLED) +#include "fm33lc0xx_fl_lcd.h" +#endif /* FL_LCD_DRIVER_ENABLED */ + +#if defined(FL_LPTIM32_DRIVER_ENABLED) +#include "fm33lc0xx_fl_lptim32.h" +#endif /* FL_LPTIM32_DRIVER_ENABLED */ + +#if defined(FL_LPUART_DRIVER_ENABLED) +#include "fm33lc0xx_fl_lpuart.h" +#endif /* FL_LPUART_DRIVER_ENABLED */ + +#if defined(FL_OPA_DRIVER_ENABLED) +#include "fm33lc0xx_fl_opa.h" +#endif /* FL_OPA_DRIVER_ENABLED */ + +#if defined(FL_PMU_DRIVER_ENABLED) +#include "fm33lc0xx_fl_pmu.h" +#endif /* FL_PMU_DRIVER_ENABLED */ + +#if defined(FL_RCC_DRIVER_ENABLED) +#include "fm33lc0xx_fl_rcc.h" +#endif /* FL_RCC_DRIVER_ENABLED */ + +#if defined(FL_RMU_DRIVER_ENABLED) +#include "fm33lc0xx_fl_rmu.h" +#endif /* FL_RMU_DRIVER_ENABLED */ + +#if defined(FL_RNG_DRIVER_ENABLED) +#include "fm33lc0xx_fl_rng.h" +#endif /* FL_RNG_DRIVER_ENABLED */ + +#if defined(FL_RTC_DRIVER_ENABLED) +#include "fm33lc0xx_fl_rtc.h" +#endif /* FL_RTC_DRIVER_ENABLED */ + +#if defined(FL_SPI_DRIVER_ENABLED) +#include "fm33lc0xx_fl_spi.h" +#endif /* FL_SPI_DRIVER_ENABLED */ + +#if defined(FL_SVD_DRIVER_ENABLED) +#include "fm33lc0xx_fl_svd.h" +#endif /* FL_SVD_DRIVER_ENABLED */ + +#if defined(FL_U7816_DRIVER_ENABLED) +#include "fm33lc0xx_fl_u7816.h" +#endif /* FL_U7816_DRIVER_ENABLED */ + +#if defined(FL_UART_DRIVER_ENABLED) +#include "fm33lc0xx_fl_uart.h" +#endif /* FL_UART_DRIVER_ENABLED */ + +#if defined(FL_VREF_DRIVER_ENABLED) +#include "fm33lc0xx_fl_vref.h" +#endif /* FL_VREF_DRIVER_ENABLED */ + +#if defined(FL_WWDT_DRIVER_ENABLED) +#include "fm33lc0xx_fl_wwdt.h" +#endif /* FL_WWDT_DRIVER_ENABLED */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_H */ + +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_adc.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_adc.h new file mode 100644 index 0000000000..02fdc00e46 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_adc.h @@ -0,0 +1,1655 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_adc.h + * @author FMSH Application Team + * @brief Head file of ADC FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_ADC_H +#define __FM33LC0XX_FL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup ADC_FL_ES_INIT ADC Exported Init structures + * @{ + */ + +/** + * @brief ADC Common Init Sturcture Definition + */ +typedef struct +{ + /*ADCCLK源选择*/ + uint32_t clockSource; + /*ADCCLK预分频配置*/ + uint32_t clockPrescaler; + +} FL_ADC_CommonInitTypeDef; + +/** + * @brief ADC Init Sturcture Definition + */ +typedef struct +{ + /*连续转换模式配置*/ + uint32_t conversionMode; + + /*单次自动转换模式配置*/ + uint32_t autoMode; + + /*等待模式配置*/ + FL_FunState waitMode; + + /*覆盖模式配置*/ + FL_FunState overrunMode; + + /*通道扫描顺序配置*/ + uint32_t scanDirection; + + /*触发信号使能配置*/ + uint32_t externalTrigConv; + + /*触发源选择*/ + uint32_t triggerSource; + + /*快速通道采样时间配置*/ + uint32_t fastChannelTime; + + /*慢速通道采样时间配置*/ + uint32_t lowChannelTime; + + /*过采样使能配置*/ + FL_FunState oversamplingMode; + + /*过采样率配置*/ + uint32_t overSampingMultiplier; + + /*过采样移位配置*/ + uint32_t oversamplingShift; +} FL_ADC_InitTypeDef; + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup ADC_FL_Exported_Constants ADC Exported Constants + * @{ + */ + +#define ADC_ISR_EOC_Pos (0U) +#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) +#define ADC_ISR_EOC ADC_ISR_EOC_Msk + +#define ADC_ISR_EOS_Pos (1U) +#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) +#define ADC_ISR_EOS ADC_ISR_EOS_Msk + +#define ADC_ISR_OVR_Pos (2U) +#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) +#define ADC_ISR_OVR ADC_ISR_OVR_Msk + +#define ADC_ISR_BUSY_Pos (3U) +#define ADC_ISR_BUSY_Msk (0x1U << ADC_ISR_BUSY_Pos) +#define ADC_ISR_BUSY ADC_ISR_BUSY_Msk + +#define ADC_ISR_AWD_UL_Pos (5U) +#define ADC_ISR_AWD_UL_Msk (0x1U << ADC_ISR_AWD_UL_Pos) +#define ADC_ISR_AWD_UL ADC_ISR_AWD_UL_Msk + +#define ADC_ISR_AWD_AH_Pos (6U) +#define ADC_ISR_AWD_AH_Msk (0x1U << ADC_ISR_AWD_AH_Pos) +#define ADC_ISR_AWD_AH ADC_ISR_AWD_AH_Msk + +#define ADC_IER_EOCIE_Pos (0U) +#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk + +#define ADC_IER_EOSIE_Pos (1U) +#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk + +#define ADC_IER_OVRIE_Pos (2U) +#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk + +#define ADC_IER_AWD_ULIE_Pos (5U) +#define ADC_IER_AWD_ULIE_Msk (0x1U << ADC_IER_AWD_ULIE_Pos) +#define ADC_IER_AWD_ULIE ADC_IER_AWD_ULIE_Msk + +#define ADC_IER_AWD_AHIE_Pos (6U) +#define ADC_IER_AWD_AHIE_Msk (0x1U << ADC_IER_AWD_AHIE_Pos) +#define ADC_IER_AWD_AHIE ADC_IER_AWD_AHIE_Msk + +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) +#define ADC_CR_ADEN ADC_CR_ADEN_Msk + +#define ADC_CR_START_Pos (1U) +#define ADC_CR_START_Msk (0x1U << ADC_CR_START_Pos) +#define ADC_CR_START ADC_CR_START_Msk + +#define ADC_CR_EXSAMP_Pos (9U) +#define ADC_CR_EXSAMP_Msk (0x1U << ADC_CR_EXSAMP_Pos) +#define ADC_CR_EXSAMP ADC_CR_EXSAMP_Msk + +#define ADC_CR_EXSYNC_Pos (8U) +#define ADC_CR_EXSYNC_Msk (0x1U << ADC_CR_EXSYNC_Pos) +#define ADC_CR_EXSYNC ADC_CR_EXSYNC_Msk + +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk + +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk + +#define ADC_CFGR_SCANDIR_Pos (2U) +#define ADC_CFGR_SCANDIR_Msk (0x1U << ADC_CFGR_SCANDIR_Pos) +#define ADC_CFGR_SCANDIR ADC_CFGR_SCANDIR_Msk + +#define ADC_CFGR_EXTS_Pos (4U) +#define ADC_CFGR_EXTS_Msk (0xfU << ADC_CFGR_EXTS_Pos) +#define ADC_CFGR_EXTS ADC_CFGR_EXTS_Msk + +#define ADC_CFGR_OVRM_Pos (8U) +#define ADC_CFGR_OVRM_Msk (0x1U << ADC_CFGR_OVRM_Pos) +#define ADC_CFGR_OVRM ADC_CFGR_OVRM_Msk + +#define ADC_CFGR_CONT_Pos (9U) +#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk + +#define ADC_CFGR_WAIT_Pos (10U) +#define ADC_CFGR_WAIT_Msk (0x1U << ADC_CFGR_WAIT_Pos) +#define ADC_CFGR_WAIT ADC_CFGR_WAIT_Msk + +#define ADC_CFGR_SEMI_Pos (11U) +#define ADC_CFGR_SEMI_Msk (0x1U << ADC_CFGR_SEMI_Pos) +#define ADC_CFGR_SEMI ADC_CFGR_SEMI_Msk + +#define ADC_CFGR_TRGCFG_Pos (12U) +#define ADC_CFGR_TRGCFG_Msk (0x3U << ADC_CFGR_TRGCFG_Pos) +#define ADC_CFGR_TRGCFG ADC_CFGR_TRGCFG_Msk + +#define ADC_CFGR_IOTRFEN_Pos (14U) +#define ADC_CFGR_IOTRFEN_Msk (0x1U << ADC_CFGR_IOTRFEN_Pos) +#define ADC_CFGR_IOTRFEN ADC_CFGR_IOTRFEN_Msk + +#define ADC_CFGR_OVSEN_Pos (16U) +#define ADC_CFGR_OVSEN_Msk (0x1U << ADC_CFGR_OVSEN_Pos) +#define ADC_CFGR_OVSEN ADC_CFGR_OVSEN_Msk + +#define ADC_CFGR_OVSR_Pos (17U) +#define ADC_CFGR_OVSR_Msk (0x7U << ADC_CFGR_OVSR_Pos) +#define ADC_CFGR_OVSR ADC_CFGR_OVSR_Msk + +#define ADC_CFGR_OVSS_Pos (20U) +#define ADC_CFGR_OVSS_Msk (0xfU << ADC_CFGR_OVSS_Pos) +#define ADC_CFGR_OVSS ADC_CFGR_OVSS_Msk + +#define ADC_CFGR_AWDEN_Pos (24U) +#define ADC_CFGR_AWDEN_Msk (0x1U << ADC_CFGR_AWDEN_Pos) +#define ADC_CFGR_AWDEN ADC_CFGR_AWDEN_Msk + +#define ADC_CFGR_AWDSC_Pos (25U) +#define ADC_CFGR_AWDSC_Msk (0x1U << ADC_CFGR_AWDSC_Pos) +#define ADC_CFGR_AWDSC ADC_CFGR_AWDSC_Msk + +#define ADC_CFGR_AWDCH_Pos (26U) +#define ADC_CFGR_AWDCH_Msk (0xfU << ADC_CFGR_AWDCH_Pos) +#define ADC_CFGR_AWDCH ADC_CFGR_AWDCH_Msk + +#define ADC_SMTR_SMTS1_Pos (0U) +#define ADC_SMTR_SMTS1_Msk (0xfU << ADC_SMTR_SMTS1_Pos) +#define ADC_SMTR_SMTS1 ADC_SMTR_SMTS1_Msk + +#define ADC_SMTR_SMTS2_Pos (4U) +#define ADC_SMTR_SMTS2_Msk (0xfU << ADC_SMTR_SMTS2_Pos) +#define ADC_SMTR_SMTS2 ADC_SMTR_SMTS2_Msk + +#define ADC_SMTR_CHCG_Pos (8U) +#define ADC_SMTR_CHCG_Msk (0xfU << ADC_SMTR_CHCG_Pos) +#define ADC_SMTR_CHCG ADC_SMTR_CHCG_Msk + +#define ADC_SAMPT_SAMPT_S_Pos (0U) +#define ADC_SAMPT_SAMPT_S_Msk (0x1U << ADC_SAMPT_SAMPT_S_Pos) +#define ADC_SAMPT_SAMPT_S ADC_SAMPT_SAMPT_S_Msk + +#define ADC_HLTR_AWD_LT_Pos (0U) +#define ADC_HLTR_AWD_LT_Msk (0xfffU << ADC_HLTR_AWD_LT_Pos) +#define ADC_HLTR_AWD_LT ADC_HLTR_AWD_LT_Msk + +#define ADC_HLTR_AWD_HT_Pos (16U) +#define ADC_HLTR_AWD_HT_Msk (0xfffU << ADC_HLTR_AWD_HT_Pos) +#define ADC_HLTR_AWD_HT ADC_HLTR_AWD_HT_Msk + + + +#define FL_ADC_EXTERNAL_CH0 (0x1U << 0U) +#define FL_ADC_EXTERNAL_CH1 (0x1U << 1U) +#define FL_ADC_EXTERNAL_CH2 (0x1U << 2U) +#define FL_ADC_EXTERNAL_CH3 (0x1U << 3U) +#define FL_ADC_EXTERNAL_CH4 (0x1U << 4U) +#define FL_ADC_EXTERNAL_CH5 (0x1U << 5U) +#define FL_ADC_EXTERNAL_CH6 (0x1U << 6U) +#define FL_ADC_EXTERNAL_CH7 (0x1U << 7U) +#define FL_ADC_EXTERNAL_CH8 (0x1U << 8U) +#define FL_ADC_EXTERNAL_CH9 (0x1U << 9U) +#define FL_ADC_EXTERNAL_CH10 (0x1U << 10U) +#define FL_ADC_EXTERNAL_CH11 (0x1U << 11U) +#define FL_ADC_INTERNAL_TS (0x1U << 16U) +#define FL_ADC_INTERNAL_VREF1P2 (0x1U << 17U) +#define FL_ADC_INTERNAL_OPA1 (0x1U << 18U) +#define FL_ADC_INTERNAL_OPA2 (0x1U << 19U) + + + +#define FL_ADC_SAMPLING_TIME_CONTROL_BY_REG (0x0U << ADC_CR_EXSAMP_Pos) +#define FL_ADC_SAMPLING_TIME_CONTROL_BY_IO (0x1U << ADC_CR_EXSAMP_Pos) + + +#define FL_ADC_SAMPLING_START_CONTROL_BY_REG (0x0U << ADC_CR_EXSYNC_Pos) +#define FL_ADC_SAMPLING_START_CONTROL_BY_IO (0x1U << ADC_CR_EXSYNC_Pos) + + +#define FL_ADC_DMA_MODE_SINGLE (0x0U << ADC_CFGR_DMACFG_Pos) +#define FL_ADC_DMA_MODE_CIRCULAR (0x1U << ADC_CFGR_DMACFG_Pos) + + +#define FL_ADC_SEQ_SCAN_DIR_FORWARD (0x0U << ADC_CFGR_SCANDIR_Pos) +#define FL_ADC_SEQ_SCAN_DIR_BACKWARD (0x1U << ADC_CFGR_SCANDIR_Pos) + + +#define FL_ADC_TRGI_PA8 (0x0U << ADC_CFGR_EXTS_Pos) +#define FL_ADC_TRGI_PB9 (0x1U << ADC_CFGR_EXTS_Pos) +#define FL_ADC_TRGI_ATIM (0x3U << ADC_CFGR_EXTS_Pos) +#define FL_ADC_TRGI_GPTIM0 (0x4U << ADC_CFGR_EXTS_Pos) +#define FL_ADC_TRGI_GPTIM1 (0x5U << ADC_CFGR_EXTS_Pos) +#define FL_ADC_TRGI_RTC (0x7U << ADC_CFGR_EXTS_Pos) +#define FL_ADC_TRGI_BSTIM1 (0x8U << ADC_CFGR_EXTS_Pos) +#define FL_ADC_TRGI_COMP1 (0xaU << ADC_CFGR_EXTS_Pos) +#define FL_ADC_TRGI_COMP2 (0xbU << ADC_CFGR_EXTS_Pos) + + +#define FL_ADC_CONV_MODE_SINGLE (0x0U << ADC_CFGR_CONT_Pos) +#define FL_ADC_CONV_MODE_CONTINUOUS (0x1U << ADC_CFGR_CONT_Pos) + + +#define FL_ADC_SINGLE_CONV_MODE_AUTO (0x0U << ADC_CFGR_SEMI_Pos) +#define FL_ADC_SINGLE_CONV_MODE_SEMIAUTO (0x1U << ADC_CFGR_SEMI_Pos) + + +#define FL_ADC_TRIGGER_EDGE_NONE (0x0U << ADC_CFGR_TRGCFG_Pos) +#define FL_ADC_TRIGGER_EDGE_RISING (0x1U << ADC_CFGR_TRGCFG_Pos) +#define FL_ADC_TRIGGER_EDGE_FALLING (0x2U << ADC_CFGR_TRGCFG_Pos) +#define FL_ADC_TRIGGER_EDGE_BOTH (0x3U << ADC_CFGR_TRGCFG_Pos) + + +#define FL_ADC_OVERSAMPLING_MUL_2X (0x0U << ADC_CFGR_OVSR_Pos) +#define FL_ADC_OVERSAMPLING_MUL_4X (0x1U << ADC_CFGR_OVSR_Pos) +#define FL_ADC_OVERSAMPLING_MUL_8X (0x2U << ADC_CFGR_OVSR_Pos) +#define FL_ADC_OVERSAMPLING_MUL_16X (0x3U << ADC_CFGR_OVSR_Pos) +#define FL_ADC_OVERSAMPLING_MUL_32X (0x4U << ADC_CFGR_OVSR_Pos) +#define FL_ADC_OVERSAMPLING_MUL_64X (0x5U << ADC_CFGR_OVSR_Pos) +#define FL_ADC_OVERSAMPLING_MUL_128X (0x6U << ADC_CFGR_OVSR_Pos) +#define FL_ADC_OVERSAMPLING_MUL_256X (0x7U << ADC_CFGR_OVSR_Pos) + + +#define FL_ADC_OVERSAMPLING_SHIFT_0B (0x0U << ADC_CFGR_OVSS_Pos) +#define FL_ADC_OVERSAMPLING_SHIFT_1B (0x1U << ADC_CFGR_OVSS_Pos) +#define FL_ADC_OVERSAMPLING_SHIFT_2B (0x2U << ADC_CFGR_OVSS_Pos) +#define FL_ADC_OVERSAMPLING_SHIFT_3B (0x3U << ADC_CFGR_OVSS_Pos) +#define FL_ADC_OVERSAMPLING_SHIFT_4B (0x4U << ADC_CFGR_OVSS_Pos) +#define FL_ADC_OVERSAMPLING_SHIFT_5B (0x5U << ADC_CFGR_OVSS_Pos) +#define FL_ADC_OVERSAMPLING_SHIFT_6B (0x6U << ADC_CFGR_OVSS_Pos) +#define FL_ADC_OVERSAMPLING_SHIFT_7B (0x7U << ADC_CFGR_OVSS_Pos) +#define FL_ADC_OVERSAMPLING_SHIFT_8B (0x8U << ADC_CFGR_OVSS_Pos) + + +#define FL_ADC_AWDG_ALL_CHANNEL (0x0U << ADC_CFGR_AWDSC_Pos) +#define FL_ADC_AWDG_SINGLE_CHANNEL (0x1U << ADC_CFGR_AWDSC_Pos) + + +#define FL_ADC_AWDG_CH0 (0x0U << ADC_CFGR_AWDCH_Pos) +#define FL_ADC_AWDG_CH1 (0x1U << ADC_CFGR_AWDCH_Pos) +#define FL_ADC_AWDG_CH2 (0x2U << ADC_CFGR_AWDCH_Pos) +#define FL_ADC_AWDG_CH3 (0x3U << ADC_CFGR_AWDCH_Pos) +#define FL_ADC_AWDG_CH4 (0x4U << ADC_CFGR_AWDCH_Pos) +#define FL_ADC_AWDG_CH5 (0x5U << ADC_CFGR_AWDCH_Pos) +#define FL_ADC_AWDG_CH6 (0x6U << ADC_CFGR_AWDCH_Pos) +#define FL_ADC_AWDG_CH7 (0x7U << ADC_CFGR_AWDCH_Pos) +#define FL_ADC_AWDG_CH8 (0x8U << ADC_CFGR_AWDCH_Pos) +#define FL_ADC_AWDG_CH9 (0x9U << ADC_CFGR_AWDCH_Pos) +#define FL_ADC_AWDG_CH10 (0xaU << ADC_CFGR_AWDCH_Pos) +#define FL_ADC_AWDG_CH11 (0xbU << ADC_CFGR_AWDCH_Pos) + + +#define FL_ADC_FAST_CH_SAMPLING_TIME_4_ADCCLK (0x0U << ADC_SMTR_SMTS1_Pos) +#define FL_ADC_FAST_CH_SAMPLING_TIME_6_ADCCLK (0x1U << ADC_SMTR_SMTS1_Pos) +#define FL_ADC_FAST_CH_SAMPLING_TIME_9_ADCCLK (0x2U << ADC_SMTR_SMTS1_Pos) +#define FL_ADC_FAST_CH_SAMPLING_TIME_10_ADCCLK (0x3U << ADC_SMTR_SMTS1_Pos) +#define FL_ADC_FAST_CH_SAMPLING_TIME_16_ADCCLK (0x4U << ADC_SMTR_SMTS1_Pos) +#define FL_ADC_FAST_CH_SAMPLING_TIME_24_ADCCLK (0x5U << ADC_SMTR_SMTS1_Pos) +#define FL_ADC_FAST_CH_SAMPLING_TIME_32_ADCCLK (0x6U << ADC_SMTR_SMTS1_Pos) +#define FL_ADC_FAST_CH_SAMPLING_TIME_48_ADCCLK (0x7U << ADC_SMTR_SMTS1_Pos) +#define FL_ADC_FAST_CH_SAMPLING_TIME_96_ADCCLK (0x8U << ADC_SMTR_SMTS1_Pos) +#define FL_ADC_FAST_CH_SAMPLING_TIME_128_ADCCLK (0x9U << ADC_SMTR_SMTS1_Pos) +#define FL_ADC_FAST_CH_SAMPLING_TIME_192_ADCCLK (0xaU << ADC_SMTR_SMTS1_Pos) +#define FL_ADC_FAST_CH_SAMPLING_TIME_256_ADCCLK (0xbU << ADC_SMTR_SMTS1_Pos) +#define FL_ADC_FAST_CH_SAMPLING_TIME_384_ADCCLK (0xcU << ADC_SMTR_SMTS1_Pos) +#define FL_ADC_FAST_CH_SAMPLING_TIME_SOFTWARE_CONTROL (0xdU << ADC_SMTR_SMTS1_Pos) + + +#define FL_ADC_SLOW_CH_SAMPLING_TIME_4_ADCCLK (0x0U << ADC_SMTR_SMTS2_Pos) +#define FL_ADC_SLOW_CH_SAMPLING_TIME_6_ADCCLK (0x1U << ADC_SMTR_SMTS2_Pos) +#define FL_ADC_SLOW_CH_SAMPLING_TIME_9_ADCCLK (0x2U << ADC_SMTR_SMTS2_Pos) +#define FL_ADC_SLOW_CH_SAMPLING_TIME_10_ADCCLK (0x3U << ADC_SMTR_SMTS2_Pos) +#define FL_ADC_SLOW_CH_SAMPLING_TIME_16_ADCCLK (0x4U << ADC_SMTR_SMTS2_Pos) +#define FL_ADC_SLOW_CH_SAMPLING_TIME_24_ADCCLK (0x5U << ADC_SMTR_SMTS2_Pos) +#define FL_ADC_SLOW_CH_SAMPLING_TIME_32_ADCCLK (0x6U << ADC_SMTR_SMTS2_Pos) +#define FL_ADC_SLOW_CH_SAMPLING_TIME_48_ADCCLK (0x7U << ADC_SMTR_SMTS2_Pos) +#define FL_ADC_SLOW_CH_SAMPLING_TIME_96_ADCCLK (0x8U << ADC_SMTR_SMTS2_Pos) +#define FL_ADC_SLOW_CH_SAMPLING_TIME_128_ADCCLK (0x9U << ADC_SMTR_SMTS2_Pos) +#define FL_ADC_SLOW_CH_SAMPLING_TIME_192_ADCCLK (0xaU << ADC_SMTR_SMTS2_Pos) +#define FL_ADC_SLOW_CH_SAMPLING_TIME_256_ADCCLK (0xbU << ADC_SMTR_SMTS2_Pos) +#define FL_ADC_SLOW_CH_SAMPLING_TIME_384_ADCCLK (0xcU << ADC_SMTR_SMTS2_Pos) +#define FL_ADC_SLOW_CH_SAMPLING_TIME_SOFTWARE_CONTROL (0xdU << ADC_SMTR_SMTS2_Pos) + + +#define FL_ADC_SAMPLING_INTERVAL_2_CYCLE (0x0U << ADC_SMTR_CHCG_Pos) +#define FL_ADC_SAMPLING_INTERVAL_3_CYCLE (0x3U << ADC_SMTR_CHCG_Pos) +#define FL_ADC_SAMPLING_INTERVAL_4_CYCLE (0x4U << ADC_SMTR_CHCG_Pos) +#define FL_ADC_SAMPLING_INTERVAL_5_CYCLE (0x5U << ADC_SMTR_CHCG_Pos) +#define FL_ADC_SAMPLING_INTERVAL_6_CYCLE (0x6U << ADC_SMTR_CHCG_Pos) +#define FL_ADC_SAMPLING_INTERVAL_7_CYCLE (0x7U << ADC_SMTR_CHCG_Pos) +#define FL_ADC_SAMPLING_INTERVAL_8_CYCLE (0x8U << ADC_SMTR_CHCG_Pos) +#define FL_ADC_SAMPLING_INTERVAL_9_CYCLE (0x9U << ADC_SMTR_CHCG_Pos) +#define FL_ADC_SAMPLING_INTERVAL_10_CYCLE (0xaU << ADC_SMTR_CHCG_Pos) +#define FL_ADC_SAMPLING_INTERVAL_11_CYCLE (0xbU << ADC_SMTR_CHCG_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup ADC_FL_Exported_Functions ADC Exported Functions + * @{ + */ + +/** + * @brief Get ADC End Of Conversion Flag + * @rmtoll ISR EOC FL_ADC_IsActiveFlag_EndOfConversion + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsActiveFlag_EndOfConversion(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->ISR, ADC_ISR_EOC_Msk) == (ADC_ISR_EOC_Msk)); +} + +/** + * @brief Clear ADC End Of Conversion Flag + * @rmtoll ISR EOC FL_ADC_ClearFlag_EndOfConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_ClearFlag_EndOfConversion(ADC_Type *ADCx) +{ + WRITE_REG(ADCx->ISR, ADC_ISR_EOC_Msk); +} + +/** + * @brief Get ADC End Of Sequence Flag + * @rmtoll ISR EOS FL_ADC_IsActiveFlag_EndOfSequence + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsActiveFlag_EndOfSequence(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->ISR, ADC_ISR_EOS_Msk) == (ADC_ISR_EOS_Msk)); +} + +/** + * @brief Clear ADC End Of Sequence Flag + * @rmtoll ISR EOS FL_ADC_ClearFlag_EndOfSequence + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_ClearFlag_EndOfSequence(ADC_Type *ADCx) +{ + WRITE_REG(ADCx->ISR, ADC_ISR_EOS_Msk); +} + +/** + * @brief Get ADC Data Overrun Flag + * @rmtoll ISR OVR FL_ADC_IsActiveFlag_Overrun + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsActiveFlag_Overrun(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->ISR, ADC_ISR_OVR_Msk) == (ADC_ISR_OVR_Msk)); +} + +/** + * @brief Clear ADC Data Overrun Flag + * @rmtoll ISR OVR FL_ADC_ClearFlag_Overrun + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_ClearFlag_Overrun(ADC_Type *ADCx) +{ + WRITE_REG(ADCx->ISR, ADC_ISR_OVR_Msk); +} + +/** + * @brief Get ADC Busy Flag + * @rmtoll ISR BUSY FL_ADC_IsActiveFlag_Busy + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsActiveFlag_Busy(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->ISR, ADC_ISR_BUSY_Msk) == (ADC_ISR_BUSY_Msk)); +} + +/** + * @brief Get ADC Analog Watchdog Under Low + * @rmtoll ISR AWD_UL FL_ADC_IsActiveFlag_AnalogWDGUnderLow + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsActiveFlag_AnalogWDGUnderLow(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->ISR, ADC_ISR_AWD_UL_Msk) == (ADC_ISR_AWD_UL_Msk)); +} + +/** + * @brief Clear ADC Analog Watchdog Under Low + * @rmtoll ISR AWD_UL FL_ADC_ClearFlag_AnalogWDGUnderLow + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_ClearFlag_AnalogWDGUnderLow(ADC_Type *ADCx) +{ + WRITE_REG(ADCx->ISR, ADC_ISR_AWD_UL_Msk); +} + +/** + * @brief Get ADC Analog Watchdog Above High + * @rmtoll ISR AWD_AH FL_ADC_IsActiveFlag_AnalogWDGAboveHigh + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsActiveFlag_AnalogWDGAboveHigh(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->ISR, ADC_ISR_AWD_AH_Msk) == (ADC_ISR_AWD_AH_Msk)); +} + +/** + * @brief Clear ADC Analog Watchdog Above High + * @rmtoll ISR AWD_AH FL_ADC_ClearFlag_AnalogWDGAboveHigh + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_ClearFlag_AnalogWDGAboveHigh(ADC_Type *ADCx) +{ + WRITE_REG(ADCx->ISR, ADC_ISR_AWD_AH_Msk); +} + +/** + * @brief Enable ADC End 0f Conversion interrupt + * @rmtoll IER EOCIE FL_ADC_EnableIT_EndOfConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_EnableIT_EndOfConversion(ADC_Type *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_EOCIE_Msk); +} + +/** + * @brief Disable ADC End 0f Conversion interrupt + * @rmtoll IER EOCIE FL_ADC_DisableIT_EndOfConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_DisableIT_EndOfConversion(ADC_Type *ADCx) +{ + CLEAR_BIT(ADCx->IER, ADC_IER_EOCIE_Msk); +} + +/** + * @brief Get ADC End 0f Conversion interrupt Enable Status + * @rmtoll IER EOCIE FL_ADC_IsEnabledIT_EndOfConversion + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsEnabledIT_EndOfConversion(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->IER, ADC_IER_EOCIE_Msk) == ADC_IER_EOCIE_Msk); +} + +/** + * @brief Enable ADC End Of Sequence interrupt + * @rmtoll IER EOSIE FL_ADC_EnableIT_EndOfSequence + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_EnableIT_EndOfSequence(ADC_Type *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_EOSIE_Msk); +} + +/** + * @brief Disable ADC End Of Sequence interrupt + * @rmtoll IER EOSIE FL_ADC_DisableIT_EndOfSequence + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_DisableIT_EndOfSequence(ADC_Type *ADCx) +{ + CLEAR_BIT(ADCx->IER, ADC_IER_EOSIE_Msk); +} + +/** + * @brief Get ADC End Of Sequence interrupt Enable Status + * @rmtoll IER EOSIE FL_ADC_IsEnabledIT_EndOfSequence + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsEnabledIT_EndOfSequence(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->IER, ADC_IER_EOSIE_Msk) == ADC_IER_EOSIE_Msk); +} + +/** + * @brief Enable ADC Data Overrun interrupt + * @rmtoll IER OVRIE FL_ADC_EnableIT_Overrun + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_EnableIT_Overrun(ADC_Type *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_OVRIE_Msk); +} + +/** + * @brief Disable ADC Data Overrun interrupt + * @rmtoll IER OVRIE FL_ADC_DisableIT_Overrun + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_DisableIT_Overrun(ADC_Type *ADCx) +{ + CLEAR_BIT(ADCx->IER, ADC_IER_OVRIE_Msk); +} + +/** + * @brief Get ADC Data Overrun interrupt Enable Status + * @rmtoll IER OVRIE FL_ADC_IsEnabledIT_Overrun + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsEnabledIT_Overrun(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->IER, ADC_IER_OVRIE_Msk) == ADC_IER_OVRIE_Msk); +} + +/** + * @brief Enable ADC Analog Watchdog Under Low interrupt + * @rmtoll IER AWD_ULIE FL_ADC_EnableIT_AnalogWDGUnderLow + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_EnableIT_AnalogWDGUnderLow(ADC_Type *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_AWD_ULIE_Msk); +} + +/** + * @brief Disable ADC Analog Watchdog Under Low interrupt + * @rmtoll IER AWD_ULIE FL_ADC_DisableIT_AnalogWDGUnderLow + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_DisableIT_AnalogWDGUnderLow(ADC_Type *ADCx) +{ + CLEAR_BIT(ADCx->IER, ADC_IER_AWD_ULIE_Msk); +} + +/** + * @brief Get ADC Analog Watchdog Under Low interrupt Enable Status + * @rmtoll IER AWD_ULIE FL_ADC_IsEnabledIT_AnalogWDGUnderLow + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsEnabledIT_AnalogWDGUnderLow(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->IER, ADC_IER_AWD_ULIE_Msk) == ADC_IER_AWD_ULIE_Msk); +} + +/** + * @brief Enable ADC Analog Watchdog Above High interrupt + * @rmtoll IER AWD_AHIE FL_ADC_EnableIT_AnalogWDGAboveHigh + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_EnableIT_AnalogWDGAboveHigh(ADC_Type *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_AWD_AHIE_Msk); +} + +/** + * @brief Disable ADC Analog Watchdog Above High interrupt + * @rmtoll IER AWD_AHIE FL_ADC_DisableIT_AnalogWDGAboveHigh + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_DisableIT_AnalogWDGAboveHigh(ADC_Type *ADCx) +{ + CLEAR_BIT(ADCx->IER, ADC_IER_AWD_AHIE_Msk); +} + +/** + * @brief Get ADC Analog Watchdog Above High interrupt Enable Status + * @rmtoll IER AWD_AHIE FL_ADC_IsEnabledIT_AnalogWDGAboveHigh + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsEnabledIT_AnalogWDGAboveHigh(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->IER, ADC_IER_AWD_AHIE_Msk) == ADC_IER_AWD_AHIE_Msk); +} + +/** + * @brief Enable ADC + * @rmtoll CR ADEN FL_ADC_Enable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_Enable(ADC_Type *ADCx) +{ + SET_BIT(ADCx->CR, ADC_CR_ADEN_Msk); +} + +/** + * @brief Disable ADC + * @rmtoll CR ADEN FL_ADC_Disable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_Disable(ADC_Type *ADCx) +{ + CLEAR_BIT(ADCx->CR, ADC_CR_ADEN_Msk); +} + +/** + * @brief Get ADC Enable Status + * @rmtoll CR ADEN FL_ADC_IsEnabled + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsEnabled(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADEN_Msk) == ADC_CR_ADEN_Msk); +} + +/** + * @brief Enable ADC Sofeware Triggered Conversion + * @rmtoll CR START FL_ADC_EnableSWConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_EnableSWConversion(ADC_Type *ADCx) +{ + SET_BIT(ADCx->CR, ADC_CR_START_Msk); +} + +/** + * @brief Set ADC Sampling Time Control Mode + * @rmtoll CR EXSAMP FL_ADC_SetSamplingTimeControlMode + * @param ADCx ADC instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_ADC_SAMPLING_TIME_CONTROL_BY_REG + * @arg @ref FL_ADC_SAMPLING_TIME_CONTROL_BY_IO + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetSamplingTimeControlMode(ADC_Type *ADCx, uint32_t mode) +{ + MODIFY_REG(ADCx->CR, ADC_CR_EXSAMP_Msk, mode); +} + +/** + * @brief Read ADC Sampling Time Control Mode + * @rmtoll CR EXSAMP FL_ADC_GetSamplingTimeControlMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_SAMPLING_TIME_CONTROL_BY_REG + * @arg @ref FL_ADC_SAMPLING_TIME_CONTROL_BY_IO + */ +__STATIC_INLINE uint32_t FL_ADC_GetSamplingTimeControlMode(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_EXSAMP_Msk)); +} + +/** + * @brief Set ADC Sampling Start Control Mode + * @rmtoll CR EXSYNC FL_ADC_SetSamplingStartControlMode + * @param ADCx ADC instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_ADC_SAMPLING_START_CONTROL_BY_REG + * @arg @ref FL_ADC_SAMPLING_START_CONTROL_BY_IO + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetSamplingStartControlMode(ADC_Type *ADCx, uint32_t mode) +{ + MODIFY_REG(ADCx->CR, ADC_CR_EXSYNC_Msk, mode); +} + +/** + * @brief Read ADC Sampling Start Control Mode + * @rmtoll CR EXSYNC FL_ADC_GetSamplingStartControlMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_SAMPLING_START_CONTROL_BY_REG + * @arg @ref FL_ADC_SAMPLING_START_CONTROL_BY_IO + */ +__STATIC_INLINE uint32_t FL_ADC_GetSamplingStartControlMode(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_EXSYNC_Msk)); +} + +/** + * @brief Enable ADC DMA + * @rmtoll CFGR DMAEN FL_ADC_EnableDMAReq + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_EnableDMAReq(ADC_Type *ADCx) +{ + SET_BIT(ADCx->CFGR, ADC_CFGR_DMAEN_Msk); +} + +/** + * @brief Disable ADC DMA + * @rmtoll CFGR DMAEN FL_ADC_DisableDMAReq + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_DisableDMAReq(ADC_Type *ADCx) +{ + CLEAR_BIT(ADCx->CFGR, ADC_CFGR_DMAEN_Msk); +} + +/** + * @brief Get ADC DMA Enable Status + * @rmtoll CFGR DMAEN FL_ADC_IsEnabledDMAReq + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsEnabledDMAReq(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN_Msk) == ADC_CFGR_DMAEN_Msk); +} + +/** + * @brief Set ADC DMA Mode + * @rmtoll CFGR DMACFG FL_ADC_SetDMAMode + * @param ADCx ADC instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_ADC_DMA_MODE_SINGLE + * @arg @ref FL_ADC_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetDMAMode(ADC_Type *ADCx, uint32_t mode) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMACFG_Msk, mode); +} + +/** + * @brief Get ADC ADC DMA Mode + * @rmtoll CFGR DMACFG FL_ADC_GetDMAMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_DMA_MODE_SINGLE + * @arg @ref FL_ADC_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t FL_ADC_GetDMAMode(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMACFG_Msk)); +} + +/** + * @brief Set ADC Channel Scan Direction + * @rmtoll CFGR SCANDIR FL_ADC_SetSequenceScanDirection + * @param ADCx ADC instance + * @param dir This parameter can be one of the following values: + * @arg @ref FL_ADC_SEQ_SCAN_DIR_FORWARD + * @arg @ref FL_ADC_SEQ_SCAN_DIR_BACKWARD + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetSequenceScanDirection(ADC_Type *ADCx, uint32_t dir) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_SCANDIR_Msk, dir); +} + +/** + * @brief Get ADC Channel Scan Direction + * @rmtoll CFGR SCANDIR FL_ADC_GetSequenceScanDirection + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_SEQ_SCAN_DIR_FORWARD + * @arg @ref FL_ADC_SEQ_SCAN_DIR_BACKWARD + */ +__STATIC_INLINE uint32_t FL_ADC_GetSequenceScanDirection(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_SCANDIR_Msk)); +} + +/** + * @brief Set ADC Trigger Source + * @rmtoll CFGR EXTS FL_ADC_SetTriggerSource + * @param ADCx ADC instance + * @param source This parameter can be one of the following values: + * @arg @ref FL_ADC_TRGI_PA8 + * @arg @ref FL_ADC_TRGI_PB9 + * @arg @ref FL_ADC_TRGI_ATIM + * @arg @ref FL_ADC_TRGI_GPTIM0 + * @arg @ref FL_ADC_TRGI_GPTIM1 + * @arg @ref FL_ADC_TRGI_RTC + * @arg @ref FL_ADC_TRGI_BSTIM1 + * @arg @ref FL_ADC_TRGI_COMP1 + * @arg @ref FL_ADC_TRGI_COMP2 + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetTriggerSource(ADC_Type *ADCx, uint32_t source) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTS_Msk, source); +} + +/** + * @brief Get ADC Trigger Source + * @rmtoll CFGR EXTS FL_ADC_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_TRGI_PA8 + * @arg @ref FL_ADC_TRGI_PB9 + * @arg @ref FL_ADC_TRGI_ATIM + * @arg @ref FL_ADC_TRGI_GPTIM0 + * @arg @ref FL_ADC_TRGI_GPTIM1 + * @arg @ref FL_ADC_TRGI_RTC + * @arg @ref FL_ADC_TRGI_BSTIM1 + * @arg @ref FL_ADC_TRGI_COMP1 + * @arg @ref FL_ADC_TRGI_COMP2 + */ +__STATIC_INLINE uint32_t FL_ADC_GetTriggerSource(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTS_Msk)); +} + +/** + * @brief Enable ADC Overrun Mode + * @rmtoll CFGR OVRM FL_ADC_EnableOverrunMode + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_EnableOverrunMode(ADC_Type *ADCx) +{ + SET_BIT(ADCx->CFGR, ADC_CFGR_OVRM_Msk); +} + +/** + * @brief Disable ADC Overrun Mode + * @rmtoll CFGR OVRM FL_ADC_DisableOverrunMode + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_DisableOverrunMode(ADC_Type *ADCx) +{ + CLEAR_BIT(ADCx->CFGR, ADC_CFGR_OVRM_Msk); +} + +/** + * @brief Get ADC Overrun Mode Enable Status + * @rmtoll CFGR OVRM FL_ADC_IsEnabledOverrunMode + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsEnabledOverrunMode(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRM_Msk) == ADC_CFGR_OVRM_Msk); +} + +/** + * @brief Set ADC Conversion Mode + * @rmtoll CFGR CONT FL_ADC_SetConversionMode + * @param ADCx ADC instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_ADC_CONV_MODE_SINGLE + * @arg @ref FL_ADC_CONV_MODE_CONTINUOUS + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetConversionMode(ADC_Type *ADCx, uint32_t mode) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT_Msk, mode); +} + +/** + * @brief Get ADC Conversion Mode + * @rmtoll CFGR CONT FL_ADC_GetConversionMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_CONV_MODE_SINGLE + * @arg @ref FL_ADC_CONV_MODE_CONTINUOUS + */ +__STATIC_INLINE uint32_t FL_ADC_GetConversionMode(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT_Msk)); +} + +/** + * @brief Enable ADC Wait Mode + * @rmtoll CFGR WAIT FL_ADC_EnableWaitMode + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_EnableWaitMode(ADC_Type *ADCx) +{ + SET_BIT(ADCx->CFGR, ADC_CFGR_WAIT_Msk); +} + +/** + * @brief Disable ADC Wait Mode + * @rmtoll CFGR WAIT FL_ADC_DisableWaitMode + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_DisableWaitMode(ADC_Type *ADCx) +{ + CLEAR_BIT(ADCx->CFGR, ADC_CFGR_WAIT_Msk); +} + +/** + * @brief Get ADC Wait Mode Enable Status + * @rmtoll CFGR WAIT FL_ADC_IsEnabledWaitMode + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsEnabledWaitMode(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_WAIT_Msk) == ADC_CFGR_WAIT_Msk); +} + +/** + * @brief Set ADC Single Conversion Mode + * @rmtoll CFGR SEMI FL_ADC_SetSingleConversionAutoMode + * @param ADCx ADC instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_ADC_SINGLE_CONV_MODE_AUTO + * @arg @ref FL_ADC_SINGLE_CONV_MODE_SEMIAUTO + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetSingleConversionAutoMode(ADC_Type *ADCx, uint32_t mode) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_SEMI_Msk, mode); +} + +/** + * @brief Get ADC Single Conversion Mode + * @rmtoll CFGR SEMI FL_ADC_GetSingleConversionAutoMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_SINGLE_CONV_MODE_AUTO + * @arg @ref FL_ADC_SINGLE_CONV_MODE_SEMIAUTO + */ +__STATIC_INLINE uint32_t FL_ADC_GetSingleConversionAutoMode(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_SEMI_Msk)); +} + +/** + * @brief Set ADC Trigger Edge + * @rmtoll CFGR TRGCFG FL_ADC_SetTriggerEdge + * @param ADCx ADC instance + * @param edge This parameter can be one of the following values: + * @arg @ref FL_ADC_TRIGGER_EDGE_NONE + * @arg @ref FL_ADC_TRIGGER_EDGE_RISING + * @arg @ref FL_ADC_TRIGGER_EDGE_FALLING + * @arg @ref FL_ADC_TRIGGER_EDGE_BOTH + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetTriggerEdge(ADC_Type *ADCx, uint32_t edge) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_TRGCFG_Msk, edge); +} + +/** + * @brief Read ADC Trigger Edge + * @rmtoll CFGR TRGCFG FL_ADC_GetTriggerEdge + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_TRIGGER_EDGE_NONE + * @arg @ref FL_ADC_TRIGGER_EDGE_RISING + * @arg @ref FL_ADC_TRIGGER_EDGE_FALLING + * @arg @ref FL_ADC_TRIGGER_EDGE_BOTH + */ +__STATIC_INLINE uint32_t FL_ADC_GetTriggerEdge(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_TRGCFG_Msk)); +} + +/** + * @brief Enable ADC Trigger Filter + * @rmtoll CFGR IOTRFEN FL_ADC_EnableTriggerFilter + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_EnableTriggerFilter(ADC_Type *ADCx) +{ + SET_BIT(ADCx->CFGR, ADC_CFGR_IOTRFEN_Msk); +} + +/** + * @brief Disable ADC Trigger Filter + * @rmtoll CFGR IOTRFEN FL_ADC_DisableTriggerFilter + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_DisableTriggerFilter(ADC_Type *ADCx) +{ + CLEAR_BIT(ADCx->CFGR, ADC_CFGR_IOTRFEN_Msk); +} + +/** + * @brief Get ADC Trigger Filter Enable Status + * @rmtoll CFGR IOTRFEN FL_ADC_IsEnabledTriggerFilter + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsEnabledTriggerFilter(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_IOTRFEN_Msk) == ADC_CFGR_IOTRFEN_Msk); +} + +/** + * @brief Enable ADC OverSampling + * @rmtoll CFGR OVSEN FL_ADC_EnableOverSampling + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_EnableOverSampling(ADC_Type *ADCx) +{ + SET_BIT(ADCx->CFGR, ADC_CFGR_OVSEN_Msk); +} + +/** + * @brief Disable ADC OverSampling + * @rmtoll CFGR OVSEN FL_ADC_DisableOverSampling + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_DisableOverSampling(ADC_Type *ADCx) +{ + CLEAR_BIT(ADCx->CFGR, ADC_CFGR_OVSEN_Msk); +} + +/** + * @brief Get ADC OverSampling Enable Status + * @rmtoll CFGR OVSEN FL_ADC_IsEnabledOverSampling + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsEnabledOverSampling(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVSEN_Msk) == ADC_CFGR_OVSEN_Msk); +} + +/** + * @brief Set ADC OverSampling Multiplier + * @rmtoll CFGR OVSR FL_ADC_SetOverSamplingMultiplier + * @param ADCx ADC instance + * @param mul This parameter can be one of the following values: + * @arg @ref FL_ADC_OVERSAMPLING_MUL_2X + * @arg @ref FL_ADC_OVERSAMPLING_MUL_4X + * @arg @ref FL_ADC_OVERSAMPLING_MUL_8X + * @arg @ref FL_ADC_OVERSAMPLING_MUL_16X + * @arg @ref FL_ADC_OVERSAMPLING_MUL_32X + * @arg @ref FL_ADC_OVERSAMPLING_MUL_64X + * @arg @ref FL_ADC_OVERSAMPLING_MUL_128X + * @arg @ref FL_ADC_OVERSAMPLING_MUL_256X + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetOverSamplingMultiplier(ADC_Type *ADCx, uint32_t mul) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVSR_Msk, mul); +} + +/** + * @brief Read ADC OverSampling Multiplier + * @rmtoll CFGR OVSR FL_ADC_GetOverSamplingMultiplier + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_OVERSAMPLING_MUL_2X + * @arg @ref FL_ADC_OVERSAMPLING_MUL_4X + * @arg @ref FL_ADC_OVERSAMPLING_MUL_8X + * @arg @ref FL_ADC_OVERSAMPLING_MUL_16X + * @arg @ref FL_ADC_OVERSAMPLING_MUL_32X + * @arg @ref FL_ADC_OVERSAMPLING_MUL_64X + * @arg @ref FL_ADC_OVERSAMPLING_MUL_128X + * @arg @ref FL_ADC_OVERSAMPLING_MUL_256X + */ +__STATIC_INLINE uint32_t FL_ADC_GetOverSamplingMultiplier(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVSR_Msk)); +} + +/** + * @brief Set ADC OverSampling Shift + * @rmtoll CFGR OVSS FL_ADC_SetOverSamplingShift + * @param ADCx ADC instance + * @param shift This parameter can be one of the following values: + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_0B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_1B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_2B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_3B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_4B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_5B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_6B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_7B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_8B + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetOverSamplingShift(ADC_Type *ADCx, uint32_t shift) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVSS_Msk, shift); +} + +/** + * @brief Read ADC OverSampling Shift + * @rmtoll CFGR OVSS FL_ADC_GetOverSamplingShift + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_0B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_1B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_2B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_3B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_4B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_5B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_6B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_7B + * @arg @ref FL_ADC_OVERSAMPLING_SHIFT_8B + */ +__STATIC_INLINE uint32_t FL_ADC_GetOverSamplingShift(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVSS_Msk)); +} + +/** + * @brief Enable ADC Analog WDG + * @rmtoll CFGR AWDEN FL_ADC_EnableAnalogWDG + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_EnableAnalogWDG(ADC_Type *ADCx) +{ + SET_BIT(ADCx->CFGR, ADC_CFGR_AWDEN_Msk); +} + +/** + * @brief Disable ADC Analog WDG + * @rmtoll CFGR AWDEN FL_ADC_DisableAnalogWDG + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_DisableAnalogWDG(ADC_Type *ADCx) +{ + CLEAR_BIT(ADCx->CFGR, ADC_CFGR_AWDEN_Msk); +} + +/** + * @brief Get ADC Analog WDG Enable Status + * @rmtoll CFGR AWDEN FL_ADC_IsEnabledAnalogWDG + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsEnabledAnalogWDG(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AWDEN_Msk) == ADC_CFGR_AWDEN_Msk); +} + +/** + * @brief Set ADC Analog WDG Monitor Mode + * @rmtoll CFGR AWDSC FL_ADC_SetAnalogWDGMonitorMode + * @param ADCx ADC instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_ADC_AWDG_ALL_CHANNEL + * @arg @ref FL_ADC_AWDG_SINGLE_CHANNEL + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetAnalogWDGMonitorMode(ADC_Type *ADCx, uint32_t mode) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_AWDSC_Msk, mode); +} + +/** + * @brief Read ADC Analog WDG Monitor Mode + * @rmtoll CFGR AWDSC FL_ADC_GetAnalogWDGMonitorMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_AWDG_ALL_CHANNEL + * @arg @ref FL_ADC_AWDG_SINGLE_CHANNEL + */ +__STATIC_INLINE uint32_t FL_ADC_GetAnalogWDGMonitorMode(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AWDSC_Msk)); +} + +/** + * @brief Set ADC Analog WDG Monitor Channel + * @rmtoll CFGR AWDCH FL_ADC_SetAnalogWDGMonitorChannel + * @param ADCx ADC instance + * @param monitorChannel This parameter can be one of the following values: + * @arg @ref FL_ADC_AWDG_CH0 + * @arg @ref FL_ADC_AWDG_CH1 + * @arg @ref FL_ADC_AWDG_CH2 + * @arg @ref FL_ADC_AWDG_CH3 + * @arg @ref FL_ADC_AWDG_CH4 + * @arg @ref FL_ADC_AWDG_CH5 + * @arg @ref FL_ADC_AWDG_CH6 + * @arg @ref FL_ADC_AWDG_CH7 + * @arg @ref FL_ADC_AWDG_CH8 + * @arg @ref FL_ADC_AWDG_CH9 + * @arg @ref FL_ADC_AWDG_CH10 + * @arg @ref FL_ADC_AWDG_CH11 + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetAnalogWDGMonitorChannel(ADC_Type *ADCx, uint32_t monitorChannel) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_AWDCH_Msk, monitorChannel); +} + +/** + * @brief Read ADC Analog WDG Monitor Channel + * @rmtoll CFGR AWDCH FL_ADC_GetAnalogWDGMonitorChannel + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_AWDG_CH0 + * @arg @ref FL_ADC_AWDG_CH1 + * @arg @ref FL_ADC_AWDG_CH2 + * @arg @ref FL_ADC_AWDG_CH3 + * @arg @ref FL_ADC_AWDG_CH4 + * @arg @ref FL_ADC_AWDG_CH5 + * @arg @ref FL_ADC_AWDG_CH6 + * @arg @ref FL_ADC_AWDG_CH7 + * @arg @ref FL_ADC_AWDG_CH8 + * @arg @ref FL_ADC_AWDG_CH9 + * @arg @ref FL_ADC_AWDG_CH10 + * @arg @ref FL_ADC_AWDG_CH11 + */ +__STATIC_INLINE uint32_t FL_ADC_GetAnalogWDGMonitorChannel(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AWDCH_Msk)); +} + +/** + * @brief Set ADC Fast Channel Sampling Time + * @rmtoll SMTR SMTS1 FL_ADC_SetFastChannelSamplingTime + * @param ADCx ADC instance + * @param time This parameter can be one of the following values: + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_4_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_6_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_9_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_10_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_16_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_24_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_32_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_48_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_96_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_128_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_192_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_256_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_384_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_SOFTWARE_CONTROL + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetFastChannelSamplingTime(ADC_Type *ADCx, uint32_t time) +{ + MODIFY_REG(ADCx->SMTR, ADC_SMTR_SMTS1_Msk, time); +} + +/** + * @brief Read ADC Fast Channel Sampling Time + * @rmtoll SMTR SMTS1 FL_ADC_GetFastChannelSamplingTime + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_4_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_6_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_9_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_10_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_16_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_24_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_32_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_48_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_96_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_128_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_192_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_256_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_384_ADCCLK + * @arg @ref FL_ADC_FAST_CH_SAMPLING_TIME_SOFTWARE_CONTROL + */ +__STATIC_INLINE uint32_t FL_ADC_GetFastChannelSamplingTime(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->SMTR, ADC_SMTR_SMTS1_Msk)); +} + +/** + * @brief Set ADC Slow Channel Sampling Time + * @rmtoll SMTR SMTS2 FL_ADC_SetSlowChannelSamplingTime + * @param ADCx ADC instance + * @param time This parameter can be one of the following values: + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_4_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_6_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_9_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_10_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_16_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_24_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_32_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_48_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_96_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_128_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_192_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_256_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_384_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_SOFTWARE_CONTROL + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetSlowChannelSamplingTime(ADC_Type *ADCx, uint32_t time) +{ + MODIFY_REG(ADCx->SMTR, ADC_SMTR_SMTS2_Msk, time); +} + +/** + * @brief Read ADC Slow Channel Sampling Time + * @rmtoll SMTR SMTS2 FL_ADC_GetSlowChannelSamplingTime + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_4_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_6_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_9_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_10_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_16_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_24_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_32_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_48_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_96_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_128_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_192_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_256_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_384_ADCCLK + * @arg @ref FL_ADC_SLOW_CH_SAMPLING_TIME_SOFTWARE_CONTROL + */ +__STATIC_INLINE uint32_t FL_ADC_GetSlowChannelSamplingTime(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->SMTR, ADC_SMTR_SMTS2_Msk)); +} + +/** + * @brief Set ADC Sampling Interval + * @rmtoll SMTR CHCG FL_ADC_SetSamplingInterval + * @param ADCx ADC instance + * @param interval This parameter can be one of the following values: + * @arg @ref FL_ADC_SAMPLING_INTERVAL_2_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_3_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_4_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_5_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_6_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_7_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_8_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_9_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_10_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_11_CYCLE + * @retval None + */ +__STATIC_INLINE void FL_ADC_SetSamplingInterval(ADC_Type *ADCx, uint32_t interval) +{ + MODIFY_REG(ADCx->SMTR, ADC_SMTR_CHCG_Msk, interval); +} + +/** + * @brief Read ADC Sampling Interval + * @rmtoll SMTR CHCG FL_ADC_GetSamplingInterval + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ADC_SAMPLING_INTERVAL_2_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_3_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_4_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_5_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_6_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_7_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_8_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_9_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_10_CYCLE + * @arg @ref FL_ADC_SAMPLING_INTERVAL_11_CYCLE + */ +__STATIC_INLINE uint32_t FL_ADC_GetSamplingInterval(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->SMTR, ADC_SMTR_CHCG_Msk)); +} + +/** + * @brief Enable ADC Channel + * @rmtoll CHER FL_ADC_EnableSequencerChannel + * @param ADCx ADC instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ADC_EXTERNAL_CH0 + * @arg @ref FL_ADC_EXTERNAL_CH1 + * @arg @ref FL_ADC_EXTERNAL_CH2 + * @arg @ref FL_ADC_EXTERNAL_CH3 + * @arg @ref FL_ADC_EXTERNAL_CH4 + * @arg @ref FL_ADC_EXTERNAL_CH5 + * @arg @ref FL_ADC_EXTERNAL_CH6 + * @arg @ref FL_ADC_EXTERNAL_CH7 + * @arg @ref FL_ADC_EXTERNAL_CH8 + * @arg @ref FL_ADC_EXTERNAL_CH9 + * @arg @ref FL_ADC_EXTERNAL_CH10 + * @arg @ref FL_ADC_EXTERNAL_CH11 + * @arg @ref FL_ADC_INTERNAL_TS + * @arg @ref FL_ADC_INTERNAL_VREF1P2 + * @arg @ref FL_ADC_INTERNAL_OPA1 + * @arg @ref FL_ADC_INTERNAL_OPA2 + * @retval None + */ +__STATIC_INLINE void FL_ADC_EnableSequencerChannel(ADC_Type *ADCx, uint32_t channel) +{ + SET_BIT(ADCx->CHER, ((channel & 0xfffff) << 0x0U)); +} + +/** + * @brief Disable ADC Channel + * @rmtoll CHER FL_ADC_DisableSequencerChannel + * @param ADCx ADC instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ADC_EXTERNAL_CH0 + * @arg @ref FL_ADC_EXTERNAL_CH1 + * @arg @ref FL_ADC_EXTERNAL_CH2 + * @arg @ref FL_ADC_EXTERNAL_CH3 + * @arg @ref FL_ADC_EXTERNAL_CH4 + * @arg @ref FL_ADC_EXTERNAL_CH5 + * @arg @ref FL_ADC_EXTERNAL_CH6 + * @arg @ref FL_ADC_EXTERNAL_CH7 + * @arg @ref FL_ADC_EXTERNAL_CH8 + * @arg @ref FL_ADC_EXTERNAL_CH9 + * @arg @ref FL_ADC_EXTERNAL_CH10 + * @arg @ref FL_ADC_EXTERNAL_CH11 + * @arg @ref FL_ADC_INTERNAL_TS + * @arg @ref FL_ADC_INTERNAL_VREF1P2 + * @arg @ref FL_ADC_INTERNAL_OPA1 + * @arg @ref FL_ADC_INTERNAL_OPA2 + * @retval None + */ +__STATIC_INLINE void FL_ADC_DisableSequencerChannel(ADC_Type *ADCx, uint32_t channel) +{ + CLEAR_BIT(ADCx->CHER, ((channel & 0xfffff) << 0x0U)); +} + +/** + * @brief Get ADC Channel Enable Status + * @rmtoll CHER FL_ADC_IsEnabledSequencerChannel + * @param ADCx ADC instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ADC_EXTERNAL_CH0 + * @arg @ref FL_ADC_EXTERNAL_CH1 + * @arg @ref FL_ADC_EXTERNAL_CH2 + * @arg @ref FL_ADC_EXTERNAL_CH3 + * @arg @ref FL_ADC_EXTERNAL_CH4 + * @arg @ref FL_ADC_EXTERNAL_CH5 + * @arg @ref FL_ADC_EXTERNAL_CH6 + * @arg @ref FL_ADC_EXTERNAL_CH7 + * @arg @ref FL_ADC_EXTERNAL_CH8 + * @arg @ref FL_ADC_EXTERNAL_CH9 + * @arg @ref FL_ADC_EXTERNAL_CH10 + * @arg @ref FL_ADC_EXTERNAL_CH11 + * @arg @ref FL_ADC_INTERNAL_TS + * @arg @ref FL_ADC_INTERNAL_VREF1P2 + * @arg @ref FL_ADC_INTERNAL_OPA1 + * @arg @ref FL_ADC_INTERNAL_OPA2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ADC_IsEnabledSequencerChannel(ADC_Type *ADCx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(ADCx->CHER, ((channel & 0xfffff) << 0x0U)) == ((channel & 0xfffff) << 0x0U)); +} + +/** + * @brief Get ADC Conversion Data + * @rmtoll DR FL_ADC_ReadConversionData + * @param ADCx ADC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_ADC_ReadConversionData(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->DR, 0xffffU) >> 0U); +} + +/** + * @brief Enable ADC Stop Sampling + * @rmtoll SAMPT SAMPT_S FL_ADC_SWStopSampling + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void FL_ADC_SWStopSampling(ADC_Type *ADCx) +{ + SET_BIT(ADCx->SAMPT, ADC_SAMPT_SAMPT_S_Msk); +} + +/** + * @brief Write ADC Analog Watchdog Under Low + * @rmtoll HLTR AWD_LT FL_ADC_WriteAnalogWDGLowThreshold + * @param ADCx ADC instance + * @param threshold + * @retval None + */ +__STATIC_INLINE void FL_ADC_WriteAnalogWDGLowThreshold(ADC_Type *ADCx, uint32_t threshold) +{ + MODIFY_REG(ADCx->HLTR, (0xfffU << 0U), (threshold << 0U)); +} + +/** + * @brief Read ADC Analog Watchdog Under Low + * @rmtoll HLTR AWD_LT FL_ADC_ReadAnalogWDGLowThreshold + * @param ADCx ADC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_ADC_ReadAnalogWDGLowThreshold(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->HLTR, 0xfffU) >> 0U); +} + +/** + * @brief Write ADC Analog Watchdog Above High + * @rmtoll HLTR AWD_HT FL_ADC_WriteAnalogWDGHighThreshold + * @param ADCx ADC instance + * @param threshold + * @retval None + */ +__STATIC_INLINE void FL_ADC_WriteAnalogWDGHighThreshold(ADC_Type *ADCx, uint32_t threshold) +{ + MODIFY_REG(ADCx->HLTR, (0xfffU << 16U), (threshold << 16U)); +} + +/** + * @brief Read ADC Analog Watchdog Above High + * @rmtoll HLTR AWD_HT FL_ADC_ReadAnalogWDGHighThreshold + * @param ADCx ADC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_ADC_ReadAnalogWDGHighThreshold(ADC_Type *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->HLTR, 0xfffU) >> 16U); +} + +/** + * @} + */ + +/** @defgroup ADC_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_ADC_CommonDeInit(void); +FL_ErrorStatus FL_ADC_DeInit(ADC_Type *ADCx); +void FL_ADC_StructInit(FL_ADC_InitTypeDef *ADC_InitStruct); +FL_ErrorStatus FL_ADC_Init(ADC_Type *ADCx, FL_ADC_InitTypeDef *ADC_InitStruct); +void FL_ADC_CommonStructInit(FL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); +FL_ErrorStatus FL_ADC_CommonInit(FL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_ADC_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_aes.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_aes.h new file mode 100644 index 0000000000..b0a6e38357 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_aes.h @@ -0,0 +1,701 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_aes.h + * @author FMSH Application Team + * @brief Head file of AES FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_AES_H +#define __FM33LC0XX_FL_AES_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup AES AES + * @brief AES FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup AES_FL_ES_INIT AES Exported Init structures + * @{ + */ + +/** + * @brief FL AES Init Sturcture definition + */ +typedef struct +{ + /** 秘钥长度 */ + uint32_t keyLength; + + /** 数据流处理模式 */ + uint32_t cipherMode; + + /** AES工作模式 */ + uint32_t operationMode; + + /** 输入数据类型 */ + uint32_t dataType; + +} FL_AES_InitTypeDef; + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup AES_FL_Exported_Constants AES Exported Constants + * @{ + */ + +#define AES_CR_KEYLEN_Pos (13U) +#define AES_CR_KEYLEN_Msk (0x3U << AES_CR_KEYLEN_Pos) +#define AES_CR_KEYLEN AES_CR_KEYLEN_Msk + +#define AES_CR_DMAOEN_Pos (12U) +#define AES_CR_DMAOEN_Msk (0x1U << AES_CR_DMAOEN_Pos) +#define AES_CR_DMAOEN AES_CR_DMAOEN_Msk + +#define AES_CR_DMAIEN_Pos (11U) +#define AES_CR_DMAIEN_Msk (0x1U << AES_CR_DMAIEN_Pos) +#define AES_CR_DMAIEN AES_CR_DMAIEN_Msk + +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x3U << AES_CR_CHMOD_Pos) +#define AES_CR_CHMOD AES_CR_CHMOD_Msk + +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3U << AES_CR_MODE_Pos) +#define AES_CR_MODE AES_CR_MODE_Msk + +#define AES_CR_DATATYP_Pos (1U) +#define AES_CR_DATATYP_Msk (0x3U << AES_CR_DATATYP_Pos) +#define AES_CR_DATATYP AES_CR_DATATYP_Msk + +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1U << AES_CR_EN_Pos) +#define AES_CR_EN AES_CR_EN_Msk + +#define AES_IER_WRERR_IE_Pos (2U) +#define AES_IER_WRERR_IE_Msk (0x1U << AES_IER_WRERR_IE_Pos) +#define AES_IER_WRERR_IE AES_IER_WRERR_IE_Msk + +#define AES_IER_RDERR_IE_Pos (1U) +#define AES_IER_RDERR_IE_Msk (0x1U << AES_IER_RDERR_IE_Pos) +#define AES_IER_RDERR_IE AES_IER_RDERR_IE_Msk + +#define AES_IER_CCF_IE_Pos (0U) +#define AES_IER_CCF_IE_Msk (0x1U << AES_IER_CCF_IE_Pos) +#define AES_IER_CCF_IE AES_IER_CCF_IE_Msk + +#define AES_ISR_WRERR_Pos (2U) +#define AES_ISR_WRERR_Msk (0x1U << AES_ISR_WRERR_Pos) +#define AES_ISR_WRERR AES_ISR_WRERR_Msk + +#define AES_ISR_RDERR_Pos (1U) +#define AES_ISR_RDERR_Msk (0x1U << AES_ISR_RDERR_Pos) +#define AES_ISR_RDERR AES_ISR_RDERR_Msk + +#define AES_ISR_CCF_Pos (0U) +#define AES_ISR_CCF_Msk (0x1U << AES_ISR_CCF_Pos) +#define AES_ISR_CCF AES_ISR_CCF_Msk + + + +#define FL_AES_KEY0_OFFSET (0x0U << 0U) +#define FL_AES_KEY1_OFFSET (0x1U << 0U) +#define FL_AES_KEY2_OFFSET (0x2U << 0U) +#define FL_AES_KEY3_OFFSET (0x3U << 0U) +#define FL_AES_KEY4_OFFSET (0x4U << 0U) +#define FL_AES_KEY5_OFFSET (0x5U << 0U) +#define FL_AES_KEY6_OFFSET (0x6U << 0U) +#define FL_AES_KEY7_OFFSET (0x7U << 0U) +#define FL_AES_IVR0_OFFSET (0x0U << 0U) +#define FL_AES_IVR1_OFFSET (0x1U << 0U) +#define FL_AES_IVR2_OFFSET (0x2U << 0U) +#define FL_AES_IVR3_OFFSET (0x3U << 0U) +#define FL_AES_H0_OFFSET (0x0U << 0U) +#define FL_AES_H1_OFFSET (0x1U << 0U) +#define FL_AES_H2_OFFSET (0x2U << 0U) +#define FL_AES_H3_OFFSET (0x3U << 0U) + + + +#define FL_AES_KEY_LENGTH_128B (0x0U << AES_CR_KEYLEN_Pos) +#define FL_AES_KEY_LENGTH_192B (0x1U << AES_CR_KEYLEN_Pos) +#define FL_AES_KEY_LENGTH_256B (0x2U << AES_CR_KEYLEN_Pos) + + +#define FL_AES_CIPHER_ECB (0x0U << AES_CR_CHMOD_Pos) +#define FL_AES_CIPHER_CBC (0x1U << AES_CR_CHMOD_Pos) +#define FL_AES_CIPHER_CTR (0x2U << AES_CR_CHMOD_Pos) +#define FL_AES_CIPHER_MULTH (0x3U << AES_CR_CHMOD_Pos) + + +#define FL_AES_OPERATION_MODE_ENCRYPTION (0x0U << AES_CR_MODE_Pos) +#define FL_AES_OPERATION_MODE_KEYDERIVATION (0x1U << AES_CR_MODE_Pos) +#define FL_AES_OPERATION_MODE_DECRYPTION (0x2U << AES_CR_MODE_Pos) +#define FL_AES_OPERATION_MODE_KEYDERIVATION_DECRYPTION (0x3U << AES_CR_MODE_Pos) + + +#define FL_AES_DATA_TYPE_32B (0x0U << AES_CR_DATATYP_Pos) +#define FL_AES_DATA_TYPE_16B (0x1U << AES_CR_DATATYP_Pos) +#define FL_AES_DATA_TYPE_8B (0x2U << AES_CR_DATATYP_Pos) +#define FL_AES_DATA_TYPE_1B (0x3U << AES_CR_DATATYP_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup AES_FL_Exported_Functions AES Exported Functions + * @{ + */ + +/** + * @brief Set key size selection + * @rmtoll CR KEYLEN FL_AES_SetKeySize + * @param AESx AES instance + * @param keySize This parameter can be one of the following values: + * @arg @ref FL_AES_KEY_LENGTH_128B + * @arg @ref FL_AES_KEY_LENGTH_192B + * @arg @ref FL_AES_KEY_LENGTH_256B + * @retval None + */ +__STATIC_INLINE void FL_AES_SetKeySize(AES_Type *AESx, uint32_t keySize) +{ + MODIFY_REG(AESx->CR, AES_CR_KEYLEN_Msk, keySize); +} + +/** + * @brief Get key size selection + * @rmtoll CR KEYLEN FL_AES_GetKeySize + * @param AESx AES instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_AES_KEY_LENGTH_128B + * @arg @ref FL_AES_KEY_LENGTH_192B + * @arg @ref FL_AES_KEY_LENGTH_256B + */ +__STATIC_INLINE uint32_t FL_AES_GetKeySize(AES_Type *AESx) +{ + return (uint32_t)(READ_BIT(AESx->CR, AES_CR_KEYLEN_Msk)); +} + +/** + * @brief DMA output enable + * @rmtoll CR DMAOEN FL_AES_EnableDMAReq_Output + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_EnableDMAReq_Output(AES_Type *AESx) +{ + SET_BIT(AESx->CR, AES_CR_DMAOEN_Msk); +} + +/** + * @brief DMA output disable + * @rmtoll CR DMAOEN FL_AES_DisableDMAReq_Output + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_DisableDMAReq_Output(AES_Type *AESx) +{ + CLEAR_BIT(AESx->CR, AES_CR_DMAOEN_Msk); +} + +/** + * @brief DMA input enable + * @rmtoll CR DMAIEN FL_AES_EnableDMAReq_Input + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_EnableDMAReq_Input(AES_Type *AESx) +{ + SET_BIT(AESx->CR, AES_CR_DMAIEN_Msk); +} + +/** + * @brief DMA input disable + * @rmtoll CR DMAIEN FL_AES_DisableDMAReq_Input + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_DisableDMAReq_Input(AES_Type *AESx) +{ + CLEAR_BIT(AESx->CR, AES_CR_DMAIEN_Msk); +} + +/** + * @brief Set cipher mode + * @rmtoll CR CHMOD FL_AES_SetCipherMode + * @param AESx AES instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_AES_CIPHER_ECB + * @arg @ref FL_AES_CIPHER_CBC + * @arg @ref FL_AES_CIPHER_CTR + * @arg @ref FL_AES_CIPHER_MULTH + * @retval None + */ +__STATIC_INLINE void FL_AES_SetCipherMode(AES_Type *AESx, uint32_t mode) +{ + MODIFY_REG(AESx->CR, AES_CR_CHMOD_Msk, mode); +} + +/** + * @brief Get cipher mode + * @rmtoll CR CHMOD FL_AES_GetCipherMode + * @param AESx AES instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_AES_CIPHER_ECB + * @arg @ref FL_AES_CIPHER_CBC + * @arg @ref FL_AES_CIPHER_CTR + * @arg @ref FL_AES_CIPHER_MULTH + */ +__STATIC_INLINE uint32_t FL_AES_GetCipherMode(AES_Type *AESx) +{ + return (uint32_t)(READ_BIT(AESx->CR, AES_CR_CHMOD_Msk)); +} + +/** + * @brief Set operation mode + * @rmtoll CR MODE FL_AES_SetOperationMode + * @param AESx AES instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_AES_OPERATION_MODE_ENCRYPTION + * @arg @ref FL_AES_OPERATION_MODE_KEYDERIVATION + * @arg @ref FL_AES_OPERATION_MODE_DECRYPTION + * @arg @ref FL_AES_OPERATION_MODE_KEYDERIVATION_DECRYPTION + * @retval None + */ +__STATIC_INLINE void FL_AES_SetOperationMode(AES_Type *AESx, uint32_t mode) +{ + MODIFY_REG(AESx->CR, AES_CR_MODE_Msk, mode); +} + +/** + * @brief Get operation mode + * @rmtoll CR MODE FL_AES_GetOperationMode + * @param AESx AES instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_AES_OPERATION_MODE_ENCRYPTION + * @arg @ref FL_AES_OPERATION_MODE_KEYDERIVATION + * @arg @ref FL_AES_OPERATION_MODE_DECRYPTION + * @arg @ref FL_AES_OPERATION_MODE_KEYDERIVATION_DECRYPTION + */ +__STATIC_INLINE uint32_t FL_AES_GetOperationMode(AES_Type *AESx) +{ + return (uint32_t)(READ_BIT(AESx->CR, AES_CR_MODE_Msk)); +} + +/** + * @brief Set data type selection + * @rmtoll CR DATATYP FL_AES_SetDataType + * @param AESx AES instance + * @param rule This parameter can be one of the following values: + * @arg @ref FL_AES_DATA_TYPE_32B + * @arg @ref FL_AES_DATA_TYPE_16B + * @arg @ref FL_AES_DATA_TYPE_8B + * @arg @ref FL_AES_DATA_TYPE_1B + * @retval None + */ +__STATIC_INLINE void FL_AES_SetDataType(AES_Type *AESx, uint32_t rule) +{ + MODIFY_REG(AESx->CR, AES_CR_DATATYP_Msk, rule); +} + +/** + * @brief Get data type selection + * @rmtoll CR DATATYP FL_AES_GetDataType + * @param AESx AES instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_AES_DATA_TYPE_32B + * @arg @ref FL_AES_DATA_TYPE_16B + * @arg @ref FL_AES_DATA_TYPE_8B + * @arg @ref FL_AES_DATA_TYPE_1B + */ +__STATIC_INLINE uint32_t FL_AES_GetDataType(AES_Type *AESx) +{ + return (uint32_t)(READ_BIT(AESx->CR, AES_CR_DATATYP_Msk)); +} + +/** + * @brief AES enable + * @rmtoll CR EN FL_AES_Enable + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_Enable(AES_Type *AESx) +{ + SET_BIT(AESx->CR, AES_CR_EN_Msk); +} + +/** + * @brief Get AES enable status + * @rmtoll CR EN FL_AES_IsEnabled + * @param AESx AES instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_AES_IsEnabled(AES_Type *AESx) +{ + return (uint32_t)(READ_BIT(AESx->CR, AES_CR_EN_Msk) == AES_CR_EN_Msk); +} + +/** + * @brief AES disable + * @rmtoll CR EN FL_AES_Disable + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_Disable(AES_Type *AESx) +{ + CLEAR_BIT(AESx->CR, AES_CR_EN_Msk); +} + +/** + * @brief Write error interrupt enable + * @rmtoll IER WRERR_IE FL_AES_EnableIT_WriteError + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_EnableIT_WriteError(AES_Type *AESx) +{ + SET_BIT(AESx->IER, AES_IER_WRERR_IE_Msk); +} + +/** + * @brief Get write error interrupt enable status + * @rmtoll IER WRERR_IE FL_AES_IsEnabledIT_WriteError + * @param AESx AES instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_AES_IsEnabledIT_WriteError(AES_Type *AESx) +{ + return (uint32_t)(READ_BIT(AESx->IER, AES_IER_WRERR_IE_Msk) == AES_IER_WRERR_IE_Msk); +} + +/** + * @brief Write error interrupt disable + * @rmtoll IER WRERR_IE FL_AES_DisableIT_WriteError + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_DisableIT_WriteError(AES_Type *AESx) +{ + CLEAR_BIT(AESx->IER, AES_IER_WRERR_IE_Msk); +} + +/** + * @brief Read error interrupt enable + * @rmtoll IER RDERR_IE FL_AES_EnableIT_ReadError + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_EnableIT_ReadError(AES_Type *AESx) +{ + SET_BIT(AESx->IER, AES_IER_RDERR_IE_Msk); +} + +/** + * @brief Get read Error interrupt enable status + * @rmtoll IER RDERR_IE FL_AES_IsEnabledIT_ReadError + * @param AESx AES instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_AES_IsEnabledIT_ReadError(AES_Type *AESx) +{ + return (uint32_t)(READ_BIT(AESx->IER, AES_IER_RDERR_IE_Msk) == AES_IER_RDERR_IE_Msk); +} + +/** + * @brief Read error interrupt disable + * @rmtoll IER RDERR_IE FL_AES_DisableIT_ReadError + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_DisableIT_ReadError(AES_Type *AESx) +{ + CLEAR_BIT(AESx->IER, AES_IER_RDERR_IE_Msk); +} + +/** + * @brief Cipher complete interrupt enable + * @rmtoll IER CCF_IE FL_AES_EnableIT_Complete + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_EnableIT_Complete(AES_Type *AESx) +{ + SET_BIT(AESx->IER, AES_IER_CCF_IE_Msk); +} + +/** + * @brief Get cipher complete interrupt enable status + * @rmtoll IER CCF_IE FL_AES_IsEnabledIT_Complete + * @param AESx AES instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_AES_IsEnabledIT_Complete(AES_Type *AESx) +{ + return (uint32_t)(READ_BIT(AESx->IER, AES_IER_CCF_IE_Msk) == AES_IER_CCF_IE_Msk); +} + +/** + * @brief Cipher complete interrupt disable + * @rmtoll IER CCF_IE FL_AES_DisableIT_Complete + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_DisableIT_Complete(AES_Type *AESx) +{ + CLEAR_BIT(AESx->IER, AES_IER_CCF_IE_Msk); +} + +/** + * @brief Get write error flag + * @rmtoll ISR WRERR FL_AES_IsActiveFlag_WriteError + * @param AESx AES instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_AES_IsActiveFlag_WriteError(AES_Type *AESx) +{ + return (uint32_t)(READ_BIT(AESx->ISR, AES_ISR_WRERR_Msk) == (AES_ISR_WRERR_Msk)); +} + +/** + * @brief Clear write error flag + * @rmtoll ISR WRERR FL_AES_ClearFlag_WriteError + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_ClearFlag_WriteError(AES_Type *AESx) +{ + WRITE_REG(AESx->ISR, AES_ISR_WRERR_Msk); +} + +/** + * @brief Get read error flag + * @rmtoll ISR RDERR FL_AES_IsActiveFlag_ReadError + * @param AESx AES instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_AES_IsActiveFlag_ReadError(AES_Type *AESx) +{ + return (uint32_t)(READ_BIT(AESx->ISR, AES_ISR_RDERR_Msk) == (AES_ISR_RDERR_Msk)); +} + +/** + * @brief Clear read error flag + * @rmtoll ISR RDERR FL_AES_ClearFlag_ReadError + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_ClearFlag_ReadError(AES_Type *AESx) +{ + WRITE_REG(AESx->ISR, AES_ISR_RDERR_Msk); +} + +/** + * @brief Get cipher complete flag + * @rmtoll ISR CCF FL_AES_IsActiveFlag_Complete + * @param AESx AES instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_AES_IsActiveFlag_Complete(AES_Type *AESx) +{ + return (uint32_t)(READ_BIT(AESx->ISR, AES_ISR_CCF_Msk) == (AES_ISR_CCF_Msk)); +} + +/** + * @brief Clear cipher complete flag + * @rmtoll ISR CCF FL_AES_ClearFlag_Complete + * @param AESx AES instance + * @retval None + */ +__STATIC_INLINE void FL_AES_ClearFlag_Complete(AES_Type *AESx) +{ + WRITE_REG(AESx->ISR, AES_ISR_CCF_Msk); +} + +/** + * @brief Write AES data input register + * @rmtoll DIR FL_AES_WriteInputData + * @param AESx AES instance + * @param data + * @retval None + */ +__STATIC_INLINE void FL_AES_WriteInputData(AES_Type *AESx, uint32_t data) +{ + MODIFY_REG(AESx->DIR, (0xffffffffU << 0U), (data << 0U)); +} + +/** + * @brief Read AES data output register + * @rmtoll DOR FL_AES_ReadOutputData + * @param AESx AES instance + * @retval + */ +__STATIC_INLINE uint32_t FL_AES_ReadOutputData(AES_Type *AESx) +{ + return (uint32_t)(READ_BIT(AESx->DOR, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @brief Set key registers + * @rmtoll KEY0 FL_AES_WriteKeys + * @param AESx AES instance + * @param offset This parameter can be one of the following values: + * @arg @ref FL_AES_KEY0_OFFSET + * @arg @ref FL_AES_KEY1_OFFSET + * @arg @ref FL_AES_KEY2_OFFSET + * @arg @ref FL_AES_KEY3_OFFSET + * @arg @ref FL_AES_KEY4_OFFSET + * @arg @ref FL_AES_KEY5_OFFSET + * @arg @ref FL_AES_KEY6_OFFSET + * @arg @ref FL_AES_KEY7_OFFSET + * @param data + * @retval None + */ +__STATIC_INLINE void FL_AES_WriteKeys(AES_Type *AESx, uint32_t offset, uint32_t data) +{ + WRITE_REG(*(((uint32_t *)&AESx->KEY0) + offset), data); +} + +/** + * @brief Get key registers + * @rmtoll KEY0 FL_AES_ReadKeys + * @param AESx AES instance + * @param offset This parameter can be one of the following values: + * @arg @ref FL_AES_KEY0_OFFSET + * @arg @ref FL_AES_KEY1_OFFSET + * @arg @ref FL_AES_KEY2_OFFSET + * @arg @ref FL_AES_KEY3_OFFSET + * @arg @ref FL_AES_KEY4_OFFSET + * @arg @ref FL_AES_KEY5_OFFSET + * @arg @ref FL_AES_KEY6_OFFSET + * @arg @ref FL_AES_KEY7_OFFSET + * @retval + */ +__STATIC_INLINE uint32_t FL_AES_ReadKeys(AES_Type *AESx, uint32_t offset) +{ + return (uint32_t)READ_REG(*(((uint32_t *)&AESx->KEY0) + offset)); +} + +/** + * @brief Write initialization vector registers + * @rmtoll DIR FL_AES_WriteIVR + * @param AESx AES instance + * @param offset This parameter can be one of the following values: + * @arg @ref FL_AES_IVR0_OFFSET + * @arg @ref FL_AES_IVR1_OFFSET + * @arg @ref FL_AES_IVR2_OFFSET + * @arg @ref FL_AES_IVR3_OFFSET + * @param data + * @retval None + */ +__STATIC_INLINE void FL_AES_WriteIVR(AES_Type *AESx, uint32_t offset, uint32_t data) +{ + WRITE_REG(*(((uint32_t *)&AESx->IVR0) + offset), data); +} + +/** + * @brief Read initialization vector registers + * @rmtoll DOR FL_AES_ReadIVR + * @param AESx AES instance + * @param offset This parameter can be one of the following values: + * @arg @ref FL_AES_IVR0_OFFSET + * @arg @ref FL_AES_IVR1_OFFSET + * @arg @ref FL_AES_IVR2_OFFSET + * @arg @ref FL_AES_IVR3_OFFSET + * @retval + */ +__STATIC_INLINE uint32_t FL_AES_ReadIVR(AES_Type *AESx, uint32_t offset) +{ + return (uint32_t)READ_REG(*(((uint32_t *)&AESx->IVR0) + offset)); +} + +/** + * @brief Set AES MultH parameter Register + * @rmtoll KEY0 FL_AES_WriteHParams + * @param AESx AES instance + * @param offset This parameter can be one of the following values: + * @arg @ref FL_AES_H0_OFFSET + * @arg @ref FL_AES_H1_OFFSET + * @arg @ref FL_AES_H2_OFFSET + * @arg @ref FL_AES_H3_OFFSET + * @param data + * @retval None + */ +__STATIC_INLINE void FL_AES_WriteHParams(AES_Type *AESx, uint32_t offset, uint32_t data) +{ + WRITE_REG(*(((uint32_t *)&AESx->KEY0) + offset), data); +} + +/** + * @brief Get AES MultH parameter Register + * @rmtoll KEY0 FL_AES_ReadHParams + * @param AESx AES instance + * @param offset This parameter can be one of the following values: + * @arg @ref FL_AES_H0_OFFSET + * @arg @ref FL_AES_H1_OFFSET + * @arg @ref FL_AES_H2_OFFSET + * @arg @ref FL_AES_H3_OFFSET + * @retval + */ +__STATIC_INLINE uint32_t FL_AES_ReadHParams(AES_Type *AESx, uint32_t offset) +{ + return (uint32_t)READ_REG(*(((uint32_t *)&AESx->KEY0) + offset)); +} + +/** + * @} + */ + +/** @defgroup AES_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_AES_DeInit(void); +void FL_AES_StructInit(FL_AES_InitTypeDef *AES_InitStructer); +FL_ErrorStatus FL_AES_Init(AES_Type *AESx, FL_AES_InitTypeDef *AES_InitStructer); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_AES_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_atim.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_atim.h new file mode 100644 index 0000000000..29a68ed35f --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_atim.h @@ -0,0 +1,3790 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_atim.h + * @author FMSH Application Team + * @brief Head file of ATIM FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_ATIM_H +#define __FM33LC0XX_FL_ATIM_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup ATIM ATIM + * @brief ATIM FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup ATIM_FL_ES_INIT ATIM Exported Init structures + * @{ + */ + +/** + * @brief ATIM Init Sturcture Definition + */ +typedef struct +{ + /** 时钟源选择 */ + uint32_t clockSource; + + /** 预分频系数 */ + uint32_t prescaler; + + /** 计数模式 */ + uint32_t counterMode; + + /** 自动重装载值 */ + uint32_t autoReload; + + /** 预装载使能 */ + uint32_t autoReloadState; + + /** 定时器分频系数与数字滤波器所使用的采样时钟分频比 */ + uint32_t clockDivision; + + /** 重复计数次数 */ + uint32_t repetitionCounter; + +} FL_ATIM_InitTypeDef; + +/** + * @brief ATIM Slave Init Sturcture Definition + */ +typedef struct +{ + + /** 外部时钟源模式 */ + uint32_t slaveMode; + + /** 输入触发信号选择 */ + uint32_t triggerSrc; + + /** Trigger 延迟*/ + uint32_t triggerDelay; + +} FL_ATIM_SlaveInitTypeDef; + +/** + * @brief ATIM ETR Init Structure Definition + */ +typedef struct +{ + /** 外部触发使能 */ + uint32_t useExternalTrigger; + + /** 外部时钟滤波 */ + uint32_t ETRFilter; + + /** 外部时钟分频 */ + uint32_t ETRClockDivision; + + /** 外部时钟触发极性 */ + uint32_t ETRPolarity; + +} FL_ATIM_ETR_InitTypeDef; + +/** + * @brief TIM Output Compare Init Structure Definition + */ +typedef struct +{ + /** 比较输出模式 */ + uint32_t OCMode; + + /** 比较正向通道输出使能 */ + uint32_t OCState; + + /** 比较互补通道输出使能 */ + uint32_t OCNState; + + /** 比较输出极性 */ + uint32_t OCPolarity; + + /** 比较互补输出极性 */ + uint32_t OCNPolarity; + + /** 比较输出通道快速模式使能 */ + uint32_t OCFastMode; + + /** 输出比较预装载 */ + uint32_t OCPreload; + + /** 通道比较值 */ + uint32_t compareValue; + + /** 输出空闲状态电平 */ + uint32_t OCIdleState; + + /** ETR清0使能 */ + uint32_t OCETRFStatus; + + /** 互补输出空闲状态电平 */ + uint32_t OCNIdleState; + +} FL_ATIM_OC_InitTypeDef; + +/** + * @brief TIM Input Capture Init Structure Definition + */ +typedef struct +{ + /** 输入捕获使能 */ + uint32_t captureState; + + /** 输入捕获极性 */ + uint32_t ICPolarity; + + /** 通道映射激活的输入选择 */ + uint32_t ICActiveInput; + + /** 输入分频 */ + uint32_t ICPrescaler; + + /** 输入滤波 */ + uint32_t ICFilter; + +} FL_ATIM_IC_InitTypeDef; + +/** + * @brief BDTR (Break and Dead Time) Init Structure Definition + */ +typedef struct +{ + /** 运行状态下的输出关闭状态 */ + uint32_t OSSRState; + + /** 空闲状态下的输出关闭状态 */ + uint32_t OSSIState; + + /** 寄存器写保护等级 */ + uint32_t lockLevel; + + /** 死区时间 */ + uint32_t deadTime; + + /** 刹车使能 */ + uint32_t breakState; + + /** 刹车信号滤波 */ + uint32_t breakFilter; + + /** 刹车信号极性 */ + uint32_t breakPolarity; + + /** 刹车后计数器重装后自动输出使能*/ + uint32_t automaticOutput; + + /** 刹车信号1门控 */ + uint32_t gatedBrakeSignal_1; + + /** 刹车信号2门控 */ + uint32_t gatedBrakeSignal_2; + + /** 两路刹车信号控制逻辑 */ + uint32_t brakeSignalCombined; + +} FL_ATIM_BDTR_InitTypeDef; + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup ATIM_FL_Exported_Constants ATIM Exported Constants + * @{ + */ + +#define ATIM_CR1_CKD_Pos (8U) +#define ATIM_CR1_CKD_Msk (0x3U << ATIM_CR1_CKD_Pos) +#define ATIM_CR1_CKD ATIM_CR1_CKD_Msk + +#define ATIM_CR1_ARPE_Pos (7U) +#define ATIM_CR1_ARPE_Msk (0x1U << ATIM_CR1_ARPE_Pos) +#define ATIM_CR1_ARPE ATIM_CR1_ARPE_Msk + +#define ATIM_CR1_CMS_Pos (5U) +#define ATIM_CR1_CMS_Msk (0x3U << ATIM_CR1_CMS_Pos) +#define ATIM_CR1_CMS ATIM_CR1_CMS_Msk + +#define ATIM_CR1_DIR_Pos (4U) +#define ATIM_CR1_DIR_Msk (0x1U << ATIM_CR1_DIR_Pos) +#define ATIM_CR1_DIR ATIM_CR1_DIR_Msk + +#define ATIM_CR1_OPM_Pos (3U) +#define ATIM_CR1_OPM_Msk (0x1U << ATIM_CR1_OPM_Pos) +#define ATIM_CR1_OPM ATIM_CR1_OPM_Msk + +#define ATIM_CR1_URS_Pos (2U) +#define ATIM_CR1_URS_Msk (0x1U << ATIM_CR1_URS_Pos) +#define ATIM_CR1_URS ATIM_CR1_URS_Msk + +#define ATIM_CR1_UDIS_Pos (1U) +#define ATIM_CR1_UDIS_Msk (0x1U << ATIM_CR1_UDIS_Pos) +#define ATIM_CR1_UDIS ATIM_CR1_UDIS_Msk + +#define ATIM_CR1_CEN_Pos (0U) +#define ATIM_CR1_CEN_Msk (0x1U << ATIM_CR1_CEN_Pos) +#define ATIM_CR1_CEN ATIM_CR1_CEN_Msk + +#define ATIM_CR2_OISN_Pos (9U) +#define ATIM_CR2_OISN_Msk (0x1U << ATIM_CR2_OISN_Pos) +#define ATIM_CR2_OISN ATIM_CR2_OISN_Msk + +#define ATIM_CR2_OIS_Pos (8U) +#define ATIM_CR2_OIS_Msk (0x1U << ATIM_CR2_OIS_Pos) +#define ATIM_CR2_OIS ATIM_CR2_OIS_Msk + +#define ATIM_CR2_TI1S_Pos (7U) +#define ATIM_CR2_TI1S_Msk (0x1U << ATIM_CR2_TI1S_Pos) +#define ATIM_CR2_TI1S ATIM_CR2_TI1S_Msk + +#define ATIM_CR2_MMS_Pos (4U) +#define ATIM_CR2_MMS_Msk (0x7U << ATIM_CR2_MMS_Pos) +#define ATIM_CR2_MMS ATIM_CR2_MMS_Msk + +#define ATIM_CR2_CCDS_Pos (3U) +#define ATIM_CR2_CCDS_Msk (0x1U << ATIM_CR2_CCDS_Pos) +#define ATIM_CR2_CCDS ATIM_CR2_CCDS_Msk + +#define ATIM_CR2_CCUS_Pos (2U) +#define ATIM_CR2_CCUS_Msk (0x1U << ATIM_CR2_CCUS_Pos) +#define ATIM_CR2_CCUS ATIM_CR2_CCUS_Msk + +#define ATIM_CR2_CCPC_Pos (0U) +#define ATIM_CR2_CCPC_Msk (0x1U << ATIM_CR2_CCPC_Pos) +#define ATIM_CR2_CCPC ATIM_CR2_CCPC_Msk + +#define ATIM_SMCR_ETP_Pos (15U) +#define ATIM_SMCR_ETP_Msk (0x1U << ATIM_SMCR_ETP_Pos) +#define ATIM_SMCR_ETP ATIM_SMCR_ETP_Msk + +#define ATIM_SMCR_ECE_Pos (14U) +#define ATIM_SMCR_ECE_Msk (0x1U << ATIM_SMCR_ECE_Pos) +#define ATIM_SMCR_ECE ATIM_SMCR_ECE_Msk + +#define ATIM_SMCR_ETPS_Pos (12U) +#define ATIM_SMCR_ETPS_Msk (0x3U << ATIM_SMCR_ETPS_Pos) +#define ATIM_SMCR_ETPS ATIM_SMCR_ETPS_Msk + +#define ATIM_SMCR_ETF_Pos (8U) +#define ATIM_SMCR_ETF_Msk (0xfU << ATIM_SMCR_ETF_Pos) +#define ATIM_SMCR_ETF ATIM_SMCR_ETF_Msk + +#define ATIM_SMCR_MSM_Pos (7U) +#define ATIM_SMCR_MSM_Msk (0x1U << ATIM_SMCR_MSM_Pos) +#define ATIM_SMCR_MSM ATIM_SMCR_MSM_Msk + +#define ATIM_SMCR_TS_Pos (4U) +#define ATIM_SMCR_TS_Msk (0x7U << ATIM_SMCR_TS_Pos) +#define ATIM_SMCR_TS ATIM_SMCR_TS_Msk + +#define ATIM_SMCR_SMS_Pos (0U) +#define ATIM_SMCR_SMS_Msk (0x7U << ATIM_SMCR_SMS_Pos) +#define ATIM_SMCR_SMS ATIM_SMCR_SMS_Msk + +#define ATIM_DIER_CC1BURSTEN_Pos (16U) +#define ATIM_DIER_CC1BURSTEN_Msk (0x1U << ATIM_DIER_CC1BURSTEN_Pos) +#define ATIM_DIER_CC1BURSTEN ATIM_DIER_CC1BURSTEN_Msk + +#define ATIM_DIER_CC2BURSTEN_Pos (17U) +#define ATIM_DIER_CC2BURSTEN_Msk (0x1U << ATIM_DIER_CC2BURSTEN_Pos) +#define ATIM_DIER_CC2BURSTEN ATIM_DIER_CC2BURSTEN_Msk + +#define ATIM_DIER_CC3BURSTEN_Pos (18U) +#define ATIM_DIER_CC3BURSTEN_Msk (0x1U << ATIM_DIER_CC3BURSTEN_Pos) +#define ATIM_DIER_CC3BURSTEN ATIM_DIER_CC3BURSTEN_Msk + +#define ATIM_DIER_CC4BURSTEN_Pos (19U) +#define ATIM_DIER_CC4BURSTEN_Msk (0x1U << ATIM_DIER_CC4BURSTEN_Pos) +#define ATIM_DIER_CC4BURSTEN ATIM_DIER_CC4BURSTEN_Msk + +#define ATIM_DIER_TDE_Pos (14U) +#define ATIM_DIER_TDE_Msk (0x1U << ATIM_DIER_TDE_Pos) +#define ATIM_DIER_TDE ATIM_DIER_TDE_Msk + +#define ATIM_DIER_COMDE_Pos (13U) +#define ATIM_DIER_COMDE_Msk (0x1U << ATIM_DIER_COMDE_Pos) +#define ATIM_DIER_COMDE ATIM_DIER_COMDE_Msk + +#define ATIM_DIER_CCDE_Pos (9U) +#define ATIM_DIER_CCDE_Msk (0x1U << ATIM_DIER_CCDE_Pos) +#define ATIM_DIER_CCDE ATIM_DIER_CCDE_Msk + +#define ATIM_DIER_UDE_Pos (8U) +#define ATIM_DIER_UDE_Msk (0x1U << ATIM_DIER_UDE_Pos) +#define ATIM_DIER_UDE ATIM_DIER_UDE_Msk + +#define ATIM_DIER_BIE_Pos (7U) +#define ATIM_DIER_BIE_Msk (0x1U << ATIM_DIER_BIE_Pos) +#define ATIM_DIER_BIE ATIM_DIER_BIE_Msk + +#define ATIM_DIER_TIE_Pos (6U) +#define ATIM_DIER_TIE_Msk (0x1U << ATIM_DIER_TIE_Pos) +#define ATIM_DIER_TIE ATIM_DIER_TIE_Msk + +#define ATIM_DIER_COMIE_Pos (5U) +#define ATIM_DIER_COMIE_Msk (0x1U << ATIM_DIER_COMIE_Pos) +#define ATIM_DIER_COMIE ATIM_DIER_COMIE_Msk + +#define ATIM_DIER_CCIE_Pos (1U) +#define ATIM_DIER_CCIE_Msk (0x1U << ATIM_DIER_CCIE_Pos) +#define ATIM_DIER_CCIE ATIM_DIER_CCIE_Msk + +#define ATIM_DIER_UIE_Pos (0U) +#define ATIM_DIER_UIE_Msk (0x1U << ATIM_DIER_UIE_Pos) +#define ATIM_DIER_UIE ATIM_DIER_UIE_Msk + +#define ATIM_ISR_CCOF_Pos (9U) +#define ATIM_ISR_CCOF_Msk (0x1U << ATIM_ISR_CCOF_Pos) +#define ATIM_ISR_CCOF ATIM_ISR_CCOF_Msk + +#define ATIM_ISR_BIF_Pos (7U) +#define ATIM_ISR_BIF_Msk (0x1U << ATIM_ISR_BIF_Pos) +#define ATIM_ISR_BIF ATIM_ISR_BIF_Msk + +#define ATIM_ISR_TIF_Pos (6U) +#define ATIM_ISR_TIF_Msk (0x1U << ATIM_ISR_TIF_Pos) +#define ATIM_ISR_TIF ATIM_ISR_TIF_Msk + +#define ATIM_ISR_COMIF_Pos (5U) +#define ATIM_ISR_COMIF_Msk (0x1U << ATIM_ISR_COMIF_Pos) +#define ATIM_ISR_COMIF ATIM_ISR_COMIF_Msk + +#define ATIM_ISR_CCIF_Pos (1U) +#define ATIM_ISR_CCIF_Msk (0x1U << ATIM_ISR_CCIF_Pos) +#define ATIM_ISR_CCIF ATIM_ISR_CCIF_Msk + +#define ATIM_ISR_UIF_Pos (0U) +#define ATIM_ISR_UIF_Msk (0x1U << ATIM_ISR_UIF_Pos) +#define ATIM_ISR_UIF ATIM_ISR_UIF_Msk + +#define ATIM_EGR_BG_Pos (7U) +#define ATIM_EGR_BG_Msk (0x1U << ATIM_EGR_BG_Pos) +#define ATIM_EGR_BG ATIM_EGR_BG_Msk + +#define ATIM_EGR_TG_Pos (6U) +#define ATIM_EGR_TG_Msk (0x1U << ATIM_EGR_TG_Pos) +#define ATIM_EGR_TG ATIM_EGR_TG_Msk + +#define ATIM_EGR_COMG_Pos (5U) +#define ATIM_EGR_COMG_Msk (0x1U << ATIM_EGR_COMG_Pos) +#define ATIM_EGR_COMG ATIM_EGR_COMG_Msk + +#define ATIM_EGR_CCG_Pos (1U) +#define ATIM_EGR_CCG_Msk (0x1U << ATIM_EGR_CCG_Pos) +#define ATIM_EGR_CCG ATIM_EGR_CCG_Msk + +#define ATIM_EGR_UG_Pos (0U) +#define ATIM_EGR_UG_Msk (0x1U << ATIM_EGR_UG_Pos) +#define ATIM_EGR_UG ATIM_EGR_UG_Msk + +#define ATIM_DCR_DBL_Pos (8U) +#define ATIM_DCR_DBL_Msk (0x1fU << ATIM_DCR_DBL_Pos) +#define ATIM_DCR_DBL ATIM_DCR_DBL_Msk + +#define ATIM_DCR_DBA_Pos (0U) +#define ATIM_DCR_DBA_Msk (0x1fU << ATIM_DCR_DBA_Pos) +#define ATIM_DCR_DBA ATIM_DCR_DBA_Msk + +#define ATIM_CCMR_OCCE_Pos (7U) +#define ATIM_CCMR_OCCE_Msk (0x1U << ATIM_CCMR_OCCE_Pos) +#define ATIM_CCMR_OCCE ATIM_CCMR_OCCE_Msk + +#define ATIM_CCMR_OCM_Pos (4U) +#define ATIM_CCMR_OCM_Msk (0x7U << ATIM_CCMR_OCM_Pos) +#define ATIM_CCMR_OCM ATIM_CCMR_OCM_Msk + +#define ATIM_CCMR_OCPE_Pos (3U) +#define ATIM_CCMR_OCPE_Msk (0x1U << ATIM_CCMR_OCPE_Pos) +#define ATIM_CCMR_OCPE ATIM_CCMR_OCPE_Msk + +#define ATIM_CCMR_OCFE_Pos (2U) +#define ATIM_CCMR_OCFE_Msk (0x1U << ATIM_CCMR_OCFE_Pos) +#define ATIM_CCMR_OCFE ATIM_CCMR_OCFE_Msk + +#define ATIM_CCMR_ICF_Pos (4U) +#define ATIM_CCMR_ICF_Msk (0xfU << ATIM_CCMR_ICF_Pos) +#define ATIM_CCMR_ICF ATIM_CCMR_ICF_Msk + +#define ATIM_CCMR_ICPSC_Pos (2U) +#define ATIM_CCMR_ICPSC_Msk (0x3U << ATIM_CCMR_ICPSC_Pos) +#define ATIM_CCMR_ICPSC ATIM_CCMR_ICPSC_Msk + +#define ATIM_CCMR_CCS_Pos (0U) +#define ATIM_CCMR_CCS_Msk (0x3U << ATIM_CCMR_CCS_Pos) +#define ATIM_CCMR_CCS ATIM_CCMR_CCS_Msk + +#define ATIM_CCER_CCNP_Pos (3U) +#define ATIM_CCER_CCNP_Msk (0x1U << ATIM_CCER_CCNP_Pos) +#define ATIM_CCER_CCNP ATIM_CCER_CCNP_Msk + +#define ATIM_CCER_CCNE_Pos (2U) +#define ATIM_CCER_CCNE_Msk (0x1U << ATIM_CCER_CCNE_Pos) +#define ATIM_CCER_CCNE ATIM_CCER_CCNE_Msk + +#define ATIM_CCER_CCOP_Pos (1U) +#define ATIM_CCER_CCOP_Msk (0x1U << ATIM_CCER_CCOP_Pos) +#define ATIM_CCER_CCOP ATIM_CCER_CCOP_Msk + +#define ATIM_CCER_CCIP_Pos (1U) +#define ATIM_CCER_CCIP_Msk (0x1U << ATIM_CCER_CCIP_Pos) +#define ATIM_CCER_CCIP ATIM_CCER_CCIP_Msk + +#define ATIM_CCER_CCOE_Pos (0U) +#define ATIM_CCER_CCOE_Msk (0x1U << ATIM_CCER_CCOE_Pos) +#define ATIM_CCER_CCOE ATIM_CCER_CCOE_Msk + +#define ATIM_CCER_CCIE_Pos (0U) +#define ATIM_CCER_CCIE_Msk (0x1U << ATIM_CCER_CCIE_Pos) +#define ATIM_CCER_CCIE ATIM_CCER_CCIE_Msk + +#define ATIM_BDTR_MOE_Pos (15U) +#define ATIM_BDTR_MOE_Msk (0x1U << ATIM_BDTR_MOE_Pos) +#define ATIM_BDTR_MOE ATIM_BDTR_MOE_Msk + +#define ATIM_BDTR_AOE_Pos (14U) +#define ATIM_BDTR_AOE_Msk (0x1U << ATIM_BDTR_AOE_Pos) +#define ATIM_BDTR_AOE ATIM_BDTR_AOE_Msk + +#define ATIM_BDTR_BKP_Pos (13U) +#define ATIM_BDTR_BKP_Msk (0x1U << ATIM_BDTR_BKP_Pos) +#define ATIM_BDTR_BKP ATIM_BDTR_BKP_Msk + +#define ATIM_BDTR_BKE_Pos (12U) +#define ATIM_BDTR_BKE_Msk (0x1U << ATIM_BDTR_BKE_Pos) +#define ATIM_BDTR_BKE ATIM_BDTR_BKE_Msk + +#define ATIM_BDTR_OSSR_Pos (11U) +#define ATIM_BDTR_OSSR_Msk (0x1U << ATIM_BDTR_OSSR_Pos) +#define ATIM_BDTR_OSSR ATIM_BDTR_OSSR_Msk + +#define ATIM_BDTR_OSSI_Pos (10U) +#define ATIM_BDTR_OSSI_Msk (0x1U << ATIM_BDTR_OSSI_Pos) +#define ATIM_BDTR_OSSI ATIM_BDTR_OSSI_Msk + +#define ATIM_BDTR_LOCK_Pos (8U) +#define ATIM_BDTR_LOCK_Msk (0x3U << ATIM_BDTR_LOCK_Pos) +#define ATIM_BDTR_LOCK ATIM_BDTR_LOCK_Msk + +#define ATIM_BDTR_DTG_Pos (0U) +#define ATIM_BDTR_DTG_Msk (0xffU << ATIM_BDTR_DTG_Pos) +#define ATIM_BDTR_DTG ATIM_BDTR_DTG_Msk + +#define ATIM_BKCR_BRK1GATE_Pos (8U) +#define ATIM_BKCR_BRK1GATE_Msk (0x1U << ATIM_BKCR_BRK1GATE_Pos) +#define ATIM_BKCR_BRK1GATE ATIM_BKCR_BRK1GATE_Msk + +#define ATIM_BKCR_BRK2GATE_Pos (9U) +#define ATIM_BKCR_BRK2GATE_Msk (0x1U << ATIM_BKCR_BRK2GATE_Pos) +#define ATIM_BKCR_BRK2GATE ATIM_BKCR_BRK2GATE_Msk + +#define ATIM_BKCR_BRKF_Pos (4U) +#define ATIM_BKCR_BRKF_Msk (0xfU << ATIM_BKCR_BRKF_Pos) +#define ATIM_BKCR_BRKF ATIM_BKCR_BRKF_Msk + +#define ATIM_BKCR_BRKCOMB_Pos (3U) +#define ATIM_BKCR_BRKCOMB_Msk (0x1U << ATIM_BKCR_BRKCOMB_Pos) +#define ATIM_BKCR_BRKCOMB ATIM_BKCR_BRKCOMB_Msk + +#define ATIM_BKCR_HFDET_BRKEN_Pos (2U) +#define ATIM_BKCR_HFDET_BRKEN_Msk (0x1U << ATIM_BKCR_HFDET_BRKEN_Pos) +#define ATIM_BKCR_HFDET_BRKEN ATIM_BKCR_HFDET_BRKEN_Msk + +#define ATIM_BKCR_SVD_BRKEN_Pos (1U) +#define ATIM_BKCR_SVD_BRKEN_Msk (0x1U << ATIM_BKCR_SVD_BRKEN_Pos) +#define ATIM_BKCR_SVD_BRKEN ATIM_BKCR_SVD_BRKEN_Msk + +#define ATIM_BKCR_COMP_BRKEN_Pos (0U) +#define ATIM_BKCR_COMP_BRKEN_Msk (0x1U << ATIM_BKCR_COMP_BRKEN_Pos) +#define ATIM_BKCR_COMP_BRKEN ATIM_BKCR_COMP_BRKEN_Msk + + + +#define FL_ATIM_CHANNEL_1 0x0U +#define FL_ATIM_CHANNEL_2 0x1U +#define FL_ATIM_CHANNEL_3 0x2U +#define FL_ATIM_CHANNEL_4 0x3U + + + +#define FL_ATIM_CLK_DIVISION_DIV1 (0x0U << ATIM_CR1_CKD_Pos) +#define FL_ATIM_CLK_DIVISION_DIV2 (0x1U << ATIM_CR1_CKD_Pos) +#define FL_ATIM_CLK_DIVISION_DIV4 (0x2U << ATIM_CR1_CKD_Pos) + + +#define FL_ATIM_COUNTER_ALIGNED_EDGE (0x0U << ATIM_CR1_CMS_Pos) +#define FL_ATIM_COUNTER_ALIGNED_CENTER_DOWN (0x1U << ATIM_CR1_CMS_Pos) +#define FL_ATIM_COUNTER_ALIGNED_CENTER_UP (0x2U << ATIM_CR1_CMS_Pos) +#define FL_ATIM_COUNTER_ALIGNED_CENTER_UP_DOWN (0x3U << ATIM_CR1_CMS_Pos) + + +#define FL_ATIM_COUNTER_DIR_UP (0x0U << ATIM_CR1_DIR_Pos) +#define FL_ATIM_COUNTER_DIR_DOWN (0x1U << ATIM_CR1_DIR_Pos) + + +#define FL_ATIM_ONE_PULSE_MODE_CONTINUOUS (0x0U << ATIM_CR1_OPM_Pos) +#define FL_ATIM_ONE_PULSE_MODE_SINGLE (0x1U << ATIM_CR1_OPM_Pos) + + +#define FL_ATIM_UPDATE_SOURCE_REGULAR (0x0U << ATIM_CR1_URS_Pos) +#define FL_ATIM_UPDATE_SOURCE_COUNTER (0x1U << ATIM_CR1_URS_Pos) + + +#define FL_ATIM_OCN_IDLE_STATE_LOW (0x0U << ATIM_CR2_OISN_Pos) +#define FL_ATIM_OCN_IDLE_STATE_HIGH (0x1U << ATIM_CR2_OISN_Pos) + + +#define FL_ATIM_OC_IDLE_STATE_LOW (0x0U << ATIM_CR2_OIS_Pos) +#define FL_ATIM_OC_IDLE_STATE_HIGH (0x1U << ATIM_CR2_OIS_Pos) + + +#define FL_ATIM_TRGO_RESET (0x0U << ATIM_CR2_MMS_Pos) +#define FL_ATIM_TRGO_ENABLE (0x1U << ATIM_CR2_MMS_Pos) +#define FL_ATIM_TRGO_UPDATE (0x2U << ATIM_CR2_MMS_Pos) +#define FL_ATIM_TRGO_CC1IF (0x3U << ATIM_CR2_MMS_Pos) +#define FL_ATIM_TRGO_OC1REF (0x4U << ATIM_CR2_MMS_Pos) +#define FL_ATIM_TRGO_OC2REF (0x5U << ATIM_CR2_MMS_Pos) +#define FL_ATIM_TRGO_OC3REF (0x6U << ATIM_CR2_MMS_Pos) +#define FL_ATIM_TRGO_OC4REF (0x7U << ATIM_CR2_MMS_Pos) + + +#define FL_ATIM_DMA_REQ_CC (0x0U << ATIM_CR2_CCDS_Pos) +#define FL_ATIM_DMA_REQ_UPDATE (0x1U << ATIM_CR2_CCDS_Pos) + + +#define FL_ATIM_UPDATE_SOURCE_COMG_ONLY (0x0U << ATIM_CR2_CCUS_Pos) +#define FL_ATIM_UPDATE_SOURCE_COMG_AND_TRGI (0x1U << ATIM_CR2_CCUS_Pos) + + +#define FL_ATIM_ETR_POLARITY_NORMAL (0x0U << ATIM_SMCR_ETP_Pos) +#define FL_ATIM_ETR_POLARITY_INVERT (0x1U << ATIM_SMCR_ETP_Pos) + + +#define FL_ATIM_ETR_PSC_DIV1 (0x0U << ATIM_SMCR_ETPS_Pos) +#define FL_ATIM_ETR_PSC_DIV2 (0x1U << ATIM_SMCR_ETPS_Pos) +#define FL_ATIM_ETR_PSC_DIV4 (0x2U << ATIM_SMCR_ETPS_Pos) +#define FL_ATIM_ETR_PSC_DIV8 (0x3U << ATIM_SMCR_ETPS_Pos) + + +#define FL_ATIM_ETR_FILTER_DIV1 (0x0U << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV1_N2 (0x1U << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV1_N4 (0x2U << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV1_N8 (0x3U << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV2_N6 (0x4U << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV2_N8 (0x5U << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV4_N6 (0x6U << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV4_N8 (0x7U << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV8_N6 (0x8U << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV8_N8 (0x9U << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV16_N5 (0xaU << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV16_N6 (0xbU << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV16_N8 (0xcU << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV32_N5 (0xdU << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV32_N6 (0xeU << ATIM_SMCR_ETF_Pos) +#define FL_ATIM_ETR_FILTER_DIV32_N8 (0xfU << ATIM_SMCR_ETF_Pos) + + +#define FL_ATIM_TRGI_ITR0 (0x0U << ATIM_SMCR_TS_Pos) +#define FL_ATIM_TRGI_ITR1 (0x1U << ATIM_SMCR_TS_Pos) +#define FL_ATIM_TRGI_ITR2 (0x2U << ATIM_SMCR_TS_Pos) +#define FL_ATIM_TRGI_ITR3 (0x3U << ATIM_SMCR_TS_Pos) +#define FL_ATIM_TRGI_TI1F_EDGE (0x4U << ATIM_SMCR_TS_Pos) +#define FL_ATIM_TRGI_TI1FP1 (0x5U << ATIM_SMCR_TS_Pos) +#define FL_ATIM_TRGI_TI2FP2 (0x6U << ATIM_SMCR_TS_Pos) +#define FL_ATIM_TRGI_ETRF (0x7U << ATIM_SMCR_TS_Pos) + + +#define FL_ATIM_SLAVE_MODE_PROHIBITED (0x0U << ATIM_SMCR_SMS_Pos) +#define FL_ATIM_SLAVE_MODE_ENCODER_X2_TI1 (0x1U << ATIM_SMCR_SMS_Pos) +#define FL_ATIM_SLAVE_MODE_ENCODER_X2_TI2 (0x2U << ATIM_SMCR_SMS_Pos) +#define FL_ATIM_SLAVE_MODE_ENCODER_X4_TI1TI2 (0x3U << ATIM_SMCR_SMS_Pos) +#define FL_ATIM_SLAVE_MODE_TRGI_RISE_RST (0x4U << ATIM_SMCR_SMS_Pos) +#define FL_ATIM_SLAVE_MODE_TRGI_HIGH_RUN (0x5U << ATIM_SMCR_SMS_Pos) +#define FL_ATIM_SLAVE_MODE_TRGI_RISE_RUN (0x6U << ATIM_SMCR_SMS_Pos) +#define FL_ATIM_SLAVE_MODE_TRGI_CLK (0x7U << ATIM_SMCR_SMS_Pos) + + +#define FL_ATIM_DMA_BURST_LENGTH_1 (0x0U << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_2 (0x1U << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_3 (0x2U << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_4 (0x3U << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_5 (0x4U << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_6 (0x5U << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_7 (0x6U << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_8 (0x7U << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_9 (0x8U << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_10 (0x9U << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_11 (0xaU << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_12 (0xbU << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_13 (0xcU << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_14 (0xdU << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_15 (0xeU << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_16 (0xfU << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_17 (0x10U << ATIM_DCR_DBL_Pos) +#define FL_ATIM_DMA_BURST_LENGTH_18 (0x11U << ATIM_DCR_DBL_Pos) + + +#define FL_ATIM_DMA_BURST_ADDR_CR1 (0x0U << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_CR2 (0x1U << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_SMCR (0x2U << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_DIER (0x3U << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_SR (0x4U << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_EGR (0x5U << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_CCMR1 (0x6U << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_CCMR2 (0x7U << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_CCER (0x8U << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_CNT (0x9U << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_PSC (0xaU << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_ARR (0xbU << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_RCR (0xcU << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_CCR1 (0xdU << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_CCR2 (0xeU << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_CCR3 (0xfU << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_CCR4 (0x10U << ATIM_DCR_DBA_Pos) +#define FL_ATIM_DMA_BURST_ADDR_BDTR (0x11U << ATIM_DCR_DBA_Pos) + + +#define FL_ATIM_OC_MODE_FROZEN (0x0U << ATIM_CCMR_OCM_Pos) +#define FL_ATIM_OC_MODE_ACTIVE (0x1U << ATIM_CCMR_OCM_Pos) +#define FL_ATIM_OC_MODE_INACTIVE (0x2U << ATIM_CCMR_OCM_Pos) +#define FL_ATIM_OC_MODE_TOGGLE (0x3U << ATIM_CCMR_OCM_Pos) +#define FL_ATIM_OC_MODE_FORCED_INACTIVE (0x4U << ATIM_CCMR_OCM_Pos) +#define FL_ATIM_OC_MODE_FORCED_ACTIVE (0x5U << ATIM_CCMR_OCM_Pos) +#define FL_ATIM_OC_MODE_PWM1 (0x6U << ATIM_CCMR_OCM_Pos) +#define FL_ATIM_OC_MODE_PWM2 (0x7U << ATIM_CCMR_OCM_Pos) + + +#define FL_ATIM_IC_FILTER_DIV1 (0x0U << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV1_N2 (0x1U << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV1_N4 (0x2U << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV1_N8 (0x3U << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV2_N6 (0x4U << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV2_N8 (0x5U << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV4_N6 (0x6U << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV4_N8 (0x7U << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV8_N6 (0x8U << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV8_N8 (0x9U << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV16_N5 (0xaU << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV16_N6 (0xbU << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV16_N8 (0xcU << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV32_N5 (0xdU << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV32_N6 (0xeU << ATIM_CCMR_ICF_Pos) +#define FL_ATIM_IC_FILTER_DIV32_N8 (0xfU << ATIM_CCMR_ICF_Pos) + + +#define FL_ATIM_IC_PSC_DIV1 (0x0U << ATIM_CCMR_ICPSC_Pos) +#define FL_ATIM_IC_PSC_DIV2 (0x1U << ATIM_CCMR_ICPSC_Pos) +#define FL_ATIM_IC_PSC_DIV4 (0x2U << ATIM_CCMR_ICPSC_Pos) +#define FL_ATIM_IC_PSC_DIV8 (0x3U << ATIM_CCMR_ICPSC_Pos) + + +#define FL_ATIM_CHANNEL_MODE_OUTPUT (0x0U << ATIM_CCMR_CCS_Pos) +#define FL_ATIM_CHANNEL_MODE_INPUT_NORMAL (0x1U << ATIM_CCMR_CCS_Pos) +#define FL_ATIM_CHANNEL_MODE_INPUT_CROSSOVER (0x2U << ATIM_CCMR_CCS_Pos) +#define FL_ATIM_CHANNEL_MODE_INPUT_TRC (0x3U << ATIM_CCMR_CCS_Pos) + + +#define FL_ATIM_OCN_POLARITY_NORMAL (0x0U << ATIM_CCER_CCNP_Pos) +#define FL_ATIM_OCN_POLARITY_INVERT (0x1U << ATIM_CCER_CCNP_Pos) + + +#define FL_ATIM_OC_POLARITY_NORMAL (0x0U << ATIM_CCER_CCOP_Pos) +#define FL_ATIM_OC_POLARITY_INVERT (0x1U << ATIM_CCER_CCOP_Pos) + + +#define FL_ATIM_IC_POLARITY_NORMAL (0x0U << ATIM_CCER_CCIP_Pos) +#define FL_ATIM_IC_POLARITY_INVERT (0x1U << ATIM_CCER_CCIP_Pos) + + +#define FL_ATIM_BREAK_POLARITY_LOW (0x0U << ATIM_BDTR_BKP_Pos) +#define FL_ATIM_BREAK_POLARITY_HIGH (0x1U << ATIM_BDTR_BKP_Pos) + + +#define FL_ATIM_OSSR_DISABLE (0x0U << ATIM_BDTR_OSSR_Pos) +#define FL_ATIM_OSSR_ENABLE (0x1U << ATIM_BDTR_OSSR_Pos) + + +#define FL_ATIM_OSSI_DISABLE (0x0U << ATIM_BDTR_OSSI_Pos) +#define FL_ATIM_OSSI_ENABLE (0x1U << ATIM_BDTR_OSSI_Pos) + + +#define FL_ATIM_LOCK_LEVEL_OFF (0x0U << ATIM_BDTR_LOCK_Pos) +#define FL_ATIM_LOCK_LEVEL_1 (0x1U << ATIM_BDTR_LOCK_Pos) +#define FL_ATIM_LOCK_LEVEL_2 (0x2U << ATIM_BDTR_LOCK_Pos) +#define FL_ATIM_LOCK_LEVEL_3 (0x3U << ATIM_BDTR_LOCK_Pos) + + +#define FL_ATIM_BREAK1_GATE_LOW (0x0U << ATIM_BKCR_BRK1GATE_Pos) +#define FL_ATIM_BREAK1_GATE_AUTO (0x1U << ATIM_BKCR_BRK1GATE_Pos) + + +#define FL_ATIM_BREAK2_GATE_LOW (0x0U << ATIM_BKCR_BRK2GATE_Pos) +#define FL_ATIM_BREAK2_GATE_AUTO (0x1U << ATIM_BKCR_BRK2GATE_Pos) + + +#define FL_ATIM_BREAK_FILTER_DIV1 (0x0U << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV1_N2 (0x1U << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV1_N4 (0x2U << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV1_N8 (0x3U << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV2_N6 (0x4U << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV2_N8 (0x5U << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV4_N6 (0x6U << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV4_N8 (0x7U << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV8_N6 (0x8U << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV8_N8 (0x9U << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV16_N5 (0xaU << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV16_N6 (0xbU << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV16_N8 (0xcU << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV32_N5 (0xdU << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV32_N6 (0xeU << ATIM_BKCR_BRKF_Pos) +#define FL_ATIM_BREAK_FILTER_DIV32_N8 (0xfU << ATIM_BKCR_BRKF_Pos) + + +#define FL_ATIM_BREAK_COMBINATION_OR (0x0U << ATIM_BKCR_BRKCOMB_Pos) +#define FL_ATIM_BREAK_COMBINATION_AND (0x1U << ATIM_BKCR_BRKCOMB_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup ATIM_FL_Exported_Functions ATIM Exported Functions + * @{ + */ + +/** + * @brief 设置时钟分频因子 + * @rmtoll CR1 CKD FL_ATIM_SetClockDivision + * @param TIMx TIM instance + * @param div This parameter can be one of the following values: + * @arg @ref FL_ATIM_CLK_DIVISION_DIV1 + * @arg @ref FL_ATIM_CLK_DIVISION_DIV2 + * @arg @ref FL_ATIM_CLK_DIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetClockDivision(ATIM_Type *TIMx, uint32_t div) +{ + MODIFY_REG(TIMx->CR1, ATIM_CR1_CKD_Msk, div); +} + +/** + * @brief 读取时钟分频因子 + * @rmtoll CR1 CKD FL_ATIM_GetClockDivision + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_CLK_DIVISION_DIV1 + * @arg @ref FL_ATIM_CLK_DIVISION_DIV2 + * @arg @ref FL_ATIM_CLK_DIVISION_DIV4 + */ +__STATIC_INLINE uint32_t FL_ATIM_GetClockDivision(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, ATIM_CR1_CKD_Msk)); +} + +/** + * @brief 自动重装载使能 + * @rmtoll CR1 ARPE FL_ATIM_EnableARRPreload + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableARRPreload(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->CR1, ATIM_CR1_ARPE_Msk); +} + +/** + * @brief 获取自动重装载使能状态 + * @rmtoll CR1 ARPE FL_ATIM_IsEnabledARRPreload + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledARRPreload(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, ATIM_CR1_ARPE_Msk) == ATIM_CR1_ARPE_Msk); +} + +/** + * @brief 自动重装载禁用 + * @rmtoll CR1 ARPE FL_ATIM_DisableARRPreload + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableARRPreload(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->CR1, ATIM_CR1_ARPE_Msk); +} + +/** + * @brief 计数器对齐模式设置 + * @rmtoll CR1 CMS FL_ATIM_SetCounterAlignedMode + * @param TIMx TIM instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_ATIM_COUNTER_ALIGNED_EDGE + * @arg @ref FL_ATIM_COUNTER_ALIGNED_CENTER_DOWN + * @arg @ref FL_ATIM_COUNTER_ALIGNED_CENTER_UP + * @arg @ref FL_ATIM_COUNTER_ALIGNED_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetCounterAlignedMode(ATIM_Type *TIMx, uint32_t mode) +{ + MODIFY_REG(TIMx->CR1, ATIM_CR1_CMS_Msk, mode); +} + +/** + * @brief 读取计数器对齐模式 + * @rmtoll CR1 CMS FL_ATIM_GetCounterAlignedMode + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_COUNTER_ALIGNED_EDGE + * @arg @ref FL_ATIM_COUNTER_ALIGNED_CENTER_DOWN + * @arg @ref FL_ATIM_COUNTER_ALIGNED_CENTER_UP + * @arg @ref FL_ATIM_COUNTER_ALIGNED_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t FL_ATIM_GetCounterAlignedMode(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, ATIM_CR1_CMS_Msk)); +} + +/** + * @brief 设置记数方向 + * @rmtoll CR1 DIR FL_ATIM_SetCounterDirection + * @param TIMx TIM instance + * @param dir This parameter can be one of the following values: + * @arg @ref FL_ATIM_COUNTER_DIR_UP + * @arg @ref FL_ATIM_COUNTER_DIR_DOWN + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetCounterDirection(ATIM_Type *TIMx, uint32_t dir) +{ + MODIFY_REG(TIMx->CR1, ATIM_CR1_DIR_Msk, dir); +} + +/** + * @brief 读取记数方向 + * @rmtoll CR1 DIR FL_ATIM_GetCounterDirection + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_COUNTER_DIR_UP + * @arg @ref FL_ATIM_COUNTER_DIR_DOWN + */ +__STATIC_INLINE uint32_t FL_ATIM_GetCounterDirection(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, ATIM_CR1_DIR_Msk)); +} + +/** + * @brief 设置单脉冲输出模式 + * @rmtoll CR1 OPM FL_ATIM_SetOnePulseMode + * @param TIMx TIM instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_ATIM_ONE_PULSE_MODE_CONTINUOUS + * @arg @ref FL_ATIM_ONE_PULSE_MODE_SINGLE + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetOnePulseMode(ATIM_Type *TIMx, uint32_t mode) +{ + MODIFY_REG(TIMx->CR1, ATIM_CR1_OPM_Msk, mode); +} + +/** + * @brief 读取单脉冲输出的模式 + * @rmtoll CR1 OPM FL_ATIM_GetOnePulseMode + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_ONE_PULSE_MODE_CONTINUOUS + * @arg @ref FL_ATIM_ONE_PULSE_MODE_SINGLE + */ +__STATIC_INLINE uint32_t FL_ATIM_GetOnePulseMode(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, ATIM_CR1_OPM_Msk)); +} + +/** + * @brief 设置更新请求源 + * @rmtoll CR1 URS FL_ATIM_SetUpdateSource + * @param TIMx TIM instance + * @param source This parameter can be one of the following values: + * @arg @ref FL_ATIM_UPDATE_SOURCE_REGULAR + * @arg @ref FL_ATIM_UPDATE_SOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetUpdateSource(ATIM_Type *TIMx, uint32_t source) +{ + MODIFY_REG(TIMx->CR1, ATIM_CR1_URS_Msk, source); +} + +/** + * @brief 读取更新请求源 + * @rmtoll CR1 URS FL_ATIM_GetUpdateSource + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_UPDATE_SOURCE_REGULAR + * @arg @ref FL_ATIM_UPDATE_SOURCE_COUNTER + */ +__STATIC_INLINE uint32_t FL_ATIM_GetUpdateSource(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, ATIM_CR1_URS_Msk)); +} + +/** + * @brief 使能更新事件 + * @rmtoll CR1 UDIS FL_ATIM_EnableUpdateEvent + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableUpdateEvent(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->CR1, ATIM_CR1_UDIS_Msk); +} + +/** + * @brief 读取更新事件状态 + * @rmtoll CR1 UDIS FL_ATIM_IsEnabledUpdateEvent + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledUpdateEvent(ATIM_Type *TIMx) +{ + return (uint32_t)!(READ_BIT(TIMx->CR1, ATIM_CR1_UDIS_Msk) == ATIM_CR1_UDIS_Msk); +} + +/** + * @brief 禁用更新事件 + * @rmtoll CR1 UDIS FL_ATIM_DisableUpdateEvent + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableUpdateEvent(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->CR1, ATIM_CR1_UDIS_Msk); +} + +/** + * @brief 计数器使能 + * @rmtoll CR1 CEN FL_ATIM_Enable + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_Enable(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->CR1, ATIM_CR1_CEN_Msk); +} + +/** + * @brief 读取计数器使能状态 + * @rmtoll CR1 CEN FL_ATIM_IsEnabled + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabled(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, ATIM_CR1_CEN_Msk) == ATIM_CR1_CEN_Msk); +} + +/** + * @brief 计数器关闭 + * @rmtoll CR1 CEN FL_ATIM_Disable + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_Disable(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->CR1, ATIM_CR1_CEN_Msk); +} + +/** + * @brief 设置OCN的输出空闲状态 + * @note + * @rmtoll CR2 OISN FL_ATIM_OC_SetReverseChannelIdleState + * @param TIMx TIM instance + * @param OCNIdleState This parameter can be one of the following values: + * @arg @ref FL_ATIM_OCN_IDLE_STATE_LOW + * @arg @ref FL_ATIM_OCN_IDLE_STATE_HIGH + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_SetReverseChannelIdleState(ATIM_Type *TIMx, uint32_t OCNIdleState, uint32_t channel) +{ + MODIFY_REG(TIMx->CR2, ATIM_CR2_OISN_Msk << (channel * 2), OCNIdleState << (channel * 2)); +} + +/** + * @brief 读取OCN的输出空闲状态 + * @note + * @rmtoll CR2 OISN FL_ATIM_OC_GetReverseChannelIdleState + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_OCN_IDLE_STATE_LOW + * @arg @ref FL_ATIM_OCN_IDLE_STATE_HIGH + */ +__STATIC_INLINE uint32_t FL_ATIM_OC_GetReverseChannelIdleState(ATIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, (ATIM_CR2_OISN_Msk << (channel * 2)))); +} + +/** + * @brief 设置OC的输出空闲状态 + * @note + * @rmtoll CR2 OIS FL_ATIM_OC_SetChannelIdleState + * @param TIMx TIM instance + * @param OCIdleState This parameter can be one of the following values: + * @arg @ref FL_ATIM_OC_IDLE_STATE_LOW + * @arg @ref FL_ATIM_OC_IDLE_STATE_HIGH + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_SetChannelIdleState(ATIM_Type *TIMx, uint32_t OCIdleState, uint32_t channel) +{ + MODIFY_REG(TIMx->CR2, (ATIM_CR2_OIS_Msk << (channel * 2)), OCIdleState << (channel * 2)); +} + +/** + * @brief 读取OC的输出空闲状态 + * @note + * @rmtoll CR2 OIS FL_ATIM_OC_GetChannelIdleState + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_OC_IDLE_STATE_LOW + * @arg @ref FL_ATIM_OC_IDLE_STATE_HIGH + */ +__STATIC_INLINE uint32_t FL_ATIM_OC_GetChannelIdleState(ATIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, (ATIM_CR2_OIS_Msk << (channel * 2)))); +} + +/** + * @brief 通道1输入源选择 + * @rmtoll CR2 TI1S FL_ATIM_IC_EnableXORCombination + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_IC_EnableXORCombination(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->CR2, ATIM_CR2_TI1S_Msk); +} + +/** + * @brief 读取通道1输入源 + * @rmtoll CR2 TI1S FL_ATIM_IC_IsEnabledXORCombination + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IC_IsEnabledXORCombination(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, ATIM_CR2_TI1S_Msk) == ATIM_CR2_TI1S_Msk); +} + +/** + * @brief 通道1输入源禁用XOR组合 + * @rmtoll CR2 TI1S FL_ATIM_IC_DisableXORCombination + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_IC_DisableXORCombination(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->CR2, ATIM_CR2_TI1S_Msk); +} + +/** + * @brief 设置同步触发信号源 + * @rmtoll CR2 MMS FL_ATIM_SetTriggerOutput + * @param TIMx TIM instance + * @param triggerOutput This parameter can be one of the following values: + * @arg @ref FL_ATIM_TRGO_RESET + * @arg @ref FL_ATIM_TRGO_ENABLE + * @arg @ref FL_ATIM_TRGO_UPDATE + * @arg @ref FL_ATIM_TRGO_CC1IF + * @arg @ref FL_ATIM_TRGO_OC1REF + * @arg @ref FL_ATIM_TRGO_OC2REF + * @arg @ref FL_ATIM_TRGO_OC3REF + * @arg @ref FL_ATIM_TRGO_OC4REF + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetTriggerOutput(ATIM_Type *TIMx, uint32_t triggerOutput) +{ + MODIFY_REG(TIMx->CR2, ATIM_CR2_MMS_Msk, triggerOutput); +} + +/** + * @brief 读取同步触发源 + * @rmtoll CR2 MMS FL_ATIM_GetTriggerOutput + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_TRGO_RESET + * @arg @ref FL_ATIM_TRGO_ENABLE + * @arg @ref FL_ATIM_TRGO_UPDATE + * @arg @ref FL_ATIM_TRGO_CC1IF + * @arg @ref FL_ATIM_TRGO_OC1REF + * @arg @ref FL_ATIM_TRGO_OC2REF + * @arg @ref FL_ATIM_TRGO_OC3REF + * @arg @ref FL_ATIM_TRGO_OC4REF + */ +__STATIC_INLINE uint32_t FL_ATIM_GetTriggerOutput(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, ATIM_CR2_MMS_Msk)); +} + +/** + * @brief 设置DMA请求触发 + * @rmtoll CR2 CCDS FL_ATIM_CC_SetDMAReqTrigger + * @param TIMx TIM instance + * @param trigger This parameter can be one of the following values: + * @arg @ref FL_ATIM_DMA_REQ_CC + * @arg @ref FL_ATIM_DMA_REQ_UPDATE + * @retval None + */ +__STATIC_INLINE void FL_ATIM_CC_SetDMAReqTrigger(ATIM_Type *TIMx, uint32_t trigger) +{ + MODIFY_REG(TIMx->CR2, ATIM_CR2_CCDS_Msk, trigger); +} + +/** + * @brief 读取DMA请求触发 + * @rmtoll CR2 CCDS FL_ATIM_CC_GetDMAReqTrigger + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_DMA_REQ_CC + * @arg @ref FL_ATIM_DMA_REQ_UPDATE + */ +__STATIC_INLINE uint32_t FL_ATIM_CC_GetDMAReqTrigger(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, ATIM_CR2_CCDS_Msk)); +} + +/** + * @brief 设置捕捉比较寄存器更新选择 + * @rmtoll CR2 CCUS FL_ATIM_CC_SetUpdateSource + * @param TIMx TIM instance + * @param updateSource This parameter can be one of the following values: + * @arg @ref FL_ATIM_UPDATE_SOURCE_COMG_ONLY + * @arg @ref FL_ATIM_UPDATE_SOURCE_COMG_AND_TRGI? + * @retval None + */ +__STATIC_INLINE void FL_ATIM_CC_SetUpdateSource(ATIM_Type *TIMx, uint32_t updateSource) +{ + MODIFY_REG(TIMx->CR2, ATIM_CR2_CCUS_Msk, updateSource); +} + +/** + * @brief 读取捕捉比较寄存器更新源 + * @rmtoll CR2 CCUS FL_ATIM_CC_GetUpdateSource + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_UPDATE_SOURCE_COMG_ONLY + * @arg @ref FL_ATIM_UPDATE_SOURCE_COMG_AND_TRGI? + */ +__STATIC_INLINE uint32_t FL_ATIM_CC_GetUpdateSource(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, ATIM_CR2_CCUS_Msk)); +} + +/** + * @brief 捕捉比较预装载使能 + * @rmtoll CR2 CCPC FL_ATIM_CC_EnablePreload + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_CC_EnablePreload(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->CR2, ATIM_CR2_CCPC_Msk); +} + +/** + * @brief 读取捕捉比较预装载使能状态 + * @rmtoll CR2 CCPC FL_ATIM_CC_IsEnabledPreload + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_CC_IsEnabledPreload(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, ATIM_CR2_CCPC_Msk) == ATIM_CR2_CCPC_Msk); +} + +/** + * @brief 捕捉比较预装载失能 + * @rmtoll CR2 CCPC FL_ATIM_CC_DisablePreload + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_CC_DisablePreload(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->CR2, ATIM_CR2_CCPC_Msk); +} + +/** + * @brief 设置外部触发信号极性 + * @rmtoll SMCR ETP FL_ATIM_SetETRPolarity + * @param TIMx TIM instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_ATIM_ETR_POLARITY_NORMAL + * @arg @ref FL_ATIM_ETR_POLARITY_INVERT + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetETRPolarity(ATIM_Type *TIMx, uint32_t polarity) +{ + MODIFY_REG(TIMx->SMCR, ATIM_SMCR_ETP_Msk, polarity); +} + +/** + * @brief 读取外部触发信号极性 + * @rmtoll SMCR ETP FL_ATIM_GetETRPolarity + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_ETR_POLARITY_NORMAL + * @arg @ref FL_ATIM_ETR_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_ATIM_GetETRPolarity(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, ATIM_SMCR_ETP_Msk)); +} + +/** + * @brief 外部时钟使能 + * @rmtoll SMCR ECE FL_ATIM_EnableExternalClock + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableExternalClock(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->SMCR, ATIM_SMCR_ECE_Msk); +} + +/** + * @brief 读取外部时钟使能状态 + * @rmtoll SMCR ECE FL_ATIM_IsEnabledExternalClock + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledExternalClock(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, ATIM_SMCR_ECE_Msk) == ATIM_SMCR_ECE_Msk); +} + +/** + * @brief 外部时钟禁用 + * @rmtoll SMCR ECE FL_ATIM_DisableExternalClock + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableExternalClock(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, ATIM_SMCR_ECE_Msk); +} + +/** + * @brief 设置外部触发信号预分频 + * @rmtoll SMCR ETPS FL_ATIM_SetETRPrescaler + * @param TIMx TIM instance + * @param psc This parameter can be one of the following values: + * @arg @ref FL_ATIM_ETR_PSC_DIV1 + * @arg @ref FL_ATIM_ETR_PSC_DIV2 + * @arg @ref FL_ATIM_ETR_PSC_DIV4 + * @arg @ref FL_ATIM_ETR_PSC_DIV8 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetETRPrescaler(ATIM_Type *TIMx, uint32_t psc) +{ + MODIFY_REG(TIMx->SMCR, ATIM_SMCR_ETPS_Msk, psc); +} + +/** + * @brief 读取外部触发信号预分频 + * @rmtoll SMCR ETPS FL_ATIM_GetETRPrescaler + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_ETR_PSC_DIV1 + * @arg @ref FL_ATIM_ETR_PSC_DIV2 + * @arg @ref FL_ATIM_ETR_PSC_DIV4 + * @arg @ref FL_ATIM_ETR_PSC_DIV8 + */ +__STATIC_INLINE uint32_t FL_ATIM_GetETRPrescaler(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, ATIM_SMCR_ETPS_Msk)); +} + +/** + * @brief 设置外部触发信号滤波时钟和长度 + * @rmtoll SMCR ETF FL_ATIM_SetETRFilter + * @param TIMx TIM instance + * @param filter This parameter can be one of the following values: + * @arg @ref FL_ATIM_ETR_FILTER_DIV1 + * @arg @ref FL_ATIM_ETR_FILTER_DIV1_N2 + * @arg @ref FL_ATIM_ETR_FILTER_DIV1_N4 + * @arg @ref FL_ATIM_ETR_FILTER_DIV1_N8 + * @arg @ref FL_ATIM_ETR_FILTER_DIV2_N6 + * @arg @ref FL_ATIM_ETR_FILTER_DIV2_N8 + * @arg @ref FL_ATIM_ETR_FILTER_DIV4_N6 + * @arg @ref FL_ATIM_ETR_FILTER_DIV4_N8 + * @arg @ref FL_ATIM_ETR_FILTER_DIV8_N6 + * @arg @ref FL_ATIM_ETR_FILTER_DIV8_N8 + * @arg @ref FL_ATIM_ETR_FILTER_DIV16_N5 + * @arg @ref FL_ATIM_ETR_FILTER_DIV16_N6 + * @arg @ref FL_ATIM_ETR_FILTER_DIV16_N8 + * @arg @ref FL_ATIM_ETR_FILTER_DIV32_N5 + * @arg @ref FL_ATIM_ETR_FILTER_DIV32_N6 + * @arg @ref FL_ATIM_ETR_FILTER_DIV32_N8 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetETRFilter(ATIM_Type *TIMx, uint32_t filter) +{ + MODIFY_REG(TIMx->SMCR, ATIM_SMCR_ETF_Msk, filter); +} + +/** + * @brief 读取外部触发信号滤波时钟和长度 + * @rmtoll SMCR ETF FL_ATIM_GetETRFilter + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_ETR_FILTER_DIV1 + * @arg @ref FL_ATIM_ETR_FILTER_DIV1_N2 + * @arg @ref FL_ATIM_ETR_FILTER_DIV1_N4 + * @arg @ref FL_ATIM_ETR_FILTER_DIV1_N8 + * @arg @ref FL_ATIM_ETR_FILTER_DIV2_N6 + * @arg @ref FL_ATIM_ETR_FILTER_DIV2_N8 + * @arg @ref FL_ATIM_ETR_FILTER_DIV4_N6 + * @arg @ref FL_ATIM_ETR_FILTER_DIV4_N8 + * @arg @ref FL_ATIM_ETR_FILTER_DIV8_N6 + * @arg @ref FL_ATIM_ETR_FILTER_DIV8_N8 + * @arg @ref FL_ATIM_ETR_FILTER_DIV16_N5 + * @arg @ref FL_ATIM_ETR_FILTER_DIV16_N6 + * @arg @ref FL_ATIM_ETR_FILTER_DIV16_N8 + * @arg @ref FL_ATIM_ETR_FILTER_DIV32_N5 + * @arg @ref FL_ATIM_ETR_FILTER_DIV32_N6 + * @arg @ref FL_ATIM_ETR_FILTER_DIV32_N8 + */ +__STATIC_INLINE uint32_t FL_ATIM_GetETRFilter(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, ATIM_SMCR_ETF_Msk)); +} + +/** + * @brief 主/从模式使能 + * @rmtoll SMCR MSM FL_ATIM_EnableMasterSlaveMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableMasterSlaveMode(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->SMCR, ATIM_SMCR_MSM_Msk); +} + +/** + * @brief 读取主/从模式使能状态 + * @rmtoll SMCR MSM FL_ATIM_IsEnabledMasterSlaveMode + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledMasterSlaveMode(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, ATIM_SMCR_MSM_Msk) == ATIM_SMCR_MSM_Msk); +} + +/** + * @brief 定时器主/从模式禁用 + * @rmtoll SMCR MSM FL_ATIM_DisableMasterSlaveMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableMasterSlaveMode(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, ATIM_SMCR_MSM_Msk); +} + +/** + * @brief 设置同步计数器触发源 + * @rmtoll SMCR TS FL_ATIM_SetTriggerInput + * @param TIMx TIM instance + * @param triggerInput This parameter can be one of the following values: + * @arg @ref FL_ATIM_TRGI_ITR0 + * @arg @ref FL_ATIM_TRGI_ITR1 + * @arg @ref FL_ATIM_TRGI_ITR2 + * @arg @ref FL_ATIM_TRGI_ITR3 + * @arg @ref FL_ATIM_TRGI_TI1F_EDGE + * @arg @ref FL_ATIM_TRGI_TI1FP1 + * @arg @ref FL_ATIM_TRGI_TI2FP2 + * @arg @ref FL_ATIM_TRGI_ETRF + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetTriggerInput(ATIM_Type *TIMx, uint32_t triggerInput) +{ + MODIFY_REG(TIMx->SMCR, ATIM_SMCR_TS_Msk, triggerInput); +} + +/** + * @brief 读取同步计数器的触发源 + * @rmtoll SMCR TS FL_ATIM_GetTriggerInput + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_TRGI_ITR0 + * @arg @ref FL_ATIM_TRGI_ITR1 + * @arg @ref FL_ATIM_TRGI_ITR2 + * @arg @ref FL_ATIM_TRGI_ITR3 + * @arg @ref FL_ATIM_TRGI_TI1F_EDGE + * @arg @ref FL_ATIM_TRGI_TI1FP1 + * @arg @ref FL_ATIM_TRGI_TI2FP2 + * @arg @ref FL_ATIM_TRGI_ETRF + */ +__STATIC_INLINE uint32_t FL_ATIM_GetTriggerInput(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, ATIM_SMCR_TS_Msk)); +} + +/** + * @brief 从机模式设置 + * @rmtoll SMCR SMS FL_ATIM_SetSlaveMode + * @param TIMx TIM instance + * @param encoderMode This parameter can be one of the following values: + * @arg @ref FL_ATIM_SLAVE_MODE_PROHIBITED + * @arg @ref FL_ATIM_SLAVE_MODE_ENCODER_X2_TI1 + * @arg @ref FL_ATIM_SLAVE_MODE_ENCODER_X2_TI2 + * @arg @ref FL_ATIM_SLAVE_MODE_ENCODER_X4_TI1TI2 + * @arg @ref FL_ATIM_SLAVE_MODE_TRGI_RISE_RST + * @arg @ref FL_ATIM_SLAVE_MODE_TRGI_HIGH_RUN + * @arg @ref FL_ATIM_SLAVE_MODE_TRGI_RISE_RUN + * @arg @ref FL_ATIM_SLAVE_MODE_TRGI_CLK + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetSlaveMode(ATIM_Type *TIMx, uint32_t encoderMode) +{ + MODIFY_REG(TIMx->SMCR, ATIM_SMCR_SMS_Msk, encoderMode); +} + +/** + * @brief 读取从机模式 + * @rmtoll SMCR SMS FL_ATIM_GetSlaveMode + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_SLAVE_MODE_PROHIBITED + * @arg @ref FL_ATIM_SLAVE_MODE_ENCODER_X2_TI1 + * @arg @ref FL_ATIM_SLAVE_MODE_ENCODER_X2_TI2 + * @arg @ref FL_ATIM_SLAVE_MODE_NCODER_X4_TI1TI2 + * @arg @ref FL_ATIM_SLAVE_MODE_TRGI_RISE_RST + * @arg @ref FL_ATIM_SLAVE_MODE_TRGI_HIGH_RUN + * @arg @ref FL_ATIM_SLAVE_MODE_TRGI_RISE_RUN + * @arg @ref FL_ATIM_SLAVE_MODE_TRGI_CLK + */ +__STATIC_INLINE uint32_t FL_ATIM_GetSlaveMode(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, ATIM_SMCR_SMS_Msk)); +} + +/** + * @brief 通道1的模式配置为Burst模式 + * @rmtoll DIER CC1BURSTEN FL_ATIM_EnableCC1DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableCC1DMABurstMode(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, ATIM_DIER_CC1BURSTEN_Msk); +} + +/** + * @brief 读取通道1的模式配置 + * @rmtoll DIER CC1BURSTEN FL_ATIM_IsEnabledCC1DMABurstMode + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledCC1DMABurstMode(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, ATIM_DIER_CC1BURSTEN_Msk) == ATIM_DIER_CC1BURSTEN_Msk); +} + +/** + * @brief 通道1的Burst模式禁用 + * @rmtoll DIER CC1BURSTEN FL_ATIM_DisableCC1DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableCC1DMABurstMode(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, ATIM_DIER_CC1BURSTEN_Msk); +} + +/** + * @brief 通道2的模式配置为Burst模式 + * @rmtoll DIER CC2BURSTEN FL_ATIM_EnableCC2DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableCC2DMABurstMode(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, ATIM_DIER_CC2BURSTEN_Msk); +} + +/** + * @brief 读取通道2的模式配置 + * @rmtoll DIER CC2BURSTEN FL_ATIM_IsEnabledCC2DMABurstMode + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledCC2DMABurstMode(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, ATIM_DIER_CC2BURSTEN_Msk) == ATIM_DIER_CC2BURSTEN_Msk); +} + +/** + * @brief 通道2的Burst模式禁用 + * @rmtoll DIER CC2BURSTEN FL_ATIM_DisableCC2DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableCC2DMABurstMode(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, ATIM_DIER_CC2BURSTEN_Msk); +} + +/** + * @brief 通道3的模式配置为Burst模式 + * @rmtoll DIER CC3BURSTEN FL_ATIM_EnableCC3DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableCC3DMABurstMode(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, ATIM_DIER_CC3BURSTEN_Msk); +} + +/** + * @brief 读取通道3的模式配置 + * @rmtoll DIER CC3BURSTEN FL_ATIM_IsEnabledCC3DMABurstMode + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledCC3DMABurstMode(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, ATIM_DIER_CC3BURSTEN_Msk) == ATIM_DIER_CC3BURSTEN_Msk); +} + +/** + * @brief 通道3的Burst模式禁用 + * @rmtoll DIER CC3BURSTEN FL_ATIM_DisableCC3DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableCC3DMABurstMode(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, ATIM_DIER_CC3BURSTEN_Msk); +} + +/** + * @brief 通道4的模式配置为Burst模式 + * @rmtoll DIER CC4BURSTEN FL_ATIM_EnableCC4DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableCC4DMABurstMode(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, ATIM_DIER_CC4BURSTEN_Msk); +} + +/** + * @brief 读取通道4的模式配置 + * @rmtoll DIER CC4BURSTEN FL_ATIM_IsEnabledCC4DMABurstMode + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledCC4DMABurstMode(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, ATIM_DIER_CC4BURSTEN_Msk) == ATIM_DIER_CC4BURSTEN_Msk); +} + +/** + * @brief 通道4的Burst模式禁用 + * @rmtoll DIER CC4BURSTEN FL_ATIM_DisableCC4DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableCC4DMABurstMode(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, ATIM_DIER_CC4BURSTEN_Msk); +} + +/** + * @brief 外部触发DMA请求使能 + * @rmtoll DIER TDE FL_ATIM_EnableDMAReq_Trigger + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableDMAReq_Trigger(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, ATIM_DIER_TDE_Msk); +} + +/** + * @brief 读取外部触发DMA请求使能状态 + * @rmtoll DIER TDE FL_ATIM_IsEnabledDMAReq_Trigger + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledDMAReq_Trigger(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, ATIM_DIER_TDE_Msk) == ATIM_DIER_TDE_Msk); +} + +/** + * @brief 外部触发DMA请求禁用 + * @rmtoll DIER TDE FL_ATIM_DisableDMAReq_Trigger + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableDMAReq_Trigger(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, ATIM_DIER_TDE_Msk); +} + +/** + * @brief COM事件DMA请求使能 + * @note + * @rmtoll DIER COMDE FL_ATIM_EnableDMAReq_COM + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableDMAReq_COM(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, ATIM_DIER_COMDE_Msk); +} + +/** + * @brief 读取COM事件DMA请求使能状态 + * @note + * @rmtoll DIER COMDE FL_ATIM_IsEnabledDMAReq_COM + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledDMAReq_COM(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, ATIM_DIER_COMDE_Msk) == ATIM_DIER_COMDE_Msk); +} + +/** + * @brief COM事件DMA请求禁用 + * @note + * @rmtoll DIER COMDE FL_ATIM_DisableDMAReq_COM + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableDMAReq_COM(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, ATIM_DIER_COMDE_Msk); +} + +/** + * @brief 捕捉比较通道的DMA请求使能 + * @rmtoll DIER CCDE FL_ATIM_EnableDMAReq_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableDMAReq_CC(ATIM_Type *TIMx, uint32_t channel) +{ + SET_BIT(TIMx->DIER, ATIM_DIER_CCDE_Msk << channel); +} + +/** + * @brief 读取捕捉比较通道的DMA请求使能 + * @rmtoll DIER CCDE FL_ATIM_IsEnabledDMAReq_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledDMAReq_CC(ATIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, (ATIM_DIER_CCDE_Msk << channel)) == (ATIM_DIER_CCDE_Msk << channel)); +} + +/** + * @brief 捕捉比较通道的DMA请求禁用 + * @rmtoll DIER CCDE FL_ATIM_DisableDMAReq_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableDMAReq_CC(ATIM_Type *TIMx, uint32_t channel) +{ + CLEAR_BIT(TIMx->DIER, ATIM_DIER_CCDE_Msk << channel); +} + +/** + * @brief 更新事件DMA请求使能 + * @rmtoll DIER UDE FL_ATIM_EnableDMAReq_Update + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableDMAReq_Update(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, ATIM_DIER_UDE_Msk); +} + +/** + * @brief 读取更新事件DMA请求使能状态 + * @rmtoll DIER UDE FL_ATIM_IsEnabledDMAReq_Update + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledDMAReq_Update(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, ATIM_DIER_UDE_Msk) == ATIM_DIER_UDE_Msk); +} + +/** + * @brief 更新事件DMA请求禁用 + * @rmtoll DIER UDE FL_ATIM_DisableDMAReq_Update + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableDMAReq_Update(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, ATIM_DIER_UDE_Msk); +} + +/** + * @brief 刹车事件中断使能 + * @note + * @rmtoll DIER BIE FL_ATIM_EnableIT_Break + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableIT_Break(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, ATIM_DIER_BIE_Msk); +} + +/** + * @brief 读取刹车事件中断使能状态 + * @note + * @rmtoll DIER BIE FL_ATIM_IsEnabledIT_Break + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledIT_Break(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, ATIM_DIER_BIE_Msk) == ATIM_DIER_BIE_Msk); +} + +/** + * @brief 刹车事件中断禁用 + * @note + * @rmtoll DIER BIE FL_ATIM_DisableIT_Break + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableIT_Break(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, ATIM_DIER_BIE_Msk); +} + +/** + * @brief 触发事件中断使能 + * @rmtoll DIER TIE FL_ATIM_EnableIT_Trigger + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableIT_Trigger(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, ATIM_DIER_TIE_Msk); +} + +/** + * @brief 读取触发事件中断使能 + * @rmtoll DIER TIE FL_ATIM_IsEnabledIT_Trigger + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledIT_Trigger(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, ATIM_DIER_TIE_Msk) == ATIM_DIER_TIE_Msk); +} + +/** + * @brief 触发事件中断禁用 + * @rmtoll DIER TIE FL_ATIM_DisableIT_Trigger + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableIT_Trigger(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, ATIM_DIER_TIE_Msk); +} + +/** + * @brief COM事件中断使能 + * @note + * @rmtoll DIER COMIE FL_ATIM_EnableIT_COM + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableIT_COM(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, ATIM_DIER_COMIE_Msk); +} + +/** + * @brief 读取COM事件中断使能状态 + * @note + * @rmtoll DIER COMIE FL_ATIM_IsEnabledIT_COM + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledIT_COM(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, ATIM_DIER_COMIE_Msk) == ATIM_DIER_COMIE_Msk); +} + +/** + * @brief COM事件中断禁用 + * @note + * @rmtoll DIER COMIE FL_ATIM_DisableIT_COM + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableIT_COM(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, ATIM_DIER_COMIE_Msk); +} + +/** + * @brief 捕捉/比较通道中断使能 + * @rmtoll DIER CCIE FL_ATIM_EnableIT_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableIT_CC(ATIM_Type *TIMx, uint32_t channel) +{ + SET_BIT(TIMx->DIER, ATIM_DIER_CCIE_Msk << channel); +} + +/** + * @brief 读取捕捉/比较通道中断使能状态 + * @rmtoll DIER CCIE FL_ATIM_IsEnabledIT_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledIT_CC(ATIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, (ATIM_DIER_CCIE_Msk << channel)) == (ATIM_DIER_CCIE_Msk << channel)); +} + +/** + * @brief 捕捉/比较通道中断禁用 + * @rmtoll DIER CCIE FL_ATIM_DisableIT_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableIT_CC(ATIM_Type *TIMx, uint32_t channel) +{ + CLEAR_BIT(TIMx->DIER, ATIM_DIER_CCIE_Msk << channel); +} + +/** + * @brief 更新事件中断使能 + * @rmtoll DIER UIE FL_ATIM_EnableIT_Update + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableIT_Update(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, ATIM_DIER_UIE_Msk); +} + +/** + * @brief 读取更新事件中断使能状态 + * @rmtoll DIER UIE FL_ATIM_IsEnabledIT_Update + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledIT_Update(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, ATIM_DIER_UIE_Msk) == ATIM_DIER_UIE_Msk); +} + +/** + * @brief 更新事件中断禁用 + * @rmtoll DIER UIE FL_ATIM_DisableIT_Update + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableIT_Update(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, ATIM_DIER_UIE_Msk); +} + +/** + * @brief 捕捉/比较通道的Overcapture中断标志 + * @rmtoll ISR CCOF FL_ATIM_IsActiveFlag_CCOverflow + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsActiveFlag_CCOverflow(ATIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->ISR, (ATIM_ISR_CCOF_Msk << channel)) == (ATIM_ISR_CCOF_Msk << channel)); +} + +/** + * @brief 清除Overcapture中断标志 + * @rmtoll ISR CCOF FL_ATIM_ClearFlag_CCOverflow + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_ClearFlag_CCOverflow(ATIM_Type *TIMx, uint32_t channel) +{ + WRITE_REG(TIMx->ISR, (ATIM_ISR_CCOF_Msk << channel)); +} + +/** + * @brief 读取刹车事件中断标志 + * @note + * @rmtoll ISR BIF FL_ATIM_IsActiveFlag_Break + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsActiveFlag_Break(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ISR, ATIM_ISR_BIF_Msk) == (ATIM_ISR_BIF_Msk)); +} + +/** + * @brief 清除刹车事件中断标志 + * @note + * @rmtoll ISR BIF FL_ATIM_ClearFlag_Break + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_ClearFlag_Break(ATIM_Type *TIMx) +{ + WRITE_REG(TIMx->ISR, ATIM_ISR_BIF_Msk); +} + +/** + * @brief 触发事件中断标志 + * @rmtoll ISR TIF FL_ATIM_IsActiveFlag_Trigger + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsActiveFlag_Trigger(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ISR, ATIM_ISR_TIF_Msk) == (ATIM_ISR_TIF_Msk)); +} + +/** + * @brief 清除触发事件中断标志 + * @rmtoll ISR TIF FL_ATIM_ClearFlag_Trigger + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_ClearFlag_Trigger(ATIM_Type *TIMx) +{ + WRITE_REG(TIMx->ISR, ATIM_ISR_TIF_Msk); +} + +/** + * @brief 读取COM事件中断标志 + * @note + * @rmtoll ISR COMIF FL_ATIM_IsActiveFlag_COM + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsActiveFlag_COM(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ISR, ATIM_ISR_COMIF_Msk) == (ATIM_ISR_COMIF_Msk)); +} + +/** + * @brief 清除COM事件中断标志 + * @note + * @rmtoll ISR COMIF FL_ATIM_ClearFlag_COM + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_ClearFlag_COM(ATIM_Type *TIMx) +{ + WRITE_REG(TIMx->ISR, ATIM_ISR_COMIF_Msk); +} + +/** + * @brief 读取捕捉/比较通道中断标志 + * @rmtoll ISR CCIF FL_ATIM_IsActiveFlag_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsActiveFlag_CC(ATIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->ISR, (ATIM_ISR_CCIF_Msk << channel)) == (ATIM_ISR_CCIF_Msk << channel)); +} + +/** + * @brief 清除捕捉/比较通道中断标志 + * @rmtoll ISR CCIF FL_ATIM_ClearFlag_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_ClearFlag_CC(ATIM_Type *TIMx, uint32_t channel) +{ + WRITE_REG(TIMx->ISR, (ATIM_ISR_CCIF_Msk << channel)); +} + +/** + * @brief 读取更新事件中断标志 + * @rmtoll ISR UIF FL_ATIM_IsActiveFlag_Update + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsActiveFlag_Update(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ISR, ATIM_ISR_UIF_Msk) == (ATIM_ISR_UIF_Msk)); +} + +/** + * @brief 清除更新事件中断标志 + * @rmtoll ISR UIF FL_ATIM_ClearFlag_Update + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_ClearFlag_Update(ATIM_Type *TIMx) +{ + WRITE_REG(TIMx->ISR, ATIM_ISR_UIF_Msk); +} + +/** + * @brief 软件刹车使能 + * @note + * @rmtoll EGR BG FL_ATIM_GenerateBreakEvent + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_GenerateBreakEvent(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->EGR, ATIM_EGR_BG_Msk); +} + +/** + * @brief 软件触发使能 + * @rmtoll EGR TG FL_ATIM_GenerateTriggerEvent + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_GenerateTriggerEvent(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->EGR, ATIM_EGR_TG_Msk); +} + +/** + * @brief 软件COM事件使能 + * @note + * @rmtoll EGR COMG FL_ATIM_GenerateCOMEvent + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_GenerateCOMEvent(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->EGR, ATIM_EGR_COMG_Msk); +} + +/** + * @brief 捕捉/比较通道软件触发使能 + * @rmtoll EGR CCG FL_ATIM_GenerateCCEvent + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_GenerateCCEvent(ATIM_Type *TIMx, uint32_t channel) +{ + SET_BIT(TIMx->EGR, ATIM_EGR_CCG_Msk << channel); +} + +/** + * @brief 软件更新事件使能 + * @rmtoll EGR UG FL_ATIM_GenerateUpdateEvent + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_GenerateUpdateEvent(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->EGR, ATIM_EGR_UG_Msk); +} + +/** + * @brief 设置计数器值 + * @rmtoll CNT FL_ATIM_WriteCounter + * @param TIMx TIM instance + * @param counter + * @retval None + */ +__STATIC_INLINE void FL_ATIM_WriteCounter(ATIM_Type *TIMx, uint32_t counter) +{ + MODIFY_REG(TIMx->CNT, (0xffffU << 0U), (counter << 0U)); +} + +/** + * @brief 读取计数器值 + * @rmtoll CNT FL_ATIM_ReadCounter + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_ATIM_ReadCounter(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CNT, 0xffffU) >> 0U); +} + +/** + * @brief 设置计数器时钟预分频值 + * @rmtoll PSC FL_ATIM_WritePrescaler + * @param TIMx TIM instance + * @param psc + * @retval None + */ +__STATIC_INLINE void FL_ATIM_WritePrescaler(ATIM_Type *TIMx, uint32_t psc) +{ + MODIFY_REG(TIMx->PSC, (0xffffU << 0U), (psc << 0U)); +} + +/** + * @brief 读取计数器时钟预分频值 + * @rmtoll PSC FL_ATIM_ReadPrescaler + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_ATIM_ReadPrescaler(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->PSC, 0xffffU) >> 0U); +} + +/** + * @brief 设置计数溢出时的自动重载值 + * @rmtoll ARR FL_ATIM_WriteAutoReload + * @param TIMx TIM instance + * @param autoReload + * @retval None + */ +__STATIC_INLINE void FL_ATIM_WriteAutoReload(ATIM_Type *TIMx, uint32_t autoReload) +{ + MODIFY_REG(TIMx->ARR, (0xffffU << 0U), (autoReload << 0U)); +} + +/** + * @brief 读取计数溢出时的自动重载值 + * @rmtoll ARR FL_ATIM_ReadAutoReload + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_ATIM_ReadAutoReload(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ARR, 0xffffU) >> 0U); +} + +/** + * @brief 捕捉/比较通道1寄存器配置 + * @rmtoll CCR1 FL_ATIM_WriteCompareCH1 + * @param TIMx TIM instance + * @param compareValue + * @retval None + */ +__STATIC_INLINE void FL_ATIM_WriteCompareCH1(ATIM_Type *TIMx, uint32_t compareValue) +{ + MODIFY_REG(TIMx->CCR1, (0xffffU << 0U), (compareValue << 0U)); +} + +/** + * @brief 读取捕捉/比较通道1寄存器值 + * @rmtoll CCR1 FL_ATIM_ReadCompareCH1 + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_ATIM_ReadCompareCH1(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR1, 0xffffU) >> 0U); +} + +/** + * @brief 捕捉/比较通道2寄存器配置 + * @rmtoll CCR2 FL_ATIM_WriteCompareCH2 + * @param TIMx TIM instance + * @param compareValue + * @retval None + */ +__STATIC_INLINE void FL_ATIM_WriteCompareCH2(ATIM_Type *TIMx, uint32_t compareValue) +{ + MODIFY_REG(TIMx->CCR2, (0xffffU << 0U), (compareValue << 0U)); +} + +/** + * @brief 读取捕捉/比较通道2寄存器值 + * @rmtoll CCR2 FL_ATIM_ReadCompareCH2 + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_ATIM_ReadCompareCH2(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR2, 0xffffU) >> 0U); +} + +/** + * @brief 捕捉/比较通道3寄存器配置 + * @rmtoll CCR3 FL_ATIM_WriteCompareCH3 + * @param TIMx TIM instance + * @param compareValue + * @retval None + */ +__STATIC_INLINE void FL_ATIM_WriteCompareCH3(ATIM_Type *TIMx, uint32_t compareValue) +{ + MODIFY_REG(TIMx->CCR3, (0xffffU << 0U), (compareValue << 0U)); +} + +/** + * @brief 读取捕捉/比较通道3寄存器值 + * @rmtoll CCR3 FL_ATIM_ReadCompareCH3 + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_ATIM_ReadCompareCH3(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR3, 0xffffU) >> 0U); +} + +/** + * @brief 捕捉/比较通道4寄存器配置 + * @rmtoll CCR4 FL_ATIM_WriteCompareCH4 + * @param TIMx TIM instance + * @param compareValue + * @retval None + */ +__STATIC_INLINE void FL_ATIM_WriteCompareCH4(ATIM_Type *TIMx, uint32_t compareValue) +{ + MODIFY_REG(TIMx->CCR4, (0xffffU << 0U), (compareValue << 0U)); +} + +/** + * @brief 读取捕捉/比较通道4寄存器值 + * @rmtoll CCR4 FL_ATIM_ReadCompareCH4 + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_ATIM_ReadCompareCH4(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR4, 0xffffU) >> 0U); +} + +/** + * @brief 设置DMA Burst长度 + * @rmtoll DCR DBL FL_ATIM_SetDMABurstLength + * @param TIMx TIM instance + * @param length This parameter can be one of the following values: + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_1 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_2 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_3 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_4 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_5 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_6 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_7 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_8 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_9 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_10 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_11 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_12 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_13 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_14 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_15 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_16 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_17 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_18 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetDMABurstLength(ATIM_Type *TIMx, uint32_t length) +{ + MODIFY_REG(TIMx->DCR, ATIM_DCR_DBL_Msk, length); +} + +/** + * @brief 读取DMA Burst长度 + * @rmtoll DCR DBL FL_ATIM_GetDMABurstLength + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_1 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_2 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_3 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_4 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_5 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_6 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_7 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_8 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_9 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_10 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_11 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_12 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_13 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_14 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_15 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_16 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_17 + * @arg @ref FL_ATIM_DMA_BURST_LENGTH_18 + */ +__STATIC_INLINE uint32_t FL_ATIM_GetDMABurstLength(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DCR, ATIM_DCR_DBL_Msk)); +} + +/** + * @brief 设置指向DMA寄存器的偏移地址 + * @rmtoll DCR DBA FL_ATIM_SetDMABurstAddress + * @param TIMx TIM instance + * @param address This parameter can be one of the following values: + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CR1 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CR2 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_SMCR + * @arg @ref FL_ATIM_DMA_BURST_ADDR_DIER + * @arg @ref FL_ATIM_DMA_BURST_ADDR_SR + * @arg @ref FL_ATIM_DMA_BURST_ADDR_EGR + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CCMR1 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CCMR2 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CCER + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CNT + * @arg @ref FL_ATIM_DMA_BURST_ADDR_PSC + * @arg @ref FL_ATIM_DMA_BURST_ADDR_ARR + * @arg @ref FL_ATIM_DMA_BURST_ADDR_RCR + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CCR1 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CCR2 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CCR3 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CCR4 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_BDTR + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetDMABurstAddress(ATIM_Type *TIMx, uint32_t address) +{ + MODIFY_REG(TIMx->DCR, ATIM_DCR_DBA_Msk, address); +} + +/** + * @brief 读取指向DMA寄存器的偏移地址 + * @rmtoll DCR DBA FL_ATIM_GetDMABurstAddress + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CR1 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CR2 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_SMCR + * @arg @ref FL_ATIM_DMA_BURST_ADDR_DIER + * @arg @ref FL_ATIM_DMA_BURST_ADDR_SR + * @arg @ref FL_ATIM_DMA_BURST_ADDR_EGR + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CCMR1 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CCMR2 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CCER + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CNT + * @arg @ref FL_ATIM_DMA_BURST_ADDR_PSC + * @arg @ref FL_ATIM_DMA_BURST_ADDR_ARR + * @arg @ref FL_ATIM_DMA_BURST_ADDR_RCR + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CCR1 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CCR2 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CCR3 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_CCR4 + * @arg @ref FL_ATIM_DMA_BURST_ADDR_BDTR + */ +__STATIC_INLINE uint32_t FL_ATIM_GetDMABurstAddress(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DCR, ATIM_DCR_DBA_Msk)); +} + +/** + * @brief 配置DMA burst访问寄存器 + * @rmtoll DMAR FL_ATIM_WriteDMAAddress + * @param TIMx TIM instance + * @param address + * @retval None + */ +__STATIC_INLINE void FL_ATIM_WriteDMAAddress(ATIM_Type *TIMx, uint32_t address) +{ + MODIFY_REG(TIMx->DMAR, (0xffffU << 0U), (address << 0U)); +} + +/** + * @brief 读取DMA burst访问寄存器值 + * @rmtoll DMAR FL_ATIM_ReadDMAAddress + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_ATIM_ReadDMAAddress(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DMAR, 0xffffU) >> 0U); +} + +/** + * @brief 输出比较清零使能 + * @rmtoll CCMR OCCE FL_ATIM_OC_EnableClear + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_EnableClear(ATIM_Type *TIMx, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + SET_BIT(TIMx->CCMR1, (ATIM_CCMR_OCCE_Msk << (channel * 8))); + } + else + { + SET_BIT(TIMx->CCMR2, (ATIM_CCMR_OCCE_Msk << ((channel - 2) * 8))); + } +} + +/** + * @brief 读取输出比较清零使能状态 + * @rmtoll CCMR OCCE FL_ATIM_OC_IsEnabledClear + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_OC_IsEnabledClear(ATIM_Type *TIMx, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + return (uint32_t)(READ_BIT(TIMx->CCMR1, (ATIM_CCMR_OCCE_Msk << (channel * 8))) == (ATIM_CCMR_OCCE_Msk << (channel * 8))); + } + else + { + return (uint32_t)(READ_BIT(TIMx->CCMR2, (ATIM_CCMR_OCCE_Msk << ((channel - 2) * 8))) == (ATIM_CCMR_OCCE_Msk << ((channel - 2) * 8))); + } +} + +/** + * @brief 输出比较清零禁用 + * @rmtoll CCMR OCCE FL_ATIM_OC_DisableClear + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_DisableClear(ATIM_Type *TIMx, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + CLEAR_BIT(TIMx->CCMR1, (ATIM_CCMR_OCCE_Msk << (channel * 8))); + } + else + { + CLEAR_BIT(TIMx->CCMR2, (ATIM_CCMR_OCCE_Msk << ((channel - 2) * 8))); + } +} + +/** + * @brief 输出比较模式配置 + * @rmtoll CCMR OCM FL_ATIM_OC_SetMode + * @param TIMx TIM instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_ATIM_OC_MODE_FROZEN + * @arg @ref FL_ATIM_OC_MODE_ACTIVE + * @arg @ref FL_ATIM_OC_MODE_INACTIVE + * @arg @ref FL_ATIM_OC_MODE_TOGGLE + * @arg @ref FL_ATIM_OC_MODE_FORCED_INACTIVE + * @arg @ref FL_ATIM_OC_MODE_FORCED_ACTIVE + * @arg @ref FL_ATIM_OC_MODE_PWM1 + * @arg @ref FL_ATIM_OC_MODE_PWM2 + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_SetMode(ATIM_Type *TIMx, uint32_t mode, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + MODIFY_REG(TIMx->CCMR1, (ATIM_CCMR_OCM_Msk << (channel * 8)), (mode << (channel * 8))); + } + else + { + MODIFY_REG(TIMx->CCMR2, (ATIM_CCMR_OCM_Msk << ((channel - 2) * 8)), (mode << ((channel - 2) * 8))); + } +} + +/** + * @brief 读取输出比较模式配置值 + * @rmtoll CCMR OCM FL_ATIM_OC_GetMode + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_OC_MODE_FROZEN + * @arg @ref FL_ATIM_OC_MODE_ACTIVE + * @arg @ref FL_ATIM_OC_MODE_INACTIVE + * @arg @ref FL_ATIM_OC_MODE_TOGGLE + * @arg @ref FL_ATIM_OC_MODE_FORCED_INACTIVE + * @arg @ref FL_ATIM_OC_MODE_FORCED_ACTIVE + * @arg @ref FL_ATIM_OC_MODE_PWM1 + * @arg @ref FL_ATIM_OC_MODE_PWM2 + */ +__STATIC_INLINE uint32_t FL_ATIM_OC_GetMode(ATIM_Type *TIMx, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + return (uint32_t)(READ_BIT(TIMx->CCMR1, (ATIM_CCMR_OCM_Msk << (channel * 8)))); + } + else + { + return (uint32_t)(READ_BIT(TIMx->CCMR2, (ATIM_CCMR_OCM_Msk << ((channel - 2) * 8)))); + } +} + +/** + * @brief 输出比较预装载使能 + * @rmtoll CCMR OCPE FL_ATIM_OC_EnablePreload + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_EnablePreload(ATIM_Type *TIMx, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + SET_BIT(TIMx->CCMR1, (ATIM_CCMR_OCPE_Msk << (channel * 8))); + } + else + { + SET_BIT(TIMx->CCMR2, (ATIM_CCMR_OCPE_Msk << ((channel - 2) * 8))); + } +} + +/** + * @brief 读取输出比较预装载使能状态 + * @rmtoll CCMR OCPE FL_ATIM_OC_IsEnabledPreload + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_OC_IsEnabledPreload(ATIM_Type *TIMx, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + return (uint32_t)(READ_BIT(TIMx->CCMR1, (ATIM_CCMR_OCPE_Msk << (channel * 8))) == (ATIM_CCMR_OCPE_Msk << (channel * 8))); + } + else + { + return (uint32_t)(READ_BIT(TIMx->CCMR2, (ATIM_CCMR_OCPE_Msk << ((channel - 2) * 8))) == (ATIM_CCMR_OCPE_Msk << ((channel - 2) * 8))); + } +} + +/** + * @brief 输出比较预装载禁用 + * @rmtoll CCMR OCPE FL_ATIM_OC_DisablePreload + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_DisablePreload(ATIM_Type *TIMx, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + CLEAR_BIT(TIMx->CCMR1, (ATIM_CCMR_OCPE_Msk << (channel * 8))); + } + else + { + CLEAR_BIT(TIMx->CCMR2, (ATIM_CCMR_OCPE_Msk << ((channel - 2) * 8))); + } +} + +/** + * @brief 输出比较快速使能 + * @rmtoll CCMR OCFE FL_ATIM_OC_EnableFastMode + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_EnableFastMode(ATIM_Type *TIMx, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + SET_BIT(TIMx->CCMR1, (ATIM_CCMR_OCFE_Msk << (channel * 8))); + } + else + { + SET_BIT(TIMx->CCMR2, (ATIM_CCMR_OCFE_Msk << ((channel - 2) * 8))); + } +} + +/** + * @brief 获取输出比较快速使能状态 + * @rmtoll CCMR OCFE FL_ATIM_OC_IsEnabledFastMode + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_OC_IsEnabledFastMode(ATIM_Type *TIMx, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + return (uint32_t)(READ_BIT(TIMx->CCMR1, (ATIM_CCMR_OCFE_Msk << (channel * 8))) == (ATIM_CCMR_OCFE_Msk << (channel * 8))); + } + else + { + return (uint32_t)(READ_BIT(TIMx->CCMR2, (ATIM_CCMR_OCFE_Msk << ((channel - 2) * 8))) == (ATIM_CCMR_OCFE_Msk << ((channel - 2) * 8))); + } +} + +/** + * @brief 输出比较快速禁用 + * @rmtoll CCMR OCFE FL_ATIM_OC_DisableFastMode + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_DisableFastMode(ATIM_Type *TIMx, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + CLEAR_BIT(TIMx->CCMR1, (ATIM_CCMR_OCFE_Msk << (channel * 8))); + } + else + { + CLEAR_BIT(TIMx->CCMR2, (ATIM_CCMR_OCFE_Msk << ((channel - 2) * 8))); + } +} + +/** + * @brief 设置输入捕捉滤波器 + * @rmtoll CCMR ICF FL_ATIM_IC_SetFilter + * @param TIMx TIM instance + * @param filter This parameter can be one of the following values: + * @arg @ref FL_ATIM_IC_FILTER_DIV1 + * @arg @ref FL_ATIM_IC_FILTER_DIV1_N2 + * @arg @ref FL_ATIM_IC_FILTER_DIV1_N4 + * @arg @ref FL_ATIM_IC_FILTER_DIV1_N8 + * @arg @ref FL_ATIM_IC_FILTER_DIV2_N6 + * @arg @ref FL_ATIM_IC_FILTER_DIV2_N8 + * @arg @ref FL_ATIM_IC_FILTER_DIV4_N6 + * @arg @ref FL_ATIM_IC_FILTER_DIV4_N8 + * @arg @ref FL_ATIM_IC_FILTER_DIV8_N6 + * @arg @ref FL_ATIM_IC_FILTER_DIV8_N8 + * @arg @ref FL_ATIM_IC_FILTER_DIV16_N5 + * @arg @ref FL_ATIM_IC_FILTER_DIV16_N6 + * @arg @ref FL_ATIM_IC_FILTER_DIV16_N8 + * @arg @ref FL_ATIM_IC_FILTER_DIV32_N5 + * @arg @ref FL_ATIM_IC_FILTER_DIV32_N6 + * @arg @ref FL_ATIM_IC_FILTER_DIV32_N8 + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_IC_SetFilter(ATIM_Type *TIMx, uint32_t filter, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + MODIFY_REG(TIMx->CCMR1, (ATIM_CCMR_ICF_Msk << (channel * 8)), (filter << (channel * 8))); + } + else + { + MODIFY_REG(TIMx->CCMR2, (ATIM_CCMR_ICF_Msk << ((channel - 2) * 8)), (filter << ((channel - 2) * 8))); + } +} + +/** + * @brief 读取输入滤波器值 + * @rmtoll CCMR ICF FL_ATIM_IC_GetFilter + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_IC_FILTER_DIV1 + * @arg @ref FL_ATIM_IC_FILTER_DIV1_N2 + * @arg @ref FL_ATIM_IC_FILTER_DIV1_N4 + * @arg @ref FL_ATIM_IC_FILTER_DIV1_N8 + * @arg @ref FL_ATIM_IC_FILTER_DIV2_N6 + * @arg @ref FL_ATIM_IC_FILTER_DIV2_N8 + * @arg @ref FL_ATIM_IC_FILTER_DIV4_N6 + * @arg @ref FL_ATIM_IC_FILTER_DIV4_N8 + * @arg @ref FL_ATIM_IC_FILTER_DIV8_N6 + * @arg @ref FL_ATIM_IC_FILTER_DIV8_N8 + * @arg @ref FL_ATIM_IC_FILTER_DIV16_N5 + * @arg @ref FL_ATIM_IC_FILTER_DIV16_N6 + * @arg @ref FL_ATIM_IC_FILTER_DIV16_N8 + * @arg @ref FL_ATIM_IC_FILTER_DIV32_N5 + * @arg @ref FL_ATIM_IC_FILTER_DIV32_N6 + * @arg @ref FL_ATIM_IC_FILTER_DIV32_N8 + */ +__STATIC_INLINE uint32_t FL_ATIM_IC_GetFilter(ATIM_Type *TIMx, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + return (uint32_t)(READ_BIT(TIMx->CCMR1, (ATIM_CCMR_ICF_Msk << (channel * 8)))); + } + else + { + return (uint32_t)(READ_BIT(TIMx->CCMR2, (ATIM_CCMR_ICF_Msk << ((channel - 2) * 8)))); + } +} + +/** + * @brief 设置输入捕捉预分频 + * @rmtoll CCMR ICPSC FL_ATIM_IC_SetPrescaler + * @param TIMx TIM instance + * @param psc This parameter can be one of the following values: + * @arg @ref FL_ATIM_IC_PSC_DIV1 + * @arg @ref FL_ATIM_IC_PSC_DIV2 + * @arg @ref FL_ATIM_IC_PSC_DIV4 + * @arg @ref FL_ATIM_IC_PSC_DIV8 + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_IC_SetPrescaler(ATIM_Type *TIMx, uint32_t psc, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + MODIFY_REG(TIMx->CCMR1, (ATIM_CCMR_ICPSC_Msk << (channel * 8)), (psc << (channel * 8))); + } + else + { + MODIFY_REG(TIMx->CCMR2, (ATIM_CCMR_ICPSC_Msk << ((channel - 2) * 8)), (psc << ((channel - 2) * 8))); + } +} + +/** + * @brief 读取输入捕捉预分频值 + * @rmtoll CCMR ICPSC FL_ATIM_IC_GetPrescaler + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_IC_PSC_DIV1 + * @arg @ref FL_ATIM_IC_PSC_DIV2 + * @arg @ref FL_ATIM_IC_PSC_DIV4 + * @arg @ref FL_ATIM_IC_PSC_DIV8 + */ +__STATIC_INLINE uint32_t FL_ATIM_IC_GetPrescaler(ATIM_Type *TIMx, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + return (uint32_t)(READ_BIT(TIMx->CCMR1, (ATIM_CCMR_ICPSC_Msk << (channel * 8)))); + } + else + { + return (uint32_t)(READ_BIT(TIMx->CCMR2, (ATIM_CCMR_ICPSC_Msk << ((channel - 2) * 8)))); + } +} + +/** + * @brief 捕捉/比较通道选择 + * @rmtoll CCMR CCS FL_ATIM_CC_SetChannelMode + * @param TIMx TIM instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_MODE_OUTPUT + * @arg @ref FL_ATIM_CHANNEL_MODE_INPUT_NORMAL + * @arg @ref FL_ATIM_CHANNEL_MODE_INPUT_CROSSOVER + * @arg @ref FL_ATIM_CHANNEL_MODE_INPUT_TRC + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_CC_SetChannelMode(ATIM_Type *TIMx, uint32_t mode, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + MODIFY_REG(TIMx->CCMR1, (ATIM_CCMR_CCS_Msk << (channel * 8)), (mode << (channel * 8))); + } + else + { + MODIFY_REG(TIMx->CCMR2, (ATIM_CCMR_CCS_Msk << ((channel - 2) * 8)), (mode << ((channel - 2) * 8))); + } +} + +/** + * @brief 获取捕捉/比较通道 + * @rmtoll CCMR CCS FL_ATIM_CC_GetChannelMode + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_MODE_OUTPUT + * @arg @ref FL_ATIM_CHANNEL_MODE_INPUT_NORMAL + * @arg @ref FL_ATIM_CHANNEL_MODE_INPUT_CROSSOVER + * @arg @ref FL_ATIM_CHANNEL_MODE_INPUT_TRC + */ +__STATIC_INLINE uint32_t FL_ATIM_CC_GetChannelMode(ATIM_Type *TIMx, uint32_t channel) +{ + if(channel < FL_ATIM_CHANNEL_3) + { + return (uint32_t)(READ_BIT(TIMx->CCMR1, (ATIM_CCMR_CCS_Msk << (channel * 8)))); + } + else + { + return (uint32_t)(READ_BIT(TIMx->CCMR2, (ATIM_CCMR_CCS_Msk << ((channel - 2) * 8)))); + } +} + +/** + * @brief 设置捕捉/比较互补输出极性 + * @note + * @rmtoll CCER CCNP FL_ATIM_OC_SetReverseChannelPolarity + * @param TIMx TIM instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_ATIM_OCN_POLARITY_NORMAL + * @arg @ref FL_ATIM_OCN_POLARITY_INVERT + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_SetReverseChannelPolarity(ATIM_Type *TIMx, uint32_t polarity, uint32_t channel) +{ + MODIFY_REG(TIMx->CCER, (ATIM_CCER_CCNP_Msk << (channel * 4)), (polarity << (channel * 4))); +} + +/** + * @brief 读取捕捉/比较互补输出极性 + * @note + * @rmtoll CCER CCNP FL_ATIM_OC_GetReverseChannelPolarty + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_OCN_POLARITY_NORMAL + * @arg @ref FL_ATIM_OCN_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_ATIM_OC_GetReverseChannelPolarity(ATIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->CCER, (ATIM_CCER_CCNP_Msk << (channel * 4)))); +} + +/** + * @brief 捕捉/比较互补输出使能 + * @note + * @rmtoll CCER CCNE FL_ATIM_OC_EnableReverseChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_EnableReverseChannel(ATIM_Type *TIMx, uint32_t channel) +{ + SET_BIT(TIMx->CCER, (ATIM_CCER_CCNE_Msk << (channel * 4))); +} + +/** + * @brief 读取捕捉/比较互补输出使能状态 + * @note + * @rmtoll CCER CCNE FL_ATIM_OC_IsEnabledReverseChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_OC_IsEnabledReverseChannel(ATIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->CCER, (ATIM_CCER_CCNE_Msk << (channel * 4))) == (ATIM_CCER_CCNE_Msk << (channel * 4))); +} + +/** + * @brief 捕捉/比较互补输出禁用 + * @note + * @rmtoll CCER CCNE FL_ATIM_OC_DisableReverseChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_DisableReverseChannel(ATIM_Type *TIMx, uint32_t channel) +{ + CLEAR_BIT(TIMx->CCER, (ATIM_CCER_CCNE_Msk << (channel * 4))); +} + +/** + * @brief CC1通道配置为输出时，设置捕捉/比较输出极性 + * @rmtoll CCER CCOP FL_ATIM_OC_SetChannelPolarity + * @param TIMx TIM instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_ATIM_OC_POLARITY_NORMAL + * @arg @ref FL_ATIM_OC_POLARITY_INVERT + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_SetChannelPolarity(ATIM_Type *TIMx, uint32_t polarity, uint32_t channel) +{ + MODIFY_REG(TIMx->CCER, (ATIM_CCER_CCOP_Msk << (channel * 4)), (polarity << (channel * 4))); +} + +/** + * @brief CC1通道配置为输出时，读取捕捉/比较输出极性 + * @rmtoll CCER CCOP FL_ATIM_OC_GetChannelPolarity + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_OC_POLARITY_NORMAL + * @arg @ref FL_ATIM_OC_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_ATIM_OC_GetChannelPolarity(ATIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->CCER, (ATIM_CCER_CCOP_Msk << (channel * 4)))); +} + +/** + * @brief CC1通道配置为输入时，设置捕捉/比较输出极性 + * @rmtoll CCER CCIP FL_ATIM_IC_SetChannelPolarity + * @param TIMx TIM instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_ATIM_IC_POLARITY_NORMAL + * @arg @ref FL_ATIM_IC_POLARITY_INVERT + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_IC_SetChannelPolarity(ATIM_Type *TIMx, uint32_t polarity, uint32_t channel) +{ + MODIFY_REG(TIMx->CCER, (ATIM_CCER_CCIP_Msk << (channel * 4)), (polarity << (channel * 4))); +} + +/** + * @brief CC1通道配置为输入时，设置捕捉/比较输出极性 + * @rmtoll CCER CCIP FL_ATIM_IC_GetChannelPolarity + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_IC_POLARITY_NORMAL + * @arg @ref FL_ATIM_IC_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_ATIM_IC_GetChannelPolarity(ATIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->CCER, (ATIM_CCER_CCIP_Msk << (channel * 4)))); +} + +/** + * @brief CC1通道配置为输出时，捕捉/比较输出使能 + * @rmtoll CCER CCOE FL_ATIM_OC_EnableChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_EnableChannel(ATIM_Type *TIMx, uint32_t channel) +{ + SET_BIT(TIMx->CCER, (ATIM_CCER_CCOE_Msk << (channel * 4))); +} + +/** + * @brief CC1通道配置为输出时，读取捕捉/比较输出使能状态 + * @rmtoll CCER CCOE FL_ATIM_OC_IsEnabledChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_OC_IsEnabledChannel(ATIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->CCER, (ATIM_CCER_CCOE_Msk << (channel * 4))) == (ATIM_CCER_CCOE_Msk << (channel * 4))); +} + +/** + * @brief CC1通道配置为输出时，捕捉/比较输出禁用 + * @rmtoll CCER CCOE FL_ATIM_OC_DisableChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_OC_DisableChannel(ATIM_Type *TIMx, uint32_t channel) +{ + CLEAR_BIT(TIMx->CCER, (ATIM_CCER_CCOE_Msk << (channel * 4))); +} + +/** + * @brief CC1通道配置为输入时，捕捉/比较输出使能 + * @rmtoll CCER CCIE FL_ATIM_IC_EnableChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_IC_EnableChannel(ATIM_Type *TIMx, uint32_t channel) +{ + SET_BIT(TIMx->CCER, (ATIM_CCER_CCIE_Msk << (channel * 4))); +} + +/** + * @brief CC1通道配置为输入时，读取捕捉/比较输出使能状态 + * @rmtoll CCER CCIE FL_ATIM_IC_IsEnabledChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IC_IsEnabledChannel(ATIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->CCER, (ATIM_CCER_CCIE_Msk << (channel * 4))) == (ATIM_CCER_CCIE_Msk << (channel * 4))); +} + +/** + * @brief CC1通道配置为输入时，捕捉/比较输出禁用 + * @rmtoll CCER CCIE FL_ATIM_IC_DisableChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_IC_DisableChannel(ATIM_Type *TIMx, uint32_t channel) +{ + CLEAR_BIT(TIMx->CCER, (ATIM_CCER_CCIE_Msk << (channel * 4))); +} + +/** + * @brief 设置重复计数值 + * @note + * @rmtoll RCR FL_ATIM_WriteRepetitionCounter + * @param TIMx TIM instance + * @param repeatCounter + * @retval None + */ +__STATIC_INLINE void FL_ATIM_WriteRepetitionCounter(ATIM_Type *TIMx, uint32_t repeatCounter) +{ + MODIFY_REG(TIMx->RCR, (0xffU << 0U), (repeatCounter << 0U)); +} + +/** + * @brief 读取重复计数值 + * @note + * @rmtoll RCR FL_ATIM_ReadRepetitionCounter + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_ATIM_ReadRepetitionCounter(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->RCR, 0xffU) >> 0U); +} + +/** + * @brief 主控输出使能 + * @note + * @rmtoll BDTR MOE FL_ATIM_EnableALLOutput + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableALLOutput(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->BDTR, ATIM_BDTR_MOE_Msk); +} + +/** + * @brief 读取主控输出使能状态 + * @note + * @rmtoll BDTR MOE FL_ATIM_IsEnabledALLOutput + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledALLOutput(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BDTR, ATIM_BDTR_MOE_Msk) == ATIM_BDTR_MOE_Msk); +} + +/** + * @brief 主控输出禁用 + * @note + * @rmtoll BDTR MOE FL_ATIM_DisableALLOutput + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableALLOutput(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, ATIM_BDTR_MOE_Msk); +} + +/** + * @brief 自动输出使能 + * @note + * @rmtoll BDTR AOE FL_ATIM_EnableAutomaticOutput + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableAutomaticOutput(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->BDTR, ATIM_BDTR_AOE_Msk); +} + +/** + * @brief 读取自动输出使能状态 + * @note + * @rmtoll BDTR AOE FL_ATIM_IsEnabledAutomaticOutput + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledAutomaticOutput(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BDTR, ATIM_BDTR_AOE_Msk) == ATIM_BDTR_AOE_Msk); +} + +/** + * @brief 自动输出禁用 + * @note + * @rmtoll BDTR AOE FL_ATIM_DisableAutomaticOutput + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableAutomaticOutput(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, ATIM_BDTR_AOE_Msk); +} + +/** + * @brief 设置刹车极性 + * @note + * @rmtoll BDTR BKP FL_ATIM_SetBreakPolarity + * @param TIMx TIM instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_ATIM_BREAK_POLARITY_LOW + * @arg @ref FL_ATIM_BREAK_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetBreakPolarity(ATIM_Type *TIMx, uint32_t polarity) +{ + MODIFY_REG(TIMx->BDTR, ATIM_BDTR_BKP_Msk, polarity); +} + +/** + * @brief 读取刹车极性 + * @note + * @rmtoll BDTR BKP FL_ATIM_GetBreakPolarity + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_BREAK_POLARITY_LOW + * @arg @ref FL_ATIM_BREAK_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t FL_ATIM_GetBreakPolarity(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BDTR, ATIM_BDTR_BKP_Msk)); +} + +/** + * @brief 刹车使能 + * @note + * @rmtoll BDTR BKE FL_ATIM_EnableBreak + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableBreak(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->BDTR, ATIM_BDTR_BKE_Msk); +} + +/** + * @brief 读取刹车使能状态 + * @note + * @rmtoll BDTR BKE FL_ATIM_IsEnabledBreak + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledBreak(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BDTR, ATIM_BDTR_BKE_Msk) == ATIM_BDTR_BKE_Msk); +} + +/** + * @brief 刹车禁用 + * @note + * @rmtoll BDTR BKE FL_ATIM_DisableBreak + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableBreak(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, ATIM_BDTR_BKE_Msk); +} + +/** + * @brief 运行状态下的输出关闭状态选择 + * @note + * @rmtoll BDTR OSSR FL_ATIM_SetOffStateRun + * @param TIMx TIM instance + * @param state This parameter can be one of the following values: + * @arg @ref FL_ATIM_OSSR_DISABLE + * @arg @ref FL_ATIM_OSSR_ENABLE + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetOffStateRun(ATIM_Type *TIMx, uint32_t state) +{ + MODIFY_REG(TIMx->BDTR, ATIM_BDTR_OSSR_Msk, state); +} + +/** + * @brief 读取运行状态下的输出关闭状态选择 + * @note + * @rmtoll BDTR OSSR FL_ATIM_GetOffStateRun + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_OSSR_DISABLE + * @arg @ref FL_ATIM_OSSR_ENABLE + */ +__STATIC_INLINE uint32_t FL_ATIM_GetOffStateRun(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BDTR, ATIM_BDTR_OSSR_Msk)); +} + +/** + * @brief IDLE状态下的输出关闭状态选择 + * @note + * @rmtoll BDTR OSSI FL_ATIM_SetOffStateIdle + * @param TIMx TIM instance + * @param state This parameter can be one of the following values: + * @arg @ref FL_ATIM_OSSI_DISABLE + * @arg @ref FL_ATIM_OSSI_ENABLE + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetOffStateIdle(ATIM_Type *TIMx, uint32_t state) +{ + MODIFY_REG(TIMx->BDTR, ATIM_BDTR_OSSI_Msk, state); +} + +/** + * @brief IDLE状态下的输出关闭状态选择 + * @note + * @rmtoll BDTR OSSI FL_ATIM_GetOffStateIdle + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_OSSI_DISABLE + * @arg @ref FL_ATIM_OSSI_ENABLE + */ +__STATIC_INLINE uint32_t FL_ATIM_GetOffStateIdle(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BDTR, ATIM_BDTR_OSSI_Msk)); +} + +/** + * @brief 设置寄存器写保护等级 + * @note + * @rmtoll BDTR LOCK FL_ATIM_SetLockLevel + * @param TIMx TIM instance + * @param lockLevel This parameter can be one of the following values: + * @arg @ref FL_ATIM_LOCK_LEVEL_OFF + * @arg @ref FL_ATIM_LOCK_LEVEL_1 + * @arg @ref FL_ATIM_LOCK_LEVEL_2 + * @arg @ref FL_ATIM_LOCK_LEVEL_3 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetLockLevel(ATIM_Type *TIMx, uint32_t lockLevel) +{ + MODIFY_REG(TIMx->BDTR, ATIM_BDTR_LOCK_Msk, lockLevel); +} + +/** + * @brief 读取寄存器写保护配置状态 + * @note + * @rmtoll BDTR LOCK FL_ATIM_GetLockLevel + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_LOCK_LEVEL_OFF + * @arg @ref FL_ATIM_LOCK_LEVEL_1 + * @arg @ref FL_ATIM_LOCK_LEVEL_2 + * @arg @ref FL_ATIM_LOCK_LEVEL_3 + */ +__STATIC_INLINE uint32_t FL_ATIM_GetLockLevel(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BDTR, ATIM_BDTR_LOCK_Msk)); +} + +/** + * @brief 设置死区时间长度 + * @note + * @rmtoll BDTR DTG FL_ATIM_WriteDeadTime + * @param TIMx TIM instance + * @param deadTime + * @retval None + */ +__STATIC_INLINE void FL_ATIM_WriteDeadTime(ATIM_Type *TIMx, uint32_t deadTime) +{ + MODIFY_REG(TIMx->BDTR, (0xffU << 0U), (deadTime << 0U)); +} + +/** + * @brief 读取死区时间长度 + * @note + * @rmtoll BDTR DTG FL_ATIM_ReadDeadTime + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_ATIM_ReadDeadTime(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BDTR, 0xffU) >> 0U); +} + +/** + * @brief 设置ATIM_BRK1引脚输入门控信号 + * @note + * @rmtoll BKCR BRK1GATE FL_ATIM_SetBreak1GateState + * @param TIMx TIM instance + * @param state This parameter can be one of the following values: + * @arg @ref FL_ATIM_BREAK1_GATE_LOW + * @arg @ref FL_ATIM_BREAK1_GATE_AUTO + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetBreak1GateState(ATIM_Type *TIMx, uint32_t state) +{ + MODIFY_REG(TIMx->BKCR, ATIM_BKCR_BRK1GATE_Msk, state); +} + +/** + * @brief 读取ATIM_BRK1引脚输入门控信号 + * @note + * @rmtoll BKCR BRK1GATE FL_ATIM_GetBreak1GateState + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_BREAK1_GATE_LOW + * @arg @ref FL_ATIM_BREAK1_GATE_AUTO + */ +__STATIC_INLINE uint32_t FL_ATIM_GetBreak1GateState(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BKCR, ATIM_BKCR_BRK1GATE_Msk)); +} + +/** + * @brief 设置ATIM_BRK2引脚输入门控信号 + * @note + * @rmtoll BKCR BRK2GATE FL_ATIM_SetBreak2GateState + * @param TIMx TIM instance + * @param state This parameter can be one of the following values: + * @arg @ref FL_ATIM_BREAK2_GATE_LOW + * @arg @ref FL_ATIM_BREAK2_GATE_AUTO + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetBreak2GateState(ATIM_Type *TIMx, uint32_t state) +{ + MODIFY_REG(TIMx->BKCR, ATIM_BKCR_BRK2GATE_Msk, state); +} + +/** + * @brief 读取ATIM_BRK2引脚输入门控信号 + * @note + * @rmtoll BKCR BRK2GATE FL_ATIM_GetBreak2GateState + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_BREAK2_GATE_LOW + * @arg @ref FL_ATIM_BREAK2_GATE_AUTO + */ +__STATIC_INLINE uint32_t FL_ATIM_GetBreak2GateState(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BKCR, ATIM_BKCR_BRK2GATE_Msk)); +} + +/** + * @brief 设置刹车信号的滤波时钟和长度选择 + * @note + * @rmtoll BKCR BRKF FL_ATIM_SetBreakFilter + * @param TIMx TIM instance + * @param filter This parameter can be one of the following values: + * @arg @ref FL_ATIM_BREAK_FILTER_DIV1 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV1_N2 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV1_N4 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV1_N8 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV2_N6 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV2_N8 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV4_N6 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV4_N8 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV8_N6 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV8_N8 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV16_N5 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV16_N6 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV16_N8 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV32_N5 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV32_N6 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV32_N8 + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetBreakFilter(ATIM_Type *TIMx, uint32_t filter) +{ + MODIFY_REG(TIMx->BKCR, ATIM_BKCR_BRKF_Msk, filter); +} + +/** + * @brief 读取刹车信号的滤波时钟和长度选择 + * @note + * @rmtoll BKCR BRKF FL_ATIM_GetBreakFilter + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_BREAK_FILTER_DIV1 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV1_N2 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV1_N4 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV1_N8 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV2_N6 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV2_N8 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV4_N6 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV4_N8 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV8_N6 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV8_N8 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV16_N5 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV16_N6 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV16_N8 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV32_N5 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV32_N6 + * @arg @ref FL_ATIM_BREAK_FILTER_DIV32_N8 + */ +__STATIC_INLINE uint32_t FL_ATIM_GetBreakFilter(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BKCR, ATIM_BKCR_BRKF_Msk)); +} + +/** + * @brief 刹车组合控制 + * @note + * @rmtoll BKCR BRKCOMB FL_ATIM_SetBreakSignalCombination + * @param TIMx TIM instance + * @param filter This parameter can be one of the following values: + * @arg @ref FL_ATIM_BREAK_COMBINATION_OR + * @arg @ref FL_ATIM_BREAK_COMBINATION_AND + * @retval None + */ +__STATIC_INLINE void FL_ATIM_SetBreakSignalCombination(ATIM_Type *TIMx, uint32_t filter) +{ + MODIFY_REG(TIMx->BKCR, ATIM_BKCR_BRKCOMB_Msk, filter); +} + +/** + * @brief 读取刹车组合控制状态 + * @note + * @rmtoll BKCR BRKCOMB FL_ATIM_GetBreakSignalCombination + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_ATIM_BREAK_COMBINATION_OR + * @arg @ref FL_ATIM_BREAK_COMBINATION_AND + */ +__STATIC_INLINE uint32_t FL_ATIM_GetBreakSignalCombination(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BKCR, ATIM_BKCR_BRKCOMB_Msk)); +} + +/** + * @brief XTHF停振检测刹车信号使能 + * @note + * @rmtoll BKCR HFDET_BRKEN FL_ATIM_EnableHFDETBreak + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableHFDETBreak(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->BKCR, ATIM_BKCR_HFDET_BRKEN_Msk); +} + +/** + * @brief 读取XTHF停振检测刹车信号使能状态 + * @note + * @rmtoll BKCR HFDET_BRKEN FL_ATIM_IsEnabledHFDETBreak + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledHFDETBreak(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BKCR, ATIM_BKCR_HFDET_BRKEN_Msk) == ATIM_BKCR_HFDET_BRKEN_Msk); +} + +/** + * @brief XTHF停振检测刹车信号禁用 + * @note + * @rmtoll BKCR HFDET_BRKEN FL_ATIM_DisableHFDETBreak + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableHFDETBreak(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->BKCR, ATIM_BKCR_HFDET_BRKEN_Msk); +} + +/** + * @brief SVD刹车信号使能 + * @note + * @rmtoll BKCR SVD_BRKEN FL_ATIM_EnableSVDBreak + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableSVDBreak(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->BKCR, ATIM_BKCR_SVD_BRKEN_Msk); +} + +/** + * @brief 读取SVD刹车信号使能状态 + * @note + * @rmtoll BKCR SVD_BRKEN FL_ATIM_IsEnabledSVDBreak + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledSVDBreak(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BKCR, ATIM_BKCR_SVD_BRKEN_Msk) == ATIM_BKCR_SVD_BRKEN_Msk); +} + +/** + * @brief SVD刹车信号禁用 + * @note + * @rmtoll BKCR SVD_BRKEN FL_ATIM_DisableSVDBreak + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableSVDBreak(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->BKCR, ATIM_BKCR_SVD_BRKEN_Msk); +} + +/** + * @brief 比较器输出刹车信号使能 + * @note + * @rmtoll BKCR COMP_BRKEN FL_ATIM_EnableCOMPBreak + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_EnableCOMPBreak(ATIM_Type *TIMx) +{ + SET_BIT(TIMx->BKCR, ATIM_BKCR_COMP_BRKEN_Msk); +} + +/** + * @brief 读取比较器输出刹车信号使能状态 + * @note + * @rmtoll BKCR COMP_BRKEN FL_ATIM_IsEnabledCOMPBreak + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_ATIM_IsEnabledCOMPBreak(ATIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->BKCR, ATIM_BKCR_COMP_BRKEN_Msk) == ATIM_BKCR_COMP_BRKEN_Msk); +} + +/** + * @brief 比较器输出刹车信号禁用 + * @note + * @rmtoll BKCR COMP_BRKEN FL_ATIM_DisableCOMPBreak + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_ATIM_DisableCOMPBreak(ATIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->BKCR, ATIM_BKCR_COMP_BRKEN_Msk); +} + +/** + * @} + */ + +/** @defgroup ATIM_FL_EF_Init Initialization and de-initialization functions + * @{ + */ + +FL_ErrorStatus FL_ATIM_DeInit(ATIM_Type *TIMx); + +void FL_ATIM_StructInit(FL_ATIM_InitTypeDef *TIM_InitStruct); +void FL_ATIM_SlaveModeStructInit(FL_ATIM_SlaveInitTypeDef *TIM_InitStruct); +void FL_ATIM_IC_StructInit(FL_ATIM_IC_InitTypeDef *TIM_ICInitStruct); +void FL_ATIM_OC_StructInit(FL_ATIM_OC_InitTypeDef *TIM_OC_InitStruct); +void FL_ATIM_ETRStructInit(FL_ATIM_ETR_InitTypeDef *TIM_InitStruct); +void FL_ATIM_BDTR_StructInit(FL_ATIM_BDTR_InitTypeDef *TIM_BDTR_InitStruct); + +FL_ErrorStatus FL_ATIM_Init(ATIM_Type *TIMx, FL_ATIM_InitTypeDef *TIM_InitStruct); +FL_ErrorStatus FL_ATIM_IC_Init(ATIM_Type *TIMx, uint32_t Channel, FL_ATIM_IC_InitTypeDef *IC_InitStruct); +FL_ErrorStatus FL_ATIM_ETR_Init(ATIM_Type *TIMx, FL_ATIM_ETR_InitTypeDef *TIM_InitStruct); +FL_ErrorStatus FL_ATIM_SlaveMode_Init(ATIM_Type *TIMx, FL_ATIM_SlaveInitTypeDef *TIM_InitStruct); +FL_ErrorStatus FL_ATIM_OC_Init(ATIM_Type *TIMx, uint32_t Channel, FL_ATIM_OC_InitTypeDef *TIM_OC_InitStruct); +FL_ErrorStatus FL_ATIM_BDTR_Init(ATIM_Type *TIMx, FL_ATIM_BDTR_InitTypeDef *TIM_BDTR_InitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_ATIM_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-12*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_bstim32.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_bstim32.h new file mode 100644 index 0000000000..7c873f965b --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_bstim32.h @@ -0,0 +1,483 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_bstim32.h + * @author FMSH Application Team + * @brief Head file of BSTIM32 FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_BSTIM32_H +#define __FM33LC0XX_FL_BSTIM32_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup BSTIM32 BSTIM32 + * @brief BSTIM32 FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup BSTIM32_FL_ES_INIT BSTIM32 Exported Init structures + * @{ + */ + +/** + * @brief BSTIM32 Init Sturcture Definition + */ + +typedef struct +{ + /* 预分频系数 */ + uint32_t prescaler; + + /* 自动重装载值 */ + uint32_t autoReload; + + /* 自动重装载值 */ + uint32_t autoReloadState; + + /* 时钟源 */ + uint32_t clockSource; + +} FL_BSTIM32_InitTypeDef; + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup BSTIM32_FL_Exported_Constants BSTIM32 Exported Constants + * @{ + */ + +#define BSTIM32_CR1_ARPE_Pos (7U) +#define BSTIM32_CR1_ARPE_Msk (0x1U << BSTIM32_CR1_ARPE_Pos) +#define BSTIM32_CR1_ARPE BSTIM32_CR1_ARPE_Msk + +#define BSTIM32_CR1_OPM_Pos (3U) +#define BSTIM32_CR1_OPM_Msk (0x1U << BSTIM32_CR1_OPM_Pos) +#define BSTIM32_CR1_OPM BSTIM32_CR1_OPM_Msk + +#define BSTIM32_CR1_URS_Pos (2U) +#define BSTIM32_CR1_URS_Msk (0x1U << BSTIM32_CR1_URS_Pos) +#define BSTIM32_CR1_URS BSTIM32_CR1_URS_Msk + +#define BSTIM32_CR1_UDIS_Pos (1U) +#define BSTIM32_CR1_UDIS_Msk (0x1U << BSTIM32_CR1_UDIS_Pos) +#define BSTIM32_CR1_UDIS BSTIM32_CR1_UDIS_Msk + +#define BSTIM32_CR1_CEN_Pos (0U) +#define BSTIM32_CR1_CEN_Msk (0x1U << BSTIM32_CR1_CEN_Pos) +#define BSTIM32_CR1_CEN BSTIM32_CR1_CEN_Msk + +#define BSTIM32_CR2_MMS_Pos (4U) +#define BSTIM32_CR2_MMS_Msk (0x7U << BSTIM32_CR2_MMS_Pos) +#define BSTIM32_CR2_MMS BSTIM32_CR2_MMS_Msk + +#define BSTIM32_IER_UIE_Pos (0U) +#define BSTIM32_IER_UIE_Msk (0x1U << BSTIM32_IER_UIE_Pos) +#define BSTIM32_IER_UIE BSTIM32_IER_UIE_Msk + +#define BSTIM32_ISR_UIF_Pos (0U) +#define BSTIM32_ISR_UIF_Msk (0x1U << BSTIM32_ISR_UIF_Pos) +#define BSTIM32_ISR_UIF BSTIM32_ISR_UIF_Msk + +#define BSTIM32_EGR_UG_Pos (0U) +#define BSTIM32_EGR_UG_Msk (0x1U << BSTIM32_EGR_UG_Pos) +#define BSTIM32_EGR_UG BSTIM32_EGR_UG_Msk + + + + + + +#define FL_BSTIM32_ONE_PULSE_MODE_CONTINUOUS (0x0U << BSTIM32_CR1_OPM_Pos) +#define FL_BSTIM32_ONE_PULSE_MODE_SINGLE (0x1U << BSTIM32_CR1_OPM_Pos) + + +#define FL_BSTIM32_UPDATE_SOURCE_REGULAR (0x0U << BSTIM32_CR1_URS_Pos) +#define FL_BSTIM32_UPDATE_SOURCE_COUNTER (0x1U << BSTIM32_CR1_URS_Pos) + + +#define FL_BSTIM32_TRGO_UG (0x0U << BSTIM32_CR2_MMS_Pos) +#define FL_BSTIM32_TRGO_ENABLE (0x1U << BSTIM32_CR2_MMS_Pos) +#define FL_BSTIM32_TRGO_UPDATE (0x2U << BSTIM32_CR2_MMS_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup BSTIM32_FL_Exported_Functions BSTIM32 Exported Functions + * @{ + */ + +/** + * @brief Auto-Reload preload enable + * @rmtoll CR1 ARPE FL_BSTIM32_EnableARRPreload + * @param BSTIM32x BSTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_EnableARRPreload(BSTIM32_Type *BSTIM32x) +{ + SET_BIT(BSTIM32x->CR1, BSTIM32_CR1_ARPE_Msk); +} + +/** + * @brief Get Auto-Reload preload enable status + * @rmtoll CR1 ARPE FL_BSTIM32_IsEnabledARRPreload + * @param BSTIM32x BSTIM32 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_BSTIM32_IsEnabledARRPreload(BSTIM32_Type *BSTIM32x) +{ + return (uint32_t)(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_ARPE_Msk) == BSTIM32_CR1_ARPE_Msk); +} + +/** + * @brief Auto-Reload preload disable + * @rmtoll CR1 ARPE FL_BSTIM32_DisableARRPreload + * @param BSTIM32x BSTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_DisableARRPreload(BSTIM32_Type *BSTIM32x) +{ + CLEAR_BIT(BSTIM32x->CR1, BSTIM32_CR1_ARPE_Msk); +} + +/** + * @brief Set one pulse mode + * @rmtoll CR1 OPM FL_BSTIM32_SetOnePulseMode + * @param BSTIM32x BSTIM32 instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_BSTIM32_ONE_PULSE_MODE_CONTINUOUS + * @arg @ref FL_BSTIM32_ONE_PULSE_MODE_SINGLE + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_SetOnePulseMode(BSTIM32_Type *BSTIM32x, uint32_t mode) +{ + MODIFY_REG(BSTIM32x->CR1, BSTIM32_CR1_OPM_Msk, mode); +} + +/** + * @brief Get one pulse mode + * @rmtoll CR1 OPM FL_BSTIM32_GetOnePulseMode + * @param BSTIM32x BSTIM32 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_BSTIM32_ONE_PULSE_MODE_CONTINUOUS + * @arg @ref FL_BSTIM32_ONE_PULSE_MODE_SINGLE + */ +__STATIC_INLINE uint32_t FL_BSTIM32_GetOnePulseMode(BSTIM32_Type *BSTIM32x) +{ + return (uint32_t)(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_OPM_Msk)); +} + +/** + * @brief Set update request + * @rmtoll CR1 URS FL_BSTIM32_SetUpdateSource + * @param BSTIM32x BSTIM32 instance + * @param source This parameter can be one of the following values: + * @arg @ref FL_BSTIM32_UPDATE_SOURCE_REGULAR + * @arg @ref FL_BSTIM32_UPDATE_SOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_SetUpdateSource(BSTIM32_Type *BSTIM32x, uint32_t source) +{ + MODIFY_REG(BSTIM32x->CR1, BSTIM32_CR1_URS_Msk, source); +} + +/** + * @brief Get update request status + * @rmtoll CR1 URS FL_BSTIM32_GetUpdateSource + * @param BSTIM32x BSTIM32 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_BSTIM32_UPDATE_SOURCE_REGULAR + * @arg @ref FL_BSTIM32_UPDATE_SOURCE_COUNTER + */ +__STATIC_INLINE uint32_t FL_BSTIM32_GetUpdateSource(BSTIM32_Type *BSTIM32x) +{ + return (uint32_t)(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_URS_Msk)); +} + +/** + * @brief Update event enable + * @rmtoll CR1 UDIS FL_BSTIM32_EnableUpdateEvent + * @param BSTIM32x BSTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_EnableUpdateEvent(BSTIM32_Type *BSTIM32x) +{ + CLEAR_BIT(BSTIM32x->CR1, BSTIM32_CR1_UDIS_Msk); +} + +/** + * @brief Get update event disable status + * @rmtoll CR1 UDIS FL_BSTIM32_IsEnabledUpdateEvent + * @param BSTIM32x BSTIM32 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_BSTIM32_IsEnabledUpdateEvent(BSTIM32_Type *BSTIM32x) +{ + return (uint32_t)!(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_UDIS_Msk) == BSTIM32_CR1_UDIS_Msk); +} + +/** + * @brief Update event disable + * @rmtoll CR1 UDIS FL_BSTIM32_DisableUpdateEvent + * @param BSTIM32x BSTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_DisableUpdateEvent(BSTIM32_Type *BSTIM32x) +{ + CLEAR_BIT(BSTIM32x->CR1, BSTIM32_CR1_UDIS_Msk); +} + +/** + * @brief Counter enable + * @rmtoll CR1 CEN FL_BSTIM32_Enable + * @param BSTIM32x BSTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_Enable(BSTIM32_Type *BSTIM32x) +{ + SET_BIT(BSTIM32x->CR1, BSTIM32_CR1_CEN_Msk); +} + +/** + * @brief Get counter enable status + * @rmtoll CR1 CEN FL_BSTIM32_IsEnabled + * @param BSTIM32x BSTIM32 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_BSTIM32_IsEnabled(BSTIM32_Type *BSTIM32x) +{ + return (uint32_t)(READ_BIT(BSTIM32x->CR1, BSTIM32_CR1_CEN_Msk) == BSTIM32_CR1_CEN_Msk); +} + +/** + * @brief Counter disable + * @rmtoll CR1 CEN FL_BSTIM32_Disable + * @param BSTIM32x BSTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_Disable(BSTIM32_Type *BSTIM32x) +{ + CLEAR_BIT(BSTIM32x->CR1, BSTIM32_CR1_CEN_Msk); +} + +/** + * @brief Set master mode + * @rmtoll CR2 MMS FL_BSTIM32_SetTriggerOutput + * @param BSTIM32x BSTIM32 instance + * @param triggerOutput This parameter can be one of the following values: + * @arg @ref FL_BSTIM32_TRGO_UG + * @arg @ref FL_BSTIM32_TRGO_ENABLE + * @arg @ref FL_BSTIM32_TRGO_UPDATE + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_SetTriggerOutput(BSTIM32_Type *BSTIM32x, uint32_t triggerOutput) +{ + MODIFY_REG(BSTIM32x->CR2, BSTIM32_CR2_MMS_Msk, triggerOutput); +} + +/** + * @brief Get master mode status + * @rmtoll CR2 MMS FL_BSTIM32_GetTriggerOutput + * @param BSTIM32x BSTIM32 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_BSTIM32_TRGO_UG + * @arg @ref FL_BSTIM32_TRGO_ENABLE + * @arg @ref FL_BSTIM32_TRGO_UPDATE + */ +__STATIC_INLINE uint32_t FL_BSTIM32_GetTriggerOutput(BSTIM32_Type *BSTIM32x) +{ + return (uint32_t)(READ_BIT(BSTIM32x->CR2, BSTIM32_CR2_MMS_Msk)); +} + +/** + * @brief Update event interrupt disable + * @rmtoll IER UIE FL_BSTIM32_DisableIT_Update + * @param BSTIM32x BSTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_DisableIT_Update(BSTIM32_Type *BSTIM32x) +{ + CLEAR_BIT(BSTIM32x->IER, BSTIM32_IER_UIE_Msk); +} + +/** + * @brief Update event interrupt enable + * @rmtoll IER UIE FL_BSTIM32_EnableIT_Update + * @param BSTIM32x BSTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_EnableIT_Update(BSTIM32_Type *BSTIM32x) +{ + SET_BIT(BSTIM32x->IER, BSTIM32_IER_UIE_Msk); +} + +/** + * @brief Get update event interrupt enable status + * @rmtoll IER UIE FL_BSTIM32_IsEnabledIT_Update + * @param BSTIM32x BSTIM32 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_BSTIM32_IsEnabledIT_Update(BSTIM32_Type *BSTIM32x) +{ + return (uint32_t)(READ_BIT(BSTIM32x->IER, BSTIM32_IER_UIE_Msk) == BSTIM32_IER_UIE_Msk); +} + +/** + * @brief Get update event interrupt flag + * @rmtoll ISR UIF FL_BSTIM32_IsActiveFlag_Update + * @param BSTIM32x BSTIM32 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_BSTIM32_IsActiveFlag_Update(BSTIM32_Type *BSTIM32x) +{ + return (uint32_t)(READ_BIT(BSTIM32x->ISR, BSTIM32_ISR_UIF_Msk) == (BSTIM32_ISR_UIF_Msk)); +} + +/** + * @brief Clear update event interrupt flag + * @rmtoll ISR UIF FL_BSTIM32_ClearFlag_Update + * @param BSTIM32x BSTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_ClearFlag_Update(BSTIM32_Type *BSTIM32x) +{ + WRITE_REG(BSTIM32x->ISR, BSTIM32_ISR_UIF_Msk); +} + +/** + * @brief Software update event enable + * @rmtoll EGR UG FL_BSTIM32_GenerateUpdateEvent + * @param BSTIM32x BSTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_GenerateUpdateEvent(BSTIM32_Type *BSTIM32x) +{ + SET_BIT(BSTIM32x->EGR, BSTIM32_EGR_UG_Msk); +} + +/** + * @brief Set counter value + * @rmtoll CNT FL_BSTIM32_WriteCounter + * @param BSTIM32x BSTIM32 instance + * @param cnt + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_WriteCounter(BSTIM32_Type *BSTIM32x, uint32_t cnt) +{ + MODIFY_REG(BSTIM32x->CNT, (0xffffffffU << 0U), (cnt << 0U)); +} + +/** + * @brief Get counter value + * @rmtoll CNT FL_BSTIM32_ReadCounter + * @param BSTIM32x BSTIM32 instance + * @retval + */ +__STATIC_INLINE uint32_t FL_BSTIM32_ReadCounter(BSTIM32_Type *BSTIM32x) +{ + return (uint32_t)(READ_BIT(BSTIM32x->CNT, 0xffffffffU) >> 0U); +} + +/** + * @brief Set counter Clock prescaler value + * @rmtoll PSC FL_BSTIM32_WritePrescaler + * @param BSTIM32x BSTIM32 instance + * @param psc + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_WritePrescaler(BSTIM32_Type *BSTIM32x, uint32_t psc) +{ + MODIFY_REG(BSTIM32x->PSC, (0xffffffffU << 0U), (psc << 0U)); +} + +/** + * @brief Get counter Clock prescaler value + * @rmtoll PSC FL_BSTIM32_ReadPrescaler + * @param BSTIM32x BSTIM32 instance + * @retval + */ +__STATIC_INLINE uint32_t FL_BSTIM32_ReadPrescaler(BSTIM32_Type *BSTIM32x) +{ + return (uint32_t)(READ_BIT(BSTIM32x->PSC, 0xffffffffU) >> 0U); +} + +/** + * @brief Set Auto-Reload register value + * @rmtoll ARR FL_BSTIM32_WriteAutoReload + * @param BSTIM32x BSTIM32 instance + * @param value + * @retval None + */ +__STATIC_INLINE void FL_BSTIM32_WriteAutoReload(BSTIM32_Type *BSTIM32x, uint32_t value) +{ + MODIFY_REG(BSTIM32x->ARR, (0xffffffffU << 0U), (value << 0U)); +} + +/** + * @brief Get Auto-Reload register value + * @rmtoll ARR FL_BSTIM32_ReadAutoReload + * @param BSTIM32x BSTIM32 instance + * @retval + */ +__STATIC_INLINE uint32_t FL_BSTIM32_ReadAutoReload(BSTIM32_Type *BSTIM32x) +{ + return (uint32_t)(READ_BIT(BSTIM32x->ARR, 0xffffffffU) >> 0U); +} + +/** + * @} + */ + +/** @defgroup BSTIM32_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_BSTIM32_DeInit(BSTIM32_Type *BSTIM32x); +FL_ErrorStatus FL_BSTIM32_Init(BSTIM32_Type *BSTIM32x, FL_BSTIM32_InitTypeDef *initStruct); +void FL_BSTIM32_StructInit(FL_BSTIM32_InitTypeDef *initStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_BSTIM32_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_comp.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_comp.h new file mode 100644 index 0000000000..55246088c1 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_comp.h @@ -0,0 +1,572 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_comp.h + * @author FMSH Application Team + * @brief Head file of COMP FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_COMP_H +#define __FM33LC0XX_FL_COMP_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup COMP COMP + * @brief COMP FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup COMP_FL_ES_INIT COMP Exported Init structures + * @{ + */ + +/** + * @brief FL COMP Init Sturcture definition + */ +typedef struct +{ + /** 比较器正向输入选择 */ + uint32_t positiveInput; + + /** 比较器反向输入选择 */ + uint32_t negativeInput; + + /** 结果输出极性 */ + uint32_t polarity; + + /** 中断触发边沿选择 */ + uint32_t edge; + + /** 数字滤波器使能 */ + uint32_t digitalFilter; + + /** 数字滤波器长度 */ + uint32_t digitalFilterLen; //此芯片不可设 + +} FL_COMP_InitTypeDef; + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup COMP_FL_Exported_Constants COMP Exported Constants + * @{ + */ + +#define COMP_CR_CMPO_Pos (8U) +#define COMP_CR_CMPO_Msk (0x1U << COMP_CR_CMPO_Pos) +#define COMP_CR_CMPO COMP_CR_CMPO_Msk + +#define COMP_CR_POLAR_Pos (5U) +#define COMP_CR_POLAR_Msk (0x1U << COMP_CR_POLAR_Pos) +#define COMP_CR_POLAR COMP_CR_POLAR_Msk + +#define COMP_CR_VPSEL_Pos (3U) +#define COMP_CR_VPSEL_Msk (0x3U << COMP_CR_VPSEL_Pos) +#define COMP_CR_VPSEL COMP_CR_VPSEL_Msk + +#define COMP_CR_VNSEL_Pos (1U) +#define COMP_CR_VNSEL_Msk (0x3U << COMP_CR_VNSEL_Pos) +#define COMP_CR_VNSEL COMP_CR_VNSEL_Msk + +#define COMP_CR_CMPEN_Pos (0U) +#define COMP_CR_CMPEN_Msk (0x1U << COMP_CR_CMPEN_Pos) +#define COMP_CR_CMPEN COMP_CR_CMPEN_Msk + +#define COMP_ICR_COMP2DF_Pos (9U) +#define COMP_ICR_COMP2DF_Msk (0x1U << COMP_ICR_COMP2DF_Pos) +#define COMP_ICR_COMP2DF COMP_ICR_COMP2DF_Msk + +#define COMP_ICR_COMP1DF_Pos (8U) +#define COMP_ICR_COMP1DF_Msk (0x1U << COMP_ICR_COMP1DF_Pos) +#define COMP_ICR_COMP1DF COMP_ICR_COMP1DF_Msk + +#define COMP_ICR_CMP2SEL_Pos (4U) +#define COMP_ICR_CMP2SEL_Msk (0x3U << COMP_ICR_CMP2SEL_Pos) +#define COMP_ICR_CMP2SEL COMP_ICR_CMP2SEL_Msk + +#define COMP_ICR_CMP1SEL_Pos (2U) +#define COMP_ICR_CMP1SEL_Msk (0x3U << COMP_ICR_CMP1SEL_Pos) +#define COMP_ICR_CMP1SEL COMP_ICR_CMP1SEL_Msk + +#define COMP_ICR_CMP2IE_Pos (1U) +#define COMP_ICR_CMP2IE_Msk (0x1U << COMP_ICR_CMP2IE_Pos) +#define COMP_ICR_CMP2IE COMP_ICR_CMP2IE_Msk + +#define COMP_ICR_CMP1IE_Pos (0U) +#define COMP_ICR_CMP1IE_Msk (0x1U << COMP_ICR_CMP1IE_Pos) +#define COMP_ICR_CMP1IE COMP_ICR_CMP1IE_Msk + +#define COMP_ISR_CMP2IF_Pos (1U) +#define COMP_ISR_CMP2IF_Msk (0x1U << COMP_ISR_CMP2IF_Pos) +#define COMP_ISR_CMP2IF COMP_ISR_CMP2IF_Msk + +#define COMP_ISR_CMP1IF_Pos (0U) +#define COMP_ISR_CMP1IF_Msk (0x1U << COMP_ISR_CMP1IF_Pos) +#define COMP_ISR_CMP1IF COMP_ISR_CMP1IF_Msk + + + +#define FL_COMP_INTERRUPT_EDGE_BOTH 0x0U +#define FL_COMP_INTERRUPT_EDGE_RISING 0x1U +#define FL_COMP_INTERRUPT_EDGE_FALLING 0x2U + + + +#define FL_COMP_OUTPUT_LOW (0x0U << COMP_CR_CMPO_Pos) +#define FL_COMP_OUTPUT_HIGH (0x1U << COMP_CR_CMPO_Pos) + +#define FL_COMP_OUTPUT_POLARITY_NORMAL (0x0U << COMP_CR_POLAR_Pos) +#define FL_COMP_OUTPUT_POLARITY_INVERT (0x1U << COMP_CR_POLAR_Pos) + + +#define FL_COMP_INP_SOURCE_INP1 (0x0U << COMP_CR_VPSEL_Pos) +#define FL_COMP_INP_SOURCE_INP2 (0x1U << COMP_CR_VPSEL_Pos) +#define FL_COMP_INP_SOURCE_INP3 (0x2U << COMP_CR_VPSEL_Pos) + + +#define FL_COMP_INN_SOURCE_INN1 (0x0U << COMP_CR_VNSEL_Pos) +#define FL_COMP_INN_SOURCE_INN2 (0x1U << COMP_CR_VNSEL_Pos) +#define FL_COMP_INN_SOURCE_VREF (0x2U << COMP_CR_VNSEL_Pos) +#define FL_COMP_INN_SOURCE_VREF_DIV_2 (0x3U << COMP_CR_VNSEL_Pos) + + +#define FL_COMP_COMP2_INTERRUPT_EDGE_BOTH (0x0U << COMP_ICR_CMP2SEL_Pos) +#define FL_COMP_COMP2_INTERRUPT_EDGE_RISING (0x1U << COMP_ICR_CMP2SEL_Pos) +#define FL_COMP_COMP2_INTERRUPT_EDGE_FALLING (0x2U << COMP_ICR_CMP2SEL_Pos) + + +#define FL_COMP_COMP1_INTERRUPT_EDGE_BOTH (0x0U << COMP_ICR_CMP1SEL_Pos) +#define FL_COMP_COMP1_INTERRUPT_EDGE_RISING (0x1U << COMP_ICR_CMP1SEL_Pos) +#define FL_COMP_COMP1_INTERRUPT_EDGE_FALLING (0x2U << COMP_ICR_CMP1SEL_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup COMP_FL_Exported_Functions COMP Exported Functions + * @{ + */ + +/** + * @brief Get comparator output channel + * @rmtoll CR CMPO FL_COMP_GetOutput + * @param COMPx COMP instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_COMP_OUTPUT_LOW + * @arg @ref FL_COMP_OUTPUT_HIGH + */ +__STATIC_INLINE uint32_t FL_COMP_GetOutput(COMP_Type *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->CR, COMP_CR_CMPO_Msk)); +} + +/** + * @brief Set COMPx output polarity + * @rmtoll CR POLAR FL_COMP_SetOutputPolarity + * @param COMPx COMP instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_COMP_OUTPUT_POLARITY_NORMAL + * @arg @ref FL_COMP_OUTPUT_POLARITY_INVERT + * @retval None + */ +__STATIC_INLINE void FL_COMP_SetOutputPolarity(COMP_Type *COMPx, uint32_t polarity) +{ + MODIFY_REG(COMPx->CR, COMP_CR_POLAR_Msk, polarity); +} + +/** + * @brief Get COMPx output polarity + * @rmtoll CR POLAR FL_COMP_GetOutputPolarity + * @param COMPx COMP instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_COMP_OUTPUT_POLARITY_NORMAL + * @arg @ref FL_COMP_OUTPUT_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_COMP_GetOutputPolarity(COMP_Type *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->CR, COMP_CR_POLAR_Msk)); +} + +/** + * @brief Set COMPx positive input + * @rmtoll CR VPSEL FL_COMP_SetINPSource + * @param COMPx COMP instance + * @param source This parameter can be one of the following values: + * @arg @ref FL_COMP_INP_SOURCE_INP1 + * @arg @ref FL_COMP_INP_SOURCE_INP2 + * @arg @ref FL_COMP_INP_SOURCE_INP3 + * @retval None + */ +__STATIC_INLINE void FL_COMP_SetINPSource(COMP_Type *COMPx, uint32_t source) +{ + MODIFY_REG(COMPx->CR, COMP_CR_VPSEL_Msk, source); +} + +/** + * @brief Get COMPx positive input status + * @rmtoll CR VPSEL FL_COMP_GetINPSource + * @param COMPx COMP instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_COMP_INP_SOURCE_INP1 + * @arg @ref FL_COMP_INP_SOURCE_INP2 + * @arg @ref FL_COMP_INP_SOURCE_INP3 + */ +__STATIC_INLINE uint32_t FL_COMP_GetINPSource(COMP_Type *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->CR, COMP_CR_VPSEL_Msk)); +} + +/** + * @brief Set COMPx negative input + * @rmtoll CR VNSEL FL_COMP_SetINNSource + * @param COMPx COMP instance + * @param source This parameter can be one of the following values: + * @arg @ref FL_COMP_INN_SOURCE_INN1 + * @arg @ref FL_COMP_INN_SOURCE_INN2 + * @arg @ref FL_COMP_INN_SOURCE_VREF + * @arg @ref FL_COMP_INN_SOURCE_VREF_DIV_2 + * @retval None + */ +__STATIC_INLINE void FL_COMP_SetINNSource(COMP_Type *COMPx, uint32_t source) +{ + MODIFY_REG(COMPx->CR, COMP_CR_VNSEL_Msk, source); +} + +/** + * @brief Get COMPx negative input status + * @rmtoll CR VNSEL FL_COMP_GetINNSource + * @param COMPx COMP instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_COMP_INN_SOURCE_INN1 + * @arg @ref FL_COMP_INN_SOURCE_INN2 + * @arg @ref FL_COMP_INN_SOURCE_VREF + * @arg @ref FL_COMP_INN_SOURCE_VREF_DIV_2 + */ +__STATIC_INLINE uint32_t FL_COMP_GetINNSource(COMP_Type *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->CR, COMP_CR_VNSEL_Msk)); +} + +/** + * @brief COMPx enable + * @rmtoll CR CMPEN FL_COMP_Enable + * @param COMPx COMP instance + * @retval None + */ +__STATIC_INLINE void FL_COMP_Enable(COMP_Type *COMPx) +{ + SET_BIT(COMPx->CR, COMP_CR_CMPEN_Msk); +} + +/** + * @brief Get COMPx enable status + * @rmtoll CR CMPEN FL_COMP_IsEnabled + * @param COMPx COMP instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_COMP_IsEnabled(COMP_Type *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->CR, COMP_CR_CMPEN_Msk) == COMP_CR_CMPEN_Msk); +} + +/** + * @brief COMPx disable + * @rmtoll CR CMPEN FL_COMP_Disable + * @param COMPx COMP instance + * @retval None + */ +__STATIC_INLINE void FL_COMP_Disable(COMP_Type *COMPx) +{ + CLEAR_BIT(COMPx->CR, COMP_CR_CMPEN_Msk); +} + +/** + * @brief Comparator2 DigitalFilter enable + * @rmtoll ICR COMP2DF FL_COMP_EnableComparator2OutputFilter + * @param COMPx COMP instance + * @retval None + */ +__STATIC_INLINE void FL_COMP_EnableComparator2OutputFilter(COMP_COMMON_Type *COMPx) +{ + SET_BIT(COMPx->ICR, COMP_ICR_COMP2DF_Msk); +} + +/** + * @brief Get comparator2 DigitalFilter enable status + * @rmtoll ICR COMP2DF FL_COMP_IsEnabledComparator2OutputFilter + * @param COMPx COMP instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_COMP_IsEnabledComparator2OutputFilter(COMP_COMMON_Type *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->ICR, COMP_ICR_COMP2DF_Msk) == COMP_ICR_COMP2DF_Msk); +} + +/** + * @brief Comparator2 DigitalFilter disable + * @rmtoll ICR COMP2DF FL_COMP_DisableComparator2OutputFilter + * @param COMPx COMP instance + * @retval None + */ +__STATIC_INLINE void FL_COMP_DisableComparator2OutputFilter(COMP_COMMON_Type *COMPx) +{ + CLEAR_BIT(COMPx->ICR, COMP_ICR_COMP2DF_Msk); +} + +/** + * @brief Comparator1 DigitalFilter enable + * @rmtoll ICR COMP1DF FL_COMP_EnableComparator1OutputFilter + * @param COMPx COMP instance + * @retval None + */ +__STATIC_INLINE void FL_COMP_EnableComparator1OutputFilter(COMP_COMMON_Type *COMPx) +{ + SET_BIT(COMPx->ICR, COMP_ICR_COMP1DF_Msk); +} + +/** + * @brief Get comparator1 DigitalFilter enable status + * @rmtoll ICR COMP1DF FL_COMP_IsEnabledComparator1OutputFilter + * @param COMPx COMP instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_COMP_IsEnabledComparator1OutputFilter(COMP_COMMON_Type *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->ICR, COMP_ICR_COMP1DF_Msk) == COMP_ICR_COMP1DF_Msk); +} + +/** + * @brief Comparator1 DigitalFilter disable + * @rmtoll ICR COMP1DF FL_COMP_DisableComparator1OutputFilter + * @param COMPx COMP instance + * @retval None + */ +__STATIC_INLINE void FL_COMP_DisableComparator1OutputFilter(COMP_COMMON_Type *COMPx) +{ + CLEAR_BIT(COMPx->ICR, COMP_ICR_COMP1DF_Msk); +} + +/** + * @brief Set comparator2 interrupt edge + * @rmtoll ICR CMP2SEL FL_COMP_SetComparator2InterruptEdge + * @param COMPx COMP instance + * @param edge This parameter can be one of the following values: + * @arg @ref FL_COMP_COMP2_INTERRUPT_EDGE_BOTH + * @arg @ref FL_COMP_COMP2_INTERRUPT_EDGE_RISING + * @arg @ref FL_COMP_COMP2_INTERRUPT_EDGE_FALLING + * @retval None + */ +__STATIC_INLINE void FL_COMP_SetComparator2InterruptEdge(COMP_COMMON_Type *COMPx, uint32_t edge) +{ + MODIFY_REG(COMPx->ICR, COMP_ICR_CMP2SEL_Msk, edge); +} + +/** + * @brief Get comparator2 interrupt edge + * @rmtoll ICR CMP2SEL FL_COMP_GetComparator2InterruptEdge + * @param COMPx COMP instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_COMP_COMP2_INTERRUPT_EDGE_BOTH + * @arg @ref FL_COMP_COMP2_INTERRUPT_EDGE_RISING + * @arg @ref FL_COMP_COMP2_INTERRUPT_EDGE_FALLING + */ +__STATIC_INLINE uint32_t FL_COMP_GetComparator2InterruptEdge(COMP_COMMON_Type *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->ICR, COMP_ICR_CMP2SEL_Msk)); +} + +/** + * @brief Set comparator1 interrupt edge + * @rmtoll ICR CMP1SEL FL_COMP_SetComparator1InterruptEdge + * @param COMPx COMP instance + * @param edge This parameter can be one of the following values: + * @arg @ref FL_COMP_COMP1_INTERRUPT_EDGE_BOTH + * @arg @ref FL_COMP_COMP1_INTERRUPT_EDGE_RISING + * @arg @ref FL_COMP_COMP1_INTERRUPT_EDGE_FALLING + * @retval None + */ +__STATIC_INLINE void FL_COMP_SetComparator1InterruptEdge(COMP_COMMON_Type *COMPx, uint32_t edge) +{ + MODIFY_REG(COMPx->ICR, COMP_ICR_CMP1SEL_Msk, edge); +} + +/** + * @brief Get comparator1 interrupt edge + * @rmtoll ICR CMP1SEL FL_COMP_GetComparator1InterruptEdge + * @param COMPx COMP instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_COMP_COMP1_INTERRUPT_EDGE_BOTH + * @arg @ref FL_COMP_COMP1_INTERRUPT_EDGE_RISING + * @arg @ref FL_COMP_COMP1_INTERRUPT_EDGE_FALLING + */ +__STATIC_INLINE uint32_t FL_COMP_GetComparator1InterruptEdge(COMP_COMMON_Type *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->ICR, COMP_ICR_CMP1SEL_Msk)); +} + +/** + * @brief Comparator2 interrupt enable + * @rmtoll ICR CMP2IE FL_COMP_EnableIT_Comparator2 + * @param COMPx COMP instance + * @retval None + */ +__STATIC_INLINE void FL_COMP_EnableIT_Comparator2(COMP_COMMON_Type *COMPx) +{ + SET_BIT(COMPx->ICR, COMP_ICR_CMP2IE_Msk); +} + +/** + * @brief Get comparator2 interrupt enable status + * @rmtoll ICR CMP2IE FL_COMP_IsEnabledIT_Comparator2 + * @param COMPx COMP instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_COMP_IsEnabledIT_Comparator2(COMP_COMMON_Type *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->ICR, COMP_ICR_CMP2IE_Msk) == COMP_ICR_CMP2IE_Msk); +} + +/** + * @brief Comparator2 interrupt disable + * @rmtoll ICR CMP2IE FL_COMP_DisableIT_Comparator2 + * @param COMPx COMP instance + * @retval None + */ +__STATIC_INLINE void FL_COMP_DisableIT_Comparator2(COMP_COMMON_Type *COMPx) +{ + CLEAR_BIT(COMPx->ICR, COMP_ICR_CMP2IE_Msk); +} + +/** + * @brief Comparator1 interrupt enable + * @rmtoll ICR CMP1IE FL_COMP_EnableIT_Comparator1 + * @param COMPx COMP instance + * @retval None + */ +__STATIC_INLINE void FL_COMP_EnableIT_Comparator1(COMP_COMMON_Type *COMPx) +{ + SET_BIT(COMPx->ICR, COMP_ICR_CMP1IE_Msk); +} + +/** + * @brief Get comparator1 interrupt enable status + * @rmtoll ICR CMP1IE FL_COMP_IsEnabledIT_Comparator1 + * @param COMPx COMP instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_COMP_IsEnabledIT_Comparator1(COMP_COMMON_Type *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->ICR, COMP_ICR_CMP1IE_Msk) == COMP_ICR_CMP1IE_Msk); +} + +/** + * @brief Comparator1 interrupt disable + * @rmtoll ICR CMP1IE FL_COMP_DisableIT_Comparator1 + * @param COMPx COMP instance + * @retval None + */ +__STATIC_INLINE void FL_COMP_DisableIT_Comparator1(COMP_COMMON_Type *COMPx) +{ + CLEAR_BIT(COMPx->ICR, COMP_ICR_CMP1IE_Msk); +} + +/** + * @brief Get comparator2 interrupt flag + * @rmtoll ISR CMP2IF FL_COMP_IsActiveFlag_Comparator2 + * @param COMPx COMP instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_COMP_IsActiveFlag_Comparator2(COMP_COMMON_Type *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->ISR, COMP_ISR_CMP2IF_Msk) == (COMP_ISR_CMP2IF_Msk)); +} + +/** + * @brief Clear comparator2 interrupt flag + * @rmtoll ISR CMP2IF FL_COMP_ClearFlag_Comparator2 + * @param COMPx COMP instance + * @retval None + */ +__STATIC_INLINE void FL_COMP_ClearFlag_Comparator2(COMP_COMMON_Type *COMPx) +{ + WRITE_REG(COMPx->ISR, COMP_ISR_CMP2IF_Msk); +} + +/** + * @brief Get comparator1 interrupt flag + * @rmtoll ISR CMP1IF FL_COMP_IsActiveFlag_Comparator1 + * @param COMPx COMP instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_COMP_IsActiveFlag_Comparator1(COMP_COMMON_Type *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->ISR, COMP_ISR_CMP1IF_Msk) == (COMP_ISR_CMP1IF_Msk)); +} + +/** + * @brief Clear comparator1 interrupt flag + * @rmtoll ISR CMP1IF FL_COMP_ClearFlag_Comparator1 + * @param COMPx COMP instance + * @retval None + */ +__STATIC_INLINE void FL_COMP_ClearFlag_Comparator1(COMP_COMMON_Type *COMPx) +{ + WRITE_REG(COMPx->ISR, COMP_ISR_CMP1IF_Msk); +} + +/** + * @} + */ + +/** @defgroup COMP_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_COMP_DeInit(COMP_Type *COMPx); +void FL_COMP_StructInit(FL_COMP_InitTypeDef *initStruct); +FL_ErrorStatus FL_COMP_Init(COMP_Type *COMPx, FL_COMP_InitTypeDef *initStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_COMP_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-22*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_crc.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_crc.h new file mode 100644 index 0000000000..d625a372f7 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_crc.h @@ -0,0 +1,474 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_crc.h + * @author FMSH Application Team + * @brief Head file of CRC FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_CRC_H +#define __FM33LC0XX_FL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup CRC_FL_ES_INIT CRC Exported Init structures + * @{ + */ + +/** + * @brief FL CRC Init Sturcture definition + */ +typedef struct +{ + /** CRC初值 */ + uint32_t initVal; + + /** 计算数据宽度 */ + uint32_t dataWidth; + + /** 输入数据翻转 */ + uint32_t reflectIn; + + /** 输出数据翻转 */ + uint32_t reflectOut; + + /** 输出结果异或寄存器 */ + uint32_t xorReg; + + /** 输出结果异或使能 */ + uint32_t xorRegState; + + /** CRC多项式宽 */ + uint32_t polynomialWidth; + + /** CRC多项式 */ + uint32_t polynomial; + + /** 计算模式串行或并行 */ + uint32_t calculatMode; + +} FL_CRC_InitTypeDef; + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup CRC_FL_Exported_Constants CRC Exported Constants + * @{ + */ + +#define CRC_CR_OPWD_Pos (9U) +#define CRC_CR_OPWD_Msk (0x1U << CRC_CR_OPWD_Pos) +#define CRC_CR_OPWD CRC_CR_OPWD_Msk + +#define CRC_CR_PARA_Pos (8U) +#define CRC_CR_PARA_Msk (0x1U << CRC_CR_PARA_Pos) +#define CRC_CR_PARA CRC_CR_PARA_Msk + +#define CRC_CR_RFLTIN_Pos (6U) +#define CRC_CR_RFLTIN_Msk (0x3U << CRC_CR_RFLTIN_Pos) +#define CRC_CR_RFLTIN CRC_CR_RFLTIN_Msk + +#define CRC_CR_RFLTO_Pos (5U) +#define CRC_CR_RFLTO_Msk (0x1U << CRC_CR_RFLTO_Pos) +#define CRC_CR_RFLTO CRC_CR_RFLTO_Msk + +#define CRC_CR_RES_Pos (4U) +#define CRC_CR_RES_Msk (0x1U << CRC_CR_RES_Pos) +#define CRC_CR_RES CRC_CR_RES_Msk + +#define CRC_CR_BUSY_Pos (3U) +#define CRC_CR_BUSY_Msk (0x1U << CRC_CR_BUSY_Pos) +#define CRC_CR_BUSY CRC_CR_BUSY_Msk + +#define CRC_CR_XOR_Pos (2U) +#define CRC_CR_XOR_Msk (0x1U << CRC_CR_XOR_Pos) +#define CRC_CR_XOR CRC_CR_XOR_Msk + +#define CRC_CR_SEL_Pos (0U) +#define CRC_CR_SEL_Msk (0x3U << CRC_CR_SEL_Pos) +#define CRC_CR_SEL CRC_CR_SEL_Msk + + +#define FL_CRC_DATA_WIDTH_8B (0x0U << CRC_CR_OPWD_Pos) +#define FL_CRC_DATA_WIDTH_32B (0x1U << CRC_CR_OPWD_Pos) + + +#define FL_CRC_CALCULATE_SERIAL (0x0U << CRC_CR_PARA_Pos) +#define FL_CRC_CALCULATE_PARALLEL (0x1U << CRC_CR_PARA_Pos) + + +#define FL_CRC_INPUT_INVERT_NONE (0x0U << CRC_CR_RFLTIN_Pos) +#define FL_CRC_INPUT_INVERT_BYTE (0x1U << CRC_CR_RFLTIN_Pos) +#define FL_CRC_INPUT_INVERT_HALF_WORD (0x2U << CRC_CR_RFLTIN_Pos) +#define FL_CRC_INPUT_INVERT_WORD (0x3U << CRC_CR_RFLTIN_Pos) + + +#define FL_CRC_OUPUT_INVERT_NONE (0x0U << CRC_CR_RFLTO_Pos) +#define FL_CRC_OUPUT_INVERT_BYTE (0x1U << CRC_CR_RFLTO_Pos) + + +#define FL_CRC_POLYNOMIAL_32B (0x0U << CRC_CR_SEL_Pos) +#define FL_CRC_POLYNOMIAL_16B (0x1U << CRC_CR_SEL_Pos) +#define FL_CRC_POLYNOMIAL_8B (0x2U << CRC_CR_SEL_Pos) +#define FL_CRC_POLYNOMIAL_7B (0x3U << CRC_CR_SEL_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup CRC_FL_Exported_Functions CRC Exported Functions + * @{ + */ + +/** + * @brief Set CRC data register + * @rmtoll DR FL_CRC_WriteData + * @param CRCx CRC instance + * @param data + * @retval None + */ +__STATIC_INLINE void FL_CRC_WriteData(CRC_Type *CRCx, uint32_t data) +{ + MODIFY_REG(CRCx->DR, (0xffffffffU << 0U), (data << 0U)); +} + +/** + * @brief Get CRC data register value + * @rmtoll DR FL_CRC_ReadData + * @param CRCx CRC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_CRC_ReadData(CRC_Type *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->DR, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @brief Set CRC calculate operation width + * @rmtoll CR OPWD FL_CRC_SetDataWidth + * @param CRCx CRC instance + * @param dataWidth This parameter can be one of the following values: + * @arg @ref FL_CRC_DATA_WIDTH_8B + * @arg @ref FL_CRC_DATA_WIDTH_32B + * @retval None + */ +__STATIC_INLINE void FL_CRC_SetDataWidth(CRC_Type *CRCx, uint32_t dataWidth) +{ + MODIFY_REG(CRCx->CR, CRC_CR_OPWD_Msk, dataWidth); +} + +/** + * @brief Get CRC calculate operation width + * @rmtoll CR OPWD FL_CRC_GetDataWidth + * @param CRCx CRC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_CRC_DATA_WIDTH_8B + * @arg @ref FL_CRC_DATA_WIDTH_32B + */ +__STATIC_INLINE uint32_t FL_CRC_GetDataWidth(CRC_Type *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_OPWD_Msk)); +} + +/** + * @brief Set CRC parallel calculation mode + * @rmtoll CR PARA FL_CRC_SetCalculateMode + * @param CRCx CRC instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_CRC_CALCULATE_SERIAL + * @arg @ref FL_CRC_CALCULATE_PARALLEL + * @retval None + */ +__STATIC_INLINE void FL_CRC_SetCalculateMode(CRC_Type *CRCx, uint32_t mode) +{ + MODIFY_REG(CRCx->CR, CRC_CR_PARA_Msk, mode); +} + +/** + * @brief Get CRC parallel calculation mode + * @rmtoll CR PARA FL_CRC_GetCalculateMode + * @param CRCx CRC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_CRC_CALCULATE_SERIAL + * @arg @ref FL_CRC_CALCULATE_PARALLEL + */ +__STATIC_INLINE uint32_t FL_CRC_GetCalculateMode(CRC_Type *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_PARA_Msk)); +} + +/** + * @brief Set CRC reflected input + * @rmtoll CR RFLTIN FL_CRC_SetInputInvertMode + * @param CRCx CRC instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_CRC_INPUT_INVERT_NONE + * @arg @ref FL_CRC_INPUT_INVERT_BYTE + * @arg @ref FL_CRC_INPUT_INVERT_HALF_WORD + * @arg @ref FL_CRC_INPUT_INVERT_WORD + * @retval None + */ +__STATIC_INLINE void FL_CRC_SetInputInvertMode(CRC_Type *CRCx, uint32_t mode) +{ + MODIFY_REG(CRCx->CR, CRC_CR_RFLTIN_Msk, mode); +} + +/** + * @brief Get CRC reflected input status + * @rmtoll CR RFLTIN FL_CRC_GetInputInvertMode + * @param CRCx CRC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_CRC_INPUT_INVERT_NONE + * @arg @ref FL_CRC_INPUT_INVERT_BYTE + * @arg @ref FL_CRC_INPUT_INVERT_HALF_WORD + * @arg @ref FL_CRC_INPUT_INVERT_WORD + */ +__STATIC_INLINE uint32_t FL_CRC_GetInputInvertMode(CRC_Type *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_RFLTIN_Msk)); +} + +/** + * @brief Set CRC reflected output + * @rmtoll CR RFLTO FL_CRC_SetOutputInvertMode + * @param CRCx CRC instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_CRC_OUPUT_INVERT_NONE + * @arg @ref FL_CRC_OUPUT_INVERT_BYTE + * @retval None + */ +__STATIC_INLINE void FL_CRC_SetOutputInvertMode(CRC_Type *CRCx, uint32_t mode) +{ + MODIFY_REG(CRCx->CR, CRC_CR_RFLTO_Msk, mode); +} + +/** + * @brief Get CRC feflected output status + * @rmtoll CR RFLTO FL_CRC_GetOutputInvertMode + * @param CRCx CRC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_CRC_OUPUT_INVERT_NONE + * @arg @ref FL_CRC_OUPUT_INVERT_BYTE + */ +__STATIC_INLINE uint32_t FL_CRC_GetOutputInvertMode(CRC_Type *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_RFLTO_Msk)); +} + +/** + * @brief Get CRC result flag + * @rmtoll CR RES FL_CRC_IsActiveFlag_Zero + * @param CRCx CRC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_CRC_IsActiveFlag_Zero(CRC_Type *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_RES_Msk) == (CRC_CR_RES_Msk)); +} + +/** + * @brief Get CRC operational flag + * @rmtoll CR BUSY FL_CRC_IsActiveFlag_Busy + * @param CRCx CRC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_CRC_IsActiveFlag_Busy(CRC_Type *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_BUSY_Msk) == (CRC_CR_BUSY_Msk)); +} + +/** + * @brief Output XORed with CRC_XOR register enable + * @rmtoll CR XOR FL_CRC_EnableOutputXOR + * @param CRCx CRC instance + * @retval None + */ +__STATIC_INLINE void FL_CRC_EnableOutputXOR(CRC_Type *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_XOR_Msk); +} + +/** + * @brief Get output XORed with CRC_XOR register enable status + * @rmtoll CR XOR FL_CRC_IsEnabledOutputXOR + * @param CRCx CRC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_CRC_IsEnabledOutputXOR(CRC_Type *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_XOR_Msk) == CRC_CR_XOR_Msk); +} + +/** + * @brief Output XORed with CRC_XOR register disable + * @rmtoll CR XOR FL_CRC_DisableOutputXOR + * @param CRCx CRC instance + * @retval None + */ +__STATIC_INLINE void FL_CRC_DisableOutputXOR(CRC_Type *CRCx) +{ + CLEAR_BIT(CRCx->CR, CRC_CR_XOR_Msk); +} + +/** + * @brief Polynomial width selection + * @rmtoll CR SEL FL_CRC_SetPolynomialWidth + * @param CRCx CRC instance + * @param width This parameter can be one of the following values: + * @arg @ref FL_CRC_POLYNOMIAL_32B + * @arg @ref FL_CRC_POLYNOMIAL_16B + * @arg @ref FL_CRC_POLYNOMIAL_8B + * @arg @ref FL_CRC_POLYNOMIAL_7B + * @retval None + */ +__STATIC_INLINE void FL_CRC_SetPolynomialWidth(CRC_Type *CRCx, uint32_t width) +{ + MODIFY_REG(CRCx->CR, CRC_CR_SEL_Msk, width); +} + +/** + * @brief Get Polynomial width Selection status + * @rmtoll CR SEL FL_CRC_GetPolynomialWidth + * @param CRCx CRC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_CRC_POLYNOMIAL_32B + * @arg @ref FL_CRC_POLYNOMIAL_16B + * @arg @ref FL_CRC_POLYNOMIAL_8B + * @arg @ref FL_CRC_POLYNOMIAL_7B + */ +__STATIC_INLINE uint32_t FL_CRC_GetPolynomialWidth(CRC_Type *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_SEL_Msk)); +} + +/** + * @brief Set linear feedback shift register + * @rmtoll LFSR FL_CRC_WriteInitialValue + * @param CRCx CRC instance + * @param data + * @retval None + */ +__STATIC_INLINE void FL_CRC_WriteInitialValue(CRC_Type *CRCx, uint32_t data) +{ + MODIFY_REG(CRCx->LFSR, (0xffffffffU << 0U), (data << 0U)); +} + +/** + * @brief Get linear feedback shift register value + * @rmtoll LFSR FL_CRC_ReadInitialValue + * @param CRCx CRC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_CRC_ReadInitialValue(CRC_Type *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->LFSR, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @brief Set eXclusive XOR register + * @rmtoll XOR FL_CRC_WriteXORValue + * @param CRCx CRC instance + * @param data + * @retval None + */ +__STATIC_INLINE void FL_CRC_WriteXORValue(CRC_Type *CRCx, uint32_t data) +{ + MODIFY_REG(CRCx->XOR, (0xffffffffU << 0U), (data << 0U)); +} + +/** + * @brief Get eXclusive XOR register value + * @rmtoll XOR FL_CRC_ReadXORValue + * @param CRCx CRC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_CRC_ReadXORValue(CRC_Type *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->XOR, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @brief Set CRC Polynominals + * @rmtoll POLY FL_CRC_WritePolynominalParam + * @param CRCx CRC instance + * @param data + * @retval None + */ +__STATIC_INLINE void FL_CRC_WritePolynominalParam(CRC_Type *CRCx, uint32_t data) +{ + MODIFY_REG(CRCx->POLY, (0xffffffffU << 0U), (data << 0U)); +} + +/** + * @brief Get CRC Polynominals + * @rmtoll POLY FL_CRC_ReadPolynominalParam + * @param CRCx CRC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_CRC_ReadPolynominalParam(CRC_Type *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->POLY, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @} + */ + +/** @defgroup CRC_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_CRC_DeInit(CRC_Type *CRCx); +void FL_CRC_StructInit(FL_CRC_InitTypeDef *CRC_InitStruct); +FL_ErrorStatus FL_CRC_Init(CRC_Type *CRCx, FL_CRC_InitTypeDef *CRC_InitStruct); + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_CRC_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_divas.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_divas.h new file mode 100644 index 0000000000..45f2e0bd8a --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_divas.h @@ -0,0 +1,206 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_divas.h + * @author FMSH Application Team + * @brief Head file of DIVAS FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_DIVAS_H +#define __FM33LC0XX_FL_DIVAS_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup DIVAS DIVAS + * @brief DIVAS FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup DIVAS_FL_ES_INIT DIVAS Exported Init structures + * @{ + */ + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup DIVAS_FL_Exported_Constants DIVAS Exported Constants + * @{ + */ + +#define DIV_SR_DIVBYZERO_Pos (1U) +#define DIV_SR_DIVBYZERO_Msk (0x1U << DIV_SR_DIVBYZERO_Pos) +#define DIV_SR_DIVBYZERO DIV_SR_DIVBYZERO_Msk + +#define DIV_SR_BUSY_Pos (0U) +#define DIV_SR_BUSY_Msk (0x1U << DIV_SR_BUSY_Pos) +#define DIV_SR_BUSY DIV_SR_BUSY_Msk + + + +#define FL_DIVAS_SR_BUSY_TIMEOUT 0xFFFU + + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup DIVAS_FL_Exported_Functions DIVAS Exported Functions + * @{ + */ + +/** + * @brief Write Dividend Register + * @rmtoll OPRD FL_DIV_WriteDividend_S32 + * @param DIVx DIV instance + * @param number + * @retval None + */ +__STATIC_INLINE void FL_DIV_WriteDividend_S32(DIV_Type *DIVx, int32_t number) +{ + MODIFY_REG(DIVx->END, (0xffffffffU << 0U), (number << 0U)); +} + +/** + * @brief Read Dividend Register + * @rmtoll OPRD FL_DIV_ReadDividend_S32 + * @param DIVx DIV instance + * @retval + */ +__STATIC_INLINE int32_t FL_DIV_ReadDividend_S32(DIV_Type *DIVx) +{ + return (uint32_t)(READ_BIT(DIVx->END, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @brief Write 16bit Signed Divisor + * @rmtoll DIVSOR FL_DIV_WriteDivisor_S16 + * @param DIVx DIV instance + * @param number + * @retval None + */ +__STATIC_INLINE void FL_DIV_WriteDivisor_S16(DIV_Type *DIVx, int16_t number) +{ + MODIFY_REG(DIVx->SOR, (0xffffU << 0U), (number << 0U)); +} + +/** + * @brief Read 16bit Signed Divisor + * @rmtoll DIVSOR FL_DIV_ReadDivisor_S16 + * @param DIVx DIV instance + * @retval + */ +__STATIC_INLINE int32_t FL_DIV_ReadDivisor_S16(DIV_Type *DIVx) +{ + return (uint32_t)(READ_BIT(DIVx->SOR, (0xffffU << 0U)) >> 0U); +} + +/** + * @brief Read 32bit Signed QUTO + * @rmtoll QUOT FL_DIV_ReadQuotient_S32 + * @param DIVx DIV instance + * @retval + */ +__STATIC_INLINE int32_t FL_DIV_ReadQuotient_S32(DIV_Type *DIVx) +{ + return (uint32_t)(READ_BIT(DIVx->QUOT, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @brief Read 16bit Signed Reminder + * @rmtoll REMD FL_DIV_ReadResidue_S16 + * @param DIVx DIV instance + * @retval + */ +__STATIC_INLINE int32_t FL_DIV_ReadResidue_S16(DIV_Type *DIVx) +{ + return (uint32_t)(READ_BIT(DIVx->REMD, (0xffffU << 0U)) >> 0U); +} + +/** + * @brief Get divided by 0 flag + * @rmtoll SR DIVBYZERO FL_DIV_IsActiveFlag_DividedZero + * @param DIVx DIV instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_DIV_IsActiveFlag_DividedZero(DIV_Type *DIVx) +{ + return (uint32_t)(READ_BIT(DIVx->SR, DIV_SR_DIVBYZERO_Msk) == (DIV_SR_DIVBYZERO_Msk)); +} + +/** + * @brief Get Busy flag + * @rmtoll SR BUSY FL_DIV_IsActiveFlag_Busy + * @param DIVx DIV instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_DIV_IsActiveFlag_Busy(DIV_Type *DIVx) +{ + return (uint32_t)(READ_BIT(DIVx->SR, DIV_SR_BUSY_Msk) == (DIV_SR_BUSY_Msk)); +} + +/** + * @} + */ + +/** @defgroup DIVAS_FL_EF_Init Initialization and de-initialization functions + * @{ + */ + +FL_ErrorStatus FL_DIVAS_DeInit(DIV_Type *DIVx); +FL_ErrorStatus FL_DIVAS_Init(DIV_Type *DIVx); + +/** + * @} + */ + +/** @defgroup DIVAS_FL_EF_Operation Opeartion functions + * @{ + */ + +uint32_t FL_DIVAS_Hdiv_Calculation(DIV_Type *DIVx, int32_t DivisorEnd, int16_t Divisor, int32_t *Quotient, int16_t *Residue); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_DIVAS_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_dma.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_dma.h new file mode 100644 index 0000000000..2921aa5dc4 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_dma.h @@ -0,0 +1,1287 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_dma.h + * @author FMSH Application Team + * @brief Head file of DMA FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ +/********************************************DMA channel mapping***************************************** + ------------------------------------------------------------------------------------------------- + |Channel| 0 | 1 | 2 | 3 | 4 | 5 | 6 | + -------------------------------------------------------------------------------------------------- + |Func1 |ADC |UARTRX0 | SPI2RX |SPI1_RX |ADC |SPI1RX |SPI1TX | + ----------------------------------------------------------------------------------------- + |Func2 |LPUART0RX|LPUART0TX| UARTTX0 |UARTRX0 |SPI1TX |SPI2RX |SPI2TX | + -------------------------------------------------------------------------------------------------- + |Func3 |LPUART1TX|IICRX | UARTRX4 |UARTRX1 |SPI2TX |UARTRX1 |UARTTX1 | + -------------------------------------------------------------------------------------------------- + |Func4 |AESIN |AESOUT | LPUART1RX|UARTTX4 |UARTTX0 |LPUART0TX |UARTTX5 | + -------------------------------------------------------------------------------------------------- + |Func5 |CRC |ATIMCH2 | I2CTX |LPUART0RX|UARTTX1 |LPUART1RX |LPUART1TX | + -------------------------------------------------------------------------------------------------- + |Func6 |ATIMCH1 |GTIM0CH2 | ATIMCH3 |ATIMCH4 |UARTRX5 |U7816RX |U7816TX | + -------------------------------------------------------------------------------------------------- + |Func7 |GTIM0CH1 |GTIM1CH2 | GTIM0CH3 |GTIM0CH4 |I2CRX |GTIM1TRIG/UEV |I2CTX | + -------------------------------------------------------------------------------------------------- + |Func8 |GTIM1CH1 |LPT32CH1 | GTIM1CH3 |GTIM1CH4 |ATIMTRIG/COM/UEV |LPT32CH2 |GTIM0TRIG\UEV | + -------------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------------- +********************************************DMA channel mapping*****************************************/ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_DMA_H +#define __FM33LC0XX_FL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup DMA_FL_ES_INIT DMA Exported Init structures + * @{ + */ + +/** + * @brief FL DMA Init Sturcture definition + */ +typedef struct +{ + /*! DMA外设映射地址 */ + uint32_t periphAddress; + + /*! DMA传输方向 */ + uint32_t direction; + + /*! RAM地址增长方向 */ + uint32_t memoryAddressIncMode; + + /*! RAM地址增长方向 */ + uint32_t flashAddressIncMode; + + /*! DAM传输通道数据位宽 */ + uint32_t dataSize; + + /*! DMA通道优先级 */ + uint32_t priority; + + /*! 循环模式使能 */ + uint32_t circMode; + +} FL_DMA_InitTypeDef; + +/** + * @brief FL DMA Config Sturcture definition + */ +typedef struct +{ + /* DMA传输RAM地址 */ + uint32_t memoryAddress; + + /* DMA传输请求次数 */ + uint32_t transmissionCount; + +} FL_DMA_ConfigTypeDef; + +/** + * @brief Configuration with temporary structure variable users will not be used directly + */ +typedef struct +{ + __IO uint32_t CHCR; + __IO uint32_t CHMAD; +} CHANNEL; + +/** + * @brief Configuration with temporary structure variable users will not be used directly + */ +typedef struct +{ + __IO uint32_t RESV; + __IO CHANNEL Channel[7]; + __IO uint32_t CH7CR; + __IO uint32_t CH7FLSAD; + __IO uint32_t CH7MAD; +} DMA_ADDR; + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup DMA_FL_Exported_Constants DMA Exported Constants + * @{ + */ + +#define DMA_GCR_ADDRERR_IE_Pos (1U) +#define DMA_GCR_ADDRERR_IE_Msk (0x1U << DMA_GCR_ADDRERR_IE_Pos) +#define DMA_GCR_ADDRERR_IE DMA_GCR_ADDRERR_IE_Msk + +#define DMA_GCR_EN_Pos (0U) +#define DMA_GCR_EN_Msk (0x1U << DMA_GCR_EN_Pos) +#define DMA_GCR_EN DMA_GCR_EN_Msk + +#define DMA_CHCR_TSIZE_Pos (16U) +#define DMA_CHCR_TSIZE_Msk (0xffffU << DMA_CHCR_TSIZE_Pos) +#define DMA_CHCR_TSIZE DMA_CHCR_TSIZE_Msk + +#define DMA_CHCR_PRI_Pos (12U) +#define DMA_CHCR_PRI_Msk (0x3U << DMA_CHCR_PRI_Pos) +#define DMA_CHCR_PRI DMA_CHCR_PRI_Msk + +#define DMA_CHCR_INC_Pos (11U) +#define DMA_CHCR_INC_Msk (0x1U << DMA_CHCR_INC_Pos) +#define DMA_CHCR_INC DMA_CHCR_INC_Msk + +#define DMA_CH7CR_MEMORY_INC_Pos (9U) +#define DMA_CH7CR_MEMORY_INC_Msk (0x1U << DMA_CH7CR_MEMORY_INC_Pos) +#define DMA_CH7CR_MEMORY_INC DMA_CH7CR_MEMORY_INC_Msk + +#define DMA_CH7CR_FLASH_INC_Pos (8U) +#define DMA_CH7CR_FLASH_INC_Msk (0x1U << DMA_CH7CR_FLASH_INC_Pos) +#define DMA_CH7CR_FLASH_INC DMA_CH7CR_FLASH_INC_Msk + +#define DMA_CHCR_SSEL_Pos (8U) +#define DMA_CHCR_SSEL_Msk (0x7U << DMA_CHCR_SSEL_Pos) +#define DMA_CHCR_SSEL DMA_CHCR_SSEL_Msk + +#define DMA_CHCR_DIR_Pos (6U) +#define DMA_CHCR_DIR_Msk (0x1U << DMA_CHCR_DIR_Pos) +#define DMA_CHCR_DIR DMA_CHCR_DIR_Msk + +#define DMA_CH7CR_DIR_Pos (10U) +#define DMA_CH7CR_DIR_Msk (0x1U << DMA_CH7CR_DIR_Pos) +#define DMA_CH7CR_DIR DMA_CH7CR_DIR_Msk + +#define DMA_CHCR_BDW_Pos (4U) +#define DMA_CHCR_BDW_Msk (0x3U << DMA_CHCR_BDW_Pos) +#define DMA_CHCR_BDW DMA_CHCR_BDW_Msk + +#define DMA_CHCR_CIRC_Pos (3U) +#define DMA_CHCR_CIRC_Msk (0x1U << DMA_CHCR_CIRC_Pos) +#define DMA_CHCR_CIRC DMA_CHCR_CIRC_Msk + +#define DMA_CHCR_FTIE_Pos (2U) +#define DMA_CHCR_FTIE_Msk (0x1U << DMA_CHCR_FTIE_Pos) +#define DMA_CHCR_FTIE DMA_CHCR_FTIE_Msk + +#define DMA_CHCR_HTIE_Pos (1U) +#define DMA_CHCR_HTIE_Msk (0x1U << DMA_CHCR_HTIE_Pos) +#define DMA_CHCR_HTIE DMA_CHCR_HTIE_Msk + +#define DMA_CHCR_EN_Pos (0U) +#define DMA_CHCR_EN_Msk (0x1U << DMA_CHCR_EN_Pos) +#define DMA_CHCR_EN DMA_CHCR_EN_Msk + +#define DMA_ISR_ADDRERR_Pos (16U) +#define DMA_ISR_ADDRERR_Msk (0x1U << DMA_ISR_ADDRERR_Pos) +#define DMA_ISR_ADDRERR DMA_ISR_ADDRERR_Msk + +#define DMA_ISR_CHFT_Pos (8U) +#define DMA_ISR_CHFT_Msk (0x1U << DMA_ISR_CHFT_Pos) +#define DMA_ISR_CHFT DMA_ISR_CHFT_Msk + +#define DMA_ISR_CHHT_Pos (0U) +#define DMA_ISR_CHHT_Msk (0x1U << DMA_ISR_CHHT_Pos) +#define DMA_ISR_CHHT DMA_ISR_CHHT_Msk + + + +#define FL_DMA_CHANNEL_0 (0x0U << 0U) +#define FL_DMA_CHANNEL_1 (0x1U << 0U) +#define FL_DMA_CHANNEL_2 (0x2U << 0U) +#define FL_DMA_CHANNEL_3 (0x3U << 0U) +#define FL_DMA_CHANNEL_4 (0x4U << 0U) +#define FL_DMA_CHANNEL_5 (0x5U << 0U) +#define FL_DMA_CHANNEL_6 (0x6U << 0U) +#define FL_DMA_CHANNEL_7 (0x7U << 0U) + + + +#define FL_DMA_PRIORITY_LOW (0x0U << DMA_CHCR_PRI_Pos) +#define FL_DMA_PRIORITY_MEDIUM (0x1U << DMA_CHCR_PRI_Pos) +#define FL_DMA_PRIORITY_HIGH (0x2U << DMA_CHCR_PRI_Pos) +#define FL_DMA_PRIORITY_VERYHIGH (0x3U << DMA_CHCR_PRI_Pos) + + +#define FL_DMA_MEMORY_INC_MODE_INCREASE (0x1U << DMA_CHCR_INC_Pos) +#define FL_DMA_MEMORY_INC_MODE_DECREASE (0x0U << DMA_CHCR_INC_Pos) +#define FL_DMA_CH7_MEMORY_INC_MODE_INCREASE (0x1U << DMA_CH7CR_MEMORY_INC_Pos) +#define FL_DMA_CH7_MEMORY_INC_MODE_DECREASE (0x0U << DMA_CH7CR_MEMORY_INC_Pos) +#define FL_DMA_CH7_FLASH_INC_MODE_INCREASE (0x1U << DMA_CH7CR_FLASH_INC_Pos) +#define FL_DMA_CH7_FLASH_INC_MODE_DECREASE (0x0U << DMA_CH7CR_FLASH_INC_Pos) + + +#define FL_DMA_FLASH_INC_MODE_INCREASE (0x1U << DMA_CH7CR_FLASH_INC_Pos) +#define FL_DMA_FLASH_INC_MODE_DECREASE (0x0U << DMA_CH7CR_FLASH_INC_Pos) + + +#define FL_DMA_PERIPHERAL_FUNCTION1 (0x0U << DMA_CHCR_SSEL_Pos) +#define FL_DMA_PERIPHERAL_FUNCTION2 (0x1U << DMA_CHCR_SSEL_Pos) +#define FL_DMA_PERIPHERAL_FUNCTION3 (0x2U << DMA_CHCR_SSEL_Pos) +#define FL_DMA_PERIPHERAL_FUNCTION4 (0x3U << DMA_CHCR_SSEL_Pos) +#define FL_DMA_PERIPHERAL_FUNCTION5 (0x4U << DMA_CHCR_SSEL_Pos) +#define FL_DMA_PERIPHERAL_FUNCTION6 (0x5U << DMA_CHCR_SSEL_Pos) +#define FL_DMA_PERIPHERAL_FUNCTION7 (0x6U << DMA_CHCR_SSEL_Pos) +#define FL_DMA_PERIPHERAL_FUNCTION8 (0x7U << DMA_CHCR_SSEL_Pos) + + +#define FL_DMA_DIR_PERIPHERAL_TO_RAM (0x0U << DMA_CHCR_DIR_Pos) +#define FL_DMA_DIR_RAM_TO_PERIPHERAL (0x1U << DMA_CHCR_DIR_Pos) +#define FL_DMA_DIR_FLASH_TO_RAM (0x1U << DMA_CH7CR_DIR_Pos) +#define FL_DMA_DIR_RAM_TO_FLASH (0x0U << DMA_CH7CR_DIR_Pos) + + +#define FL_DMA_BANDWIDTH_8B (0x0U << DMA_CHCR_BDW_Pos) +#define FL_DMA_BANDWIDTH_16B (0x1U << DMA_CHCR_BDW_Pos) +#define FL_DMA_BANDWIDTH_32B (0x2U << DMA_CHCR_BDW_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup DMA_FL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** + * @brief DMA address error interrupt enable + * @rmtoll GCR ADDRERR_IE FL_DMA_EnableIT_AddressError + * @param DMAx DMA instance + * @retval None + */ +__STATIC_INLINE void FL_DMA_EnableIT_AddressError(DMA_Type *DMAx) +{ + SET_BIT(DMAx->GCR, DMA_GCR_ADDRERR_IE_Msk); +} + +/** + * @brief Get DMA address error interrupt enable status + * @rmtoll GCR ADDRERR_IE FL_DMA_IsEnabledIT_AddressError + * @param DMAx DMA instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_DMA_IsEnabledIT_AddressError(DMA_Type *DMAx) +{ + return (uint32_t)(READ_BIT(DMAx->GCR, DMA_GCR_ADDRERR_IE_Msk) == DMA_GCR_ADDRERR_IE_Msk); +} + +/** + * @brief DMA address error interrupt disable + * @rmtoll GCR ADDRERR_IE FL_DMA_DisableIT_AddressError + * @param DMAx DMA instance + * @retval None + */ +__STATIC_INLINE void FL_DMA_DisableIT_AddressError(DMA_Type *DMAx) +{ + CLEAR_BIT(DMAx->GCR, DMA_GCR_ADDRERR_IE_Msk); +} + +/** + * @brief DMA enable + * @rmtoll GCR EN FL_DMA_Enable + * @param DMAx DMA instance + * @retval None + */ +__STATIC_INLINE void FL_DMA_Enable(DMA_Type *DMAx) +{ + SET_BIT(DMAx->GCR, DMA_GCR_EN_Msk); +} + +/** + * @brief Get DMA enable status + * @rmtoll GCR EN FL_DMA_IsEnabled + * @param DMAx DMA instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_DMA_IsEnabled(DMA_Type *DMAx) +{ + return (uint32_t)(READ_BIT(DMAx->GCR, DMA_GCR_EN_Msk) == DMA_GCR_EN_Msk); +} + +/** + * @brief DMA disable + * @rmtoll GCR EN FL_DMA_Disable + * @param DMAx DMA instance + * @retval None + */ +__STATIC_INLINE void FL_DMA_Disable(DMA_Type *DMAx) +{ + CLEAR_BIT(DMAx->GCR, DMA_GCR_EN_Msk); +} + +/** + * @brief Set channelx transmission length + * @rmtoll CHCR TSIZE FL_DMA_WriteTransmissionSize + * @param DMAx DMA instance + * @param size + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_WriteTransmissionSize(DMA_Type *DMAx, uint32_t size, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + MODIFY_REG(Temp->Channel[channel].CHCR, (0xffffU << 16U), (size << 16U)); + } + else + { + MODIFY_REG(Temp->CH7CR, (0xffffU << 16U), (size << 16U)); + } +} + +/** + * @brief Get channelx transmission length + * @rmtoll CHCR TSIZE FL_DMA_ReadTransmissionSize + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval + */ +__STATIC_INLINE uint32_t FL_DMA_ReadTransmissionSize(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, 0xffffU) >> 16U); + } + else + { + return (uint32_t)(READ_BIT(Temp->CH7CR, 0xffffU) >> 16U); + } +} + +/** + * @brief Set channelx priority + * @rmtoll CHCR PRI FL_DMA_SetPriority + * @param DMAx DMA instance + * @param priority This parameter can be one of the following values: + * @arg @ref FL_DMA_PRIORITY_LOW + * @arg @ref FL_DMA_PRIORITY_MEDIUM + * @arg @ref FL_DMA_PRIORITY_HIGH + * @arg @ref FL_DMA_PRIORITY_VERYHIGH + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_SetPriority(DMA_Type *DMAx, uint32_t priority, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + MODIFY_REG(Temp->Channel[channel].CHCR, DMA_CHCR_PRI_Msk, priority); + } + else + { + MODIFY_REG(Temp->CH7CR, DMA_CHCR_PRI_Msk, priority); + } +} + +/** + * @brief Get channelx priority + * @rmtoll CHCR PRI FL_DMA_GetPriority + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref FL_DMA_PRIORITY_LOW + * @arg @ref FL_DMA_PRIORITY_MEDIUM + * @arg @ref FL_DMA_PRIORITY_HIGH + * @arg @ref FL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t FL_DMA_GetPriority(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_PRI_Msk)); + } + else + { + return (uint32_t)(READ_BIT(Temp->CH7CR, DMA_CHCR_PRI_Msk)); + } +} + +/** + * @brief Set channelx RAM address incremental + * @rmtoll CHCR INC FL_DMA_SetMemoryIncrementMode + * @param DMAx DMA instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_DMA_MEMORY_INC_MODE_INCREASE + * @arg @ref FL_DMA_MEMORY_INC_MODE_DECREASE + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_SetMemoryIncrementMode(DMA_Type *DMAx, uint32_t mode, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + MODIFY_REG(Temp->Channel[channel].CHCR, DMA_CHCR_INC_Msk, mode); + } + else + { + MODIFY_REG(Temp->CH7CR, DMA_CH7CR_MEMORY_INC_Msk, mode); + } +} + +/** + * @brief Get channelx RAM address incremental status + * @rmtoll CHCR INC FL_DMA_GetMemoryIncrementMode + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref FL_DMA_MEMORY_INC_MODE_INCREASE + * @arg @ref FL_DMA_MEMORY_INC_MODE_DECREASE + */ +__STATIC_INLINE uint32_t FL_DMA_GetMemoryIncrementMode(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_INC_Msk)); + } + else + { + return (uint32_t)(READ_BIT(Temp->CH7CR, DMA_CH7CR_MEMORY_INC_Msk)); + } +} + +/** + * @brief Set channel7 FLASH address incremental + * @rmtoll CH7CR FLASH_INC FL_DMA_SetFlashIncrementMode + * @param DMAx DMA instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_DMA_FLASH_INC_MODE_INCREASE + * @arg @ref FL_DMA_FLASH_INC_MODE_DECREASE + * @retval None + */ +__STATIC_INLINE void FL_DMA_SetFlashIncrementMode(DMA_Type *DMAx, uint32_t mode) +{ + MODIFY_REG(DMAx->CH7CR, DMA_CH7CR_FLASH_INC_Msk, mode); +} + +/** + * @brief Get channel7 FLASH address incremental status + * @rmtoll CH7CR FLASH_INC FL_DMA_GetFlashIncrementMode + * @param DMAx DMA instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_DMA_FLASH_INC_MODE_INCREASE + * @arg @ref FL_DMA_FLASH_INC_MODE_DECREASE + */ +__STATIC_INLINE uint32_t FL_DMA_GetFlashIncrementMode(DMA_Type *DMAx) +{ + return (uint32_t)(READ_BIT(DMAx->CH7CR, DMA_CH7CR_FLASH_INC_Msk)); +} + +/** + * @brief Channelx request source select + * @rmtoll CHCR SSEL FL_DMA_SetPeripheralMap + * @param DMAx DMA instance + * @param peripheral This parameter can be one of the following values: + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION1 + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION2 + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION3 + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION4 + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION5 + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION6 + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION7 + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION8 + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_SetPeripheralMap(DMA_Type *DMAx, uint32_t peripheral, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + MODIFY_REG(Temp->Channel[channel].CHCR, DMA_CHCR_SSEL_Msk, peripheral); + } +} + +/** + * @brief Get Channelx request source select status + * @rmtoll CHCR SSEL FL_DMA_GetPeripheralMap + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION1 + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION2 + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION3 + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION4 + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION5 + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION6 + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION7 + * @arg @ref FL_DMA_PERIPHERAL_FUNCTION8 + */ +__STATIC_INLINE uint32_t FL_DMA_GetPeripheralMap(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_SSEL_Msk)); + } + return 0; +} + +/** + * @brief Set channelx transmit direction + * @rmtoll CHCR DIR FL_DMA_SetTransmissionDirection + * @param DMAx DMA instance + * @param direction This parameter can be one of the following values: + * @arg @ref FL_DMA_DIR_PERIPHERAL_TO_RAM + * @arg @ref FL_DMA_DIR_RAM_TO_PERIPHERAL + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_SetTransmissionDirection(DMA_Type *DMAx, uint32_t direction, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + MODIFY_REG(Temp->Channel[channel].CHCR, DMA_CHCR_DIR_Msk, direction); + } + else + { + MODIFY_REG(Temp->CH7CR, DMA_CH7CR_DIR_Msk, direction); + } +} + +/** + * @brief Get channelx transmit direction + * @rmtoll CHCR DIR FL_DMA_GetTransmissionDirection + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref FL_DMA_DIR_PERIPHERAL_TO_RAM + * @arg @ref FL_DMA_DIR_RAM_TO_PERIPHERAL + */ +__STATIC_INLINE uint32_t FL_DMA_GetTransmissionDirection(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_DIR_Msk)); + } + else + { + return (uint32_t)(READ_BIT(Temp->CH7CR, DMA_CH7CR_DIR_Msk)); + } +} + +/** + * @brief Set transmit bandwidth + * @rmtoll CHCR BDW FL_DMA_SetBandwidth + * @param DMAx DMA instance + * @param bandwidth This parameter can be one of the following values: + * @arg @ref FL_DMA_BANDWIDTH_8B + * @arg @ref FL_DMA_BANDWIDTH_16B + * @arg @ref FL_DMA_BANDWIDTH_32B + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_SetBandwidth(DMA_Type *DMAx, uint32_t bandwidth, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + MODIFY_REG(Temp->Channel[channel].CHCR, DMA_CHCR_BDW_Msk, bandwidth); + } +} + +/** + * @brief Get transmit bandwidth + * @rmtoll CHCR BDW FL_DMA_GetBandwidth + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref FL_DMA_BANDWIDTH_8B + * @arg @ref FL_DMA_BANDWIDTH_16B + * @arg @ref FL_DMA_BANDWIDTH_32B + */ +__STATIC_INLINE uint32_t FL_DMA_GetBandwidth(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_BDW_Msk)); + } + return 0; +} + +/** + * @brief Circular mode enable + * @rmtoll CHCR CIRC FL_DMA_EnableCircularMode + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_EnableCircularMode(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + SET_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_CIRC_Msk); + } + else + { + SET_BIT(Temp->CH7CR, DMA_CHCR_CIRC_Msk); + } +} + +/** + * @brief Get circular mode enable status + * @rmtoll CHCR CIRC FL_DMA_IsEnabledCircularMode + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_DMA_IsEnabledCircularMode(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_CIRC_Msk) == DMA_CHCR_CIRC_Msk); + } + else + { + return (uint32_t)(READ_BIT(Temp->CH7CR, DMA_CHCR_CIRC_Msk) == DMA_CHCR_CIRC_Msk); + } +} + +/** + * @brief Circular mode disable + * @rmtoll CHCR CIRC FL_DMA_DisableCircularMode + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_DisableCircularMode(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + CLEAR_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_CIRC_Msk); + } + else + { + CLEAR_BIT(Temp->CH7CR, DMA_CHCR_CIRC_Msk); + } +} + +/** + * @brief channelx transmit finished interrupt enable + * @rmtoll CHCR FTIE FL_DMA_EnableIT_TransferComplete + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_EnableIT_TransferComplete(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + SET_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_FTIE_Msk); + } + else + { + SET_BIT(Temp->CH7CR, DMA_CHCR_FTIE_Msk); + } +} + +/** + * @brief Get channelx transmit finished interrupt enable status + * @rmtoll CHCR FTIE FL_DMA_IsEnabledIT_TransferComplete + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_DMA_IsEnabledIT_TransferComplete(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_FTIE_Msk) == DMA_CHCR_FTIE_Msk); + } + else + { + return (uint32_t)(READ_BIT(Temp->CH7CR, DMA_CHCR_FTIE_Msk) == DMA_CHCR_FTIE_Msk); + } +} + +/** + * @brief channelx transmit finished interrupt disable + * @rmtoll CHCR FTIE FL_DMA_DisableIT_TransferComplete + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_DisableIT_TransferComplete(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + CLEAR_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_FTIE_Msk); + } + else + { + CLEAR_BIT(Temp->CH7CR, DMA_CHCR_FTIE_Msk); + } +} + +/** + * @brief Channelx Half-transfer interrupt enable + * @rmtoll CHCR HTIE FL_DMA_EnableIT_TransferHalfComplete + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_EnableIT_TransferHalfComplete(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + SET_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_HTIE_Msk); + } + else + { + SET_BIT(Temp->CH7CR, DMA_CHCR_HTIE_Msk); + } +} + +/** + * @brief Get Channelx Half-transfer interrupt enable status + * @rmtoll CHCR HTIE FL_DMA_IsEnabledIT_TransferHalfComplete + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_DMA_IsEnabledIT_TransferHalfComplete(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_HTIE_Msk) == DMA_CHCR_HTIE_Msk); + } + else + { + return (uint32_t)(READ_BIT(Temp->CH7CR, DMA_CHCR_HTIE_Msk) == DMA_CHCR_HTIE_Msk); + } +} + +/** + * @brief Channelx Half-transfer interrupt disable + * @rmtoll CHCR HTIE FL_DMA_DisableIT_TransferHalfComplete + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_DisableIT_TransferHalfComplete(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + CLEAR_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_HTIE_Msk); + } + else + { + CLEAR_BIT(Temp->CH7CR, DMA_CHCR_HTIE_Msk); + } +} + +/** + * @brief Channelx enable + * @rmtoll CHCR EN FL_DMA_EnableChannel + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_EnableChannel(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + SET_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_EN_Msk); + } + else + { + SET_BIT(Temp->CH7CR, DMA_CHCR_EN_Msk); + } +} + +/** + * @brief Get channelx enable status + * @rmtoll CHCR EN FL_DMA_IsEnabledChannel + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_DMA_IsEnabledChannel(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_EN_Msk) == DMA_CHCR_EN_Msk); + } + else + { + return (uint32_t)(READ_BIT(Temp->CH7CR, DMA_CHCR_EN_Msk) == DMA_CHCR_EN_Msk); + } +} + +/** + * @brief Channelx disable + * @rmtoll CHCR EN FL_DMA_DisableChannel + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_DisableChannel(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + CLEAR_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_EN_Msk); + } + else + { + CLEAR_BIT(Temp->CH7CR, DMA_CHCR_EN_Msk); + } +} + +/** + * @brief Set channelx memory pointer address + * @rmtoll MEMAD FL_DMA_WriteMemoryAddress + * @param DMAx DMA instance + * @param data + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_WriteMemoryAddress(DMA_Type *DMAx, uint32_t data, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + MODIFY_REG(Temp->Channel[channel].CHMAD, (0xffffffffU), (data)); + } + else + { + MODIFY_REG(Temp->CH7MAD, (0xffffffffU), (data)); + } +} + +/** + * @brief Get channelx memory pointer address + * @rmtoll MEMAD FL_DMA_ReadMemoryAddress + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval + */ +__STATIC_INLINE uint32_t FL_DMA_ReadMemoryAddress(DMA_Type *DMAx, uint32_t channel) +{ + DMA_ADDR *Temp = (DMA_ADDR *)DMAx; + if(channel <= FL_DMA_CHANNEL_6) + { + return (uint32_t)(READ_BIT(Temp->Channel[channel].CHMAD, (0xffffffffU))); + } + else + { + return (uint32_t)(READ_BIT(Temp->CH7MAD, (0xffffffffU))); + } +} + +/** + * @brief Set channel7 flash pointer address + * @rmtoll CH7FLSAD FL_DMA_WriteFlashAddress + * @param DMAx DMA instance + * @param data + * @retval None + */ +__STATIC_INLINE void FL_DMA_WriteFlashAddress(DMA_Type *DMAx, uint32_t data) +{ + MODIFY_REG(DMAx->CH7FLSAD, (0xffffffffU << 0U), (data << 0U)); +} + +/** + * @brief Get channel7 flash pointer address + * @rmtoll CH7FLSAD FL_DMA_ReadFlashAddress + * @param DMAx DMA instance + * @retval + */ +__STATIC_INLINE uint32_t FL_DMA_ReadFlashAddress(DMA_Type *DMAx) +{ + return (uint32_t)(READ_BIT(DMAx->CH7FLSAD, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @brief Get DMA address error flag + * @rmtoll ISR ADDRERR FL_DMA_IsActiveFlag_AddressError + * @param DMAx DMA instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_DMA_IsActiveFlag_AddressError(DMA_Type *DMAx) +{ + return (uint32_t)(READ_BIT(DMAx->ISR, DMA_ISR_ADDRERR_Msk) == (DMA_ISR_ADDRERR_Msk)); +} + +/** + * @brief Clear DMA address error flag + * @rmtoll ISR ADDRERR FL_DMA_ClearFlag_AddressError + * @param DMAx DMA instance + * @retval None + */ +__STATIC_INLINE void FL_DMA_ClearFlag_AddressError(DMA_Type *DMAx) +{ + WRITE_REG(DMAx->ISR, DMA_ISR_ADDRERR_Msk); +} + +/** + * @brief Get DMA channelx finished-transfer flag + * @rmtoll ISR CHFT FL_DMA_IsActiveFlag_TransferComplete + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_DMA_IsActiveFlag_TransferComplete(DMA_Type *DMAx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(DMAx->ISR, ((0x1U << channel) << DMA_ISR_CHFT_Pos)) == ((0x1U << channel) << DMA_ISR_CHFT_Pos)); +} + +/** + * @brief Clear DMA channelx finished-transfer flag + * @rmtoll ISR CHFT FL_DMA_ClearFlag_TransferComplete + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_ClearFlag_TransferComplete(DMA_Type *DMAx, uint32_t channel) +{ + WRITE_REG(DMAx->ISR, (DMA_ISR_CHFT_Msk << channel)); +} + +/** + * @brief Get DMA channel half-transfer flag + * @rmtoll ISR CHHT FL_DMA_IsActiveFlag_TransferHalfComplete + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_DMA_IsActiveFlag_TransferHalfComplete(DMA_Type *DMAx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(DMAx->ISR, ((0x1U << channel) << DMA_ISR_CHHT_Pos)) == ((0x1U << channel) << DMA_ISR_CHHT_Pos)); +} + +/** + * @brief Clear DMA channel half-transfer flag + * @rmtoll ISR CHHT FL_DMA_ClearFlag_TransferHalfComplete + * @param DMAx DMA instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void FL_DMA_ClearFlag_TransferHalfComplete(DMA_Type *DMAx, uint32_t channel) +{ + WRITE_REG(DMAx->ISR, (DMA_ISR_CHHT_Msk << channel)); +} + +/** + * @} + */ + +/** @defgroup DMA_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_DMA_DeInit(DMA_Type *DMAx); +FL_ErrorStatus FL_DMA_Init(DMA_Type *DMAx, FL_DMA_InitTypeDef *initStruct, uint32_t channel); +void FL_DMA_StructInit(FL_DMA_InitTypeDef *initStruct); + +/** + * @} + */ + +/** @defgroup DMA_FL_EF_Operation Opeartion functions + * @{ + */ + +FL_ErrorStatus FL_DMA_StartTransmission(DMA_Type *DMAx, FL_DMA_ConfigTypeDef *configStruct, uint32_t channel); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_DMA_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.14-0.2 @ 2020-10-20*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_exti.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_exti.h new file mode 100644 index 0000000000..fa210d5e81 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_exti.h @@ -0,0 +1,123 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_exti.h + * @author FMSH Application Team + * @brief Head file of EXTI FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_EXTI_H +#define __FM33LC0XX_FL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_FL_ES_INIT EXTI Exported Init structures + * @{ + */ + +/** + * @brief FL EXTI Common Init Sturcture definition + */ +typedef struct +{ + /*! EXTI时钟源配置 */ + uint32_t clockSource; + +} FL_EXTI_CommonInitTypeDef; + +/** + * @brief FL EXTI Init Sturcture definition + */ +typedef struct +{ + /*! EXTI输入配置 */ + uint32_t input; + + /*! EXTI触发边沿配置 */ + uint32_t triggerEdge; + + /*! EXTI数字滤波配置 */ + uint32_t filter; + +} FL_EXTI_InitTypeDef; + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup EXTI_FL_Exported_Constants EXTI Exported Constants + * @{ + */ + + + +#define FL_GPIO_EXTI_INPUT_GROUP0 (0x0U << 0U) +#define FL_GPIO_EXTI_INPUT_GROUP1 (0x1U << 0U) +#define FL_GPIO_EXTI_INPUT_GROUP2 (0x2U << 0U) +#define FL_GPIO_EXTI_INPUT_GROUP3 (0x3U << 0U) + + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup EXTI_FL_Exported_Functions EXTI Exported Functions + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_FL_EF_Init Initialization and de-initialization functions + * @{ + */ + +FL_ErrorStatus FL_EXTI_CommonInit(FL_EXTI_CommonInitTypeDef *init); +FL_ErrorStatus FL_EXTI_CommonDeinit(void); +void FL_EXTI_CommonStructInit(FL_EXTI_CommonInitTypeDef *init); + +FL_ErrorStatus FL_EXTI_Init(uint32_t extiLineX, FL_EXTI_InitTypeDef *init); +FL_ErrorStatus FL_EXTI_DeInit(uint32_t extiLineX); +void FL_EXTI_StructInit(FL_EXTI_InitTypeDef *init); + +/** + * @} + */ + + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_EXTI_H */ + +/*************************Py_Code_Generator Version: 0.1-0.14-0.2 @ 2021-03-16*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_flash.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_flash.h new file mode 100644 index 0000000000..d7c5a106ba --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_flash.h @@ -0,0 +1,981 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_flash.h + * @author FMSH Application Team + * @brief Head file of FLASH FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_FLASH_H +#define __FM33LC0XX_FL_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_FL_ES_INIT FLASH Exported Init structures + * @{ + */ + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup FLASH_FL_Exported_Constants FLASH Exported Constants + * @{ + */ + +#define FLASH_RDCR_WAIT_Pos (0U) +#define FLASH_RDCR_WAIT_Msk (0x3U << FLASH_RDCR_WAIT_Pos) +#define FLASH_RDCR_WAIT FLASH_RDCR_WAIT_Msk + +#define FLASH_PFCR_PRFTEN_Pos (0U) +#define FLASH_PFCR_PRFTEN_Msk (0x1U << FLASH_PFCR_PRFTEN_Pos) +#define FLASH_PFCR_PRFTEN FLASH_PFCR_PRFTEN_Msk + +#define FLASH_OPTBR_IWDTSLP_Pos (31U) +#define FLASH_OPTBR_IWDTSLP_Msk (0x1U << FLASH_OPTBR_IWDTSLP_Pos) +#define FLASH_OPTBR_IWDTSLP FLASH_OPTBR_IWDTSLP_Msk + +#define FLASH_OPTBR_IFLOCK_Pos (17U) +#define FLASH_OPTBR_IFLOCK_Msk (0x3U << FLASH_OPTBR_IFLOCK_Pos) +#define FLASH_OPTBR_IFLOCK FLASH_OPTBR_IFLOCK_Msk + +#define FLASH_OPTBR_DFLSEN_Pos (10U) +#define FLASH_OPTBR_DFLSEN_Msk (0x1U << FLASH_OPTBR_DFLSEN_Pos) +#define FLASH_OPTBR_DFLSEN FLASH_OPTBR_DFLSEN_Msk + +#define FLASH_OPTBR_BTSEN_Pos (8U) +#define FLASH_OPTBR_BTSEN_Msk (0x3U << FLASH_OPTBR_BTSEN_Pos) +#define FLASH_OPTBR_BTSEN FLASH_OPTBR_BTSEN_Msk + +#define FLASH_OPTBR_ACLOCKEN_Pos (2U) +#define FLASH_OPTBR_ACLOCKEN_Msk (0x3U << FLASH_OPTBR_ACLOCKEN_Pos) +#define FLASH_OPTBR_ACLOCKEN FLASH_OPTBR_ACLOCKEN_Msk + +#define FLASH_OPTBR_DBRDPEN_Pos (0U) +#define FLASH_OPTBR_DBRDPEN_Msk (0x3U << FLASH_OPTBR_DBRDPEN_Pos) +#define FLASH_OPTBR_DBRDPEN FLASH_OPTBR_DBRDPEN_Msk + +#define FLASH_EPCR_ERTYPE_Pos (8U) +#define FLASH_EPCR_ERTYPE_Msk (0x3U << FLASH_EPCR_ERTYPE_Pos) +#define FLASH_EPCR_ERTYPE FLASH_EPCR_ERTYPE_Msk + +#define FLASH_EPCR_PREQ_Pos (1U) +#define FLASH_EPCR_PREQ_Msk (0x1U << FLASH_EPCR_PREQ_Pos) +#define FLASH_EPCR_PREQ FLASH_EPCR_PREQ_Msk + +#define FLASH_EPCR_EREQ_Pos (0U) +#define FLASH_EPCR_EREQ_Msk (0x1U << FLASH_EPCR_EREQ_Pos) +#define FLASH_EPCR_EREQ FLASH_EPCR_EREQ_Msk + +#define FLASH_IER_OPTIE_Pos (11U) +#define FLASH_IER_OPTIE_Msk (0x1U << FLASH_IER_OPTIE_Pos) +#define FLASH_IER_OPTIE FLASH_IER_OPTIE_Msk + +#define FLASH_IER_AUTHIE_Pos (10U) +#define FLASH_IER_AUTHIE_Msk (0x1U << FLASH_IER_AUTHIE_Pos) +#define FLASH_IER_AUTHIE FLASH_IER_AUTHIE_Msk + +#define FLASH_IER_KEYIE_Pos (9U) +#define FLASH_IER_KEYIE_Msk (0x1U << FLASH_IER_KEYIE_Pos) +#define FLASH_IER_KEYIE FLASH_IER_KEYIE_Msk + +#define FLASH_IER_CKIE_Pos (8U) +#define FLASH_IER_CKIE_Msk (0x1U << FLASH_IER_CKIE_Pos) +#define FLASH_IER_CKIE FLASH_IER_CKIE_Msk + +#define FLASH_IER_PRDIE_Pos (1U) +#define FLASH_IER_PRDIE_Msk (0x1U << FLASH_IER_PRDIE_Pos) +#define FLASH_IER_PRDIE FLASH_IER_PRDIE_Msk + +#define FLASH_IER_ERDIE_Pos (0U) +#define FLASH_IER_ERDIE_Msk (0x1U << FLASH_IER_ERDIE_Pos) +#define FLASH_IER_ERDIE FLASH_IER_ERDIE_Msk + +#define FLASH_ISR_KEYSTA_Pos (17U) +#define FLASH_ISR_KEYSTA_Msk (0x7U << FLASH_ISR_KEYSTA_Pos) +#define FLASH_ISR_KEYSTA FLASH_ISR_KEYSTA_Msk + +#define FLASH_ISR_BTSF_Pos (16U) +#define FLASH_ISR_BTSF_Msk (0x1U << FLASH_ISR_BTSF_Pos) +#define FLASH_ISR_BTSF FLASH_ISR_BTSF_Msk + +#define FLASH_ISR_OPTERR_Pos (11U) +#define FLASH_ISR_OPTERR_Msk (0x1U << FLASH_ISR_OPTERR_Pos) +#define FLASH_ISR_OPTERR FLASH_ISR_OPTERR_Msk + +#define FLASH_ISR_AUTHERR_Pos (10U) +#define FLASH_ISR_AUTHERR_Msk (0x1U << FLASH_ISR_AUTHERR_Pos) +#define FLASH_ISR_AUTHERR FLASH_ISR_AUTHERR_Msk + +#define FLASH_ISR_KEYERR_Pos (9U) +#define FLASH_ISR_KEYERR_Msk (0x1U << FLASH_ISR_KEYERR_Pos) +#define FLASH_ISR_KEYERR FLASH_ISR_KEYERR_Msk + +#define FLASH_ISR_CKERR_Pos (8U) +#define FLASH_ISR_CKERR_Msk (0x1U << FLASH_ISR_CKERR_Pos) +#define FLASH_ISR_CKERR FLASH_ISR_CKERR_Msk + +#define FLASH_ISR_PRD_Pos (1U) +#define FLASH_ISR_PRD_Msk (0x1U << FLASH_ISR_PRD_Pos) +#define FLASH_ISR_PRD FLASH_ISR_PRD_Msk + +#define FLASH_ISR_ERD_Pos (0U) +#define FLASH_ISR_ERD_Msk (0x1U << FLASH_ISR_ERD_Pos) +#define FLASH_ISR_ERD FLASH_ISR_ERD_Msk + + + +#define FL_FLASH_INFORMATION1_REGIN (0x1U << 17U) +#define FL_FLASH_INFORMATION2_REGIN (0x1U << 18U) +#define FL_FLASH_BLOCK_0 (0x1U << 0U) +#define FL_FLASH_BLOCK_1 (0x1U << 1U) +#define FL_FLASH_BLOCK_2 (0x1U << 2U) +#define FL_FLASH_BLOCK_3 (0x1U << 3U) +#define FL_FLASH_BLOCK_4 (0x1U << 4U) +#define FL_FLASH_BLOCK_5 (0x1U << 5U) +#define FL_FLASH_BLOCK_6 (0x1U << 6U) +#define FL_FLASH_BLOCK_7 (0x1U << 7U) +#define FL_FLASH_BLOCK_8 (0x1U << 8U) +#define FL_FLASH_BLOCK_9 (0x1U << 9U) +#define FL_FLASH_BLOCK_10 (0x1U << 10U) +#define FL_FLASH_BLOCK_11 (0x1U << 11U) +#define FL_FLASH_BLOCK_12 (0x1U << 12U) +#define FL_FLASH_BLOCK_13 (0x1U << 13U) +#define FL_FLASH_BLOCK_14 (0x1U << 14U) +#define FL_FLASH_BLOCK_15 (0x1U << 15U) +#define FL_FLASH_LOCK_ALL (0x0U << 0U) +#define FL_FLASH_LOCK_SOFTWARE (0x2U << 0U) +#define FL_FLASH_LOCK_NONE (0x3U << 0U) +#define FL_FLASH_BOOTSWAP_ENABLE (0x2U << 8U) +#define FL_FLASH_BOOTSWAP_DISABLE (0x0U << 8U) +#define FL_FLASH_APPCODE_LOCK_ENABLE (0x2U << 2U) +#define FL_FLASH_APPCODE_LOCK_DISABLE (0x0U << 2U) +#define FL_FLASH_DEBUG_READ_ENABLE (0x2U << 0U) +#define FL_FLASH_DEBUG_READ_DISABLE (0x0U << 0U) +#define FL_FLASH_ERASE_KEY 0x96969696U +#define FL_FLASH_CHIP_ERASE_KEY 0x7D7D7D7DU +#define FL_FLASH_PAGE_ERASE_KEY 0xEAEAEAEAU +#define FL_FLASH_SECTOR_ERASE_KEY 0x3C3C3C3CU +#define FL_FLASH_ERASE_REQUEST 0x1234ABCDU +#define FL_FLASH_PROGRAM_KEY1 0xA5A5A5A5U +#define FL_FLASH_PROGRAM_KEY2 0xF1F1F1F1U +#define FL_FLASH_ERASE_TIMEOUT 0x0000FFFFU +#define FL_FLASH_ADDRS_ALIGN 0x00000004U +#define FL_FLASH_MAX_PAGE_NUM 0x00000200U +#define FL_FLASH_MAX_SECTOR_NUM 0x00000080U +#define FL_FLASH_SECTOR_SIZE_BYTE 0x00000800U +#define FL_FLASH_PAGE_SIZE_BYTE 0x00000200U +#define FL_FLASH_ADDR_MAXPROGRAM 0x0003FFFFU + + + +#define FL_FLASH_READ_WAIT_0CYCLE (0x0U << FLASH_RDCR_WAIT_Pos) +#define FL_FLASH_READ_WAIT_1CYCLE (0x1U << FLASH_RDCR_WAIT_Pos) +#define FL_FLASH_READ_WAIT_2CYCLE (0x2U << FLASH_RDCR_WAIT_Pos) + + +#define FL_FLASH_IWDT_STOP_UNDER_SLEEP (0x0U << FLASH_OPTBR_IWDTSLP_Pos) +#define FL_FLASH_IWDT_WORK_UNDER_SLEEP (0x1U << FLASH_OPTBR_IWDTSLP_Pos) + +#define FL_FLASH_IF_UNLOCK (0x0U << FLASH_OPTBR_IFLOCK_Pos) +#define FL_FLASH_IF_LOCK (0x1U << FLASH_OPTBR_IFLOCK_Pos) + +#define FL_FLASH_DATA_FLASH_DISABLE (0x0U << FLASH_OPTBR_DFLSEN_Pos) +#define FL_FLASH_DATA_FLASH_ENABLE (0x1U << FLASH_OPTBR_DFLSEN_Pos) + +#define FL_FLASH_BOOT_SWAP_DISABLE (0x0U << FLASH_OPTBR_BTSEN_Pos) +#define FL_FLASH_BOOT_SWAP_ENABLE (0x1U << FLASH_OPTBR_BTSEN_Pos) + +#define FL_FLASH_FLASH_LOCK_DISABLE (0x0U << FLASH_OPTBR_ACLOCKEN_Pos) +#define FL_FLASH_FLASH_LOCK_ENABLE (0x1U << FLASH_OPTBR_ACLOCKEN_Pos) + +#define FL_FLASH_SWD_READ_PEOTECTION_DISABLE (0x0U << FLASH_OPTBR_DBRDPEN_Pos) +#define FL_FLASH_SWD_READ_PEOTECTION_ENABLE (0x1U << FLASH_OPTBR_DBRDPEN_Pos) + +#define FL_FLASH_ERASE_TYPE_PAGE (0x0U << FLASH_EPCR_ERTYPE_Pos) +#define FL_FLASH_ERASE_TYPE_SECTOR (0x1U << FLASH_EPCR_ERTYPE_Pos) + + +#define FL_FLASH_KEY_STATUS_LOCK (0x0U << FLASH_ISR_KEYSTA_Pos) +#define FL_FLASH_KEY_STATUS_PAGE_ERASE (0x2U << FLASH_ISR_KEYSTA_Pos) +#define FL_FLASH_KEY_STATUS_PROGRAM (0x3U << FLASH_ISR_KEYSTA_Pos) +#define FL_FLASH_KEY_STATUS_ERROR (0x4U << FLASH_ISR_KEYSTA_Pos) +#define FL_FLASH_KEY_STATUS_SECTOR_ERASE (0x5U << FLASH_ISR_KEYSTA_Pos) + +#define FL_FLASH_BOOT_SECTOR_0000H_1FFFH (0x0U << FLASH_ISR_BTSF_Pos) +#define FL_FLASH_BOOT_SECTOR_2000H_3FFFH (0x1U << FLASH_ISR_BTSF_Pos) + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup FLASH_FL_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** + * @brief Flash wait cycles config + * @rmtoll RDCR WAIT FL_FLASH_SetReadWait + * @param FLASHx FLASH instance + * @param wait This parameter can be one of the following values: + * @arg @ref FL_FLASH_READ_WAIT_0CYCLE + * @arg @ref FL_FLASH_READ_WAIT_1CYCLE + * @arg @ref FL_FLASH_READ_WAIT_2CYCLE + * @retval None + */ +__STATIC_INLINE void FL_FLASH_SetReadWait(FLASH_Type *FLASHx, uint32_t wait) +{ + MODIFY_REG(FLASHx->RDCR, FLASH_RDCR_WAIT_Msk, wait); +} + +/** + * @brief Get flash wait cycles config status + * @rmtoll RDCR WAIT FL_FLASH_GetReadWait + * @param FLASHx FLASH instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_FLASH_READ_WAIT_0CYCLE + * @arg @ref FL_FLASH_READ_WAIT_1CYCLE + * @arg @ref FL_FLASH_READ_WAIT_2CYCLE + */ +__STATIC_INLINE uint32_t FL_FLASH_GetReadWait(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->RDCR, FLASH_RDCR_WAIT_Msk)); +} + +/** + * @brief Prefetch Enable + * @rmtoll PFCR PRFTEN FL_FLASH_EnablePrefetch + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_EnablePrefetch(FLASH_Type *FLASHx) +{ + SET_BIT(FLASHx->PFCR, FLASH_PFCR_PRFTEN_Msk); +} + +/** + * @brief Get prefetch enable status + * @rmtoll PFCR PRFTEN FL_FLASH_IsEnabledPrefetch + * @param FLASHx FLASH instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FLASH_IsEnabledPrefetch(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->PFCR, FLASH_PFCR_PRFTEN_Msk) == FLASH_PFCR_PRFTEN_Msk); +} + +/** + * @brief Prefetch disable + * @rmtoll PFCR PRFTEN FL_FLASH_DisablePrefetch + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_DisablePrefetch(FLASH_Type *FLASHx) +{ + CLEAR_BIT(FLASHx->PFCR, FLASH_PFCR_PRFTEN_Msk); +} + +/** + * @brief Get IWDT sleep enable status + * @rmtoll OPTBR IWDTSLP FL_FLASH_GetIWDTStateUnderSleep + * @param FLASHx FLASH instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_FLASH_IWDT_STOP_UNDER_SLEEP + * @arg @ref FL_FLASH_IWDT_WORK_UNDER_SLEEP + */ +__STATIC_INLINE uint32_t FL_FLASH_GetIWDTStateUnderSleep(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->OPTBR, FLASH_OPTBR_IWDTSLP_Msk)); +} + +/** + * @brief Get information2 lock enable flag + * @rmtoll OPTBR IFLOCK FL_FLASH_IsActiveFlag_IFLockedState + * @param FLASHx FLASH instance + * @param region This parameter can be one of the following values: + * @arg @ref FL_FLASH_INFORMATION1_REGIN + * @arg @ref FL_FLASH_INFORMATION2_REGIN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FLASH_IsActiveFlag_IFLockedState(FLASH_Type *FLASHx, uint32_t region) +{ + return (uint32_t)(READ_BIT(FLASHx->OPTBR, FLASH_OPTBR_IFLOCK_Msk) == (FLASH_OPTBR_IFLOCK_Msk)); +} + +/** + * @brief Get dataflash enable status + * @rmtoll OPTBR DFLSEN FL_FLASH_GetDataFlashState + * @param FLASHx FLASH instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_FLASH_DATA_FLASH_DISABLE + * @arg @ref FL_FLASH_DATA_FLASH_ENABLE + */ +__STATIC_INLINE uint32_t FL_FLASH_GetDataFlashState(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->OPTBR, FLASH_OPTBR_DFLSEN_Msk)); +} + +/** + * @brief Get BootSwap enable status + * @rmtoll OPTBR BTSEN FL_FLASH_GetBootSwapState + * @param FLASHx FLASH instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_FLASH_BOOT_SWAP_DISABLE + * @arg @ref FL_FLASH_BOOT_SWAP_ENABLE + */ +__STATIC_INLINE uint32_t FL_FLASH_GetBootSwapState(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->OPTBR, FLASH_OPTBR_BTSEN_Msk)); +} + +/** + * @brief Get AppCode lock enable + * @rmtoll OPTBR ACLOCKEN FL_FLASH_GetFlashLockState + * @param FLASHx FLASH instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_FLASH_FLASH_LOCK_DISABLE + * @arg @ref FL_FLASH_FLASH_LOCK_ENABLE + */ +__STATIC_INLINE uint32_t FL_FLASH_GetFlashLockState(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->OPTBR, FLASH_OPTBR_ACLOCKEN_Msk)); +} + +/** + * @brief Get debug read protection enable status + * @rmtoll OPTBR DBRDPEN FL_FLASH_GetSWDReadProtectionState + * @param FLASHx FLASH instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_FLASH_SWD_READ_PEOTECTION_DISABLE + * @arg @ref FL_FLASH_SWD_READ_PEOTECTION_ENABLE + */ +__STATIC_INLINE uint32_t FL_FLASH_GetSWDReadProtectionState(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->OPTBR, FLASH_OPTBR_DBRDPEN_Msk)); +} + +/** + * @brief Set ACLOCK register low 32 bit + * @rmtoll ACLOCK1 FL_FLASH_SetFlashLowRegionLock + * @param FLASHx FLASH instance + * @param region This parameter can be one of the following values: + * @arg @ref FL_FLASH_BLOCK_0 + * @arg @ref FL_FLASH_BLOCK_1 + * @arg @ref FL_FLASH_BLOCK_2 + * @arg @ref FL_FLASH_BLOCK_3 + * @arg @ref FL_FLASH_BLOCK_4 + * @arg @ref FL_FLASH_BLOCK_5 + * @arg @ref FL_FLASH_BLOCK_6 + * @arg @ref FL_FLASH_BLOCK_7 + * @arg @ref FL_FLASH_BLOCK_8 + * @arg @ref FL_FLASH_BLOCK_9 + * @arg @ref FL_FLASH_BLOCK_10 + * @arg @ref FL_FLASH_BLOCK_11 + * @arg @ref FL_FLASH_BLOCK_12 + * @arg @ref FL_FLASH_BLOCK_13 + * @arg @ref FL_FLASH_BLOCK_14 + * @arg @ref FL_FLASH_BLOCK_15 + * @param mode This parameter can be one of the following values: + * @arg @ref FL_FLASH_LOCK_ALL + * @arg @ref FL_FLASH_LOCK_SOFTWARE + * @arg @ref FL_FLASH_LOCK_NONE + * @retval None + */ +__STATIC_INLINE void FL_FLASH_SetFlashLowRegionLock(FLASH_Type *FLASHx, uint32_t region, uint32_t mode) +{ + CLEAR_BIT(FLASHx->ACLOCK1, ((region * region) * (((mode == 3) ? 0 : (~mode)) & 0x03))); +} + +/** + * @brief Get ACLOCK register low 32 bit status + * @rmtoll ACLOCK1 FL_FLASH_GetFlashLowRegionLock + * @param FLASHx FLASH instance + * @param region This parameter can be one of the following values: + * @arg @ref FL_FLASH_BLOCK_0 + * @arg @ref FL_FLASH_BLOCK_1 + * @arg @ref FL_FLASH_BLOCK_2 + * @arg @ref FL_FLASH_BLOCK_3 + * @arg @ref FL_FLASH_BLOCK_4 + * @arg @ref FL_FLASH_BLOCK_5 + * @arg @ref FL_FLASH_BLOCK_6 + * @arg @ref FL_FLASH_BLOCK_7 + * @arg @ref FL_FLASH_BLOCK_8 + * @arg @ref FL_FLASH_BLOCK_9 + * @arg @ref FL_FLASH_BLOCK_10 + * @arg @ref FL_FLASH_BLOCK_11 + * @arg @ref FL_FLASH_BLOCK_12 + * @arg @ref FL_FLASH_BLOCK_13 + * @arg @ref FL_FLASH_BLOCK_14 + * @arg @ref FL_FLASH_BLOCK_15 + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_FLASH_GetFlashLowRegionLock(FLASH_Type *FLASHx, uint32_t region) +{ + return (uint32_t)(READ_BIT(FLASHx->ACLOCK1, ((region * region) * 0x03)) / (region * region)); +} + +/** + * @brief Set ACLOCK register high 32 bit + * @rmtoll ACLOCK2 FL_FLASH_SetFlashHighRegionLock + * @param FLASHx FLASH instance + * @param region This parameter can be one of the following values: + * @arg @ref FL_FLASH_BLOCK_0 + * @arg @ref FL_FLASH_BLOCK_1 + * @arg @ref FL_FLASH_BLOCK_2 + * @arg @ref FL_FLASH_BLOCK_3 + * @arg @ref FL_FLASH_BLOCK_4 + * @arg @ref FL_FLASH_BLOCK_5 + * @arg @ref FL_FLASH_BLOCK_6 + * @arg @ref FL_FLASH_BLOCK_7 + * @arg @ref FL_FLASH_BLOCK_8 + * @arg @ref FL_FLASH_BLOCK_9 + * @arg @ref FL_FLASH_BLOCK_10 + * @arg @ref FL_FLASH_BLOCK_11 + * @arg @ref FL_FLASH_BLOCK_12 + * @arg @ref FL_FLASH_BLOCK_13 + * @arg @ref FL_FLASH_BLOCK_14 + * @arg @ref FL_FLASH_BLOCK_15 + * @param mode This parameter can be one of the following values: + * @arg @ref FL_FLASH_LOCK_ALL + * @arg @ref FL_FLASH_LOCK_SOFTWARE + * @arg @ref FL_FLASH_LOCK_NONE + * @retval None + */ +__STATIC_INLINE void FL_FLASH_SetFlashHighRegionLock(FLASH_Type *FLASHx, uint32_t region, uint32_t mode) +{ + CLEAR_BIT(FLASHx->ACLOCK2, ((region * region) * (((mode == 3) ? 0 : (~mode)) & 0x03))); +} + +/** + * @brief Get ACLOCK register high 32 bit status + * @rmtoll ACLOCK2 FL_FLASH_GetFlashHighRegionLock + * @param FLASHx FLASH instance + * @param region This parameter can be one of the following values: + * @arg @ref FL_FLASH_BLOCK_0 + * @arg @ref FL_FLASH_BLOCK_1 + * @arg @ref FL_FLASH_BLOCK_2 + * @arg @ref FL_FLASH_BLOCK_3 + * @arg @ref FL_FLASH_BLOCK_4 + * @arg @ref FL_FLASH_BLOCK_5 + * @arg @ref FL_FLASH_BLOCK_6 + * @arg @ref FL_FLASH_BLOCK_7 + * @arg @ref FL_FLASH_BLOCK_8 + * @arg @ref FL_FLASH_BLOCK_9 + * @arg @ref FL_FLASH_BLOCK_10 + * @arg @ref FL_FLASH_BLOCK_11 + * @arg @ref FL_FLASH_BLOCK_12 + * @arg @ref FL_FLASH_BLOCK_13 + * @arg @ref FL_FLASH_BLOCK_14 + * @arg @ref FL_FLASH_BLOCK_15 + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_FLASH_GetFlashHighRegionLock(FLASH_Type *FLASHx, uint32_t region) +{ + return (uint32_t)(READ_BIT(FLASHx->ACLOCK2, ((region * region) * 0x03)) / (region * region)); +} + +/** + * @brief Set flash erase type + * @rmtoll EPCR ERTYPE FL_FLASH_SetFlashEraseType + * @param FLASHx FLASH instance + * @param type This parameter can be one of the following values: + * @arg @ref FL_FLASH_ERASE_TYPE_PAGE + * @arg @ref FL_FLASH_ERASE_TYPE_SECTOR + * @retval None + */ +__STATIC_INLINE void FL_FLASH_SetFlashEraseType(FLASH_Type *FLASHx, uint32_t type) +{ + MODIFY_REG(FLASHx->EPCR, FLASH_EPCR_ERTYPE_Msk, type); +} + +/** + * @brief Get flash erase type + * @rmtoll EPCR ERTYPE FL_FLASH_GetFlashEraseType + * @param FLASHx FLASH instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_FLASH_ERASE_TYPE_PAGE + * @arg @ref FL_FLASH_ERASE_TYPE_SECTOR + */ +__STATIC_INLINE uint32_t FL_FLASH_GetFlashEraseType(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->EPCR, FLASH_EPCR_ERTYPE_Msk)); +} + +/** + * @brief Program request enable + * @rmtoll EPCR PREQ FL_FLASH_EnableProgram + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_EnableProgram(FLASH_Type *FLASHx) +{ + CLEAR_BIT(FLASHx->EPCR, FLASH_EPCR_EREQ_Msk); + SET_BIT(FLASHx->EPCR, FLASH_EPCR_PREQ_Msk); +} + +/** + * @brief Erase request enable + * @rmtoll EPCR EREQ FL_FLASH_EnableErase + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_EnableErase(FLASH_Type *FLASHx) +{ + CLEAR_BIT(FLASHx->EPCR, FLASH_EPCR_PREQ_Msk); + SET_BIT(FLASHx->EPCR, FLASH_EPCR_EREQ_Msk); +} + +/** + * @brief Set flash key + * @rmtoll KEY FL_FLASH_UnlockFlash + * @param FLASHx FLASH instance + * @param key + * @retval None + */ +__STATIC_INLINE void FL_FLASH_UnlockFlash(FLASH_Type *FLASHx, uint32_t key) +{ + WRITE_REG(FLASHx->KEY, key); +} + +/** + * @brief Reset flash key + * @rmtoll KEY FL_FLASH_LockFlash + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_LockFlash(FLASH_Type *FLASHx) +{ + WRITE_REG(FLASHx->KEY, 0xFFFFFFFF); +} + +/** + * @brief OTP program error interrupt enable + * @rmtoll IER OPTIE FL_FLASH_EnableIT_OTPProgramError + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_EnableIT_OTPProgramError(FLASH_Type *FLASHx) +{ + SET_BIT(FLASHx->IER, FLASH_IER_OPTIE_Msk); +} + +/** + * @brief OTP program error interrupt disable + * @rmtoll IER OPTIE FL_FLASH_DisableIT_OTPProgramError + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_DisableIT_OTPProgramError(FLASH_Type *FLASHx) +{ + CLEAR_BIT(FLASHx->IER, FLASH_IER_OPTIE_Msk); +} + +/** + * @brief Get OTP program error interrupt enable status + * @rmtoll IER OPTIE FL_FLASH_IsEnabledIT_OTPProgramError + * @param FLASHx FLASH instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FLASH_IsEnabledIT_OTPProgramError(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->IER, FLASH_IER_OPTIE_Msk) == FLASH_IER_OPTIE_Msk); +} + +/** + * @brief Flash authentication error interrupt enable + * @rmtoll IER AUTHIE FL_FLASH_EnableIT_AuthenticationError + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_EnableIT_AuthenticationError(FLASH_Type *FLASHx) +{ + SET_BIT(FLASHx->IER, FLASH_IER_AUTHIE_Msk); +} + +/** + * @brief Flash authentication error interrupt disable + * @rmtoll IER AUTHIE FL_FLASH_DisableIT_AuthenticationError + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_DisableIT_AuthenticationError(FLASH_Type *FLASHx) +{ + CLEAR_BIT(FLASHx->IER, FLASH_IER_AUTHIE_Msk); +} + +/** + * @brief Get flash authentication error interrupt enable status + * @rmtoll IER AUTHIE FL_FLASH_IsEnabledIT_AuthenticationError + * @param FLASHx FLASH instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FLASH_IsEnabledIT_AuthenticationError(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->IER, FLASH_IER_AUTHIE_Msk) == FLASH_IER_AUTHIE_Msk); +} + +/** + * @brief Flash key error interrupt enable + * @rmtoll IER KEYIE FL_FLASH_EnableIT_KeyError + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_EnableIT_KeyError(FLASH_Type *FLASHx) +{ + SET_BIT(FLASHx->IER, FLASH_IER_KEYIE_Msk); +} + +/** + * @brief Flash key error interrupt disable + * @rmtoll IER KEYIE FL_FLASH_DisableIT_KeyError + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_DisableIT_KeyError(FLASH_Type *FLASHx) +{ + CLEAR_BIT(FLASHx->IER, FLASH_IER_KEYIE_Msk); +} + +/** + * @brief Get Flash key error interrupt enable status + * @rmtoll IER KEYIE FL_FLASH_IsEnabledIT_KeyError + * @param FLASHx FLASH instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FLASH_IsEnabledIT_KeyError(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->IER, FLASH_IER_KEYIE_Msk) == FLASH_IER_KEYIE_Msk); +} + +/** + * @brief Erase/Program clock error interrupt enable + * @rmtoll IER CKIE FL_FLASH_EnableIT_ClockError + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_EnableIT_ClockError(FLASH_Type *FLASHx) +{ + SET_BIT(FLASHx->IER, FLASH_IER_CKIE_Msk); +} + +/** + * @brief Erase/Program clock error interrupt disable + * @rmtoll IER CKIE FL_FLASH_DisableIT_ClockError + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_DisableIT_ClockError(FLASH_Type *FLASHx) +{ + CLEAR_BIT(FLASHx->IER, FLASH_IER_CKIE_Msk); +} + +/** + * @brief Get Erase/Program clock error interrupt enable status + * @rmtoll IER CKIE FL_FLASH_IsEnabledIT_ClockError + * @param FLASHx FLASH instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FLASH_IsEnabledIT_ClockError(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->IER, FLASH_IER_CKIE_Msk) == FLASH_IER_CKIE_Msk); +} + +/** + * @brief Program done interrupt enable + * @rmtoll IER PRDIE FL_FLASH_EnableIT_ProgramComplete + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_EnableIT_ProgramComplete(FLASH_Type *FLASHx) +{ + SET_BIT(FLASHx->IER, FLASH_IER_PRDIE_Msk); +} + +/** + * @brief Program done interrupt disable + * @rmtoll IER PRDIE FL_FLASH_DisableIT_ProgramComplete + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_DisableIT_ProgramComplete(FLASH_Type *FLASHx) +{ + CLEAR_BIT(FLASHx->IER, FLASH_IER_PRDIE_Msk); +} + +/** + * @brief Get program done interrupt enable status + * @rmtoll IER PRDIE FL_FLASH_IsEnabledIT_ProgramComplete + * @param FLASHx FLASH instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FLASH_IsEnabledIT_ProgramComplete(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->IER, FLASH_IER_PRDIE_Msk) == FLASH_IER_PRDIE_Msk); +} + +/** + * @brief Erase done interrupt enable + * @rmtoll IER ERDIE FL_FLASH_EnableIT_EraseComplete + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_EnableIT_EraseComplete(FLASH_Type *FLASHx) +{ + SET_BIT(FLASHx->IER, FLASH_IER_ERDIE_Msk); +} + +/** + * @brief Erase done interrupt disable + * @rmtoll IER ERDIE FL_FLASH_DisableIT_EraseComplete + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_DisableIT_EraseComplete(FLASH_Type *FLASHx) +{ + CLEAR_BIT(FLASHx->IER, FLASH_IER_ERDIE_Msk); +} + +/** + * @brief Get erase done interrupt enable status + * @rmtoll IER ERDIE FL_FLASH_IsEnabledIT_EraseComplete + * @param FLASHx FLASH instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FLASH_IsEnabledIT_EraseComplete(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->IER, FLASH_IER_ERDIE_Msk) == FLASH_IER_ERDIE_Msk); +} + +/** + * @brief Get flash key status + * @rmtoll ISR KEYSTA FL_FLASH_GetFlashLockStatus + * @param FLASHx FLASH instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_FLASH_KEY_STATUS_LOCK + * @arg @ref FL_FLASH_KEY_STATUS_PAGE_ERASE + * @arg @ref FL_FLASH_KEY_STATUS_PROGRAM + * @arg @ref FL_FLASH_KEY_STATUS_ERROR + * @arg @ref FL_FLASH_KEY_STATUS_SECTOR_ERASE + */ +__STATIC_INLINE uint32_t FL_FLASH_GetFlashLockStatus(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->ISR, FLASH_ISR_KEYSTA_Msk)); +} + +/** + * @brief Get BootSwap +register value + * @rmtoll ISR BTSF FL_FLASH_GetFlashSwapStatus + * @param FLASHx FLASH instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_FLASH_BOOT_SECTOR_0000H_1FFFH + * @arg @ref FL_FLASH_BOOT_SECTOR_2000H_3FFFH + */ +__STATIC_INLINE uint32_t FL_FLASH_GetFlashSwapStatus(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->ISR, FLASH_ISR_BTSF_Msk)); +} + +/** + * @brief Get OTP program Error Flag + * @rmtoll ISR OPTERR FL_FLASH_IsActiveFlag_OPTProgramError + * @param FLASHx FLASH instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FLASH_IsActiveFlag_OPTProgramError(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->ISR, FLASH_ISR_OPTERR_Msk) == (FLASH_ISR_OPTERR_Msk)); +} + +/** + * @brief Clear OTP program Error Flag + * @rmtoll ISR OPTERR FL_FLASH_ClearFlag_OPTProgramError + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_ClearFlag_OPTProgramError(UART_Type *UARTx) +{ + WRITE_REG(UARTx->ISR, FLASH_ISR_OPTERR_Msk); +} + +/** + * @brief Get Flash Authentication Error Flag + * @rmtoll ISR AUTHERR FL_FLASH_IsActiveFlag_AuthenticationError + * @param FLASHx FLASH instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FLASH_IsActiveFlag_AuthenticationError(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->ISR, FLASH_ISR_AUTHERR_Msk) == (FLASH_ISR_AUTHERR_Msk)); +} + +/** + * @brief ClearFlash Authentication Error Flag + * @rmtoll ISR AUTHERR FL_FLASH_ClearFlag_AuthenticationError + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_ClearFlag_AuthenticationError(FLASH_Type *FLASHx) +{ + WRITE_REG(FLASHx->ISR, FLASH_ISR_AUTHERR_Msk); +} + +/** + * @brief Get Flash Key Error Flag + * @rmtoll ISR KEYERR FL_FLASH_IsActiveFlag_KeyError + * @param FLASHx FLASH instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FLASH_IsActiveFlag_KeyError(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->ISR, FLASH_ISR_KEYERR_Msk) == (FLASH_ISR_KEYERR_Msk)); +} + +/** + * @brief Clear Flash Key Error Flag + * @rmtoll ISR KEYERR FL_FLASH_ClearFlag_KeyError + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_ClearFlag_KeyError(FLASH_Type *FLASHx) +{ + WRITE_REG(FLASHx->ISR, FLASH_ISR_KEYERR_Msk); +} + +/** + * @brief Get Erase/Program Clock Error Flag + * @rmtoll ISR CKERR FL_FLASH_IsActiveFlag_ClockError + * @param FLASHx FLASH instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FLASH_IsActiveFlag_ClockError(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->ISR, FLASH_ISR_CKERR_Msk) == (FLASH_ISR_CKERR_Msk)); +} + +/** + * @brief Clear Erase/Program Clock Error Flag + * @rmtoll ISR CKERR FL_FLASH_ClearFlag_ClockError + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_ClearFlag_ClockError(FLASH_Type *FLASHx) +{ + WRITE_REG(FLASHx->ISR, FLASH_ISR_CKERR_Msk); +} + +/** + * @brief Get Program Done Flag + * @rmtoll ISR PRD FL_FLASH_IsActiveFlag_ProgramComplete + * @param FLASHx FLASH instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FLASH_IsActiveFlag_ProgramComplete(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->ISR, FLASH_ISR_PRD_Msk) == (FLASH_ISR_PRD_Msk)); +} + +/** + * @brief Clear Program Done Flag + * @rmtoll ISR PRD FL_FLASH_ClearFlag_ProgramComplete + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_ClearFlag_ProgramComplete(FLASH_Type *FLASHx) +{ + WRITE_REG(FLASHx->ISR, FLASH_ISR_PRD_Msk); +} + +/** + * @brief Get Erase Done Flag + * @rmtoll ISR ERD FL_FLASH_IsActiveFlag_EraseComplete + * @param FLASHx FLASH instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FLASH_IsActiveFlag_EraseComplete(FLASH_Type *FLASHx) +{ + return (uint32_t)(READ_BIT(FLASHx->ISR, FLASH_ISR_ERD_Msk) == (FLASH_ISR_ERD_Msk)); +} + +/** + * @brief Clear Erase Done Flag + * @rmtoll ISR ERD FL_FLASH_ClearFlag_EraseComplete + * @param FLASHx FLASH instance + * @retval None + */ +__STATIC_INLINE void FL_FLASH_ClearFlag_EraseComplete(FLASH_Type *FLASHx) +{ + WRITE_REG(FLASHx->ISR, FLASH_ISR_ERD_Msk); +} + +/** + * @} + */ + +/** @defgroup FLASH_FL_EF_Init Initialization and de-initialization functions + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_FL_EF_Operation Opeartion functions + * @{ + */ + +FL_ErrorStatus FL_FLASH_PageErase(FLASH_Type *FLASHx, uint32_t address); +FL_ErrorStatus FL_FLASH_SectorErase(FLASH_Type *FLASHx, uint32_t address); + +FL_ErrorStatus FL_FLASH_Program_Word(FLASH_Type *FLASHx, uint32_t address, uint32_t data); +FL_ErrorStatus FL_FLASH_Program_Page(FLASH_Type *FLASHx, uint32_t pageNum, uint32_t *data); +FL_ErrorStatus FL_FLASH_Program_Sector(FLASH_Type *FLASHx, uint32_t sectorNum, uint32_t *data); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_FLASH_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.14-0.2 @ 2020-12-15*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_gpio.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_gpio.h new file mode 100644 index 0000000000..8943e67da1 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_gpio.h @@ -0,0 +1,1959 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_gpio.h + * @author FMSH Application Team + * @brief Head file of GPIO FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_GPIO_H +#define __FM33LC0XX_FL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_FL_ES_INIT GPIO Exported Init structures + * @{ + */ +/** + * @brief FL GPIO Init Sturcture definition + */ +typedef struct +{ + /*! PIN */ + uint32_t pin; + + /*! 功能模式 */ + uint32_t mode; + + /*! 输出类型 */ + uint32_t outputType; + + /*! 上拉使能 */ + uint32_t pull; + + /*! 数字功能重定向 */ + uint32_t remapPin; + +} FL_GPIO_InitTypeDef; + +/** + * @brief FL GPIO WKUP Init Sturcture definition + */ +typedef struct +{ + /*! 触发边沿 */ + uint32_t polarity; + +} FL_WKUP_InitTypeDef; + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup GPIO_FL_Exported_Constants GPIO Exported Constants + * @{ + */ + +#define GPIO_FCR_Pos (0U) +#define GPIO_FCR_Msk (0x3U << GPIO_FCR_Pos) +#define GPIO_FCR GPIO_FCR_Msk + +#define GPIO_EXTIEDS_Pos (0U) +#define GPIO_EXTIEDS_Msk (0x3U << GPIO_EXTIEDS_Pos) +#define GPIO_EXTIEDS GPIO_EXTIEDS_Msk + +#define GPIO_FOUTSEL_FOUT0_Pos (0U) +#define GPIO_FOUTSEL_FOUT0_Msk (0xfU << GPIO_FOUTSEL_FOUT0_Pos) +#define GPIO_FOUTSEL_FOUT0 GPIO_FOUTSEL_FOUT0_Msk + +#define GPIO_FOUTSEL_FOUT1_Pos (4U) +#define GPIO_FOUTSEL_FOUT1_Msk (0xfU << GPIO_FOUTSEL_FOUT1_Pos) +#define GPIO_FOUTSEL_FOUT1 GPIO_FOUTSEL_FOUT1_Msk + +#define GPIO_EXTISEL_EXTI0_Pos (0U) +#define GPIO_EXTISEL_EXTI0_Msk (0x3U << GPIO_EXTISEL_EXTI0_Pos) +#define GPIO_EXTISEL_EXTI0 GPIO_EXTISEL_EXTI0_Msk + +#define GPIO_EXTISEL_EXTI1_Pos (2U) +#define GPIO_EXTISEL_EXTI1_Msk (0x3U << GPIO_EXTISEL_EXTI1_Pos) +#define GPIO_EXTISEL_EXTI1 GPIO_EXTISEL_EXTI1_Msk + +#define GPIO_EXTISEL_EXTI2_Pos (4U) +#define GPIO_EXTISEL_EXTI2_Msk (0x3U << GPIO_EXTISEL_EXTI2_Pos) +#define GPIO_EXTISEL_EXTI2 GPIO_EXTISEL_EXTI2_Msk + +#define GPIO_EXTISEL_EXTI3_Pos (6U) +#define GPIO_EXTISEL_EXTI3_Msk (0x3U << GPIO_EXTISEL_EXTI3_Pos) +#define GPIO_EXTISEL_EXTI3 GPIO_EXTISEL_EXTI3_Msk + +#define GPIO_EXTISEL_EXTI4_Pos (8U) +#define GPIO_EXTISEL_EXTI4_Msk (0x3U << GPIO_EXTISEL_EXTI4_Pos) +#define GPIO_EXTISEL_EXTI4 GPIO_EXTISEL_EXTI4_Msk + +#define GPIO_EXTISEL_EXTI5_Pos (10U) +#define GPIO_EXTISEL_EXTI5_Msk (0x3U << GPIO_EXTISEL_EXTI5_Pos) +#define GPIO_EXTISEL_EXTI5 GPIO_EXTISEL_EXTI5_Msk + +#define GPIO_EXTISEL_EXTI6_Pos (12U) +#define GPIO_EXTISEL_EXTI6_Msk (0x3U << GPIO_EXTISEL_EXTI6_Pos) +#define GPIO_EXTISEL_EXTI6 GPIO_EXTISEL_EXTI6_Msk + +#define GPIO_EXTISEL_EXTI7_Pos (14U) +#define GPIO_EXTISEL_EXTI7_Msk (0x3U << GPIO_EXTISEL_EXTI7_Pos) +#define GPIO_EXTISEL_EXTI7 GPIO_EXTISEL_EXTI7_Msk + +#define GPIO_EXTISEL_EXTI8_Pos (16U) +#define GPIO_EXTISEL_EXTI8_Msk (0x3U << GPIO_EXTISEL_EXTI8_Pos) +#define GPIO_EXTISEL_EXTI8 GPIO_EXTISEL_EXTI8_Msk + +#define GPIO_EXTISEL_EXTI9_Pos (18U) +#define GPIO_EXTISEL_EXTI9_Msk (0x3U << GPIO_EXTISEL_EXTI9_Pos) +#define GPIO_EXTISEL_EXTI9 GPIO_EXTISEL_EXTI9_Msk + +#define GPIO_EXTISEL_EXTI10_Pos (20U) +#define GPIO_EXTISEL_EXTI10_Msk (0x3U << GPIO_EXTISEL_EXTI10_Pos) +#define GPIO_EXTISEL_EXTI10 GPIO_EXTISEL_EXTI10_Msk + +#define GPIO_EXTISEL_EXTI11_Pos (22U) +#define GPIO_EXTISEL_EXTI11_Msk (0x3U << GPIO_EXTISEL_EXTI11_Pos) +#define GPIO_EXTISEL_EXTI11 GPIO_EXTISEL_EXTI11_Msk + +#define GPIO_EXTISEL_EXTI12_Pos (24U) +#define GPIO_EXTISEL_EXTI12_Msk (0x3U << GPIO_EXTISEL_EXTI12_Pos) +#define GPIO_EXTISEL_EXTI12 GPIO_EXTISEL_EXTI12_Msk + +#define GPIO_EXTISEL_EXTI13_Pos (26U) +#define GPIO_EXTISEL_EXTI13_Msk (0x3U << GPIO_EXTISEL_EXTI13_Pos) +#define GPIO_EXTISEL_EXTI13 GPIO_EXTISEL_EXTI13_Msk + +#define GPIO_EXTISEL_EXTI14_Pos (28U) +#define GPIO_EXTISEL_EXTI14_Msk (0x3U << GPIO_EXTISEL_EXTI14_Pos) +#define GPIO_EXTISEL_EXTI14 GPIO_EXTISEL_EXTI14_Msk + +#define GPIO_PINWKEN_EN_Pos (0U) +#define GPIO_PINWKEN_EN_Msk (0xffU << GPIO_PINWKEN_EN_Pos) +#define GPIO_PINWKEN_EN GPIO_PINWKEN_EN_Msk + +#define GPIO_PINWKEN_WKISEL_Pos (31U) +#define GPIO_PINWKEN_WKISEL_Msk (0x1U << GPIO_PINWKEN_WKISEL_Pos) +#define GPIO_PINWKEN_WKISEL GPIO_PINWKEN_WKISEL_Msk + +#define GPIO_PINWKEN_SEL_Pos (8U) +#define GPIO_PINWKEN_SEL_Msk (0x1U << GPIO_PINWKEN_SEL_Pos) +#define GPIO_PINWKEN_SEL GPIO_PINWKEN_SEL_Msk + + + +#define FL_GPIO_PIN_0 (0x1U << 0U) +#define FL_GPIO_PIN_1 (0x1U << 1U) +#define FL_GPIO_PIN_2 (0x1U << 2U) +#define FL_GPIO_PIN_3 (0x1U << 3U) +#define FL_GPIO_PIN_4 (0x1U << 4U) +#define FL_GPIO_PIN_5 (0x1U << 5U) +#define FL_GPIO_PIN_6 (0x1U << 6U) +#define FL_GPIO_PIN_7 (0x1U << 7U) +#define FL_GPIO_PIN_8 (0x1U << 8U) +#define FL_GPIO_PIN_9 (0x1U << 9U) +#define FL_GPIO_PIN_10 (0x1U << 10U) +#define FL_GPIO_PIN_11 (0x1U << 11U) +#define FL_GPIO_PIN_12 (0x1U << 12U) +#define FL_GPIO_PIN_13 (0x1U << 13U) +#define FL_GPIO_PIN_14 (0x1U << 14U) +#define FL_GPIO_PIN_15 (0x1U << 15U) +#define FL_GPIO_PIN_ALL (0xffffU << 0U) +#define FL_GPIO_PIN_ALL_EXCEPTSWD 0xFE7FU +#define FL_GPIO_EXTI_LINE_0 (0x1U << 0U) +#define FL_GPIO_EXTI_LINE_1 (0x1U << 1U) +#define FL_GPIO_EXTI_LINE_2 (0x1U << 2U) +#define FL_GPIO_EXTI_LINE_3 (0x1U << 3U) +#define FL_GPIO_EXTI_LINE_4 (0x1U << 4U) +#define FL_GPIO_EXTI_LINE_5 (0x1U << 5U) +#define FL_GPIO_EXTI_LINE_6 (0x1U << 6U) +#define FL_GPIO_EXTI_LINE_7 (0x1U << 7U) +#define FL_GPIO_EXTI_LINE_8 (0x1U << 8U) +#define FL_GPIO_EXTI_LINE_9 (0x1U << 9U) +#define FL_GPIO_EXTI_LINE_10 (0x1U << 10U) +#define FL_GPIO_EXTI_LINE_11 (0x1U << 11U) +#define FL_GPIO_EXTI_LINE_12 (0x1U << 12U) +#define FL_GPIO_EXTI_LINE_13 (0x1U << 13U) +#define FL_GPIO_EXTI_LINE_14 (0x1U << 14U) +#define FL_GPIO_EXTI_LINE_15 (0x1U << 15U) +#define FL_GPIO_EXTI_LINE_ALL (0xffffU << 0U) +#define FL_GPIO_EXTI_LINE_0_PA0 (0x0U << 0U) +#define FL_GPIO_EXTI_LINE_0_PA1 (0x1U << 0U) +#define FL_GPIO_EXTI_LINE_0_PA2 (0x2U << 0U) +#define FL_GPIO_EXTI_LINE_0_PA3 (0x3U << 0U) +#define FL_GPIO_EXTI_LINE_1_PA4 (0x0U << 2U) +#define FL_GPIO_EXTI_LINE_1_PA5 (0x1U << 2U) +#define FL_GPIO_EXTI_LINE_1_PA6 (0x2U << 2U) +#define FL_GPIO_EXTI_LINE_1_PA7 (0x3U << 2U) +#define FL_GPIO_EXTI_LINE_2_PA8 (0x0U << 4U) +#define FL_GPIO_EXTI_LINE_2_PA9 (0x1U << 4U) +#define FL_GPIO_EXTI_LINE_2_PA10 (0x2U << 4U) +#define FL_GPIO_EXTI_LINE_2_PA11 (0x3U << 4U) +#define FL_GPIO_EXTI_LINE_3_PA12 (0x0U << 6U) +#define FL_GPIO_EXTI_LINE_3_PA13 (0x1U << 6U) +#define FL_GPIO_EXTI_LINE_3_PA14 (0x2U << 6U) +#define FL_GPIO_EXTI_LINE_3_PA15 (0x3U << 6U) +#define FL_GPIO_EXTI_LINE_4_PB0 (0x0U << 8U) +#define FL_GPIO_EXTI_LINE_4_PB1 (0x1U << 8U) +#define FL_GPIO_EXTI_LINE_4_PB2 (0x2U << 8U) +#define FL_GPIO_EXTI_LINE_4_PB3 (0x3U << 8U) +#define FL_GPIO_EXTI_LINE_5_PB4 (0x0U << 10U) +#define FL_GPIO_EXTI_LINE_5_PB5 (0x1U << 10U) +#define FL_GPIO_EXTI_LINE_5_PB6 (0x2U << 10U) +#define FL_GPIO_EXTI_LINE_5_PB7 (0x3U << 10U) +#define FL_GPIO_EXTI_LINE_6_PB8 (0x0U << 12U) +#define FL_GPIO_EXTI_LINE_6_PB9 (0x1U << 12U) +#define FL_GPIO_EXTI_LINE_6_PB10 (0x2U << 12U) +#define FL_GPIO_EXTI_LINE_6_PB11 (0x3U << 12U) +#define FL_GPIO_EXTI_LINE_7_PB12 (0x0U << 14U) +#define FL_GPIO_EXTI_LINE_7_PB13 (0x1U << 14U) +#define FL_GPIO_EXTI_LINE_7_PB14 (0x2U << 14U) +#define FL_GPIO_EXTI_LINE_7_PB15 (0x3U << 14U) +#define FL_GPIO_EXTI_LINE_8_PC0 (0x0U << 16U) +#define FL_GPIO_EXTI_LINE_8_PC1 (0x1U << 16U) +#define FL_GPIO_EXTI_LINE_8_PC2 (0x2U << 16U) +#define FL_GPIO_EXTI_LINE_8_PC3 (0x3U << 16U) +#define FL_GPIO_EXTI_LINE_9_PC4 (0x0U << 18U) +#define FL_GPIO_EXTI_LINE_9_PC5 (0x1U << 18U) +#define FL_GPIO_EXTI_LINE_9_PC6 (0x2U << 18U) +#define FL_GPIO_EXTI_LINE_9_PC7 (0x3U << 18U) +#define FL_GPIO_EXTI_LINE_10_PC8 (0x0U << 20U) +#define FL_GPIO_EXTI_LINE_10_PC9 (0x1U << 20U) +#define FL_GPIO_EXTI_LINE_10_PC10 (0x2U << 20U) +#define FL_GPIO_EXTI_LINE_10_PC11 (0x3U << 20U) +#define FL_GPIO_EXTI_LINE_12_PD0 (0x0U << 24U) +#define FL_GPIO_EXTI_LINE_12_PD1 (0x1U << 24U) +#define FL_GPIO_EXTI_LINE_12_PD2 (0x2U << 24U) +#define FL_GPIO_EXTI_LINE_12_PD3 (0x3U << 24U) +#define FL_GPIO_EXTI_LINE_13_PD4 (0x0U << 26U) +#define FL_GPIO_EXTI_LINE_13_PD5 (0x1U << 26U) +#define FL_GPIO_EXTI_LINE_13_PD6 (0x2U << 26U) +#define FL_GPIO_EXTI_LINE_13_PD7 (0x3U << 26U) +#define FL_GPIO_EXTI_LINE_14_PD8 (0x0U << 28U) +#define FL_GPIO_EXTI_LINE_14_PD9 (0x1U << 28U) +#define FL_GPIO_EXTI_LINE_14_PD10 (0x2U << 28U) +#define FL_GPIO_EXTI_LINE_14_PD11 (0x3U << 28U) +#define FL_GPIO_WAKEUP_0 (0x1U << 0U) +#define FL_GPIO_WAKEUP_1 (0x1U << 1U) +#define FL_GPIO_WAKEUP_2 (0x1U << 2U) +#define FL_GPIO_WAKEUP_3 (0x1U << 3U) +#define FL_GPIO_WAKEUP_4 (0x1U << 4U) +#define FL_GPIO_WAKEUP_5 (0x1U << 5U) +#define FL_GPIO_WAKEUP_6 (0x1U << 6U) +#define FL_GPIO_WAKEUP_7 (0x1U << 7U) +#define FL_GPIO_OUTPUT_PUSHPULL 0x0U +#define FL_GPIO_OUTPUT_OPENDRAIN 0x1U + + + +#define FL_GPIO_MODE_INPUT (0x0U << GPIO_FCR_Pos) +#define FL_GPIO_MODE_OUTPUT (0x1U << GPIO_FCR_Pos) +#define FL_GPIO_MODE_DIGITAL (0x2U << GPIO_FCR_Pos) +#define FL_GPIO_MODE_ANALOG (0x3U << GPIO_FCR_Pos) + + +#define FL_GPIO_EXTI_TRIGGER_EDGE_RISING (0x0U << GPIO_EXTIEDS_Pos) +#define FL_GPIO_EXTI_TRIGGER_EDGE_FALLING (0x1U << GPIO_EXTIEDS_Pos) +#define FL_GPIO_EXTI_TRIGGER_EDGE_BOTH (0x2U << GPIO_EXTIEDS_Pos) +#define FL_GPIO_EXTI_TRIGGER_EDGE_DISABLE (0x3U << GPIO_EXTIEDS_Pos) + + +#define FL_GPIO_FOUT0_SELECT_XTLF (0x0U << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_RCLP (0x1U << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_RCHF_DIV64 (0x2U << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_LSCLK (0x3U << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_AHBCLK_DIV64 (0x4U << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_RTCTM (0x5U << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_PLLOUTPUT_DIV64 (0x6U << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_RTCCLK64Hz (0x7U << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_APBCLK_DIV64 (0x8U << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_PLLOUTPUT (0x9U << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_RC4M_PSC (0xaU << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_RCHF (0xbU << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_XTHF_DIV64 (0xcU << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_ADCCLK_DIV64 (0xdU << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_CLK_8K (0xeU << GPIO_FOUTSEL_FOUT0_Pos) +#define FL_GPIO_FOUT0_SELECT_ADC_CLK (0xfU << GPIO_FOUTSEL_FOUT0_Pos) + + +#define FL_GPIO_FOUT1_SELECT_XTLF (0x0U << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_RCLP (0x1U << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_RCHF_DIV64 (0x2U << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_LSCLK (0x3U << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_AHBCLK_DIV64 (0x4U << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_RTCTM (0x5U << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_PLLOUTPUT_DIV64 (0x6U << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_RTCCLK64Hz (0x7U << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_APBCLK_DIV64 (0x8U << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_PLLOUTPUT (0x9U << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_RC4M_PSC (0xaU << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_RCHF (0xbU << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_XTHF_DIV64 (0xcU << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_COMP1_OUTPUT (0xdU << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_CLK_8K (0xeU << GPIO_FOUTSEL_FOUT1_Pos) +#define FL_GPIO_FOUT1_SELECT_COMP2_OUTPUT (0xfU << GPIO_FOUTSEL_FOUT1_Pos) + + +#define FL_GPIO_WAKEUP_INT_ENTRY_NMI (0x0U << GPIO_PINWKEN_WKISEL_Pos) +#define FL_GPIO_WAKEUP_INT_ENTRY_38 (0x1U << GPIO_PINWKEN_WKISEL_Pos) + + +#define FL_GPIO_WAKEUP_TRIGGER_RISING (0x1U << GPIO_PINWKEN_SEL_Pos) +#define FL_GPIO_WAKEUP_TRIGGER_FALLING (0x0U << GPIO_PINWKEN_SEL_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup GPIO_FL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** + * @brief GPIOx input enable + * @rmtoll INEN FL_GPIO_EnablePinInput + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @arg @ref FL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_EnablePinInput(GPIO_Type *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->INEN, ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief CPIOx input disable + * @rmtoll INEN FL_GPIO_DisablePinInput + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @arg @ref FL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_DisablePinInput(GPIO_Type *GPIOx, uint32_t pin) +{ + CLEAR_BIT(GPIOx->INEN, ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief Get GPIOx input enable status + * @rmtoll INEN FL_GPIO_IsEnabledPinInput + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPIO_IsEnabledPinInput(GPIO_Type *GPIOx, uint32_t pin) +{ + return (uint32_t)(READ_BIT(GPIOx->INEN, ((pin & 0xffff) << 0x0U)) == ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief GPIOx Pull-Up enable + * @rmtoll PUEN FL_GPIO_EnablePinPullup + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @arg @ref FL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_EnablePinPullup(GPIO_Type *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->PUEN, ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief GPIOx Pull-Up disable + * @rmtoll PUEN FL_GPIO_DisablePinPullup + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @arg @ref FL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_DisablePinPullup(GPIO_Type *GPIOx, uint32_t pin) +{ + CLEAR_BIT(GPIOx->PUEN, ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief Get GPIOx Pull-Up enable status + * @rmtoll PUEN FL_GPIO_IsEnabledPinPullup + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPIO_IsEnabledPinPullup(GPIO_Type *GPIOx, uint32_t pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUEN, ((pin & 0xffff) << 0x0U)) == ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief GPIOx Open-Drain enable + * @rmtoll ODEN FL_GPIO_EnablePinOpenDrain + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @arg @ref FL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_EnablePinOpenDrain(GPIO_Type *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->ODEN, ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief Open-Drain disable + * @rmtoll ODEN FL_GPIO_DisablePinOpenDrain + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @arg @ref FL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_DisablePinOpenDrain(GPIO_Type *GPIOx, uint32_t pin) +{ + CLEAR_BIT(GPIOx->ODEN, ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief Get Open-Drain enable status + * @rmtoll ODEN FL_GPIO_IsEnabledPinOpenDrain + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPIO_IsEnabledPinOpenDrain(GPIO_Type *GPIOx, uint32_t pin) +{ + return (uint32_t)(READ_BIT(GPIOx->ODEN, ((pin & 0xffff) << 0x0U)) == ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief GPIOx digital function enable + * @rmtoll DFS FL_GPIO_EnablePinRemap + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @arg @ref FL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_EnablePinRemap(GPIO_Type *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->DFS, ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief GPIOx digital function disable + * @rmtoll DFS FL_GPIO_DisablePinRemap + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @arg @ref FL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_DisablePinRemap(GPIO_Type *GPIOx, uint32_t pin) +{ + CLEAR_BIT(GPIOx->DFS, ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief Get GPIOx digital function enable status + * @rmtoll DFS FL_GPIO_IsEnabledPinRemap + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPIO_IsEnabledPinRemap(GPIO_Type *GPIOx, uint32_t pin) +{ + return (uint32_t)(READ_BIT(GPIOx->DFS, ((pin & 0xffff) << 0x0U)) == ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief GPIOx analog channel enable + * @rmtoll ANEN FL_GPIO_EnablePinAnalogSwitch + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @arg @ref FL_GPIO_PIN_ALL + * @arg @ref FL_GPIO_EXTI_LINE_0 + * @arg @ref FL_GPIO_EXTI_LINE_1 + * @arg @ref FL_GPIO_EXTI_LINE_2 + * @arg @ref FL_GPIO_EXTI_LINE_3 + * @arg @ref FL_GPIO_EXTI_LINE_4 + * @arg @ref FL_GPIO_EXTI_LINE_7 + * @arg @ref FL_GPIO_EXTI_LINE_8 + * @arg @ref FL_GPIO_EXTI_LINE_9 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_EnablePinAnalogSwitch(GPIO_Type *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->ANEN, ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief GPIOx analog channel disable + * @rmtoll ANEN FL_GPIO_DisablePinAnalogSwitch + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @arg @ref FL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_DisablePinAnalogSwitch(GPIO_Type *GPIOx, uint32_t pin) +{ + CLEAR_BIT(GPIOx->ANEN, ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief Get GPIOx analog channel enable status + * @rmtoll ANEN FL_GPIO_IsEnabledPinAnalogSwitch + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @arg @ref FL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPIO_IsEnabledPinAnalogSwitch(GPIO_Type *GPIOx, uint32_t pin) +{ + return (uint32_t)(READ_BIT(GPIOx->ANEN, ((pin & 0xffff) << 0x0U)) == ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief Set Portx mode + * @rmtoll FCR FL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @param mode This parameter can be one of the following values: + * @arg @ref FL_GPIO_MODE_INPUT + * @arg @ref FL_GPIO_MODE_OUTPUT + * @arg @ref FL_GPIO_MODE_DIGITAL + * @arg @ref FL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetPinMode(GPIO_Type *GPIOx, uint32_t pin, uint32_t mode) +{ + MODIFY_REG(GPIOx->FCR, ((pin * pin) * GPIO_FCR), ((pin * pin) * mode)); +} + +/** + * @brief Get Portx mode + * @rmtoll FCR FL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPIO_MODE_INPUT + * @arg @ref FL_GPIO_MODE_OUTPUT + * @arg @ref FL_GPIO_MODE_DIGITAL + * @arg @ref FL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t FL_GPIO_GetPinMode(GPIO_Type *GPIOx, uint32_t pin) +{ + return (uint32_t)(READ_BIT(GPIOx->FCR, ((pin * pin) * GPIO_FCR)) / (pin * pin)); +} + +/** + * @brief Set GPIO output data + * @rmtoll DO FL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param output Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void FL_GPIO_WriteOutputPort(GPIO_Type *GPIOx, uint32_t output) +{ + MODIFY_REG(GPIOx->DO, (0xffffU << 0U), (output << 0U)); +} + +/** + * @brief Get GPIO output data + * @rmtoll DO FL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t FL_GPIO_ReadOutputPort(GPIO_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->DO, 0xffffU) >> 0U); +} + +/** + * @brief Get GPIO output pin status + * @rmtoll DO FL_GPIO_GetOutputPin + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPIO_GetOutputPin(GPIO_Type *GPIOx, uint32_t pin) +{ + return (uint32_t)(READ_BIT(GPIOx->DO, ((pin & 0xffff) << 0x0U)) == ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief Toggle output pin + * @rmtoll DO FL_GPIO_ToggleOutputPin + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @arg @ref FL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_ToggleOutputPin(GPIO_Type *GPIOx, uint32_t pin) +{ + WRITE_REG(GPIOx->DO, READ_REG(GPIOx->DO) ^ pin); +} + +/** + * @brief Get input data + * @rmtoll DIN FL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t FL_GPIO_ReadInputPort(GPIO_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->DIN, 0xffffU) >> 0U); +} + +/** + * @brief Get GPIO input set status + * @rmtoll DIN FL_GPIO_GetInputPin + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPIO_GetInputPin(GPIO_Type *GPIOx, uint32_t pin) +{ + return (uint32_t)(READ_BIT(GPIOx->DIN, ((pin & 0xffff) << 0x0U)) == ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief Set pin output 1 + * @rmtoll DSET FL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @arg @ref FL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetOutputPin(GPIO_Type *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->DSET, ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief Set pin output 0 + * @rmtoll DRST FL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param pin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @arg @ref FL_GPIO_PIN_1 + * @arg @ref FL_GPIO_PIN_2 + * @arg @ref FL_GPIO_PIN_3 + * @arg @ref FL_GPIO_PIN_4 + * @arg @ref FL_GPIO_PIN_5 + * @arg @ref FL_GPIO_PIN_6 + * @arg @ref FL_GPIO_PIN_7 + * @arg @ref FL_GPIO_PIN_8 + * @arg @ref FL_GPIO_PIN_9 + * @arg @ref FL_GPIO_PIN_10 + * @arg @ref FL_GPIO_PIN_11 + * @arg @ref FL_GPIO_PIN_12 + * @arg @ref FL_GPIO_PIN_13 + * @arg @ref FL_GPIO_PIN_14 + * @arg @ref FL_GPIO_PIN_15 + * @arg @ref FL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_ResetOutputPin(GPIO_Type *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->DRST, ((pin & 0xffff) << 0x0U)); +} + +/** + * @brief EXTI edge select + * @rmtoll EXTIEDS FL_GPIO_SetTriggerEdge + * @param GPIOx GPIO Port + * @param line This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_0 + * @arg @ref FL_GPIO_EXTI_LINE_1 + * @arg @ref FL_GPIO_EXTI_LINE_2 + * @arg @ref FL_GPIO_EXTI_LINE_3 + * @arg @ref FL_GPIO_EXTI_LINE_4 + * @arg @ref FL_GPIO_EXTI_LINE_5 + * @arg @ref FL_GPIO_EXTI_LINE_6 + * @arg @ref FL_GPIO_EXTI_LINE_7 + * @arg @ref FL_GPIO_EXTI_LINE_8 + * @arg @ref FL_GPIO_EXTI_LINE_9 + * @arg @ref FL_GPIO_EXTI_LINE_10 + * @arg @ref FL_GPIO_EXTI_LINE_11 + * @arg @ref FL_GPIO_EXTI_LINE_12 + * @arg @ref FL_GPIO_EXTI_LINE_13 + * @arg @ref FL_GPIO_EXTI_LINE_14 + * @arg @ref FL_GPIO_EXTI_LINE_15 + * @param edge This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_TRIGGER_EDGE_RISING + * @arg @ref FL_GPIO_EXTI_TRIGGER_EDGE_FALLING + * @arg @ref FL_GPIO_EXTI_TRIGGER_EDGE_BOTH + * @arg @ref FL_GPIO_EXTI_TRIGGER_EDGE_DISABLE + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetTriggerEdge(GPIO_COMMON_Type *GPIOx, uint32_t line, uint32_t edge) +{ + MODIFY_REG(GPIOx->EXTIEDS, ((line * line) * GPIO_EXTIEDS), ((line * line) * edge)); +} + +/** + * @brief Get EXTI edge select + * @rmtoll EXTIEDS FL_GPIO_GetTriggerEdge + * @param GPIOx GPIO Port + * @param line This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_0 + * @arg @ref FL_GPIO_EXTI_LINE_1 + * @arg @ref FL_GPIO_EXTI_LINE_2 + * @arg @ref FL_GPIO_EXTI_LINE_3 + * @arg @ref FL_GPIO_EXTI_LINE_4 + * @arg @ref FL_GPIO_EXTI_LINE_5 + * @arg @ref FL_GPIO_EXTI_LINE_6 + * @arg @ref FL_GPIO_EXTI_LINE_7 + * @arg @ref FL_GPIO_EXTI_LINE_8 + * @arg @ref FL_GPIO_EXTI_LINE_9 + * @arg @ref FL_GPIO_EXTI_LINE_10 + * @arg @ref FL_GPIO_EXTI_LINE_11 + * @arg @ref FL_GPIO_EXTI_LINE_12 + * @arg @ref FL_GPIO_EXTI_LINE_13 + * @arg @ref FL_GPIO_EXTI_LINE_14 + * @arg @ref FL_GPIO_EXTI_LINE_15 + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPIO_EXTI_TRIGGER_EDGE_RISING + * @arg @ref FL_GPIO_EXTI_TRIGGER_EDGE_FALLING + * @arg @ref FL_GPIO_EXTI_TRIGGER_EDGE_BOTH + * @arg @ref FL_GPIO_EXTI_TRIGGER_EDGE_DISABLE + */ +__STATIC_INLINE uint32_t FL_GPIO_GetTriggerEdge(GPIO_COMMON_Type *GPIOx, uint32_t line) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTIEDS, ((line * line) * GPIO_EXTIEDS)) / (line * line)); +} + +/** + * @brief EXTI digital filter enable + * @rmtoll EXTIDF FL_GPIO_EnableDigitalFilter + * @param GPIOx GPIO Port + * @param line This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_0 + * @arg @ref FL_GPIO_EXTI_LINE_1 + * @arg @ref FL_GPIO_EXTI_LINE_2 + * @arg @ref FL_GPIO_EXTI_LINE_3 + * @arg @ref FL_GPIO_EXTI_LINE_4 + * @arg @ref FL_GPIO_EXTI_LINE_5 + * @arg @ref FL_GPIO_EXTI_LINE_6 + * @arg @ref FL_GPIO_EXTI_LINE_7 + * @arg @ref FL_GPIO_EXTI_LINE_8 + * @arg @ref FL_GPIO_EXTI_LINE_9 + * @arg @ref FL_GPIO_EXTI_LINE_10 + * @arg @ref FL_GPIO_EXTI_LINE_11 + * @arg @ref FL_GPIO_EXTI_LINE_12 + * @arg @ref FL_GPIO_EXTI_LINE_13 + * @arg @ref FL_GPIO_EXTI_LINE_14 + * @arg @ref FL_GPIO_EXTI_LINE_15 + * @arg @ref FL_GPIO_EXTI_LINE_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_EnableDigitalFilter(GPIO_COMMON_Type *GPIOx, uint32_t line) +{ + SET_BIT(GPIOx->EXTIDF, ((line & 0xffff) << 0x0U)); +} + +/** + * @brief EXTI digital filter disable + * @rmtoll EXTIDF FL_GPIO_DisableDigitalFilter + * @param GPIOx GPIO Port + * @param line This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_0 + * @arg @ref FL_GPIO_EXTI_LINE_1 + * @arg @ref FL_GPIO_EXTI_LINE_2 + * @arg @ref FL_GPIO_EXTI_LINE_3 + * @arg @ref FL_GPIO_EXTI_LINE_4 + * @arg @ref FL_GPIO_EXTI_LINE_5 + * @arg @ref FL_GPIO_EXTI_LINE_6 + * @arg @ref FL_GPIO_EXTI_LINE_7 + * @arg @ref FL_GPIO_EXTI_LINE_8 + * @arg @ref FL_GPIO_EXTI_LINE_9 + * @arg @ref FL_GPIO_EXTI_LINE_10 + * @arg @ref FL_GPIO_EXTI_LINE_11 + * @arg @ref FL_GPIO_EXTI_LINE_12 + * @arg @ref FL_GPIO_EXTI_LINE_13 + * @arg @ref FL_GPIO_EXTI_LINE_14 + * @arg @ref FL_GPIO_EXTI_LINE_15 + * @arg @ref FL_GPIO_EXTI_LINE_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_DisableDigitalFilter(GPIO_COMMON_Type *GPIOx, uint32_t line) +{ + CLEAR_BIT(GPIOx->EXTIDF, ((line & 0xffff) << 0x0U)); +} + +/** + * @brief Get EXTI digital filter enable status + * @rmtoll EXTIDF FL_GPIO_IsEnabledDigitalFilter + * @param GPIOx GPIO Port + * @param line This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_0 + * @arg @ref FL_GPIO_EXTI_LINE_1 + * @arg @ref FL_GPIO_EXTI_LINE_2 + * @arg @ref FL_GPIO_EXTI_LINE_3 + * @arg @ref FL_GPIO_EXTI_LINE_4 + * @arg @ref FL_GPIO_EXTI_LINE_5 + * @arg @ref FL_GPIO_EXTI_LINE_6 + * @arg @ref FL_GPIO_EXTI_LINE_7 + * @arg @ref FL_GPIO_EXTI_LINE_8 + * @arg @ref FL_GPIO_EXTI_LINE_9 + * @arg @ref FL_GPIO_EXTI_LINE_10 + * @arg @ref FL_GPIO_EXTI_LINE_11 + * @arg @ref FL_GPIO_EXTI_LINE_12 + * @arg @ref FL_GPIO_EXTI_LINE_13 + * @arg @ref FL_GPIO_EXTI_LINE_14 + * @arg @ref FL_GPIO_EXTI_LINE_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPIO_IsEnabledDigitalFilter(GPIO_COMMON_Type *GPIOx, uint32_t line) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTIDF, ((line & 0xffff) << 0x0U)) == ((line & 0xffff) << 0x0U)); +} + +/** + * @brief Get external interrupt flag status + * @rmtoll EXTIISR FL_GPIO_IsActiveFlag_EXTI + * @param GPIOx GPIO Port + * @param line This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_0 + * @arg @ref FL_GPIO_EXTI_LINE_1 + * @arg @ref FL_GPIO_EXTI_LINE_2 + * @arg @ref FL_GPIO_EXTI_LINE_3 + * @arg @ref FL_GPIO_EXTI_LINE_4 + * @arg @ref FL_GPIO_EXTI_LINE_5 + * @arg @ref FL_GPIO_EXTI_LINE_6 + * @arg @ref FL_GPIO_EXTI_LINE_7 + * @arg @ref FL_GPIO_EXTI_LINE_8 + * @arg @ref FL_GPIO_EXTI_LINE_9 + * @arg @ref FL_GPIO_EXTI_LINE_10 + * @arg @ref FL_GPIO_EXTI_LINE_11 + * @arg @ref FL_GPIO_EXTI_LINE_12 + * @arg @ref FL_GPIO_EXTI_LINE_13 + * @arg @ref FL_GPIO_EXTI_LINE_14 + * @arg @ref FL_GPIO_EXTI_LINE_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPIO_IsActiveFlag_EXTI(GPIO_COMMON_Type *GPIOx, uint32_t line) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTIISR, ((line & 0xffff) << 0x0U)) == ((line & 0xffff) << 0x0U)); +} + +/** + * @brief Clear external interrupt flag + * @rmtoll EXTIISR FL_GPIO_ClearFlag_EXTI + * @param GPIOx GPIO Port + * @param line This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_0 + * @arg @ref FL_GPIO_EXTI_LINE_1 + * @arg @ref FL_GPIO_EXTI_LINE_2 + * @arg @ref FL_GPIO_EXTI_LINE_3 + * @arg @ref FL_GPIO_EXTI_LINE_4 + * @arg @ref FL_GPIO_EXTI_LINE_5 + * @arg @ref FL_GPIO_EXTI_LINE_6 + * @arg @ref FL_GPIO_EXTI_LINE_7 + * @arg @ref FL_GPIO_EXTI_LINE_8 + * @arg @ref FL_GPIO_EXTI_LINE_9 + * @arg @ref FL_GPIO_EXTI_LINE_10 + * @arg @ref FL_GPIO_EXTI_LINE_11 + * @arg @ref FL_GPIO_EXTI_LINE_12 + * @arg @ref FL_GPIO_EXTI_LINE_13 + * @arg @ref FL_GPIO_EXTI_LINE_14 + * @arg @ref FL_GPIO_EXTI_LINE_15 + * @arg @ref FL_GPIO_EXTI_LINE_ALL + * @retval None + */ +__STATIC_INLINE void FL_GPIO_ClearFlag_EXTI(GPIO_COMMON_Type *GPIOx, uint32_t line) +{ + WRITE_REG(GPIOx->EXTIISR, ((line & 0xffff) << 0x0U)); +} + +/** + * @brief Get EXTI input set status + * @rmtoll EXTIDI FL_GPIO_GetEXTILine + * @param GPIOx GPIO Port + * @param line This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_0 + * @arg @ref FL_GPIO_EXTI_LINE_1 + * @arg @ref FL_GPIO_EXTI_LINE_2 + * @arg @ref FL_GPIO_EXTI_LINE_3 + * @arg @ref FL_GPIO_EXTI_LINE_4 + * @arg @ref FL_GPIO_EXTI_LINE_5 + * @arg @ref FL_GPIO_EXTI_LINE_6 + * @arg @ref FL_GPIO_EXTI_LINE_7 + * @arg @ref FL_GPIO_EXTI_LINE_8 + * @arg @ref FL_GPIO_EXTI_LINE_9 + * @arg @ref FL_GPIO_EXTI_LINE_10 + * @arg @ref FL_GPIO_EXTI_LINE_11 + * @arg @ref FL_GPIO_EXTI_LINE_12 + * @arg @ref FL_GPIO_EXTI_LINE_13 + * @arg @ref FL_GPIO_EXTI_LINE_14 + * @arg @ref FL_GPIO_EXTI_LINE_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPIO_GetEXTILine(GPIO_COMMON_Type *GPIOx, uint32_t line) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTIDI, ((line & 0xffff) << 0x0U)) == ((line & 0xffff) << 0x0U)); +} + +/** + * @brief Get EXTI input status + * @rmtoll EXTIDI FL_GPIO_ReadEXTILines + * @param GPIOx GPIO Port + * @retval EXTI data register value of port + */ +__STATIC_INLINE uint32_t FL_GPIO_ReadEXTILines(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTIDI, 0xffffU) >> 0U); +} + +/** + * @brief Set PD11 frequency output + * @rmtoll FOUTSEL FOUT0 FL_GPIO_SetFOUT0 + * @param GPIOx GPIO Port + * @param select This parameter can be one of the following values: + * @arg @ref FL_GPIO_FOUT0_SELECT_XTLF + * @arg @ref FL_GPIO_FOUT0_SELECT_RCLP + * @arg @ref FL_GPIO_FOUT0_SELECT_RCHF_DIV64 + * @arg @ref FL_GPIO_FOUT0_SELECT_LSCLK + * @arg @ref FL_GPIO_FOUT0_SELECT_AHBCLK_DIV64 + * @arg @ref FL_GPIO_FOUT0_SELECT_RTCTM + * @arg @ref FL_GPIO_FOUT0_SELECT_PLLOUTPUT_DIV64 + * @arg @ref FL_GPIO_FOUT0_SELECT_RTCCLK64Hz + * @arg @ref FL_GPIO_FOUT0_SELECT_APBCLK_DIV64 + * @arg @ref FL_GPIO_FOUT0_SELECT_PLLOUTPUT + * @arg @ref FL_GPIO_FOUT0_SELECT_RC4M_PSC + * @arg @ref FL_GPIO_FOUT0_SELECT_RCHF + * @arg @ref FL_GPIO_FOUT0_SELECT_XTHF_DIV64 + * @arg @ref FL_GPIO_FOUT0_SELECT_ADCCLK_DIV64 + * @arg @ref FL_GPIO_FOUT0_SELECT_CLK_8K + * @arg @ref FL_GPIO_FOUT0_SELECT_ADC_CLK + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetFOUT0(GPIO_COMMON_Type *GPIOx, uint32_t select) +{ + MODIFY_REG(GPIOx->FOUTSEL, GPIO_FOUTSEL_FOUT0_Msk, select); +} + +/** + * @brief Get PD11 frequency output + * @rmtoll FOUTSEL FOUT0 FL_GPIO_GetFOUT0 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPIO_FOUT0_SELECT_XTLF + * @arg @ref FL_GPIO_FOUT0_SELECT_RCLP + * @arg @ref FL_GPIO_FOUT0_SELECT_RCHF_DIV64 + * @arg @ref FL_GPIO_FOUT0_SELECT_LSCLK + * @arg @ref FL_GPIO_FOUT0_SELECT_AHBCLK_DIV64 + * @arg @ref FL_GPIO_FOUT0_SELECT_RTCTM + * @arg @ref FL_GPIO_FOUT0_SELECT_PLLOUTPUT_DIV64 + * @arg @ref FL_GPIO_FOUT0_SELECT_RTCCLK64Hz + * @arg @ref FL_GPIO_FOUT0_SELECT_APBCLK_DIV64 + * @arg @ref FL_GPIO_FOUT0_SELECT_PLLOUTPUT + * @arg @ref FL_GPIO_FOUT0_SELECT_RC4M_PSC + * @arg @ref FL_GPIO_FOUT0_SELECT_RCHF + * @arg @ref FL_GPIO_FOUT0_SELECT_XTHF_DIV64 + * @arg @ref FL_GPIO_FOUT0_SELECT_ADCCLK_DIV64 + * @arg @ref FL_GPIO_FOUT0_SELECT_CLK_8K + * @arg @ref FL_GPIO_FOUT0_SELECT_ADC_CLK + */ +__STATIC_INLINE uint32_t FL_GPIO_GetFOUT0(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->FOUTSEL, GPIO_FOUTSEL_FOUT0_Msk)); +} + +/** + * @brief Set PB12 frequency output + * @rmtoll FOUTSEL FOUT1 FL_GPIO_SetFOUT1 + * @param GPIOx GPIO Port + * @param select This parameter can be one of the following values: + * @arg @ref FL_GPIO_FOUT1_SELECT_XTLF + * @arg @ref FL_GPIO_FOUT1_SELECT_RCLP + * @arg @ref FL_GPIO_FOUT1_SELECT_RCHF_DIV64 + * @arg @ref FL_GPIO_FOUT1_SELECT_LSCLK + * @arg @ref FL_GPIO_FOUT1_SELECT_AHBCLK_DIV64 + * @arg @ref FL_GPIO_FOUT1_SELECT_RTCTM + * @arg @ref FL_GPIO_FOUT1_SELECT_PLLOUTPUT_DIV64 + * @arg @ref FL_GPIO_FOUT1_SELECT_RTCCLK64Hz + * @arg @ref FL_GPIO_FOUT1_SELECT_APBCLK_DIV64 + * @arg @ref FL_GPIO_FOUT1_SELECT_PLLOUTPUT + * @arg @ref FL_GPIO_FOUT1_SELECT_RC4M_PSC + * @arg @ref FL_GPIO_FOUT1_SELECT_RCHF + * @arg @ref FL_GPIO_FOUT1_SELECT_XTHF_DIV64 + * @arg @ref FL_GPIO_FOUT1_SELECT_COMP1_OUTPUT + * @arg @ref FL_GPIO_FOUT1_SELECT_CLK_8K + * @arg @ref FL_GPIO_FOUT1_SELECT_COMP2_OUTPUT + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetFOUT1(GPIO_COMMON_Type *GPIOx, uint32_t select) +{ + MODIFY_REG(GPIOx->FOUTSEL, GPIO_FOUTSEL_FOUT1_Msk, select); +} + +/** + * @brief Get PB12 frequency output + * @rmtoll FOUTSEL FOUT1 FL_GPIO_GetFOUT1 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPIO_FOUT1_SELECT_XTLF + * @arg @ref FL_GPIO_FOUT1_SELECT_RCLP + * @arg @ref FL_GPIO_FOUT1_SELECT_RCHF_DIV64 + * @arg @ref FL_GPIO_FOUT1_SELECT_LSCLK + * @arg @ref FL_GPIO_FOUT1_SELECT_AHBCLK_DIV64 + * @arg @ref FL_GPIO_FOUT1_SELECT_RTCTM + * @arg @ref FL_GPIO_FOUT1_SELECT_PLLOUTPUT_DIV64 + * @arg @ref FL_GPIO_FOUT1_SELECT_RTCCLK64Hz + * @arg @ref FL_GPIO_FOUT1_SELECT_APBCLK_DIV64 + * @arg @ref FL_GPIO_FOUT1_SELECT_PLLOUTPUT + * @arg @ref FL_GPIO_FOUT1_SELECT_RC4M_PSC + * @arg @ref FL_GPIO_FOUT1_SELECT_RCHF + * @arg @ref FL_GPIO_FOUT1_SELECT_XTHF_DIV64 + * @arg @ref FL_GPIO_FOUT1_SELECT_COMP1_OUTPUT + * @arg @ref FL_GPIO_FOUT1_SELECT_CLK_8K + * @arg @ref FL_GPIO_FOUT1_SELECT_COMP2_OUTPUT + */ +__STATIC_INLINE uint32_t FL_GPIO_GetFOUT1(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->FOUTSEL, GPIO_FOUTSEL_FOUT1_Msk)); +} + +/** + * @brief Set EXTI0 interrupt input + * @rmtoll EXTISEL EXTI0 FL_GPIO_SetExtiLine0 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_0_PA0 + * @arg @ref FL_GPIO_EXTI_LINE_0_PA1 + * @arg @ref FL_GPIO_EXTI_LINE_0_PA2 + * @arg @ref FL_GPIO_EXTI_LINE_0_PA3 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine0(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI0_Msk, EXTIPin); +} + +/** + * @brief Get EXTI0 interrupt input + * @rmtoll EXTISEL EXTI0 FL_GPIO_GetExtiLine0 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine0(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI0_Msk)); +} + +/** + * @brief Set EXTI1 interrupt input + * @rmtoll EXTISEL EXTI1 FL_GPIO_SetExtiLine1 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_1_PA4 + * @arg @ref FL_GPIO_EXTI_LINE_1_PA5 + * @arg @ref FL_GPIO_EXTI_LINE_1_PA6 + * @arg @ref FL_GPIO_EXTI_LINE_1_PA7 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine1(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI1_Msk, EXTIPin); +} + +/** + * @brief Get EXTI1 interrupt input + * @rmtoll EXTISEL EXTI1 FL_GPIO_GetExtiLine1 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine1(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI1_Msk)); +} + +/** + * @brief Set EXTI2 interrupt input + * @rmtoll EXTISEL EXTI2 FL_GPIO_SetExtiLine2 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_2_PA8 + * @arg @ref FL_GPIO_EXTI_LINE_2_PA9 + * @arg @ref FL_GPIO_EXTI_LINE_2_PA10 + * @arg @ref FL_GPIO_EXTI_LINE_2_PA11 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine2(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI2_Msk, EXTIPin); +} + +/** + * @brief Get EXTI2 interrupt input + * @rmtoll EXTISEL EXTI2 FL_GPIO_GetExtiLine2 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine2(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI2_Msk)); +} + +/** + * @brief Set EXTI3 interrupt input + * @rmtoll EXTISEL EXTI3 FL_GPIO_SetExtiLine3 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_3_PA12 + * @arg @ref FL_GPIO_EXTI_LINE_3_PA13 + * @arg @ref FL_GPIO_EXTI_LINE_3_PA14 + * @arg @ref FL_GPIO_EXTI_LINE_3_PA15 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine3(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI3_Msk, EXTIPin); +} + +/** + * @brief Get EXTI3 interrupt input + * @rmtoll EXTISEL EXTI3 FL_GPIO_GetExtiLine3 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine3(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI3_Msk)); +} + +/** + * @brief Set EXTI4 interrupt input + * @rmtoll EXTISEL EXTI4 FL_GPIO_SetExtiLine4 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_4_PB0 + * @arg @ref FL_GPIO_EXTI_LINE_4_PB1 + * @arg @ref FL_GPIO_EXTI_LINE_4_PB2 + * @arg @ref FL_GPIO_EXTI_LINE_4_PB3 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine4(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI4_Msk, EXTIPin); +} + +/** + * @brief Get EXTI4 interrupt input + * @rmtoll EXTISEL EXTI4 FL_GPIO_GetExtiLine4 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine4(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI4_Msk)); +} + +/** + * @brief Set EXTI5 interrupt input + * @rmtoll EXTISEL EXTI5 FL_GPIO_SetExtiLine5 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_5_PB4 + * @arg @ref FL_GPIO_EXTI_LINE_5_PB5 + * @arg @ref FL_GPIO_EXTI_LINE_5_PB6 + * @arg @ref FL_GPIO_EXTI_LINE_5_PB7 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine5(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI5_Msk, EXTIPin); +} + +/** + * @brief Get EXTI5 interrupt input + * @rmtoll EXTISEL EXTI5 FL_GPIO_GetExtiLine5 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine5(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI5_Msk)); +} + +/** + * @brief Set EXTI6 interrupt input + * @rmtoll EXTISEL EXTI6 FL_GPIO_SetExtiLine6 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_6_PB8 + * @arg @ref FL_GPIO_EXTI_LINE_6_PB9 + * @arg @ref FL_GPIO_EXTI_LINE_6_PB10 + * @arg @ref FL_GPIO_EXTI_LINE_6_PB11 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine6(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI6_Msk, EXTIPin); +} + +/** + * @brief Get EXTI6 interrupt input + * @rmtoll EXTISEL EXTI6 FL_GPIO_GetExtiLine6 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine6(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI6_Msk)); +} + +/** + * @brief Set EXTI7 interrupt input + * @rmtoll EXTISEL EXTI7 FL_GPIO_SetExtiLine7 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_7_PB12 + * @arg @ref FL_GPIO_EXTI_LINE_7_PB13 + * @arg @ref FL_GPIO_EXTI_LINE_7_PB14 + * @arg @ref FL_GPIO_EXTI_LINE_7_PB15 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine7(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI7_Msk, EXTIPin); +} + +/** + * @brief Get EXTI7 interrupt input + * @rmtoll EXTISEL EXTI7 FL_GPIO_GetExtiLine7 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine7(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI7_Msk)); +} + +/** + * @brief Set EXTI8 interrupt input + * @rmtoll EXTISEL EXTI8 FL_GPIO_SetExtiLine8 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_8_PC0 + * @arg @ref FL_GPIO_EXTI_LINE_8_PC1 + * @arg @ref FL_GPIO_EXTI_LINE_8_PC2 + * @arg @ref FL_GPIO_EXTI_LINE_8_PC3 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine8(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI8_Msk, EXTIPin); +} + +/** + * @brief Get EXTI8 interrupt input + * @rmtoll EXTISEL EXTI8 FL_GPIO_GetExtiLine8 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine8(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI8_Msk)); +} + +/** + * @brief Set EXTI9 interrupt input + * @rmtoll EXTISEL EXTI9 FL_GPIO_SetExtiLine9 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_9_PC4 + * @arg @ref FL_GPIO_EXTI_LINE_9_PC5 + * @arg @ref FL_GPIO_EXTI_LINE_9_PC6 + * @arg @ref FL_GPIO_EXTI_LINE_9_PC7 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine9(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI9_Msk, EXTIPin); +} + +/** + * @brief Get EXTI9 interrupt input + * @rmtoll EXTISEL EXTI9 FL_GPIO_GetExtiLine9 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine9(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI9_Msk)); +} + +/** + * @brief Set EXTI10 interrupt input + * @rmtoll EXTISEL EXTI10 FL_GPIO_SetExtiLine10 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_10_PC8 + * @arg @ref FL_GPIO_EXTI_LINE_10_PC9 + * @arg @ref FL_GPIO_EXTI_LINE_10_PC10 + * @arg @ref FL_GPIO_EXTI_LINE_10_PC11 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine10(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI10_Msk, EXTIPin); +} + +/** + * @brief Get EXTI10 interrupt input + * @rmtoll EXTISEL EXTI10 FL_GPIO_GetExtiLine10 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine10(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI10_Msk)); +} + +/** + * @brief Set EXTI11 interrupt input + * @rmtoll EXTISEL EXTI11 FL_GPIO_SetExtiLine11 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_PIN_0 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine11(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI11_Msk, EXTIPin); +} + +/** + * @brief Get EXTI11 interrupt input + * @rmtoll EXTISEL EXTI11 FL_GPIO_GetExtiLine11 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine11(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI11_Msk)); +} + +/** + * @brief Set EXTI12 interrupt input + * @rmtoll EXTISEL EXTI12 FL_GPIO_SetExtiLine12 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_12_PD0 + * @arg @ref FL_GPIO_EXTI_LINE_12_PD1 + * @arg @ref FL_GPIO_EXTI_LINE_12_PD2 + * @arg @ref FL_GPIO_EXTI_LINE_12_PD3 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine12(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI12_Msk, EXTIPin); +} + +/** + * @brief Get EXTI12 interrupt input + * @rmtoll EXTISEL EXTI12 FL_GPIO_GetExtiLine12 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine12(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI12_Msk)); +} + +/** + * @brief Set EXTI13 interrupt input + * @rmtoll EXTISEL EXTI13 FL_GPIO_SetExtiLine13 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_13_PD4 + * @arg @ref FL_GPIO_EXTI_LINE_13_PD5 + * @arg @ref FL_GPIO_EXTI_LINE_13_PD6 + * @arg @ref FL_GPIO_EXTI_LINE_13_PD7 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine13(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI13_Msk, EXTIPin); +} + +/** + * @brief Get EXTI13 interrupt input + * @rmtoll EXTISEL EXTI13 FL_GPIO_GetExtiLine13 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine13(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI13_Msk)); +} + +/** + * @brief Set EXTI14 interrupt input + * @rmtoll EXTISEL EXTI14 FL_GPIO_SetExtiLine14 + * @param GPIOx GPIO Port + * @param EXTIPin This parameter can be one of the following values: + * @arg @ref FL_GPIO_EXTI_LINE_14_PD8 + * @arg @ref FL_GPIO_EXTI_LINE_14_PD9 + * @arg @ref FL_GPIO_EXTI_LINE_14_PD10 + * @arg @ref FL_GPIO_EXTI_LINE_14_PD11 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetExtiLine14(GPIO_COMMON_Type *GPIOx, uint32_t EXTIPin) +{ + MODIFY_REG(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI14_Msk, EXTIPin); +} + +/** + * @brief Get EXTI14 interrupt input + * @rmtoll EXTISEL EXTI14 FL_GPIO_GetExtiLine14 + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPIO_GetExtiLine14(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->EXTISEL, GPIO_EXTISEL_EXTI14_Msk)); +} + +/** + * @brief Get WKUP enable status + * @rmtoll PINWKEN EN FL_GPIO_IsEnabledWakeup + * @param GPIOx GPIO Port + * @param wakeup This parameter can be one of the following values: + * @arg @ref FL_GPIO_WAKEUP_0 + * @arg @ref FL_GPIO_WAKEUP_1 + * @arg @ref FL_GPIO_WAKEUP_2 + * @arg @ref FL_GPIO_WAKEUP_3 + * @arg @ref FL_GPIO_WAKEUP_4 + * @arg @ref FL_GPIO_WAKEUP_5 + * @arg @ref FL_GPIO_WAKEUP_6 + * @arg @ref FL_GPIO_WAKEUP_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPIO_IsEnabledWakeup(GPIO_COMMON_Type *GPIOx, uint32_t wakeup) +{ + return (uint32_t)(READ_BIT(GPIOx->PINWKEN, ((wakeup & 0xff) << 0x0U)) == ((wakeup & 0xff) << 0x0U)); +} + +/** + * @brief WKUP enable + * @rmtoll PINWKEN EN FL_GPIO_EnableWakeup + * @param GPIOx GPIO Port + * @param wakeup This parameter can be one of the following values: + * @arg @ref FL_GPIO_WAKEUP_0 + * @arg @ref FL_GPIO_WAKEUP_1 + * @arg @ref FL_GPIO_WAKEUP_2 + * @arg @ref FL_GPIO_WAKEUP_3 + * @arg @ref FL_GPIO_WAKEUP_4 + * @arg @ref FL_GPIO_WAKEUP_5 + * @arg @ref FL_GPIO_WAKEUP_6 + * @arg @ref FL_GPIO_WAKEUP_7 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_EnableWakeup(GPIO_COMMON_Type *GPIOx, uint32_t wakeup) +{ + SET_BIT(GPIOx->PINWKEN, ((wakeup & 0xff) << 0x0U)); +} + +/** + * @brief WKUP disable + * @rmtoll PINWKEN EN FL_GPIO_DisableWakeup + * @param GPIOx GPIO Port + * @param wakeup This parameter can be one of the following values: + * @arg @ref FL_GPIO_WAKEUP_0 + * @arg @ref FL_GPIO_WAKEUP_1 + * @arg @ref FL_GPIO_WAKEUP_2 + * @arg @ref FL_GPIO_WAKEUP_3 + * @arg @ref FL_GPIO_WAKEUP_4 + * @arg @ref FL_GPIO_WAKEUP_5 + * @arg @ref FL_GPIO_WAKEUP_6 + * @arg @ref FL_GPIO_WAKEUP_7 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_DisableWakeup(GPIO_COMMON_Type *GPIOx, uint32_t wakeup) +{ + CLEAR_BIT(GPIOx->PINWKEN, ((wakeup & 0xff) << 0x0U)); +} + +/** + * @brief Get WKUP interrupt entry + * @rmtoll PINWKEN WKISEL FL_GPIO_GetWakeupInterruptEntry + * @param GPIOx GPIO Port + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPIO_WAKEUP_INT_ENTRY_NMI + * @arg @ref FL_GPIO_WAKEUP_INT_ENTRY_38 + */ +__STATIC_INLINE uint32_t FL_GPIO_GetWakeupInterruptEntry(GPIO_COMMON_Type *GPIOx) +{ + return (uint32_t)(READ_BIT(GPIOx->PINWKEN, GPIO_PINWKEN_WKISEL_Msk)); +} + +/** + * @brief Set wkup interrupt entry + * @rmtoll PINWKEN WKISEL FL_GPIO_SetWakeupInterruptEntry + * @param GPIOx GPIO Port + * @param wakeup This parameter can be one of the following values: + * @arg @ref FL_GPIO_WAKEUP_INT_ENTRY_NMI + * @arg @ref FL_GPIO_WAKEUP_INT_ENTRY_38 + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetWakeupInterruptEntry(GPIO_COMMON_Type *GPIOx, uint32_t wakeup) +{ + MODIFY_REG(GPIOx->PINWKEN, GPIO_PINWKEN_WKISEL_Msk, wakeup); +} + +/** + * @brief Set WKUP edge polarity + * @rmtoll PINWKEN SEL FL_GPIO_SetWakeupEdge + * @param GPIOx GPIO Port + * @param wakeup This parameter can be one of the following values: + * @arg @ref FL_GPIO_WAKEUP_0 + * @arg @ref FL_GPIO_WAKEUP_1 + * @arg @ref FL_GPIO_WAKEUP_2 + * @arg @ref FL_GPIO_WAKEUP_3 + * @arg @ref FL_GPIO_WAKEUP_4 + * @arg @ref FL_GPIO_WAKEUP_5 + * @arg @ref FL_GPIO_WAKEUP_6 + * @arg @ref FL_GPIO_WAKEUP_7 + * @param mode This parameter can be one of the following values: + * @arg @ref FL_GPIO_WAKEUP_TRIGGER_RISING + * @arg @ref FL_GPIO_WAKEUP_TRIGGER_FALLING + * @retval None + */ +__STATIC_INLINE void FL_GPIO_SetWakeupEdge(GPIO_COMMON_Type *GPIOx, uint32_t wakeup, uint32_t mode) +{ + MODIFY_REG(GPIOx->PINWKEN, (wakeup << GPIO_PINWKEN_SEL_Pos), (wakeup * mode)); +} + +/** + * @brief Get WKUP edge polarity + * @rmtoll PINWKEN SEL FL_GPIO_GetWakeupEdge + * @param GPIOx GPIO Port + * @param wakeup This parameter can be one of the following values: + * @arg @ref FL_GPIO_WAKEUP_0 + * @arg @ref FL_GPIO_WAKEUP_1 + * @arg @ref FL_GPIO_WAKEUP_2 + * @arg @ref FL_GPIO_WAKEUP_3 + * @arg @ref FL_GPIO_WAKEUP_4 + * @arg @ref FL_GPIO_WAKEUP_5 + * @arg @ref FL_GPIO_WAKEUP_6 + * @arg @ref FL_GPIO_WAKEUP_7 + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPIO_WAKEUP_TRIGGER_RISING + * @arg @ref FL_GPIO_WAKEUP_TRIGGER_FALLING + */ +__STATIC_INLINE uint32_t FL_GPIO_GetWakeupEdge(GPIO_COMMON_Type *GPIOx, uint32_t wakeup) +{ + return (uint32_t)(READ_BIT(GPIOx->PINWKEN, (wakeup << GPIO_PINWKEN_SEL_Pos)) / wakeup); +} + +/** + * @} + */ + +/** @defgroup GPIO_FL_EF_Init Initialization and de-initialization functions + * @{ + */ + +FL_ErrorStatus FL_GPIO_Init(GPIO_Type *GPIOx, FL_GPIO_InitTypeDef *initStruct); +FL_ErrorStatus FL_GPIO_DeInit(GPIO_Type *GPIOx, uint32_t pin); +void FL_GPIO_StructInit(FL_GPIO_InitTypeDef *initStruct); +FL_ErrorStatus FL_WKUP_Init(FL_WKUP_InitTypeDef *initStruct, uint32_t wakeup); +FL_ErrorStatus FL_WKUP_DeInit(uint32_t wakeup); +void FL_WKUP_StructInit(FL_WKUP_InitTypeDef *initStruct); + +/** + * @} + */ + +/** @defgroup RNG_FL_EF_Operation Opeartion functions + * @{ + */ + +void FL_GPIO_ALLPIN_LPM_MODE(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_GPIO_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_gptim.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_gptim.h new file mode 100644 index 0000000000..afa017305c --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_gptim.h @@ -0,0 +1,2958 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_gptim.h + * @author FMSH Application Team + * @brief Head file of GPTIM FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_GPTIM_H +#define __FM33LC0XX_FL_GPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup GPTIM GPTIM + * @brief GPTIM FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup GPTIM_FL_ES_INIT GPTIM Exported Init structures + * @{ + */ + +/** + * @brief GPTIM Init Sturcture Definition + */ +typedef struct +{ + /** 预分频系数 */ + uint32_t prescaler; + + /** 计数模式 */ + uint32_t counterMode; + + /** 自动重装载值 */ + uint32_t autoReload; + + /** 预装载使能 */ + uint32_t autoReloadState; + + /** 定时器分频系数与数字滤波器所使用的采样时钟分频比*/ + uint32_t clockDivision; + +} FL_GPTIM_InitTypeDef; + +/** + * @brief GPTIM SlaveMode Init Sturcture Definition + */ +typedef struct +{ + /** ITRx 源*/ + uint32_t ITRSourceGroup; + + /** 外部时钟源模式 */ + uint32_t slaveMode; + + /** 输入触发信号选择 */ + uint32_t triggerSrc; + + /** Trigger 延迟*/ + uint32_t triggerDelay; + +} FL_GPTIM_SlaveInitTypeDef; + +/** + * @brief GPTIM Input Capture Init Structure Definition + */ +typedef struct +{ + /** 输入捕获使能 */ + uint32_t captureState; + + /** 输入捕获极性 */ + uint32_t ICPolarity; + + /** 通道映射激活的输入选择 */ + uint32_t ICActiveInput; + + /** 输入分频 */ + uint32_t ICPrescaler; + + /** 输入滤波 */ + uint32_t ICFilter; + +} FL_GPTIM_IC_InitTypeDef; + +/** + * @brief GPTIM ETR Init Structure Definition + */ +typedef struct +{ + /** 外部触发使能 */ + uint32_t useExternalTrigger; + + /** 外部时钟滤波 */ + uint32_t ETRFilter; + + /** 外部时钟分频 */ + uint32_t ETRClockDivision; + + /** 外部时钟触发极性 */ + uint32_t ETRPolarity; + +} FL_GPTIM_ETR_InitTypeDef; + +/** + * @brief GPTIM Output Compare Init Structure Definition + */ +typedef struct +{ + /** 比较输出模式 */ + uint32_t OCMode; + + /** 比较输出通道快速模式使能 */ + uint32_t OCFastMode; + + /** 输出比较预装载 */ + uint32_t OCPreload; + + /** 通道比较值 */ + uint32_t compareValue; + + /** 比较输出极性 */ + uint32_t OCPolarity; + + /** ETR清0使能 */ + uint32_t OCETRFStatus; + +} FL_GPTIM_OC_InitTypeDef; + +/** + * @} + */ + +/** + * GPTIM0~GPTIM2 ITRSEL_Group 映射表 + * + * ===================== GPTIM0 ====================== + * --------------------------------------------------- + * ITRx | Group | Function Name | Function Type + * --------------------------------------------------- + * ITR0 | 0 | ATIM_TRGO | 计数触发 + * | 1 | UART0_RX | 宽度捕捉 + * | 2 | UART1_RX | 宽度捕捉 + * | 3 | UART3_RX | 宽度捕捉 + * --------------------------------------------------- + * ITR1 | 0 | GPTIM2_TRGO | 计数触发 + * | 1 | XTHF | 周期捕捉 + * | 2 | RCHF | 周期捕捉 + * | 3 | LPUART1_RX | 周期捕捉 + * --------------------------------------------------- + * ITR2 | 0 | BSTIM32_TRGO | 计数触发 + * | 1 | LPUART2_RX | 宽度捕捉 + * | 2 | RCLP | 周期捕捉 + * | 3 | XTLF | 周期捕捉 + * --------------------------------------------------- + * ITR3 | 0 | COMP1_TRGO | 计数触发 + * | 1 | RCLF | 周期捕捉 + * | 2 | COMP2_TRGO | 计数触发 + * | 3 | LPT32_TRGO | 计数触发 + * --------------------------------------------------- + * + * ===================== GPTIM1 ====================== + * --------------------------------------------------- + * ITRx | Group | Function Name | Function Type + * --------------------------------------------------- + * ITR0 | 0 | ATIM_TRGO | 计数触发 + * | 1 | UART0_RX | 宽度捕捉 + * | 2 | UART1_RX | 宽度捕捉 + * | 3 | UART3_RX | 宽度捕捉 + * --------------------------------------------------- + * ITR1 | 0 | GPTIM0_TRGO | 计数触发 + * | 1 | LUT1_TRGO | 周期捕捉 + * | 2 | RCHF | 周期捕捉 + * | 3 | ADC_EOC_TRGO | 计数触发 + * --------------------------------------------------- + * ITR2 | 0 | BSTIM32_TRGO | 计数触发 + * | 1 | LSCLK | 周期捕捉 + * | 2 | RCLP | 周期捕捉 + * | 3 | XTLF | 周期捕捉 + * --------------------------------------------------- + * ITR3 | 0 | COMP1_TRGO | 计数触发 + * | 1 | LUT3_TRGO | 周期捕捉 + * | 2 | COMP2_TRGO | 计数触发 + * | 3 | LPT32_TRGO | 计数触发 + * --------------------------------------------------- + * + */ + +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup GPTIM_FL_Exported_Constants GPTIM Exported Constants + * @{ + */ + +#define GPTIM_CR1_CKD_Pos (8U) +#define GPTIM_CR1_CKD_Msk (0x3U << GPTIM_CR1_CKD_Pos) +#define GPTIM_CR1_CKD GPTIM_CR1_CKD_Msk + +#define GPTIM_CR1_ARPE_Pos (7U) +#define GPTIM_CR1_ARPE_Msk (0x1U << GPTIM_CR1_ARPE_Pos) +#define GPTIM_CR1_ARPE GPTIM_CR1_ARPE_Msk + +#define GPTIM_CR1_CMS_Pos (5U) +#define GPTIM_CR1_CMS_Msk (0x3U << GPTIM_CR1_CMS_Pos) +#define GPTIM_CR1_CMS GPTIM_CR1_CMS_Msk + +#define GPTIM_CR1_DIR_Pos (4U) +#define GPTIM_CR1_DIR_Msk (0x1U << GPTIM_CR1_DIR_Pos) +#define GPTIM_CR1_DIR GPTIM_CR1_DIR_Msk + +#define GPTIM_CR1_OPM_Pos (3U) +#define GPTIM_CR1_OPM_Msk (0x1U << GPTIM_CR1_OPM_Pos) +#define GPTIM_CR1_OPM GPTIM_CR1_OPM_Msk + +#define GPTIM_CR1_URS_Pos (2U) +#define GPTIM_CR1_URS_Msk (0x1U << GPTIM_CR1_URS_Pos) +#define GPTIM_CR1_URS GPTIM_CR1_URS_Msk + +#define GPTIM_CR1_UDIS_Pos (1U) +#define GPTIM_CR1_UDIS_Msk (0x1U << GPTIM_CR1_UDIS_Pos) +#define GPTIM_CR1_UDIS GPTIM_CR1_UDIS_Msk + +#define GPTIM_CR1_CEN_Pos (0U) +#define GPTIM_CR1_CEN_Msk (0x1U << GPTIM_CR1_CEN_Pos) +#define GPTIM_CR1_CEN GPTIM_CR1_CEN_Msk + +#define GPTIM_CR2_TI1S_Pos (7U) +#define GPTIM_CR2_TI1S_Msk (0x1U << GPTIM_CR2_TI1S_Pos) +#define GPTIM_CR2_TI1S GPTIM_CR2_TI1S_Msk + +#define GPTIM_CR2_MMS_Pos (4U) +#define GPTIM_CR2_MMS_Msk (0x7U << GPTIM_CR2_MMS_Pos) +#define GPTIM_CR2_MMS GPTIM_CR2_MMS_Msk + +#define GPTIM_CR2_CCDS_Pos (3U) +#define GPTIM_CR2_CCDS_Msk (0x1U << GPTIM_CR2_CCDS_Pos) +#define GPTIM_CR2_CCDS GPTIM_CR2_CCDS_Msk + +#define GPTIM_SMCR_ETP_Pos (15U) +#define GPTIM_SMCR_ETP_Msk (0x1U << GPTIM_SMCR_ETP_Pos) +#define GPTIM_SMCR_ETP GPTIM_SMCR_ETP_Msk + +#define GPTIM_SMCR_ECE_Pos (14U) +#define GPTIM_SMCR_ECE_Msk (0x1U << GPTIM_SMCR_ECE_Pos) +#define GPTIM_SMCR_ECE GPTIM_SMCR_ECE_Msk + +#define GPTIM_SMCR_ETPS_Pos (12U) +#define GPTIM_SMCR_ETPS_Msk (0x3U << GPTIM_SMCR_ETPS_Pos) +#define GPTIM_SMCR_ETPS GPTIM_SMCR_ETPS_Msk + +#define GPTIM_SMCR_ETF_Pos (8U) +#define GPTIM_SMCR_ETF_Msk (0xfU << GPTIM_SMCR_ETF_Pos) +#define GPTIM_SMCR_ETF GPTIM_SMCR_ETF_Msk + +#define GPTIM_SMCR_MSM_Pos (7U) +#define GPTIM_SMCR_MSM_Msk (0x1U << GPTIM_SMCR_MSM_Pos) +#define GPTIM_SMCR_MSM GPTIM_SMCR_MSM_Msk + +#define GPTIM_SMCR_TS_Pos (4U) +#define GPTIM_SMCR_TS_Msk (0x7U << GPTIM_SMCR_TS_Pos) +#define GPTIM_SMCR_TS GPTIM_SMCR_TS_Msk + +#define GPTIM_SMCR_SMS_Pos (0U) +#define GPTIM_SMCR_SMS_Msk (0x7U << GPTIM_SMCR_SMS_Pos) +#define GPTIM_SMCR_SMS GPTIM_SMCR_SMS_Msk + +#define GPTIM_DIER_CC1BURSTEN_Pos (16U) +#define GPTIM_DIER_CC1BURSTEN_Msk (0x1U << GPTIM_DIER_CC1BURSTEN_Pos) +#define GPTIM_DIER_CC1BURSTEN GPTIM_DIER_CC1BURSTEN_Msk + +#define GPTIM_DIER_CC2BURSTEN_Pos (17U) +#define GPTIM_DIER_CC2BURSTEN_Msk (0x1U << GPTIM_DIER_CC2BURSTEN_Pos) +#define GPTIM_DIER_CC2BURSTEN GPTIM_DIER_CC2BURSTEN_Msk + +#define GPTIM_DIER_CC3BURSTEN_Pos (18U) +#define GPTIM_DIER_CC3BURSTEN_Msk (0x1U << GPTIM_DIER_CC3BURSTEN_Pos) +#define GPTIM_DIER_CC3BURSTEN GPTIM_DIER_CC3BURSTEN_Msk + +#define GPTIM_DIER_CC4BURSTEN_Pos (19U) +#define GPTIM_DIER_CC4BURSTEN_Msk (0x1U << GPTIM_DIER_CC4BURSTEN_Pos) +#define GPTIM_DIER_CC4BURSTEN GPTIM_DIER_CC4BURSTEN_Msk + +#define GPTIM_DIER_TDE_Pos (14U) +#define GPTIM_DIER_TDE_Msk (0x1U << GPTIM_DIER_TDE_Pos) +#define GPTIM_DIER_TDE GPTIM_DIER_TDE_Msk + +#define GPTIM_DIER_CCDE_Pos (9U) +#define GPTIM_DIER_CCDE_Msk (0x1U << GPTIM_DIER_CCDE_Pos) +#define GPTIM_DIER_CCDE GPTIM_DIER_CCDE_Msk + +#define GPTIM_DIER_UDE_Pos (8U) +#define GPTIM_DIER_UDE_Msk (0x1U << GPTIM_DIER_UDE_Pos) +#define GPTIM_DIER_UDE GPTIM_DIER_UDE_Msk + +#define GPTIM_DIER_TIE_Pos (6U) +#define GPTIM_DIER_TIE_Msk (0x1U << GPTIM_DIER_TIE_Pos) +#define GPTIM_DIER_TIE GPTIM_DIER_TIE_Msk + +#define GPTIM_DIER_CCIE_Pos (1U) +#define GPTIM_DIER_CCIE_Msk (0x1U << GPTIM_DIER_CCIE_Pos) +#define GPTIM_DIER_CCIE GPTIM_DIER_CCIE_Msk + +#define GPTIM_DIER_UIE_Pos (0U) +#define GPTIM_DIER_UIE_Msk (0x1U << GPTIM_DIER_UIE_Pos) +#define GPTIM_DIER_UIE GPTIM_DIER_UIE_Msk + +#define GPTIM_ISR_CCOF_Pos (9U) +#define GPTIM_ISR_CCOF_Msk (0x1U << GPTIM_ISR_CCOF_Pos) +#define GPTIM_ISR_CCOF GPTIM_ISR_CCOF_Msk + +#define GPTIM_ISR_TIF_Pos (6U) +#define GPTIM_ISR_TIF_Msk (0x1U << GPTIM_ISR_TIF_Pos) +#define GPTIM_ISR_TIF GPTIM_ISR_TIF_Msk + +#define GPTIM_ISR_CCIF_Pos (1U) +#define GPTIM_ISR_CCIF_Msk (0x1U << GPTIM_ISR_CCIF_Pos) +#define GPTIM_ISR_CCIF GPTIM_ISR_CCIF_Msk + +#define GPTIM_ISR_UIF_Pos (0U) +#define GPTIM_ISR_UIF_Msk (0x1U << GPTIM_ISR_UIF_Pos) +#define GPTIM_ISR_UIF GPTIM_ISR_UIF_Msk + +#define GPTIM_EGR_TG_Pos (6U) +#define GPTIM_EGR_TG_Msk (0x1U << GPTIM_EGR_TG_Pos) +#define GPTIM_EGR_TG GPTIM_EGR_TG_Msk + +#define GPTIM_EGR_CCG_Pos (1U) +#define GPTIM_EGR_CCG_Msk (0x1U << GPTIM_EGR_CCG_Pos) +#define GPTIM_EGR_CCG GPTIM_EGR_CCG_Msk + +#define GPTIM_EGR_UG_Pos (0U) +#define GPTIM_EGR_UG_Msk (0x1U << GPTIM_EGR_UG_Pos) +#define GPTIM_EGR_UG GPTIM_EGR_UG_Msk + +#define GPTIM_DCR_DBL_Pos (8U) +#define GPTIM_DCR_DBL_Msk (0x1fU << GPTIM_DCR_DBL_Pos) +#define GPTIM_DCR_DBL GPTIM_DCR_DBL_Msk + +#define GPTIM_DCR_DBA_Pos (0U) +#define GPTIM_DCR_DBA_Msk (0x1fU << GPTIM_DCR_DBA_Pos) +#define GPTIM_DCR_DBA GPTIM_DCR_DBA_Msk + +#define GPTIM_ITRSEL_Pos (0U) +#define GPTIM_ITRSEL_Msk (0x3U << GPTIM_ITRSEL_Pos) +#define GPTIM_ITRSEL GPTIM_ITRSEL_Msk + +#define GPTIM_CCMR_OCCE_Pos (7U) +#define GPTIM_CCMR_OCCE_Msk (0x1U << GPTIM_CCMR_OCCE_Pos) +#define GPTIM_CCMR_OCCE GPTIM_CCMR_OCCE_Msk + +#define GPTIM_CCMR_OCM_Pos (4U) +#define GPTIM_CCMR_OCM_Msk (0x7U << GPTIM_CCMR_OCM_Pos) +#define GPTIM_CCMR_OCM GPTIM_CCMR_OCM_Msk + +#define GPTIM_CCMR_OCPE_Pos (3U) +#define GPTIM_CCMR_OCPE_Msk (0x1U << GPTIM_CCMR_OCPE_Pos) +#define GPTIM_CCMR_OCPE GPTIM_CCMR_OCPE_Msk + +#define GPTIM_CCMR_OCFE_Pos (2U) +#define GPTIM_CCMR_OCFE_Msk (0x1U << GPTIM_CCMR_OCFE_Pos) +#define GPTIM_CCMR_OCFE GPTIM_CCMR_OCFE_Msk + +#define GPTIM_CCMR_ICF_Pos (4U) +#define GPTIM_CCMR_ICF_Msk (0xfU << GPTIM_CCMR_ICF_Pos) +#define GPTIM_CCMR_ICF GPTIM_CCMR_ICF_Msk + +#define GPTIM_CCMR_ICPSC_Pos (2U) +#define GPTIM_CCMR_ICPSC_Msk (0x3U << GPTIM_CCMR_ICPSC_Pos) +#define GPTIM_CCMR_ICPSC GPTIM_CCMR_ICPSC_Msk + +#define GPTIM_CCMR_CCS_Pos (0U) +#define GPTIM_CCMR_CCS_Msk (0x3U << GPTIM_CCMR_CCS_Pos) +#define GPTIM_CCMR_CCS GPTIM_CCMR_CCS_Msk + +#define GPTIM_CCER_CCOP_Pos (1U) +#define GPTIM_CCER_CCOP_Msk (0x1U << GPTIM_CCER_CCOP_Pos) +#define GPTIM_CCER_CCOP GPTIM_CCER_CCOP_Msk + +#define GPTIM_CCER_CCIP_Pos (1U) +#define GPTIM_CCER_CCIP_Msk (0x1U << GPTIM_CCER_CCIP_Pos) +#define GPTIM_CCER_CCIP GPTIM_CCER_CCIP_Msk + +#define GPTIM_CCER_CCE_Pos (0U) +#define GPTIM_CCER_CCE_Msk (0x1U << GPTIM_CCER_CCE_Pos) +#define GPTIM_CCER_CCE GPTIM_CCER_CCE_Msk + + + +#define FL_GPTIM_CHANNEL_1 (0x1U << 0U) +#define FL_GPTIM_CHANNEL_2 (0x1U << 1U) +#define FL_GPTIM_CHANNEL_3 (0x1U << 2U) +#define FL_GPTIM_CHANNEL_4 (0x1U << 3U) +#define FL_GPTIM_ITR0 (0x1U << 0U) +#define FL_GPTIM_ITR1 (0x1U << 1U) +#define FL_GPTIM_ITR2 (0x1U << 2U) +#define FL_GPTIM_ITR3 (0x1U << 3U) + + + +#define FL_GPTIM_CLK_DIVISION_DIV1 (0x0U << GPTIM_CR1_CKD_Pos) +#define FL_GPTIM_CLK_DIVISION_DIV2 (0x1U << GPTIM_CR1_CKD_Pos) +#define FL_GPTIM_CLK_DIVISION_DIV4 (0x2U << GPTIM_CR1_CKD_Pos) + + +#define FL_GPTIM_COUNTER_ALIGNED_EDGE (0x0U << GPTIM_CR1_CMS_Pos) +#define FL_GPTIM_COUNTER_ALIGNED_CENTER_DOWN (0x1U << GPTIM_CR1_CMS_Pos) +#define FL_GPTIM_COUNTER_ALIGNED_CENTER_UP (0x2U << GPTIM_CR1_CMS_Pos) +#define FL_GPTIM_COUNTER_ALIGNED_CENTER_UP_DOWN (0x3U << GPTIM_CR1_CMS_Pos) + + +#define FL_GPTIM_COUNTER_DIR_UP (0x0U << GPTIM_CR1_DIR_Pos) +#define FL_GPTIM_COUNTER_DIR_DOWN (0x1U << GPTIM_CR1_DIR_Pos) + + +#define FL_GPTIM_ONE_PULSE_MODE_CONTINUOUS (0x0U << GPTIM_CR1_OPM_Pos) +#define FL_GPTIM_ONE_PULSE_MODE_SINGLE (0x1U << GPTIM_CR1_OPM_Pos) + + +#define FL_GPTIM_UPDATE_SOURCE_REGULAR (0x0U << GPTIM_CR1_URS_Pos) +#define FL_GPTIM_UPDATE_SOURCE_COUNTER (0x1U << GPTIM_CR1_URS_Pos) + + +#define FL_GPTIM_TRGO_RESET (0x0U << GPTIM_CR2_MMS_Pos) +#define FL_GPTIM_TRGO_ENABLE (0x1U << GPTIM_CR2_MMS_Pos) +#define FL_GPTIM_TRGO_UPDATE (0x2U << GPTIM_CR2_MMS_Pos) +#define FL_GPTIM_TRGO_CC1IF (0x3U << GPTIM_CR2_MMS_Pos) +#define FL_GPTIM_TRGO_OC1REF (0x4U << GPTIM_CR2_MMS_Pos) +#define FL_GPTIM_TRGO_OC2REF (0x5U << GPTIM_CR2_MMS_Pos) +#define FL_GPTIM_TRGO_OC3REF (0x6U << GPTIM_CR2_MMS_Pos) +#define FL_GPTIM_TRGO_OC4REF (0x7U << GPTIM_CR2_MMS_Pos) + + +#define FL_GPTIM_DMA_REQ_CC (0x0U << GPTIM_CR2_CCDS_Pos) +#define FL_GPTIM_DMA_REQ_UPDATE (0x1U << GPTIM_CR2_CCDS_Pos) + + +#define FL_GPTIM_ETR_POLARITY_NORMAL (0x0U << GPTIM_SMCR_ETP_Pos) +#define FL_GPTIM_ETR_POLARITY_INVERT (0x1U << GPTIM_SMCR_ETP_Pos) + + +#define FL_GPTIM_ETR_PSC_DIV1 (0x0U << GPTIM_SMCR_ETPS_Pos) +#define FL_GPTIM_ETR_PSC_DIV2 (0x1U << GPTIM_SMCR_ETPS_Pos) +#define FL_GPTIM_ETR_PSC_DIV4 (0x2U << GPTIM_SMCR_ETPS_Pos) +#define FL_GPTIM_ETR_PSC_DIV8 (0x3U << GPTIM_SMCR_ETPS_Pos) + + +#define FL_GPTIM_ETR_FILTER_DIV1 (0x0U << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV1_N2 (0x1U << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV1_N4 (0x2U << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV1_N8 (0x3U << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV2_N6 (0x4U << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV2_N8 (0x5U << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV4_N6 (0x6U << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV4_N8 (0x7U << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV8_N6 (0x8U << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV8_N8 (0x9U << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV16_N5 (0xaU << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV16_N6 (0xbU << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV16_N8 (0xcU << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV32_N5 (0xdU << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV32_N6 (0xeU << GPTIM_SMCR_ETF_Pos) +#define FL_GPTIM_ETR_FILTER_DIV32_N8 (0xfU << GPTIM_SMCR_ETF_Pos) + + +#define FL_GPTIM_TIM_TS_ITR0 (0x0U << GPTIM_SMCR_TS_Pos) +#define FL_GPTIM_TIM_TS_ITR1 (0x1U << GPTIM_SMCR_TS_Pos) +#define FL_GPTIM_TIM_TS_ITR2 (0x2U << GPTIM_SMCR_TS_Pos) +#define FL_GPTIM_TIM_TS_ITR3 (0x3U << GPTIM_SMCR_TS_Pos) +#define FL_GPTIM_TIM_TS_TI1F_ED (0x4U << GPTIM_SMCR_TS_Pos) +#define FL_GPTIM_TIM_TS_TI1FP1 (0x5U << GPTIM_SMCR_TS_Pos) +#define FL_GPTIM_TIM_TS_TI2FP2 (0x6U << GPTIM_SMCR_TS_Pos) +#define FL_GPTIM_TIM_TS_ETRF (0x7U << GPTIM_SMCR_TS_Pos) + + +#define FL_GPTIM_SLAVE_MODE_PROHIBITED (0x0U << GPTIM_SMCR_SMS_Pos) +#define FL_GPTIM_SLAVE_MODE_ENCODER_X2_TI1 (0x1U << GPTIM_SMCR_SMS_Pos) +#define FL_GPTIM_SLAVE_MODE_ENCODER_X2_TI2 (0x2U << GPTIM_SMCR_SMS_Pos) +#define FL_GPTIM_SLAVE_MODE_ENCODER_X4_TI1TI2 (0x3U << GPTIM_SMCR_SMS_Pos) +#define FL_GPTIM_SLAVE_MODE_TRGI_RISE_RST (0x4U << GPTIM_SMCR_SMS_Pos) +#define FL_GPTIM_SLAVE_MODE_TRGI_HIGH_RUN (0x5U << GPTIM_SMCR_SMS_Pos) +#define FL_GPTIM_SLAVE_MODE_TRGI_RISE_RUN (0x6U << GPTIM_SMCR_SMS_Pos) +#define FL_GPTIM_SLAVE_MODE_TRGI_CLK (0x7U << GPTIM_SMCR_SMS_Pos) + + +#define FL_GPTIM_DMA_BURST_LENGTH_1 (0x0U << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_2 (0x1U << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_3 (0x2U << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_4 (0x3U << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_5 (0x4U << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_6 (0x5U << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_7 (0x6U << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_8 (0x7U << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_9 (0x8U << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_10 (0x9U << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_11 (0xaU << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_12 (0xbU << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_13 (0xcU << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_14 (0xdU << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_15 (0xeU << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_16 (0xfU << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_17 (0x10U << GPTIM_DCR_DBL_Pos) +#define FL_GPTIM_DMA_BURST_LENGTH_18 (0x11U << GPTIM_DCR_DBL_Pos) + + +#define FL_GPTIM_DMA_BURST_ADDR_CR1 (0x0U << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_CR2 (0x1U << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_SMCR (0x2U << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_DIER (0x3U << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_SR (0x4U << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_EGR (0x5U << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_CCMR1 (0x6U << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_CCMR2 (0x7U << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_CCER (0x8U << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_CNT (0x9U << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_PSC (0xaU << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_ARR (0xbU << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_RCR (0xcU << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_CCR1 (0xdU << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_CCR2 (0xeU << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_CCR3 (0xfU << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_CCR4 (0x10U << GPTIM_DCR_DBA_Pos) +#define FL_GPTIM_DMA_BURST_ADDR_BDTR (0x11U << GPTIM_DCR_DBA_Pos) + + +#define FL_GPTIM_ITRSEL_GROUP0 (0x0U << GPTIM_ITRSEL_Pos) +#define FL_GPTIM_ITRSEL_GROUP1 (0x1U << GPTIM_ITRSEL_Pos) +#define FL_GPTIM_ITRSEL_GROUP2 (0x2U << GPTIM_ITRSEL_Pos) +#define FL_GPTIM_ITRSEL_GROUP3 (0x3U << GPTIM_ITRSEL_Pos) + + +#define FL_GPTIM_OC_MODE_FROZEN (0x0U << GPTIM_CCMR_OCM_Pos) +#define FL_GPTIM_OC_MODE_ACTIVE (0x1U << GPTIM_CCMR_OCM_Pos) +#define FL_GPTIM_OC_MODE_INACTIVE (0x2U << GPTIM_CCMR_OCM_Pos) +#define FL_GPTIM_OC_MODE_TOGGLE (0x3U << GPTIM_CCMR_OCM_Pos) +#define FL_GPTIM_OC_MODE_FORCED_INACTIVE (0x4U << GPTIM_CCMR_OCM_Pos) +#define FL_GPTIM_OC_MODE_FORCED_ACTIVE (0x5U << GPTIM_CCMR_OCM_Pos) +#define FL_GPTIM_OC_MODE_PWM1 (0x6U << GPTIM_CCMR_OCM_Pos) +#define FL_GPTIM_OC_MODE_PWM2 (0x7U << GPTIM_CCMR_OCM_Pos) + + +#define FL_GPTIM_IC_FILTER_DIV1 (0x0U << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV1_N2 (0x1U << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV1_N4 (0x2U << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV1_N8 (0x3U << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV2_N6 (0x4U << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV2_N8 (0x5U << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV4_N6 (0x6U << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV4_N8 (0x7U << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV8_N6 (0x8U << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV8_N8 (0x9U << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV16_N5 (0xaU << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV16_N6 (0xbU << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV16_N8 (0xcU << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV32_N5 (0xdU << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV32_N6 (0xeU << GPTIM_CCMR_ICF_Pos) +#define FL_GPTIM_IC_FILTER_DIV32_N8 (0xfU << GPTIM_CCMR_ICF_Pos) + + +#define FL_GPTIM_IC_PSC_DIV1 (0x0U << GPTIM_CCMR_ICPSC_Pos) +#define FL_GPTIM_IC_PSC_DIV2 (0x1U << GPTIM_CCMR_ICPSC_Pos) +#define FL_GPTIM_IC_PSC_DIV4 (0x2U << GPTIM_CCMR_ICPSC_Pos) +#define FL_GPTIM_IC_PSC_DIV8 (0x3U << GPTIM_CCMR_ICPSC_Pos) + + +#define FL_GPTIM_CHANNEL_MODE_OUTPUT (0x0U << GPTIM_CCMR_CCS_Pos) +#define FL_GPTIM_CHANNEL_MODE_INPUT_NORMAL (0x1U << GPTIM_CCMR_CCS_Pos) +#define FL_GPTIM_CHANNEL_MODE_INPUT_CROSSOVER (0x2U << GPTIM_CCMR_CCS_Pos) +#define FL_GPTIM_CHANNEL_MODE_INPUT_TRC (0x3U << GPTIM_CCMR_CCS_Pos) + + +#define FL_GPTIM_OC_POLARITY_NORMAL (0x0U << GPTIM_CCER_CCOP_Pos) +#define FL_GPTIM_OC_POLARITY_INVERT (0x1U << GPTIM_CCER_CCOP_Pos) + + +#define FL_GPTIM_IC_POLARITY_NORMAL (0x0U << GPTIM_CCER_CCIP_Pos) +#define FL_GPTIM_IC_POLARITY_INVERT (0x1U << GPTIM_CCER_CCIP_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup GPTIM_FL_Exported_Functions GPTIM Exported Functions + * @{ + */ + +/** + * @brief + * @rmtoll CR1 CKD FL_GPTIM_SetClockDivision + * @param TIMx TIM instance + * @param div This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CLK_DIVISION_DIV1 + * @arg @ref FL_GPTIM_CLK_DIVISION_DIV2 + * @arg @ref FL_GPTIM_CLK_DIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_SetClockDivision(GPTIM_Type *TIMx, uint32_t div) +{ + MODIFY_REG(TIMx->CR1, GPTIM_CR1_CKD_Msk, div); +} + +/** + * @brief + * @rmtoll CR1 CKD FL_GPTIM_GetClockDivision + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_CLK_DIVISION_DIV1 + * @arg @ref FL_GPTIM_CLK_DIVISION_DIV2 + * @arg @ref FL_GPTIM_CLK_DIVISION_DIV4 + */ +__STATIC_INLINE uint32_t FL_GPTIM_GetClockDivision(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, GPTIM_CR1_CKD_Msk)); +} + +/** + * @brief + * @rmtoll CR1 ARPE FL_GPTIM_EnableARRPreload + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_EnableARRPreload(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->CR1, GPTIM_CR1_ARPE_Msk); +} + +/** + * @brief + * @rmtoll CR1 ARPE FL_GPTIM_IsEnabledARRPreload + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabledARRPreload(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, GPTIM_CR1_ARPE_Msk) == GPTIM_CR1_ARPE_Msk); +} + +/** + * @brief + * @rmtoll CR1 ARPE FL_GPTIM_DisableARRPreload + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_DisableARRPreload(GPTIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->CR1, GPTIM_CR1_ARPE_Msk); +} + +/** + * @brief + * @rmtoll CR1 CMS FL_GPTIM_SetCounterAlignedMode + * @param TIMx TIM instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_GPTIM_COUNTER_ALIGNED_EDGE + * @arg @ref FL_GPTIM_COUNTER_ALIGNED_CENTER_DOWN + * @arg @ref FL_GPTIM_COUNTER_ALIGNED_CENTER_UP + * @arg @ref FL_GPTIM_COUNTER_ALIGNED_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_SetCounterAlignedMode(GPTIM_Type *TIMx, uint32_t mode) +{ + MODIFY_REG(TIMx->CR1, GPTIM_CR1_CMS_Msk, mode); +} + +/** + * @brief + * @rmtoll CR1 CMS FL_GPTIM_GetCounterAlignedMode + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_COUNTER_ALIGNED_EDGE + * @arg @ref FL_GPTIM_COUNTER_ALIGNED_CENTER_DOWN + * @arg @ref FL_GPTIM_COUNTER_ALIGNED_CENTER_UP + * @arg @ref FL_GPTIM_COUNTER_ALIGNED_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t FL_GPTIM_GetCounterAlignedMode(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, GPTIM_CR1_CMS_Msk)); +} + +/** + * @brief + * @rmtoll CR1 DIR FL_GPTIM_SetCounterDirection + * @param TIMx TIM instance + * @param dir This parameter can be one of the following values: + * @arg @ref FL_GPTIM_COUNTER_DIR_UP + * @arg @ref FL_GPTIM_COUNTER_DIR_DOWN + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_SetCounterDirection(GPTIM_Type *TIMx, uint32_t dir) +{ + MODIFY_REG(TIMx->CR1, GPTIM_CR1_DIR_Msk, dir); +} + +/** + * @brief + * @rmtoll CR1 DIR FL_GPTIM_GetCounterDirection + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_COUNTER_DIR_UP + * @arg @ref FL_GPTIM_COUNTER_DIR_DOWN + */ +__STATIC_INLINE uint32_t FL_GPTIM_GetCounterDirection(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, GPTIM_CR1_DIR_Msk)); +} + +/** + * @brief + * @rmtoll CR1 OPM FL_GPTIM_SetOnePulseMode + * @param TIMx TIM instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_GPTIM_ONE_PULSE_MODE_CONTINUOUS + * @arg @ref FL_GPTIM_ONE_PULSE_MODE_SINGLE + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_SetOnePulseMode(GPTIM_Type *TIMx, uint32_t mode) +{ + MODIFY_REG(TIMx->CR1, GPTIM_CR1_OPM_Msk, mode); +} + +/** + * @brief + * @rmtoll CR1 OPM FL_GPTIM_GetOnePulseMode + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_ONE_PULSE_MODE_CONTINUOUS + * @arg @ref FL_GPTIM_ONE_PULSE_MODE_SINGLE + */ +__STATIC_INLINE uint32_t FL_GPTIM_GetOnePulseMode(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, GPTIM_CR1_OPM_Msk)); +} + +/** + * @brief + * @rmtoll CR1 URS FL_GPTIM_SetUpdateSource + * @param TIMx TIM instance + * @param source This parameter can be one of the following values: + * @arg @ref FL_GPTIM_UPDATE_SOURCE_REGULAR + * @arg @ref FL_GPTIM_UPDATE_SOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_SetUpdateSource(GPTIM_Type *TIMx, uint32_t source) +{ + MODIFY_REG(TIMx->CR1, GPTIM_CR1_URS_Msk, source); +} + +/** + * @brief + * @rmtoll CR1 URS FL_GPTIM_GetUpdateSource + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_UPDATE_SOURCE_REGULAR + * @arg @ref FL_GPTIM_UPDATE_SOURCE_COUNTER + */ +__STATIC_INLINE uint32_t FL_GPTIM_GetUpdateSource(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, GPTIM_CR1_URS_Msk)); +} + +/** + * @brief + * @rmtoll CR1 UDIS FL_GPTIM_EnableUpdateEvent + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_EnableUpdateEvent(GPTIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->CR1, GPTIM_CR1_UDIS_Msk); +} + +/** + * @brief + * @rmtoll CR1 UDIS FL_GPTIM_IsEnabledUpdateEvent + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabledUpdateEvent(GPTIM_Type *TIMx) +{ + return (uint32_t)!(READ_BIT(TIMx->CR1, GPTIM_CR1_UDIS_Msk) == GPTIM_CR1_UDIS_Msk); +} + +/** + * @brief + * @rmtoll CR1 UDIS FL_GPTIM_DisableUpdateEvent + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_DisableUpdateEvent(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->CR1, GPTIM_CR1_UDIS_Msk); +} + +/** + * @brief + * @rmtoll CR1 CEN FL_GPTIM_Enable + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_Enable(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->CR1, GPTIM_CR1_CEN_Msk); +} + +/** + * @brief + * @rmtoll CR1 CEN FL_GPTIM_IsEnabled + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabled(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, GPTIM_CR1_CEN_Msk) == GPTIM_CR1_CEN_Msk); +} + +/** + * @brief + * @rmtoll CR1 CEN FL_GPTIM_Disable + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_Disable(GPTIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->CR1, GPTIM_CR1_CEN_Msk); +} + +/** + * @brief + * @rmtoll CR2 TI1S FL_GPTIM_IC_EnableXORCombination + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_IC_EnableXORCombination(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->CR2, GPTIM_CR2_TI1S_Msk); +} + +/** + * @brief + * @rmtoll CR2 TI1S FL_GPTIM_IC_IsEnabledXORCombination + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IC_IsEnabledXORCombination(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, GPTIM_CR2_TI1S_Msk) == GPTIM_CR2_TI1S_Msk); +} + +/** + * @brief + * @rmtoll CR2 TI1S FL_GPTIM_IC_DisableXORCombination + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_IC_DisableXORCombination(GPTIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->CR2, GPTIM_CR2_TI1S_Msk); +} + +/** + * @brief + * @rmtoll CR2 MMS FL_GPTIM_SetTriggerOutput + * @param TIMx TIM instance + * @param triggerOutput This parameter can be one of the following values: + * @arg @ref FL_GPTIM_TRGO_RESET + * @arg @ref FL_GPTIM_TRGO_ENABLE + * @arg @ref FL_GPTIM_TRGO_UPDATE + * @arg @ref FL_GPTIM_TRGO_CC1IF + * @arg @ref FL_GPTIM_TRGO_OC1REF + * @arg @ref FL_GPTIM_TRGO_OC2REF + * @arg @ref FL_GPTIM_TRGO_OC3REF + * @arg @ref FL_GPTIM_TRGO_OC4REF + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_SetTriggerOutput(GPTIM_Type *TIMx, uint32_t triggerOutput) +{ + MODIFY_REG(TIMx->CR2, GPTIM_CR2_MMS_Msk, triggerOutput); +} + +/** + * @brief + * @rmtoll CR2 MMS FL_GPTIM_GetTriggerOutput + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_TRGO_RESET + * @arg @ref FL_GPTIM_TRGO_ENABLE + * @arg @ref FL_GPTIM_TRGO_UPDATE + * @arg @ref FL_GPTIM_TRGO_CC1IF + * @arg @ref FL_GPTIM_TRGO_OC1REF + * @arg @ref FL_GPTIM_TRGO_OC2REF + * @arg @ref FL_GPTIM_TRGO_OC3REF + * @arg @ref FL_GPTIM_TRGO_OC4REF + */ +__STATIC_INLINE uint32_t FL_GPTIM_GetTriggerOutput(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, GPTIM_CR2_MMS_Msk)); +} + +/** + * @brief + * @rmtoll CR2 CCDS FL_GPTIM_CC_SetDMAReqTrigger + * @param TIMx TIM instance + * @param trigger This parameter can be one of the following values: + * @arg @ref FL_GPTIM_DMA_REQ_CC + * @arg @ref FL_GPTIM_DMA_REQ_UPDATE + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_CC_SetDMAReqTrigger(GPTIM_Type *TIMx, uint32_t trigger) +{ + MODIFY_REG(TIMx->CR2, GPTIM_CR2_CCDS_Msk, trigger); +} + +/** + * @brief + * @rmtoll CR2 CCDS FL_GPTIM_CC_GetDMAReqTrigger + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_DMA_REQ_CC + * @arg @ref FL_GPTIM_DMA_REQ_UPDATE + */ +__STATIC_INLINE uint32_t FL_GPTIM_CC_GetDMAReqTrigger(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, GPTIM_CR2_CCDS_Msk)); +} + +/** + * @brief + * @rmtoll SMCR ETP FL_GPTIM_SetETRPolarity + * @param TIMx TIM instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_GPTIM_ETR_POLARITY_NORMAL + * @arg @ref FL_GPTIM_ETR_POLARITY_INVERT + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_SetETRPolarity(GPTIM_Type *TIMx, uint32_t polarity) +{ + MODIFY_REG(TIMx->SMCR, GPTIM_SMCR_ETP_Msk, polarity); +} + +/** + * @brief + * @rmtoll SMCR ETP FL_GPTIM_GetETRPolarity + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_ETR_POLARITY_NORMAL + * @arg @ref FL_GPTIM_ETR_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_GPTIM_GetETRPolarity(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, GPTIM_SMCR_ETP_Msk)); +} + +/** + * @brief + * @rmtoll SMCR ECE FL_GPTIM_EnableExternalClock + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_EnableExternalClock(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->SMCR, GPTIM_SMCR_ECE_Msk); +} + +/** + * @brief + * @rmtoll SMCR ECE FL_GPTIM_IsEnabledExternalClock + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabledExternalClock(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, GPTIM_SMCR_ECE_Msk) == GPTIM_SMCR_ECE_Msk); +} + +/** + * @brief + * @rmtoll SMCR ECE FL_GPTIM_DisableExternalClock + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_DisableExternalClock(GPTIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, GPTIM_SMCR_ECE_Msk); +} + +/** + * @brief + * @rmtoll SMCR ETPS FL_GPTIM_SetETRPrescaler + * @param TIMx TIM instance + * @param psc This parameter can be one of the following values: + * @arg @ref FL_GPTIM_ETR_PSC_DIV1 + * @arg @ref FL_GPTIM_ETR_PSC_DIV2 + * @arg @ref FL_GPTIM_ETR_PSC_DIV4 + * @arg @ref FL_GPTIM_ETR_PSC_DIV8 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_SetETRPrescaler(GPTIM_Type *TIMx, uint32_t psc) +{ + MODIFY_REG(TIMx->SMCR, GPTIM_SMCR_ETPS_Msk, psc); +} + +/** + * @brief + * @rmtoll SMCR ETPS FL_GPTIM_GetETRPrescaler + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_ETR_PSC_DIV1 + * @arg @ref FL_GPTIM_ETR_PSC_DIV2 + * @arg @ref FL_GPTIM_ETR_PSC_DIV4 + * @arg @ref FL_GPTIM_ETR_PSC_DIV8 + */ +__STATIC_INLINE uint32_t FL_GPTIM_GetETRPrescaler(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, GPTIM_SMCR_ETPS_Msk)); +} + +/** + * @brief + * @rmtoll SMCR ETF FL_GPTIM_SetETRFilter + * @param TIMx TIM instance + * @param filter This parameter can be one of the following values: + * @arg @ref FL_GPTIM_ETR_FILTER_DIV1 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV1_N2 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV1_N4 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV1_N8 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV2_N6 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV2_N8 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV4_N6 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV4_N8 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV8_N6 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV8_N8 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV16_N5 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV16_N6 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV16_N8 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV32_N5 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV32_N6 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV32_N8 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_SetETRFilter(GPTIM_Type *TIMx, uint32_t filter) +{ + MODIFY_REG(TIMx->SMCR, GPTIM_SMCR_ETF_Msk, filter); +} + +/** + * @brief + * @rmtoll SMCR ETF FL_GPTIM_GetETRFilter + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_ETR_FILTER_DIV1 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV1_N2 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV1_N4 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV1_N8 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV2_N6 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV2_N8 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV4_N6 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV4_N8 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV8_N6 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV8_N8 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV16_N5 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV16_N6 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV16_N8 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV32_N5 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV32_N6 + * @arg @ref FL_GPTIM_ETR_FILTER_DIV32_N8 + */ +__STATIC_INLINE uint32_t FL_GPTIM_GetETRFilter(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, GPTIM_SMCR_ETF_Msk)); +} + +/** + * @brief + * @rmtoll SMCR MSM FL_GPTIM_EnableMasterSlaveMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_EnableMasterSlaveMode(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->SMCR, GPTIM_SMCR_MSM_Msk); +} + +/** + * @brief + * @rmtoll SMCR MSM FL_GPTIM_IsEnabledMasterSlaveMode + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabledMasterSlaveMode(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, GPTIM_SMCR_MSM_Msk) == GPTIM_SMCR_MSM_Msk); +} + +/** + * @brief + * @rmtoll SMCR MSM FL_GPTIM_DisableMasterSlaveMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_DisableMasterSlaveMode(GPTIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, GPTIM_SMCR_MSM_Msk); +} + +/** + * @brief + * @rmtoll SMCR TS FL_GPTIM_SetTriggerInput + * @param TIMx TIM instance + * @param triggerInput This parameter can be one of the following values: + * @arg @ref FL_GPTIM_TIM_TS_ITR0 + * @arg @ref FL_GPTIM_TIM_TS_ITR1 + * @arg @ref FL_GPTIM_TIM_TS_ITR2 + * @arg @ref FL_GPTIM_TIM_TS_ITR3 + * @arg @ref FL_GPTIM_TIM_TS_TI1F_ED + * @arg @ref FL_GPTIM_TIM_TS_TI1FP1 + * @arg @ref FL_GPTIM_TIM_TS_TI2FP2 + * @arg @ref FL_GPTIM_TIM_TS_ETRF + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_SetTriggerInput(GPTIM_Type *TIMx, uint32_t triggerInput) +{ + MODIFY_REG(TIMx->SMCR, GPTIM_SMCR_TS_Msk, triggerInput); +} + +/** + * @brief + * @rmtoll SMCR TS FL_GPTIM_GetTriggerInput + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_TIM_TS_ITR0 + * @arg @ref FL_GPTIM_TIM_TS_ITR1 + * @arg @ref FL_GPTIM_TIM_TS_ITR2 + * @arg @ref FL_GPTIM_TIM_TS_ITR3 + * @arg @ref FL_GPTIM_TIM_TS_TI1F_ED + * @arg @ref FL_GPTIM_TIM_TS_TI1FP1 + * @arg @ref FL_GPTIM_TIM_TS_TI2FP2 + * @arg @ref FL_GPTIM_TIM_TS_ETRF + */ +__STATIC_INLINE uint32_t FL_GPTIM_GetTriggerInput(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, GPTIM_SMCR_TS_Msk)); +} + +/** + * @brief + * @rmtoll SMCR SMS FL_GPTIM_SetSlaveMode + * @param TIMx TIM instance + * @param encoderMode This parameter can be one of the following values: + * @arg @ref FL_GPTIM_SLAVE_MODE_PROHIBITED + * @arg @ref FL_GPTIM_SLAVE_MODE_ENCODER_X2_TI1 + * @arg @ref FL_GPTIM_SLAVE_MODE_ENCODER_X2_TI2 + * @arg @ref FL_GPTIM_SLAVE_MODE_ENCODER_X4_TI1TI2 + * @arg @ref FL_GPTIM_SLAVE_MODE_TRGI_RISE_RST + * @arg @ref FL_GPTIM_SLAVE_MODE_TRGI_HIGH_RUN + * @arg @ref FL_GPTIM_SLAVE_MODE_TRGI_RISE_RUN + * @arg @ref FL_GPTIM_SLAVE_MODE_TRGI_CLK + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_SetSlaveMode(GPTIM_Type *TIMx, uint32_t encoderMode) +{ + MODIFY_REG(TIMx->SMCR, GPTIM_SMCR_SMS_Msk, encoderMode); +} + +/** + * @brief + * @rmtoll SMCR SMS FL_GPTIM_GetSlaveMode + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_SLAVE_MODE_PROHIBITED + * @arg @ref FL_GPTIM_SLAVE_MODE_ENCODER_X2_TI1 + * @arg @ref FL_GPTIM_SLAVE_MODE_ENCODER_X2_TI2 + * @arg @ref FL_GPTIM_SLAVE_MODE_ENCODER_X4_TI1TI2 + * @arg @ref FL_GPTIM_SLAVE_MODE_TRGI_RISE_RST + * @arg @ref FL_GPTIM_SLAVE_MODE_TRGI_HIGH_RUN + * @arg @ref FL_GPTIM_SLAVE_MODE_TRGI_RISE_RUN + * @arg @ref FL_GPTIM_SLAVE_MODE_TRGI_CLK + */ +__STATIC_INLINE uint32_t FL_GPTIM_GetSlaveMode(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, GPTIM_SMCR_SMS_Msk)); +} + +/** + * @brief + * @rmtoll DIER CC1BURSTEN FL_GPTIM_EnableCC1DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_EnableCC1DMABurstMode(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, GPTIM_DIER_CC1BURSTEN_Msk); +} + +/** + * @brief + * @rmtoll DIER CC1BURSTEN FL_GPTIM_IsEnabledCC1DMABurstMode + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabledCC1DMABurstMode(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, GPTIM_DIER_CC1BURSTEN_Msk) == GPTIM_DIER_CC1BURSTEN_Msk); +} + +/** + * @brief + * @rmtoll DIER CC1BURSTEN FL_GPTIM_DisableCC1DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_DisableCC1DMABurstMode(GPTIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, GPTIM_DIER_CC1BURSTEN_Msk); +} + +/** + * @brief + * @rmtoll DIER CC2BURSTEN FL_GPTIM_EnableCC2DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_EnableCC2DMABurstMode(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, GPTIM_DIER_CC2BURSTEN_Msk); +} + +/** + * @brief + * @rmtoll DIER CC2BURSTEN FL_GPTIM_IsEnabledCC2DMABurstMode + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabledCC2DMABurstMode(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, GPTIM_DIER_CC2BURSTEN_Msk) == GPTIM_DIER_CC2BURSTEN_Msk); +} + +/** + * @brief + * @rmtoll DIER CC2BURSTEN FL_GPTIM_DisableCC2DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_DisableCC2DMABurstMode(GPTIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, GPTIM_DIER_CC2BURSTEN_Msk); +} + +/** + * @brief + * @rmtoll DIER CC3BURSTEN FL_GPTIM_EnableCC3DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_EnableCC3DMABurstMode(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, GPTIM_DIER_CC3BURSTEN_Msk); +} + +/** + * @brief + * @rmtoll DIER CC3BURSTEN FL_GPTIM_IsEnabledCC3DMABurstMode + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabledCC3DMABurstMode(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, GPTIM_DIER_CC3BURSTEN_Msk) == GPTIM_DIER_CC3BURSTEN_Msk); +} + +/** + * @brief + * @rmtoll DIER CC3BURSTEN FL_GPTIM_DisableCC3DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_DisableCC3DMABurstMode(GPTIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, GPTIM_DIER_CC3BURSTEN_Msk); +} + +/** + * @brief + * @rmtoll DIER CC4BURSTEN FL_GPTIM_EnableCC4DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_EnableCC4DMABurstMode(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, GPTIM_DIER_CC4BURSTEN_Msk); +} + +/** + * @brief + * @rmtoll DIER CC4BURSTEN FL_GPTIM_IsEnabledCC4DMABurstMode + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabledCC4DMABurstMode(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, GPTIM_DIER_CC4BURSTEN_Msk) == GPTIM_DIER_CC4BURSTEN_Msk); +} + +/** + * @brief + * @rmtoll DIER CC4BURSTEN FL_GPTIM_DisableCC4DMABurstMode + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_DisableCC4DMABurstMode(GPTIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, GPTIM_DIER_CC4BURSTEN_Msk); +} + +/** + * @brief + * @rmtoll DIER TDE FL_GPTIM_EnableDMAReq_Trigger + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_EnableDMAReq_Trigger(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, GPTIM_DIER_TDE_Msk); +} + +/** + * @brief + * @rmtoll DIER TDE FL_GPTIM_IsEnabledDMAReq_Trigger + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabledDMAReq_Trigger(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, GPTIM_DIER_TDE_Msk) == GPTIM_DIER_TDE_Msk); +} + +/** + * @brief + * @rmtoll DIER TDE FL_GPTIM_DisableDMAReq_Trigger + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_DisableDMAReq_Trigger(GPTIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, GPTIM_DIER_TDE_Msk); +} + +/** + * @brief + * @rmtoll DIER CCDE FL_GPTIM_EnableDMAReq_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_EnableDMAReq_CC(GPTIM_Type *TIMx, uint32_t channel) +{ + SET_BIT(TIMx->DIER, ((channel & 0xf) << 0x9U)); +} + +/** + * @brief + * @rmtoll DIER CCDE FL_GPTIM_IsEnabledDMAReq_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabledDMAReq_CC(GPTIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, ((channel & 0xf) << 0x9U)) == ((channel & 0xf) << 0x9U)); +} + +/** + * @brief + * @rmtoll DIER CCDE FL_GPTIM_DisableDMAReq_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_DisableDMAReq_CC(GPTIM_Type *TIMx, uint32_t channel) +{ + CLEAR_BIT(TIMx->DIER, ((channel & 0xf) << 0x9U)); +} + +/** + * @brief + * @rmtoll DIER UDE FL_GPTIM_EnableDMAReq_Update + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_EnableDMAReq_Update(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, GPTIM_DIER_UDE_Msk); +} + +/** + * @brief + * @rmtoll DIER UDE FL_GPTIM_IsEnabledDMAReq_Update + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabledDMAReq_Update(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, GPTIM_DIER_UDE_Msk) == GPTIM_DIER_UDE_Msk); +} + +/** + * @brief + * @rmtoll DIER UDE FL_GPTIM_DisableDMAReq_Update + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_DisableDMAReq_Update(GPTIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, GPTIM_DIER_UDE_Msk); +} + +/** + * @brief + * @rmtoll DIER TIE FL_GPTIM_EnableIT_Trigger + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_EnableIT_Trigger(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, GPTIM_DIER_TIE_Msk); +} + +/** + * @brief + * @rmtoll DIER TIE FL_GPTIM_IsEnabledIT_Trigger + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabledIT_Trigger(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, GPTIM_DIER_TIE_Msk) == GPTIM_DIER_TIE_Msk); +} + +/** + * @brief + * @rmtoll DIER TIE FL_GPTIM_DisableIT_Trigger + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_DisableIT_Trigger(GPTIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, GPTIM_DIER_TIE_Msk); +} + +/** + * @brief + * @rmtoll DIER CCIE FL_GPTIM_EnableIT_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_EnableIT_CC(GPTIM_Type *TIMx, uint32_t channel) +{ + SET_BIT(TIMx->DIER, ((channel & 0xf) << 0x1U)); +} + +/** + * @brief + * @rmtoll DIER CCIE FL_GPTIM_IsEnabledIT_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabledIT_CC(GPTIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, ((channel & 0xf) << 0x1U)) == ((channel & 0xf) << 0x1U)); +} + +/** + * @brief + * @rmtoll DIER CCIE FL_GPTIM_DisableIT_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_DisableIT_CC(GPTIM_Type *TIMx, uint32_t channel) +{ + CLEAR_BIT(TIMx->DIER, ((channel & 0xf) << 0x1U)); +} + +/** + * @brief + * @rmtoll DIER UIE FL_GPTIM_EnableIT_Update + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_EnableIT_Update(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->DIER, GPTIM_DIER_UIE_Msk); +} + +/** + * @brief + * @rmtoll DIER UIE FL_GPTIM_IsEnabledIT_Update + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsEnabledIT_Update(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DIER, GPTIM_DIER_UIE_Msk) == GPTIM_DIER_UIE_Msk); +} + +/** + * @brief + * @rmtoll DIER UIE FL_GPTIM_DisableIT_Update + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_DisableIT_Update(GPTIM_Type *TIMx) +{ + CLEAR_BIT(TIMx->DIER, GPTIM_DIER_UIE_Msk); +} + +/** + * @brief + * @rmtoll ISR CCOF FL_GPTIM_IsActiveFlag_CCOverflow + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsActiveFlag_CCOverflow(GPTIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->ISR, ((channel & 0xf) << 0x9U)) == ((channel & 0xf) << 0x9U)); +} + +/** + * @brief + * @rmtoll ISR CCOF FL_GPTIM_ClearFlag_CCOverflow + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_ClearFlag_CCOverflow(GPTIM_Type *TIMx, uint32_t channel) +{ + WRITE_REG(TIMx->ISR, ((channel & 0xf) << 0x9U)); +} + +/** + * @brief + * @rmtoll ISR TIF FL_GPTIM_IsActiveFlag_Trigger + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsActiveFlag_Trigger(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ISR, GPTIM_ISR_TIF_Msk) == (GPTIM_ISR_TIF_Msk)); +} + +/** + * @brief + * @rmtoll ISR TIF FL_GPTIM_ClearFlag_Trigger + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_ClearFlag_Trigger(GPTIM_Type *TIMx) +{ + WRITE_REG(TIMx->ISR, GPTIM_ISR_TIF_Msk); +} + +/** + * @brief + * @rmtoll ISR CCIF FL_GPTIM_IsActiveFlag_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsActiveFlag_CC(GPTIM_Type *TIMx, uint32_t channel) +{ + return (uint32_t)(READ_BIT(TIMx->ISR, ((channel & 0xf) << 0x1U)) == ((channel & 0xf) << 0x1U)); +} + +/** + * @brief + * @rmtoll ISR CCIF FL_GPTIM_ClearFlag_CC + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_ClearFlag_CC(GPTIM_Type *TIMx, uint32_t channel) +{ + WRITE_REG(TIMx->ISR, ((channel & 0xf) << 0x1U)); +} + +/** + * @brief + * @rmtoll ISR UIF FL_GPTIM_IsActiveFlag_Update + * @param TIMx TIM instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IsActiveFlag_Update(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ISR, GPTIM_ISR_UIF_Msk) == (GPTIM_ISR_UIF_Msk)); +} + +/** + * @brief + * @rmtoll ISR UIF FL_GPTIM_ClearFlag_Update + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_ClearFlag_Update(GPTIM_Type *TIMx) +{ + WRITE_REG(TIMx->ISR, GPTIM_ISR_UIF_Msk); +} + +/** + * @brief + * @rmtoll EGR TG FL_GPTIM_GenerateTriggerEvent + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_GenerateTriggerEvent(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->EGR, GPTIM_EGR_TG_Msk); +} + +/** + * @brief + * @rmtoll EGR CCG FL_GPTIM_GenerateCCEvent + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_GenerateCCEvent(GPTIM_Type *TIMx, uint32_t channel) +{ + SET_BIT(TIMx->EGR, ((channel & 0x3) << 0x1U)); +} + +/** + * @brief + * @rmtoll EGR UG FL_GPTIM_GenerateUpdateEvent + * @param TIMx TIM instance + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_GenerateUpdateEvent(GPTIM_Type *TIMx) +{ + SET_BIT(TIMx->EGR, GPTIM_EGR_UG_Msk); +} + +/** + * @brief + * @rmtoll CNT FL_GPTIM_WriteCounter + * @param TIMx TIM instance + * @param counter + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_WriteCounter(GPTIM_Type *TIMx, uint32_t counter) +{ + MODIFY_REG(TIMx->CNT, (0xffffU << 0U), (counter << 0U)); +} + +/** + * @brief + * @rmtoll CNT FL_GPTIM_ReadCounter + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_GPTIM_ReadCounter(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CNT, 0xffffU) >> 0U); +} + +/** + * @brief + * @rmtoll PSC FL_GPTIM_WritePrescaler + * @param TIMx TIM instance + * @param psc + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_WritePrescaler(GPTIM_Type *TIMx, uint32_t psc) +{ + MODIFY_REG(TIMx->PSC, (0xffffU << 0U), (psc << 0U)); +} + +/** + * @brief + * @rmtoll PSC FL_GPTIM_ReadPrescaler + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_GPTIM_ReadPrescaler(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->PSC, 0xffffU) >> 0U); +} + +/** + * @brief + * @rmtoll ARR FL_GPTIM_WriteAutoReload + * @param TIMx TIM instance + * @param autoReload + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_WriteAutoReload(GPTIM_Type *TIMx, uint32_t autoReload) +{ + MODIFY_REG(TIMx->ARR, (0xffffU << 0U), (autoReload << 0U)); +} + +/** + * @brief + * @rmtoll ARR FL_GPTIM_ReadAutoReload + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_GPTIM_ReadAutoReload(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ARR, 0xffffU) >> 0U); +} + +/** + * @brief + * @rmtoll CCR1 FL_GPTIM_WriteCompareCH1 + * @param TIMx TIM instance + * @param compareValue + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_WriteCompareCH1(GPTIM_Type *TIMx, uint32_t compareValue) +{ + MODIFY_REG(TIMx->CCR1, (0xffffU << 0U), (compareValue << 0U)); +} + +/** + * @brief + * @rmtoll CCR1 FL_GPTIM_ReadCompareCH1 + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_GPTIM_ReadCompareCH1(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR1, 0xffffU) >> 0U); +} + +/** + * @brief + * @rmtoll CCR2 FL_GPTIM_WriteCompareCH2 + * @param TIMx TIM instance + * @param compareValue + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_WriteCompareCH2(GPTIM_Type *TIMx, uint32_t compareValue) +{ + MODIFY_REG(TIMx->CCR2, (0xffffU << 0U), (compareValue << 0U)); +} + +/** + * @brief + * @rmtoll CCR2 FL_GPTIM_ReadCompareCH2 + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_GPTIM_ReadCompareCH2(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR2, 0xffffU) >> 0U); +} + +/** + * @brief + * @rmtoll CCR3 FL_GPTIM_WriteCompareCH3 + * @param TIMx TIM instance + * @param compareValue + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_WriteCompareCH3(GPTIM_Type *TIMx, uint32_t compareValue) +{ + MODIFY_REG(TIMx->CCR3, (0xffffU << 0U), (compareValue << 0U)); +} + +/** + * @brief + * @rmtoll CCR3 FL_GPTIM_ReadCompareCH3 + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_GPTIM_ReadCompareCH3(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR3, 0xffffU) >> 0U); +} + +/** + * @brief + * @rmtoll CCR4 FL_GPTIM_WriteCompareCH4 + * @param TIMx TIM instance + * @param compareValue + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_WriteCompareCH4(GPTIM_Type *TIMx, uint32_t compareValue) +{ + MODIFY_REG(TIMx->CCR4, (0xffffU << 0U), (compareValue << 0U)); +} + +/** + * @brief + * @rmtoll CCR4 FL_GPTIM_ReadCompareCH4 + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_GPTIM_ReadCompareCH4(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR4, 0xffffU) >> 0U); +} + +/** + * @brief + * @rmtoll DCR DBL FL_GPTIM_SetDMABurstLength + * @param TIMx TIM instance + * @param length This parameter can be one of the following values: + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_1 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_2 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_3 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_4 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_5 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_6 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_7 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_8 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_9 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_10 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_11 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_12 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_13 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_14 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_15 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_16 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_17 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_18 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_SetDMABurstLength(GPTIM_Type *TIMx, uint32_t length) +{ + MODIFY_REG(TIMx->DCR, GPTIM_DCR_DBL_Msk, length); +} + +/** + * @brief + * @rmtoll DCR DBL FL_GPTIM_GetDMABurstLength + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_1 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_2 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_3 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_4 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_5 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_6 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_7 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_8 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_9 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_10 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_11 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_12 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_13 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_14 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_15 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_16 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_17 + * @arg @ref FL_GPTIM_DMA_BURST_LENGTH_18 + */ +__STATIC_INLINE uint32_t FL_GPTIM_GetDMABurstLength(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DCR, GPTIM_DCR_DBL_Msk)); +} + +/** + * @brief + * @rmtoll DCR DBA FL_GPTIM_SetDMABurstAddress + * @param TIMx TIM instance + * @param address This parameter can be one of the following values: + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CR1 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CR2 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_SMCR + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_DIER + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_SR + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_EGR + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CCMR1 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CCMR2 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CCER + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CNT + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_PSC + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_ARR + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_RCR + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CCR1 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CCR2 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CCR3 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CCR4 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_BDTR + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_SetDMABurstAddress(GPTIM_Type *TIMx, uint32_t address) +{ + MODIFY_REG(TIMx->DCR, GPTIM_DCR_DBA_Msk, address); +} + +/** + * @brief + * @rmtoll DCR DBA FL_GPTIM_GetDMABurstAddress + * @param TIMx TIM instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CR1 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CR2 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_SMCR + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_DIER + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_SR + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_EGR + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CCMR1 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CCMR2 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CCER + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CNT + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_PSC + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_ARR + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_RCR + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CCR1 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CCR2 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CCR3 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_CCR4 + * @arg @ref FL_GPTIM_DMA_BURST_ADDR_BDTR + */ +__STATIC_INLINE uint32_t FL_GPTIM_GetDMABurstAddress(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DCR, GPTIM_DCR_DBA_Msk)); +} + +/** + * @brief + * @rmtoll DMAR FL_GPTIM_WriteDMAAddress + * @param TIMx TIM instance + * @param address + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_WriteDMAAddress(GPTIM_Type *TIMx, uint32_t address) +{ + MODIFY_REG(TIMx->DMAR, (0xffffU << 0U), (address << 0U)); +} + +/** + * @brief + * @rmtoll DMAR FL_GPTIM_ReadDMAAddress + * @param TIMx TIM instance + * @retval + */ +__STATIC_INLINE uint32_t FL_GPTIM_ReadDMAAddress(GPTIM_Type *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DMAR, 0xffffU) >> 0U); +} + +/** + * @brief + * @rmtoll ITRSEL FL_GPTIM_SetITRInput + * @param TIMx TIM instance + * @param ITRx This parameter can be one of the following values: + * @arg @ref FL_GPTIM_ITR0 + * @arg @ref FL_GPTIM_ITR1 + * @arg @ref FL_GPTIM_ITR2 + * @arg @ref FL_GPTIM_ITR3 + * @param input This parameter can be one of the following values: + * @arg @ref FL_GPTIM_ITRSEL_GROUP0 + * @arg @ref FL_GPTIM_ITRSEL_GROUP1 + * @arg @ref FL_GPTIM_ITRSEL_GROUP2 + * @arg @ref FL_GPTIM_ITRSEL_GROUP3 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_SetITRInput(GPTIM_Type *TIMx, uint32_t ITRx, uint32_t input) +{ + MODIFY_REG(TIMx->ITRSEL, ((ITRx * ITRx) * GPTIM_ITRSEL), ((ITRx * ITRx) * input)); +} + +/** + * @brief + * @rmtoll ITRSEL FL_GPTIM_GetITRInput + * @param TIMx TIM instance + * @param ITRx This parameter can be one of the following values: + * @arg @ref FL_GPTIM_ITR0 + * @arg @ref FL_GPTIM_ITR1 + * @arg @ref FL_GPTIM_ITR2 + * @arg @ref FL_GPTIM_ITR3 + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_ITRSEL_GROUP0 + * @arg @ref FL_GPTIM_ITRSEL_GROUP1 + * @arg @ref FL_GPTIM_ITRSEL_GROUP2 + * @arg @ref FL_GPTIM_ITRSEL_GROUP3 + */ +__STATIC_INLINE uint32_t FL_GPTIM_GetITRInput(GPTIM_Type *TIMx, uint32_t ITRx) +{ + return (uint32_t)(READ_BIT(TIMx->ITRSEL, ((ITRx * ITRx) * GPTIM_ITRSEL)) / (ITRx * ITRx)); +} + +/** + * @brief OCx clear enable + * @rmtoll CCMR OCCE FL_GPTIM_OC_EnableClear + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_OC_EnableClear(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + MODIFY_REG(TIMx->CCMR1, (0x1U << 7U), (0x1U << 7U)); + break; + case FL_GPTIM_CHANNEL_2: + MODIFY_REG(TIMx->CCMR1, (0x1U << 15U), (0x1U << 15U)); + break; + case FL_GPTIM_CHANNEL_3: + MODIFY_REG(TIMx->CCMR2, (0x1U << 7U), (0x1U << 7U)); + break; + case FL_GPTIM_CHANNEL_4: + MODIFY_REG(TIMx->CCMR2, (0x1U << 15U), (0x1U << 15U)); + break; + } +} + +/** + * @brief Get OCx Clear enable status + * @rmtoll CCMR OCCE FL_GPTIM_OC_IsEnabledClear + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_OC_IsEnabledClear(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + return (uint32_t)(READ_BIT(TIMx->CCMR1, (0x1U << 7U)) >> 7U); + case FL_GPTIM_CHANNEL_2: + return (uint32_t)(READ_BIT(TIMx->CCMR1, (0x1U << 15U)) >> 15U); + case FL_GPTIM_CHANNEL_3: + return (uint32_t)(READ_BIT(TIMx->CCMR2, (0x1U << 7U)) >> 7U); + case FL_GPTIM_CHANNEL_4: + return (uint32_t)(READ_BIT(TIMx->CCMR2, (0x1U << 15U)) >> 15U); + default: + return 0; + } +} + +/** + * @brief OCx clear disable + * @rmtoll CCMR OCCE FL_GPTIM_OC_DisableClear + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_OC_DisableClear(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + CLEAR_BIT(TIMx->CCMR1, (0x1U << 7U)); + break; + case FL_GPTIM_CHANNEL_2: + CLEAR_BIT(TIMx->CCMR1, (0x1U << 15U)); + break; + case FL_GPTIM_CHANNEL_3: + CLEAR_BIT(TIMx->CCMR2, (0x1U << 7U)); + break; + case FL_GPTIM_CHANNEL_4: + CLEAR_BIT(TIMx->CCMR2, (0x1U << 15U)); + break; + } +} + +/** + * @brief Set OCx mode + * @rmtoll CCMR OCM FL_GPTIM_OC_SetMode + * @param TIMx TIM instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_GPTIM_OC_MODE_FROZEN + * @arg @ref FL_GPTIM_OC_MODE_ACTIVE + * @arg @ref FL_GPTIM_OC_MODE_INACTIVE + * @arg @ref FL_GPTIM_OC_MODE_TOGGLE + * @arg @ref FL_GPTIM_OC_MODE_FORCED_INACTIVE + * @arg @ref FL_GPTIM_OC_MODE_FORCED_ACTIVE + * @arg @ref FL_GPTIM_OC_MODE_PWM1 + * @arg @ref FL_GPTIM_OC_MODE_PWM2 + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_OC_SetMode(GPTIM_Type *TIMx, uint32_t mode, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + MODIFY_REG(TIMx->CCMR1, (0x7U << 4U), (mode)); + break; + case FL_GPTIM_CHANNEL_2: + MODIFY_REG(TIMx->CCMR1, (0x7U << 12U), (mode << 8U)); + break; + case FL_GPTIM_CHANNEL_3: + MODIFY_REG(TIMx->CCMR2, (0x7U << 4U), (mode)); + break; + case FL_GPTIM_CHANNEL_4: + MODIFY_REG(TIMx->CCMR2, (0x7U << 12U), (mode << 8U)); + break; + } +} + +/** + * @brief Get OCx mode value + * @rmtoll CCMR OCM FL_GPTIM_OC_GetMode + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_OC_MODE_FROZEN + * @arg @ref FL_GPTIM_OC_MODE_ACTIVE + * @arg @ref FL_GPTIM_OC_MODE_INACTIVE + * @arg @ref FL_GPTIM_OC_MODE_TOGGLE + * @arg @ref FL_GPTIM_OC_MODE_FORCED_INACTIVE + * @arg @ref FL_GPTIM_OC_MODE_FORCED_ACTIVE + * @arg @ref FL_GPTIM_OC_MODE_PWM1 + * @arg @ref FL_GPTIM_OC_MODE_PWM2 + */ +__STATIC_INLINE uint32_t FL_GPTIM_OC_GetMode(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + return (uint32_t)(READ_BIT(TIMx->CCMR1, (0x7U << 4U)) >> 0U); + case FL_GPTIM_CHANNEL_2: + return (uint32_t)(READ_BIT(TIMx->CCMR1, (0x7U << 12U)) >> 8U); + case FL_GPTIM_CHANNEL_3: + return (uint32_t)(READ_BIT(TIMx->CCMR2, (0x7U << 4U)) >> 0U); + case FL_GPTIM_CHANNEL_4: + return (uint32_t)(READ_BIT(TIMx->CCMR2, (0x7U << 12U)) >> 8U); + default: + return 0; + } +} + +/** + * @brief + * @rmtoll CCMR OCPE FL_GPTIM_OC_EnablePreload + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_OC_EnablePreload(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + SET_BIT(TIMx->CCMR1, (0x1U << 3U)); + break; + case FL_GPTIM_CHANNEL_2: + SET_BIT(TIMx->CCMR1, (0x1U << 11U)); + break; + case FL_GPTIM_CHANNEL_3: + SET_BIT(TIMx->CCMR2, (0x1U << 3U)); + break; + case FL_GPTIM_CHANNEL_4: + SET_BIT(TIMx->CCMR2, (0x1U << 11U)); + break; + } +} + +/** + * @brief + * @rmtoll CCMR OCPE FL_GPTIM_OC_IsEnabledPreload + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_OC_IsEnabledPreload(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + return (uint32_t)(READ_BIT(TIMx->CCMR1, (0x1U << 3U)) >> 3U); + case FL_GPTIM_CHANNEL_2: + return (uint32_t)(READ_BIT(TIMx->CCMR1, (0x1U << 11U)) >> 11U); + case FL_GPTIM_CHANNEL_3: + return (uint32_t)(READ_BIT(TIMx->CCMR2, (0x1U << 3U)) >> 3U); + case FL_GPTIM_CHANNEL_4: + return (uint32_t)(READ_BIT(TIMx->CCMR2, (0x1U << 11U)) >> 11U); + default: + return 0; + } +} + +/** + * @brief + * @rmtoll CCMR OCPE FL_GPTIM_OC_DisablePreload + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_OC_DisablePreload(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + CLEAR_BIT(TIMx->CCMR1, (0x1U << 3U)); + break; + case FL_GPTIM_CHANNEL_2: + CLEAR_BIT(TIMx->CCMR1, (0x1U << 11U)); + break; + case FL_GPTIM_CHANNEL_3: + CLEAR_BIT(TIMx->CCMR2, (0x1U << 3U)); + break; + case FL_GPTIM_CHANNEL_4: + CLEAR_BIT(TIMx->CCMR2, (0x1U << 11U)); + break; + } +} + +/** + * @brief + * @rmtoll CCMR OCFE FL_GPTIM_OC_EnableFastMode + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_OC_EnableFastMode(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + SET_BIT(TIMx->CCMR1, (0x1U << 2U)); + break; + case FL_GPTIM_CHANNEL_2: + SET_BIT(TIMx->CCMR1, (0x1U << 10U)); + break; + case FL_GPTIM_CHANNEL_3: + SET_BIT(TIMx->CCMR2, (0x1U << 2U)); + break; + case FL_GPTIM_CHANNEL_4: + SET_BIT(TIMx->CCMR2, (0x1U << 10U)); + break; + } +} + +/** + * @brief + * @rmtoll CCMR OCFE FL_GPTIM_OC_IsEnabledFastMode + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_OC_IsEnabledFastMode(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + return (uint32_t)(READ_BIT(TIMx->CCMR1, (0x1U << 2U)) >> 2U); + case FL_GPTIM_CHANNEL_2: + return (uint32_t)(READ_BIT(TIMx->CCMR1, (0x1U << 10U)) >> 10U); + case FL_GPTIM_CHANNEL_3: + return (uint32_t)(READ_BIT(TIMx->CCMR2, (0x1U << 2U)) >> 2U); + case FL_GPTIM_CHANNEL_4: + return (uint32_t)(READ_BIT(TIMx->CCMR2, (0x1U << 10U)) >> 10U); + default: + return 0; + } +} + +/** + * @brief + * @rmtoll CCMR OCFE FL_GPTIM_OC_DisableFastMode + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_OC_DisableFastMode(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + CLEAR_BIT(TIMx->CCMR1, (0x1U << 2U)); + break; + case FL_GPTIM_CHANNEL_2: + CLEAR_BIT(TIMx->CCMR1, (0x1U << 10U)); + break; + case FL_GPTIM_CHANNEL_3: + CLEAR_BIT(TIMx->CCMR2, (0x1U << 2U)); + break; + case FL_GPTIM_CHANNEL_4: + CLEAR_BIT(TIMx->CCMR2, (0x1U << 10U)); + break; + } +} + +/** + * @brief + * @rmtoll CCMR ICF FL_GPTIM_IC_SetFilter + * @param TIMx TIM instance + * @param filter This parameter can be one of the following values: + * @arg @ref FL_GPTIM_IC_FILTER_DIV1 + * @arg @ref FL_GPTIM_IC_FILTER_DIV1_N2 + * @arg @ref FL_GPTIM_IC_FILTER_DIV1_N4 + * @arg @ref FL_GPTIM_IC_FILTER_DIV1_N8 + * @arg @ref FL_GPTIM_IC_FILTER_DIV2_N6 + * @arg @ref FL_GPTIM_IC_FILTER_DIV2_N8 + * @arg @ref FL_GPTIM_IC_FILTER_DIV4_N6 + * @arg @ref FL_GPTIM_IC_FILTER_DIV4_N8 + * @arg @ref FL_GPTIM_IC_FILTER_DIV8_N6 + * @arg @ref FL_GPTIM_IC_FILTER_DIV8_N8 + * @arg @ref FL_GPTIM_IC_FILTER_DIV16_N5 + * @arg @ref FL_GPTIM_IC_FILTER_DIV16_N6 + * @arg @ref FL_GPTIM_IC_FILTER_DIV16_N8 + * @arg @ref FL_GPTIM_IC_FILTER_DIV32_N5 + * @arg @ref FL_GPTIM_IC_FILTER_DIV32_N6 + * @arg @ref FL_GPTIM_IC_FILTER_DIV32_N8 + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_IC_SetFilter(GPTIM_Type *TIMx, uint32_t filter, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + MODIFY_REG(TIMx->CCMR1, (0xFU << 4U), (filter)); + break; + case FL_GPTIM_CHANNEL_2: + MODIFY_REG(TIMx->CCMR1, (0xFU << 12U), (filter << 8U)); + break; + case FL_GPTIM_CHANNEL_3: + MODIFY_REG(TIMx->CCMR2, (0xFU << 4U), (filter)); + break; + case FL_GPTIM_CHANNEL_4: + MODIFY_REG(TIMx->CCMR2, (0xFU << 12U), (filter << 8U)); + break; + } +} + +/** + * @brief + * @rmtoll CCMR ICF FL_GPTIM_IC_GetFilter + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_IC_FILTER_DIV1 + * @arg @ref FL_GPTIM_IC_FILTER_DIV1_N2 + * @arg @ref FL_GPTIM_IC_FILTER_DIV1_N4 + * @arg @ref FL_GPTIM_IC_FILTER_DIV1_N8 + * @arg @ref FL_GPTIM_IC_FILTER_DIV2_N6 + * @arg @ref FL_GPTIM_IC_FILTER_DIV2_N8 + * @arg @ref FL_GPTIM_IC_FILTER_DIV4_N6 + * @arg @ref FL_GPTIM_IC_FILTER_DIV4_N8 + * @arg @ref FL_GPTIM_IC_FILTER_DIV8_N6 + * @arg @ref FL_GPTIM_IC_FILTER_DIV8_N8 + * @arg @ref FL_GPTIM_IC_FILTER_DIV16_N5 + * @arg @ref FL_GPTIM_IC_FILTER_DIV16_N6 + * @arg @ref FL_GPTIM_IC_FILTER_DIV16_N8 + * @arg @ref FL_GPTIM_IC_FILTER_DIV32_N5 + * @arg @ref FL_GPTIM_IC_FILTER_DIV32_N6 + * @arg @ref FL_GPTIM_IC_FILTER_DIV32_N8 + */ +__STATIC_INLINE uint32_t FL_GPTIM_IC_GetFilter(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + return (uint32_t)(READ_BIT(TIMx->CCMR1, (0xFU << 4U)) >> 0U); + case FL_GPTIM_CHANNEL_2: + return (uint32_t)(READ_BIT(TIMx->CCMR1, (0xFU << 12U)) >> 8U); + case FL_GPTIM_CHANNEL_3: + return (uint32_t)(READ_BIT(TIMx->CCMR2, (0xFU << 4U)) >> 0U); + case FL_GPTIM_CHANNEL_4: + return (uint32_t)(READ_BIT(TIMx->CCMR2, (0xFU << 12U)) >> 8U); + default: + return 0; + } +} + +/** + * @brief + * @rmtoll CCMR ICPSC FL_GPTIM_IC_SetPrescaler + * @param TIMx TIM instance + * @param psc This parameter can be one of the following values: + * @arg @ref FL_GPTIM_IC_PSC_DIV1 + * @arg @ref FL_GPTIM_IC_PSC_DIV2 + * @arg @ref FL_GPTIM_IC_PSC_DIV4 + * @arg @ref FL_GPTIM_IC_PSC_DIV8 + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_IC_SetPrescaler(GPTIM_Type *TIMx, uint32_t psc, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + MODIFY_REG(TIMx->CCMR1, (0x3U << 2U), (psc)); + break; + case FL_GPTIM_CHANNEL_2: + MODIFY_REG(TIMx->CCMR1, (0x3U << 10U), (psc << 8U)); + break; + case FL_GPTIM_CHANNEL_3: + MODIFY_REG(TIMx->CCMR2, (0x3U << 2U), (psc)); + break; + case FL_GPTIM_CHANNEL_4: + MODIFY_REG(TIMx->CCMR2, (0x3U << 10U), (psc << 8U)); + break; + } +} + +/** + * @brief + * @rmtoll CCMR ICPSC FL_GPTIM_IC_GetPrescaler + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_IC_PSC_DIV1 + * @arg @ref FL_GPTIM_IC_PSC_DIV2 + * @arg @ref FL_GPTIM_IC_PSC_DIV4 + * @arg @ref FL_GPTIM_IC_PSC_DIV8 + */ +__STATIC_INLINE uint32_t FL_GPTIM_IC_GetPrescaler(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + return (uint32_t)(READ_BIT(TIMx->CCMR1, (0x3U << 2U)) >> 0U); + case FL_GPTIM_CHANNEL_2: + return (uint32_t)(READ_BIT(TIMx->CCMR1, (0x3U << 10U)) >> 8U); + case FL_GPTIM_CHANNEL_3: + return (uint32_t)(READ_BIT(TIMx->CCMR2, (0x3U << 2U)) >> 0U); + case FL_GPTIM_CHANNEL_4: + return (uint32_t)(READ_BIT(TIMx->CCMR2, (0x3U << 10U)) >> 8U); + default: + return 0; + } +} + +/** + * @brief + * @rmtoll CCMR CCS FL_GPTIM_CC_SetChannelMode + * @param TIMx TIM instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_MODE_OUTPUT + * @arg @ref FL_GPTIM_CHANNEL_MODE_INPUT_NORMAL + * @arg @ref FL_GPTIM_CHANNEL_MODE_INPUT_CROSSOVER + * @arg @ref FL_GPTIM_CHANNEL_MODE_INPUT_TRC + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_CC_SetChannelMode(GPTIM_Type *TIMx, uint32_t mode, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + MODIFY_REG(TIMx->CCMR1, (0x3U << 0U), (mode)); + break; + case FL_GPTIM_CHANNEL_2: + MODIFY_REG(TIMx->CCMR1, (0x3U << 8U), (mode << 8U)); + break; + case FL_GPTIM_CHANNEL_3: + MODIFY_REG(TIMx->CCMR2, (0x3U << 0U), (mode)); + break; + case FL_GPTIM_CHANNEL_4: + MODIFY_REG(TIMx->CCMR2, (0x3U << 8U), (mode << 8U)); + break; + } +} + +/** + * @brief + * @rmtoll CCMR CCS FL_GPTIM_CC_GetChannelMode + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_MODE_OUTPUT + * @arg @ref FL_GPTIM_CHANNEL_MODE_INPUT_NORMAL + * @arg @ref FL_GPTIM_CHANNEL_MODE_INPUT_CROSSOVER + * @arg @ref FL_GPTIM_CHANNEL_MODE_INPUT_TRC + */ +__STATIC_INLINE uint32_t FL_GPTIM_CC_GetChannelMode(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + return (uint32_t)(READ_BIT(TIMx->CCMR1, (0x3U << 0U)) >> 0U); + case FL_GPTIM_CHANNEL_2: + return (uint32_t)(READ_BIT(TIMx->CCMR1, (0x3U << 8U)) >> 8U); + case FL_GPTIM_CHANNEL_3: + return (uint32_t)(READ_BIT(TIMx->CCMR2, (0x3U << 0U)) >> 0U); + case FL_GPTIM_CHANNEL_4: + return (uint32_t)(READ_BIT(TIMx->CCMR2, (0x3U << 8U)) >> 8U); + default: + return 0; + } +} + +/** + * @brief + * @rmtoll CCER CCOP FL_GPTIM_OC_SetChannelPolarity + * @param TIMx TIM instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_GPTIM_OC_POLARITY_NORMAL + * @arg @ref FL_GPTIM_OC_POLARITY_INVERT + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_OC_SetChannelPolarity(GPTIM_Type *TIMx, uint32_t polarity, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + MODIFY_REG(TIMx->CCER, (0x1U << 1U), (polarity)); + break; + case FL_GPTIM_CHANNEL_2: + MODIFY_REG(TIMx->CCER, (0x1U << 5U), (polarity << 4U)); + break; + case FL_GPTIM_CHANNEL_3: + MODIFY_REG(TIMx->CCER, (0x1U << 9U), (polarity << 8U)); + break; + case FL_GPTIM_CHANNEL_4: + MODIFY_REG(TIMx->CCER, (0x1U << 13U), (polarity << 12U)); + break; + } +} + +/** + * @brief + * @rmtoll CCER CCOP FL_GPTIM_OC_GetChannelPolarity + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_OC_POLARITY_NORMAL + * @arg @ref FL_GPTIM_OC_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_GPTIM_OC_GetChannelPolarity(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 1U)) >> 0U); + case FL_GPTIM_CHANNEL_2: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 5U)) >> 4U); + case FL_GPTIM_CHANNEL_3: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 9U)) >> 8U); + case FL_GPTIM_CHANNEL_4: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 13U)) >> 12U); + default: + return 0; + } +} + +/** + * @brief + * @rmtoll CCER CCIP FL_GPTIM_IC_SetChannelPolarity + * @param TIMx TIM instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_GPTIM_IC_POLARITY_NORMAL + * @arg @ref FL_GPTIM_IC_POLARITY_INVERT + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_IC_SetChannelPolarity(GPTIM_Type *TIMx, uint32_t polarity, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + MODIFY_REG(TIMx->CCER, (0x1U << 1U), (polarity)); + break; + case FL_GPTIM_CHANNEL_2: + MODIFY_REG(TIMx->CCER, (0x1U << 5U), (polarity << 4U)); + break; + case FL_GPTIM_CHANNEL_3: + MODIFY_REG(TIMx->CCER, (0x1U << 9U), (polarity << 8U)); + break; + case FL_GPTIM_CHANNEL_4: + MODIFY_REG(TIMx->CCER, (0x1U << 13U), (polarity << 12U)); + break; + } +} + +/** + * @brief + * @rmtoll CCER CCIP FL_GPTIM_IC_GetChannelPolarity + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval Returned value can be one of the following values: + * @arg @ref FL_GPTIM_IC_POLARITY_NORMAL + * @arg @ref FL_GPTIM_IC_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_GPTIM_IC_GetChannelPolarity(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 1U)) >> 0U); + case FL_GPTIM_CHANNEL_2: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 5U)) >> 4U); + case FL_GPTIM_CHANNEL_3: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 9U)) >> 8U); + case FL_GPTIM_CHANNEL_4: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 13U)) >> 12U); + default: + return 0; + } +} + +/** + * @brief + * @rmtoll CCER CCE FL_GPTIM_OC_EnableChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_OC_EnableChannel(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + SET_BIT(TIMx->CCER, (0x1U << 0U)); + break; + case FL_GPTIM_CHANNEL_2: + SET_BIT(TIMx->CCER, (0x1U << 4U)); + break; + case FL_GPTIM_CHANNEL_3: + SET_BIT(TIMx->CCER, (0x1U << 8U)); + break; + case FL_GPTIM_CHANNEL_4: + SET_BIT(TIMx->CCER, (0x1U << 12U)); + break; + } +} + +/** + * @brief + * @rmtoll CCER CCE FL_GPTIM_OC_IsEnabledChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_OC_IsEnabledChannel(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 0U)) >> 0U); + case FL_GPTIM_CHANNEL_2: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 4U)) >> 4U); + case FL_GPTIM_CHANNEL_3: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 8U)) >> 8U); + case FL_GPTIM_CHANNEL_4: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 12U)) >> 12U); + default: + return 0; + } +} + +/** + * @brief + * @rmtoll CCER CCE FL_GPTIM_OC_DisableChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_OC_DisableChannel(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + CLEAR_BIT(TIMx->CCER, (0x1U << 0U)); + break; + case FL_GPTIM_CHANNEL_2: + CLEAR_BIT(TIMx->CCER, (0x1U << 4U)); + break; + case FL_GPTIM_CHANNEL_3: + CLEAR_BIT(TIMx->CCER, (0x1U << 8U)); + break; + case FL_GPTIM_CHANNEL_4: + CLEAR_BIT(TIMx->CCER, (0x1U << 12U)); + break; + } +} + +/** + * @brief + * @rmtoll CCER CCE FL_GPTIM_IC_EnableChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_IC_EnableChannel(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + SET_BIT(TIMx->CCER, (0x1U << 0U)); + break; + case FL_GPTIM_CHANNEL_2: + SET_BIT(TIMx->CCER, (0x1U << 4U)); + break; + case FL_GPTIM_CHANNEL_3: + SET_BIT(TIMx->CCER, (0x1U << 8U)); + break; + case FL_GPTIM_CHANNEL_4: + SET_BIT(TIMx->CCER, (0x1U << 12U)); + break; + } +} + +/** + * @brief + * @rmtoll CCER CCE FL_GPTIM_IC_IsEnabledChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_GPTIM_IC_IsEnabledChannel(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 0U)) >> 0U); + case FL_GPTIM_CHANNEL_2: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 4U)) >> 4U); + case FL_GPTIM_CHANNEL_3: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 8U)) >> 8U); + case FL_GPTIM_CHANNEL_4: + return (uint32_t)(READ_BIT(TIMx->CCER, (0x1U << 12U)) >> 12U); + default: + return 0; + } +} + +/** + * @brief + * @rmtoll CCER CCE FL_GPTIM_IC_DisableChannel + * @param TIMx TIM instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @retval None + */ +__STATIC_INLINE void FL_GPTIM_IC_DisableChannel(GPTIM_Type *TIMx, uint32_t channel) +{ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + CLEAR_BIT(TIMx->CCER, (0x1U << 0U)); + break; + case FL_GPTIM_CHANNEL_2: + CLEAR_BIT(TIMx->CCER, (0x1U << 4U)); + break; + case FL_GPTIM_CHANNEL_3: + CLEAR_BIT(TIMx->CCER, (0x1U << 8U)); + break; + case FL_GPTIM_CHANNEL_4: + CLEAR_BIT(TIMx->CCER, (0x1U << 12U)); + break; + } +} + +/** + * @} + */ + +/** @defgroup GPTIM_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_GPTIM_DeInit(GPTIM_Type *TIMx); + +void FL_GPTIM_StructInit(FL_GPTIM_InitTypeDef *init); +void FL_GPTIM_SlaveMode_StructInit(FL_GPTIM_SlaveInitTypeDef *slave_init); +void FL_GPTIM_OC_StructInit(FL_GPTIM_OC_InitTypeDef *oc_init); +void FL_GPTIM_IC_StructInit(FL_GPTIM_IC_InitTypeDef *ic_init); +void FL_GPTIM_ETR_StructInit(FL_GPTIM_ETR_InitTypeDef *etr_init); + +FL_ErrorStatus FL_GPTIM_Init(GPTIM_Type *TIMx, FL_GPTIM_InitTypeDef *init); +FL_ErrorStatus FL_GPTIM_SlaveMode_Init(GPTIM_Type *TIMx, FL_GPTIM_SlaveInitTypeDef *slave_init); +FL_ErrorStatus FL_GPTIM_OC_Init(GPTIM_Type *TIMx, uint32_t channel, FL_GPTIM_OC_InitTypeDef *oc_init); +FL_ErrorStatus FL_GPTIM_IC_Init(GPTIM_Type *TIMx, uint32_t channel, FL_GPTIM_IC_InitTypeDef *ic_init); +FL_ErrorStatus FL_GPTIM_ETR_Init(GPTIM_Type *TIMx, FL_GPTIM_ETR_InitTypeDef *etr_init); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_GPTIM_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-23*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_i2c.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_i2c.h new file mode 100644 index 0000000000..a10f355979 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_i2c.h @@ -0,0 +1,1865 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_i2c.h + * @author FMSH Application Team + * @brief Head file of I2C FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_I2C_H +#define __FM33LC0XX_FL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup I2C_FL_ES_INIT I2C Exported Init structures + * @{ + */ + +/** + * @brief I2C Init Sturcture Definition + */ +typedef struct +{ + /** 主机时使用的时钟源*/ + uint32_t clockSource; + + /** I2C通讯速率*/ + uint32_t baudRate; + +} FL_I2C_MasterMode_InitTypeDef; + +/** + * @brief I2C Slavemode Init Sturcture Definition + */ +typedef struct +{ + /** 从机模式从机地址 */ + uint32_t ownAddr; + + /** 从机模式自动回应ACK */ + uint32_t ACK; + + /** 从机模式地址位宽 */ + uint32_t ownAddrSize10bit; + + /** 从机时钟延展*/ + uint32_t SCLSEN; + +} FL_I2C_SlaveMode_InitTypeDef; + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup I2C_FL_Exported_Constants I2C Exported Constants + * @{ + */ + +#define I2C_MSPCFGR_MSPEN_Pos (0U) +#define I2C_MSPCFGR_MSPEN_Msk (0x1U << I2C_MSPCFGR_MSPEN_Pos) +#define I2C_MSPCFGR_MSPEN I2C_MSPCFGR_MSPEN_Msk + +#define I2C_MSPCFGR_TOEN_Pos (1U) +#define I2C_MSPCFGR_TOEN_Msk (0x1U << I2C_MSPCFGR_TOEN_Pos) +#define I2C_MSPCFGR_TOEN I2C_MSPCFGR_TOEN_Msk + +#define I2C_MSPCFGR_DMAEN_Pos (16U) +#define I2C_MSPCFGR_DMAEN_Msk (0x1U << I2C_MSPCFGR_DMAEN_Pos) +#define I2C_MSPCFGR_DMAEN I2C_MSPCFGR_DMAEN_Msk + +#define I2C_MSPCFGR_AUTOEND_Pos (17U) +#define I2C_MSPCFGR_AUTOEND_Msk (0x1U << I2C_MSPCFGR_AUTOEND_Pos) +#define I2C_MSPCFGR_AUTOEND I2C_MSPCFGR_AUTOEND_Msk + +#define I2C_MSPCR_RCEN_Pos (3U) +#define I2C_MSPCR_RCEN_Msk (0x1U << I2C_MSPCR_RCEN_Pos) +#define I2C_MSPCR_RCEN I2C_MSPCR_RCEN_Msk + +#define I2C_MSPCR_PEN_Pos (2U) +#define I2C_MSPCR_PEN_Msk (0x1U << I2C_MSPCR_PEN_Pos) +#define I2C_MSPCR_PEN I2C_MSPCR_PEN_Msk + +#define I2C_MSPCR_RSEN_Pos (1U) +#define I2C_MSPCR_RSEN_Msk (0x1U << I2C_MSPCR_RSEN_Pos) +#define I2C_MSPCR_RSEN I2C_MSPCR_RSEN_Msk + +#define I2C_MSPCR_SEN_Pos (0U) +#define I2C_MSPCR_SEN_Msk (0x1U << I2C_MSPCR_SEN_Pos) +#define I2C_MSPCR_SEN I2C_MSPCR_SEN_Msk + +#define I2C_MSPIER_WCOLIE_Pos (6U) +#define I2C_MSPIER_WCOLIE_Msk (0x1U << I2C_MSPIER_WCOLIE_Pos) +#define I2C_MSPIER_WCOLIE I2C_MSPIER_WCOLIE_Msk + +#define I2C_MSPIER_TOIE_Pos (5U) +#define I2C_MSPIER_TOIE_Msk (0x1U << I2C_MSPIER_TOIE_Pos) +#define I2C_MSPIER_TOIE I2C_MSPIER_TOIE_Msk + +#define I2C_MSPIER_SIE_Pos (4U) +#define I2C_MSPIER_SIE_Msk (0x1U << I2C_MSPIER_SIE_Pos) +#define I2C_MSPIER_SIE I2C_MSPIER_SIE_Msk + +#define I2C_MSPIER_PIE_Pos (3U) +#define I2C_MSPIER_PIE_Msk (0x1U << I2C_MSPIER_PIE_Pos) +#define I2C_MSPIER_PIE I2C_MSPIER_PIE_Msk + +#define I2C_MSPIER_NACKIE_Pos (2U) +#define I2C_MSPIER_NACKIE_Msk (0x1U << I2C_MSPIER_NACKIE_Pos) +#define I2C_MSPIER_NACKIE I2C_MSPIER_NACKIE_Msk + +#define I2C_MSPIER_TXIE_Pos (1U) +#define I2C_MSPIER_TXIE_Msk (0x1U << I2C_MSPIER_TXIE_Pos) +#define I2C_MSPIER_TXIE I2C_MSPIER_TXIE_Msk + +#define I2C_MSPIER_RXIE_Pos (0U) +#define I2C_MSPIER_RXIE_Msk (0x1U << I2C_MSPIER_RXIE_Pos) +#define I2C_MSPIER_RXIE I2C_MSPIER_RXIE_Msk + +#define I2C_MSPISR_WCOL_Pos (6U) +#define I2C_MSPISR_WCOL_Msk (0x1U << I2C_MSPISR_WCOL_Pos) +#define I2C_MSPISR_WCOL I2C_MSPISR_WCOL_Msk + +#define I2C_MSPISR_TO_Pos (5U) +#define I2C_MSPISR_TO_Msk (0x1U << I2C_MSPISR_TO_Pos) +#define I2C_MSPISR_TO I2C_MSPISR_TO_Msk + +#define I2C_MSPISR_S_Pos (4U) +#define I2C_MSPISR_S_Msk (0x1U << I2C_MSPISR_S_Pos) +#define I2C_MSPISR_S I2C_MSPISR_S_Msk + +#define I2C_MSPISR_P_Pos (3U) +#define I2C_MSPISR_P_Msk (0x1U << I2C_MSPISR_P_Pos) +#define I2C_MSPISR_P I2C_MSPISR_P_Msk + +#define I2C_MSPISR_ACKSTA_Pos (2U) +#define I2C_MSPISR_ACKSTA_Msk (0x1U << I2C_MSPISR_ACKSTA_Pos) +#define I2C_MSPISR_ACKSTA I2C_MSPISR_ACKSTA_Msk + +#define I2C_MSPISR_TXIF_Pos (1U) +#define I2C_MSPISR_TXIF_Msk (0x1U << I2C_MSPISR_TXIF_Pos) +#define I2C_MSPISR_TXIF I2C_MSPISR_TXIF_Msk + +#define I2C_MSPISR_RXIF_Pos (0U) +#define I2C_MSPISR_RXIF_Msk (0x1U << I2C_MSPISR_RXIF_Pos) +#define I2C_MSPISR_RXIF I2C_MSPISR_RXIF_Msk + +#define I2C_MSPSR_BUSY_Pos (5U) +#define I2C_MSPSR_BUSY_Msk (0x1U << I2C_MSPSR_BUSY_Pos) +#define I2C_MSPSR_BUSY I2C_MSPSR_BUSY_Msk + +#define I2C_MSPSR_RW_Pos (4U) +#define I2C_MSPSR_RW_Msk (0x1U << I2C_MSPSR_RW_Pos) +#define I2C_MSPSR_RW I2C_MSPSR_RW_Msk + +#define I2C_MSPSR_BF_Pos (2U) +#define I2C_MSPSR_BF_Msk (0x1U << I2C_MSPSR_BF_Pos) +#define I2C_MSPSR_BF I2C_MSPSR_BF_Msk + +#define I2C_MSPSR_ACKMO_Pos (0U) +#define I2C_MSPSR_ACKMO_Msk (0x1U << I2C_MSPSR_ACKMO_Pos) +#define I2C_MSPSR_ACKMO I2C_MSPSR_ACKMO_Msk + +#define I2C_MSPBGR_MSPBGRH_Pos (16U) +#define I2C_MSPBGR_MSPBGRH_Msk (0x1ffU << I2C_MSPBGR_MSPBGRH_Pos) +#define I2C_MSPBGR_MSPBGRH I2C_MSPBGR_MSPBGRH_Msk + +#define I2C_MSPBGR_MSPBGRL_Pos (0U) +#define I2C_MSPBGR_MSPBGRL_Msk (0x1ffU << I2C_MSPBGR_MSPBGRL_Pos) +#define I2C_MSPBGR_MSPBGRL I2C_MSPBGR_MSPBGRL_Msk + +#define I2C_MSPBUF_MSPBUF_Pos (0U) +#define I2C_MSPBUF_MSPBUF_Msk (0xffU << I2C_MSPBUF_MSPBUF_Pos) +#define I2C_MSPBUF_MSPBUF I2C_MSPBUF_MSPBUF_Msk + +#define I2C_MSPTCR_SDAHD_Pos (0U) +#define I2C_MSPTCR_SDAHD_Msk (0x1ffU << I2C_MSPTCR_SDAHD_Pos) +#define I2C_MSPTCR_SDAHD I2C_MSPTCR_SDAHD_Msk + +#define I2C_MSPTOR_TIMEOUT_Pos (0U) +#define I2C_MSPTOR_TIMEOUT_Msk (0xfffU << I2C_MSPTOR_TIMEOUT_Pos) +#define I2C_MSPTOR_TIMEOUT I2C_MSPTOR_TIMEOUT_Msk + +#define I2C_SSPCR_SCLSEN_Pos (9U) +#define I2C_SSPCR_SCLSEN_Msk (0x1U << I2C_SSPCR_SCLSEN_Pos) +#define I2C_SSPCR_SCLSEN I2C_SSPCR_SCLSEN_Msk + +#define I2C_SSPCR_DMAEN_Pos (8U) +#define I2C_SSPCR_DMAEN_Msk (0x1U << I2C_SSPCR_DMAEN_Pos) +#define I2C_SSPCR_DMAEN I2C_SSPCR_DMAEN_Msk + +#define I2C_SSPCR_ACKEN_Pos (4U) +#define I2C_SSPCR_ACKEN_Msk (0x1U << I2C_SSPCR_ACKEN_Pos) +#define I2C_SSPCR_ACKEN I2C_SSPCR_ACKEN_Msk + +#define I2C_SSPCR_SDAO_DLYEN_Pos (3U) +#define I2C_SSPCR_SDAO_DLYEN_Msk (0x1U << I2C_SSPCR_SDAO_DLYEN_Pos) +#define I2C_SSPCR_SDAO_DLYEN I2C_SSPCR_SDAO_DLYEN_Msk + +#define I2C_SSPCR_SCLI_ANFEN_Pos (2U) +#define I2C_SSPCR_SCLI_ANFEN_Msk (0x1U << I2C_SSPCR_SCLI_ANFEN_Pos) +#define I2C_SSPCR_SCLI_ANFEN I2C_SSPCR_SCLI_ANFEN_Msk + +#define I2C_SSPCR_A10EN_Pos (1U) +#define I2C_SSPCR_A10EN_Msk (0x1U << I2C_SSPCR_A10EN_Pos) +#define I2C_SSPCR_A10EN I2C_SSPCR_A10EN_Msk + +#define I2C_SSPCR_SSPEN_Pos (0U) +#define I2C_SSPCR_SSPEN_Msk (0x1U << I2C_SSPCR_SSPEN_Pos) +#define I2C_SSPCR_SSPEN I2C_SSPCR_SSPEN_Msk + +#define I2C_SSPIER_ADEIE_Pos (7U) +#define I2C_SSPIER_ADEIE_Msk (0x1U << I2C_SSPIER_ADEIE_Pos) +#define I2C_SSPIER_ADEIE I2C_SSPIER_ADEIE_Msk + +#define I2C_SSPIER_SIE_Pos (6U) +#define I2C_SSPIER_SIE_Msk (0x1U << I2C_SSPIER_SIE_Pos) +#define I2C_SSPIER_SIE I2C_SSPIER_SIE_Msk + +#define I2C_SSPIER_PIE_Pos (5U) +#define I2C_SSPIER_PIE_Msk (0x1U << I2C_SSPIER_PIE_Pos) +#define I2C_SSPIER_PIE I2C_SSPIER_PIE_Msk + +#define I2C_SSPIER_WCOLIE_Pos (4U) +#define I2C_SSPIER_WCOLIE_Msk (0x1U << I2C_SSPIER_WCOLIE_Pos) +#define I2C_SSPIER_WCOLIE I2C_SSPIER_WCOLIE_Msk + +#define I2C_SSPIER_SSPOVIE_Pos (3U) +#define I2C_SSPIER_SSPOVIE_Msk (0x1U << I2C_SSPIER_SSPOVIE_Pos) +#define I2C_SSPIER_SSPOVIE I2C_SSPIER_SSPOVIE_Msk + +#define I2C_SSPIER_ADMIE_Pos (2U) +#define I2C_SSPIER_ADMIE_Msk (0x1U << I2C_SSPIER_ADMIE_Pos) +#define I2C_SSPIER_ADMIE I2C_SSPIER_ADMIE_Msk + +#define I2C_SSPIER_TXIE_Pos (1U) +#define I2C_SSPIER_TXIE_Msk (0x1U << I2C_SSPIER_TXIE_Pos) +#define I2C_SSPIER_TXIE I2C_SSPIER_TXIE_Msk + +#define I2C_SSPIER_RXIE_Pos (0U) +#define I2C_SSPIER_RXIE_Msk (0x1U << I2C_SSPIER_RXIE_Pos) +#define I2C_SSPIER_RXIE I2C_SSPIER_RXIE_Msk + +#define I2C_SSPISR_ADE_Pos (7U) +#define I2C_SSPISR_ADE_Msk (0x1U << I2C_SSPISR_ADE_Pos) +#define I2C_SSPISR_ADE I2C_SSPISR_ADE_Msk + +#define I2C_SSPISR_S_Pos (6U) +#define I2C_SSPISR_S_Msk (0x1U << I2C_SSPISR_S_Pos) +#define I2C_SSPISR_S I2C_SSPISR_S_Msk + +#define I2C_SSPISR_P_Pos (5U) +#define I2C_SSPISR_P_Msk (0x1U << I2C_SSPISR_P_Pos) +#define I2C_SSPISR_P I2C_SSPISR_P_Msk + +#define I2C_SSPISR_WCOL_Pos (4U) +#define I2C_SSPISR_WCOL_Msk (0x1U << I2C_SSPISR_WCOL_Pos) +#define I2C_SSPISR_WCOL I2C_SSPISR_WCOL_Msk + +#define I2C_SSPISR_SSPOV_Pos (3U) +#define I2C_SSPISR_SSPOV_Msk (0x1U << I2C_SSPISR_SSPOV_Pos) +#define I2C_SSPISR_SSPOV I2C_SSPISR_SSPOV_Msk + +#define I2C_SSPISR_ADM_Pos (2U) +#define I2C_SSPISR_ADM_Msk (0x1U << I2C_SSPISR_ADM_Pos) +#define I2C_SSPISR_ADM I2C_SSPISR_ADM_Msk + +#define I2C_SSPISR_TXIF_Pos (1U) +#define I2C_SSPISR_TXIF_Msk (0x1U << I2C_SSPISR_TXIF_Pos) +#define I2C_SSPISR_TXIF I2C_SSPISR_TXIF_Msk + +#define I2C_SSPISR_RXIF_Pos (0U) +#define I2C_SSPISR_RXIF_Msk (0x1U << I2C_SSPISR_RXIF_Pos) +#define I2C_SSPISR_RXIF I2C_SSPISR_RXIF_Msk + +#define I2C_SSPSR_BUSY_Pos (3U) +#define I2C_SSPSR_BUSY_Msk (0x1U << I2C_SSPSR_BUSY_Pos) +#define I2C_SSPSR_BUSY I2C_SSPSR_BUSY_Msk + +#define I2C_SSPSR_RW_Pos (2U) +#define I2C_SSPSR_RW_Msk (0x1U << I2C_SSPSR_RW_Pos) +#define I2C_SSPSR_RW I2C_SSPSR_RW_Msk + +#define I2C_SSPSR_DA_Pos (1U) +#define I2C_SSPSR_DA_Msk (0x1U << I2C_SSPSR_DA_Pos) +#define I2C_SSPSR_DA I2C_SSPSR_DA_Msk + +#define I2C_SSPSR_BF_Pos (0U) +#define I2C_SSPSR_BF_Msk (0x1U << I2C_SSPSR_BF_Pos) +#define I2C_SSPSR_BF I2C_SSPSR_BF_Msk + + + + + + +#define FL_I2C_MSP_DATA_DIRECTION_SLAVE_TO_MASTER (0x0U << I2C_MSPSR_RW_Pos) +#define FL_I2C_MSP_DATA_DIRECTION_MASTER_TO_SLAVE (0x1U << I2C_MSPSR_RW_Pos) + +#define FL_I2C_MSP_DATA_BUFF_STATUS_FULL (0x0U << I2C_MSPSR_BF_Pos) +#define FL_I2C_MSP_DATA_BUFF_STATUS_EMPTY (0x1U << I2C_MSPSR_BF_Pos) + +#define FL_I2C_MASTER_RESPOND_ACK (0x0U << I2C_MSPSR_ACKMO_Pos) +#define FL_I2C_MASTER_RESPOND_NACK (0x1U << I2C_MSPSR_ACKMO_Pos) + +#define FL_I2C_SSP_DATA_DIRECTION_SLAVE_TO_MASTER (0x1U << I2C_SSPSR_RW_Pos) +#define FL_I2C_SSP_DATA_DIRECTION_MASTER_TO_SLAVE (0x0U << I2C_SSPSR_RW_Pos) + +#define FL_I2C_SSP_DATA_TYPE_DATA (0x1U << I2C_SSPSR_DA_Pos) +#define FL_I2C_SSP_DATA_TYPE_ADDR (0x0U << I2C_SSPSR_DA_Pos) + +#define FL_I2C_SSP_DATA_BUFF_STATUS_FULL (0x1U << I2C_SSPSR_BF_Pos) +#define FL_I2C_SSP_DATA_BUFF_STATUS_EMPTY (0x0U << I2C_SSPSR_BF_Pos) + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup I2C_FL_Exported_Functions I2C Exported Functions + * @{ + */ + +/** + * @brief + * @rmtoll MSPCFGR MSPEN FL_I2C_Master_Enable + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_Enable(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPCFGR, I2C_MSPCFGR_MSPEN_Msk); +} + +/** + * @brief + * @rmtoll MSPCFGR MSPEN FL_I2C_Master_IsEnabled + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsEnabled(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPCFGR, I2C_MSPCFGR_MSPEN_Msk) == I2C_MSPCFGR_MSPEN_Msk); +} + +/** + * @brief + * @rmtoll MSPCFGR MSPEN FL_I2C_Master_Disable + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_Disable(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->MSPCFGR, I2C_MSPCFGR_MSPEN_Msk); +} + +/** + * @brief + * @rmtoll MSPCFGR TOEN FL_I2C_Master_EnableTimeout + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_EnableTimeout(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPCFGR, I2C_MSPCFGR_TOEN_Msk); +} + +/** + * @brief + * @rmtoll MSPCFGR TOEN FL_I2C_Master_IsEnabledTimeout + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsEnabledTimeout(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPCFGR, I2C_MSPCFGR_TOEN_Msk) == I2C_MSPCFGR_TOEN_Msk); +} + +/** + * @brief + * @rmtoll MSPCFGR TOEN FL_I2C_Master_DisableTimeout + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_DisableTimeout(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->MSPCFGR, I2C_MSPCFGR_TOEN_Msk); +} + +/** + * @brief + * @rmtoll MSPCFGR DMAEN FL_I2C_Master_EnableDMAReq + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_EnableDMAReq(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPCFGR, I2C_MSPCFGR_DMAEN_Msk); +} + +/** + * @brief + * @rmtoll MSPCFGR DMAEN FL_I2C_Master_IsEnabledDMAReq + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsEnabledDMAReq(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPCFGR, I2C_MSPCFGR_DMAEN_Msk) == I2C_MSPCFGR_DMAEN_Msk); +} + +/** + * @brief + * @rmtoll MSPCFGR DMAEN FL_I2C_Master_DisableDMAReq + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_DisableDMAReq(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->MSPCFGR, I2C_MSPCFGR_DMAEN_Msk); +} + +/** + * @brief + * @rmtoll MSPCFGR AUTOEND FL_I2C_Master_EnableAutoStop + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_EnableAutoStop(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPCFGR, I2C_MSPCFGR_AUTOEND_Msk); +} + +/** + * @brief + * @rmtoll MSPCFGR AUTOEND FL_I2C_Master_IsEnabledAutoStop + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsEnabledAutoStop(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPCFGR, I2C_MSPCFGR_AUTOEND_Msk) == I2C_MSPCFGR_AUTOEND_Msk); +} + +/** + * @brief + * @rmtoll MSPCFGR AUTOEND FL_I2C_Master_DisableAutoStop + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_DisableAutoStop(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->MSPCFGR, I2C_MSPCFGR_AUTOEND_Msk); +} + +/** + * @brief + * @rmtoll MSPCR RCEN FL_I2C_Master_EnableRX + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_EnableRX(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPCR, I2C_MSPCR_RCEN_Msk); +} + +/** + * @brief + * @rmtoll MSPCR RCEN FL_I2C_Master_IsEnabledRX + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsEnabledRX(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPCR, I2C_MSPCR_RCEN_Msk) == I2C_MSPCR_RCEN_Msk); +} + +/** + * @brief + * @rmtoll MSPCR RCEN FL_I2C_Master_DisableRX + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_DisableRX(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->MSPCR, I2C_MSPCR_RCEN_Msk); +} + +/** + * @brief + * @rmtoll MSPCR PEN FL_I2C_Master_EnableI2CStop + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_EnableI2CStop(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPCR, I2C_MSPCR_PEN_Msk); +} + +/** + * @brief + * @rmtoll MSPCR RSEN FL_I2C_Master_EnableI2CRestart + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_EnableI2CRestart(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPCR, I2C_MSPCR_RSEN_Msk); +} + +/** + * @brief + * @rmtoll MSPCR SEN FL_I2C_Master_EnableI2CStart + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_EnableI2CStart(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPCR, I2C_MSPCR_SEN_Msk); +} + +/** + * @brief + * @rmtoll MSPIER WCOLIE FL_I2C_Master_EnableIT_WriteConflict + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_EnableIT_WriteConflict(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPIER, I2C_MSPIER_WCOLIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER WCOLIE FL_I2C_Master_IsEnabledIT_WriteConflict + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsEnabledIT_WriteConflict(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPIER, I2C_MSPIER_WCOLIE_Msk) == I2C_MSPIER_WCOLIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER WCOLIE FL_I2C_Master_DisableIT_WriteConflict + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_DisableIT_WriteConflict(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->MSPIER, I2C_MSPIER_WCOLIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER TOIE FL_I2C_Master_EnableIT_Timeout + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_EnableIT_Timeout(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPIER, I2C_MSPIER_TOIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER TOIE FL_I2C_Master_IsEnabledIT_Timeout + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsEnabledIT_Timeout(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPIER, I2C_MSPIER_TOIE_Msk) == I2C_MSPIER_TOIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER TOIE FL_I2C_Master_DisableIT_Timeout + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_DisableIT_Timeout(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->MSPIER, I2C_MSPIER_TOIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER SIE FL_I2C_Master_EnableIT_Start + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_EnableIT_Start(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPIER, I2C_MSPIER_SIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER SIE FL_I2C_Master_IsEnabledIT_Start + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsEnabledIT_Start(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPIER, I2C_MSPIER_SIE_Msk) == I2C_MSPIER_SIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER SIE FL_I2C_Master_DisableIT_Start + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_DisableIT_Start(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->MSPIER, I2C_MSPIER_SIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER PIE FL_I2C_Master_EnableIT_Stop + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_EnableIT_Stop(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPIER, I2C_MSPIER_PIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER PIE FL_I2C_Master_IsEnabledIT_Stop + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsEnabledIT_Stop(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPIER, I2C_MSPIER_PIE_Msk) == I2C_MSPIER_PIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER PIE FL_I2C_Master_DisableIT_Stop + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_DisableIT_Stop(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->MSPIER, I2C_MSPIER_PIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER NACKIE FL_I2C_Master_EnableIT_NACK + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_EnableIT_NACK(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPIER, I2C_MSPIER_NACKIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER NACKIE FL_I2C_Master_IsEnabledIT_NACK + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsEnabledIT_NACK(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPIER, I2C_MSPIER_NACKIE_Msk) == I2C_MSPIER_NACKIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER NACKIE FL_I2C_Master_DisableIT_NACK + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_DisableIT_NACK(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->MSPIER, I2C_MSPIER_NACKIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER TXIE FL_I2C_Master_EnableIT_TXComplete + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_EnableIT_TXComplete(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPIER, I2C_MSPIER_TXIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER TXIE FL_I2C_Master_IsEnabledIT_TXComplete + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsEnabledIT_TXComplete(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPIER, I2C_MSPIER_TXIE_Msk) == I2C_MSPIER_TXIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER TXIE FL_I2C_Master_DisableIT_TXComplete + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_DisableIT_TXComplete(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->MSPIER, I2C_MSPIER_TXIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER RXIE FL_I2C_Master_EnableIT_RXComplete + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_EnableIT_RXComplete(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->MSPIER, I2C_MSPIER_RXIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER RXIE FL_I2C_Master_IsEnabledIT_RXComplete + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsEnabledIT_RXComplete(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPIER, I2C_MSPIER_RXIE_Msk) == I2C_MSPIER_RXIE_Msk); +} + +/** + * @brief + * @rmtoll MSPIER RXIE FL_I2C_Master_DisableIT_RXComplete + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_DisableIT_RXComplete(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->MSPIER, I2C_MSPIER_RXIE_Msk); +} + +/** + * @brief + * @rmtoll MSPISR WCOL FL_I2C_Master_IsActiveFlag_WriteConflict + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsActiveFlag_WriteConflict(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPISR, I2C_MSPISR_WCOL_Msk) == (I2C_MSPISR_WCOL_Msk)); +} + +/** + * @brief + * @rmtoll MSPISR WCOL FL_I2C_Master_ClearFlag_WriteConflict + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_ClearFlag_WriteConflict(I2C_Type *I2Cx) +{ + WRITE_REG(I2Cx->MSPISR, I2C_MSPISR_WCOL_Msk); +} + +/** + * @brief + * @rmtoll MSPISR TO FL_I2C_Master_IsActiveFlag_Timeout + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsActiveFlag_Timeout(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPISR, I2C_MSPISR_TO_Msk) == (I2C_MSPISR_TO_Msk)); +} + +/** + * @brief + * @rmtoll MSPISR TO FL_I2C_Master_ClearFlag_Timeout + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_ClearFlag_Timeout(I2C_Type *I2Cx) +{ + WRITE_REG(I2Cx->MSPISR, I2C_MSPISR_TO_Msk); +} + +/** + * @brief + * @rmtoll MSPISR S FL_I2C_Master_IsActiveFlag_Start + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsActiveFlag_Start(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPISR, I2C_MSPISR_S_Msk) == (I2C_MSPISR_S_Msk)); +} + +/** + * @brief + * @rmtoll MSPISR P FL_I2C_Master_IsActiveFlag_Stop + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsActiveFlag_Stop(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPISR, I2C_MSPISR_P_Msk) == (I2C_MSPISR_P_Msk)); +} + +/** + * @brief + * @rmtoll MSPISR ACKSTA FL_I2C_Master_IsActiveFlag_NACK + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsActiveFlag_NACK(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPISR, I2C_MSPISR_ACKSTA_Msk) == (I2C_MSPISR_ACKSTA_Msk)); +} + +/** + * @brief + * @rmtoll MSPISR ACKSTA FL_I2C_Master_ClearFlag_NACK + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_ClearFlag_NACK(I2C_Type *I2Cx) +{ + WRITE_REG(I2Cx->MSPISR, I2C_MSPISR_ACKSTA_Msk); +} + +/** + * @brief + * @rmtoll MSPISR TXIF FL_I2C_Master_IsActiveFlag_TXComplete + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsActiveFlag_TXComplete(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPISR, I2C_MSPISR_TXIF_Msk) == (I2C_MSPISR_TXIF_Msk)); +} + +/** + * @brief + * @rmtoll MSPISR TXIF FL_I2C_Master_ClearFlag_TXComplete + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_ClearFlag_TXComplete(I2C_Type *I2Cx) +{ + WRITE_REG(I2Cx->MSPISR, I2C_MSPISR_TXIF_Msk); +} + +/** + * @brief + * @rmtoll MSPISR RXIF FL_I2C_Master_IsActiveFlag_RXComplete + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsActiveFlag_RXComplete(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPISR, I2C_MSPISR_RXIF_Msk) == (I2C_MSPISR_RXIF_Msk)); +} + +/** + * @brief + * @rmtoll MSPISR RXIF FL_I2C_Master_ClearFlag_RXComplete + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_ClearFlag_RXComplete(I2C_Type *I2Cx) +{ + WRITE_REG(I2Cx->MSPISR, I2C_MSPISR_RXIF_Msk); +} + +/** + * @brief + * @rmtoll MSPSR BUSY FL_I2C_Master_IsActiveFlag_Busy + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Master_IsActiveFlag_Busy(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPSR, I2C_MSPSR_BUSY_Msk) == (I2C_MSPSR_BUSY_Msk)); +} + +/** + * @brief + * @rmtoll MSPSR RW FL_I2C_Master_GetDirection + * @param I2Cx I2C instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_I2C_MSP_DATA_DIRECTION_SLAVE_TO_MASTER + * @arg @ref FL_I2C_MSP_DATA_DIRECTION_MASTER_TO_SLAVE + */ +__STATIC_INLINE uint32_t FL_I2C_Master_GetDirection(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPSR, I2C_MSPSR_RW_Msk)); +} + +/** + * @brief + * @rmtoll MSPSR BF FL_I2C_Master_GetBuffStatus + * @param I2Cx I2C instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_I2C_MSP_DATA_BUFF_STATUS_FULL + * @arg @ref FL_I2C_MSP_DATA_BUFF_STATUS_EMPTY + */ +__STATIC_INLINE uint32_t FL_I2C_Master_GetBuffStatus(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPSR, I2C_MSPSR_BF_Msk)); +} + +/** + * @brief + * @rmtoll MSPSR ACKMO FL_I2C_Master_SetRespond + * @param I2Cx I2C instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_I2C_MASTER_RESPOND_ACK + * @arg @ref FL_I2C_MASTER_RESPOND_NACK + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_SetRespond(I2C_Type *I2Cx, uint32_t mode) +{ + MODIFY_REG(I2Cx->MSPSR, I2C_MSPSR_ACKMO_Msk, mode); +} + +/** + * @brief + * @rmtoll MSPSR ACKMO FL_I2C_Master_GetRespond + * @param I2Cx I2C instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_I2C_MASTER_RESPOND_ACK + * @arg @ref FL_I2C_MASTER_RESPOND_NACK + */ +__STATIC_INLINE uint32_t FL_I2C_Master_GetRespond(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPSR, I2C_MSPSR_ACKMO_Msk)); +} + +/** + * @brief + * @rmtoll MSPBGR MSPBGRH FL_I2C_Master_WriteSCLHighWidth + * @param I2Cx I2C instance + * @param width + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_WriteSCLHighWidth(I2C_Type *I2Cx, uint32_t width) +{ + MODIFY_REG(I2Cx->MSPBGR, (0x1ffU << 16U), (width << 16U)); +} + +/** + * @brief + * @rmtoll MSPBGR MSPBGRH FL_I2C_Master_ReadSCLHighWidth + * @param I2Cx I2C instance + * @retval + */ +__STATIC_INLINE uint32_t FL_I2C_Master_ReadSCLHighWidth(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPBGR, (0x1ffU << 16U)) >> 16U); +} + +/** + * @brief + * @rmtoll MSPBGR MSPBGRL FL_I2C_Master_WriteSCLLowWidth + * @param I2Cx I2C instance + * @param width + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_WriteSCLLowWidth(I2C_Type *I2Cx, uint32_t width) +{ + MODIFY_REG(I2Cx->MSPBGR, (0x1ffU << 0U), (width << 0U)); +} + +/** + * @brief + * @rmtoll MSPBGR MSPBGRL FL_I2C_Master_ReadSCLLowWidth + * @param I2Cx I2C instance + * @retval + */ +__STATIC_INLINE uint32_t FL_I2C_Master_ReadSCLLowWidth(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPBGR, (0x1ffU << 0U)) >> 0U); +} + +/** + * @brief + * @rmtoll MSPBUF MSPBUF FL_I2C_Master_WriteTXBuff + * @param I2Cx I2C instance + * @param data + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_WriteTXBuff(I2C_Type *I2Cx, uint32_t data) +{ + MODIFY_REG(I2Cx->MSPBUF, (0xffU << 0U), (data << 0U)); +} + +/** + * @brief + * @rmtoll MSPBUF MSPBUF FL_I2C_Master_ReadRXBuff + * @param I2Cx I2C instance + * @retval + */ +__STATIC_INLINE uint32_t FL_I2C_Master_ReadRXBuff(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPBUF, (0xffU << 0U)) >> 0U); +} + +/** + * @brief + * @rmtoll MSPTCR SDAHD FL_I2C_Master_WriteSDAHoldTime + * @param I2Cx I2C instance + * @param time + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_WriteSDAHoldTime(I2C_Type *I2Cx, uint32_t time) +{ + MODIFY_REG(I2Cx->MSPTCR, (0x1ffU << 0U), (time << 0U)); +} + +/** + * @brief + * @rmtoll MSPTCR SDAHD FL_I2C_Master_ReadSDAHoldTime + * @param I2Cx I2C instance + * @retval + */ +__STATIC_INLINE uint32_t FL_I2C_Master_ReadSDAHoldTime(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPTCR, (0x1ffU << 0U)) >> 0U); +} + +/** + * @brief + * @rmtoll MSPTOR TIMEOUT FL_I2C_Master_WriteSlaveSCLTimeout + * @param I2Cx I2C instance + * @param time + * @retval None + */ +__STATIC_INLINE void FL_I2C_Master_WriteSlaveSCLTimeout(I2C_Type *I2Cx, uint32_t time) +{ + MODIFY_REG(I2Cx->MSPTOR, (0xfffU << 0U), (time << 0U)); +} + +/** + * @brief + * @rmtoll MSPTOR TIMEOUT FL_I2C_Master_ReadSlaveSCLTimeout + * @param I2Cx I2C instance + * @retval + */ +__STATIC_INLINE uint32_t FL_I2C_Master_ReadSlaveSCLTimeout(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->MSPTOR, (0xfffU << 0U)) >> 0U); +} + +/** + * @brief + * @rmtoll SSPCR SCLSEN FL_I2C_Slave_EnableSCLStretching + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_EnableSCLStretching(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPCR, I2C_SSPCR_SCLSEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR SCLSEN FL_I2C_Slave_IsEnabledSCLStretching + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabledSCLStretching(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPCR, I2C_SSPCR_SCLSEN_Msk) == I2C_SSPCR_SCLSEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR SCLSEN FL_I2C_Slave_DisableSCLStretching + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_DisableSCLStretching(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPCR, I2C_SSPCR_SCLSEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR DMAEN FL_I2C_Slave_EnableDMAReq + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_EnableDMAReq(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPCR, I2C_SSPCR_DMAEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR DMAEN FL_I2C_Slave_IsEnabledDMAReq + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabledDMAReq(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPCR, I2C_SSPCR_DMAEN_Msk) == I2C_SSPCR_DMAEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR DMAEN FL_I2C_Slave_DisableDMAReq + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_DisableDMAReq(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPCR, I2C_SSPCR_DMAEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR ACKEN FL_I2C_Slave_EnableACK + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_EnableACK(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPCR, I2C_SSPCR_ACKEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR ACKEN FL_I2C_Slave_IsEnabledACK + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabledACK(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPCR, I2C_SSPCR_ACKEN_Msk) == I2C_SSPCR_ACKEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR ACKEN FL_I2C_Slave_DisableACK + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_DisableACK(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPCR, I2C_SSPCR_ACKEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR SDAO_DLYEN FL_I2C_Slave_EnableSDAStretching + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_EnableSDAStretching(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPCR, I2C_SSPCR_SDAO_DLYEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR SDAO_DLYEN FL_I2C_Slave_IsEnabledSDAStretching + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabledSDAStretching(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPCR, I2C_SSPCR_SDAO_DLYEN_Msk) == I2C_SSPCR_SDAO_DLYEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR SDAO_DLYEN FL_I2C_Slave_DisableSDAStretching + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_DisableSDAStretching(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPCR, I2C_SSPCR_SDAO_DLYEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR SCLI_ANFEN FL_I2C_Slave_EnableSCLAnalogFilter + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_EnableSCLAnalogFilter(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPCR, I2C_SSPCR_SCLI_ANFEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR SCLI_ANFEN FL_I2C_Slave_IsEnabledSCLAnalogFilter + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabledSCLAnalogFilter(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPCR, I2C_SSPCR_SCLI_ANFEN_Msk) == I2C_SSPCR_SCLI_ANFEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR SCLI_ANFEN FL_I2C_Slave_DisableSCLAnalogFilter + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_DisableSCLAnalogFilter(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPCR, I2C_SSPCR_SCLI_ANFEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR A10EN FL_I2C_Slave_Enable10BitAddress + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_Enable10BitAddress(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPCR, I2C_SSPCR_A10EN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR A10EN FL_I2C_Slave_IsEnabled10BitAddress + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabled10BitAddress(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPCR, I2C_SSPCR_A10EN_Msk) == I2C_SSPCR_A10EN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR A10EN FL_I2C_Slave_Disable10BitAddress + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_Disable10BitAddress(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPCR, I2C_SSPCR_A10EN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR SSPEN FL_I2C_Slave_Enable + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_Enable(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPCR, I2C_SSPCR_SSPEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR SSPEN FL_I2C_Slave_IsEnabled + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabled(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPCR, I2C_SSPCR_SSPEN_Msk) == I2C_SSPCR_SSPEN_Msk); +} + +/** + * @brief + * @rmtoll SSPCR SSPEN FL_I2C_Slave_Disable + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_Disable(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPCR, I2C_SSPCR_SSPEN_Msk); +} + +/** + * @brief + * @rmtoll SSPIER ADEIE FL_I2C_Slave_EnableIT_AddressError + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_EnableIT_AddressError(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPIER, I2C_SSPIER_ADEIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER ADEIE FL_I2C_Slave_IsEnabledIT_AddressError + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabledIT_AddressError(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPIER, I2C_SSPIER_ADEIE_Msk) == I2C_SSPIER_ADEIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER ADEIE FL_I2C_Slave_DisableIT_AddressError + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_DisableIT_AddressError(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPIER, I2C_SSPIER_ADEIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER SIE FL_I2C_Slave_EnableIT_Start + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_EnableIT_Start(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPIER, I2C_SSPIER_SIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER SIE FL_I2C_Slave_IsEnabledIT_Start + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabledIT_Start(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPIER, I2C_SSPIER_SIE_Msk) == I2C_SSPIER_SIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER SIE FL_I2C_Slave_DisableIT_Start + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_DisableIT_Start(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPIER, I2C_SSPIER_SIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER PIE FL_I2C_Slave_EnableIT_Stop + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_EnableIT_Stop(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPIER, I2C_SSPIER_PIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER PIE FL_I2C_Slave_IsEnabledIT_Stop + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabledIT_Stop(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPIER, I2C_SSPIER_PIE_Msk) == I2C_SSPIER_PIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER PIE FL_I2C_Slave_DisableIT_Stop + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_DisableIT_Stop(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPIER, I2C_SSPIER_PIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER WCOLIE FL_I2C_Slave_EnableIT_WriteConflict + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_EnableIT_WriteConflict(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPIER, I2C_SSPIER_WCOLIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER WCOLIE FL_I2C_Slave_IsEnabledIT_WriteConflict + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabledIT_WriteConflict(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPIER, I2C_SSPIER_WCOLIE_Msk) == I2C_SSPIER_WCOLIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER WCOLIE FL_I2C_Slave_DisableIT_WriteConflict + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_DisableIT_WriteConflict(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPIER, I2C_SSPIER_WCOLIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER SSPOVIE FL_I2C_Slave_EnableIT_BuffOverflow + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_EnableIT_BuffOverflow(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPIER, I2C_SSPIER_SSPOVIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER SSPOVIE FL_I2C_Slave_IsEnabledIT_BuffOverflow + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabledIT_BuffOverflow(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPIER, I2C_SSPIER_SSPOVIE_Msk) == I2C_SSPIER_SSPOVIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER SSPOVIE FL_I2C_Slave_DisableIT_BuffOverflow + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_DisableIT_BuffOverflow(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPIER, I2C_SSPIER_SSPOVIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER ADMIE FL_I2C_Slave_EnableIT_AddressMatch + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_EnableIT_AddressMatch(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPIER, I2C_SSPIER_ADMIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER ADMIE FL_I2C_Slave_IsEnabledIT_AddressMatch + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabledIT_AddressMatch(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPIER, I2C_SSPIER_ADMIE_Msk) == I2C_SSPIER_ADMIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER ADMIE FL_I2C_Slave_DisableIT_AddressMatch + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_DisableIT_AddressMatch(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPIER, I2C_SSPIER_ADMIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER TXIE FL_I2C_Slave_EnableIT_TXComplete + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_EnableIT_TXComplete(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPIER, I2C_SSPIER_TXIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER TXIE FL_I2C_Slave_IsEnabledIT_TXComplete + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabledIT_TXComplete(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPIER, I2C_SSPIER_TXIE_Msk) == I2C_SSPIER_TXIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER TXIE FL_I2C_Slave_DisableIT_TXComplete + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_DisableIT_TXComplete(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPIER, I2C_SSPIER_TXIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER RXIE FL_I2C_Slave_EnableIT_RXComplete + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_EnableIT_RXComplete(I2C_Type *I2Cx) +{ + SET_BIT(I2Cx->SSPIER, I2C_SSPIER_RXIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER RXIE FL_I2C_Slave_IsEnabledIT_RXComplete + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsEnabledIT_RXComplete(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPIER, I2C_SSPIER_RXIE_Msk) == I2C_SSPIER_RXIE_Msk); +} + +/** + * @brief + * @rmtoll SSPIER RXIE FL_I2C_Slave_DisableIT_RXCompleted + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_DisableIT_RXComplete(I2C_Type *I2Cx) +{ + CLEAR_BIT(I2Cx->SSPIER, I2C_SSPIER_RXIE_Msk); +} + +/** + * @brief + * @rmtoll SSPISR ADE FL_I2C_Slave_IsActiveFlag_AddressError + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsActiveFlag_AddressError(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPISR, I2C_SSPISR_ADE_Msk) == (I2C_SSPISR_ADE_Msk)); +} + +/** + * @brief + * @rmtoll SSPISR ADE FL_I2C_Slave_ClearFlag_AddressError + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_ClearFlag_AddressError(I2C_Type *I2Cx) +{ + WRITE_REG(I2Cx->SSPISR, I2C_SSPISR_ADE_Msk); +} + +/** + * @brief + * @rmtoll SSPISR S FL_I2C_Slave_IsActiveFlag_Start + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsActiveFlag_Start(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPISR, I2C_SSPISR_S_Msk) == (I2C_SSPISR_S_Msk)); +} + +/** + * @brief + * @rmtoll SSPISR P FL_I2C_Slave_IsActiveFlag_Stop + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsActiveFlag_Stop(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPISR, I2C_SSPISR_P_Msk) == (I2C_SSPISR_P_Msk)); +} + +/** + * @brief + * @rmtoll SSPISR WCOL FL_I2C_Slave_IsActiveFlag_WriteConflict + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsActiveFlag_WriteConflict(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPISR, I2C_SSPISR_WCOL_Msk) == (I2C_SSPISR_WCOL_Msk)); +} + +/** + * @brief + * @rmtoll SSPISR WCOL FL_I2C_Slave_ClearFlag_WriteConflict + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_ClearFlag_WriteConflict(I2C_Type *I2Cx) +{ + WRITE_REG(I2Cx->SSPISR, I2C_SSPISR_WCOL_Msk); +} + +/** + * @brief + * @rmtoll SSPISR SSPOV FL_I2C_Slave_IsActiveFlag_BuffOverflow + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsActiveFlag_BuffOverflow(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPISR, I2C_SSPISR_SSPOV_Msk) == (I2C_SSPISR_SSPOV_Msk)); +} +/** + * @brief + * @rmtoll SSPISR SSPOV FL_I2C_Slave_ClearFlag_BuffOverflow + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_ClearFlag_BuffOverflow(I2C_Type *I2Cx) +{ + WRITE_REG(I2Cx->SSPISR, I2C_SSPISR_SSPOV_Msk); +} + +/** + * @brief + * @rmtoll SSPISR ADM FL_I2C_Slave_IsActiveFlag_AddressMatch + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsActiveFlag_AddressMatch(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPISR, I2C_SSPISR_ADM_Msk) == (I2C_SSPISR_ADM_Msk)); +} + +/** + * @brief + * @rmtoll SSPISR ADM FL_I2C_Slave_ClearFlag_AddressMatch + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_ClearFlag_AddressMatch(I2C_Type *I2Cx) +{ + WRITE_REG(I2Cx->SSPISR, I2C_SSPISR_ADM_Msk); +} + +/** + * @brief + * @rmtoll SSPISR TXIF FL_I2C_Slave_IsActiveFlag_TXComplete + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsActiveFlag_TXComplete(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPISR, I2C_SSPISR_TXIF_Msk) == (I2C_SSPISR_TXIF_Msk)); +} + +/** + * @brief + * @rmtoll SSPISR TXIF FL_I2C_Slave_ClearFlag_TXComplete + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_ClearFlag_TXComplete(I2C_Type *I2Cx) +{ + WRITE_REG(I2Cx->SSPISR, I2C_SSPISR_TXIF_Msk); +} + +/** + * @brief + * @rmtoll SSPISR RXIF FL_I2C_Slave_IsActiveFlag_RXComplete + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsActiveFlag_RXComplete(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPISR, I2C_SSPISR_RXIF_Msk) == (I2C_SSPISR_RXIF_Msk)); +} + +/** + * @brief + * @rmtoll SSPISR RXIF FL_I2C_Slave_ClearFlag_RXComplete + * @param I2Cx I2C instance + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_ClearFlag_RXComplete(I2C_Type *I2Cx) +{ + WRITE_REG(I2Cx->SSPISR, I2C_SSPISR_RXIF_Msk); +} + +/** + * @brief + * @rmtoll SSPSR BUSY FL_I2C_Slave_IsActiveFlag_Busy + * @param I2Cx I2C instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_IsActiveFlag_Busy(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPSR, I2C_SSPSR_BUSY_Msk) == (I2C_SSPSR_BUSY_Msk)); +} + +/** + * @brief + * @rmtoll SSPSR RW FL_I2C_Slave_GetDataDirection + * @param I2Cx I2C instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_I2C_SSP_DATA_DIRECTION_SLAVE_TO_MASTER + * @arg @ref FL_I2C_SSP_DATA_DIRECTION_MASTER_TO_SLAVE + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_GetDataDirection(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPSR, I2C_SSPSR_RW_Msk)); +} + +/** + * @brief + * @rmtoll SSPSR DA FL_I2C_Slave_GetDataType + * @param I2Cx I2C instance + * @param I2Cx I2C instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_I2C_SSP_DATA_TYPE_DATA + * @arg @ref FL_I2C_SSP_DATA_TYPE_ADDR + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_GetDataType(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPSR, I2C_SSPSR_DA_Msk)); +} +/** + * @brief + * @rmtoll SSPSR BF FL_I2C_Slave_GetBuffStatus + * @param I2Cx I2C instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_I2C_SSP_DATA_BUFF_STATUS_FULL + * @arg @ref FL_I2C_SSP_DATA_BUFF_STATUS_EMPTY + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_GetBuffStatus(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPSR, I2C_SSPSR_BF_Msk)); +} + +/** + * @brief + * @rmtoll SSPBUF FL_I2C_Slave_WriteTXBuff + * @param I2Cx I2C instance + * @param data + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_WriteTXBuff(I2C_Type *I2Cx, uint32_t data) +{ + MODIFY_REG(I2Cx->SSPBUF, (0xffU << 0U), (data << 0U)); +} + +/** + * @brief + * @rmtoll SSPBUF FL_I2C_Slave_ReadRXBuff + * @param I2Cx I2C instance + * @retval + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_ReadRXBuff(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPBUF, (0xffU << 0U)) >> 0U); +} + +/** + * @brief + * @rmtoll SSPADR FL_I2C_Slave_WriteSlaveAddress + * @param I2Cx I2C instance + * @param address + * @retval None + */ +__STATIC_INLINE void FL_I2C_Slave_WriteSlaveAddress(I2C_Type *I2Cx, uint32_t address) +{ + MODIFY_REG(I2Cx->SSPADR, (0x3ffU << 0U), (address << 0U)); +} + +/** + * @brief + * @rmtoll SSPADR FL_I2C_Slave_ReadSlaveAddress + * @param I2Cx I2C instance + * @retval + */ +__STATIC_INLINE uint32_t FL_I2C_Slave_ReadSlaveAddress(I2C_Type *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SSPADR, (0x3ffU << 0U)) >> 0U); +} + +/** + * @} + */ + +/** @defgroup I2C_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_I2C_DeInit(I2C_Type *I2Cx); +void FL_I2C_SlaveMode_StructInit(FL_I2C_SlaveMode_InitTypeDef *I2C_InitStruct); +void FL_I2C_MasterMode_StructInit(FL_I2C_MasterMode_InitTypeDef *I2C_InitStruct); +FL_ErrorStatus FL_I2C_SlaveMode_Init(I2C_Type *I2cx, FL_I2C_SlaveMode_InitTypeDef *I2C_InitStruct); +FL_ErrorStatus FL_I2C_MasterMode_Init(I2C_Type *I2Cx, FL_I2C_MasterMode_InitTypeDef *I2C_InitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_I2C_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-12*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_iwdt.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_iwdt.h new file mode 100644 index 0000000000..baee4b3291 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_iwdt.h @@ -0,0 +1,309 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_iwdt.h + * @author FMSH Application Team + * @brief Head file of IWDT FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_IWDT_H +#define __FM33LC0XX_FL_IWDT_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup IWDT IWDT + * @brief IWDT FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup IWDT_FL_ES_INIT IWDT Exported Init structures + * @{ + */ + +/** + * @brief IWDT Init Sturcture definition + */ +typedef struct +{ + /** 看门狗溢出时间 */ + uint32_t overflowPeriod; + /** 清狗窗口 */ + uint32_t iwdtWindows; + +} FL_IWDT_InitTypeDef; + +/** + * @} + */ + +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup IWDT_FL_Exported_Constants IWDT Exported Constants + * @{ + */ + +#define IWDT_CR_FREEZE_Pos (11U) +#define IWDT_CR_FREEZE_Msk (0x1U << IWDT_CR_FREEZE_Pos) +#define IWDT_CR_FREEZE IWDT_CR_FREEZE_Msk + +#define IWDT_CR_CFG_Pos (0U) +#define IWDT_CR_CFG_Msk (0x7U << IWDT_CR_CFG_Pos) +#define IWDT_CR_CFG IWDT_CR_CFG_Msk + +#define IWDT_IER_IE_Pos (0U) +#define IWDT_IER_IE_Msk (0x1U << IWDT_IER_IE_Pos) +#define IWDT_IER_IE IWDT_IER_IE_Msk + +#define IWDT_ISR_WINF_Pos (0U) +#define IWDT_ISR_WINF_Msk (0x1U << IWDT_ISR_WINF_Pos) +#define IWDT_ISR_WINF IWDT_ISR_WINF_Msk + + + +#define FL_IWDT_RELOAD_KEY 0x12345A5AU + + + +#define FL_IWDT_PERIOD_125MS (0x0U << IWDT_CR_CFG_Pos) +#define FL_IWDT_PERIOD_250MS (0x1U << IWDT_CR_CFG_Pos) +#define FL_IWDT_PERIOD_500MS (0x2U << IWDT_CR_CFG_Pos) +#define FL_IWDT_PERIOD_1000MS (0x3U << IWDT_CR_CFG_Pos) +#define FL_IWDT_PERIOD_2000MS (0x4U << IWDT_CR_CFG_Pos) +#define FL_IWDT_PERIOD_4000MS (0x5U << IWDT_CR_CFG_Pos) +#define FL_IWDT_PERIOD_8000MS (0x6U << IWDT_CR_CFG_Pos) +#define FL_IWDT_PERIOD_16000MS (0x7U << IWDT_CR_CFG_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup IWDT_FL_Exported_Functions IWDT Exported Functions + * @{ + */ + +/** + * @brief Set IWDT service register + * @rmtoll SERV FL_IWDT_ReloadCounter + * @param IWDTx IWDT instance + * @retval None + */ +__STATIC_INLINE void FL_IWDT_ReloadCounter(IWDT_Type *IWDTx) +{ + IWDTx->SERV = FL_IWDT_RELOAD_KEY; +} + +/** + * @brief Set freeze in sleep enable + * @rmtoll CR FREEZE FL_IWDT_EnableFreezeWhileSleep + * @param IWDTx IWDT instance + * @retval None + */ +__STATIC_INLINE void FL_IWDT_EnableFreezeWhileSleep(IWDT_Type *IWDTx) +{ + SET_BIT(IWDTx->CR, IWDT_CR_FREEZE_Msk); +} + +/** + * @brief Set freeze in sleep disable + * @rmtoll CR FREEZE FL_IWDT_DisableFreezeWhileSleep + * @param IWDTx IWDT instance + * @retval None + */ +__STATIC_INLINE void FL_IWDT_DisableFreezeWhileSleep(IWDT_Type *IWDTx) +{ + CLEAR_BIT(IWDTx->CR, IWDT_CR_FREEZE_Msk); +} + +/** + * @brief Get freeze in sleep enable status + * @rmtoll CR FREEZE FL_IWDT_IsEnabledFreezeWhileSleep + * @param IWDTx IWDT instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_IWDT_IsEnabledFreezeWhileSleep(IWDT_Type *IWDTx) +{ + return (uint32_t)(READ_BIT(IWDTx->CR, IWDT_CR_FREEZE_Msk) == IWDT_CR_FREEZE_Msk); +} + +/** + * @brief Set IWDT overflow period + * @rmtoll CR CFG FL_IWDT_SetPeriod + * @param IWDTx IWDT instance + * @param period This parameter can be one of the following values: + * @arg @ref FL_IWDT_PERIOD_125MS + * @arg @ref FL_IWDT_PERIOD_250MS + * @arg @ref FL_IWDT_PERIOD_500MS + * @arg @ref FL_IWDT_PERIOD_1000MS + * @arg @ref FL_IWDT_PERIOD_2000MS + * @arg @ref FL_IWDT_PERIOD_4000MS + * @arg @ref FL_IWDT_PERIOD_8000MS + * @arg @ref FL_IWDT_PERIOD_16000MS + * @retval None + */ +__STATIC_INLINE void FL_IWDT_SetPeriod(IWDT_Type *IWDTx, uint32_t period) +{ + MODIFY_REG(IWDTx->CR, IWDT_CR_CFG_Msk, period); +} + +/** + * @brief Get IWDT overflow period + * @rmtoll CR CFG FL_IWDT_GetPeriod + * @param IWDTx IWDT instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_IWDT_PERIOD_125MS + * @arg @ref FL_IWDT_PERIOD_250MS + * @arg @ref FL_IWDT_PERIOD_500MS + * @arg @ref FL_IWDT_PERIOD_1000MS + * @arg @ref FL_IWDT_PERIOD_2000MS + * @arg @ref FL_IWDT_PERIOD_4000MS + * @arg @ref FL_IWDT_PERIOD_8000MS + * @arg @ref FL_IWDT_PERIOD_16000MS + */ +__STATIC_INLINE uint32_t FL_IWDT_GetPeriod(IWDT_Type *IWDTx) +{ + return (uint32_t)(READ_BIT(IWDTx->CR, IWDT_CR_CFG_Msk)); +} + +/** + * @brief Get IWDT current counter value + * @rmtoll CNT FL_IWDT_ReadCounter + * @param IWDTx IWDT instance + * @retval + */ +__STATIC_INLINE uint32_t FL_IWDT_ReadCounter(IWDT_Type *IWDTx) +{ + return (uint32_t)(READ_BIT(IWDTx->CNT, (0xfffU << 0U)) >> 0U); +} + +/** + * @brief Set IWDT window register + * @rmtoll WIN FL_IWDT_WriteWindow + * @param IWDTx IWDT instance + * @param value + * @retval None + */ +__STATIC_INLINE void FL_IWDT_WriteWindow(IWDT_Type *IWDTx, uint32_t value) +{ + MODIFY_REG(IWDTx->WIN, (0xfffU << 0U), (value << 0U)); +} + +/** + * @brief Get IWDT window register + * @rmtoll WIN FL_IWDT_ReadWindow + * @param IWDTx IWDT instance + * @retval + */ +__STATIC_INLINE uint32_t FL_IWDT_ReadWindow(IWDT_Type *IWDTx) +{ + return (uint32_t)(READ_BIT(IWDTx->WIN, (0xfffU << 0U)) >> 0U); +} + +/** + * @brief IWDT interrupt enable + * @rmtoll IER IE FL_IWDT_EnableIT_EnterWindow + * @param IWDTx IWDT instance + * @retval None + */ +__STATIC_INLINE void FL_IWDT_EnableIT_EnterWindow(IWDT_Type *IWDTx) +{ + SET_BIT(IWDTx->IER, IWDT_IER_IE_Msk); +} + +/** + * @brief IWDT interrupt disable + * @rmtoll IER IE FL_IWDT_DisableIT_EnterWindow + * @param IWDTx IWDT instance + * @retval None + */ +__STATIC_INLINE void FL_IWDT_DisableIT_EnterWindow(IWDT_Type *IWDTx) +{ + CLEAR_BIT(IWDTx->IER, IWDT_IER_IE_Msk); +} + +/** + * @brief Get IWDT interrupt enable status + * @rmtoll IER IE FL_IWDT_IsEnabledIT_EnterWindow + * @param IWDTx IWDT instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_IWDT_IsEnabledIT_EnterWindow(IWDT_Type *IWDTx) +{ + return (uint32_t)(READ_BIT(IWDTx->IER, IWDT_IER_IE_Msk) == IWDT_IER_IE_Msk); +} + +/** + * @brief Get IWDT window interrupt flag + * @rmtoll ISR WINF FL_IWDT_IsActiveFlag_EnterWindow + * @param IWDTx IWDT instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_IWDT_IsActiveFlag_EnterWindow(IWDT_Type *IWDTx) +{ + return (uint32_t)(READ_BIT(IWDTx->ISR, IWDT_ISR_WINF_Msk) == (IWDT_ISR_WINF_Msk)); +} + +/** + * @brief Clear IWDT window interrupt flag + * @rmtoll ISR WINF FL_IWDT_ClearFlag_EnterWindow + * @param IWDTx IWDT instance + * @retval None + */ +__STATIC_INLINE void FL_IWDT_ClearFlag_EnterWindow(IWDT_Type *IWDTx) +{ + WRITE_REG(IWDTx->ISR, IWDT_ISR_WINF_Msk); +} + +/** + * @} + */ + +/** @defgroup IWDT_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_IWDT_DeInit(IWDT_Type *IWDTx); +void FL_IWDT_StructInit(FL_IWDT_InitTypeDef *IWDT_InitStruct); +FL_ErrorStatus FL_IWDT_Init(IWDT_Type *IWDTx, FL_IWDT_InitTypeDef *IWDT_InitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_IWDT_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-27*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_lcd.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_lcd.h new file mode 100644 index 0000000000..0229a12c9e --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_lcd.h @@ -0,0 +1,1015 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_lcd.h + * @author FMSH Application Team + * @brief Head file of LCD FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_LCD_H +#define __FM33LC0XX_FL_LCD_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup LCD LCD + * @brief LCD FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup LCD_FL_ES_INIT LCD Exported Init structures + * @{ + */ + +/** + * @brief LCD Init Sturcture definition + */ +typedef struct +{ + /*! 电流源大小控制 */ + uint32_t biasCurrent; + /*! 驱动模式 */ + uint32_t mode; + /*! 偏执电平 */ + uint32_t biasVoltage; + /*! 偏执类型 */ + uint32_t biasMode; + /*! 驱动波形 */ + uint32_t waveform; + /*! COM数目 */ + uint32_t COMxNum; + /*! 显示频率 */ + uint32_t displayFreq; + /*! 显示闪烁点亮时间(ms) */ + uint32_t flickOnTime; + /*! 显示闪烁熄灭时间(ms) */ + uint32_t flickOffTime; +} FL_LCD_InitTypeDef; + +/** + * @} + */ + +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup LCD_FL_Exported_Constants LCD Exported Constants + * @{ + */ + +#define LCD_CR_IC_CTRL_Pos (16U) +#define LCD_CR_IC_CTRL_Msk (0x3U << LCD_CR_IC_CTRL_Pos) +#define LCD_CR_IC_CTRL LCD_CR_IC_CTRL_Msk + +#define LCD_CR_ENMODE_Pos (15U) +#define LCD_CR_ENMODE_Msk (0x1U << LCD_CR_ENMODE_Pos) +#define LCD_CR_ENMODE LCD_CR_ENMODE_Msk + +#define LCD_CR_FLICK_Pos (14U) +#define LCD_CR_FLICK_Msk (0x1U << LCD_CR_FLICK_Pos) +#define LCD_CR_FLICK LCD_CR_FLICK_Msk + +#define LCD_CR_BIAS_Pos (8U) +#define LCD_CR_BIAS_Msk (0xfU << LCD_CR_BIAS_Pos) +#define LCD_CR_BIAS LCD_CR_BIAS_Msk + +#define LCD_CR_BIASMD_Pos (5U) +#define LCD_CR_BIASMD_Msk (0x1U << LCD_CR_BIASMD_Pos) +#define LCD_CR_BIASMD LCD_CR_BIASMD_Msk + +#define LCD_CR_ANTIPOLAR_Pos (4U) +#define LCD_CR_ANTIPOLAR_Msk (0x1U << LCD_CR_ANTIPOLAR_Pos) +#define LCD_CR_ANTIPOLAR LCD_CR_ANTIPOLAR_Msk + +#define LCD_CR_WFT_Pos (3U) +#define LCD_CR_WFT_Msk (0x1U << LCD_CR_WFT_Pos) +#define LCD_CR_WFT LCD_CR_WFT_Msk + +#define LCD_CR_LMUX_Pos (1U) +#define LCD_CR_LMUX_Msk (0x3U << LCD_CR_LMUX_Pos) +#define LCD_CR_LMUX LCD_CR_LMUX_Msk + +#define LCD_CR_EN_Pos (0U) +#define LCD_CR_EN_Msk (0x1U << LCD_CR_EN_Pos) +#define LCD_CR_EN LCD_CR_EN_Msk + +#define LCD_FCR_DF_Pos (0U) +#define LCD_FCR_DF_Msk (0xffU << LCD_FCR_DF_Pos) +#define LCD_FCR_DF LCD_FCR_DF_Msk + +#define LCD_FLKT_TOFF_Pos (8U) +#define LCD_FLKT_TOFF_Msk (0xffU << LCD_FLKT_TOFF_Pos) +#define LCD_FLKT_TOFF LCD_FLKT_TOFF_Msk + +#define LCD_FLKT_TON_Pos (0U) +#define LCD_FLKT_TON_Msk (0xffU << LCD_FLKT_TON_Pos) +#define LCD_FLKT_TON LCD_FLKT_TON_Msk + +#define LCD_IER_DONIE_Pos (1U) +#define LCD_IER_DONIE_Msk (0x1U << LCD_IER_DONIE_Pos) +#define LCD_IER_DONIE LCD_IER_DONIE_Msk + +#define LCD_IER_DOFFIE_Pos (0U) +#define LCD_IER_DOFFIE_Msk (0x1U << LCD_IER_DOFFIE_Pos) +#define LCD_IER_DOFFIE LCD_IER_DOFFIE_Msk + +#define LCD_ISR_DONIF_Pos (1U) +#define LCD_ISR_DONIF_Msk (0x1U << LCD_ISR_DONIF_Pos) +#define LCD_ISR_DONIF LCD_ISR_DONIF_Msk + +#define LCD_ISR_DOFFIF_Pos (0U) +#define LCD_ISR_DOFFIF_Msk (0x1U << LCD_ISR_DOFFIF_Pos) +#define LCD_ISR_DOFFIF LCD_ISR_DOFFIF_Msk + +#define LCD_DATA0_DSDA_Pos (0U) +#define LCD_DATA0_DSDA_Msk (0xffffffffU << LCD_DATA0_DSDA_Pos) +#define LCD_DATA0_DSDA LCD_DATA0_DSDA_Msk + + + +#define FL_LCD_DATA_REG0 (0x0U << 0U) +#define FL_LCD_DATA_REG1 (0x1U << 0U) +#define FL_LCD_DATA_REG2 (0x2U << 0U) +#define FL_LCD_DATA_REG3 (0x3U << 0U) +#define FL_LCD_DATA_REG4 (0x4U << 0U) +#define FL_LCD_DATA_REG5 (0x5U << 0U) +#define FL_LCD_DATA_REG6 (0x6U << 0U) +#define FL_LCD_DATA_REG7 (0x7U << 0U) +#define FL_LCD_COMEN_COM0 (0x1U << 0U) +#define FL_LCD_COMEN_COM1 (0x1U << 1U) +#define FL_LCD_COMEN_COM2 (0x1U << 2U) +#define FL_LCD_COMEN_COM3 (0x1U << 3U) +#define FL_LCD_COMEN_COM4 (0x1U << 28U) +#define FL_LCD_COMEN_COM5 (0x1U << 29U) +#define FL_LCD_COMEN_COM6 (0x1U << 30U) +#define FL_LCD_COMEN_COM7 (0x1U << 31U) +#define FL_LCD_SEGEN0_SEG0 (0x1U << 0U) +#define FL_LCD_SEGEN0_SEG1 (0x1U << 1U) +#define FL_LCD_SEGEN0_SEG2 (0x1U << 2U) +#define FL_LCD_SEGEN0_SEG3 (0x1U << 3U) +#define FL_LCD_SEGEN0_SEG4 (0x1U << 4U) +#define FL_LCD_SEGEN0_SEG5 (0x1U << 5U) +#define FL_LCD_SEGEN0_SEG6 (0x1U << 6U) +#define FL_LCD_SEGEN0_SEG7 (0x1U << 7U) +#define FL_LCD_SEGEN0_SEG8 (0x1U << 8U) +#define FL_LCD_SEGEN0_SEG9 (0x1U << 9U) +#define FL_LCD_SEGEN0_SEG10 (0x1U << 10U) +#define FL_LCD_SEGEN0_SEG11 (0x1U << 11U) +#define FL_LCD_SEGEN0_SEG12 (0x1U << 12U) +#define FL_LCD_SEGEN0_SEG13 (0x1U << 13U) +#define FL_LCD_SEGEN0_SEG14 (0x1U << 14U) +#define FL_LCD_SEGEN0_SEG15 (0x1U << 15U) +#define FL_LCD_SEGEN0_SEG16 (0x1U << 16U) +#define FL_LCD_SEGEN0_SEG17 (0x1U << 17U) +#define FL_LCD_SEGEN0_SEG18 (0x1U << 18U) +#define FL_LCD_SEGEN0_SEG19 (0x1U << 19U) +#define FL_LCD_SEGEN0_SEG20 (0x1U << 20U) +#define FL_LCD_SEGEN0_SEG21 (0x1U << 21U) +#define FL_LCD_SEGEN0_SEG22 (0x1U << 22U) +#define FL_LCD_SEGEN0_SEG23 (0x1U << 23U) +#define FL_LCD_SEGEN0_SEG24 (0x1U << 24U) +#define FL_LCD_SEGEN0_SEG25 (0x1U << 25U) +#define FL_LCD_SEGEN0_SEG26 (0x1U << 26U) +#define FL_LCD_SEGEN0_SEG27 (0x1U << 27U) +#define FL_LCD_SEGEN0_SEG28 (0x1U << 28U) +#define FL_LCD_SEGEN0_SEG29 (0x1U << 29U) +#define FL_LCD_SEGEN0_SEG30 (0x1U << 30U) +#define FL_LCD_SEGEN0_SEG31 (0x1U << 31U) + + + +#define FL_LCD_BIAS_CURRENT_VERYHIGH (0x0U << LCD_CR_IC_CTRL_Pos) +#define FL_LCD_BIAS_CURRENT_HIGH (0x1U << LCD_CR_IC_CTRL_Pos) +#define FL_LCD_BIAS_CURRENT_MEDIUM (0x2U << LCD_CR_IC_CTRL_Pos) +#define FL_LCD_BIAS_CURRENT_LOW (0x3U << LCD_CR_IC_CTRL_Pos) + + +#define FL_LCD_DRIVER_MODE_INNER_RESISTER (0x1U << LCD_CR_ENMODE_Pos) + + +#define FL_LCD_BIAS_VOLTAGE_LEVEL0 (0x0U << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL1 (0x1U << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL2 (0x2U << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL3 (0x3U << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL4 (0x4U << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL5 (0x5U << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL6 (0x6U << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL7 (0x7U << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL8 (0x8U << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL9 (0x9U << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL10 (0xaU << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL11 (0xbU << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL12 (0xcU << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL13 (0xdU << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL14 (0xeU << LCD_CR_BIAS_Pos) +#define FL_LCD_BIAS_VOLTAGE_LEVEL15 (0xfU << LCD_CR_BIAS_Pos) + + +#define FL_LCD_BIAS_MODE_4BIAS (0x0U << LCD_CR_BIASMD_Pos) +#define FL_LCD_BIAS_MODE_3BIAS (0x1U << LCD_CR_BIASMD_Pos) + + +#define FL_LCD_ANTIPOLAR_FLOATING (0x0U << LCD_CR_ANTIPOLAR_Pos) +#define FL_LCD_ANTIPOLAR_GND (0x1U << LCD_CR_ANTIPOLAR_Pos) + +#define FL_LCD_WAVEFORM_TYPEA (0x0U << LCD_CR_WFT_Pos) +#define FL_LCD_WAVEFORM_TYPEB (0x1U << LCD_CR_WFT_Pos) + + +#define FL_LCD_COM_NUM_4COM (0x0U << LCD_CR_LMUX_Pos) +#define FL_LCD_COM_NUM_6COM (0x1U << LCD_CR_LMUX_Pos) +#define FL_LCD_COM_NUM_8COM (0x2U << LCD_CR_LMUX_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup LCD_FL_Exported_Functions LCD Exported Functions + * @{ + */ + +/** + * @brief Set Input Bias Current + * @rmtoll CR IC_CTRL FL_LCD_SetBiasCurrent + * @param LCDx LCD instance + * @param current This parameter can be one of the following values: + * @arg @ref FL_LCD_BIAS_CURRENT_VERYHIGH + * @arg @ref FL_LCD_BIAS_CURRENT_HIGH + * @arg @ref FL_LCD_BIAS_CURRENT_MEDIUM + * @arg @ref FL_LCD_BIAS_CURRENT_LOW + * @retval None + */ +__STATIC_INLINE void FL_LCD_SetBiasCurrent(LCD_Type *LCDx, uint32_t current) +{ + MODIFY_REG(LCDx->CR, LCD_CR_IC_CTRL_Msk, current); +} + +/** + * @brief Set Input Bias Current + * @rmtoll CR IC_CTRL FL_LCD_GetBiasCurrent + * @param LCDx LCD instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LCD_BIAS_CURRENT_VERYHIGH + * @arg @ref FL_LCD_BIAS_CURRENT_HIGH + * @arg @ref FL_LCD_BIAS_CURRENT_MEDIUM + * @arg @ref FL_LCD_BIAS_CURRENT_LOW + */ +__STATIC_INLINE uint32_t FL_LCD_GetBiasCurrent(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->CR, LCD_CR_IC_CTRL_Msk)); +} + +/** + * @brief Set LCD Enabling Mode + * @rmtoll CR ENMODE FL_LCD_SetDriverMode + * @param LCDx LCD instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_LCD_DRIVER_MODE_INNER_RESISTER + * @retval None + */ +__STATIC_INLINE void FL_LCD_SetDriverMode(LCD_Type *LCDx, uint32_t mode) +{ + MODIFY_REG(LCDx->CR, LCD_CR_ENMODE_Msk, mode); +} + +/** + * @brief Get LCD Enabling Mode + * @rmtoll CR ENMODE FL_LCD_GetDriverMode + * @param LCDx LCD instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LCD_DRIVER_MODE_INNER_RESISTER + */ +__STATIC_INLINE uint32_t FL_LCD_GetDriverMode(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->CR, LCD_CR_ENMODE_Msk)); +} + +/** + * @brief Enable LCD Blink + * @rmtoll CR FLICK FL_LCD_EnableDisplayBlink + * @param LCDx LCD instance + * @retval None + */ +__STATIC_INLINE void FL_LCD_EnableDisplayBlink(LCD_Type *LCDx) +{ + SET_BIT(LCDx->CR, LCD_CR_FLICK_Msk); +} + +/** + * @brief Disable LCD Blink + * @rmtoll CR FLICK FL_LCD_DisableDisplayBlink + * @param LCDx LCD instance + * @retval None + */ +__STATIC_INLINE void FL_LCD_DisableDisplayBlink(LCD_Type *LCDx) +{ + CLEAR_BIT(LCDx->CR, LCD_CR_FLICK_Msk); +} + +/** + * @brief Get LCD Blink State + * @rmtoll CR FLICK FL_LCD_IsEnabledDisplayBlink + * @param LCDx LCD instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LCD_IsEnabledDisplayBlink(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->CR, LCD_CR_FLICK_Msk) == LCD_CR_FLICK_Msk); +} + +/** + * @brief Set LCD Bias Voltage Select + * @rmtoll CR BIAS FL_LCD_SetBiasVoltage + * @param LCDx LCD instance + * @param voltage This parameter can be one of the following values: + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL0 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL1 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL2 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL3 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL4 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL5 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL6 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL7 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL8 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL9 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL10 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL11 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL12 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL13 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL14 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL15 + * @retval None + */ +__STATIC_INLINE void FL_LCD_SetBiasVoltage(LCD_Type *LCDx, uint32_t voltage) +{ + MODIFY_REG(LCDx->CR, LCD_CR_BIAS_Msk, voltage); +} + +/** + * @brief Get LCD Bias Voltage Select + * @rmtoll CR BIAS FL_LCD_GetBiasVoltage + * @param LCDx LCD instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL0 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL1 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL2 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL3 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL4 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL5 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL6 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL7 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL8 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL9 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL10 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL11 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL12 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL13 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL14 + * @arg @ref FL_LCD_BIAS_VOLTAGE_LEVEL15 + */ +__STATIC_INLINE uint32_t FL_LCD_GetBiasVoltage(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->CR, LCD_CR_BIAS_Msk)); +} + +/** + * @brief Set LCD Bias Mode + * @rmtoll CR BIASMD FL_LCD_SetBiasMode + * @param LCDx LCD instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_LCD_BIAS_MODE_4BIAS + * @arg @ref FL_LCD_BIAS_MODE_3BIAS + * @retval None + */ +__STATIC_INLINE void FL_LCD_SetBiasMode(LCD_Type *LCDx, uint32_t mode) +{ + MODIFY_REG(LCDx->CR, LCD_CR_BIASMD_Msk, mode); +} + +/** + * @brief Get LCD Bias Mode + * @rmtoll CR BIASMD FL_LCD_GetBiasMode + * @param LCDx LCD instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LCD_BIAS_MODE_4BIAS + * @arg @ref FL_LCD_BIAS_MODE_3BIAS + */ +__STATIC_INLINE uint32_t FL_LCD_GetBiasMode(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->CR, LCD_CR_BIASMD_Msk)); +} + +/** + * @brief Set LCD Anti-Polarization + * @rmtoll CR ANTIPOLAR FL_LCD_SetAntiPolar + * @param LCDx LCD instance + * @param state This parameter can be one of the following values: + * @arg @ref FL_LCD_ANTIPOLAR_FLOATING + * @arg @ref FL_LCD_ANTIPOLAR_GND + * @retval None + */ +__STATIC_INLINE void FL_LCD_SetAntiPolar(LCD_Type *LCDx, uint32_t state) +{ + MODIFY_REG(LCDx->CR, LCD_CR_ANTIPOLAR_Msk, state); +} + +/** + * @brief Get LCD Anti-Polarization + * @rmtoll CR ANTIPOLAR FL_LCD_GetAntiPolar + * @param LCDx LCD instance + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_LCD_GetAntiPolar(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->CR, LCD_CR_ANTIPOLAR_Msk)); +} + +/** + * @brief Set LCD Waveform Format + * @rmtoll CR WFT FL_LCD_SetWaveform + * @param LCDx LCD instance + * @param state This parameter can be one of the following values: + * @arg @ref FL_LCD_WAVEFORM_TYPEA + * @arg @ref FL_LCD_WAVEFORM_TYPEB + * @retval None + */ +__STATIC_INLINE void FL_LCD_SetWaveform(LCD_Type *LCDx, uint32_t state) +{ + MODIFY_REG(LCDx->CR, LCD_CR_WFT_Msk, state); +} + +/** + * @brief Get LCD Waveform Format + * @rmtoll CR WFT FL_LCD_GetWaveform + * @param LCDx LCD instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LCD_WAVEFORM_TYPEA + * @arg @ref FL_LCD_WAVEFORM_TYPEB + */ +__STATIC_INLINE uint32_t FL_LCD_GetWaveform(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->CR, LCD_CR_WFT_Msk)); +} + +/** + * @brief Set LCD Segment Line Mux + * @rmtoll CR LMUX FL_LCD_SetCOMNumber + * @param LCDx LCD instance + * @param number This parameter can be one of the following values: + * @arg @ref FL_LCD_COM_NUM_4COM + * @arg @ref FL_LCD_COM_NUM_6COM + * @arg @ref FL_LCD_COM_NUM_8COM + * @retval None + */ +__STATIC_INLINE void FL_LCD_SetCOMNumber(LCD_Type *LCDx, uint32_t number) +{ + MODIFY_REG(LCDx->CR, LCD_CR_LMUX_Msk, number); +} + +/** + * @brief Get LCD Segment Line Mux + * @rmtoll CR LMUX FL_LCD_GetCOMNumber + * @param LCDx LCD instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LCD_COM_NUM_4COM + * @arg @ref FL_LCD_COM_NUM_6COM + * @arg @ref FL_LCD_COM_NUM_8COM + */ +__STATIC_INLINE uint32_t FL_LCD_GetCOMNumber(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->CR, LCD_CR_LMUX_Msk)); +} + +/** + * @brief Enable LCD + * @rmtoll CR EN FL_LCD_Enable + * @param LCDx LCD instance + * @retval None + */ +__STATIC_INLINE void FL_LCD_Enable(LCD_Type *LCDx) +{ + SET_BIT(LCDx->CR, LCD_CR_EN_Msk); +} + +/** + * @brief Get LCD State + * @rmtoll CR EN FL_LCD_IsEnabled + * @param LCDx LCD instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LCD_IsEnabled(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->CR, LCD_CR_EN_Msk) == LCD_CR_EN_Msk); +} + +/** + * @brief Disable LCD + * @rmtoll CR EN FL_LCD_Disable + * @param LCDx LCD instance + * @retval None + */ +__STATIC_INLINE void FL_LCD_Disable(LCD_Type *LCDx) +{ + CLEAR_BIT(LCDx->CR, LCD_CR_EN_Msk); +} + +/** + * @brief Set LCD Display Frequency + * @rmtoll FCR DF FL_LCD_WriteDisplayFrequency + * @param LCDx LCD instance + * @param frequency + * @retval None + */ +__STATIC_INLINE void FL_LCD_WriteDisplayFrequency(LCD_Type *LCDx, uint32_t frequency) +{ + MODIFY_REG(LCDx->FCR, (0xffU << 0U), (frequency << 0U)); +} + +/** + * @brief Get LCD Display Frequency + * @rmtoll FCR DF FL_LCD_ReadDisplayFrequency + * @param LCDx LCD instance + * @retval + */ +__STATIC_INLINE uint32_t FL_LCD_ReadDisplayFrequency(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->FCR, (0xffU << 0U)) >> 0U); +} + +/** + * @brief Set LCD Display Off Time + * @rmtoll FLKT TOFF FL_LCD_WriteDisplayOffTime + * @param LCDx LCD instance + * @param time + * @retval None + */ +__STATIC_INLINE void FL_LCD_WriteDisplayOffTime(LCD_Type *LCDx, uint32_t time) +{ + MODIFY_REG(LCDx->FLKT, (0xffU << 8U), (time << 8U)); +} + +/** + * @brief Get LCD Display Off Time + * @rmtoll FLKT TOFF FL_LCD_ReadDisplayOffTime + * @param LCDx LCD instance + * @retval + */ +__STATIC_INLINE uint32_t FL_LCD_ReadDisplayOffTime(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->FLKT, (0xffU << 8U)) >> 8U); +} + +/** + * @brief Set LCD Display On Time + * @rmtoll FLKT TON FL_LCD_WriteDisplayOnTime + * @param LCDx LCD instance + * @param time + * @retval None + */ +__STATIC_INLINE void FL_LCD_WriteDisplayOnTime(LCD_Type *LCDx, uint32_t time) +{ + MODIFY_REG(LCDx->FLKT, (0xffU << 0U), (time << 0U)); +} + +/** + * @brief Get LCD Display On Time + * @rmtoll FLKT TON FL_LCD_ReadDisplayOnTime + * @param LCDx LCD instance + * @retval + */ +__STATIC_INLINE uint32_t FL_LCD_ReadDisplayOnTime(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->FLKT, (0xffU << 0U)) >> 0U); +} + +/** + * @brief Enable LCD Display OFF IRQ + * @rmtoll IER DONIE FL_LCD_EnableIT_DisplayOff + * @param LCDx LCD instance + * @retval None + */ +__STATIC_INLINE void FL_LCD_EnableIT_DisplayOff(LCD_Type *LCDx) +{ + SET_BIT(LCDx->IER, LCD_IER_DONIE_Msk); +} + +/** + * @brief Disable LCD Display OFF IRQ + * @rmtoll IER DONIE FL_LCD_DisableIT_DisplayOff + * @param LCDx LCD instance + * @retval None + */ +__STATIC_INLINE void FL_LCD_DisableIT_DisplayOff(LCD_Type *LCDx) +{ + CLEAR_BIT(LCDx->IER, LCD_IER_DONIE_Msk); +} + +/** + * @brief Getable LCD Display OFF IRQ + * @rmtoll IER DONIE FL_LCD_IsEnabledIT_DisplayOff + * @param LCDx LCD instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LCD_IsEnabledIT_DisplayOff(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->IER, LCD_IER_DONIE_Msk) == LCD_IER_DONIE_Msk); +} + +/** + * @brief Enable LCD Display ON Interrupt + * @rmtoll IER DOFFIE FL_LCD_EnableIT_DisplayOn + * @param LCDx LCD instance + * @retval None + */ +__STATIC_INLINE void FL_LCD_EnableIT_DisplayOn(LCD_Type *LCDx) +{ + SET_BIT(LCDx->IER, LCD_IER_DOFFIE_Msk); +} + +/** + * @brief Disable LCD Display ON Interrupt + * @rmtoll IER DOFFIE FL_LCD_DisableIT_DisplayOn + * @param LCDx LCD instance + * @retval None + */ +__STATIC_INLINE void FL_LCD_DisableIT_DisplayOn(LCD_Type *LCDx) +{ + CLEAR_BIT(LCDx->IER, LCD_IER_DOFFIE_Msk); +} + +/** + * @brief Getable LCD Display ON Interrupt + * @rmtoll IER DOFFIE FL_LCD_IsEnabledIT_DisplayOn + * @param LCDx LCD instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LCD_IsEnabledIT_DisplayOn(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->IER, LCD_IER_DOFFIE_Msk) == LCD_IER_DOFFIE_Msk); +} + +/** + * @brief Get LCD Display OFF Flag + * @rmtoll ISR DONIF FL_LCD_IsActiveFlag_DisplayOff + * @param LCDx LCD instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LCD_IsActiveFlag_DisplayOff(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->ISR, LCD_ISR_DONIF_Msk) == (LCD_ISR_DONIF_Msk)); +} + +/** + * @brief Clear LCD Display OFF Flag + * @rmtoll ISR DONIF FL_LCD_ClearFlag_DisplayOff + * @param LCDx LCD instance + * @retval None + */ +__STATIC_INLINE void FL_LCD_ClearFlag_DisplayOff(LCD_Type *LCDx) +{ + WRITE_REG(LCDx->ISR, LCD_ISR_DONIF_Msk); +} + +/** + * @brief Get LCD Display On Flag + * @rmtoll ISR DOFFIF FL_LCD_IsActiveFlag_DisplayOn + * @param LCDx LCD instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LCD_IsActiveFlag_DisplayOn(LCD_Type *LCDx) +{ + return (uint32_t)(READ_BIT(LCDx->ISR, LCD_ISR_DOFFIF_Msk) == (LCD_ISR_DOFFIF_Msk)); +} + +/** + * @brief Clear LCD Display On Flag + * @rmtoll ISR DOFFIF FL_LCD_ClearFlag_DisplayOn + * @param LCDx LCD instance + * @retval None + */ +__STATIC_INLINE void FL_LCD_ClearFlag_DisplayOn(LCD_Type *LCDx) +{ + WRITE_REG(LCDx->ISR, LCD_ISR_DOFFIF_Msk); +} + +/** + * @brief Write LCD Display Data + * @rmtoll DATA0 DSDA FL_LCD_WriteData + * @param LCDx LCD instance + * @param reg This parameter can be one of the following values: + * @arg @ref FL_LCD_DATA_REG0 + * @arg @ref FL_LCD_DATA_REG1 + * @arg @ref FL_LCD_DATA_REG2 + * @arg @ref FL_LCD_DATA_REG3 + * @arg @ref FL_LCD_DATA_REG4 + * @arg @ref FL_LCD_DATA_REG5 + * @arg @ref FL_LCD_DATA_REG6 + * @arg @ref FL_LCD_DATA_REG7 + * @param data + * @retval None + */ +__STATIC_INLINE void FL_LCD_WriteData(LCD_Type *LCDx, uint32_t reg, uint32_t data) +{ + volatile uint32_t *pData = &(LCDx->DATA0); + MODIFY_REG(pData[reg], LCD_DATA0_DSDA_Msk, data); +} + +/** + * @brief Read LCD Display Data + * @rmtoll DATA0 DSDA FL_LCD_ReadData + * @param LCDx LCD instance + * @param reg This parameter can be one of the following values: + * @arg @ref FL_LCD_DATA_REG0 + * @arg @ref FL_LCD_DATA_REG1 + * @arg @ref FL_LCD_DATA_REG2 + * @arg @ref FL_LCD_DATA_REG3 + * @arg @ref FL_LCD_DATA_REG4 + * @arg @ref FL_LCD_DATA_REG5 + * @arg @ref FL_LCD_DATA_REG6 + * @arg @ref FL_LCD_DATA_REG7 + * @retval + */ +__STATIC_INLINE uint32_t FL_LCD_ReadData(LCD_Type *LCDx, uint32_t reg) +{ + volatile uint32_t *pData = &(LCDx->DATA0); + return (uint32_t)(READ_BIT(pData[reg], LCD_DATA0_DSDA_Msk)); +} + +/** + * @brief Get LCD COMx State + * @rmtoll COMEN FL_LCD_IsEnabledCOMEN + * @param LCDx LCD instance + * @param COM This parameter can be one of the following values: + * @arg @ref FL_LCD_COMEN_COM0 + * @arg @ref FL_LCD_COMEN_COM1 + * @arg @ref FL_LCD_COMEN_COM2 + * @arg @ref FL_LCD_COMEN_COM3 + * @arg @ref FL_LCD_COMEN_COM4 + * @arg @ref FL_LCD_COMEN_COM5 + * @arg @ref FL_LCD_COMEN_COM6 + * @arg @ref FL_LCD_COMEN_COM7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LCD_IsEnabledCOMEN(LCD_Type *LCDx, uint32_t COM) +{ + if(COM < FL_LCD_COMEN_COM4) + { + return (uint32_t)(READ_BIT(LCDx->COMEN, ((COM & 0xffffffff) << 0x0U)) == ((COM & 0xffffffff) << 0x0U)); + } + else + { + return (uint32_t)(READ_BIT(LCDx->SEGEN0, ((COM & 0xffffffff) << 0x0U)) == ((COM & 0xffffffff) << 0x0U)); + } +} + +/** + * @brief Enable LCD COMx + * @rmtoll COMEN FL_LCD_EnableCOMEN + * @param LCDx LCD instance + * @param COM This parameter can be one of the following values: + * @arg @ref FL_LCD_COMEN_COM0 + * @arg @ref FL_LCD_COMEN_COM1 + * @arg @ref FL_LCD_COMEN_COM2 + * @arg @ref FL_LCD_COMEN_COM3 + * @arg @ref FL_LCD_COMEN_COM4 + * @arg @ref FL_LCD_COMEN_COM5 + * @arg @ref FL_LCD_COMEN_COM6 + * @arg @ref FL_LCD_COMEN_COM7 + * @retval None + */ +__STATIC_INLINE void FL_LCD_EnableCOMEN(LCD_Type *LCDx, uint32_t COM) +{ + if(COM < FL_LCD_COMEN_COM4) + { + SET_BIT(LCDx->COMEN, ((COM & 0xffffffff) << 0x0U)); + } + else + { + SET_BIT(LCDx->SEGEN0, ((COM & 0xffffffff) << 0x0U)); + } +} + +/** + * @brief Disable LCD COMx + * @rmtoll COMEN FL_LCD_DisableCOMEN + * @param LCDx LCD instance + * @param COM This parameter can be one of the following values: + * @arg @ref FL_LCD_COMEN_COM0 + * @arg @ref FL_LCD_COMEN_COM1 + * @arg @ref FL_LCD_COMEN_COM2 + * @arg @ref FL_LCD_COMEN_COM3 + * @arg @ref FL_LCD_COMEN_COM4 + * @arg @ref FL_LCD_COMEN_COM5 + * @arg @ref FL_LCD_COMEN_COM6 + * @arg @ref FL_LCD_COMEN_COM7 + * @retval None + */ +__STATIC_INLINE void FL_LCD_DisableCOMEN(LCD_Type *LCDx, uint32_t COM) +{ + if(COM < FL_LCD_COMEN_COM4) + { + CLEAR_BIT(LCDx->COMEN, ((COM & 0xffffffff) << 0x0U)); + } + else + { + CLEAR_BIT(LCDx->SEGEN0, ((COM & 0xffffffff) << 0x0U)); + } +} + +/** + * @brief Get LCD SEGx State + * @rmtoll SEGEN0 FL_LCD_IsEnabledSEGEN0 + * @param LCDx LCD instance + * @param SEG This parameter can be one of the following values: + * @arg @ref FL_LCD_SEGEN0_SEG0 + * @arg @ref FL_LCD_SEGEN0_SEG1 + * @arg @ref FL_LCD_SEGEN0_SEG2 + * @arg @ref FL_LCD_SEGEN0_SEG3 + * @arg @ref FL_LCD_SEGEN0_SEG4 + * @arg @ref FL_LCD_SEGEN0_SEG5 + * @arg @ref FL_LCD_SEGEN0_SEG6 + * @arg @ref FL_LCD_SEGEN0_SEG7 + * @arg @ref FL_LCD_SEGEN0_SEG8 + * @arg @ref FL_LCD_SEGEN0_SEG9 + * @arg @ref FL_LCD_SEGEN0_SEG10 + * @arg @ref FL_LCD_SEGEN0_SEG11 + * @arg @ref FL_LCD_SEGEN0_SEG12 + * @arg @ref FL_LCD_SEGEN0_SEG13 + * @arg @ref FL_LCD_SEGEN0_SEG14 + * @arg @ref FL_LCD_SEGEN0_SEG15 + * @arg @ref FL_LCD_SEGEN0_SEG16 + * @arg @ref FL_LCD_SEGEN0_SEG17 + * @arg @ref FL_LCD_SEGEN0_SEG18 + * @arg @ref FL_LCD_SEGEN0_SEG19 + * @arg @ref FL_LCD_SEGEN0_SEG20 + * @arg @ref FL_LCD_SEGEN0_SEG21 + * @arg @ref FL_LCD_SEGEN0_SEG22 + * @arg @ref FL_LCD_SEGEN0_SEG23 + * @arg @ref FL_LCD_SEGEN0_SEG24 + * @arg @ref FL_LCD_SEGEN0_SEG25 + * @arg @ref FL_LCD_SEGEN0_SEG26 + * @arg @ref FL_LCD_SEGEN0_SEG27 + * @arg @ref FL_LCD_SEGEN0_SEG28 + * @arg @ref FL_LCD_SEGEN0_SEG29 + * @arg @ref FL_LCD_SEGEN0_SEG30 + * @arg @ref FL_LCD_SEGEN0_SEG31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LCD_IsEnabledSEGEN0(LCD_Type *LCDx, uint32_t SEG) +{ + return (uint32_t)(READ_BIT(LCDx->SEGEN0, ((SEG & 0xffffffff) << 0x0U)) == ((SEG & 0xffffffff) << 0x0U)); +} + +/** + * @brief Enable LCD SEGx + * @rmtoll SEGEN0 FL_LCD_EnableSEGEN0 + * @param LCDx LCD instance + * @param SEG This parameter can be one of the following values: + * @arg @ref FL_LCD_SEGEN0_SEG0 + * @arg @ref FL_LCD_SEGEN0_SEG1 + * @arg @ref FL_LCD_SEGEN0_SEG2 + * @arg @ref FL_LCD_SEGEN0_SEG3 + * @arg @ref FL_LCD_SEGEN0_SEG4 + * @arg @ref FL_LCD_SEGEN0_SEG5 + * @arg @ref FL_LCD_SEGEN0_SEG6 + * @arg @ref FL_LCD_SEGEN0_SEG7 + * @arg @ref FL_LCD_SEGEN0_SEG8 + * @arg @ref FL_LCD_SEGEN0_SEG9 + * @arg @ref FL_LCD_SEGEN0_SEG10 + * @arg @ref FL_LCD_SEGEN0_SEG11 + * @arg @ref FL_LCD_SEGEN0_SEG12 + * @arg @ref FL_LCD_SEGEN0_SEG13 + * @arg @ref FL_LCD_SEGEN0_SEG14 + * @arg @ref FL_LCD_SEGEN0_SEG15 + * @arg @ref FL_LCD_SEGEN0_SEG16 + * @arg @ref FL_LCD_SEGEN0_SEG17 + * @arg @ref FL_LCD_SEGEN0_SEG18 + * @arg @ref FL_LCD_SEGEN0_SEG19 + * @arg @ref FL_LCD_SEGEN0_SEG20 + * @arg @ref FL_LCD_SEGEN0_SEG21 + * @arg @ref FL_LCD_SEGEN0_SEG22 + * @arg @ref FL_LCD_SEGEN0_SEG23 + * @arg @ref FL_LCD_SEGEN0_SEG24 + * @arg @ref FL_LCD_SEGEN0_SEG25 + * @arg @ref FL_LCD_SEGEN0_SEG26 + * @arg @ref FL_LCD_SEGEN0_SEG27 + * @arg @ref FL_LCD_SEGEN0_SEG28 + * @arg @ref FL_LCD_SEGEN0_SEG29 + * @arg @ref FL_LCD_SEGEN0_SEG30 + * @arg @ref FL_LCD_SEGEN0_SEG31 + * @retval None + */ +__STATIC_INLINE void FL_LCD_EnableSEGEN0(LCD_Type *LCDx, uint32_t SEG) +{ + SET_BIT(LCDx->SEGEN0, ((SEG & 0xffffffff) << 0x0U)); +} + +/** + * @brief Disable LCD SEGx + * @rmtoll SEGEN0 FL_LCD_DisableSEGEN0 + * @param LCDx LCD instance + * @param SEG This parameter can be one of the following values: + * @arg @ref FL_LCD_SEGEN0_SEG0 + * @arg @ref FL_LCD_SEGEN0_SEG1 + * @arg @ref FL_LCD_SEGEN0_SEG2 + * @arg @ref FL_LCD_SEGEN0_SEG3 + * @arg @ref FL_LCD_SEGEN0_SEG4 + * @arg @ref FL_LCD_SEGEN0_SEG5 + * @arg @ref FL_LCD_SEGEN0_SEG6 + * @arg @ref FL_LCD_SEGEN0_SEG7 + * @arg @ref FL_LCD_SEGEN0_SEG8 + * @arg @ref FL_LCD_SEGEN0_SEG9 + * @arg @ref FL_LCD_SEGEN0_SEG10 + * @arg @ref FL_LCD_SEGEN0_SEG11 + * @arg @ref FL_LCD_SEGEN0_SEG12 + * @arg @ref FL_LCD_SEGEN0_SEG13 + * @arg @ref FL_LCD_SEGEN0_SEG14 + * @arg @ref FL_LCD_SEGEN0_SEG15 + * @arg @ref FL_LCD_SEGEN0_SEG16 + * @arg @ref FL_LCD_SEGEN0_SEG17 + * @arg @ref FL_LCD_SEGEN0_SEG18 + * @arg @ref FL_LCD_SEGEN0_SEG19 + * @arg @ref FL_LCD_SEGEN0_SEG20 + * @arg @ref FL_LCD_SEGEN0_SEG21 + * @arg @ref FL_LCD_SEGEN0_SEG22 + * @arg @ref FL_LCD_SEGEN0_SEG23 + * @arg @ref FL_LCD_SEGEN0_SEG24 + * @arg @ref FL_LCD_SEGEN0_SEG25 + * @arg @ref FL_LCD_SEGEN0_SEG26 + * @arg @ref FL_LCD_SEGEN0_SEG27 + * @arg @ref FL_LCD_SEGEN0_SEG28 + * @arg @ref FL_LCD_SEGEN0_SEG29 + * @arg @ref FL_LCD_SEGEN0_SEG30 + * @arg @ref FL_LCD_SEGEN0_SEG31 + * @retval None + */ +__STATIC_INLINE void FL_LCD_DisableSEGEN0(LCD_Type *LCDx, uint32_t SEG) +{ + CLEAR_BIT(LCDx->SEGEN0, ((SEG & 0xffffffff) << 0x0U)); +} + +/** + * @} + */ + +/** @defgroup LCD_FL_EF_Init Initialization and de-initialization functions + * @{ + */ + +FL_ErrorStatus FL_LCD_DeInit(LCD_Type *LCDx); +void FL_LCD_StructInit(FL_LCD_InitTypeDef *initStruct); +FL_ErrorStatus FL_LCD_Init(LCD_Type *LCDx, FL_LCD_InitTypeDef *initStruct); + +/** + * @} + */ + +/** @defgroup LCD_FL_EF_Operation Opeartion functions + * @{ + */ + +void FL_LCD_4COMDisplay(uint32_t *display, uint8_t com, uint8_t seg, uint8_t state); +void FL_LCD_6COMDisplay(uint32_t *display, uint8_t com, uint8_t seg, uint8_t state); +void FL_LCD_8COMDisplay(uint32_t *display, uint8_t com, uint8_t seg, uint8_t state); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_LCD_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.14-0.1 @ 2021-02-02*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_lptim32.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_lptim32.h new file mode 100644 index 0000000000..494e05c1b0 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_lptim32.h @@ -0,0 +1,1173 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_lptim32.h + * @author FMSH Application Team + * @brief Head file of LPTIM32 FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_LPTIM32_H +#define __FM33LC0XX_FL_LPTIM32_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup LPTIM32 LPTIM32 + * @brief LPTIM32 FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup LPTIM32_FL_ES_INIT LPTIM32 Exported Init structures + * @{ + */ + +/** + * @brief LPTIM32 Init Sturcture Definition + */ +typedef struct +{ + /* 内部时钟源 */ + uint32_t clockSource; + + /* 预分频器的时钟源 可选择内部时钟, 也可选择外部时钟 */ + uint32_t prescalerClockSource; + + /* 预分频系数 */ + uint32_t prescaler; + + /* 重装值 */ + uint32_t autoReload; + + /* 定时器工作模式选择 */ + uint32_t mode; + + /* 单次计数使能 */ + uint32_t onePulseMode; + + /* ETR异步计数边沿 */ + uint32_t countEdge; + + /* ETR触发计数边沿 */ + uint32_t triggerEdge; + +} FL_LPTIM32_InitTypeDef; + +/** + * @brief LPTIM32 Output Compare Init Structure Definition + */ +typedef struct +{ + /* 比较值 */ + uint32_t compareValue; + + /* 比较输出极性 */ + uint32_t OCPolarity; + +} FL_LPTIM32_OC_InitTypeDef; + +/** + * @brief LPTIM32 Input Capture Init Structure Definition + */ +typedef struct +{ + /* 通道1捕获源 */ + uint32_t ICSource; + + /* 输入捕获极性 */ + uint32_t ICEdge; + +} FL_LPTIM32_IC_InitTypeDef; + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup LPTIM32_FL_Exported_Constants LPTIM32 Exported Constants + * @{ + */ + +#define LPTIM32_CR_EN_Pos (0U) +#define LPTIM32_CR_EN_Msk (0x1U << LPTIM32_CR_EN_Pos) +#define LPTIM32_CR_EN LPTIM32_CR_EN_Msk + +#define LPTIM32_CFGR_ETR_AFEN_Pos (24U) +#define LPTIM32_CFGR_ETR_AFEN_Msk (0x1U << LPTIM32_CFGR_ETR_AFEN_Pos) +#define LPTIM32_CFGR_ETR_AFEN LPTIM32_CFGR_ETR_AFEN_Msk + +#define LPTIM32_CFGR_PSCSEL_Pos (14U) +#define LPTIM32_CFGR_PSCSEL_Msk (0x1U << LPTIM32_CFGR_PSCSEL_Pos) +#define LPTIM32_CFGR_PSCSEL LPTIM32_CFGR_PSCSEL_Msk + +#define LPTIM32_CFGR_LPTINSEL_Pos (13U) +#define LPTIM32_CFGR_LPTINSEL_Msk (0x1U << LPTIM32_CFGR_LPTINSEL_Pos) +#define LPTIM32_CFGR_LPTINSEL LPTIM32_CFGR_LPTINSEL_Msk + +#define LPTIM32_CFGR_DIVSEL_Pos (10U) +#define LPTIM32_CFGR_DIVSEL_Msk (0x7U << LPTIM32_CFGR_DIVSEL_Pos) +#define LPTIM32_CFGR_DIVSEL LPTIM32_CFGR_DIVSEL_Msk + +#define LPTIM32_CFGR_EDGESEL_Pos (7U) +#define LPTIM32_CFGR_EDGESEL_Msk (0x1U << LPTIM32_CFGR_EDGESEL_Pos) +#define LPTIM32_CFGR_EDGESEL LPTIM32_CFGR_EDGESEL_Msk + +#define LPTIM32_CFGR_TRIGCFG_Pos (5U) +#define LPTIM32_CFGR_TRIGCFG_Msk (0x3U << LPTIM32_CFGR_TRIGCFG_Pos) +#define LPTIM32_CFGR_TRIGCFG LPTIM32_CFGR_TRIGCFG_Msk + +#define LPTIM32_CFGR_ONST_Pos (2U) +#define LPTIM32_CFGR_ONST_Msk (0x1U << LPTIM32_CFGR_ONST_Pos) +#define LPTIM32_CFGR_ONST LPTIM32_CFGR_ONST_Msk + +#define LPTIM32_CFGR_TMOD_Pos (0U) +#define LPTIM32_CFGR_TMOD_Msk (0x3U << LPTIM32_CFGR_TMOD_Pos) +#define LPTIM32_CFGR_TMOD LPTIM32_CFGR_TMOD_Msk + +#define LPTIM32_IER_CCIE_Pos (0U) +#define LPTIM32_IER_CCIE_Msk (0x3U << LPTIM32_IER_CCIE_Pos) +#define LPTIM32_IER_CCIE LPTIM32_IER_CCIE_Msk + +#define LPTIM32_IER_OVIE_Pos (2U) +#define LPTIM32_IER_OVIE_Msk (0x1U << LPTIM32_IER_OVIE_Pos) +#define LPTIM32_IER_OVIE LPTIM32_IER_OVIE_Msk + +#define LPTIM32_IER_TRIGIE_Pos (3U) +#define LPTIM32_IER_TRIGIE_Msk (0x1U << LPTIM32_IER_TRIGIE_Pos) +#define LPTIM32_IER_TRIGIE LPTIM32_IER_TRIGIE_Msk + +#define LPTIM32_IER_OVRIE_Pos (8U) +#define LPTIM32_IER_OVRIE_Msk (0x3U << LPTIM32_IER_OVRIE_Pos) +#define LPTIM32_IER_OVRIE LPTIM32_IER_OVRIE_Msk + +#define LPTIM32_ISR_CCIF_Pos (0U) +#define LPTIM32_ISR_CCIF_Msk (0x3U << LPTIM32_ISR_CCIF_Pos) +#define LPTIM32_ISR_CCIF LPTIM32_ISR_CCIF_Msk + +#define LPTIM32_ISR_OVIF_Pos (2U) +#define LPTIM32_ISR_OVIF_Msk (0x1U << LPTIM32_ISR_OVIF_Pos) +#define LPTIM32_ISR_OVIF LPTIM32_ISR_OVIF_Msk + +#define LPTIM32_ISR_TRIGIF_Pos (3U) +#define LPTIM32_ISR_TRIGIF_Msk (0x1U << LPTIM32_ISR_TRIGIF_Pos) +#define LPTIM32_ISR_TRIGIF LPTIM32_ISR_TRIGIF_Msk + +#define LPTIM32_ISR_CAPOVR_Pos (8U) +#define LPTIM32_ISR_CAPOVR_Msk (0x3U << LPTIM32_ISR_CAPOVR_Pos) +#define LPTIM32_ISR_CAPOVR LPTIM32_ISR_CAPOVR_Msk + +#define LPTIM32_CCSR_CAPCFG_Pos (8U) +#define LPTIM32_CCSR_CAPCFG_Msk (0x3U << LPTIM32_CCSR_CAPCFG_Pos) +#define LPTIM32_CCSR_CAPCFG LPTIM32_CCSR_CAPCFG_Msk + +#define LPTIM32_CCSR_POLAR_Pos (4U) +#define LPTIM32_CCSR_POLAR_Msk (0x1U << LPTIM32_CCSR_POLAR_Pos) +#define LPTIM32_CCSR_POLAR LPTIM32_CCSR_POLAR_Msk + +#define LPTIM32_CCSR_CCS_Pos (0U) +#define LPTIM32_CCSR_CCS_Msk (0x3U << LPTIM32_CCSR_CCS_Pos) +#define LPTIM32_CCSR_CCS LPTIM32_CCSR_CCS_Msk + +#define LPTIM32_CCSR_CAPEDGE_Pos (20U) +#define LPTIM32_CCSR_CAPEDGE_Msk (0x3U << LPTIM32_CCSR_CAPEDGE_Pos) +#define LPTIM32_CCSR_CAPEDGE LPTIM32_CCSR_CAPEDGE_Msk + +#define LPTIM32_CCSR_CAPSSEL_Pos (16U) +#define LPTIM32_CCSR_CAPSSEL_Msk (0x3U << LPTIM32_CCSR_CAPSSEL_Pos) +#define LPTIM32_CCSR_CAPSSEL LPTIM32_CCSR_CAPSSEL_Msk + + + +#define FL_LPTIM32_CHANNEL_1 (0x1U << 0U) +#define FL_LPTIM32_CHANNEL_2 (0x1U << 1U) + + + +#define FL_LPTIM32_CLK_SOURCE_INTERNAL (0x0U << LPTIM32_CFGR_PSCSEL_Pos) +#define FL_LPTIM32_CLK_SOURCE_EXTERNAL (0x1U << LPTIM32_CFGR_PSCSEL_Pos) + + +#define FL_LPTIM32_ETR_SOURCE_EXTERNAL (0x0U << LPTIM32_CFGR_LPTINSEL_Pos) +#define FL_LPTIM32_ETR_SOURCE_ADC_EOC (0x1U << LPTIM32_CFGR_LPTINSEL_Pos) + + +#define FL_LPTIM32_PSC_DIV1 (0x0U << LPTIM32_CFGR_DIVSEL_Pos) +#define FL_LPTIM32_PSC_DIV2 (0x1U << LPTIM32_CFGR_DIVSEL_Pos) +#define FL_LPTIM32_PSC_DIV4 (0x2U << LPTIM32_CFGR_DIVSEL_Pos) +#define FL_LPTIM32_PSC_DIV8 (0x3U << LPTIM32_CFGR_DIVSEL_Pos) +#define FL_LPTIM32_PSC_DIV16 (0x4U << LPTIM32_CFGR_DIVSEL_Pos) +#define FL_LPTIM32_PSC_DIV32 (0x5U << LPTIM32_CFGR_DIVSEL_Pos) +#define FL_LPTIM32_PSC_DIV64 (0x6U << LPTIM32_CFGR_DIVSEL_Pos) +#define FL_LPTIM32_PSC_DIV128 (0x7U << LPTIM32_CFGR_DIVSEL_Pos) + + +#define FL_LPTIM32_ETR_COUNT_EDGE_RISING (0x0U << LPTIM32_CFGR_EDGESEL_Pos) +#define FL_LPTIM32_ETR_COUNT_EDGE_FALLING (0x1U << LPTIM32_CFGR_EDGESEL_Pos) + + +#define FL_LPTIM32_ETR_TRIGGER_EDGE_RISING (0x0U << LPTIM32_CFGR_TRIGCFG_Pos) +#define FL_LPTIM32_ETR_TRIGGER_EDGE_FALLING (0x1U << LPTIM32_CFGR_TRIGCFG_Pos) +#define FL_LPTIM32_ETR_TRIGGER_EDGE_BOTH (0x2U << LPTIM32_CFGR_TRIGCFG_Pos) + + +#define FL_LPTIM32_ONE_PULSE_MODE_CONTINUOUS (0x0U << LPTIM32_CFGR_ONST_Pos) +#define FL_LPTIM32_ONE_PULSE_MODE_SINGLE (0x1U << LPTIM32_CFGR_ONST_Pos) + + +#define FL_LPTIM32_OPERATION_MODE_NORMAL (0x0U << LPTIM32_CFGR_TMOD_Pos) +#define FL_LPTIM32_OPERATION_MODE_EXTERNAL_TRIGGER_CNT (0x1U << LPTIM32_CFGR_TMOD_Pos) +#define FL_LPTIM32_OPERATION_MODE_EXTERNAL_ASYNC_PULSE_CNT (0x2U << LPTIM32_CFGR_TMOD_Pos) +#define FL_LPTIM32_OPERATION_MODE_TIMEOUT (0x3U << LPTIM32_CFGR_TMOD_Pos) + + +#define FL_LPTIM32_IC_EDGE_RISING (0x0U << LPTIM32_CCSR_CAPCFG_Pos) +#define FL_LPTIM32_IC_EDGE_FALLING (0x1U << LPTIM32_CCSR_CAPCFG_Pos) +#define FL_LPTIM32_IC_EDGE_BOTH (0x2U << LPTIM32_CCSR_CAPCFG_Pos) + + +#define FL_LPTIM32_OC_POLARITY_NORMAL (0x0U << LPTIM32_CCSR_POLAR_Pos) +#define FL_LPTIM32_OC_POLARITY_INVERT (0x1U << LPTIM32_CCSR_POLAR_Pos) + + +#define FL_LPTIM32_CHANNEL_MODE_DISABLE (0x0U << LPTIM32_CCSR_CCS_Pos) +#define FL_LPTIM32_CHANNEL_MODE_INPUT (0x1U << LPTIM32_CCSR_CCS_Pos) +#define FL_LPTIM32_CHANNEL_MODE_OUTPUT (0x2U << LPTIM32_CCSR_CCS_Pos) + + +#define FL_LPTIM32_IC_CAPTURED_EDGE_RISING (0x0U << LPTIM32_CCSR_CAPEDGE_Pos) +#define FL_LPTIM32_IC_CAPTURED_EDGE_FALLING (0x1U << LPTIM32_CCSR_CAPEDGE_Pos) + +#define FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP0 (0x0U << LPTIM32_CCSR_CAPSSEL_Pos) +#define FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP1 (0x1U << LPTIM32_CCSR_CAPSSEL_Pos) +#define FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP2 (0x2U << LPTIM32_CCSR_CAPSSEL_Pos) +#define FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP3 (0x3U << LPTIM32_CCSR_CAPSSEL_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup LPTIM32_FL_Exported_Functions LPTIM32 Exported Functions + * @{ + */ + +/** + * @brief Enable LPTIM32 + * @rmtoll CR EN FL_LPTIM32_Enable + * @param LPTIM32x LPTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_Enable(LPTIM32_Type *LPTIM32x) +{ + SET_BIT(LPTIM32x->CR, LPTIM32_CR_EN_Msk); +} + +/** + * @brief Disable LPTIM32 + * @rmtoll CR EN FL_LPTIM32_Disable + * @param LPTIM32x LPTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_Disable(LPTIM32_Type *LPTIM32x) +{ + CLEAR_BIT(LPTIM32x->CR, LPTIM32_CR_EN_Msk); +} + +/** + * @brief Get LPTIM32 Enable Status + * @rmtoll CR EN FL_LPTIM32_IsEnabled + * @param LPTIM32x LPTIM32 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPTIM32_IsEnabled(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->CR, LPTIM32_CR_EN_Msk) == LPTIM32_CR_EN_Msk); +} + +/** + * @brief Enable External Trigger Input Analog Filter + * @rmtoll CFGR ETR_AFEN FL_LPTIM32_EnableETRFilter + * @param LPTIM32x LPTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_EnableETRFilter(LPTIM32_Type *LPTIM32x) +{ + SET_BIT(LPTIM32x->CFGR, LPTIM32_CFGR_ETR_AFEN_Msk); +} + +/** + * @brief Disable External Trigger Input Analog Filter + * @rmtoll CFGR ETR_AFEN FL_LPTIM32_DisableETRFilter + * @param LPTIM32x LPTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_DisableETRFilter(LPTIM32_Type *LPTIM32x) +{ + CLEAR_BIT(LPTIM32x->CFGR, LPTIM32_CFGR_ETR_AFEN_Msk); +} + +/** + * @brief Get External Trigger Input Analog Filter Enable Status + * @rmtoll CFGR ETR_AFEN FL_LPTIM32_IsEnabledETRFilter + * @param LPTIM32x LPTIM32 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPTIM32_IsEnabledETRFilter(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->CFGR, LPTIM32_CFGR_ETR_AFEN_Msk) == LPTIM32_CFGR_ETR_AFEN_Msk); +} + +/** + * @brief Set Prescaler Input + * @rmtoll CFGR PSCSEL FL_LPTIM32_SetClockSource + * @param LPTIM32x LPTIM32 instance + * @param source This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CLK_SOURCE_INTERNAL + * @arg @ref FL_LPTIM32_CLK_SOURCE_EXTERNAL + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_SetClockSource(LPTIM32_Type *LPTIM32x, uint32_t source) +{ + MODIFY_REG(LPTIM32x->CFGR, LPTIM32_CFGR_PSCSEL_Msk, source); +} + +/** + * @brief Get Prescaler Input Setting + * @rmtoll CFGR PSCSEL FL_LPTIM32_GetClockSource + * @param LPTIM32x LPTIM32 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPTIM32_CLK_SOURCE_INTERNAL + * @arg @ref FL_LPTIM32_CLK_SOURCE_EXTERNAL + */ +__STATIC_INLINE uint32_t FL_LPTIM32_GetClockSource(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->CFGR, LPTIM32_CFGR_PSCSEL_Msk)); +} + +/** + * @brief Set External Trigger Input Source + * @rmtoll CFGR LPTINSEL FL_LPTIM32_SetETRSource + * @param LPTIM32x LPTIM32 instance + * @param Input This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_ETR_SOURCE_EXTERNAL + * @arg @ref FL_LPTIM32_ETR_SOURCE_ADC_EOC + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_SetETRSource(LPTIM32_Type *LPTIM32x, uint32_t Input) +{ + MODIFY_REG(LPTIM32x->CFGR, LPTIM32_CFGR_LPTINSEL_Msk, Input); +} + +/** + * @brief Get External Trigger Input Source Setting + * @rmtoll CFGR LPTINSEL FL_LPTIM32_GetETRSource + * @param LPTIM32x LPTIM32 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPTIM32_ETR_SOURCE_EXTERNAL + * @arg @ref FL_LPTIM32_ETR_SOURCE_ADC_EOC + */ +__STATIC_INLINE uint32_t FL_LPTIM32_GetETRSource(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->CFGR, LPTIM32_CFGR_LPTINSEL_Msk)); +} + +/** + * @brief Set Counter Clock Divider + * @rmtoll CFGR DIVSEL FL_LPTIM32_SetPrescaler + * @param LPTIM32x LPTIM32 instance + * @param psc This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_PSC_DIV1 + * @arg @ref FL_LPTIM32_PSC_DIV2 + * @arg @ref FL_LPTIM32_PSC_DIV4 + * @arg @ref FL_LPTIM32_PSC_DIV8 + * @arg @ref FL_LPTIM32_PSC_DIV16 + * @arg @ref FL_LPTIM32_PSC_DIV32 + * @arg @ref FL_LPTIM32_PSC_DIV64 + * @arg @ref FL_LPTIM32_PSC_DIV128 + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_SetPrescaler(LPTIM32_Type *LPTIM32x, uint32_t psc) +{ + MODIFY_REG(LPTIM32x->CFGR, LPTIM32_CFGR_DIVSEL_Msk, psc); +} + +/** + * @brief Get Counter Clock Divider Setting + * @rmtoll CFGR DIVSEL FL_LPTIM32_GetPrescaler + * @param LPTIM32x LPTIM32 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPTIM32_PSC_DIV1 + * @arg @ref FL_LPTIM32_PSC_DIV2 + * @arg @ref FL_LPTIM32_PSC_DIV4 + * @arg @ref FL_LPTIM32_PSC_DIV8 + * @arg @ref FL_LPTIM32_PSC_DIV16 + * @arg @ref FL_LPTIM32_PSC_DIV32 + * @arg @ref FL_LPTIM32_PSC_DIV64 + * @arg @ref FL_LPTIM32_PSC_DIV128 + */ +__STATIC_INLINE uint32_t FL_LPTIM32_GetPrescaler(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->CFGR, LPTIM32_CFGR_DIVSEL_Msk)); +} + +/** + * @brief Set ETR Input Edge Polarity + * @rmtoll CFGR EDGESEL FL_LPTIM32_SetETRCountEdge + * @param LPTIM32x LPTIM32 instance + * @param edge This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_ETR_COUNT_EDGE_RISING + * @arg @ref FL_LPTIM32_ETR_COUNT_EDGE_FALLING + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_SetETRCountEdge(LPTIM32_Type *LPTIM32x, uint32_t edge) +{ + MODIFY_REG(LPTIM32x->CFGR, LPTIM32_CFGR_EDGESEL_Msk, edge); +} + +/** + * @brief Get ETR Input Edge Polarity Setting + * @rmtoll CFGR EDGESEL FL_LPTIM32_GetETRCountEdge + * @param LPTIM32x LPTIM32 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPTIM32_ETR_COUNT_EDGE_RISING + * @arg @ref FL_LPTIM32_ETR_COUNT_EDGE_FALLING + */ +__STATIC_INLINE uint32_t FL_LPTIM32_GetETRCountEdge(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->CFGR, LPTIM32_CFGR_EDGESEL_Msk)); +} + +/** + * @brief Set ETR Trigger Edge Polarity + * @rmtoll CFGR TRIGCFG FL_LPTIM32_SetETRTriggerEdge + * @param LPTIM32x LPTIM32 instance + * @param edge This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_ETR_TRIGGER_EDGE_RISING + * @arg @ref FL_LPTIM32_ETR_TRIGGER_EDGE_FALLING + * @arg @ref FL_LPTIM32_ETR_TRIGGER_EDGE_BOTH + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_SetETRTriggerEdge(LPTIM32_Type *LPTIM32x, uint32_t edge) +{ + MODIFY_REG(LPTIM32x->CFGR, LPTIM32_CFGR_TRIGCFG_Msk, edge); +} + +/** + * @brief Get ETR Trigger Edge Polarity Setting + * @rmtoll CFGR TRIGCFG FL_LPTIM32_GetETRTriggerEdge + * @param LPTIM32x LPTIM32 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPTIM32_ETR_TRIGGER_EDGE_RISING + * @arg @ref FL_LPTIM32_ETR_TRIGGER_EDGE_FALLING + * @arg @ref FL_LPTIM32_ETR_TRIGGER_EDGE_BOTH + */ +__STATIC_INLINE uint32_t FL_LPTIM32_GetETRTriggerEdge(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->CFGR, LPTIM32_CFGR_TRIGCFG_Msk)); +} + +/** + * @brief Set One State Timer + * @rmtoll CFGR ONST FL_LPTIM32_SetOnePulseMode + * @param LPTIM32x LPTIM32 instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_ONE_PULSE_MODE_CONTINUOUS + * @arg @ref FL_LPTIM32_ONE_PULSE_MODE_SINGLE + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_SetOnePulseMode(LPTIM32_Type *LPTIM32x, uint32_t mode) +{ + MODIFY_REG(LPTIM32x->CFGR, LPTIM32_CFGR_ONST_Msk, mode); +} + +/** + * @brief Get One State Timer Setting + * @rmtoll CFGR ONST FL_LPTIM32_GetOnePulseMode + * @param LPTIM32x LPTIM32 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPTIM32_ONE_PULSE_MODE_CONTINUOUS + * @arg @ref FL_LPTIM32_ONE_PULSE_MODE_SINGLE + */ +__STATIC_INLINE uint32_t FL_LPTIM32_GetOnePulseMode(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->CFGR, LPTIM32_CFGR_ONST_Msk)); +} + +/** + * @brief Set Operation Mode + * @rmtoll CFGR TMOD FL_LPTIM32_SetOperationMode + * @param LPTIM32x LPTIM32 instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_OPERATION_MODE_NORMAL + * @arg @ref FL_LPTIM32_OPERATION_MODE_EXTERNAL_TRIGGER_CNT + * @arg @ref FL_LPTIM32_OPERATION_MODE_EXTERNAL_ASYNC_PULSE_CNT + * @arg @ref FL_LPTIM32_OPERATION_MODE_TIMEOUT + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_SetOperationMode(LPTIM32_Type *LPTIM32x, uint32_t mode) +{ + MODIFY_REG(LPTIM32x->CFGR, LPTIM32_CFGR_TMOD_Msk, mode); +} + +/** + * @brief Get Operation Mode Setting + * @rmtoll CFGR TMOD FL_LPTIM32_GetOperationMode + * @param LPTIM32x LPTIM32 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPTIM32_OPERATION_MODE_NORMAL + * @arg @ref FL_LPTIM32_OPERATION_MODE_EXTERNAL_TRIGGER_CNT + * @arg @ref FL_LPTIM32_OPERATION_MODE_EXTERNAL_ASYNC_PULSE_CNT + * @arg @ref FL_LPTIM32_OPERATION_MODE_TIMEOUT + */ +__STATIC_INLINE uint32_t FL_LPTIM32_GetOperationMode(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->CFGR, LPTIM32_CFGR_TMOD_Msk)); +} + +/** + * @brief Set Channel 1 Compare Value + * @rmtoll CCR1 FL_LPTIM32_WriteCompareCH1 + * @param LPTIM32x LPTIM32 instance + * @param compareVal + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_WriteCompareCH1(LPTIM32_Type *LPTIM32x, uint32_t compareVal) +{ + MODIFY_REG(LPTIM32x->CCR1, (0xffffffffU << 0U), (compareVal << 0U)); +} + +/** + * @brief Get Channel 1 Compare Value + * @rmtoll CCR1 FL_LPTIM32_ReadCompareCH1 + * @param LPTIM32x LPTIM32 instance + * @retval + */ +__STATIC_INLINE uint32_t FL_LPTIM32_ReadCompareCH1(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->CCR1, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @brief Set Channel 2 Compare Value + * @rmtoll CCR2 FL_LPTIM32_WriteCompareCH2 + * @param LPTIM32x LPTIM32 instance + * @param compareVal + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_WriteCompareCH2(LPTIM32_Type *LPTIM32x, uint32_t compareVal) +{ + MODIFY_REG(LPTIM32x->CCR2, (0xffffffffU << 0U), (compareVal << 0U)); +} + +/** + * @brief Get Channel 2 Compare Value + * @rmtoll CCR2 FL_LPTIM32_ReadCompareCH2 + * @param LPTIM32x LPTIM32 instance + * @retval + */ +__STATIC_INLINE uint32_t FL_LPTIM32_ReadCompareCH2(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->CCR2, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @brief Get Channel 1 Capture Value + * @rmtoll CCR1 FL_LPTIM32_ReadCaptureCH1 + * @param LPTIM32x LPTIM32 instance + * @retval + */ +__STATIC_INLINE uint32_t FL_LPTIM32_ReadCaptureCH1(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->CCR1, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @brief Get Channel 2 Capture Value + * @rmtoll CCR2 FL_LPTIM32_ReadCaptureCH2 + * @param LPTIM32x LPTIM32 instance + * @retval + */ +__STATIC_INLINE uint32_t FL_LPTIM32_ReadCaptureCH2(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->CCR2, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @brief Enable Capture/Compare Channel1 Interrupt + * @rmtoll IER CCIE FL_LPTIM32_EnableIT_CC + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_EnableIT_CC(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + SET_BIT(LPTIM32x->IER, ((channel & 0x3) << 0x0U)); +} + +/** + * @brief Enable Counter Overflow Interrupt + * @rmtoll IER OVIE FL_LPTIM32_EnableIT_Update + * @param LPTIM32x LPTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_EnableIT_Update(LPTIM32_Type *LPTIM32x) +{ + SET_BIT(LPTIM32x->IER, LPTIM32_IER_OVIE_Msk); +} + +/** + * @brief Enable External Trigger Interrupt + * @rmtoll IER TRIGIE FL_LPTIM32_EnableIT_Trigger + * @param LPTIM32x LPTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_EnableIT_Trigger(LPTIM32_Type *LPTIM32x) +{ + SET_BIT(LPTIM32x->IER, LPTIM32_IER_TRIGIE_Msk); +} + +/** + * @brief Enable Channel1 Over-Capture Interrupt + * @rmtoll IER OVRIE FL_LPTIM32_EnableIT_CCOverflow + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_EnableIT_CCOverflow(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + SET_BIT(LPTIM32x->IER, ((channel & 0x3) << 0x8U)); +} + +/** + * @brief Disable Capture/Compare Channel1 Interrupt + * @rmtoll IER CCIE FL_LPTIM32_DisableIT_CC + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_DisableIT_CC(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + CLEAR_BIT(LPTIM32x->IER, ((channel & 0x3) << 0x0U)); +} + +/** + * @brief Disable Counter Overflow Interrupt + * @rmtoll IER OVIE FL_LPTIM32_DisableIT_Update + * @param LPTIM32x LPTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_DisableIT_Update(LPTIM32_Type *LPTIM32x) +{ + CLEAR_BIT(LPTIM32x->IER, LPTIM32_IER_OVIE_Msk); +} + +/** + * @brief Disable External Trigger Interrupt + * @rmtoll IER TRIGIE FL_LPTIM32_DisableIT_Trigger + * @param LPTIM32x LPTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_DisableIT_Trigger(LPTIM32_Type *LPTIM32x) +{ + CLEAR_BIT(LPTIM32x->IER, LPTIM32_IER_TRIGIE_Msk); +} + +/** + * @brief Disable Channel1 Over-Capture Interrupt + * @rmtoll IER OVRIE FL_LPTIM32_DisableIT_CCOverflow + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_DisableIT_CCOverflow(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + CLEAR_BIT(LPTIM32x->IER, ((channel & 0x3) << 0x8U)); +} + +/** + * @brief Get Capture/Compare Channel1 Interrupt Enable Status + * @rmtoll IER CCIE FL_LPTIM32_IsEnabledIT_CC + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPTIM32_IsEnabledIT_CC(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + return (uint32_t)(READ_BIT(LPTIM32x->IER, ((channel & 0x3) << 0x0U)) == ((channel & 0x3) << 0x0U)); +} + +/** + * @brief Get Counter Overflow Interrupt Enable Status + * @rmtoll IER OVIE FL_LPTIM32_IsEnabledIT_Update + * @param LPTIM32x LPTIM32 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPTIM32_IsEnabledIT_Update(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->IER, LPTIM32_IER_OVIE_Msk) == LPTIM32_IER_OVIE_Msk); +} + +/** + * @brief Get External Trigger Interrupt Enable Status + * @rmtoll IER TRIGIE FL_LPTIM32_IsEnabledIT_Trigger + * @param LPTIM32x LPTIM32 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPTIM32_IsEnabledIT_Trigger(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->IER, LPTIM32_IER_TRIGIE_Msk) == LPTIM32_IER_TRIGIE_Msk); +} + +/** + * @brief Get Channel1 Over-Capture Interrupt Enable Status + * @rmtoll IER OVRIE FL_LPTIM32_IsEnabledIT_CCOverflow + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPTIM32_IsEnabledIT_CCOverflow(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + return (uint32_t)(READ_BIT(LPTIM32x->IER, ((channel & 0x3) << 0x8U)) == ((channel & 0x3) << 0x8U)); +} + +/** + * @brief Get Capture/Compare Channel 1 Interrupt Flag + * @rmtoll ISR CCIF FL_LPTIM32_IsActiveFlag_CC + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_LPTIM32_IsActiveFlag_CC(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + return (uint32_t)(READ_BIT(LPTIM32x->ISR, ((channel & 0x3) << 0x0U)) == ((channel & 0x3) << 0x0U)); +} + +/** + * @brief Get External Trigger Interrupt Flag + * @rmtoll ISR OVIF FL_LPTIM32_IsActiveFlag_Update + * @param LPTIM32x LPTIM32 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPTIM32_IsActiveFlag_Update(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->ISR, LPTIM32_ISR_OVIF_Msk) == (LPTIM32_ISR_OVIF_Msk)); +} + +/** + * @brief Get External Trigger Interrupt Flag + * @rmtoll ISR TRIGIF FL_LPTIM32_IsActiveFlag_Trigger + * @param LPTIM32x LPTIM32 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPTIM32_IsActiveFlag_Trigger(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->ISR, LPTIM32_ISR_TRIGIF_Msk) == (LPTIM32_ISR_TRIGIF_Msk)); +} + +/** + * @brief Get Channel 1 Over-Capture Interrupt Flag + * @rmtoll ISR CAPOVR FL_LPTIM32_IsActiveFlag_CCOverflow + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_LPTIM32_IsActiveFlag_CCOverflow(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + return (uint32_t)(READ_BIT(LPTIM32x->ISR, ((channel & 0x3) << 0x8U)) == ((channel & 0x3) << 0x8U)); +} + +/** + * @brief Clear Capture/Compare Channel 1 Interrupt Flag + * @rmtoll ISR CCIF FL_LPTIM32_ClearFlag_CC + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_ClearFlag_CC(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + WRITE_REG(LPTIM32x->ISR, ((channel & 0x3) << 0x0U)); +} + +/** + * @brief Clear External Trigger Interrupt Flag + * @rmtoll ISR OVIF FL_LPTIM32_ClearFlag_Update + * @param LPTIM32x LPTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_ClearFlag_Update(LPTIM32_Type *LPTIM32x) +{ + WRITE_REG(LPTIM32x->ISR, LPTIM32_ISR_OVIF_Msk); +} + +/** + * @brief Clear External Trigger Interrupt Flag + * @rmtoll ISR TRIGIF FL_LPTIM32_ClearFlag_Trigger + * @param LPTIM32x LPTIM32 instance + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_ClearFlag_Trigger(LPTIM32_Type *LPTIM32x) +{ + WRITE_REG(LPTIM32x->ISR, LPTIM32_ISR_TRIGIF_Msk); +} + +/** + * @brief Clear Channel 1 Over-Capture Interrupt Flag + * @rmtoll ISR CAPOVR FL_LPTIM32_ClearFlag_CCOverflow + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_ClearFlag_CCOverflow(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + WRITE_REG(LPTIM32x->ISR, ((channel & 0x3) << 0x8U)); +} + +/** + * @brief Set Auto Reload Value + * @rmtoll ARR FL_LPTIM32_WriteAutoReload + * @param LPTIM32x LPTIM32 instance + * @param autoReload + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_WriteAutoReload(LPTIM32_Type *LPTIM32x, uint32_t autoReload) +{ + MODIFY_REG(LPTIM32x->ARR, (0xffffffffU << 0U), (autoReload << 0U)); +} + +/** + * @brief Get Auto Reload Value + * @rmtoll ARR FL_LPTIM32_ReadAutoReload + * @param LPTIM32x LPTIM32 instance + * @retval + */ +__STATIC_INLINE uint32_t FL_LPTIM32_ReadAutoReload(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->ARR, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @brief Set Input Capture Channel Capture Edge + * @rmtoll CCSR CAPCFG FL_LPTIM32_IC_SetCaptureEdge + * @param LPTIM32x LPTIM32 instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_IC_EDGE_RISING + * @arg @ref FL_LPTIM32_IC_EDGE_FALLING + * @arg @ref FL_LPTIM32_IC_EDGE_BOTH + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_IC_SetCaptureEdge(LPTIM32_Type *LPTIM32x, uint32_t polarity, uint32_t channel) +{ + switch(channel) + { + case FL_LPTIM32_CHANNEL_1: + MODIFY_REG(LPTIM32x->CCSR, (0x3U << 8U), (polarity << 0U)); + break; + case FL_LPTIM32_CHANNEL_2: + MODIFY_REG(LPTIM32x->CCSR, (0x3U << 10U), (polarity << 2U)); + break; + } +} + +/** + * @brief Get Input Capture Channel Capture Edge + * @rmtoll CCSR CAPCFG FL_LPTIM32_IC_GetCaptureEdge + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPTIM32_IC_EDGE_RISING + * @arg @ref FL_LPTIM32_IC_EDGE_FALLING + * @arg @ref FL_LPTIM32_IC_EDGE_BOTH + */ +__STATIC_INLINE uint32_t FL_LPTIM32_IC_GetCaptureEdge(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + switch(channel) + { + case FL_LPTIM32_CHANNEL_1: + return (uint32_t)(READ_BIT(LPTIM32x->CCSR, (0x3U << 8U)) >> 0U); + case FL_LPTIM32_CHANNEL_2: + return (uint32_t)(READ_BIT(LPTIM32x->CCSR, (0x3U << 10U)) >> 2U); + default: + return 0; + } +} + +/** + * @brief Set Channel Output Compare Polarity + * @rmtoll CCSR POLAR FL_LPTIM32_OC_SetPolarity + * @param LPTIM32x LPTIM32 instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_OC_POLARITY_NORMAL + * @arg @ref FL_LPTIM32_OC_POLARITY_INVERT + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_OC_SetPolarity(LPTIM32_Type *LPTIM32x, uint32_t polarity, uint32_t channel) +{ + switch(channel) + { + case FL_LPTIM32_CHANNEL_1: + MODIFY_REG(LPTIM32x->CCSR, (0x1U << 4U), (polarity << 0U)); + break; + case FL_LPTIM32_CHANNEL_2: + MODIFY_REG(LPTIM32x->CCSR, (0x1U << 5U), (polarity << 1U)); + break; + } +} + +/** + * @brief Get Channel Output Compare Polarity + * @rmtoll CCSR POLAR FL_LPTIM32_OC_GetPolarity + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPTIM32_OC_POLARITY_NORMAL + * @arg @ref FL_LPTIM32_OC_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_LPTIM32_OC_GetPolarity(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + switch(channel) + { + case FL_LPTIM32_CHANNEL_1: + return (uint32_t)(READ_BIT(LPTIM32x->CCSR, (0x1U << 4U)) >> 0U); + case FL_LPTIM32_CHANNEL_2: + return (uint32_t)(READ_BIT(LPTIM32x->CCSR, (0x1U << 5U)) >> 1U); + default: + return 0; + } +} + +/** + * @brief Set Channel Operation Mode + * @rmtoll CCSR CCS FL_LPTIM32_SetChannelMode + * @param LPTIM32x LPTIM32 instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_MODE_DISABLE + * @arg @ref FL_LPTIM32_CHANNEL_MODE_INPUT + * @arg @ref FL_LPTIM32_CHANNEL_MODE_OUTPUT + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_SetChannelMode(LPTIM32_Type *LPTIM32x, uint32_t mode, uint32_t channel) +{ + switch(channel) + { + case FL_LPTIM32_CHANNEL_1: + MODIFY_REG(LPTIM32x->CCSR, (0x3U << 0U), (mode << 0U)); + break; + case FL_LPTIM32_CHANNEL_2: + MODIFY_REG(LPTIM32x->CCSR, (0x3U << 2U), (mode << 2U)); + break; + } +} + +/** + * @brief Get Channel Operation Mode + * @rmtoll CCSR CCS FL_LPTIM32_GetChannelMode + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_MODE_DISABLE + * @arg @ref FL_LPTIM32_CHANNEL_MODE_INPUT + * @arg @ref FL_LPTIM32_CHANNEL_MODE_OUTPUT + */ +__STATIC_INLINE uint32_t FL_LPTIM32_GetChannelMode(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + switch(channel) + { + case FL_LPTIM32_CHANNEL_1: + return (uint32_t)(READ_BIT(LPTIM32x->CCSR, (0x3U << 0U)) >> 0U); + case FL_LPTIM32_CHANNEL_2: + return (uint32_t)(READ_BIT(LPTIM32x->CCSR, (0x3U << 2U)) >> 2U); + default: + return 0; + } +} + +/** + * @brief Get Channel Captured Edge + * @rmtoll CCSR CAPEDGE FL_LPTIM32_IC_GetCapturedEdge + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPTIM32_IC_CAPTURED_EDGE_RISING + * @arg @ref FL_LPTIM32_IC_CAPTURED_EDGE_FALLING + */ +__STATIC_INLINE uint32_t FL_LPTIM32_IC_GetCapturedEdge(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + switch(channel) + { + case FL_LPTIM32_CHANNEL_1: + return (uint32_t)(READ_BIT(LPTIM32x->CCSR, (0x1U << 12U)) >> 0U); + case FL_LPTIM32_CHANNEL_2: + return (uint32_t)(READ_BIT(LPTIM32x->CCSR, (0x1U << 13U)) >> 1U); + default: + return 0; + } +} + +/** + * @brief Set Channel Capture Source + * @rmtoll CCSR CAPSSEL FL_LPTIM32_IC_SetCaptureSource + * @param LPTIM32x LPTIM32 instance + * @param source This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP0 + * @arg @ref FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP1 + * @arg @ref FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP2 + * @arg @ref FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP3 + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void FL_LPTIM32_IC_SetCaptureSource(LPTIM32_Type *LPTIM32x, uint32_t source, uint32_t channel) +{ + switch(channel) + { + case FL_LPTIM32_CHANNEL_1: + MODIFY_REG(LPTIM32x->CCSR, (0x3U << 16U), (source << 0U)); + break; + case FL_LPTIM32_CHANNEL_2: + MODIFY_REG(LPTIM32x->CCSR, (0x3U << 18U), (source << 2U)); + break; + } +} + +/** + * @brief Get Channel Capture Source Setting + * @rmtoll CCSR CAPSSEL FL_LPTIM32_IC_GetCaptureSource + * @param LPTIM32x LPTIM32 instance + * @param channel This parameter can be one of the following values: + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP0 + * @arg @ref FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP1 + * @arg @ref FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP2 + * @arg @ref FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP3 + */ +__STATIC_INLINE uint32_t FL_LPTIM32_IC_GetCaptureSource(LPTIM32_Type *LPTIM32x, uint32_t channel) +{ + switch(channel) + { + case FL_LPTIM32_CHANNEL_1: + return (uint32_t)(READ_BIT(LPTIM32x->CCSR, (0x1U << 16U)) >> 0U); + case FL_LPTIM32_CHANNEL_2: + return (uint32_t)(READ_BIT(LPTIM32x->CCSR, (0x1U << 18U)) >> 2U); + default: + return 0; + } +} + +/** + * @brief Get LPTIM32 32bit Counter Value + * @rmtoll CNT FL_LPTIM32_ReadCounter + * @param LPTIM32x LPTIM32 instance + * @retval + */ +__STATIC_INLINE uint32_t FL_LPTIM32_ReadCounter(LPTIM32_Type *LPTIM32x) +{ + return (uint32_t)(READ_BIT(LPTIM32x->CNT, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @brief Set LPTIM32 32bit Counter Value + * @rmtoll CNT FL_LPTIM32_WriteCounter + * @param LPTIM32x LPTIM32 instance + * @param value + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE void FL_LPTIM32_WriteCounter(LPTIM32_Type *LPTIM32x, uint32_t value) +{ + MODIFY_REG(LPTIM32x->CNT, (0xffffffffU << 0U), (value << 0U)); +} + +/** + * @} + */ + +/** @defgroup LPTIM32_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_LPTIM32_DeInit(LPTIM32_Type *LPTIM32x); +FL_ErrorStatus FL_LPTIM32_Init(LPTIM32_Type *LPTIM32x, FL_LPTIM32_InitTypeDef *initStruct); +void FL_LPTIM32_StructInit(FL_LPTIM32_InitTypeDef *initStruct); +FL_ErrorStatus FL_LPTIM32_IC_Init(LPTIM32_Type *LPTIM32x, uint32_t channel, FL_LPTIM32_IC_InitTypeDef *initStruct_IC); +void FL_LPTIM32_IC_StructInit(FL_LPTIM32_IC_InitTypeDef *initStruct_IC); +FL_ErrorStatus FL_LPTIM32_OC_Init(LPTIM32_Type *LPTIM32x, uint32_t channel, FL_LPTIM32_OC_InitTypeDef *initStruct_OC); +void FL_LPTIM32_OC_StructInit(FL_LPTIM32_OC_InitTypeDef *initStruct_OC); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_LPTIM32_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_lpuart.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_lpuart.h new file mode 100644 index 0000000000..16071e320b --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_lpuart.h @@ -0,0 +1,1092 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_lpuart.h + * @author FMSH Application Team + * @brief Head file of LPUART FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_LPUART_H +#define __FM33LC0XX_FL_LPUART_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup LPUART LPUART + * @brief LPUART FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup LPUART_FL_ES_INIT LPUART Exported Init structures + * @{ + */ + +/** + * @brief LPUART Init Sturcture definition + */ +typedef struct +{ + /** 时钟源选择 */ + uint32_t clockSrc; + /** 通讯波特率*/ + uint32_t baudRate; + /** 数据位宽*/ + uint32_t dataWidth; + /** 停止位 */ + uint32_t stopBits; + /** 奇偶校验 */ + uint32_t parity; + /** 传输方向 */ + uint32_t transferDirection; + +} FL_LPUART_InitTypeDef; + +/** + * @} + */ + +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup LPUART_FL_Exported_Constants LPUART Exported Constants + * @{ + */ + +#define LPUART_CSR_BUSY_Pos (24U) +#define LPUART_CSR_BUSY_Msk (0x1U << LPUART_CSR_BUSY_Pos) +#define LPUART_CSR_BUSY LPUART_CSR_BUSY_Msk + +#define LPUART_CSR_WKBYTE_CFG_Pos (19U) +#define LPUART_CSR_WKBYTE_CFG_Msk (0x1U << LPUART_CSR_WKBYTE_CFG_Pos) +#define LPUART_CSR_WKBYTE_CFG LPUART_CSR_WKBYTE_CFG_Msk + +#define LPUART_CSR_RXEV_Pos (16U) +#define LPUART_CSR_RXEV_Msk (0x3U << LPUART_CSR_RXEV_Pos) +#define LPUART_CSR_RXEV LPUART_CSR_RXEV_Msk + +#define LPUART_CSR_IOSWAP_Pos (11U) +#define LPUART_CSR_IOSWAP_Msk (0x1U << LPUART_CSR_IOSWAP_Pos) +#define LPUART_CSR_IOSWAP LPUART_CSR_IOSWAP_Msk + +#define LPUART_CSR_DMATXIFCFG_Pos (10U) +#define LPUART_CSR_DMATXIFCFG_Msk (0x1U << LPUART_CSR_DMATXIFCFG_Pos) +#define LPUART_CSR_DMATXIFCFG LPUART_CSR_DMATXIFCFG_Msk + +#define LPUART_CSR_BITORD_Pos (9U) +#define LPUART_CSR_BITORD_Msk (0x1U << LPUART_CSR_BITORD_Pos) +#define LPUART_CSR_BITORD LPUART_CSR_BITORD_Msk + +#define LPUART_CSR_STOPCFG_Pos (8U) +#define LPUART_CSR_STOPCFG_Msk (0x1U << LPUART_CSR_STOPCFG_Pos) +#define LPUART_CSR_STOPCFG LPUART_CSR_STOPCFG_Msk + +#define LPUART_CSR_PDSEL_Pos (6U) +#define LPUART_CSR_PDSEL_Msk (0x3U << LPUART_CSR_PDSEL_Pos) +#define LPUART_CSR_PDSEL LPUART_CSR_PDSEL_Msk + +#define LPUART_CSR_PARITY_Pos (4U) +#define LPUART_CSR_PARITY_Msk (0x3U << LPUART_CSR_PARITY_Pos) +#define LPUART_CSR_PARITY LPUART_CSR_PARITY_Msk + +#define LPUART_CSR_RXPOL_Pos (3U) +#define LPUART_CSR_RXPOL_Msk (0x1U << LPUART_CSR_RXPOL_Pos) +#define LPUART_CSR_RXPOL LPUART_CSR_RXPOL_Msk + +#define LPUART_CSR_TXPOL_Pos (2U) +#define LPUART_CSR_TXPOL_Msk (0x1U << LPUART_CSR_TXPOL_Pos) +#define LPUART_CSR_TXPOL LPUART_CSR_TXPOL_Msk + +#define LPUART_CSR_RXEN_Pos (1U) +#define LPUART_CSR_RXEN_Msk (0x1U << LPUART_CSR_RXEN_Pos) +#define LPUART_CSR_RXEN LPUART_CSR_RXEN_Msk + +#define LPUART_CSR_TXEN_Pos (0U) +#define LPUART_CSR_TXEN_Msk (0x1U << LPUART_CSR_TXEN_Pos) +#define LPUART_CSR_TXEN LPUART_CSR_TXEN_Msk + +#define LPUART_IER_RXEV_IE_Pos (12U) +#define LPUART_IER_RXEV_IE_Msk (0x1U << LPUART_IER_RXEV_IE_Pos) +#define LPUART_IER_RXEV_IE LPUART_IER_RXEV_IE_Msk + +#define LPUART_IER_RXERR_IE_Pos (10U) +#define LPUART_IER_RXERR_IE_Msk (0x1U << LPUART_IER_RXERR_IE_Pos) +#define LPUART_IER_RXERR_IE LPUART_IER_RXERR_IE_Msk + +#define LPUART_IER_RXBF_IE_Pos (8U) +#define LPUART_IER_RXBF_IE_Msk (0x1U << LPUART_IER_RXBF_IE_Pos) +#define LPUART_IER_RXBF_IE LPUART_IER_RXBF_IE_Msk + +#define LPUART_IER_TXBE_IE_Pos (1U) +#define LPUART_IER_TXBE_IE_Msk (0x1U << LPUART_IER_TXBE_IE_Pos) +#define LPUART_IER_TXBE_IE LPUART_IER_TXBE_IE_Msk + +#define LPUART_IER_TXSE_IE_Pos (0U) +#define LPUART_IER_TXSE_IE_Msk (0x1U << LPUART_IER_TXSE_IE_Pos) +#define LPUART_IER_TXSE_IE LPUART_IER_TXSE_IE_Msk + +#define LPUART_ISR_RXEVF_Pos (24U) +#define LPUART_ISR_RXEVF_Msk (0x1U << LPUART_ISR_RXEVF_Pos) +#define LPUART_ISR_RXEVF LPUART_ISR_RXEVF_Msk + +#define LPUART_ISR_TXOV_Pos (19U) +#define LPUART_ISR_TXOV_Msk (0x1U << LPUART_ISR_TXOV_Pos) +#define LPUART_ISR_TXOV LPUART_ISR_TXOV_Msk + +#define LPUART_ISR_PERR_Pos (18U) +#define LPUART_ISR_PERR_Msk (0x1U << LPUART_ISR_PERR_Pos) +#define LPUART_ISR_PERR LPUART_ISR_PERR_Msk + +#define LPUART_ISR_FERR_Pos (17U) +#define LPUART_ISR_FERR_Msk (0x1U << LPUART_ISR_FERR_Pos) +#define LPUART_ISR_FERR LPUART_ISR_FERR_Msk + +#define LPUART_ISR_OERR_Pos (16U) +#define LPUART_ISR_OERR_Msk (0x1U << LPUART_ISR_OERR_Pos) +#define LPUART_ISR_OERR LPUART_ISR_OERR_Msk + +#define LPUART_ISR_RXBF_Pos (8U) +#define LPUART_ISR_RXBF_Msk (0x1U << LPUART_ISR_RXBF_Pos) +#define LPUART_ISR_RXBF LPUART_ISR_RXBF_Msk + +#define LPUART_ISR_TXBE_Pos (1U) +#define LPUART_ISR_TXBE_Msk (0x1U << LPUART_ISR_TXBE_Pos) +#define LPUART_ISR_TXBE LPUART_ISR_TXBE_Msk + +#define LPUART_ISR_TXSE_Pos (0U) +#define LPUART_ISR_TXSE_Msk (0x1U << LPUART_ISR_TXSE_Pos) +#define LPUART_ISR_TXSE LPUART_ISR_TXSE_Msk + +#define LPUART_BMR_BAUD_Pos (0U) +#define LPUART_BMR_BAUD_Msk (0x7U << LPUART_BMR_BAUD_Pos) +#define LPUART_BMR_BAUD LPUART_BMR_BAUD_Msk + +#define LPUART_BMR_MCTL_Pos (16U) +#define LPUART_BMR_MCTL_Msk (0xfffU << LPUART_BMR_MCTL_Pos) +#define LPUART_BMR_MCTL LPUART_BMR_MCTL_Msk + + + + + + +#define FL_LPUART_WAKEUP_NO_CHECK (0x0U << LPUART_CSR_WKBYTE_CFG_Pos) +#define FL_LPUART_WAKEUP_CHECK (0x1U << LPUART_CSR_WKBYTE_CFG_Pos) + + +#define FL_LPUART_WAKEUP_EVENT_START (0x0U << LPUART_CSR_RXEV_Pos) +#define FL_LPUART_WAKEUP_EVENT_RECV_1BYTE (0x1U << LPUART_CSR_RXEV_Pos) +#define FL_LPUART_WAKEUP_EVENT_RECV_MATCH (0x2U << LPUART_CSR_RXEV_Pos) +#define FL_LPUART_WAKEUP_EVENT_RX_FALLING (0x3U << LPUART_CSR_RXEV_Pos) + + +#define FL_LPUART_TXIF_MODE_ALWAYS (0x0U << LPUART_CSR_DMATXIFCFG_Pos) +#define FL_LPUART_TXIF_MODE_AFTER_DMA (0x1U << LPUART_CSR_DMATXIFCFG_Pos) + + +#define FL_LPUART_BIT_ORDER_LSB_FIRST (0x0U << LPUART_CSR_BITORD_Pos) +#define FL_LPUART_BIT_ORDER_MSB_FIRST (0x1U << LPUART_CSR_BITORD_Pos) + + +#define FL_LPUART_STOP_BIT_WIDTH_1B (0x0U << LPUART_CSR_STOPCFG_Pos) +#define FL_LPUART_STOP_BIT_WIDTH_2B (0x1U << LPUART_CSR_STOPCFG_Pos) + + +#define FL_LPUART_DATA_WIDTH_7B (0x0U << LPUART_CSR_PDSEL_Pos) +#define FL_LPUART_DATA_WIDTH_8B (0x1U << LPUART_CSR_PDSEL_Pos) +#define FL_LPUART_DATA_WIDTH_9B (0x2U << LPUART_CSR_PDSEL_Pos) +#define FL_LPUART_DATA_WIDTH_6B (0x3U << LPUART_CSR_PDSEL_Pos) + + +#define FL_LPUART_PARITY_NONE (0x0U << LPUART_CSR_PARITY_Pos) +#define FL_LPUART_PARITY_EVEN (0x1U << LPUART_CSR_PARITY_Pos) +#define FL_LPUART_PARITY_ODD (0x2U << LPUART_CSR_PARITY_Pos) + + +#define FL_LPUART_RX_POLARITY_NORMAL (0x0U << LPUART_CSR_RXPOL_Pos) +#define FL_LPUART_RX_POLARITY_INVERT (0x1U << LPUART_CSR_RXPOL_Pos) + + +#define FL_LPUART_TX_POLARITY_NORMAL (0x0U << LPUART_CSR_TXPOL_Pos) +#define FL_LPUART_TX_POLARITY_INVERT (0x1U << LPUART_CSR_TXPOL_Pos) + + +#define FL_LPUART_BAUDRATE_9600 (0x0U << LPUART_BMR_BAUD_Pos) +#define FL_LPUART_BAUDRATE_4800 (0x1U << LPUART_BMR_BAUD_Pos) +#define FL_LPUART_BAUDRATE_2400 (0x2U << LPUART_BMR_BAUD_Pos) +#define FL_LPUART_BAUDRATE_1200 (0x3U << LPUART_BMR_BAUD_Pos) +#define FL_LPUART_BAUDRATE_600 (0x4U << LPUART_BMR_BAUD_Pos) +#define FL_LPUART_BAUDRATE_300 (0x5U << LPUART_BMR_BAUD_Pos) + + +#define FL_LPUART_DIRECTION_NONE 0x00000000U +#define FL_LPUART_DIRECTION_RX LPUART_CSR_RXEN +#define FL_LPUART_DIRECTION_TX LPUART_CSR_TXEN +#define FL_LPUART_DIRECTION_TX_RX (LPUART_CSR_RXEN|LPUART_CSR_TXEN) +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup LPUART_FL_Exported_Functions LPUART Exported Functions + * @{ + */ + +/** + * @brief Get LPUART Busy Flag + * @rmtoll CSR BUSY FL_LPUART_IsActiveFlag_Busy + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsActiveFlag_Busy(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CSR, LPUART_CSR_BUSY_Msk) == (LPUART_CSR_BUSY_Msk)); +} + +/** + * @brief Set Data Receive Wakeup Mode + * @rmtoll CSR WKBYTE_CFG FL_LPUART_SetRXWakeupMode + * @param LPUARTx LPUART instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_LPUART_WAKEUP_NO_CHECK + * @arg @ref FL_LPUART_WAKEUP_CHECK + * @retval None + */ +__STATIC_INLINE void FL_LPUART_SetRXWakeupMode(LPUART_Type *LPUARTx, uint32_t mode) +{ + MODIFY_REG(LPUARTx->CSR, LPUART_CSR_WKBYTE_CFG_Msk, mode); +} + +/** + * @brief Get Data Receive Wakeup Mode Setting + * @rmtoll CSR WKBYTE_CFG FL_LPUART_GetRXWakeupMode + * @param LPUARTx LPUART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPUART_WAKEUP_NO_CHECK + * @arg @ref FL_LPUART_WAKEUP_CHECK + */ +__STATIC_INLINE uint32_t FL_LPUART_GetRXWakeupMode(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CSR, LPUART_CSR_WKBYTE_CFG_Msk)); +} + +/** + * @brief Set Receive Wakeup Event + * @rmtoll CSR RXEV FL_LPUART_SetWakeup + * @param LPUARTx LPUART instance + * @param event This parameter can be one of the following values: + * @arg @ref FL_LPUART_WAKEUP_EVENT_START + * @arg @ref FL_LPUART_WAKEUP_EVENT_RECV_1BYTE + * @arg @ref FL_LPUART_WAKEUP_EVENT_RECV_MATCH + * @arg @ref FL_LPUART_WAKEUP_EVENT_RX_FALLING + * @retval None + */ +__STATIC_INLINE void FL_LPUART_SetWakeup(LPUART_Type *LPUARTx, uint32_t event) +{ + MODIFY_REG(LPUARTx->CSR, LPUART_CSR_RXEV_Msk, event); +} + +/** + * @brief Get Receive Wakeup Event Setting + * @rmtoll CSR RXEV FL_LPUART_GetWakeup + * @param LPUARTx LPUART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPUART_WAKEUP_EVENT_START + * @arg @ref FL_LPUART_WAKEUP_EVENT_RECV_1BYTE + * @arg @ref FL_LPUART_WAKEUP_EVENT_RECV_MATCH + * @arg @ref FL_LPUART_WAKEUP_EVENT_RX_FALLING + */ +__STATIC_INLINE uint32_t FL_LPUART_GetWakeup(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CSR, LPUART_CSR_RXEV_Msk)); +} + +/** + * @brief Enable LPUART Pin Swap Between TX Pin and RX Pin + * @rmtoll CSR IOSWAP FL_LPUART_EnablePinSwap + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_EnablePinSwap(LPUART_Type *LPUARTx) +{ + SET_BIT(LPUARTx->CSR, LPUART_CSR_IOSWAP_Msk); +} + +/** + * @brief Disable LPUART Pin Swap Between TX Pin and RX Pin + * @rmtoll CSR IOSWAP FL_LPUART_DisablePinSwap + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_DisablePinSwap(LPUART_Type *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CSR, LPUART_CSR_IOSWAP_Msk); +} + +/** + * @brief Get UART Pin Swap Enable Status Between UART TX Pin and RX Pin + + * @rmtoll CSR IOSWAP FL_LPUART_IsEnabledPinSwap + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsEnabledPinSwap(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CSR, LPUART_CSR_IOSWAP_Msk) == LPUART_CSR_IOSWAP_Msk); +} + +/** + * @brief Enable DMA TX Complete Interrupt + * @rmtoll CSR DMATXIFCFG FL_LPUART_SetTXIFMode + * @param LPUARTx LPUART instance + * @param txifMode This parameter can be one of the following values: + * @arg @ref FL_LPUART_TXIF_MODE_ALWAYS + * @arg @ref FL_LPUART_TXIF_MODE_AFTER_DMA + * @retval None + */ +__STATIC_INLINE void FL_LPUART_SetTXIFMode(LPUART_Type *LPUARTx, uint32_t txifMode) +{ + MODIFY_REG(LPUARTx->CSR, LPUART_CSR_DMATXIFCFG_Msk, txifMode); +} + +/** + * @brief Disable DMA TX Complete Interrupt + * @rmtoll CSR DMATXIFCFG FL_LPUART_GetTXIFMode + * @param LPUARTx LPUART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPUART_TXIF_MODE_ALWAYS + * @arg @ref FL_LPUART_TXIF_MODE_AFTER_DMA + */ +__STATIC_INLINE uint32_t FL_LPUART_GetTXIFMode(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CSR, LPUART_CSR_DMATXIFCFG_Msk)); +} + +/** + * @brief Set LPUART Transfer Bit Order + * @rmtoll CSR BITORD FL_LPUART_SetBitOrder + * @param LPUARTx LPUART instance + * @param bitOrder This parameter can be one of the following values: + * @arg @ref FL_LPUART_BIT_ORDER_LSB_FIRST + * @arg @ref FL_LPUART_BIT_ORDER_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void FL_LPUART_SetBitOrder(LPUART_Type *LPUARTx, uint32_t bitOrder) +{ + MODIFY_REG(LPUARTx->CSR, LPUART_CSR_BITORD_Msk, bitOrder); +} + +/** + * @brief Get LPUART Transfer Bit Order Setting + * @rmtoll CSR BITORD FL_LPUART_GetBitOrder + * @param LPUARTx LPUART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPUART_BIT_ORDER_LSB_FIRST + * @arg @ref FL_LPUART_BIT_ORDER_MSB_FIRST + */ +__STATIC_INLINE uint32_t FL_LPUART_GetBitOrder(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CSR, LPUART_CSR_BITORD_Msk)); +} + +/** + * @brief Set LPUART Stop Bits Length + * @rmtoll CSR STOPCFG FL_LPUART_SetStopBitsWidth + * @param LPUARTx LPUART instance + * @param stopBits This parameter can be one of the following values: + * @arg @ref FL_LPUART_STOP_BIT_WIDTH_1B + * @arg @ref FL_LPUART_STOP_BIT_WIDTH_2B + * @retval None + */ +__STATIC_INLINE void FL_LPUART_SetStopBitsWidth(LPUART_Type *LPUARTx, uint32_t stopBits) +{ + MODIFY_REG(LPUARTx->CSR, LPUART_CSR_STOPCFG_Msk, stopBits); +} + +/** + * @brief Get LPUART Stop Bits Length Setting + * @rmtoll CSR STOPCFG FL_LPUART_GetStopBitsWidth + * @param LPUARTx LPUART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPUART_STOP_BIT_WIDTH_1B + * @arg @ref FL_LPUART_STOP_BIT_WIDTH_2B + */ +__STATIC_INLINE uint32_t FL_LPUART_GetStopBitsWidth(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CSR, LPUART_CSR_STOPCFG_Msk)); +} + +/** + * @brief Set LPUART Data Width + * @rmtoll CSR PDSEL FL_LPUART_SetDataWidth + * @param LPUARTx LPUART instance + * @param dataWidth This parameter can be one of the following values: + * @arg @ref FL_LPUART_DATA_WIDTH_7B + * @arg @ref FL_LPUART_DATA_WIDTH_8B + * @arg @ref FL_LPUART_DATA_WIDTH_9B + * @arg @ref FL_LPUART_DATA_WIDTH_6B + * @retval None + */ +__STATIC_INLINE void FL_LPUART_SetDataWidth(LPUART_Type *LPUARTx, uint32_t dataWidth) +{ + MODIFY_REG(LPUARTx->CSR, LPUART_CSR_PDSEL_Msk, dataWidth); +} + +/** + * @brief Get LPUART Stop Bits Length Setting + * @rmtoll CSR PDSEL FL_LPUART_GetDataWidth + * @param LPUARTx LPUART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPUART_DATA_WIDTH_7B + * @arg @ref FL_LPUART_DATA_WIDTH_8B + * @arg @ref FL_LPUART_DATA_WIDTH_9B + * @arg @ref FL_LPUART_DATA_WIDTH_6B + */ +__STATIC_INLINE uint32_t FL_LPUART_GetDataWidth(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CSR, LPUART_CSR_PDSEL_Msk)); +} + +/** + * @brief Set LPUART Parity + * @rmtoll CSR PARITY FL_LPUART_SetParity + * @param LPUARTx LPUART instance + * @param parity This parameter can be one of the following values: + * @arg @ref FL_LPUART_PARITY_NONE + * @arg @ref FL_LPUART_PARITY_EVEN + * @arg @ref FL_LPUART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void FL_LPUART_SetParity(LPUART_Type *LPUARTx, uint32_t parity) +{ + MODIFY_REG(LPUARTx->CSR, LPUART_CSR_PARITY_Msk, parity); +} + +/** + * @brief Get LPUART Parity Setting + * @rmtoll CSR PARITY FL_LPUART_GetParity + * @param LPUARTx LPUART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPUART_PARITY_NONE + * @arg @ref FL_LPUART_PARITY_EVEN + * @arg @ref FL_LPUART_PARITY_ODD + */ +__STATIC_INLINE uint32_t FL_LPUART_GetParity(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CSR, LPUART_CSR_PARITY_Msk)); +} + +/** + * @brief Set LPUART Receive Polarity + * @rmtoll CSR RXPOL FL_LPUART_SetRXPolarity + * @param LPUARTx LPUART instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_LPUART_RX_POLARITY_NORMAL + * @arg @ref FL_LPUART_RX_POLARITY_INVERT + * @retval None + */ +__STATIC_INLINE void FL_LPUART_SetRXPolarity(LPUART_Type *LPUARTx, uint32_t polarity) +{ + MODIFY_REG(LPUARTx->CSR, LPUART_CSR_RXPOL_Msk, polarity); +} + +/** + * @brief Get LPUART Receive Polarity Setting + * @rmtoll CSR RXPOL FL_LPUART_GetRXPolarity + * @param LPUARTx LPUART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPUART_RX_POLARITY_NORMAL + * @arg @ref FL_LPUART_RX_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_LPUART_GetRXPolarity(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CSR, LPUART_CSR_RXPOL_Msk)); +} + +/** + * @brief Set LPUART Transmit Polarity + * @rmtoll CSR TXPOL FL_LPUART_SetTXPolarity + * @param LPUARTx LPUART instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_LPUART_TX_POLARITY_NORMAL + * @arg @ref FL_LPUART_TX_POLARITY_INVERT + * @retval None + */ +__STATIC_INLINE void FL_LPUART_SetTXPolarity(LPUART_Type *LPUARTx, uint32_t polarity) +{ + MODIFY_REG(LPUARTx->CSR, LPUART_CSR_TXPOL_Msk, polarity); +} + +/** + * @brief Get LPUART Transmit Polarity Setting + * @rmtoll CSR TXPOL FL_LPUART_GetTXPolarity + * @param LPUARTx LPUART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPUART_TX_POLARITY_NORMAL + * @arg @ref FL_LPUART_TX_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_LPUART_GetTXPolarity(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CSR, LPUART_CSR_TXPOL_Msk)); +} + +/** + * @brief Enable LPUART Receive + * @rmtoll CSR RXEN FL_LPUART_EnableRX + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_EnableRX(LPUART_Type *LPUARTx) +{ + SET_BIT(LPUARTx->CSR, LPUART_CSR_RXEN_Msk); +} + +/** + * @brief Get LPUART Receive Enable Status + * @rmtoll CSR RXEN FL_LPUART_IsEnabledRX + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsEnabledRX(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CSR, LPUART_CSR_RXEN_Msk) == LPUART_CSR_RXEN_Msk); +} + +/** + * @brief Disable LPUART Receive + * @rmtoll CSR RXEN FL_LPUART_DisableRX + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_DisableRX(LPUART_Type *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CSR, LPUART_CSR_RXEN_Msk); +} + +/** + * @brief Enable LPUART Receive + * @rmtoll CSR TXEN FL_LPUART_EnableTX + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_EnableTX(LPUART_Type *LPUARTx) +{ + SET_BIT(LPUARTx->CSR, LPUART_CSR_TXEN_Msk); +} + +/** + * @brief Get LPUART Receive Enable Status + * @rmtoll CSR TXEN FL_LPUART_IsEnabledTX + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsEnabledTX(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CSR, LPUART_CSR_TXEN_Msk) == LPUART_CSR_TXEN_Msk); +} + +/** + * @brief Disable LPUART Receive + * @rmtoll CSR TXEN FL_LPUART_DisableTX + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_DisableTX(LPUART_Type *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CSR, LPUART_CSR_TXEN_Msk); +} + +/** + * @brief Enable LPUART Receive Event Interrupt + * @rmtoll IER RXEV_IE FL_LPUART_EnableIT_RXWakeup + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_EnableIT_RXWakeup(LPUART_Type *LPUARTx) +{ + SET_BIT(LPUARTx->IER, LPUART_IER_RXEV_IE_Msk); +} + +/** + * @brief Get LPUART Receive Event Interrupt Enable Status + * @rmtoll IER RXEV_IE FL_LPUART_IsEnabledIT_RXWakeup + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsEnabledIT_RXWakeup(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->IER, LPUART_IER_RXEV_IE_Msk) == LPUART_IER_RXEV_IE_Msk); +} + +/** + * @brief Disable LPUART Receive Event Interrupt + * @rmtoll IER RXEV_IE FL_LPUART_DisableIT_RXWakeup + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_DisableIT_RXWakeup(LPUART_Type *LPUARTx) +{ + CLEAR_BIT(LPUARTx->IER, LPUART_IER_RXEV_IE_Msk); +} + +/** + * @brief Enable LPUART Receive Error Interrupt + * @rmtoll IER RXERR_IE FL_LPUART_EnableIT_RXError + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_EnableIT_RXError(LPUART_Type *LPUARTx) +{ + SET_BIT(LPUARTx->IER, LPUART_IER_RXERR_IE_Msk); +} + +/** + * @brief Get LPUART Receive Error Interrupt Enable Status + * @rmtoll IER RXERR_IE FL_LPUART_IsEnabledIT_RXError + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsEnabledIT_RXError(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->IER, LPUART_IER_RXERR_IE_Msk) == LPUART_IER_RXERR_IE_Msk); +} + +/** + * @brief Disable LPUART Receive Error Interrupt + * @rmtoll IER RXERR_IE FL_LPUART_DisableIT_RXError + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_DisableIT_RXError(LPUART_Type *LPUARTx) +{ + CLEAR_BIT(LPUARTx->IER, LPUART_IER_RXERR_IE_Msk); +} + +/** + * @brief Enable LPUART Receive Buffer Full Interrupt + * @rmtoll IER RXBF_IE FL_LPUART_EnableIT_RXBuffFull + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_EnableIT_RXBuffFull(LPUART_Type *LPUARTx) +{ + SET_BIT(LPUARTx->IER, LPUART_IER_RXBF_IE_Msk); +} + +/** + * @brief Get LPUART Receive Buffer Full Interrupt Enable Status + * @rmtoll IER RXBF_IE FL_LPUART_IsEnabledIT_RXBuffFull + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsEnabledIT_RXBuffFull(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->IER, LPUART_IER_RXBF_IE_Msk) == LPUART_IER_RXBF_IE_Msk); +} + +/** + * @brief Disable LPUART Receive Buffer Full Interrupt + * @rmtoll IER RXBF_IE FL_LPUART_DisableIT_RXBufFull + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_DisableIT_RXBufFull(LPUART_Type *LPUARTx) +{ + CLEAR_BIT(LPUARTx->IER, LPUART_IER_RXBF_IE_Msk); +} + +/** + * @brief Enable LPUART Transmit Buffer Empty Interrupt + * @rmtoll IER TXBE_IE FL_LPUART_EnableIT_TXBuffEmpty + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_EnableIT_TXBuffEmpty(LPUART_Type *LPUARTx) +{ + SET_BIT(LPUARTx->IER, LPUART_IER_TXBE_IE_Msk); +} + +/** + * @brief Get LPUART Transmit Buffer Empty Interrupt Enable Status + * @rmtoll IER TXBE_IE FL_LPUART_IsEnabledIT_TXBuffEmpty + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsEnabledIT_TXBuffEmpty(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->IER, LPUART_IER_TXBE_IE_Msk) == LPUART_IER_TXBE_IE_Msk); +} + +/** + * @brief Disable LPUART Transmit Buffer Empty Interrupt + * @rmtoll IER TXBE_IE FL_LPUART_DisableIT_TXBuffEmpty + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_DisableIT_TXBuffEmpty(LPUART_Type *LPUARTx) +{ + CLEAR_BIT(LPUARTx->IER, LPUART_IER_TXBE_IE_Msk); +} + +/** + * @brief Enable LPUART Transmit Shift Register Interrupt + * @rmtoll IER TXSE_IE FL_LPUART_EnableIT_TXShiftBuffEmpty + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_EnableIT_TXShiftBuffEmpty(LPUART_Type *LPUARTx) +{ + SET_BIT(LPUARTx->IER, LPUART_IER_TXSE_IE_Msk); +} + +/** + * @brief Get LPUART Transmit Shift Register Interrupt Enable Status + * @rmtoll IER TXSE_IE FL_LPUART_IsEnabledIT_TXShiftBuffEmpty + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsEnabledIT_TXShiftBuffEmpty(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->IER, LPUART_IER_TXSE_IE_Msk) == LPUART_IER_TXSE_IE_Msk); +} + +/** + * @brief Disable LPUART Transmit Shift Register Interrupt + * @rmtoll IER TXSE_IE FL_LPUART_DisableIT_TXShiftBuffEmpty + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_DisableIT_TXShiftBuffEmpty(LPUART_Type *LPUARTx) +{ + CLEAR_BIT(LPUARTx->IER, LPUART_IER_TXSE_IE_Msk); +} + +/** + * @brief Get LPUART Receive Event Interrupt Flag + * @rmtoll ISR RXEVF FL_LPUART_IsActiveFlag_RXWakeup + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsActiveFlag_RXWakeup(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->ISR, LPUART_ISR_RXEVF_Msk) == (LPUART_ISR_RXEVF_Msk)); +} + +/** + * @brief Clear LPUART Receive Event Interrupt Flag + * @rmtoll ISR RXEVF FL_LPUART_ClearFlag_RXWakeup + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_ClearFlag_RXWakeup(LPUART_Type *LPUARTx) +{ + WRITE_REG(LPUARTx->ISR, LPUART_ISR_RXEVF_Msk); +} + +/** + * @brief Get LPUART Transmit Overflow Error Flag + * @rmtoll ISR TXOV FL_LPUART_IsActiveFlag_TXBuffOverflow + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsActiveFlag_TXBuffOverflow(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->ISR, LPUART_ISR_TXOV_Msk) == (LPUART_ISR_TXOV_Msk)); +} + +/** + * @brief Clear LPUART Transmit Overflow Error Flag + * @rmtoll ISR TXOV FL_LPUART_ClearFlag_TXBuffOverflow + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_ClearFlag_TXBuffOverflow(LPUART_Type *LPUARTx) +{ + WRITE_REG(LPUARTx->ISR, LPUART_ISR_TXOV_Msk); +} + +/** + * @brief Get LPUART Parity Error Flag + * @rmtoll ISR PERR FL_LPUART_IsActiveFlag_ParityError + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsActiveFlag_ParityError(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->ISR, LPUART_ISR_PERR_Msk) == (LPUART_ISR_PERR_Msk)); +} + +/** + * @brief Clear LPUART Parity Error Flag + * @rmtoll ISR PERR FL_LPUART_ClearFlag_ParityError + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_ClearFlag_ParityError(LPUART_Type *LPUARTx) +{ + WRITE_REG(LPUARTx->ISR, LPUART_ISR_PERR_Msk); +} + +/** + * @brief Get LPUART Frame Error Flag + * @rmtoll ISR FERR FL_LPUART_IsActiveFlag_FrameError + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsActiveFlag_FrameError(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->ISR, LPUART_ISR_FERR_Msk) == (LPUART_ISR_FERR_Msk)); +} + +/** + * @brief Clear LPUART Frame Error Flag + * @rmtoll ISR FERR FL_LPUART_ClearFlag_FrameError + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_ClearFlag_FrameError(LPUART_Type *LPUARTx) +{ + WRITE_REG(LPUARTx->ISR, LPUART_ISR_FERR_Msk); +} + +/** + * @brief Get LPUART Receive Buffer Overflow Error Flag + * @rmtoll ISR OERR FL_LPUART_IsActiveFlag_RXBuffOverflow + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsActiveFlag_RXBuffOverflow(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->ISR, LPUART_ISR_OERR_Msk) == (LPUART_ISR_OERR_Msk)); +} + +/** + * @brief Clear LPUART Receive Buffer Overflow Error Flag + * @rmtoll ISR OERR FL_LPUART_ClearFlag_RXBuffOverflow + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_ClearFlag_RXBuffOverflow(LPUART_Type *LPUARTx) +{ + WRITE_REG(LPUARTx->ISR, LPUART_ISR_OERR_Msk); +} + +/** + * @brief Get LPUART Receive Buffer Full Flag + * @rmtoll ISR RXBF FL_LPUART_IsActiveFlag_RXBuffFull + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsActiveFlag_RXBuffFull(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->ISR, LPUART_ISR_RXBF_Msk) == (LPUART_ISR_RXBF_Msk)); +} + +/** + * @brief Clear LPUART Receive Buffer Full Flag + * @rmtoll ISR RXBF FL_LPUART_ClearFlag_RXBuffFull + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_ClearFlag_RXBuffFull(LPUART_Type *LPUARTx) +{ + WRITE_REG(LPUARTx->ISR, LPUART_ISR_RXBF_Msk); +} + +/** + * @brief Get LPUART Transmit Buffer Empty Flag + * @rmtoll ISR TXBE FL_LPUART_IsActiveFlag_TXBuffEmpty + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsActiveFlag_TXBuffEmpty(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->ISR, LPUART_ISR_TXBE_Msk) == (LPUART_ISR_TXBE_Msk)); +} + +/** + * @brief Clear LPUART Transmit Buffer Empty Flag + * @rmtoll ISR TXBE FL_LPUART_ClearFlag_TXBuffEmpty + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_ClearFlag_TXBuffEmpty(LPUART_Type *LPUARTx) +{ + WRITE_REG(LPUARTx->ISR, LPUART_ISR_TXBE_Msk); +} + +/** + * @brief Get LPUART Transmit Shift register Empty Flag + * @rmtoll ISR TXSE FL_LPUART_IsActiveFlag_TXShiftBuffEmpty + * @param LPUARTx LPUART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_LPUART_IsActiveFlag_TXShiftBuffEmpty(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->ISR, LPUART_ISR_TXSE_Msk) == (LPUART_ISR_TXSE_Msk)); +} + +/** + * @brief Clear LPUART Transmit Shift register Empty Flag + * @rmtoll ISR TXSE FL_LPUART_ClearFlag_TXShiftBuffEmpty + * @param LPUARTx LPUART instance + * @retval None + */ +__STATIC_INLINE void FL_LPUART_ClearFlag_TXShiftBuffEmpty(LPUART_Type *LPUARTx) +{ + WRITE_REG(LPUARTx->ISR, LPUART_ISR_TXSE_Msk); +} + +/** + * @brief Set LPUART BaudRate + * @rmtoll BMR BAUD FL_LPUART_SetBaudRate + * @param LPUARTx LPUART instance + * @param baudRate This parameter can be one of the following values: + * @arg @ref FL_LPUART_BAUDRATE_9600 + * @arg @ref FL_LPUART_BAUDRATE_4800 + * @arg @ref FL_LPUART_BAUDRATE_2400 + * @arg @ref FL_LPUART_BAUDRATE_1200 + * @arg @ref FL_LPUART_BAUDRATE_600 + * @arg @ref FL_LPUART_BAUDRATE_300 + * @retval None + */ +__STATIC_INLINE void FL_LPUART_SetBaudRate(LPUART_Type *LPUARTx, uint32_t baudRate) +{ + MODIFY_REG(LPUARTx->BMR, LPUART_BMR_BAUD_Msk, baudRate); +} + +/** + * @brief Get LPUART BaudRate + * @rmtoll BMR BAUD FL_LPUART_GetBaudRate + * @param LPUARTx LPUART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_LPUART_BAUDRATE_9600 + * @arg @ref FL_LPUART_BAUDRATE_4800 + * @arg @ref FL_LPUART_BAUDRATE_2400 + * @arg @ref FL_LPUART_BAUDRATE_1200 + * @arg @ref FL_LPUART_BAUDRATE_600 + * @arg @ref FL_LPUART_BAUDRATE_300 + */ +__STATIC_INLINE uint32_t FL_LPUART_GetBaudRate(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->BMR, LPUART_BMR_BAUD_Msk)); +} + +/** + * @brief LPUART Receive 1 byte of data + * @rmtoll RXBUF FL_LPUART_ReadRXBuff + * @param LPUARTx LPUART instance + * @retval The LPUart received data + */ +__STATIC_INLINE uint32_t FL_LPUART_ReadRXBuff(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->RXBUF, 0x1ffU)); +} + +/** + * @brief LPUART Transmit 1 byte of data + * @rmtoll TXBUF FL_LPUART_WriteTXBuff + * @param LPUARTx LPUART instance + * @param data The data need to transmit through the LPUart + * @retval None + */ +__STATIC_INLINE void FL_LPUART_WriteTXBuff(LPUART_Type *LPUARTx, uint8_t data) +{ + MODIFY_REG(LPUARTx->TXBUF, 0x1ffU, data); +} + +/** + * @brief Set LPUART Matched Data + * @rmtoll DMR FL_LPUART_WriteMatchData + * @param LPUARTx LPUART instance + * @param data The value of match under SLEEP MODE + * @retval None + */ +__STATIC_INLINE void FL_LPUART_WriteMatchData(LPUART_Type *LPUARTx, uint8_t data) +{ + MODIFY_REG(LPUARTx->DMR, 0x1ffU, data); +} + +/** + * @brief Get LPUART Matched Data + * @rmtoll DMR FL_LPUART_ReadMatchData + * @param LPUARTx LPUART instance + * @retval The value of match data under SLEEP MODE + */ +__STATIC_INLINE uint32_t FL_LPUART_ReadMatchData(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->DMR, 0x1ffU)); +} + +/** + * @brief Set LPUART Bit Modulation + * @rmtoll BMR MCTL FL_LPUART_WriteBitModulation + * @param LPUARTx LPUART instance + * @param bitModulation The value of Bit Modulation Control + * @retval None + */ +__STATIC_INLINE void FL_LPUART_WriteBitModulation(LPUART_Type *LPUARTx, uint32_t bitModulation) +{ + MODIFY_REG(LPUARTx->BMR, (0xfffU << 16U), (bitModulation << 16U)); +} + +/** + * @brief Get LPUART Bit Modulation + * @rmtoll BMR MCTL FL_LPUART_ReadBitModulation + * @param LPUARTx LPUART instance + * @retval The value of Bit Modulation Control + */ +__STATIC_INLINE uint32_t FL_LPUART_ReadBitModulation(LPUART_Type *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->BMR, (0xfffU << 16U)) >> 16U); +} + +/** + * @} + */ + +/** @defgroup LPUART_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_LPUART_DeInit(LPUART_Type *LPUARTx); +void FL_LPUART_StructInit(FL_LPUART_InitTypeDef *initStruct); +FL_ErrorStatus FL_LPUART_Init(LPUART_Type *LPUARTx, FL_LPUART_InitTypeDef *initStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_LPUART_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-22*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_opa.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_opa.h new file mode 100644 index 0000000000..413d8d3421 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_opa.h @@ -0,0 +1,785 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_opa.h + * @author FMSH Application Team + * @brief Head file of OPA FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_OPA_H +#define __FM33LC0XX_FL_OPA_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup OPA OPA + * @brief OPA FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup OPA_FL_ES_INIT OPA Exported Init structures + * @{ + */ + +/** + * @brief OPA Init Sturcture definition + */ +typedef struct +{ + /** 正向输入选择 */ + uint32_t INP; + + /** 反向输入选择*/ + uint32_t INN; + + /** OPA 工作模式*/ + uint32_t mode; + + /** 数字滤波器使能 */ + uint32_t digitalFilter; + + /** PGA反向输入到选择由Pin输入 */ + uint32_t negtiveToPin; + + /** PGA模式下的放大倍数*/ + uint32_t gain; + + /** 低功耗模式使能 */ + uint32_t lowPowermode; + +} FL_OPA_InitTypeDef; + +/** + * @} + */ + +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup OPA_FL_Exported_Constants OPA Exported Constants + * @{ + */ + +#define OPA_CR_BUFFEN_Pos (31U) +#define OPA_CR_BUFFEN_Msk (0x1U << OPA_CR_BUFFEN_Pos) +#define OPA_CR_BUFFEN OPA_CR_BUFFEN_Msk + +#define OPA_CR_BUFBYP_Pos (30U) +#define OPA_CR_BUFBYP_Msk (0x1U << OPA_CR_BUFBYP_Pos) +#define OPA_CR_BUFBYP OPA_CR_BUFBYP_Msk + +#define OPA_CR_VNSEL_Pos (9U) +#define OPA_CR_VNSEL_Msk (0x7U << OPA_CR_VNSEL_Pos) +#define OPA_CR_VNSEL OPA_CR_VNSEL_Msk + +#define OPA_CR_VPSEL_Pos (8U) +#define OPA_CR_VPSEL_Msk (0x1U << OPA_CR_VPSEL_Pos) +#define OPA_CR_VPSEL OPA_CR_VPSEL_Msk + +#define OPA_CR_DF_Pos (7U) +#define OPA_CR_DF_Msk (0x1U << OPA_CR_DF_Pos) +#define OPA_CR_DF OPA_CR_DF_Msk + +#define OPA_CR_VN_EXC_Pos (6U) +#define OPA_CR_VN_EXC_Msk (0x1U << OPA_CR_VN_EXC_Pos) +#define OPA_CR_VN_EXC OPA_CR_VN_EXC_Msk + +#define OPA_CR_PGA_GAIN_Pos (4U) +#define OPA_CR_PGA_GAIN_Msk (0x3U << OPA_CR_PGA_GAIN_Pos) +#define OPA_CR_PGA_GAIN OPA_CR_PGA_GAIN_Msk + +#define OPA_CR_MOD_Pos (2U) +#define OPA_CR_MOD_Msk (0x3U << OPA_CR_MOD_Pos) +#define OPA_CR_MOD OPA_CR_MOD_Msk + +#define OPA_CR_LPM_Pos (1U) +#define OPA_CR_LPM_Msk (0x1U << OPA_CR_LPM_Pos) +#define OPA_CR_LPM OPA_CR_LPM_Msk + +#define OPA_CR_EN_Pos (0U) +#define OPA_CR_EN_Msk (0x1U << OPA_CR_EN_Pos) +#define OPA_CR_EN OPA_CR_EN_Msk + +#define OPA_CALR_NCAL_EN_Pos (31U) +#define OPA_CALR_NCAL_EN_Msk (0x1U << OPA_CALR_NCAL_EN_Pos) +#define OPA_CALR_NCAL_EN OPA_CALR_NCAL_EN_Msk + +#define OPA_CALR_NCAL_Pos (16U) +#define OPA_CALR_NCAL_Msk (0x1fU << OPA_CALR_NCAL_Pos) +#define OPA_CALR_NCAL OPA_CALR_NCAL_Msk + +#define OPA_CALR_PCAL_EN_Pos (15U) +#define OPA_CALR_PCAL_EN_Msk (0x1U << OPA_CALR_PCAL_EN_Pos) +#define OPA_CALR_PCAL_EN OPA_CALR_PCAL_EN_Msk + +#define OPA_CALR_PCAL_Pos (0U) +#define OPA_CALR_PCAL_Msk (0x1fU << OPA_CALR_PCAL_Pos) +#define OPA_CALR_PCAL OPA_CALR_PCAL_Msk + +#define OPA_IER_FIE_Pos (1U) +#define OPA_IER_FIE_Msk (0x1U << OPA_IER_FIE_Pos) +#define OPA_IER_FIE OPA_IER_FIE_Msk + +#define OPA_IER_RIE_Pos (0U) +#define OPA_IER_RIE_Msk (0x1U << OPA_IER_RIE_Pos) +#define OPA_IER_RIE OPA_IER_RIE_Msk + +#define OPA_ISR_OUT_Pos (15U) +#define OPA_ISR_OUT_Msk (0x1U << OPA_ISR_OUT_Pos) +#define OPA_ISR_OUT OPA_ISR_OUT_Msk + +#define OPA_ISR_FIF_Pos (1U) +#define OPA_ISR_FIF_Msk (0x1U << OPA_ISR_FIF_Pos) +#define OPA_ISR_FIF OPA_ISR_FIF_Msk + +#define OPA_ISR_RIF_Pos (0U) +#define OPA_ISR_RIF_Msk (0x1U << OPA_ISR_RIF_Pos) +#define OPA_ISR_RIF OPA_ISR_RIF_Msk + + + + + + +#define FL_OPA_INN_SOURCE_INN1 (0x0U << OPA_CR_VNSEL_Pos) +#define FL_OPA_INN_SOURCE_INN2 (0x1U << OPA_CR_VNSEL_Pos) +#define FL_OPA_INN_SOURCE_VREF (0x2U << OPA_CR_VNSEL_Pos) +#define FL_OPA_INN_SOURCE_THREE_QUARTERS_VREF (0x3U << OPA_CR_VNSEL_Pos) +#define FL_OPA_INN_SOURCE_HALF_VREF (0x4U << OPA_CR_VNSEL_Pos) +#define FL_OPA_INN_SOURCE_ONE_QUARTER_VREF (0x5U << OPA_CR_VNSEL_Pos) +#define FL_OPA_INN_SOURCE_ONE_EIGHTH_VREF (0x6U << OPA_CR_VNSEL_Pos) + + +#define FL_OPA_INP_SOURCE_INP1 (0x0U << OPA_CR_VPSEL_Pos) +#define FL_OPA_INP_SOURCE_INP2 (0x1U << OPA_CR_VPSEL_Pos) + + +#define FL_OPA_GAIN_X2 (0x0U << OPA_CR_PGA_GAIN_Pos) +#define FL_OPA_GAIN_X4 (0x1U << OPA_CR_PGA_GAIN_Pos) +#define FL_OPA_GAIN_X8 (0x2U << OPA_CR_PGA_GAIN_Pos) +#define FL_OPA_GAIN_X16 (0x3U << OPA_CR_PGA_GAIN_Pos) + + +#define FL_OPA_MODE_STANDALONE (0x0U << OPA_CR_MOD_Pos) +#define FL_OPA_MODE_COMPARATOR (0x1U << OPA_CR_MOD_Pos) +#define FL_OPA_MODE_PGA (0x2U << OPA_CR_MOD_Pos) +#define FL_OPA_MODE_BUFFER (0x3U << OPA_CR_MOD_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup OPA_FL_Exported_Functions OPA Exported Functions + * @{ + */ + +/** + * @brief Enable VREF Buffer + * @rmtoll CR BUFFEN FL_OPA_EnableVrefBuffer + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_EnableVrefBuffer(OPA_Type *OPAx) +{ + CLEAR_BIT(OPAx->CR, OPA_CR_BUFFEN_Msk); +} + +/** + * @brief Get VREF Buffer Enable Status + * @rmtoll CR BUFFEN FL_OPA_IsEnabledVrefBuffer + * @param OPAx OPA instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_OPA_IsEnabledVrefBuffer(OPA_Type *OPAx) +{ + return (uint32_t)!(READ_BIT(OPAx->CR, OPA_CR_BUFFEN_Msk) == OPA_CR_BUFFEN_Msk); +} + +/** + * @brief Disable VREF Buffer + * @rmtoll CR BUFFEN FL_OPA_DisableVrefBuffer + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_DisableVrefBuffer(OPA_Type *OPAx) +{ + CLEAR_BIT(OPAx->CR, OPA_CR_BUFFEN_Msk); +} + +/** + * @brief Enable VREF Buffer Bypass + * @rmtoll CR BUFBYP FL_OPA_EnableBypassVrefBuffer + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_EnableBypassVrefBuffer(OPA_Type *OPAx) +{ + SET_BIT(OPAx->CR, OPA_CR_BUFBYP_Msk); +} + +/** + * @brief Get VREF Buffer Bypass Enable Status + * @rmtoll CR BUFBYP FL_OPA_IsEnabledBypassVrefBuffer + * @param OPAx OPA instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_OPA_IsEnabledBypassVrefBuffer(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->CR, OPA_CR_BUFBYP_Msk) == OPA_CR_BUFBYP_Msk); +} + +/** + * @brief Disable VREF Buffer Bypass + * @rmtoll CR BUFBYP FL_OPA_DisableBypassVrefBuffer + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_DisableBypassVrefBuffer(OPA_Type *OPAx) +{ + CLEAR_BIT(OPAx->CR, OPA_CR_BUFBYP_Msk); +} + +/** + * @brief Set OPA Negative Input Channel + * @rmtoll CR VNSEL FL_OPA_SetINNSource + * @param OPAx OPA instance + * @param source This parameter can be one of the following values: + * @arg @ref FL_OPA_INN_SOURCE_INN1 + * @arg @ref FL_OPA_INN_SOURCE_INN2 + * @arg @ref FL_OPA_INN_SOURCE_VREF + * @arg @ref FL_OPA_INN_SOURCE_THREE_QUARTERS_VREF + * @arg @ref FL_OPA_INN_SOURCE_HALF_VREF + * @arg @ref FL_OPA_INN_SOURCE_ONE_QUARTER_VREF + * @arg @ref FL_OPA_INN_SOURCE_ONE_EIGHTH_VREF + * @retval None + */ +__STATIC_INLINE void FL_OPA_SetINNSource(OPA_Type *OPAx, uint32_t source) +{ + MODIFY_REG(OPAx->CR, OPA_CR_VNSEL_Msk, source); +} + +/** + * @brief Get OPA Negative Input Channel Setting + * @rmtoll CR VNSEL FL_OPA_GetINNSource + * @param OPAx OPA instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_OPA_INN_SOURCE_INN1 + * @arg @ref FL_OPA_INN_SOURCE_INN2 + * @arg @ref FL_OPA_INN_SOURCE_VREF + * @arg @ref FL_OPA_INN_SOURCE_THREE_QUARTERS_VREF + * @arg @ref FL_OPA_INN_SOURCE_HALF_VREF + * @arg @ref FL_OPA_INN_SOURCE_ONE_QUARTER_VREF + * @arg @ref FL_OPA_INN_SOURCE_ONE_EIGHTH_VREF + */ +__STATIC_INLINE uint32_t FL_OPA_GetINNSource(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->CR, OPA_CR_VNSEL_Msk)); +} + +/** + * @brief Set OPA Positive Input Channel + * @rmtoll CR VPSEL FL_OPA_SetINPSource + * @param OPAx OPA instance + * @param source This parameter can be one of the following values: + * @arg @ref FL_OPA_INP_SOURCE_INP1 + * @arg @ref FL_OPA_INP_SOURCE_INP2 + * @retval None + */ +__STATIC_INLINE void FL_OPA_SetINPSource(OPA_Type *OPAx, uint32_t source) +{ + MODIFY_REG(OPAx->CR, OPA_CR_VPSEL_Msk, source); +} + +/** + * @brief Get OPA Positive Input Channel Setting + * @rmtoll CR VPSEL FL_OPA_GetINPSource + * @param OPAx OPA instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_OPA_INP_SOURCE_INP1 + * @arg @ref FL_OPA_INP_SOURCE_INP2 + */ +__STATIC_INLINE uint32_t FL_OPA_GetINPSource(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->CR, OPA_CR_VPSEL_Msk)); +} + +/** + * @brief Enable OPA Comparator Mode Output Digital Filter + * @rmtoll CR DF FL_OPA_EnableCOMPModeDigitalFilter + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_EnableCOMPModeDigitalFilter(OPA_Type *OPAx) +{ + SET_BIT(OPAx->CR, OPA_CR_DF_Msk); +} + +/** + * @brief Get OPA Comparator Mode Output Digital Filter Enable Status + * @rmtoll CR DF FL_OPA_IsEnabledCOMPModeDigitalFilter + * @param OPAx OPA instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_OPA_IsEnabledCOMPModeDigitalFilter(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->CR, OPA_CR_DF_Msk) == OPA_CR_DF_Msk); +} + +/** + * @brief Disable OPA Comparator Mode Output Digital Filter + * @rmtoll CR DF FL_OPA_DisableCOMPModeDigitalFilter + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_DisableCOMPModeDigitalFilter(OPA_Type *OPAx) +{ + CLEAR_BIT(OPAx->CR, OPA_CR_DF_Msk); +} + +/** + * @brief Enable OPA Negtive Input Connected to GPIO + * @rmtoll CR VN_EXC FL_OPA_PGA_EnableINNConnectToPin + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_PGA_EnableINNConnectToPin(OPA_Type *OPAx) +{ + SET_BIT(OPAx->CR, OPA_CR_VN_EXC_Msk); +} + +/** + * @brief Get OPA Negtive Input Connected to GPIO Enable Status + * @rmtoll CR VN_EXC FL_OPA_PGA_IsEnabledINNConnectToPin + * @param OPAx OPA instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_OPA_PGA_IsEnabledINNConnectToPin(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->CR, OPA_CR_VN_EXC_Msk) == OPA_CR_VN_EXC_Msk); +} + +/** + * @brief Disable OPA Negtive Input Connected to GPIO + * @rmtoll CR VN_EXC FL_OPA_PGA_DisableINNConnectToPin + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_PGA_DisableINNConnectToPin(OPA_Type *OPAx) +{ + CLEAR_BIT(OPAx->CR, OPA_CR_VN_EXC_Msk); +} + +/** + * @brief Set OPA PGA Mode Gain + * @rmtoll CR PGA_GAIN FL_OPA_PGA_SetGain + * @param OPAx OPA instance + * @param value This parameter can be one of the following values: + * @arg @ref FL_OPA_GAIN_X2 + * @arg @ref FL_OPA_GAIN_X4 + * @arg @ref FL_OPA_GAIN_X8 + * @arg @ref FL_OPA_GAIN_X16 + * @retval None + */ +__STATIC_INLINE void FL_OPA_PGA_SetGain(OPA_Type *OPAx, uint32_t value) +{ + MODIFY_REG(OPAx->CR, OPA_CR_PGA_GAIN_Msk, value); +} + +/** + * @brief Get OPA PGA Mode Gain Setting + * @rmtoll CR PGA_GAIN FL_OPA_PGA_GetGain + * @param OPAx OPA instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_OPA_GAIN_X2 + * @arg @ref FL_OPA_GAIN_X4 + * @arg @ref FL_OPA_GAIN_X8 + * @arg @ref FL_OPA_GAIN_X16 + */ +__STATIC_INLINE uint32_t FL_OPA_PGA_GetGain(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->CR, OPA_CR_PGA_GAIN_Msk)); +} + +/** + * @brief Set OPA Mode + * @rmtoll CR MOD FL_OPA_SetMode + * @param OPAx OPA instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_OPA_MODE_STANDALONE + * @arg @ref FL_OPA_MODE_COMPARATOR + * @arg @ref FL_OPA_MODE_PGA + * @arg @ref FL_OPA_MODE_BUFFER + * @retval None + */ +__STATIC_INLINE void FL_OPA_SetMode(OPA_Type *OPAx, uint32_t mode) +{ + MODIFY_REG(OPAx->CR, OPA_CR_MOD_Msk, mode); +} + +/** + * @brief Get OPA Mode Setting + * @rmtoll CR MOD FL_OPA_GetMode + * @param OPAx OPA instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_OPA_MODE_STANDALONE + * @arg @ref FL_OPA_MODE_COMPARATOR + * @arg @ref FL_OPA_MODE_PGA + * @arg @ref FL_OPA_MODE_BUFFER + */ +__STATIC_INLINE uint32_t FL_OPA_GetMode(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->CR, OPA_CR_MOD_Msk)); +} + +/** + * @brief Enable OPA Low Power Mode + * @rmtoll CR LPM FL_OPA_EnableLowPowerMode + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_EnableLowPowerMode(OPA_Type *OPAx) +{ + SET_BIT(OPAx->CR, OPA_CR_LPM_Msk); +} + +/** + * @brief Get OPA Low Power Mode Enable Status + * @rmtoll CR LPM FL_OPA_IsEnabledLowPowerMode + * @param OPAx OPA instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_OPA_IsEnabledLowPowerMode(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->CR, OPA_CR_LPM_Msk) == OPA_CR_LPM_Msk); +} + +/** + * @brief Disable OPA Low Power Mode + * @rmtoll CR LPM FL_OPA_DisableLowPowerMode + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_DisableLowPowerMode(OPA_Type *OPAx) +{ + CLEAR_BIT(OPAx->CR, OPA_CR_LPM_Msk); +} + +/** + * @brief Enable OPA + * @rmtoll CR EN FL_OPA_Enable + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_Enable(OPA_Type *OPAx) +{ + SET_BIT(OPAx->CR, OPA_CR_EN_Msk); +} + +/** + * @brief Get OPA Enable Status + * @rmtoll CR EN FL_OPA_IsEnabled + * @param OPAx OPA instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_OPA_IsEnabled(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->CR, OPA_CR_EN_Msk) == OPA_CR_EN_Msk); +} + +/** + * @brief Disable OPA + * @rmtoll CR EN FL_OPA_Disable + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_Disable(OPA_Type *OPAx) +{ + CLEAR_BIT(OPAx->CR, OPA_CR_EN_Msk); +} + +/** + * @brief Enable OPA Negative Input Calibration + * @rmtoll CALR NCAL_EN FL_OPA_EnableINNTrim + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_EnableINNTrim(OPA_Type *OPAx) +{ + SET_BIT(OPAx->CALR, OPA_CALR_NCAL_EN_Msk); +} + +/** + * @brief Get OPA Negative Input Calibration Enable Status + * @rmtoll CALR NCAL_EN FL_OPA_IsEnabledINNTrim + * @param OPAx OPA instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_OPA_IsEnabledINNTrim(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->CALR, OPA_CALR_NCAL_EN_Msk) == OPA_CALR_NCAL_EN_Msk); +} + +/** + * @brief Disable OPA Negative Input Calibration + * @rmtoll CALR NCAL_EN FL_OPA_DisableINNTrim + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_DisableINNTrim(OPA_Type *OPAx) +{ + CLEAR_BIT(OPAx->CALR, OPA_CALR_NCAL_EN_Msk); +} + +/** + * @brief Set OPA Negative Trim Value + * @rmtoll CALR NCAL FL_OPA_WriteNegativeTrim + * @param OPAx OPA instance + * @param value + * @retval None + */ +__STATIC_INLINE void FL_OPA_WriteNegativeTrim(OPA_Type *OPAx, uint32_t value) +{ + MODIFY_REG(OPAx->CALR, (0x1fU << 16U), (value << 16U)); +} + +/** + * @brief Get OPA Negative Trim Value + * @rmtoll CALR NCAL FL_OPA_ReadNegativeTrim + * @param OPAx OPA instance + * @retval + */ +__STATIC_INLINE uint32_t FL_OPA_ReadNegativeTrim(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->CALR, (0x1fU << 16U)) >> 16U); +} + +/** + * @brief Enable OPA Positive Input Calibration + * @rmtoll CALR PCAL_EN FL_OPA_EnableINPTrim + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_EnableINPTrim(OPA_Type *OPAx) +{ + SET_BIT(OPAx->CALR, OPA_CALR_PCAL_EN_Msk); +} + +/** + * @brief Get OPA Positive Input Calibration Enable Status + * @rmtoll CALR PCAL_EN FL_OPA_IsEnabledINPTrim + * @param OPAx OPA instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_OPA_IsEnabledINPTrim(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->CALR, OPA_CALR_PCAL_EN_Msk) == OPA_CALR_PCAL_EN_Msk); +} + +/** + * @brief Disable OPA Positive Input Calibration + * @rmtoll CALR PCAL_EN FL_OPA_DisableINPTrim + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_DisableINPTrim(OPA_Type *OPAx) +{ + CLEAR_BIT(OPAx->CALR, OPA_CALR_PCAL_EN_Msk); +} + +/** + * @brief Set OPA Positive Trim Value + * @rmtoll CALR PCAL FL_OPA_WritePositiveTrim + * @param OPAx OPA instance + * @param value + * @retval None + */ +__STATIC_INLINE void FL_OPA_WritePositiveTrim(OPA_Type *OPAx, uint32_t value) +{ + MODIFY_REG(OPAx->CALR, (0x1fU << 0U), (value << 0U)); +} + +/** + * @brief Get OPA Positive Trim Value + * @rmtoll CALR PCAL FL_OPA_ReadPositiveTrim + * @param OPAx OPA instance + * @retval + */ +__STATIC_INLINE uint32_t FL_OPA_ReadPositiveTrim(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->CALR, (0x1fU << 0U)) >> 0U); +} + +/** + * @brief Enable OPA Comparator Mode Fall Interrupt + * @rmtoll IER FIE FL_OPA_EnableIT_FallingEdge + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_EnableIT_FallingEdge(OPA_Type *OPAx) +{ + SET_BIT(OPAx->IER, OPA_IER_FIE_Msk); +} + +/** + * @brief Get OPA Comparator Mode Fall Interrupt Enable Status + * @rmtoll IER FIE FL_OPA_IsEnabledIT_FallingEdge + * @param OPAx OPA instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_OPA_IsEnabledIT_FallingEdge(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->IER, OPA_IER_FIE_Msk) == OPA_IER_FIE_Msk); +} + +/** + * @brief Disable OPA Comparator Mode Fall Interrupt + * @rmtoll IER FIE FL_OPA_DisableIT_FallingEdge + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_DisableIT_FallingEdge(OPA_Type *OPAx) +{ + CLEAR_BIT(OPAx->IER, OPA_IER_FIE_Msk); +} + +/** + * @brief Enable OPA Comparator Mode Rise Interrupt + * @rmtoll IER RIE FL_OPA_EnableIT_RisingEdge + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_EnableIT_RisingEdge(OPA_Type *OPAx) +{ + SET_BIT(OPAx->IER, OPA_IER_RIE_Msk); +} + +/** + * @brief Get OPA Comparator Mode Rise Interrupt Enable Status + * @rmtoll IER RIE FL_OPA_IsEnabledIT_RisingEdge + * @param OPAx OPA instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_OPA_IsEnabledIT_RisingEdge(OPA_Type *OPAx) +{ + return (uint32_t)(READ_BIT(OPAx->IER, OPA_IER_RIE_Msk) == OPA_IER_RIE_Msk); +} + +/** + * @brief Disable OPA Comparator Mode Rise Interrupt + * @rmtoll IER RIE FL_OPA_DisableIT_RisingEdge + * @param OPAx OPA instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_DisableIT_RisingEdge(OPA_Type *OPAx) +{ + CLEAR_BIT(OPAx->IER, OPA_IER_RIE_Msk); +} + +/** + * @brief Get OPA Comparator Mode Output Level + * @rmtoll ISR OUT FL_OPA_ReadCOMPModeOutput + * @param RNGx RNG instance + * @retval + */ +__STATIC_INLINE uint32_t FL_OPA_ReadCOMPModeOutput(OPA_Type *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->ISR, (0x1U << 15U)) >> 15U); +} + +/** + * @brief Get OPA Comparator Mode Fall Interrupt Flag + * @rmtoll ISR FIF FL_OPA_IsActiveFlag_FallingEdge + * @param RNGx RNG instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_OPA_IsActiveFlag_FallingEdge(OPA_Type *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->ISR, OPA_ISR_FIF_Msk) == (OPA_ISR_FIF_Msk)); +} + +/** + * @brief Clear OPA Comparator Mode Fall Interrupt Flag + * @rmtoll ISR FIF FL_OPA_ClearFlag_FallingEdge + * @param RNGx RNG instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_ClearFlag_FallingEdge(OPA_Type *RNGx) +{ + WRITE_REG(RNGx->ISR, OPA_ISR_FIF_Msk); +} + +/** + * @brief Get OPA Comparator Mode Rise Interrupt Flag + * @rmtoll ISR RIF FL_OPA_IsActiveFlag_RisingEdge + * @param RNGx RNG instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_OPA_IsActiveFlag_RisingEdge(OPA_Type *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->ISR, OPA_ISR_RIF_Msk) == (OPA_ISR_RIF_Msk)); +} + +/** + * @brief Clear OPA Comparator Mode Rise Interrupt Flag + * @rmtoll ISR RIF FL_OPA_ClearFlag_RisingEdge + * @param RNGx RNG instance + * @retval None + */ +__STATIC_INLINE void FL_OPA_ClearFlag_RisingEdge(OPA_Type *RNGx) +{ + WRITE_REG(RNGx->ISR, OPA_ISR_RIF_Msk); +} + +/** + * @} + */ + +/** @defgroup OPA_FL_EF_Init Initialization and de-initialization functions + * @{ + */ + +FL_ErrorStatus FL_OPA_DeInit(OPA_Type *OPAx); +void FL_OPA_StructInit(FL_OPA_InitTypeDef *initStruct); +FL_ErrorStatus FL_OPA_Init(OPA_Type *OPAx, FL_OPA_InitTypeDef *initStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_OPA_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_pmu.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_pmu.h new file mode 100644 index 0000000000..f43f8fdf0a --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_pmu.h @@ -0,0 +1,956 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_pmu.h + * @author FMSH Application Team + * @brief Head file of PMU FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_PMU_H +#define __FM33LC0XX_FL_PMU_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup PMU PMU + * @brief PMU FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup PMU_FL_ES_INIT PMU Exported Init structures + * @{ + */ + +/** + * @brief PMU Init Sturcture definition + */ +typedef struct +{ + + /*! 低功耗模式下内核电压降低与否 */ + FL_FunState coreVoltageScaling; + /*! 睡眠模式配置 */ + uint32_t deepSleep; + /*! 唤醒后的系统频率，仅对RCHF */ + uint32_t wakeupFrequency; + /*! 芯片LDO是否进入低功耗 */ + uint32_t LDOLowPowerMode; + /*! 额外唤醒延迟 */ + uint32_t wakeupDelay; +} FL_PMU_SleepInitTypeDef; +/** + * @} + */ + +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup PMU_FL_Exported_Constants PMU Exported Constants + * @{ + */ + +#define PMU_CR_LDO_LPM_Pos (18U) +#define PMU_CR_LDO_LPM_Msk (0x3U << PMU_CR_LDO_LPM_Pos) +#define PMU_CR_LDO_LPM PMU_CR_LDO_LPM_Msk + +#define PMU_CR_LDO15EN_Pos (17U) +#define PMU_CR_LDO15EN_Msk (0x1U << PMU_CR_LDO15EN_Pos) +#define PMU_CR_LDO15EN PMU_CR_LDO15EN_Msk + +#define PMU_CR_LDO15EN_B_Pos (16U) +#define PMU_CR_LDO15EN_B_Msk (0x1U << PMU_CR_LDO15EN_B_Pos) +#define PMU_CR_LDO15EN_B PMU_CR_LDO15EN_B_Msk + +#define PMU_CR_WKFSEL_Pos (10U) +#define PMU_CR_WKFSEL_Msk (0x3U << PMU_CR_WKFSEL_Pos) +#define PMU_CR_WKFSEL PMU_CR_WKFSEL_Msk + +#define PMU_CR_SLPDP_Pos (9U) +#define PMU_CR_SLPDP_Msk (0x1U << PMU_CR_SLPDP_Pos) +#define PMU_CR_SLPDP PMU_CR_SLPDP_Msk + +#define PMU_CR_CVS_Pos (8U) +#define PMU_CR_CVS_Msk (0x1U << PMU_CR_CVS_Pos) +#define PMU_CR_CVS PMU_CR_CVS_Msk + +#define PMU_CR_PMOD_Pos (0U) +#define PMU_CR_PMOD_Msk (0x3U << PMU_CR_PMOD_Pos) +#define PMU_CR_PMOD PMU_CR_PMOD_Msk + +#define PMU_WKTR_STPCLR_Pos (2U) +#define PMU_WKTR_STPCLR_Msk (0x1U << PMU_WKTR_STPCLR_Pos) +#define PMU_WKTR_STPCLR PMU_WKTR_STPCLR_Msk + +#define PMU_WKTR_T1A_Pos (0U) +#define PMU_WKTR_T1A_Msk (0x3U << PMU_WKTR_T1A_Pos) +#define PMU_WKTR_T1A PMU_WKTR_T1A_Msk + +#define PMU_WKFR_ADCWKF_Pos (31U) +#define PMU_WKFR_ADCWKF_Msk (0x1U << PMU_WKFR_ADCWKF_Pos) +#define PMU_WKFR_ADCWKF PMU_WKFR_ADCWKF_Msk + +#define PMU_WKFR_RTCWKF_Pos (28U) +#define PMU_WKFR_RTCWKF_Msk (0x1U << PMU_WKFR_RTCWKF_Pos) +#define PMU_WKFR_RTCWKF PMU_WKFR_RTCWKF_Msk + +#define PMU_WKFR_SVDWKF_Pos (27U) +#define PMU_WKFR_SVDWKF_Msk (0x1U << PMU_WKFR_SVDWKF_Pos) +#define PMU_WKFR_SVDWKF PMU_WKFR_SVDWKF_Msk + +#define PMU_WKFR_LFDETWKF_Pos (26U) +#define PMU_WKFR_LFDETWKF_Msk (0x1U << PMU_WKFR_LFDETWKF_Pos) +#define PMU_WKFR_LFDETWKF PMU_WKFR_LFDETWKF_Msk + +#define PMU_WKFR_VREFWKF_Pos (25U) +#define PMU_WKFR_VREFWKF_Msk (0x1U << PMU_WKFR_VREFWKF_Pos) +#define PMU_WKFR_VREFWKF PMU_WKFR_VREFWKF_Msk + +#define PMU_WKFR_IOWKF_Pos (24U) +#define PMU_WKFR_IOWKF_Msk (0x1U << PMU_WKFR_IOWKF_Pos) +#define PMU_WKFR_IOWKF PMU_WKFR_IOWKF_Msk + +#define PMU_WKFR_IICWKF_Pos (23U) +#define PMU_WKFR_IICWKF_Msk (0x1U << PMU_WKFR_IICWKF_Pos) +#define PMU_WKFR_IICWKF PMU_WKFR_IICWKF_Msk + +#define PMU_WKFR_LPU1WKF_Pos (21U) +#define PMU_WKFR_LPU1WKF_Msk (0x1U << PMU_WKFR_LPU1WKF_Pos) +#define PMU_WKFR_LPU1WKF PMU_WKFR_LPU1WKF_Msk + +#define PMU_WKFR_LPU0WKF_Pos (20U) +#define PMU_WKFR_LPU0WKF_Msk (0x1U << PMU_WKFR_LPU0WKF_Pos) +#define PMU_WKFR_LPU0WKF PMU_WKFR_LPU0WKF_Msk + +#define PMU_WKFR_UART1WKF_Pos (19U) +#define PMU_WKFR_UART1WKF_Msk (0x1U << PMU_WKFR_UART1WKF_Pos) +#define PMU_WKFR_UART1WKF PMU_WKFR_UART1WKF_Msk + +#define PMU_WKFR_UART0WKF_Pos (18U) +#define PMU_WKFR_UART0WKF_Msk (0x1U << PMU_WKFR_UART0WKF_Pos) +#define PMU_WKFR_UART0WKF PMU_WKFR_UART0WKF_Msk + +#define PMU_WKFR_OPA2WKF_Pos (17U) +#define PMU_WKFR_OPA2WKF_Msk (0x1U << PMU_WKFR_OPA2WKF_Pos) +#define PMU_WKFR_OPA2WKF PMU_WKFR_OPA2WKF_Msk + +#define PMU_WKFR_OPA1WKF_Pos (16U) +#define PMU_WKFR_OPA1WKF_Msk (0x1U << PMU_WKFR_OPA1WKF_Pos) +#define PMU_WKFR_OPA1WKF PMU_WKFR_OPA1WKF_Msk + +#define PMU_WKFR_LPTWKF_Pos (10U) +#define PMU_WKFR_LPTWKF_Msk (0x1U << PMU_WKFR_LPTWKF_Pos) +#define PMU_WKFR_LPTWKF PMU_WKFR_LPTWKF_Msk + +#define PMU_WKFR_BSTWKF_Pos (9U) +#define PMU_WKFR_BSTWKF_Msk (0x1U << PMU_WKFR_BSTWKF_Pos) +#define PMU_WKFR_BSTWKF PMU_WKFR_BSTWKF_Msk + +#define PMU_WKFR_DBGWKF_Pos (8U) +#define PMU_WKFR_DBGWKF_Msk (0x1U << PMU_WKFR_DBGWKF_Pos) +#define PMU_WKFR_DBGWKF PMU_WKFR_DBGWKF_Msk + +#define PMU_WKFR_WKPXF_Pos (0U) +#define PMU_WKFR_WKPXF_Msk (0xffU << PMU_WKFR_WKPXF_Pos) +#define PMU_WKFR_WKPXF PMU_WKFR_WKPXF_Msk + +#define PMU_IER_LPRUNEIE_Pos (3U) +#define PMU_IER_LPRUNEIE_Msk (0x1U << PMU_IER_LPRUNEIE_Pos) +#define PMU_IER_LPRUNEIE PMU_IER_LPRUNEIE_Msk + +#define PMU_IER_LPACTEIE_Pos (2U) +#define PMU_IER_LPACTEIE_Msk (0x1U << PMU_IER_LPACTEIE_Pos) +#define PMU_IER_LPACTEIE PMU_IER_LPACTEIE_Msk + +#define PMU_IER_SLPEIE_Pos (1U) +#define PMU_IER_SLPEIE_Msk (0x1U << PMU_IER_SLPEIE_Pos) +#define PMU_IER_SLPEIE PMU_IER_SLPEIE_Msk + +#define PMU_IER_RTCEIE_Pos (0U) +#define PMU_IER_RTCEIE_Msk (0x1U << PMU_IER_RTCEIE_Pos) +#define PMU_IER_RTCEIE PMU_IER_RTCEIE_Msk + +#define PMU_ISR_SLPUNEIE_Pos (3U) +#define PMU_ISR_SLPUNEIE_Msk (0x1U << PMU_ISR_SLPUNEIE_Pos) +#define PMU_ISR_SLPUNEIE PMU_ISR_SLPUNEIE_Msk + +#define PMU_ISR_LPACTEIF_Pos (2U) +#define PMU_ISR_LPACTEIF_Msk (0x1U << PMU_ISR_LPACTEIF_Pos) +#define PMU_ISR_LPACTEIF PMU_ISR_LPACTEIF_Msk + +#define PMU_ISR_SLPEIF_Pos (1U) +#define PMU_ISR_SLPEIF_Msk (0x1U << PMU_ISR_SLPEIF_Pos) +#define PMU_ISR_SLPEIF PMU_ISR_SLPEIF_Msk + +#define PMU_ISR_RTCEIF_Pos (0U) +#define PMU_ISR_RTCEIF_Msk (0x1U << PMU_ISR_RTCEIF_Pos) +#define PMU_ISR_RTCEIF PMU_ISR_RTCEIF_Msk + + + +#define FL_PMU_WKUP0PIN (0x1U << 0U) +#define FL_PMU_WKUP1PIN (0x1U << 1U) +#define FL_PMU_WKUP2PIN (0x1U << 2U) +#define FL_PMU_WKUP3PIN (0x1U << 3U) +#define FL_PMU_WKUP4PIN (0x1U << 4U) +#define FL_PMU_WKUP5PIN (0x1U << 5U) +#define FL_PMU_WKUP6PIN (0x1U << 6U) +#define FL_PMU_WKUP7PIN (0x1U << 7U) + + + +#define FL_PMU_LDO_LPM_DISABLE (0x0U << PMU_CR_LDO_LPM_Pos) +#define FL_PMU_LDO_LPM_ENABLE (0x2U << PMU_CR_LDO_LPM_Pos) + + +#define FL_PMU_RCHF_WAKEUP_FREQ_8MHZ (0x0U << PMU_CR_WKFSEL_Pos) +#define FL_PMU_RCHF_WAKEUP_FREQ_16MHZ (0x1U << PMU_CR_WKFSEL_Pos) +#define FL_PMU_RCHF_WAKEUP_FREQ_24MHZ (0x2U << PMU_CR_WKFSEL_Pos) + + +#define FL_PMU_SLEEP_MODE_DEEP (0x1U << PMU_CR_SLPDP_Pos) +#define FL_PMU_SLEEP_MODE_NORMAL (0x0U << PMU_CR_SLPDP_Pos) + + +#define FL_PMU_POWER_MODE_ACTIVE_OR_LPACTIVE (0x0U << PMU_CR_PMOD_Pos) +#define FL_PMU_POWER_MODE_LPRUN_ONLY (0x1U << PMU_CR_PMOD_Pos) +#define FL_PMU_POWER_MODE_SLEEP_OR_DEEPSLEEP (0x2U << PMU_CR_PMOD_Pos) + +#define FL_PMU_FLASH_STOP_CLEAR_MODE_ASYNCHRONOUS (0x0U << PMU_WKTR_STPCLR_Pos) +#define FL_PMU_FLASH_STOP_CLEAR_MODE_SYNCHRONOUS (0x1U << PMU_WKTR_STPCLR_Pos) + + +#define FL_PMU_WAKEUP_DELAY_0US (0x0U << PMU_WKTR_T1A_Pos) +#define FL_PMU_WAKEUP_DELAY_2US (0x1U << PMU_WKTR_T1A_Pos) +#define FL_PMU_WAKEUP_DELAY_4US (0x2U << PMU_WKTR_T1A_Pos) +#define FL_PMU_WAKEUP_DELAY_8US (0x3U << PMU_WKTR_T1A_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup PMU_FL_Exported_Functions PMU Exported Functions + * @{ + */ + +/** + * @brief Set LDO Low Power Mode + * @rmtoll CR LDO_LPM FL_PMU_SetLDOLowPowerMode + * @param PMUx PMU instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_PMU_LDO_LPM_DISABLE + * @arg @ref FL_PMU_LDO_LPM_ENABLE + * @retval None + */ +__STATIC_INLINE void FL_PMU_SetLDOLowPowerMode(PMU_Type *PMUx, uint32_t mode) +{ + MODIFY_REG(PMUx->CR, PMU_CR_LDO_LPM_Msk, mode); +} + +/** + * @brief Get LDO Low Power Mode Setting + * @rmtoll CR LDO_LPM FL_PMU_GetLDOLowPowerMode + * @param PMUx PMU instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_PMU_LDO_LPM_DISABLE + * @arg @ref FL_PMU_LDO_LPM_ENABLE + */ +__STATIC_INLINE uint32_t FL_PMU_GetLDOLowPowerMode(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->CR, PMU_CR_LDO_LPM_Msk)); +} + +/** + * @brief Get LDO15 Enable Status + * @rmtoll CR LDO15EN FL_PMU_GetLDO15Status + * @param PMUx PMU instance + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_PMU_GetLDO15Status(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->CR, PMU_CR_LDO15EN_Msk)); +} + +/** + * @brief Get LDO15 Inverse check bit + * @rmtoll CR LDO15EN_B FL_PMU_GetLDO15StatusInvert + * @param PMUx PMU instance + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_PMU_GetLDO15StatusInvert(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->CR, PMU_CR_LDO15EN_B_Msk)); +} + +/** + * @brief Set RCHF Frequency After Wakeup + * @rmtoll CR WKFSEL FL_PMU_SetRCHFWakeupFrequency + * @param PMUx PMU instance + * @param freq This parameter can be one of the following values: + * @arg @ref FL_PMU_RCHF_WAKEUP_FREQ_8MHZ + * @arg @ref FL_PMU_RCHF_WAKEUP_FREQ_16MHZ + * @arg @ref FL_PMU_RCHF_WAKEUP_FREQ_24MHZ + * @retval None + */ +__STATIC_INLINE void FL_PMU_SetRCHFWakeupFrequency(PMU_Type *PMUx, uint32_t freq) +{ + MODIFY_REG(PMUx->CR, PMU_CR_WKFSEL_Msk, freq); +} + +/** + * @brief Get RCHF Frequency After Wakeup Setting + * @rmtoll CR WKFSEL FL_PMU_GetRCHFWakeupFrequency + * @param PMUx PMU instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_PMU_RCHF_WAKEUP_FREQ_8MHZ + * @arg @ref FL_PMU_RCHF_WAKEUP_FREQ_16MHZ + * @arg @ref FL_PMU_RCHF_WAKEUP_FREQ_24MHZ + */ +__STATIC_INLINE uint32_t FL_PMU_GetRCHFWakeupFrequency(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->CR, PMU_CR_WKFSEL_Msk)); +} + +/** + * @brief Set Sleep Mode + * @rmtoll CR SLPDP FL_PMU_SetSleepMode + * @param PMUx PMU instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_PMU_SLEEP_MODE_DEEP + * @arg @ref FL_PMU_SLEEP_MODE_NORMAL + * @retval None + */ +__STATIC_INLINE void FL_PMU_SetSleepMode(PMU_Type *PMUx, uint32_t mode) +{ + MODIFY_REG(PMUx->CR, PMU_CR_SLPDP_Msk, mode); +} + +/** + * @brief Get Sleep Mode Setting + * @rmtoll CR SLPDP FL_PMU_GetSleepMode + * @param PMUx PMU instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_PMU_SLEEP_MODE_DEEP + * @arg @ref FL_PMU_SLEEP_MODE_NORMAL + */ +__STATIC_INLINE uint32_t FL_PMU_GetSleepMode(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->CR, PMU_CR_SLPDP_Msk)); +} + +/** + * @brief Enable Core Voltage Scaling Under Low Power Mode + * @rmtoll CR CVS FL_PMU_EnableCoreVoltageScaling + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_EnableCoreVoltageScaling(PMU_Type *PMUx) +{ + SET_BIT(PMUx->CR, PMU_CR_CVS_Msk); +} + +/** + * @brief Get Core Voltage Scaling Under Low Power Mode Enable Status + * @rmtoll CR CVS FL_PMU_IsEnabledCoreVoltageScaling + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsEnabledCoreVoltageScaling(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->CR, PMU_CR_CVS_Msk) == PMU_CR_CVS_Msk); +} + +/** + * @brief Disable Core Voltage Scaling Under Low Power Mode + * @rmtoll CR CVS FL_PMU_DisableCoreVoltageScaling + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_DisableCoreVoltageScaling(PMU_Type *PMUx) +{ + CLEAR_BIT(PMUx->CR, PMU_CR_CVS_Msk); +} + +/** + * @brief Set Low Power Mode + * @rmtoll CR PMOD FL_PMU_SetLowPowerMode + * @param PMUx PMU instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_PMU_POWER_MODE_ACTIVE_OR_LPACTIVE + * @arg @ref FL_PMU_POWER_MODE_LPRUN_ONLY + * @arg @ref FL_PMU_POWER_MODE_SLEEP_OR_DEEPSLEEP + * @retval None + */ +__STATIC_INLINE void FL_PMU_SetLowPowerMode(PMU_Type *PMUx, uint32_t mode) +{ + MODIFY_REG(PMUx->CR, PMU_CR_PMOD_Msk, mode); +} + +/** + * @brief Get Low Power Mode Setting + * @rmtoll CR PMOD FL_PMU_GetLowPowerMode + * @param PMUx PMU instance + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_PMU_GetLowPowerMode(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->CR, PMU_CR_PMOD_Msk)); +} + +/** + * @brief Set Flash Stop Signal Clear Way + * @rmtoll WKTR STPCLR FL_PMU_SetFlashStopSignalClearMode + * @param PMUx PMU instance + * @param config This parameter can be one of the following values: + * @arg @ref FL_PMU_FLASH_STOP_CLEAR_MODE_ASYNCHRONOUS + * @arg @ref FL_PMU_FLASH_STOP_CLEAR_MODE_SYNCHRONOUS + * @retval None + */ +__STATIC_INLINE void FL_PMU_SetFlashStopSignalClearMode(PMU_Type *PMUx, uint32_t config) +{ + MODIFY_REG(PMUx->WKTR, PMU_WKTR_STPCLR_Msk, config); +} + +/** + * @brief Get Flash Stop Signal Clear Way Setting + * @rmtoll WKTR STPCLR FL_PMU_GetFlashStopSignalClearMode + * @param PMUx PMU instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_PMU_FLASH_STOP_CLEAR_MODE_ASYNCHRONOUS + * @arg @ref FL_PMU_FLASH_STOP_CLEAR_MODE_SYNCHRONOUS + */ +__STATIC_INLINE uint32_t FL_PMU_GetFlashStopSignalClearMode(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKTR, PMU_WKTR_STPCLR_Msk)); +} + +/** + * @brief Set Extra Wakeup Delay Under Sleep/DeepSleep Mode + * @rmtoll WKTR T1A FL_PMU_SetWakeupDelay + * @param PMUx PMU instance + * @param time This parameter can be one of the following values: + * @arg @ref FL_PMU_WAKEUP_DELAY_0US + * @arg @ref FL_PMU_WAKEUP_DELAY_2US + * @arg @ref FL_PMU_WAKEUP_DELAY_4US + * @arg @ref FL_PMU_WAKEUP_DELAY_8US + * @retval None + */ +__STATIC_INLINE void FL_PMU_SetWakeupDelay(PMU_Type *PMUx, uint32_t time) +{ + MODIFY_REG(PMUx->WKTR, PMU_WKTR_T1A_Msk, time); +} + +/** + * @brief Get Extra Wakeup Delay Under Sleep/DeepSleep Mode Setting + * @rmtoll WKTR T1A FL_PMU_GetWakeupDelay + * @param PMUx PMU instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_PMU_WAKEUP_DELAY_0US + * @arg @ref FL_PMU_WAKEUP_DELAY_2US + * @arg @ref FL_PMU_WAKEUP_DELAY_4US + * @arg @ref FL_PMU_WAKEUP_DELAY_8US + */ +__STATIC_INLINE uint32_t FL_PMU_GetWakeupDelay(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKTR, PMU_WKTR_T1A_Msk)); +} + +/** + * @brief Get ADC interrupt wakeup flag + * @rmtoll WKFR ADCWKF FL_PMU_IsActiveFlag_WakeupADC + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupADC(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_ADCWKF_Msk) == (PMU_WKFR_ADCWKF_Msk)); +} + +/** + * @brief Get RTC interrupt wakeup flag + * @rmtoll WKFR RTCWKF FL_PMU_IsActiveFlag_WakeupRTC + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupRTC(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_RTCWKF_Msk) == (PMU_WKFR_RTCWKF_Msk)); +} + +/** + * @brief Get SVD interrupt wakeup flag + * @rmtoll WKFR SVDWKF FL_PMU_IsActiveFlag_WakeupSVD + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupSVD(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_SVDWKF_Msk) == (PMU_WKFR_SVDWKF_Msk)); +} + +/** + * @brief Get LFDET interrupt wakeup flag + * @rmtoll WKFR LFDETWKF FL_PMU_IsActiveFlag_WakeupLFDET + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupLFDET(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_LFDETWKF_Msk) == (PMU_WKFR_LFDETWKF_Msk)); +} + +/** + * @brief Get VREF interrupt wakeup flag + * @rmtoll WKFR VREFWKF FL_PMU_IsActiveFlag_WakeupVREF + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupVREF(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_VREFWKF_Msk) == (PMU_WKFR_VREFWKF_Msk)); +} + +/** + * @brief Get IO interrupt wakeup flag + * @rmtoll WKFR IOWKF FL_PMU_IsActiveFlag_WakeupEXTI + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupEXTI(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_IOWKF_Msk) == (PMU_WKFR_IOWKF_Msk)); +} + +/** + * @brief Get I2C interrupt wakeup flag + * @rmtoll WKFR IICWKF FL_PMU_IsActiveFlag_WakeupI2C + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupI2C(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_IICWKF_Msk) == (PMU_WKFR_IICWKF_Msk)); +} + +/** + * @brief Get LPUART1 interrupt wakeup flag + * @rmtoll WKFR LPU1WKF FL_PMU_IsActiveFlag_WakeupLPUART1 + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupLPUART1(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_LPU1WKF_Msk) == (PMU_WKFR_LPU1WKF_Msk)); +} + +/** + * @brief Get LPUART0 interrupt wakeup flag + * @rmtoll WKFR LPU0WKF FL_PMU_IsActiveFlag_WakeupLPUART0 + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupLPUART0(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_LPU0WKF_Msk) == (PMU_WKFR_LPU0WKF_Msk)); +} + +/** + * @brief Get UART1 interrupt wakeup flag + * @rmtoll WKFR UART1WKF FL_PMU_IsActiveFlag_WakeupUART1 + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupUART1(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_UART1WKF_Msk) == (PMU_WKFR_UART1WKF_Msk)); +} + +/** + * @brief Get UART0 interrupt wakeup flag + * @rmtoll WKFR UART0WKF FL_PMU_IsActiveFlag_WakeupUART0 + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupUART0(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_UART0WKF_Msk) == (PMU_WKFR_UART0WKF_Msk)); +} + +/** + * @brief Get COMP2 interrrupt wakeup flag + * @rmtoll WKFR OPA2WKF FL_PMU_IsActiveFlag_WakeupCOMP2 + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupCOMP2(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_OPA2WKF_Msk) == (PMU_WKFR_OPA2WKF_Msk)); +} + +/** + * @brief Get COMP1 interrrupt wakeup flag + * @rmtoll WKFR OPA1WKF FL_PMU_IsActiveFlag_WakeupCOMP1 + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupCOMP1(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_OPA1WKF_Msk) == (PMU_WKFR_OPA1WKF_Msk)); +} + +/** + * @brief Get LPTIM32 interrupt wakeup flag + * @rmtoll WKFR LPTWKF FL_PMU_IsActiveFlag_WakeupLPTIM32 + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupLPTIM32(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_LPTWKF_Msk) == (PMU_WKFR_LPTWKF_Msk)); +} + +/** + * @brief Get BSTIM32 interrupt wakeup flag + * @rmtoll WKFR BSTWKF FL_PMU_IsActiveFlag_WakeupBSTIM32 + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupBSTIM32(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_BSTWKF_Msk) == (PMU_WKFR_BSTWKF_Msk)); +} + +/** + * @brief Get CPU Debugger wakeup flag + * @rmtoll WKFR DBGWKF FL_PMU_IsActiveFlag_WakeupDBG + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupDBG(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, PMU_WKFR_DBGWKF_Msk) == (PMU_WKFR_DBGWKF_Msk)); +} + +/** + * @brief Clear CPU Debugger wakeup flag + * @rmtoll WKFR DBGWKF FL_PMU_ClearFlag_WakeupDBG + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_ClearFlag_WakeupDBG(PMU_Type *PMUx) +{ + WRITE_REG(PMUx->WKFR, PMU_WKFR_DBGWKF_Msk); +} + +/** + * @brief Get pinx wakeup flag + * @rmtoll WKFR WKPXF FL_PMU_IsActiveFlag_WakeupPIN + * @param PMUx PMU instance + * @param Pin This parameter can be one of the following values: + * @arg @ref FL_PMU_WKUP0PIN + * @arg @ref FL_PMU_WKUP1PIN + * @arg @ref FL_PMU_WKUP2PIN + * @arg @ref FL_PMU_WKUP3PIN + * @arg @ref FL_PMU_WKUP4PIN + * @arg @ref FL_PMU_WKUP5PIN + * @arg @ref FL_PMU_WKUP6PIN + * @arg @ref FL_PMU_WKUP7PIN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_WakeupPIN(PMU_Type *PMUx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(PMUx->WKFR, ((Pin & 0xff) << 0x0U)) == ((Pin & 0xff) << 0x0U)); +} + +/** + * @brief Clear pinx wakeup flag + * @rmtoll WKFR WKPXF FL_PMU_ClearFlag_WakeupPIN + * @param PMUx PMU instance + * @param Pin This parameter can be one of the following values: + * @arg @ref FL_PMU_WKUP0PIN + * @arg @ref FL_PMU_WKUP1PIN + * @arg @ref FL_PMU_WKUP2PIN + * @arg @ref FL_PMU_WKUP3PIN + * @arg @ref FL_PMU_WKUP4PIN + * @arg @ref FL_PMU_WKUP5PIN + * @arg @ref FL_PMU_WKUP6PIN + * @arg @ref FL_PMU_WKUP7PIN + * @retval None + */ +__STATIC_INLINE void FL_PMU_ClearFlag_WakeupPIN(PMU_Type *PMUx, uint32_t Pin) +{ + WRITE_REG(PMUx->WKFR, ((Pin & 0xff) << 0x0U)); +} + +/** + * @brief LPREIE error interrupt enable + * @rmtoll IER LPRUNEIE FL_PMU_EnableIT_LPRunError + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_EnableIT_LPRunError(PMU_Type *PMUx) +{ + SET_BIT(PMUx->IER, PMU_IER_LPRUNEIE_Msk); +} + +/** + * @brief Get LPREIE error interrupt enable status + * @rmtoll IER LPRUNEIE FL_PMU_IsEnabledIT_LPRunError + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsEnabledIT_LPRunError(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->IER, PMU_IER_LPRUNEIE_Msk) == PMU_IER_LPRUNEIE_Msk); +} + +/** + * @brief LPREIE error interrupt disable + * @rmtoll IER LPRUNEIE FL_PMU_DisableIT_LPRunError + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_DisableIT_LPRunError(PMU_Type *PMUx) +{ + CLEAR_BIT(PMUx->IER, PMU_IER_LPRUNEIE_Msk); +} + +/** + * @brief LPActive error interrupt enable + * @rmtoll IER LPACTEIE FL_PMU_EnableIT_LPActiveError + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_EnableIT_LPActiveError(PMU_Type *PMUx) +{ + SET_BIT(PMUx->IER, PMU_IER_LPACTEIE_Msk); +} + +/** + * @brief Get LPActive error interrupt enable status + * @rmtoll IER LPACTEIE FL_PMU_IsEnabledIT_LPActiveError + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsEnabledIT_LPActiveError(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->IER, PMU_IER_LPACTEIE_Msk) == PMU_IER_LPACTEIE_Msk); +} + +/** + * @brief LPActive error interrupt disable + * @rmtoll IER LPACTEIE FL_PMU_DisableIT_LPActiveError + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_DisableIT_LPActiveError(PMU_Type *PMUx) +{ + CLEAR_BIT(PMUx->IER, PMU_IER_LPACTEIE_Msk); +} + +/** + * @brief Sleep error interrupt enable + * @rmtoll IER SLPEIE FL_PMU_EnableIT_SleepError + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_EnableIT_SleepError(PMU_Type *PMUx) +{ + SET_BIT(PMUx->IER, PMU_IER_SLPEIE_Msk); +} + +/** + * @brief Get sleep error interrupt enable status + * @rmtoll IER SLPEIE FL_PMU_IsEnabledIT_SleepError + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsEnabledIT_SleepError(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->IER, PMU_IER_SLPEIE_Msk) == PMU_IER_SLPEIE_Msk); +} + +/** + * @brief sleep error interrupt disable + * @rmtoll IER SLPEIE FL_PMU_DisableIT_SleepError + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_DisableIT_SleepError(PMU_Type *PMUx) +{ + CLEAR_BIT(PMUx->IER, PMU_IER_SLPEIE_Msk); +} + +/** + * @brief RTCBKP error interrupt enable + * @rmtoll IER RTCEIE FL_PMU_EnableIT_RTCBKPError + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_EnableIT_RTCBKPError(PMU_Type *PMUx) +{ + SET_BIT(PMUx->IER, PMU_IER_RTCEIE_Msk); +} + +/** + * @brief Get RTCBKP error interrupt enable status + * @rmtoll IER RTCEIE FL_PMU_IsEnabledIT_RTCBKPError + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsEnabledIT_RTCBKPError(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->IER, PMU_IER_RTCEIE_Msk) == PMU_IER_RTCEIE_Msk); +} + +/** + * @brief Sleep error interrupt disable + * @rmtoll IER RTCEIE FL_PMU_DisableIT_RTCBKPError + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_DisableIT_RTCBKPError(PMU_Type *PMUx) +{ + CLEAR_BIT(PMUx->IER, PMU_IER_RTCEIE_Msk); +} + +/** + * @brief Get LPRUN error interrupt flag + * @rmtoll ISR SLPUNEIE FL_PMU_IsActiveFlag_LPRunError + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_LPRunError(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->ISR, PMU_ISR_SLPUNEIE_Msk) == (PMU_ISR_SLPUNEIE_Msk)); +} + +/** + * @brief Clear LPRUN error interrupt flag + * @rmtoll ISR SLPUNEIE FL_PMU_ClearFlag_LPRunError + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_ClearFlag_LPRunError(PMU_Type *PMUx) +{ + WRITE_REG(PMUx->ISR, PMU_ISR_SLPUNEIE_Msk); +} + +/** + * @brief Get LPACTIF error interrupt flag + * @rmtoll ISR LPACTEIF FL_PMU_IsActiveFlag_LPActiveError + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_LPActiveError(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->ISR, PMU_ISR_LPACTEIF_Msk) == (PMU_ISR_LPACTEIF_Msk)); +} + +/** + * @brief Clear LPACTIF error interrupt flag + * @rmtoll ISR LPACTEIF FL_PMU_ClearFlag_LPActiveError + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_ClearFlag_LPActiveError(PMU_Type *PMUx) +{ + WRITE_REG(PMUx->ISR, PMU_ISR_LPACTEIF_Msk); +} + +/** + * @brief Get SLEEP error interrupt flag + * @rmtoll ISR SLPEIF FL_PMU_IsActiveFlag_SleepError + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_SleepError(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->ISR, PMU_ISR_SLPEIF_Msk) == (PMU_ISR_SLPEIF_Msk)); +} + +/** + * @brief Clear SLEEP error interrupt flag + * @rmtoll ISR SLPEIF FL_PMU_ClearFlag_SleepError + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_ClearFlag_SleepError(PMU_Type *PMUx) +{ + WRITE_REG(PMUx->ISR, PMU_ISR_SLPEIF_Msk); +} + +/** + * @brief Get RTCBKP error interrupt flag + * @rmtoll ISR RTCEIF FL_PMU_IsActiveFlag_RTCError + * @param PMUx PMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_PMU_IsActiveFlag_RTCError(PMU_Type *PMUx) +{ + return (uint32_t)(READ_BIT(PMUx->ISR, PMU_ISR_RTCEIF_Msk) == (PMU_ISR_RTCEIF_Msk)); +} + +/** + * @brief Clear RTCBKP error interrupt flag + * @rmtoll ISR RTCEIF FL_PMU_ClearFlag_RTCError + * @param PMUx PMU instance + * @retval None + */ +__STATIC_INLINE void FL_PMU_ClearFlag_RTCError(PMU_Type *PMUx) +{ + WRITE_REG(PMUx->ISR, PMU_ISR_RTCEIF_Msk); +} + +/** + * @} + */ + +/** @defgroup PMU_FL_EF_Init Initialization and de-initialization functions + * @{ + */ + +FL_ErrorStatus FL_PMU_Sleep_DeInit(PMU_Type *PMUx); +FL_ErrorStatus FL_PMU_Sleep_Init(PMU_Type *PMUx, FL_PMU_SleepInitTypeDef *LPM_InitStruct); +void FL_PMU_StructInit(FL_PMU_SleepInitTypeDef *LPM_InitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_PMU_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rcc.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rcc.h new file mode 100644 index 0000000000..471f61d4da --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rcc.h @@ -0,0 +1,2532 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_rcc.h + * @author FMSH Application Team + * @brief Head file of RCC FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_RCC_H +#define __FM33LC0XX_FL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup RCC_FL_ES_INIT RCC Exported Init structures + * @{ + */ + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup RCC_FL_Exported_Constants RCC Exported Constants + * @{ + */ + +#define FDET_IER_HFDET_IE_Pos (1U) +#define FDET_IER_HFDET_IE_Msk (0x1U << FDET_IER_HFDET_IE_Pos) +#define FDET_IER_HFDET_IE FDET_IER_HFDET_IE_Msk + +#define FDET_IER_LFDET_IE_Pos (0U) +#define FDET_IER_LFDET_IE_Msk (0x1U << FDET_IER_LFDET_IE_Pos) +#define FDET_IER_LFDET_IE FDET_IER_LFDET_IE_Msk + +#define FDET_ISR_HFDETO_Pos (9U) +#define FDET_ISR_HFDETO_Msk (0x1U << FDET_ISR_HFDETO_Pos) +#define FDET_ISR_HFDETO FDET_ISR_HFDETO_Msk + +#define FDET_ISR_LFDETO_Pos (8U) +#define FDET_ISR_LFDETO_Msk (0x1U << FDET_ISR_LFDETO_Pos) +#define FDET_ISR_LFDETO FDET_ISR_LFDETO_Msk + +#define FDET_ISR_HFDETIF_Pos (1U) +#define FDET_ISR_HFDETIF_Msk (0x1U << FDET_ISR_HFDETIF_Pos) +#define FDET_ISR_HFDETIF FDET_ISR_HFDETIF_Msk + +#define FDET_ISR_LFDETIF_Pos (0U) +#define FDET_ISR_LFDETIF_Msk (0x1U << FDET_ISR_LFDETIF_Pos) +#define FDET_ISR_LFDETIF FDET_ISR_LFDETIF_Msk + +#define RCC_SYSCLKCR_LSCATS_Pos (27U) +#define RCC_SYSCLKCR_LSCATS_Msk (0x1U << RCC_SYSCLKCR_LSCATS_Pos) +#define RCC_SYSCLKCR_LSCATS RCC_SYSCLKCR_LSCATS_Msk + +#define RCC_SYSCLKCR_SLP_ENEXTI_Pos (25U) +#define RCC_SYSCLKCR_SLP_ENEXTI_Msk (0x1U << RCC_SYSCLKCR_SLP_ENEXTI_Pos) +#define RCC_SYSCLKCR_SLP_ENEXTI RCC_SYSCLKCR_SLP_ENEXTI_Msk + +#define RCC_SYSCLKCR_APBPRES2_Pos (19U) +#define RCC_SYSCLKCR_APBPRES2_Msk (0x7U << RCC_SYSCLKCR_APBPRES2_Pos) +#define RCC_SYSCLKCR_APBPRES2 RCC_SYSCLKCR_APBPRES2_Msk + +#define RCC_SYSCLKCR_APBPRES1_Pos (16U) +#define RCC_SYSCLKCR_APBPRES1_Msk (0x7U << RCC_SYSCLKCR_APBPRES1_Pos) +#define RCC_SYSCLKCR_APBPRES1 RCC_SYSCLKCR_APBPRES1_Msk + +#define RCC_SYSCLKCR_AHBPRES_Pos (8U) +#define RCC_SYSCLKCR_AHBPRES_Msk (0x7U << RCC_SYSCLKCR_AHBPRES_Pos) +#define RCC_SYSCLKCR_AHBPRES RCC_SYSCLKCR_AHBPRES_Msk + +#define RCC_SYSCLKCR_STCLKSEL_Pos (6U) +#define RCC_SYSCLKCR_STCLKSEL_Msk (0x3U << RCC_SYSCLKCR_STCLKSEL_Pos) +#define RCC_SYSCLKCR_STCLKSEL RCC_SYSCLKCR_STCLKSEL_Msk + +#define RCC_SYSCLKCR_BCKOSEL_Pos (3U) +#define RCC_SYSCLKCR_BCKOSEL_Msk (0x1U << RCC_SYSCLKCR_BCKOSEL_Pos) +#define RCC_SYSCLKCR_BCKOSEL RCC_SYSCLKCR_BCKOSEL_Msk + +#define RCC_SYSCLKCR_SYSCLKSEL_Pos (0U) +#define RCC_SYSCLKCR_SYSCLKSEL_Msk (0x7U << RCC_SYSCLKCR_SYSCLKSEL_Pos) +#define RCC_SYSCLKCR_SYSCLKSEL RCC_SYSCLKCR_SYSCLKSEL_Msk + +#define RCC_RCHFCR_FSEL_Pos (16U) +#define RCC_RCHFCR_FSEL_Msk (0xfU << RCC_RCHFCR_FSEL_Pos) +#define RCC_RCHFCR_FSEL RCC_RCHFCR_FSEL_Msk + +#define RCC_RCHFCR_EN_Pos (0U) +#define RCC_RCHFCR_EN_Msk (0x1U << RCC_RCHFCR_EN_Pos) +#define RCC_RCHFCR_EN RCC_RCHFCR_EN_Msk + +#define RCC_RCMFTR_TRIM_Pos (0U) +#define RCC_RCMFTR_TRIM_Msk (0x7fU << RCC_RCMFTR_TRIM_Pos) +#define RCC_RCMFTR_TRIM RCC_RCMFTR_TRIM_Msk + +#define RCC_PLLCR_EN_Pos (0U) +#define RCC_PLLCR_EN_Msk (0x1U << RCC_PLLCR_EN_Pos) +#define RCC_PLLCR_EN RCC_PLLCR_EN_Msk + +#define RCC_PLLCR_LOCKED_Pos (7U) +#define RCC_PLLCR_LOCKED_Msk (0x1U << RCC_PLLCR_LOCKED_Pos) +#define RCC_PLLCR_LOCKED RCC_PLLCR_LOCKED_Msk + +#define RCC_PLLCR_INSEL_Pos (1U) +#define RCC_PLLCR_INSEL_Msk (0x1U << RCC_PLLCR_INSEL_Pos) +#define RCC_PLLCR_INSEL RCC_PLLCR_INSEL_Msk + +#define RCC_PLLCR_DB_Pos (16U) +#define RCC_PLLCR_DB_Msk (0x7fU << RCC_PLLCR_DB_Pos) +#define RCC_PLLCR_DB RCC_PLLCR_DB_Msk + +#define RCC_PLLCR_REFPRSC_Pos (4U) +#define RCC_PLLCR_REFPRSC_Msk (0x7U << RCC_PLLCR_REFPRSC_Pos) +#define RCC_PLLCR_REFPRSC RCC_PLLCR_REFPRSC_Msk + +#define RCC_PLLCR_OSEL_Pos (3U) +#define RCC_PLLCR_OSEL_Msk (0x1U << RCC_PLLCR_OSEL_Pos) +#define RCC_PLLCR_OSEL RCC_PLLCR_OSEL_Msk + +#define RCC_LPOSCCR_LPOENB_Pos (1U) +#define RCC_LPOSCCR_LPOENB_Msk (0x1U << RCC_LPOSCCR_LPOENB_Pos) +#define RCC_LPOSCCR_LPOENB RCC_LPOSCCR_LPOENB_Msk + +#define RCC_LPOSCCR_LPM_LPO_OFF_Pos (0U) +#define RCC_LPOSCCR_LPM_LPO_OFF_Msk (0x1U << RCC_LPOSCCR_LPM_LPO_OFF_Pos) +#define RCC_LPOSCCR_LPM_LPO_OFF RCC_LPOSCCR_LPM_LPO_OFF_Msk + +#define RCC_LPOSCCR_LPO_CHOP_EN_Pos (2U) +#define RCC_LPOSCCR_LPO_CHOP_EN_Msk (0x1U << RCC_LPOSCCR_LPO_CHOP_EN_Pos) +#define RCC_LPOSCCR_LPO_CHOP_EN RCC_LPOSCCR_LPO_CHOP_EN_Msk + +#define RCC_LPOSCTR_TRIM_Pos (0U) +#define RCC_LPOSCTR_TRIM_Msk (0xffU << RCC_LPOSCTR_TRIM_Pos) +#define RCC_LPOSCTR_TRIM RCC_LPOSCTR_TRIM_Msk + +#define RCC_XTLFCR_EN_Pos (8U) +#define RCC_XTLFCR_EN_Msk (0xfU << RCC_XTLFCR_EN_Pos) +#define RCC_XTLFCR_EN RCC_XTLFCR_EN_Msk + +#define RCC_XTLFCR_IPW_Pos (0U) +#define RCC_XTLFCR_IPW_Msk (0x7U << RCC_XTLFCR_IPW_Pos) +#define RCC_XTLFCR_IPW RCC_XTLFCR_IPW_Msk + +#define RCC_XTHFCR_CFG_Pos (8U) +#define RCC_XTHFCR_CFG_Msk (0x7U << RCC_XTHFCR_CFG_Pos) +#define RCC_XTHFCR_CFG RCC_XTHFCR_CFG_Msk + +#define RCC_XTHFCR_EN_Pos (0U) +#define RCC_XTHFCR_EN_Msk (0x1U << RCC_XTHFCR_EN_Pos) +#define RCC_XTHFCR_EN RCC_XTHFCR_EN_Msk + +#define RCC_RCMFCR_PSC_Pos (16U) +#define RCC_RCMFCR_PSC_Msk (0x3U << RCC_RCMFCR_PSC_Pos) +#define RCC_RCMFCR_PSC RCC_RCMFCR_PSC_Msk + +#define RCC_RCMFCR_EN_Pos (0U) +#define RCC_RCMFCR_EN_Msk (0x1U << RCC_RCMFCR_EN_Pos) +#define RCC_RCMFCR_EN RCC_RCMFCR_EN_Msk + +#define RCC_RCHFTR_TRIM_Pos (0U) +#define RCC_RCHFTR_TRIM_Msk (0x7fU << RCC_RCHFTR_TRIM_Pos) +#define RCC_RCHFTR_TRIM RCC_RCHFTR_TRIM_Msk + +#define RCC_OPCCR1_EXTICKS_Pos (30U) +#define RCC_OPCCR1_EXTICKS_Msk (0x1U << RCC_OPCCR1_EXTICKS_Pos) +#define RCC_OPCCR1_EXTICKS RCC_OPCCR1_EXTICKS_Msk + +#define RCC_OPCCR1_LPUART1CKS_Pos (26U) +#define RCC_OPCCR1_LPUART1CKS_Msk (0x3U << RCC_OPCCR1_LPUART1CKS_Pos) +#define RCC_OPCCR1_LPUART1CKS RCC_OPCCR1_LPUART1CKS_Msk + +#define RCC_OPCCR1_LPUART0CKS_Pos (24U) +#define RCC_OPCCR1_LPUART0CKS_Msk (0x3U << RCC_OPCCR1_LPUART0CKS_Pos) +#define RCC_OPCCR1_LPUART0CKS RCC_OPCCR1_LPUART0CKS_Msk + +#define RCC_OPCCR1_I2CCKS_Pos (16U) +#define RCC_OPCCR1_I2CCKS_Msk (0x3U << RCC_OPCCR1_I2CCKS_Pos) +#define RCC_OPCCR1_I2CCKS RCC_OPCCR1_I2CCKS_Msk + +#define RCC_OPCCR1_ATCKS_Pos (6U) +#define RCC_OPCCR1_ATCKS_Msk (0x3U << RCC_OPCCR1_ATCKS_Pos) +#define RCC_OPCCR1_ATCKS RCC_OPCCR1_ATCKS_Msk + +#define RCC_OPCCR1_UART1CKS_Pos (2U) +#define RCC_OPCCR1_UART1CKS_Msk (0x3U << RCC_OPCCR1_UART1CKS_Pos) +#define RCC_OPCCR1_UART1CKS RCC_OPCCR1_UART1CKS_Msk + +#define RCC_OPCCR1_UART0CKS_Pos (0U) +#define RCC_OPCCR1_UART0CKS_Msk (0x3U << RCC_OPCCR1_UART0CKS_Pos) +#define RCC_OPCCR1_UART0CKS RCC_OPCCR1_UART0CKS_Msk + +#define RCC_OPCCR2_RNGPRSC_Pos (28U) +#define RCC_OPCCR2_RNGPRSC_Msk (0x7U << RCC_OPCCR2_RNGPRSC_Pos) +#define RCC_OPCCR2_RNGPRSC RCC_OPCCR2_RNGPRSC_Msk + +#define RCC_OPCCR2_ADCPRSC_Pos (24U) +#define RCC_OPCCR2_ADCPRSC_Msk (0x7U << RCC_OPCCR2_ADCPRSC_Pos) +#define RCC_OPCCR2_ADCPRSC RCC_OPCCR2_ADCPRSC_Msk + +#define RCC_OPCCR2_USBCKS_Pos (23U) +#define RCC_OPCCR2_USBCKS_Msk (0x1U << RCC_OPCCR2_USBCKS_Pos) +#define RCC_OPCCR2_USBCKS RCC_OPCCR2_USBCKS_Msk + +#define RCC_OPCCR2_ADCCKS_Pos (16U) +#define RCC_OPCCR2_ADCCKS_Msk (0x3U << RCC_OPCCR2_ADCCKS_Pos) +#define RCC_OPCCR2_ADCCKS RCC_OPCCR2_ADCCKS_Msk + +#define RCC_OPCCR2_LPT32CKS_Pos (8U) +#define RCC_OPCCR2_LPT32CKS_Msk (0x3U << RCC_OPCCR2_LPT32CKS_Pos) +#define RCC_OPCCR2_LPT32CKS RCC_OPCCR2_LPT32CKS_Msk + +#define RCC_OPCCR2_BT32CKS_Pos (0U) +#define RCC_OPCCR2_BT32CKS_Msk (0x3U << RCC_OPCCR2_BT32CKS_Pos) +#define RCC_OPCCR2_BT32CKS RCC_OPCCR2_BT32CKS_Msk + +#define RCC_AHBMCR_MPRIL_Pos (0U) +#define RCC_AHBMCR_MPRIL_Msk (0x1U << RCC_AHBMCR_MPRIL_Pos) +#define RCC_AHBMCR_MPRIL RCC_AHBMCR_MPRIL_Msk + +#define RCC_LSCLKSEL_SEL_Pos (0U) +#define RCC_LSCLKSEL_SEL_Msk (0xffU << RCC_LSCLKSEL_SEL_Pos) +#define RCC_LSCLKSEL_SEL RCC_LSCLKSEL_SEL_Msk + +#define RCC_LKPCR_RST_EN_Pos (1U) +#define RCC_LKPCR_RST_EN_Msk (0x1U << RCC_LKPCR_RST_EN_Pos) +#define RCC_LKPCR_RST_EN RCC_LKPCR_RST_EN_Msk + +#define RCC_RSTFR_MDFN_FLAG_Pos (12U) +#define RCC_RSTFR_MDFN_FLAG_Msk (0x1U << RCC_RSTFR_MDFN_FLAG_Pos) +#define RCC_RSTFR_MDFN_FLAG RCC_RSTFR_MDFN_FLAG_Msk + +#define RCC_RSTFR_NRSTN_FLAG_Pos (11U) +#define RCC_RSTFR_NRSTN_FLAG_Msk (0x1U << RCC_RSTFR_NRSTN_FLAG_Pos) +#define RCC_RSTFR_NRSTN_FLAG RCC_RSTFR_NRSTN_FLAG_Msk + +#define RCC_RSTFR_TESTN_FLAG_Pos (10U) +#define RCC_RSTFR_TESTN_FLAG_Msk (0x1U << RCC_RSTFR_TESTN_FLAG_Pos) +#define RCC_RSTFR_TESTN_FLAG RCC_RSTFR_TESTN_FLAG_Msk + +#define RCC_RSTFR_PORN_FLAG_Pos (9U) +#define RCC_RSTFR_PORN_FLAG_Msk (0x1U << RCC_RSTFR_PORN_FLAG_Pos) +#define RCC_RSTFR_PORN_FLAG RCC_RSTFR_PORN_FLAG_Msk + +#define RCC_RSTFR_PDRN_FLAG_Pos (8U) +#define RCC_RSTFR_PDRN_FLAG_Msk (0x1U << RCC_RSTFR_PDRN_FLAG_Pos) +#define RCC_RSTFR_PDRN_FLAG RCC_RSTFR_PDRN_FLAG_Msk + +#define RCC_RSTFR_SOFTN_FLAG_Pos (5U) +#define RCC_RSTFR_SOFTN_FLAG_Msk (0x1U << RCC_RSTFR_SOFTN_FLAG_Pos) +#define RCC_RSTFR_SOFTN_FLAG RCC_RSTFR_SOFTN_FLAG_Msk + +#define RCC_RSTFR_IWDTN_FLAG_Pos (4U) +#define RCC_RSTFR_IWDTN_FLAG_Msk (0x1U << RCC_RSTFR_IWDTN_FLAG_Pos) +#define RCC_RSTFR_IWDTN_FLAG RCC_RSTFR_IWDTN_FLAG_Msk + +#define RCC_RSTFR_WWDTN_FLAG_Pos (2U) +#define RCC_RSTFR_WWDTN_FLAG_Msk (0x1U << RCC_RSTFR_WWDTN_FLAG_Pos) +#define RCC_RSTFR_WWDTN_FLAG RCC_RSTFR_WWDTN_FLAG_Msk + +#define RCC_RSTFR_LKUPN_FLAG_Pos (1U) +#define RCC_RSTFR_LKUPN_FLAG_Msk (0x1U << RCC_RSTFR_LKUPN_FLAG_Pos) +#define RCC_RSTFR_LKUPN_FLAG RCC_RSTFR_LKUPN_FLAG_Msk + +#define RCC_RSTFR_NVICN_FLAG_Pos (0U) +#define RCC_RSTFR_NVICN_FLAG_Msk (0x1U << RCC_RSTFR_NVICN_FLAG_Pos) +#define RCC_RSTFR_NVICN_FLAG RCC_RSTFR_NVICN_FLAG_Msk + + + +#define FL_RCC_GROUP1_BUSCLK_LPTIM32 (0x1U << 0U) +#define FL_RCC_GROUP1_BUSCLK_USB (0x1U << 1U) +#define FL_RCC_GROUP1_BUSCLK_RTC (0x1U << 2U) +#define FL_RCC_GROUP1_BUSCLK_PMU (0x1U << 3U) +#define FL_RCC_GROUP1_BUSCLK_SCU (0x1U << 4U) +#define FL_RCC_GROUP1_BUSCLK_IWDT (0x1U << 5U) +#define FL_RCC_GROUP1_BUSCLK_ANAC (0x1U << 6U) +#define FL_RCC_GROUP1_BUSCLK_PAD (0x1U << 7U) +#define FL_RCC_GROUP1_BUSCLK_DCU (0x1U << 31U) +#define FL_RCC_GROUP2_BUSCLK_CRC (0x1U << 0U) +#define FL_RCC_GROUP2_BUSCLK_RNG (0x1U << 1U) +#define FL_RCC_GROUP2_BUSCLK_AES (0x1U << 2U) +#define FL_RCC_GROUP2_BUSCLK_LCD (0x1U << 3U) +#define FL_RCC_GROUP2_BUSCLK_DMA (0x1U << 4U) +#define FL_RCC_GROUP2_BUSCLK_FLASH (0x1U << 5U) +#define FL_RCC_GROUP2_BUSCLK_RAMBIST (0x1U << 6U) +#define FL_RCC_GROUP2_BUSCLK_WWDT (0x1U << 7U) +#define FL_RCC_GROUP2_BUSCLK_ADC (0x1U << 8U) +#define FL_RCC_GROUP2_BUSCLK_HDIV (0x1U << 9U) +#define FL_RCC_GROUP3_BUSCLK_SPI1 (0x1U << 0U) +#define FL_RCC_GROUP3_BUSCLK_SPI2 (0x1U << 1U) +#define FL_RCC_GROUP3_BUSCLK_UART0 (0x1U << 8U) +#define FL_RCC_GROUP3_BUSCLK_UART1 (0x1U << 9U) +#define FL_RCC_GROUP3_BUSCLK_UART4 (0x1U << 12U) +#define FL_RCC_GROUP3_BUSCLK_UART5 (0x1U << 13U) +#define FL_RCC_GROUP3_BUSCLK_UARTIR (0x1U << 14U) +#define FL_RCC_GROUP3_BUSCLK_LPUART0 (0x1U << 15U) +#define FL_RCC_GROUP3_BUSCLK_U7816 (0x1U << 16U) +#define FL_RCC_GROUP3_BUSCLK_LPUART1 (0x1U << 18U) +#define FL_RCC_GROUP3_BUSCLK_I2C (0x1U << 24U) +#define FL_RCC_GROUP4_BUSCLK_BSTIM32 (0x1U << 0U) +#define FL_RCC_GROUP4_BUSCLK_GPTIM0 (0x1U << 2U) +#define FL_RCC_GROUP4_BUSCLK_GPTIM1 (0x1U << 3U) +#define FL_RCC_GROUP4_BUSCLK_ATIM (0x1U << 4U) +#define FL_RCC_GROUP1_OPCLK_EXTI (0x1U << 31U) +#define FL_RCC_GROUP1_OPCLK_LPUART1 (0x1U << 29U) +#define FL_RCC_GROUP1_OPCLK_LPUART0 (0x1U << 28U) +#define FL_RCC_GROUP1_OPCLK_I2C (0x1U << 20U) +#define FL_RCC_GROUP1_OPCLK_ATIM (0x1U << 15U) +#define FL_RCC_GROUP1_OPCLK_UART1 (0x1U << 9U) +#define FL_RCC_GROUP1_OPCLK_UART0 (0x1U << 8U) +#define FL_RCC_GROUP2_OPCLK_USB (0x1U << 23U) +#define FL_RCC_GROUP2_OPCLK_FLASH (0x1U << 22U) +#define FL_RCC_GROUP2_OPCLK_RNG (0x1U << 21U) +#define FL_RCC_GROUP2_OPCLK_ADC (0x1U << 20U) +#define FL_RCC_GROUP2_OPCLK_LPTIM32 (0x1U << 12U) +#define FL_RCC_GROUP2_OPCLK_BSTIM32 (0x1U << 4U) +#define FL_RCC_RSTAHB_DMA (0x1U << 0U) +#define FL_RCC_RSTAHB_USB (0x1U << 1U) +#define FL_RCC_RSTAPB_UART5 (0x1U << 31U) +#define FL_RCC_RSTAPB_UART4 (0x1U << 30U) +#define FL_RCC_RSTAPB_GPTIM1 (0x1U << 25U) +#define FL_RCC_RSTAPB_GPTIM0 (0x1U << 24U) +#define FL_RCC_RSTAPB_LCD (0x1U << 16U) +#define FL_RCC_RSTAPB_U7816 (0x1U << 14U) +#define FL_RCC_RSTAPB_SPI2 (0x1U << 10U) +#define FL_RCC_RSTAPB_LPUART0 (0x1U << 6U) +#define FL_RCC_RSTAPB_I2C (0x1U << 3U) +#define FL_RCC_RSTAPB_LPTIM32 (0x1U << 0U) +#define FL_RCC_RSTAPB_ATIM (0x1U << 31U) +#define FL_RCC_RSTAPB_BSTIM32 (0x1U << 28U) +#define FL_RCC_RSTAPB_ADCCR (0x1U << 24U) +#define FL_RCC_RSTAPB_ADC (0x1U << 23U) +#define FL_RCC_RSTAPB_OPA (0x1U << 22U) +#define FL_RCC_RSTAPB_DIVAS (0x1U << 19U) +#define FL_RCC_RSTAPB_AES (0x1U << 18U) +#define FL_RCC_RSTAPB_CRC (0x1U << 17U) +#define FL_RCC_RSTAPB_RNG (0x1U << 16U) +#define FL_RCC_RSTAPB_UART1 (0x1U << 12U) +#define FL_RCC_RSTAPB_UART0 (0x1U << 11U) +#define FL_RCC_RSTAPB_SPI1 (0x1U << 9U) +#define FL_RCC_RSTAPB_UCIR (0x1U << 8U) +#define FL_RCC_RSTAPB_LPUART1 (0x1U << 7U) +#define FL_RCC_PERIPHERAL_RESET_KEY 0x13579BDFU +#define FL_RCC_SOFTWARE_RESET_KEY 0x5C5CAABBU +#define FL_RCC_LPUART_CLK_SOURCE_LSCLK 0x0U +#define FL_RCC_LPUART_CLK_SOURCE_RCHF 0x1U +#define FL_RCC_LPUART_CLK_SOURCE_RCMF 0x2U + + + +#define FL_RCC_APB2CLK_PSC_DIV1 (0x0U << RCC_SYSCLKCR_APBPRES2_Pos) +#define FL_RCC_APB2CLK_PSC_DIV2 (0x4U << RCC_SYSCLKCR_APBPRES2_Pos) +#define FL_RCC_APB2CLK_PSC_DIV4 (0x5U << RCC_SYSCLKCR_APBPRES2_Pos) +#define FL_RCC_APB2CLK_PSC_DIV8 (0x6U << RCC_SYSCLKCR_APBPRES2_Pos) +#define FL_RCC_APB2CLK_PSC_DIV16 (0x7U << RCC_SYSCLKCR_APBPRES2_Pos) + + +#define FL_RCC_APB1CLK_PSC_DIV1 (0x0U << RCC_SYSCLKCR_APBPRES1_Pos) +#define FL_RCC_APB1CLK_PSC_DIV2 (0x4U << RCC_SYSCLKCR_APBPRES1_Pos) +#define FL_RCC_APB1CLK_PSC_DIV4 (0x5U << RCC_SYSCLKCR_APBPRES1_Pos) +#define FL_RCC_APB1CLK_PSC_DIV8 (0x6U << RCC_SYSCLKCR_APBPRES1_Pos) +#define FL_RCC_APB1CLK_PSC_DIV16 (0x7U << RCC_SYSCLKCR_APBPRES1_Pos) + + +#define FL_RCC_AHBCLK_PSC_DIV1 (0x0U << RCC_SYSCLKCR_AHBPRES_Pos) +#define FL_RCC_AHBCLK_PSC_DIV2 (0x4U << RCC_SYSCLKCR_AHBPRES_Pos) +#define FL_RCC_AHBCLK_PSC_DIV4 (0x5U << RCC_SYSCLKCR_AHBPRES_Pos) +#define FL_RCC_AHBCLK_PSC_DIV8 (0x6U << RCC_SYSCLKCR_AHBPRES_Pos) +#define FL_RCC_AHBCLK_PSC_DIV16 (0x7U << RCC_SYSCLKCR_AHBPRES_Pos) + + +#define FL_RCC_SYSTICK_CLK_SOURCE_SCLK (0x0U << RCC_SYSCLKCR_STCLKSEL_Pos) +#define FL_RCC_SYSTICK_CLK_SOURCE_LSCLK (0x1U << RCC_SYSCLKCR_STCLKSEL_Pos) +#define FL_RCC_SYSTICK_CLK_SOURCE_RCMF (0x2U << RCC_SYSCLKCR_STCLKSEL_Pos) +#define FL_RCC_SYSTICK_CLK_SOURCE_SYSCLK (0x3U << RCC_SYSCLKCR_STCLKSEL_Pos) + + +#define FL_RCC_USB_CLOCK_SELECT_48M (0x0U << RCC_SYSCLKCR_BCKOSEL_Pos) +#define FL_RCC_USB_CLOCK_SELECT_120M (0x1U << RCC_SYSCLKCR_BCKOSEL_Pos) + + +#define FL_RCC_SYSTEM_CLK_SOURCE_RCHF (0x0U << RCC_SYSCLKCR_SYSCLKSEL_Pos) +#define FL_RCC_SYSTEM_CLK_SOURCE_XTHF (0x1U << RCC_SYSCLKCR_SYSCLKSEL_Pos) +#define FL_RCC_SYSTEM_CLK_SOURCE_PLL (0x2U << RCC_SYSCLKCR_SYSCLKSEL_Pos) +#define FL_RCC_SYSTEM_CLK_SOURCE_RCMFPSC (0x4U << RCC_SYSCLKCR_SYSCLKSEL_Pos) +#define FL_RCC_SYSTEM_CLK_SOURCE_XTLF (0x5U << RCC_SYSCLKCR_SYSCLKSEL_Pos) +#define FL_RCC_SYSTEM_CLK_SOURCE_RCLP (0x6U << RCC_SYSCLKCR_SYSCLKSEL_Pos) +#define FL_RCC_SYSTEM_CLK_SOURCE_USBCLK (0x7U << RCC_SYSCLKCR_SYSCLKSEL_Pos) + + +#define FL_RCC_RCHF_FREQUENCY_8MHZ (0x0U << RCC_RCHFCR_FSEL_Pos) +#define FL_RCC_RCHF_FREQUENCY_16MHZ (0x1U << RCC_RCHFCR_FSEL_Pos) +#define FL_RCC_RCHF_FREQUENCY_24MHZ (0x2U << RCC_RCHFCR_FSEL_Pos) + + +#define FL_RCC_PLL_CLK_SOURCE_RCHF (0x0U << RCC_PLLCR_INSEL_Pos) +#define FL_RCC_PLL_CLK_SOURCE_XTHF (0x1U << RCC_PLLCR_INSEL_Pos) + + +#define FL_RCC_PLL_MUL_32 (0x1fU << RCC_PLLCR_DB_Pos) + +#define FL_RCC_PLL_MUL_48 (0x2fU << RCC_PLLCR_DB_Pos) + +#define FL_RCC_PLL_PSC_DIV1 (0x0U << RCC_PLLCR_REFPRSC_Pos) +#define FL_RCC_PLL_PSC_DIV2 (0x1U << RCC_PLLCR_REFPRSC_Pos) +#define FL_RCC_PLL_PSC_DIV4 (0x2U << RCC_PLLCR_REFPRSC_Pos) +#define FL_RCC_PLL_PSC_DIV8 (0x3U << RCC_PLLCR_REFPRSC_Pos) +#define FL_RCC_PLL_PSC_DIV12 (0x4U << RCC_PLLCR_REFPRSC_Pos) +#define FL_RCC_PLL_PSC_DIV16 (0x5U << RCC_PLLCR_REFPRSC_Pos) +#define FL_RCC_PLL_PSC_DIV24 (0x6U << RCC_PLLCR_REFPRSC_Pos) +#define FL_RCC_PLL_PSC_DIV32 (0x7U << RCC_PLLCR_REFPRSC_Pos) + + +#define FL_RCC_PLL_OUTPUT_X1 (0x0U << RCC_PLLCR_OSEL_Pos) +#define FL_RCC_PLL_OUTPUT_X2 (0x1U << RCC_PLLCR_OSEL_Pos) + + +#define FL_RCC_XTLF_FDET_ENABLE (0x5U << RCC_XTLFCR_EN_Pos) +#define FL_RCC_XTLF_FDET_DISABLE (0xaU << RCC_XTLFCR_EN_Pos) + +#define FL_RCC_XTLF_WORK_CURRENT_450NA (0x0U << RCC_XTLFCR_IPW_Pos) +#define FL_RCC_XTLF_WORK_CURRENT_400NA (0x1U << RCC_XTLFCR_IPW_Pos) +#define FL_RCC_XTLF_WORK_CURRENT_350NA (0x2U << RCC_XTLFCR_IPW_Pos) +#define FL_RCC_XTLF_WORK_CURRENT_300NA (0x3U << RCC_XTLFCR_IPW_Pos) +#define FL_RCC_XTLF_WORK_CURRENT_250NA (0x4U << RCC_XTLFCR_IPW_Pos) +#define FL_RCC_XTLF_WORK_CURRENT_200NA (0x5U << RCC_XTLFCR_IPW_Pos) +#define FL_RCC_XTLF_WORK_CURRENT_150NA (0x6U << RCC_XTLFCR_IPW_Pos) +#define FL_RCC_XTLF_WORK_CURRENT_100NA (0x7U << RCC_XTLFCR_IPW_Pos) + + +#define FL_RCC_RCMF_PSC_DIV1 (0x0U << RCC_RCMFCR_PSC_Pos) +#define FL_RCC_RCMF_PSC_DIV4 (0x1U << RCC_RCMFCR_PSC_Pos) +#define FL_RCC_RCMF_PSC_DIV8 (0x2U << RCC_RCMFCR_PSC_Pos) +#define FL_RCC_RCMF_PSC_DIV16 (0x3U << RCC_RCMFCR_PSC_Pos) + + +#define FL_RCC_EXTI_CLK_SOURCE_LSCLK (0x1U << RCC_OPCCR1_EXTICKS_Pos) +#define FL_RCC_EXTI_CLK_SOURCE_HCLK (0x0U << RCC_OPCCR1_EXTICKS_Pos) + + +#define FL_RCC_LPUART1_CLK_SOURCE_LSCLK (0x0U << RCC_OPCCR1_LPUART1CKS_Pos) +#define FL_RCC_LPUART1_CLK_SOURCE_RCHF (0x1U << RCC_OPCCR1_LPUART1CKS_Pos) +#define FL_RCC_LPUART1_CLK_SOURCE_RCMF (0x2U << RCC_OPCCR1_LPUART1CKS_Pos) + + +#define FL_RCC_LPUART0_CLK_SOURCE_LSCLK (0x0U << RCC_OPCCR1_LPUART0CKS_Pos) +#define FL_RCC_LPUART0_CLK_SOURCE_RCHF (0x1U << RCC_OPCCR1_LPUART0CKS_Pos) +#define FL_RCC_LPUART0_CLK_SOURCE_RCMF (0x2U << RCC_OPCCR1_LPUART0CKS_Pos) + + +#define FL_RCC_I2C_CLK_SOURCE_APB1CLK (0x0U << RCC_OPCCR1_I2CCKS_Pos) +#define FL_RCC_I2C_CLK_SOURCE_RCHF (0x1U << RCC_OPCCR1_I2CCKS_Pos) +#define FL_RCC_I2C_CLK_SOURCE_SYSCLK (0x2U << RCC_OPCCR1_I2CCKS_Pos) +#define FL_RCC_I2C_CLK_SOURCE_RCMF_PSC (0x3U << RCC_OPCCR1_I2CCKS_Pos) + + +#define FL_RCC_ATIM_CLK_SOURCE_APB2CLK (0x0U << RCC_OPCCR1_ATCKS_Pos) +#define FL_RCC_ATIM_CLK_SOURCE_USBPHYBCK120M (0x1U << RCC_OPCCR1_ATCKS_Pos) +#define FL_RCC_ATIM_CLK_SOURCE_PLLx2 (0x3U << RCC_OPCCR1_ATCKS_Pos) + + +#define FL_RCC_UART1_CLK_SOURCE_APB1CLK (0x0U << RCC_OPCCR1_UART1CKS_Pos) +#define FL_RCC_UART1_CLK_SOURCE_RCHF (0x1U << RCC_OPCCR1_UART1CKS_Pos) +#define FL_RCC_UART1_CLK_SOURCE_SYSCLK (0x2U << RCC_OPCCR1_UART1CKS_Pos) +#define FL_RCC_UART1_CLK_SOURCE_RCMF_PSC (0x3U << RCC_OPCCR1_UART1CKS_Pos) + + +#define FL_RCC_UART0_CLK_SOURCE_APB1CLK (0x0U << RCC_OPCCR1_UART0CKS_Pos) +#define FL_RCC_UART0_CLK_SOURCE_RCHF (0x1U << RCC_OPCCR1_UART0CKS_Pos) +#define FL_RCC_UART0_CLK_SOURCE_SYSCLK (0x2U << RCC_OPCCR1_UART0CKS_Pos) +#define FL_RCC_UART0_CLK_SOURCE_RCMF_PSC (0x3U << RCC_OPCCR1_UART0CKS_Pos) + + +#define FL_RCC_RNG_PSC_DIV1 (0x0U << RCC_OPCCR2_RNGPRSC_Pos) +#define FL_RCC_RNG_PSC_DIV2 (0x1U << RCC_OPCCR2_RNGPRSC_Pos) +#define FL_RCC_RNG_PSC_DIV4 (0x2U << RCC_OPCCR2_RNGPRSC_Pos) +#define FL_RCC_RNG_PSC_DIV8 (0x3U << RCC_OPCCR2_RNGPRSC_Pos) +#define FL_RCC_RNG_PSC_DIV16 (0x4U << RCC_OPCCR2_RNGPRSC_Pos) +#define FL_RCC_RNG_PSC_DIV32 (0x5U << RCC_OPCCR2_RNGPRSC_Pos) + + +#define FL_RCC_ADC_PSC_DIV1 (0x0U << RCC_OPCCR2_ADCPRSC_Pos) +#define FL_RCC_ADC_PSC_DIV2 (0x1U << RCC_OPCCR2_ADCPRSC_Pos) +#define FL_RCC_ADC_PSC_DIV4 (0x2U << RCC_OPCCR2_ADCPRSC_Pos) +#define FL_RCC_ADC_PSC_DIV8 (0x3U << RCC_OPCCR2_ADCPRSC_Pos) +#define FL_RCC_ADC_PSC_DIV16 (0x4U << RCC_OPCCR2_ADCPRSC_Pos) +#define FL_RCC_ADC_PSC_DIV32 (0x5U << RCC_OPCCR2_ADCPRSC_Pos) + + +#define FL_RCC_USB_CLK_SOURCE_XTLF (0x0U << RCC_OPCCR2_USBCKS_Pos) +#define FL_RCC_USB_CLK_SOURCE_XTHF (0x1U << RCC_OPCCR2_USBCKS_Pos) + + +#define FL_RCC_ADC_CLK_SOURCE_RCMF_PSC (0x0U << RCC_OPCCR2_ADCCKS_Pos) +#define FL_RCC_ADC_CLK_SOURCE_RCHF (0x1U << RCC_OPCCR2_ADCCKS_Pos) +#define FL_RCC_ADC_CLK_SOURCE_XTHF (0x2U << RCC_OPCCR2_ADCCKS_Pos) +#define FL_RCC_ADC_CLK_SOURCE_PLL (0x3U << RCC_OPCCR2_ADCCKS_Pos) + + +#define FL_RCC_LPTIM32_CLK_SOURCE_APB1CLK (0x0U << RCC_OPCCR2_LPT32CKS_Pos) +#define FL_RCC_LPTIM32_CLK_SOURCE_LSCLK (0x1U << RCC_OPCCR2_LPT32CKS_Pos) +#define FL_RCC_LPTIM32_CLK_SOURCE_RCLP (0x2U << RCC_OPCCR2_LPT32CKS_Pos) +#define FL_RCC_LPTIM32_CLK_SOURCE_RCMF_PSC (0x3U << RCC_OPCCR2_LPT32CKS_Pos) + + +#define FL_RCC_BSTIM32_CLK_SOURCE_APB1CLK (0x0U << RCC_OPCCR2_BT32CKS_Pos) +#define FL_RCC_BSTIM32_CLK_SOURCE_LSCLK (0x1U << RCC_OPCCR2_BT32CKS_Pos) +#define FL_RCC_BSTIM32_CLK_SOURCE_RCLP (0x2U << RCC_OPCCR2_BT32CKS_Pos) +#define FL_RCC_BSTIM32_CLK_SOURCE_RCMF_PSC (0x3U << RCC_OPCCR2_BT32CKS_Pos) + + +#define FL_RCC_AHB_MASTER_PRIORITY_DMA_FIRST (0x0U << RCC_AHBMCR_MPRIL_Pos) +#define FL_RCC_AHB_MASTER_PRIORITY_CPU_FIRST (0x1U << RCC_AHBMCR_MPRIL_Pos) + + +#define FL_RCC_LSCLK_CLK_SOURCE_RCLP (0x55U << RCC_LSCLKSEL_SEL_Pos) +#define FL_RCC_LSCLK_CLK_SOURCE_XTLF (0xAAU << RCC_LSCLKSEL_SEL_Pos) + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup RCC_FL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** + * @brief Enable XTHF Fail Interrupt + * @rmtoll IER HFDET_IE FL_FDET_EnableIT_XTHFFail + * @retval None + */ +__STATIC_INLINE void FL_FDET_EnableIT_XTHFFail(void) +{ + SET_BIT(FDET->IER, FDET_IER_HFDET_IE_Msk); +} + +/** + * @brief Get XTHF Fail Interrupt Enable Status + * @rmtoll IER HFDET_IE FL_FDET_IsEnabledIT_XTHFFail + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FDET_IsEnabledIT_XTHFFail(void) +{ + return (uint32_t)(READ_BIT(FDET->IER, FDET_IER_HFDET_IE_Msk) == FDET_IER_HFDET_IE_Msk); +} + +/** + * @brief Disable XTHF Fail Interrupt + * @rmtoll IER HFDET_IE FL_FDET_DisableIT_XTHFFail + * @retval None + */ +__STATIC_INLINE void FL_FDET_DisableIT_XTHFFail(void) +{ + CLEAR_BIT(FDET->IER, FDET_IER_HFDET_IE_Msk); +} + +/** + * @brief Enable XTLF Fail Interrupt + * @rmtoll IER LFDET_IE FL_FDET_EnableIT_XTLFFail + * @retval None + */ +__STATIC_INLINE void FL_FDET_EnableIT_XTLFFail(void) +{ + SET_BIT(FDET->IER, FDET_IER_LFDET_IE_Msk); +} + +/** + * @brief Get XTLF Fail Interrupt Enable Status + * @rmtoll IER LFDET_IE FL_FDET_IsEnabledIT_XTLFFail + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FDET_IsEnabledIT_XTLFFail(void) +{ + return (uint32_t)(READ_BIT(FDET->IER, FDET_IER_LFDET_IE_Msk) == FDET_IER_LFDET_IE_Msk); +} + +/** + * @brief Disable XTLF Fail Interrupt + * @rmtoll IER LFDET_IE FL_FDET_DisableIT_XTLFFail + * @retval None + */ +__STATIC_INLINE void FL_FDET_DisableIT_XTLFFail(void) +{ + CLEAR_BIT(FDET->IER, FDET_IER_LFDET_IE_Msk); +} + +/** + * @brief Get XTHF Vibrating Output + * @rmtoll ISR HFDETO FL_FDET_IsActiveFlag_XTHFFailOutput + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FDET_IsActiveFlag_XTHFFailOutput(void) +{ + return (uint32_t)(READ_BIT(FDET->ISR, FDET_ISR_HFDETO_Msk) == (FDET_ISR_HFDETO_Msk)); +} + +/** + * @brief Get XTLF Vibrating Output + * @rmtoll ISR LFDETO FL_FDET_IsActiveFlag_XTLFFailOutput + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FDET_IsActiveFlag_XTLFFailOutput(void) +{ + return (uint32_t)(READ_BIT(FDET->ISR, FDET_ISR_LFDETO_Msk) == (FDET_ISR_LFDETO_Msk)); +} + +/** + * @brief Get XTHF Vibrating Flag + * @rmtoll ISR HFDETIF FL_FDET_IsActiveFlag_XTHFFail + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FDET_IsActiveFlag_XTHFFail(void) +{ + return (uint32_t)(READ_BIT(FDET->ISR, FDET_ISR_HFDETIF_Msk) == (FDET_ISR_HFDETIF_Msk)); +} + +/** + * @brief Clear XTHF Vibrating Flag + * @rmtoll ISR HFDETIF FL_FDET_ClearFlag_XTHFFail + * @retval None + */ +__STATIC_INLINE void FL_FDET_ClearFlag_XTHFFail(void) +{ + WRITE_REG(FDET->ISR, FDET_ISR_LFDETIF_Msk); +} + +/** + * @brief Get XTLF Vibrating Output + * @rmtoll ISR LFDETIF FL_FDET_IsActiveFlag_XTLFFail + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_FDET_IsActiveFlag_XTLFFail(void) +{ + return (uint32_t)(READ_BIT(FDET->ISR, FDET_ISR_LFDETIF_Msk) == (FDET_ISR_LFDETIF_Msk)); +} + +/** + * @brief Clear XTLF Vibrating Output + * @rmtoll ISR LFDETIF FL_FDET_ClearFlag_XTLFFail + * @retval None + */ +__STATIC_INLINE void FL_FDET_ClearFlag_XTLFFail(void) +{ + WRITE_REG(FDET->ISR, FDET_ISR_HFDETIF_Msk); +} + +/** + * @brief Enable LSCLK Auto Switch + * @rmtoll SYSCLKCR LSCATS FL_RCC_EnableLSCLKAutoSwitch + * @retval None + */ +__STATIC_INLINE void FL_RCC_EnableLSCLKAutoSwitch(void) +{ + SET_BIT(RCC->SYSCLKCR, RCC_SYSCLKCR_LSCATS_Msk); +} + +/** + * @brief Get LSCLK Auto Switch Enable Status + * @rmtoll SYSCLKCR LSCATS FL_RCC_IsEnabledLSCLKAutoSwitch + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsEnabledLSCLKAutoSwitch(void) +{ + return (uint32_t)(READ_BIT(RCC->SYSCLKCR, RCC_SYSCLKCR_LSCATS_Msk) == RCC_SYSCLKCR_LSCATS_Msk); +} + +/** + * @brief Disable LSCLK Auto Switch + * @rmtoll SYSCLKCR LSCATS FL_RCC_DisableLSCLKAutoSwitch + * @retval None + */ +__STATIC_INLINE void FL_RCC_DisableLSCLKAutoSwitch(void) +{ + CLEAR_BIT(RCC->SYSCLKCR, RCC_SYSCLKCR_LSCATS_Msk); +} + +/** + * @brief Enable Sleep/DeepSleep Mode External Interrupt + * @rmtoll SYSCLKCR SLP_ENEXTI FL_RCC_EnableEXTIOnSleep + * @retval None + */ +__STATIC_INLINE void FL_RCC_EnableEXTIOnSleep(void) +{ + SET_BIT(RCC->SYSCLKCR, RCC_SYSCLKCR_SLP_ENEXTI_Msk); +} + +/** + * @brief Get Sleep/DeepSleep Mode External Interrupt Enable Status + * @rmtoll SYSCLKCR SLP_ENEXTI FL_RCC_IsEnabledEXTIOnSleep + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsEnabledEXTIOnSleep(void) +{ + return (uint32_t)(READ_BIT(RCC->SYSCLKCR, RCC_SYSCLKCR_SLP_ENEXTI_Msk) == RCC_SYSCLKCR_SLP_ENEXTI_Msk); +} + +/** + * @brief Disable Sleep/DeepSleep Mode External Interrupt + * @rmtoll SYSCLKCR SLP_ENEXTI FL_RCC_DisableEXTIOnSleep + * @retval None + */ +__STATIC_INLINE void FL_RCC_DisableEXTIOnSleep(void) +{ + CLEAR_BIT(RCC->SYSCLKCR, RCC_SYSCLKCR_SLP_ENEXTI_Msk); +} + +/** + * @brief Set APB2 Prescaler + * @rmtoll SYSCLKCR APBPRES2 FL_RCC_SetAPB2Prescaler + * @param prescaler This parameter can be one of the following values: + * @arg @ref FL_RCC_APB2CLK_PSC_DIV1 + * @arg @ref FL_RCC_APB2CLK_PSC_DIV2 + * @arg @ref FL_RCC_APB2CLK_PSC_DIV4 + * @arg @ref FL_RCC_APB2CLK_PSC_DIV8 + * @arg @ref FL_RCC_APB2CLK_PSC_DIV16 + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetAPB2Prescaler(uint32_t prescaler) +{ + MODIFY_REG(RCC->SYSCLKCR, RCC_SYSCLKCR_APBPRES2_Msk, prescaler); +} + +/** + * @brief Get APB2 Prescaler + * @rmtoll SYSCLKCR APBPRES2 FL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_APB2CLK_PSC_DIV1 + * @arg @ref FL_RCC_APB2CLK_PSC_DIV2 + * @arg @ref FL_RCC_APB2CLK_PSC_DIV4 + * @arg @ref FL_RCC_APB2CLK_PSC_DIV8 + * @arg @ref FL_RCC_APB2CLK_PSC_DIV16 + */ +__STATIC_INLINE uint32_t FL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->SYSCLKCR, RCC_SYSCLKCR_APBPRES2_Msk)); +} + +/** + * @brief Set APB1 Prescaler + * @rmtoll SYSCLKCR APBPRES1 FL_RCC_SetAPB1Prescaler + * @param prescaler This parameter can be one of the following values: + * @arg @ref FL_RCC_APB1CLK_PSC_DIV1 + * @arg @ref FL_RCC_APB1CLK_PSC_DIV2 + * @arg @ref FL_RCC_APB1CLK_PSC_DIV4 + * @arg @ref FL_RCC_APB1CLK_PSC_DIV8 + * @arg @ref FL_RCC_APB1CLK_PSC_DIV16 + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetAPB1Prescaler(uint32_t prescaler) +{ + MODIFY_REG(RCC->SYSCLKCR, RCC_SYSCLKCR_APBPRES1_Msk, prescaler); +} + +/** + * @brief Get APB1 Prescaler + * @rmtoll SYSCLKCR APBPRES1 FL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_APB1CLK_PSC_DIV1 + * @arg @ref FL_RCC_APB1CLK_PSC_DIV2 + * @arg @ref FL_RCC_APB1CLK_PSC_DIV4 + * @arg @ref FL_RCC_APB1CLK_PSC_DIV8 + * @arg @ref FL_RCC_APB1CLK_PSC_DIV16 + */ +__STATIC_INLINE uint32_t FL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->SYSCLKCR, RCC_SYSCLKCR_APBPRES1_Msk)); +} + +/** + * @brief Set AHB Prescaler + * @rmtoll SYSCLKCR AHBPRES FL_RCC_SetAHBPrescaler + * @param prescaler This parameter can be one of the following values: + * @arg @ref FL_RCC_AHBCLK_PSC_DIV1 + * @arg @ref FL_RCC_AHBCLK_PSC_DIV2 + * @arg @ref FL_RCC_AHBCLK_PSC_DIV4 + * @arg @ref FL_RCC_AHBCLK_PSC_DIV8 + * @arg @ref FL_RCC_AHBCLK_PSC_DIV16 + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetAHBPrescaler(uint32_t prescaler) +{ + MODIFY_REG(RCC->SYSCLKCR, RCC_SYSCLKCR_AHBPRES_Msk, prescaler); +} + +/** + * @brief Get AHB Prescaler + * @rmtoll SYSCLKCR AHBPRES FL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_AHBCLK_PSC_DIV1 + * @arg @ref FL_RCC_AHBCLK_PSC_DIV2 + * @arg @ref FL_RCC_AHBCLK_PSC_DIV4 + * @arg @ref FL_RCC_AHBCLK_PSC_DIV8 + * @arg @ref FL_RCC_AHBCLK_PSC_DIV16 + */ +__STATIC_INLINE uint32_t FL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->SYSCLKCR, RCC_SYSCLKCR_AHBPRES_Msk)); +} + +/** + * @brief Set USB PHY BCK Output Clock Source + * @rmtoll SYSCLKCR BCKOSEL FL_RCC_SetUSBClockSource + * @param source This parameter can be one of the following values: + * @arg @ref FL_RCC_USB_CLOCK_SELECT_48M + * @arg @ref FL_RCC_USB_CLOCK_SELECT_120M + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetUSBClockSource(uint32_t source) +{ + MODIFY_REG(RCC->SYSCLKCR, RCC_SYSCLKCR_BCKOSEL_Msk, source); +} + +/** + * @brief Get USB PHY BCK Output Clock Source Setting + * @rmtoll SYSCLKCR BCKOSEL FL_RCC_GetUSBClockSource + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_USB_CLOCK_SELECT_48M + * @arg @ref FL_RCC_USB_CLOCK_SELECT_120M + */ +__STATIC_INLINE uint32_t FL_RCC_GetUSBClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->SYSCLKCR, RCC_SYSCLKCR_BCKOSEL_Msk)); +} + +/** + * @brief Set System Clock Source + * @rmtoll SYSCLKCR SYSCLKSEL FL_RCC_SetSystemClockSource + * @param clock This parameter can be one of the following values: + * @arg @ref FL_RCC_SYSTEM_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_SYSTEM_CLK_SOURCE_XTHF + * @arg @ref FL_RCC_SYSTEM_CLK_SOURCE_PLL + * @arg @ref FL_RCC_SYSTEM_CLK_SOURCE_RCMFPSC + * @arg @ref FL_RCC_SYSTEM_CLK_SOURCE_XTLF + * @arg @ref FL_RCC_SYSTEM_CLK_SOURCE_RCLP + * @arg @ref FL_RCC_SYSTEM_CLK_SOURCE_USBCLK + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetSystemClockSource(uint32_t clock) +{ + MODIFY_REG(RCC->SYSCLKCR, RCC_SYSCLKCR_SYSCLKSEL_Msk, clock); +} + +/** + * @brief Set System Clock Source Setting + * @rmtoll SYSCLKCR SYSCLKSEL FL_RCC_GetSystemClockSource + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_SYSTEM_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_SYSTEM_CLK_SOURCE_XTHF + * @arg @ref FL_RCC_SYSTEM_CLK_SOURCE_PLL + * @arg @ref FL_RCC_SYSTEM_CLK_SOURCE_RCMFPSC + * @arg @ref FL_RCC_SYSTEM_CLK_SOURCE_XTLF + * @arg @ref FL_RCC_SYSTEM_CLK_SOURCE_RCLP + * @arg @ref FL_RCC_SYSTEM_CLK_SOURCE_USBCLK + */ +__STATIC_INLINE uint32_t FL_RCC_GetSystemClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->SYSCLKCR, RCC_SYSCLKCR_SYSCLKSEL_Msk)); +} + +/** + * @brief Set RCHF Frequency + * @rmtoll RCHFCR FSEL FL_RCC_RCHF_SetFrequency + * @param frequency This parameter can be one of the following values: + * @arg @ref FL_RCC_RCHF_FREQUENCY_8MHZ + * @arg @ref FL_RCC_RCHF_FREQUENCY_16MHZ + * @arg @ref FL_RCC_RCHF_FREQUENCY_24MHZ + * @retval None + */ +__STATIC_INLINE void FL_RCC_RCHF_SetFrequency(uint32_t frequency) +{ + MODIFY_REG(RCC->RCHFCR, RCC_RCHFCR_FSEL_Msk, frequency); +} + +/** + * @brief Get RCHF Frequency Setting + * @rmtoll RCHFCR FSEL FL_RCC_RCHF_GetFrequency + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_RCHF_FREQUENCY_8MHZ + * @arg @ref FL_RCC_RCHF_FREQUENCY_16MHZ + * @arg @ref FL_RCC_RCHF_FREQUENCY_24MHZ + */ +__STATIC_INLINE uint32_t FL_RCC_RCHF_GetFrequency(void) +{ + return (uint32_t)(READ_BIT(RCC->RCHFCR, RCC_RCHFCR_FSEL_Msk)); +} + +/** + * @brief Enable RCHF + * @rmtoll RCHFCR EN FL_RCC_RCHF_Enable + * @retval None + */ +__STATIC_INLINE void FL_RCC_RCHF_Enable(void) +{ + SET_BIT(RCC->RCHFCR, RCC_RCHFCR_EN_Msk); +} + +/** + * @brief Get RCHF Enable Status + * @rmtoll RCHFCR EN FL_RCC_RCHF_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_RCHF_IsEnabled(void) +{ + return (uint32_t)(READ_BIT(RCC->RCHFCR, RCC_RCHFCR_EN_Msk) == RCC_RCHFCR_EN_Msk); +} + +/** + * @brief Disable RCHF + * @rmtoll RCHFCR EN FL_RCC_RCHF_Disable + * @retval None + */ +__STATIC_INLINE void FL_RCC_RCHF_Disable(void) +{ + CLEAR_BIT(RCC->RCHFCR, RCC_RCHFCR_EN_Msk); +} + +/** + * @brief Set RCMF Frequency Trim Value + * @rmtoll RCMFTR TRIM FL_RCC_RCMF_WriteTrimValue + * @param value TrimValue The value of RCMF trim + * @retval None + */ +__STATIC_INLINE void FL_RCC_RCMF_WriteTrimValue(uint32_t value) +{ + MODIFY_REG(RCC->RCMFTR, (0x7fU << 0U), (value << 0U)); +} + +/** + * @brief Get RCMF Frequency Trim Value + * @rmtoll RCMFTR TRIM FL_RCC_RCMF_ReadTrimValue + * @retval The Value of RC4M trim + */ +__STATIC_INLINE uint32_t FL_RCC_RCMF_ReadTrimValue(void) +{ + return (uint32_t)(READ_BIT(RCC->RCMFTR, 0x7fU) >> 0U); +} + +/** + * @brief Enable PLL + * @rmtoll PLLCR EN FL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void FL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->PLLCR, RCC_PLLCR_EN_Msk); +} + +/** + * @brief Get PLL Enable Status + * @rmtoll PLLCR EN FL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void FL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->PLLCR, RCC_PLLCR_EN_Msk); +} + +/** + * @brief Disable PLL + * @rmtoll PLLCR EN FL_RCC_PLL_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_PLL_IsEnabled(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCR, RCC_PLLCR_EN_Msk) == RCC_PLLCR_EN_Msk); +} + +/** + * @brief Get PLL Ready Status + * @rmtoll PLLCR LOCKED FL_RCC_IsActiveFlag_PLLReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsActiveFlag_PLLReady(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCR, RCC_PLLCR_LOCKED_Msk) == (RCC_PLLCR_LOCKED_Msk)); +} + +/** + * @brief Set PLL Input Source + * @rmtoll PLLCR INSEL FL_RCC_PLL_SetClockSource + * @param clock This parameter can be one of the following values: + * @arg @ref FL_RCC_PLL_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_PLL_CLK_SOURCE_XTHF + * @retval None + */ +__STATIC_INLINE void FL_RCC_PLL_SetClockSource(uint32_t clock) +{ + MODIFY_REG(RCC->PLLCR, RCC_PLLCR_INSEL_Msk, clock); +} + +/** + * @brief Get PLL Input Source Setting + * @rmtoll PLLCR INSEL FL_RCC_PLL_GetClockSource + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_PLL_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_PLL_CLK_SOURCE_XTHF + */ +__STATIC_INLINE uint32_t FL_RCC_PLL_GetClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCR, RCC_PLLCR_INSEL_Msk)); +} + +/** + * @brief Set PLL Multiplier + * @rmtoll PLLCR DB FL_RCC_PLL_WriteMultiplier + * @param multiplier + * @retval None + */ +__STATIC_INLINE void FL_RCC_PLL_WriteMultiplier(uint32_t multiplier) +{ + MODIFY_REG(RCC->PLLCR, (0x7fU << 16U), (multiplier << 16U)); +} + +/** + * @brief Get PLL Multiplier Setting + * @rmtoll PLLCR DB FL_RCC_PLL_ReadMultiplier + * @retval + */ +__STATIC_INLINE uint32_t FL_RCC_PLL_ReadMultiplier(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCR, (0x7fU << 16U)) >> 16U); +} + +/** + * @brief Set PLL Prescaler + * @rmtoll PLLCR REFPRSC FL_RCC_PLL_SetPrescaler + * @param prescaler This parameter can be one of the following values: + * @arg @ref FL_RCC_PLL_PSC_DIV1 + * @arg @ref FL_RCC_PLL_PSC_DIV2 + * @arg @ref FL_RCC_PLL_PSC_DIV4 + * @arg @ref FL_RCC_PLL_PSC_DIV8 + * @arg @ref FL_RCC_PLL_PSC_DIV12 + * @arg @ref FL_RCC_PLL_PSC_DIV16 + * @arg @ref FL_RCC_PLL_PSC_DIV24 + * @arg @ref FL_RCC_PLL_PSC_DIV32 + * @retval None + */ +__STATIC_INLINE void FL_RCC_PLL_SetPrescaler(uint32_t prescaler) +{ + MODIFY_REG(RCC->PLLCR, RCC_PLLCR_REFPRSC_Msk, prescaler); +} + +/** + * @brief Get PLL Prescaler Setting + * @rmtoll PLLCR REFPRSC FL_RCC_PLL_GetPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_PLL_PSC_DIV1 + * @arg @ref FL_RCC_PLL_PSC_DIV2 + * @arg @ref FL_RCC_PLL_PSC_DIV4 + * @arg @ref FL_RCC_PLL_PSC_DIV8 + * @arg @ref FL_RCC_PLL_PSC_DIV12 + * @arg @ref FL_RCC_PLL_PSC_DIV16 + * @arg @ref FL_RCC_PLL_PSC_DIV24 + * @arg @ref FL_RCC_PLL_PSC_DIV32 + */ +__STATIC_INLINE uint32_t FL_RCC_PLL_GetPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCR, RCC_PLLCR_REFPRSC_Msk)); +} + +/** + * @brief Set PLL Digital Domain Output + * @rmtoll PLLCR OSEL FL_RCC_PLL_SetOutputMultiplier + * @param multiplier This parameter can be one of the following values: + * @arg @ref FL_RCC_PLL_OUTPUT_X1 + * @arg @ref FL_RCC_PLL_OUTPUT_X2 + * @retval None + */ +__STATIC_INLINE void FL_RCC_PLL_SetOutputMultiplier(uint32_t multiplier) +{ + MODIFY_REG(RCC->PLLCR, RCC_PLLCR_OSEL_Msk, multiplier); +} + +/** + * @brief Get PLL Digital Domain Output Setting + * @rmtoll PLLCR OSEL FL_RCC_PLL_GetOutputMultiplier + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_PLL_OUTPUT_X1 + * @arg @ref FL_RCC_PLL_OUTPUT_X2 + */ +__STATIC_INLINE uint32_t FL_RCC_PLL_GetOutputMultiplier(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCR, RCC_PLLCR_OSEL_Msk)); +} + +/** + * @brief Get LPOSC Enable Flag + * @rmtoll LPOSCCR LPOENB FL_RCC_LPOSC_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_LPOSC_IsEnabled(void) +{ + return (uint32_t)!(READ_BIT(RCC->LPOSCCR, RCC_LPOSCCR_LPOENB_Msk) == RCC_LPOSCCR_LPOENB_Msk); +} + +/** + * @brief Enable LPOSC On/Off in Low Power Mode + * @rmtoll LPOSCCR LPM_LPO_OFF FL_RCC_LPOSC_EnableSleepModeWork + * @retval None + */ +__STATIC_INLINE void FL_RCC_LPOSC_EnableSleepModeWork(void) +{ + CLEAR_BIT(RCC->LPOSCCR, RCC_LPOSCCR_LPM_LPO_OFF_Msk); +} + +/** + * @brief Get LPOSC On/Off Setting in Low Power Mode + * @rmtoll LPOSCCR LPM_LPO_OFF FL_RCC_LPOSC_IsEnableSleepModeWork + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_LPOSC_IsEnableSleepModeWork(void) +{ + return (uint32_t)!(READ_BIT(RCC->LPOSCCR, RCC_LPOSCCR_LPM_LPO_OFF_Msk) == RCC_LPOSCCR_LPM_LPO_OFF_Msk); +} + +/** + * @brief Disable LPOSC On/Off Setting in Low Power Mode + * @rmtoll LPOSCCR LPM_LPO_OFF FL_RCC_LPOSC_DisableSleepModeWork + * @retval None + */ +__STATIC_INLINE void FL_RCC_LPOSC_DisableSleepModeWork(void) +{ + SET_BIT(RCC->LPOSCCR, RCC_LPOSCCR_LPM_LPO_OFF_Msk); +} + +/** + * @brief Enable LPOSC Chopper + * @rmtoll LPOSCCR LPO_CHOP_EN FL_RCC_LPOSC_EnableChopper + * @retval None + */ +__STATIC_INLINE void FL_RCC_LPOSC_EnableChopper(void) +{ + SET_BIT(RCC->LPOSCCR, RCC_LPOSCCR_LPO_CHOP_EN_Msk); +} + +/** + * @brief Get LPOSC Chopper Enable Status + * @rmtoll LPOSCCR LPO_CHOP_EN FL_RCC_LPOSC_IsEnabledChopper + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_LPOSC_IsEnabledChopper(void) +{ + return (uint32_t)(READ_BIT(RCC->LPOSCCR, RCC_LPOSCCR_LPO_CHOP_EN_Msk) == RCC_LPOSCCR_LPO_CHOP_EN_Msk); +} + +/** + * @brief Disable LPOSC Chopper + * @rmtoll LPOSCCR LPO_CHOP_EN FL_RCC_LPOSC_DisableChopper + * @retval None + */ +__STATIC_INLINE void FL_RCC_LPOSC_DisableChopper(void) +{ + CLEAR_BIT(RCC->LPOSCCR, RCC_LPOSCCR_LPO_CHOP_EN_Msk); +} + +/** + * @brief Set LPOSC Frequency Trim Value + * @rmtoll LPOSCTR TRIM FL_RCC_LPOSC_WriteTrimValue + * @param value TrimValue The value of RCLP trim + * @retval None + */ +__STATIC_INLINE void FL_RCC_LPOSC_WriteTrimValue(uint32_t value) +{ + MODIFY_REG(RCC->LPOSCTR, (0xffU << 0U), (value << 0U)); +} + +/** + * @brief Get LPOSC Frequency Trim Value + * @rmtoll LPOSCTR TRIM FL_RCC_LPOSC_ReadTrimValue + * @retval The Value of RCLP trim + */ +__STATIC_INLINE uint32_t FL_RCC_LPOSC_ReadTrimValue(void) +{ + return (uint32_t)(READ_BIT(RCC->LPOSCTR, 0xffU) >> 0U); +} + +/** + * @brief Enable XTLF + * @rmtoll XTLFCR EN FL_RCC_XTLF_Enable + * @retval None + */ +__STATIC_INLINE void FL_RCC_XTLF_Enable(void) +{ + MODIFY_REG(RCC->XTLFCR, RCC_XTLFCR_EN_Msk, FL_RCC_XTLF_FDET_ENABLE); +} + +/** + * @brief Disable XTLF + * @rmtoll XTLFCR EN FL_RCC_XTLF_Disable + * @retval None + */ +__STATIC_INLINE void FL_RCC_XTLF_Disable(void) +{ + MODIFY_REG(RCC->XTLFCR, RCC_XTLFCR_EN_Msk, FL_RCC_XTLF_FDET_DISABLE); +} + +/** + * @brief Set XTLF Current + * @rmtoll XTLFCR IPW FL_RCC_XTLF_SetWorkCurrent + * @param current This parameter can be one of the following values: + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_450NA + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_400NA + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_350NA + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_300NA + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_250NA + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_200NA + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_150NA + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_100NA + * @retval None + */ +__STATIC_INLINE void FL_RCC_XTLF_SetWorkCurrent(uint32_t current) +{ + MODIFY_REG(RCC->XTLFCR, RCC_XTLFCR_IPW_Msk, current); +} + +/** + * @brief Get XTLF Current Setting + * @rmtoll XTLFCR IPW FL_RCC_XTLF_GetWorkCurrent + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_450NA + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_400NA + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_350NA + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_300NA + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_250NA + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_200NA + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_150NA + * @arg @ref FL_RCC_XTLF_WORK_CURRENT_100NA + */ +__STATIC_INLINE uint32_t FL_RCC_XTLF_GetWorkCurrent(void) +{ + return (uint32_t)(READ_BIT(RCC->XTLFCR, RCC_XTLFCR_IPW_Msk)); +} + +/** + * @brief Set XTHF Oscillation Strength + * @rmtoll XTHFCR CFG FL_RCC_XTHF_WriteDriverStrength + * @param strength + * @retval None + */ +__STATIC_INLINE void FL_RCC_XTHF_WriteDriverStrength(uint32_t strength) +{ + MODIFY_REG(RCC->XTHFCR, (0x7U << 8U), (strength << 8U)); +} + +/** + * @brief Get XTHF Oscillation Strength Setting + * @rmtoll XTHFCR CFG FL_RCC_XTHF_ReadDriverStrength + * @retval + */ +__STATIC_INLINE uint32_t FL_RCC_XTHF_ReadDriverStrength(void) +{ + return (uint32_t)(READ_BIT(RCC->XTHFCR, 0x7U) >> 8U); +} + +/** + * @brief Enable XTHF + * @rmtoll XTHFCR EN FL_RCC_XTHF_Enable + * @retval None + */ +__STATIC_INLINE void FL_RCC_XTHF_Enable(void) +{ + SET_BIT(RCC->XTHFCR, RCC_XTHFCR_EN_Msk); +} + +/** + * @brief Get XTHF Enable Status + * @rmtoll XTHFCR EN FL_RCC_XTHF_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_XTHF_IsEnabled(void) +{ + return (uint32_t)(READ_BIT(RCC->XTHFCR, RCC_XTHFCR_EN_Msk) == RCC_XTHFCR_EN_Msk); +} + +/** + * @brief Disable XTHF + * @rmtoll XTHFCR EN FL_RCC_XTHF_Disable + * @retval None + */ +__STATIC_INLINE void FL_RCC_XTHF_Disable(void) +{ + CLEAR_BIT(RCC->XTHFCR, RCC_XTHFCR_EN_Msk); +} + +/** + * @brief Set RCMF Output Prescaler + * @rmtoll RCMFCR PSC FL_RCC_RCMF_SetPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref FL_RCC_RCMF_PSC_DIV1 + * @arg @ref FL_RCC_RCMF_PSC_DIV4 + * @arg @ref FL_RCC_RCMF_PSC_DIV8 + * @arg @ref FL_RCC_RCMF_PSC_DIV16 + * @retval None + */ +__STATIC_INLINE void FL_RCC_RCMF_SetPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->RCMFCR, RCC_RCMFCR_PSC_Msk, Prescaler); +} + +/** + * @brief Get RCMF Output Prescaler Setting + * @rmtoll RCMFCR PSC FL_RCC_RCMF_GetPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_RCMF_PSC_DIV1 + * @arg @ref FL_RCC_RCMF_PSC_DIV4 + * @arg @ref FL_RCC_RCMF_PSC_DIV8 + * @arg @ref FL_RCC_RCMF_PSC_DIV16 + */ +__STATIC_INLINE uint32_t FL_RCC_RCMF_GetPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->RCMFCR, RCC_RCMFCR_PSC_Msk)); +} + +/** + * @brief Enable RCMF + * @rmtoll RCMFCR EN FL_RCC_RCMF_Enable + * @retval None + */ +__STATIC_INLINE void FL_RCC_RCMF_Enable(void) +{ + SET_BIT(RCC->RCMFCR, RCC_RCMFCR_EN_Msk); +} + +/** + * @brief Get RCMF Enable Status + * @rmtoll RCMFCR EN FL_RCC_RCMF_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_RCMF_IsEnabled(void) +{ + return (uint32_t)(READ_BIT(RCC->RCMFCR, RCC_RCMFCR_EN_Msk) == RCC_RCMFCR_EN_Msk); +} + +/** + * @brief Disable RCMF + * @rmtoll RCMFCR EN FL_RCC_RCMF_Disable + * @retval None + */ +__STATIC_INLINE void FL_RCC_RCMF_Disable(void) +{ + CLEAR_BIT(RCC->RCMFCR, RCC_RCMFCR_EN_Msk); +} + +/** + * @brief Set RCHF Freqency Trim Value + * @rmtoll RCHFTR TRIM FL_RCC_RCHF_WriteTrimValue + * @param value TrimValue The value of RCHF trim + * @retval None + */ +__STATIC_INLINE void FL_RCC_RCHF_WriteTrimValue(uint32_t value) +{ + MODIFY_REG(RCC->RCHFTR, (0x7fU << 0U), (value << 0U)); +} + +/** + * @brief Get RCHF Freqency Trim Value + * @rmtoll RCHFTR TRIM FL_RCC_RCHF_ReadTrimValue + * @retval The value of RCHF trim + */ +__STATIC_INLINE uint32_t FL_RCC_RCHF_ReadTrimValue(void) +{ + return (uint32_t)(READ_BIT(RCC->RCHFTR, 0x7fU) >> 0U); +} + +/** + * @brief Enable Group1 Periph Bus Clock + * @rmtoll PCLKCR1 FL_RCC_EnableGroup1BusClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP1_BUSCLK_LPTIM32 + * @arg @ref FL_RCC_GROUP1_BUSCLK_USB + * @arg @ref FL_RCC_GROUP1_BUSCLK_RTC + * @arg @ref FL_RCC_GROUP1_BUSCLK_PMU + * @arg @ref FL_RCC_GROUP1_BUSCLK_SCU + * @arg @ref FL_RCC_GROUP1_BUSCLK_IWDT + * @arg @ref FL_RCC_GROUP1_BUSCLK_ANAC + * @arg @ref FL_RCC_GROUP1_BUSCLK_PAD + * @arg @ref FL_RCC_GROUP1_BUSCLK_DCU + * @retval None + */ +__STATIC_INLINE void FL_RCC_EnableGroup1BusClock(uint32_t Peripheral) +{ + SET_BIT(RCC->PCLKCR1, ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Enable Group2 Periph Bus Clock + * @rmtoll PCLKCR2 FL_RCC_EnableGroup2BusClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP2_BUSCLK_CRC + * @arg @ref FL_RCC_GROUP2_BUSCLK_RNG + * @arg @ref FL_RCC_GROUP2_BUSCLK_AES + * @arg @ref FL_RCC_GROUP2_BUSCLK_LCD + * @arg @ref FL_RCC_GROUP2_BUSCLK_DMA + * @arg @ref FL_RCC_GROUP2_BUSCLK_FLASH + * @arg @ref FL_RCC_GROUP2_BUSCLK_RAMBIST + * @arg @ref FL_RCC_GROUP2_BUSCLK_WWDT + * @arg @ref FL_RCC_GROUP2_BUSCLK_ADC + * @arg @ref FL_RCC_GROUP2_BUSCLK_HDIV + * @retval None + */ +__STATIC_INLINE void FL_RCC_EnableGroup2BusClock(uint32_t Peripheral) +{ + SET_BIT(RCC->PCLKCR2, ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Enable Group3 Periph Bus Clock + * @rmtoll PCLKCR3 FL_RCC_EnableGroup3BusClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP3_BUSCLK_SPI1 + * @arg @ref FL_RCC_GROUP3_BUSCLK_SPI2 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UART0 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UART1 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UART4 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UART5 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UARTIR + * @arg @ref FL_RCC_GROUP3_BUSCLK_LPUART0 + * @arg @ref FL_RCC_GROUP3_BUSCLK_U7816 + * @arg @ref FL_RCC_GROUP3_BUSCLK_LPUART1 + * @arg @ref FL_RCC_GROUP3_BUSCLK_I2C + * @retval None + */ +__STATIC_INLINE void FL_RCC_EnableGroup3BusClock(uint32_t Peripheral) +{ + SET_BIT(RCC->PCLKCR3, ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Enable Group4 Periph Bus Clock + * @rmtoll PCLKCR4 FL_RCC_EnableGroup4BusClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP4_BUSCLK_BSTIM32 + * @arg @ref FL_RCC_GROUP4_BUSCLK_GPTIM0 + * @arg @ref FL_RCC_GROUP4_BUSCLK_GPTIM1 + * @arg @ref FL_RCC_GROUP4_BUSCLK_ATIM + * @retval None + */ +__STATIC_INLINE void FL_RCC_EnableGroup4BusClock(uint32_t Peripheral) +{ + SET_BIT(RCC->PCLKCR4, ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Disable Group1 Periph Bus Clock + * @rmtoll PCLKCR1 FL_RCC_DisableGroup1BusClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP1_BUSCLK_LPTIM32 + * @arg @ref FL_RCC_GROUP1_BUSCLK_USB + * @arg @ref FL_RCC_GROUP1_BUSCLK_RTC + * @arg @ref FL_RCC_GROUP1_BUSCLK_PMU + * @arg @ref FL_RCC_GROUP1_BUSCLK_SCU + * @arg @ref FL_RCC_GROUP1_BUSCLK_IWDT + * @arg @ref FL_RCC_GROUP1_BUSCLK_ANAC + * @arg @ref FL_RCC_GROUP1_BUSCLK_PAD + * @arg @ref FL_RCC_GROUP1_BUSCLK_DCU + * @retval None + */ +__STATIC_INLINE void FL_RCC_DisableGroup1BusClock(uint32_t Peripheral) +{ + CLEAR_BIT(RCC->PCLKCR1, ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Disable Group2 Periph Bus Clock + * @rmtoll PCLKCR2 FL_RCC_DisableGroup2BusClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP2_BUSCLK_CRC + * @arg @ref FL_RCC_GROUP2_BUSCLK_RNG + * @arg @ref FL_RCC_GROUP2_BUSCLK_AES + * @arg @ref FL_RCC_GROUP2_BUSCLK_LCD + * @arg @ref FL_RCC_GROUP2_BUSCLK_DMA + * @arg @ref FL_RCC_GROUP2_BUSCLK_FLASH + * @arg @ref FL_RCC_GROUP2_BUSCLK_RAMBIST + * @arg @ref FL_RCC_GROUP2_BUSCLK_WWDT + * @arg @ref FL_RCC_GROUP2_BUSCLK_ADC + * @arg @ref FL_RCC_GROUP2_BUSCLK_HDIV + * @retval None + */ +__STATIC_INLINE void FL_RCC_DisableGroup2BusClock(uint32_t Peripheral) +{ + CLEAR_BIT(RCC->PCLKCR2, ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Disable Group3 Periph Bus Clock + * @rmtoll PCLKCR3 FL_RCC_DisableGroup3BusClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP3_BUSCLK_SPI1 + * @arg @ref FL_RCC_GROUP3_BUSCLK_SPI2 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UART0 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UART1 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UART4 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UART5 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UARTIR + * @arg @ref FL_RCC_GROUP3_BUSCLK_LPUART0 + * @arg @ref FL_RCC_GROUP3_BUSCLK_U7816 + * @arg @ref FL_RCC_GROUP3_BUSCLK_LPUART1 + * @arg @ref FL_RCC_GROUP3_BUSCLK_I2C + * @retval None + */ +__STATIC_INLINE void FL_RCC_DisableGroup3BusClock(uint32_t Peripheral) +{ + CLEAR_BIT(RCC->PCLKCR3, ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Disable Group4 Periph Bus Clock + * @rmtoll PCLKCR4 FL_RCC_DisableGroup4BusClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP4_BUSCLK_BSTIM32 + * @arg @ref FL_RCC_GROUP4_BUSCLK_GPTIM0 + * @arg @ref FL_RCC_GROUP4_BUSCLK_GPTIM1 + * @arg @ref FL_RCC_GROUP4_BUSCLK_ATIM + * @retval None + */ +__STATIC_INLINE void FL_RCC_DisableGroup4BusClock(uint32_t Peripheral) +{ + CLEAR_BIT(RCC->PCLKCR4, ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Get Group1 Periph Bus Clock Enable Status + * @rmtoll PCLKCR1 FL_RCC_IsEnabledGroup1BusClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP1_BUSCLK_LPTIM32 + * @arg @ref FL_RCC_GROUP1_BUSCLK_USB + * @arg @ref FL_RCC_GROUP1_BUSCLK_RTC + * @arg @ref FL_RCC_GROUP1_BUSCLK_PMU + * @arg @ref FL_RCC_GROUP1_BUSCLK_SCU + * @arg @ref FL_RCC_GROUP1_BUSCLK_IWDT + * @arg @ref FL_RCC_GROUP1_BUSCLK_ANAC + * @arg @ref FL_RCC_GROUP1_BUSCLK_PAD + * @arg @ref FL_RCC_GROUP1_BUSCLK_DCU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsEnabledGroup1BusClock(uint32_t Peripheral) +{ + return (uint32_t)(READ_BIT(RCC->PCLKCR1, ((Peripheral & 0xffffffff) << 0x0U)) == ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Get Group2 Periph Bus Clock Enable Status + * @rmtoll PCLKCR2 FL_RCC_IsEnabledGroup2BusClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP2_BUSCLK_CRC + * @arg @ref FL_RCC_GROUP2_BUSCLK_RNG + * @arg @ref FL_RCC_GROUP2_BUSCLK_AES + * @arg @ref FL_RCC_GROUP2_BUSCLK_LCD + * @arg @ref FL_RCC_GROUP2_BUSCLK_DMA + * @arg @ref FL_RCC_GROUP2_BUSCLK_FLASH + * @arg @ref FL_RCC_GROUP2_BUSCLK_RAMBIST + * @arg @ref FL_RCC_GROUP2_BUSCLK_WWDT + * @arg @ref FL_RCC_GROUP2_BUSCLK_ADC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsEnabledGroup2BusClock(uint32_t Peripheral) +{ + return (uint32_t)(READ_BIT(RCC->PCLKCR2, ((Peripheral & 0xffffffff) << 0x0U)) == ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Get Group3 Periph Bus Clock Enable Status + * @rmtoll PCLKCR3 FL_RCC_IsEnabledGroup3BusClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP3_BUSCLK_SPI1 + * @arg @ref FL_RCC_GROUP3_BUSCLK_SPI2 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UART0 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UART1 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UART4 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UART5 + * @arg @ref FL_RCC_GROUP3_BUSCLK_UARTIR + * @arg @ref FL_RCC_GROUP3_BUSCLK_LPUART0 + * @arg @ref FL_RCC_GROUP3_BUSCLK_U7816 + * @arg @ref FL_RCC_GROUP3_BUSCLK_LPUART1 + * @arg @ref FL_RCC_GROUP3_BUSCLK_I2C + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsEnabledGroup3BusClock(uint32_t Peripheral) +{ + return (uint32_t)(READ_BIT(RCC->PCLKCR3, ((Peripheral & 0xffffffff) << 0x0U)) == ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Get Group4 Periph Bus Clock Enable Status + * @rmtoll PCLKCR4 FL_RCC_IsEnabledGroup4BusClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP4_BUSCLK_BSTIM32 + * @arg @ref FL_RCC_GROUP4_BUSCLK_GPTIM0 + * @arg @ref FL_RCC_GROUP4_BUSCLK_GPTIM1 + * @arg @ref FL_RCC_GROUP4_BUSCLK_ATIM + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsEnabledGroup4BusClock(uint32_t Peripheral) +{ + return (uint32_t)(READ_BIT(RCC->PCLKCR4, ((Peripheral & 0xffffffff) << 0x0U)) == ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Enable Group1 Periph Operation Clock + * @rmtoll OPCCR1 FL_RCC_EnableGroup1OperationClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP1_OPCLK_EXTI + * @arg @ref FL_RCC_GROUP1_OPCLK_LPUART1 + * @arg @ref FL_RCC_GROUP1_OPCLK_LPUART0 + * @arg @ref FL_RCC_GROUP1_OPCLK_I2C + * @arg @ref FL_RCC_GROUP1_OPCLK_ATIM + * @arg @ref FL_RCC_GROUP1_OPCLK_UART1 + * @arg @ref FL_RCC_GROUP1_OPCLK_UART0 + * @retval None + */ +__STATIC_INLINE void FL_RCC_EnableGroup1OperationClock(uint32_t Peripheral) +{ + SET_BIT(RCC->OPCCR1, ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Enable Group2 Periph Operation Clock + * @rmtoll OPCCR2 FL_RCC_EnableGroup2OperationClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP2_OPCLK_FLASH + * @arg @ref FL_RCC_GROUP2_OPCLK_RNG + * @arg @ref FL_RCC_GROUP2_OPCLK_ADC + * @arg @ref FL_RCC_GROUP2_OPCLK_LPTIM32 + * @arg @ref FL_RCC_GROUP2_OPCLK_BSTIM32 + * @retval None + */ +__STATIC_INLINE void FL_RCC_EnableGroup2OperationClock(uint32_t Peripheral) +{ + SET_BIT(RCC->OPCCR2, ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Disable Group1 Periph Operation Clock + * @rmtoll OPCCR1 FL_RCC_DisableGroup1OperationClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP1_OPCLK_EXTI + * @arg @ref FL_RCC_GROUP1_OPCLK_LPUART1 + * @arg @ref FL_RCC_GROUP1_OPCLK_LPUART0 + * @arg @ref FL_RCC_GROUP1_OPCLK_I2C + * @arg @ref FL_RCC_GROUP1_OPCLK_ATIM + * @arg @ref FL_RCC_GROUP1_OPCLK_UART1 + * @retval None + */ +__STATIC_INLINE void FL_RCC_DisableGroup1OperationClock(uint32_t Peripheral) +{ + CLEAR_BIT(RCC->OPCCR1, ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Disable Group2 Periph Operation Clock + * @rmtoll OPCCR2 FL_RCC_DisableGroup2OperationClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP2_OPCLK_FLASH + * @arg @ref FL_RCC_GROUP2_OPCLK_RNG + * @arg @ref FL_RCC_GROUP2_OPCLK_ADC + * @arg @ref FL_RCC_GROUP2_OPCLK_LPTIM32 + * @arg @ref FL_RCC_GROUP2_OPCLK_BSTIM32 + * @retval None + */ +__STATIC_INLINE void FL_RCC_DisableGroup2OperationClock(uint32_t Peripheral) +{ + CLEAR_BIT(RCC->OPCCR2, ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Get Group1 Periph Operation Clock Enable Status + * @rmtoll OPCCR1 FL_RCC_IsEnabledGroup1OperationClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP1_OPCLK_EXTI + * @arg @ref FL_RCC_GROUP1_OPCLK_LPUART1 + * @arg @ref FL_RCC_GROUP1_OPCLK_LPUART0 + * @arg @ref FL_RCC_GROUP1_OPCLK_I2C + * @arg @ref FL_RCC_GROUP1_OPCLK_ATIM + * @arg @ref FL_RCC_GROUP1_OPCLK_UART1 + * @arg @ref FL_RCC_GROUP1_OPCLK_UART0 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsEnabledGroup1OperationClock(uint32_t Peripheral) +{ + return (uint32_t)(READ_BIT(RCC->OPCCR1, ((Peripheral & 0xffffffff) << 0x0U)) == ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Get Group2 Periph Operation Clock Enable Status + * @rmtoll OPCCR2 FL_RCC_IsEnabledGroup2OperationClock + * @param Peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_GROUP2_OPCLK_FLASH + * @arg @ref FL_RCC_GROUP2_OPCLK_RNG + * @arg @ref FL_RCC_GROUP2_OPCLK_ADC + * @arg @ref FL_RCC_GROUP2_OPCLK_LPTIM32 + * @arg @ref FL_RCC_GROUP2_OPCLK_BSTIM32 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsEnabledGroup2OperationClock(uint32_t Peripheral) +{ + return (uint32_t)(READ_BIT(RCC->OPCCR2, ((Peripheral & 0xffffffff) << 0x0U)) == ((Peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Set EXTI Clock Source + * @rmtoll OPCCR1 EXTICKS FL_RCC_SetEXTIClockSource + * @param clock This parameter can be one of the following values: + * @arg @ref FL_RCC_EXTI_CLK_SOURCE_LSCLK + * @arg @ref FL_RCC_EXTI_CLK_SOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetEXTIClockSource(uint32_t clock) +{ + MODIFY_REG(RCC->OPCCR1, RCC_OPCCR1_EXTICKS_Msk, clock); +} + +/** + * @brief Get EXTI Clock Source Setting + * @rmtoll OPCCR1 EXTICKS FL_RCC_GetEXTIClockSource + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_EXTI_CLK_SOURCE_LSCLK + * @arg @ref FL_RCC_EXTI_CLK_SOURCE_HCLK + */ +__STATIC_INLINE uint32_t FL_RCC_GetEXTIClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->OPCCR1, RCC_OPCCR1_EXTICKS_Msk)); +} + +/** + * @brief Set LPUART1 Clock Source + * @rmtoll OPCCR1 LPUART1CKS FL_RCC_SetLPUART1ClockSource + * @param clock This parameter can be one of the following values: + * @arg @ref FL_RCC_LPUART1_CLK_SOURCE_LSCLK + * @arg @ref FL_RCC_LPUART1_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_LPUART1_CLK_SOURCE_RCMF + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetLPUART1ClockSource(uint32_t clock) +{ + MODIFY_REG(RCC->OPCCR1, RCC_OPCCR1_LPUART1CKS_Msk, clock); +} + +/** + * @brief Get LPUART1 Clock Source Setting + * @rmtoll OPCCR1 LPUART1CKS FL_RCC_GetLPUART1ClockSource + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_LPUART1_CLK_SOURCE_LSCLK + * @arg @ref FL_RCC_LPUART1_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_LPUART1_CLK_SOURCE_RCMF + */ +__STATIC_INLINE uint32_t FL_RCC_GetLPUART1ClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->OPCCR1, RCC_OPCCR1_LPUART1CKS_Msk)); +} + +/** + * @brief Set LPUART0 Clock Source + * @rmtoll OPCCR1 LPUART0CKS FL_RCC_SetLPUART0ClockSource + * @param clock This parameter can be one of the following values: + * @arg @ref FL_RCC_LPUART0_CLK_SOURCE_LSCLK + * @arg @ref FL_RCC_LPUART0_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_LPUART0_CLK_SOURCE_RCMF + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetLPUART0ClockSource(uint32_t clock) +{ + MODIFY_REG(RCC->OPCCR1, RCC_OPCCR1_LPUART0CKS_Msk, clock); +} + +/** + * @brief Get LPUART0 Clock Source Setting + * @rmtoll OPCCR1 LPUART0CKS FL_RCC_GetLPUART0ClockSource + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_LPUART0_CLK_SOURCE_LSCLK + * @arg @ref FL_RCC_LPUART0_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_LPUART0_CLK_SOURCE_RCMF + */ +__STATIC_INLINE uint32_t FL_RCC_GetLPUART0ClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->OPCCR1, RCC_OPCCR1_LPUART0CKS_Msk)); +} + +/** + * @brief Set I2C Clock Source + * @rmtoll OPCCR1 I2CCKS FL_RCC_SetI2CClockSource + * @param clock This parameter can be one of the following values: + * @arg @ref FL_RCC_I2C_CLK_SOURCE_APB1CLK + * @arg @ref FL_RCC_I2C_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_I2C_CLK_SOURCE_SYSCLK + * @arg @ref FL_RCC_I2C_CLK_SOURCE_RCMF_PSC + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetI2CClockSource(uint32_t clock) +{ + MODIFY_REG(RCC->OPCCR1, RCC_OPCCR1_I2CCKS_Msk, clock); +} + +/** + * @brief Get I2C Clock Source Setting + * @rmtoll OPCCR1 I2CCKS FL_RCC_GetI2CClockSource + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_I2C_CLK_SOURCE_APB1CLK + * @arg @ref FL_RCC_I2C_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_I2C_CLK_SOURCE_SYSCLK + * @arg @ref FL_RCC_I2C_CLK_SOURCE_RCMF_PSC + */ +__STATIC_INLINE uint32_t FL_RCC_GetI2CClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->OPCCR1, RCC_OPCCR1_I2CCKS_Msk)); +} + +/** + * @brief Set ATIM Clock Source + * @rmtoll OPCCR1 ATCKS FL_RCC_SetATIMClockSource + * @param clock This parameter can be one of the following values: + * @arg @ref FL_RCC_ATIM_CLK_SOURCE_APB2CLK + * @arg @ref FL_RCC_ATIM_CLK_SOURCE_USBPHYBCK120M + * @arg @ref FL_RCC_ATIM_CLK_SOURCE_PLLx2 + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetATIMClockSource(uint32_t clock) +{ + MODIFY_REG(RCC->OPCCR1, RCC_OPCCR1_ATCKS_Msk, clock); +} + +/** + * @brief Get ATIM Clock Source Setting + * @rmtoll OPCCR1 ATCKS FL_RCC_GetATIMClockSource + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_ATIM_CLK_SOURCE_APB2CLK + * @arg @ref FL_RCC_ATIM_CLK_SOURCE_USBPHYBCK120M + * @arg @ref FL_RCC_ATIM_CLK_SOURCE_PLLx2 + */ +__STATIC_INLINE uint32_t FL_RCC_GetATIMClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->OPCCR1, RCC_OPCCR1_ATCKS_Msk)); +} + +/** + * @brief Set UART1 Clock Source + * @rmtoll OPCCR1 UART1CKS FL_RCC_SetUART1ClockSource + * @param clock This parameter can be one of the following values: + * @arg @ref FL_RCC_UART1_CLK_SOURCE_APB1CLK + * @arg @ref FL_RCC_UART1_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_UART1_CLK_SOURCE_SYSCLK + * @arg @ref FL_RCC_UART1_CLK_SOURCE_RCMF_PSC + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetUART1ClockSource(uint32_t clock) +{ + MODIFY_REG(RCC->OPCCR1, RCC_OPCCR1_UART1CKS_Msk, clock); +} + +/** + * @brief Get UART1 Clock Source Setting + * @rmtoll OPCCR1 UART1CKS FL_RCC_GetUART1ClockSource + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_UART1_CLK_SOURCE_APB1CLK + * @arg @ref FL_RCC_UART1_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_UART1_CLK_SOURCE_SYSCLK + * @arg @ref FL_RCC_UART1_CLK_SOURCE_RCMF_PSC + */ +__STATIC_INLINE uint32_t FL_RCC_GetUART1ClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->OPCCR1, RCC_OPCCR1_UART1CKS_Msk)); +} + +/** + * @brief Set UART0 Clock Source + * @rmtoll OPCCR1 UART0CKS FL_RCC_SetUART0ClockSource + * @param clock This parameter can be one of the following values: + * @arg @ref FL_RCC_UART0_CLK_SOURCE_APB1CLK + * @arg @ref FL_RCC_UART0_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_UART0_CLK_SOURCE_SYSCLK + * @arg @ref FL_RCC_UART0_CLK_SOURCE_RCMF_PSC + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetUART0ClockSource(uint32_t clock) +{ + MODIFY_REG(RCC->OPCCR1, RCC_OPCCR1_UART0CKS_Msk, clock); +} + +/** + * @brief Get UART0 Clock Source Setting + * @rmtoll OPCCR1 UART0CKS FL_RCC_GetUART0ClockSource + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_UART0_CLK_SOURCE_APB1CLK + * @arg @ref FL_RCC_UART0_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_UART0_CLK_SOURCE_SYSCLK + * @arg @ref FL_RCC_UART0_CLK_SOURCE_RCMF_PSC + */ +__STATIC_INLINE uint32_t FL_RCC_GetUART0ClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->OPCCR1, RCC_OPCCR1_UART0CKS_Msk)); +} + +/** + * @brief Set RNG Prescaler + * @rmtoll OPCCR2 RNGPRSC FL_RCC_SetRNGPrescaler + * @param prescaler This parameter can be one of the following values: + * @arg @ref FL_RCC_RNG_PSC_DIV1 + * @arg @ref FL_RCC_RNG_PSC_DIV2 + * @arg @ref FL_RCC_RNG_PSC_DIV4 + * @arg @ref FL_RCC_RNG_PSC_DIV8 + * @arg @ref FL_RCC_RNG_PSC_DIV16 + * @arg @ref FL_RCC_RNG_PSC_DIV32 + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetRNGPrescaler(uint32_t prescaler) +{ + MODIFY_REG(RCC->OPCCR2, RCC_OPCCR2_RNGPRSC_Msk, prescaler); +} + +/** + * @brief Get RNG Prescaler Setting + * @rmtoll OPCCR2 RNGPRSC FL_RCC_GetRNGPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_RNG_PSC_DIV1 + * @arg @ref FL_RCC_RNG_PSC_DIV2 + * @arg @ref FL_RCC_RNG_PSC_DIV4 + * @arg @ref FL_RCC_RNG_PSC_DIV8 + * @arg @ref FL_RCC_RNG_PSC_DIV16 + * @arg @ref FL_RCC_RNG_PSC_DIV32 + */ +__STATIC_INLINE uint32_t FL_RCC_GetRNGPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->OPCCR2, RCC_OPCCR2_RNGPRSC_Msk)); +} + +/** + * @brief Set ADC Prescaler + * @rmtoll OPCCR2 ADCPRSC FL_RCC_SetADCPrescaler + * @param prescaler This parameter can be one of the following values: + * @arg @ref FL_RCC_ADC_PSC_DIV1 + * @arg @ref FL_RCC_ADC_PSC_DIV2 + * @arg @ref FL_RCC_ADC_PSC_DIV4 + * @arg @ref FL_RCC_ADC_PSC_DIV8 + * @arg @ref FL_RCC_ADC_PSC_DIV16 + * @arg @ref FL_RCC_ADC_PSC_DIV32 + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetADCPrescaler(uint32_t prescaler) +{ + MODIFY_REG(RCC->OPCCR2, RCC_OPCCR2_ADCPRSC_Msk, prescaler); +} + +/** + * @brief Get ADC Prescaler Setting + * @rmtoll OPCCR2 ADCPRSC FL_RCC_GetADCPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_ADC_PSC_DIV1 + * @arg @ref FL_RCC_ADC_PSC_DIV2 + * @arg @ref FL_RCC_ADC_PSC_DIV4 + * @arg @ref FL_RCC_ADC_PSC_DIV8 + * @arg @ref FL_RCC_ADC_PSC_DIV16 + * @arg @ref FL_RCC_ADC_PSC_DIV32 + */ +__STATIC_INLINE uint32_t FL_RCC_GetADCPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->OPCCR2, RCC_OPCCR2_ADCPRSC_Msk)); +} + +/** + * @brief Set ADC Clock Source + * @rmtoll OPCCR2 ADCCKS FL_RCC_SetADCClockSource + * @param clock This parameter can be one of the following values: + * @arg @ref FL_RCC_ADC_CLK_SOURCE_RCMF_PSC + * @arg @ref FL_RCC_ADC_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_ADC_CLK_SOURCE_XTHF + * @arg @ref FL_RCC_ADC_CLK_SOURCE_PLL + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetADCClockSource(uint32_t clock) +{ + MODIFY_REG(RCC->OPCCR2, RCC_OPCCR2_ADCCKS_Msk, clock); +} + +/** + * @brief Get ADC Clock Source Setting + * @rmtoll OPCCR2 ADCCKS FL_RCC_GetADCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_ADC_CLK_SOURCE_RCMF_PSC + * @arg @ref FL_RCC_ADC_CLK_SOURCE_RCHF + * @arg @ref FL_RCC_ADC_CLK_SOURCE_XTHF + * @arg @ref FL_RCC_ADC_CLK_SOURCE_PLL + */ +__STATIC_INLINE uint32_t FL_RCC_GetADCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->OPCCR2, RCC_OPCCR2_ADCCKS_Msk)); +} + +/** + * @brief Set LPTIM Clock Source + * @rmtoll OPCCR2 LPT32CKS FL_RCC_SetLPTIM32ClockSource + * @param clock This parameter can be one of the following values: + * @arg @ref FL_RCC_LPTIM32_CLK_SOURCE_APB1CLK + * @arg @ref FL_RCC_LPTIM32_CLK_SOURCE_LSCLK + * @arg @ref FL_RCC_LPTIM32_CLK_SOURCE_RCLP + * @arg @ref FL_RCC_LPTIM32_CLK_SOURCE_RCMF_PSC + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetLPTIM32ClockSource(uint32_t clock) +{ + MODIFY_REG(RCC->OPCCR2, RCC_OPCCR2_LPT32CKS_Msk, clock); +} + +/** + * @brief Get LPTIM Clock Source Setting + * @rmtoll OPCCR2 LPT32CKS FL_RCC_GetLPTIM32ClockSource + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_LPTIM32_CLK_SOURCE_APB1CLK + * @arg @ref FL_RCC_LPTIM32_CLK_SOURCE_LSCLK + * @arg @ref FL_RCC_LPTIM32_CLK_SOURCE_RCLP + * @arg @ref FL_RCC_LPTIM32_CLK_SOURCE_RCMF_PSC + */ +__STATIC_INLINE uint32_t FL_RCC_GetLPTIM32ClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->OPCCR2, RCC_OPCCR2_LPT32CKS_Msk)); +} + +/** + * @brief Set BSTIM Clock Source + * @rmtoll OPCCR2 BT32CKS FL_RCC_SetBSTIM32ClockSource + * @param clock This parameter can be one of the following values: + * @arg @ref FL_RCC_BSTIM32_CLK_SOURCE_APB1CLK + * @arg @ref FL_RCC_BSTIM32_CLK_SOURCE_LSCLK + * @arg @ref FL_RCC_BSTIM32_CLK_SOURCE_RCLP + * @arg @ref FL_RCC_BSTIM32_CLK_SOURCE_RCMF_PSC + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetBSTIM32ClockSource(uint32_t clock) +{ + MODIFY_REG(RCC->OPCCR2, RCC_OPCCR2_BT32CKS_Msk, clock); +} + +/** + * @brief Get BSTIM Clock Source Setting + * @rmtoll OPCCR2 BT32CKS FL_RCC_GetBSTIM32ClockSource + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_BSTIM32_CLK_SOURCE_APB1CLK + * @arg @ref FL_RCC_BSTIM32_CLK_SOURCE_LSCLK + * @arg @ref FL_RCC_BSTIM32_CLK_SOURCE_RCLP + * @arg @ref FL_RCC_BSTIM32_CLK_SOURCE_RCMF_PSC + */ +__STATIC_INLINE uint32_t FL_RCC_GetBSTIM32ClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->OPCCR2, RCC_OPCCR2_BT32CKS_Msk)); +} + +/** + * @brief Set AHB Master Priority + * @rmtoll AHBMCR MPRIL FL_RCC_SetAHBMasterPriority + * @param priority This parameter can be one of the following values: + * @arg @ref FL_RCC_AHB_MASTER_PRIORITY_DMA_FIRST + * @arg @ref FL_RCC_AHB_MASTER_PRIORITY_CPU_FIRST + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetAHBMasterPriority(uint32_t priority) +{ + MODIFY_REG(RCC->AHBMCR, RCC_AHBMCR_MPRIL_Msk, priority); +} + +/** + * @brief Get AHB Master Priority Setting + * @rmtoll AHBMCR MPRIL FL_RCC_GetAHBMasterPriority + * @retval Returned value can be one of the following values: + * @arg @ref FL_RCC_AHB_MASTER_PRIORITY_DMA_FIRST + * @arg @ref FL_RCC_AHB_MASTER_PRIORITY_CPU_FIRST + */ +__STATIC_INLINE uint32_t FL_RCC_GetAHBMasterPriority(void) +{ + return (uint32_t)(READ_BIT(RCC->AHBMCR, RCC_AHBMCR_MPRIL_Msk)); +} + +/** + * @brief Set LSCLK Clock Source + * @rmtoll LSCLKSEL SEL FL_RCC_SetLSCLKClockSource + * @param clock This parameter can be one of the following values: + * @arg @ref FL_RCC_LSCLK_CLK_SOURCE_RCLP + * @arg @ref FL_RCC_LSCLK_CLK_SOURCE_XTLF + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetLSCLKClockSource(uint32_t clock) +{ + MODIFY_REG(RCC->LSCLKSEL, RCC_LSCLKSEL_SEL_Msk, clock); +} + +/** + * @brief Get LockUp Reset Enable Status + * @rmtoll LKPCR RST_EN FL_RCC_IsEnabledLockUpReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsEnabledLockUpReset(void) +{ + return (uint32_t)(READ_BIT(RCC->LKPCR, RCC_LKPCR_RST_EN_Msk) == RCC_LKPCR_RST_EN_Msk); +} + +/** + * @brief Disable LockUp Reset + * @rmtoll LKPCR RST_EN FL_RCC_DisableLockUpReset + * @retval None + */ +__STATIC_INLINE void FL_RCC_DisableLockUpReset(void) +{ + CLEAR_BIT(RCC->LKPCR, RCC_LKPCR_RST_EN_Msk); +} + +/** + * @brief Enable LockUp Reset + * @rmtoll LKPCR RST_EN FL_RCC_EnableLockUpReset + * @retval None + */ +__STATIC_INLINE void FL_RCC_EnableLockUpReset(void) +{ + SET_BIT(RCC->LKPCR, RCC_LKPCR_RST_EN_Msk); +} + +/** + * @brief SoftReset Chip + * @rmtoll SOFTRST FL_RCC_SetSoftReset + * @retval None + */ +__STATIC_INLINE void FL_RCC_SetSoftReset(void) +{ + WRITE_REG(RCC->SOFTRST, FL_RCC_SOFTWARE_RESET_KEY); +} + +/** + * @brief Get MDFN Reset Flag + * @rmtoll RSTFR MDFN_FLAG FL_RCC_IsActiveFlag_MDF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsActiveFlag_MDF(void) +{ + return (uint32_t)(READ_BIT(RCC->RSTFR, RCC_RSTFR_MDFN_FLAG_Msk) == (RCC_RSTFR_MDFN_FLAG_Msk)); +} + +/** + * @brief Clear MDFN Reset Flag + * @rmtoll RSTFR MDFN_FLAG FL_RCC_ClearFlag_MDF + * @retval None + */ +__STATIC_INLINE void FL_RCC_ClearFlag_MDF(void) +{ + WRITE_REG(RCC->RSTFR, RCC_RSTFR_MDFN_FLAG_Msk); +} + +/** + * @brief Get NRST Reset Flag + * @rmtoll RSTFR NRSTN_FLAG FL_RCC_IsActiveFlag_NRSTN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsActiveFlag_NRSTN(void) +{ + return (uint32_t)(READ_BIT(RCC->RSTFR, RCC_RSTFR_NRSTN_FLAG_Msk) == (RCC_RSTFR_NRSTN_FLAG_Msk)); +} + +/** + * @brief Clear NRST Reset Flag + * @rmtoll RSTFR NRSTN_FLAG FL_RCC_ClearFlag_NRSTN + * @retval None + */ +__STATIC_INLINE void FL_RCC_ClearFlag_NRSTN(void) +{ + WRITE_REG(RCC->RSTFR, RCC_RSTFR_NRSTN_FLAG_Msk); +} + +/** + * @brief Get TESTN Reset Flag + * @rmtoll RSTFR TESTN_FLAG FL_RCC_IsActiveFlag_TESTN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsActiveFlag_TESTN(void) +{ + return (uint32_t)(READ_BIT(RCC->RSTFR, RCC_RSTFR_TESTN_FLAG_Msk) == (RCC_RSTFR_TESTN_FLAG_Msk)); +} + +/** + * @brief Clear TESTN Reset Flag + * @rmtoll RSTFR TESTN_FLAG FL_RCC_ClearFlag_TESTN + * @retval None + */ +__STATIC_INLINE void FL_RCC_ClearFlag_TESTN(void) +{ + WRITE_REG(RCC->RSTFR, RCC_RSTFR_TESTN_FLAG_Msk); +} + +/** + * @brief Get Power Up Reset Flag + * @rmtoll RSTFR PORN_FLAG FL_RCC_IsActiveFlag_PORN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsActiveFlag_PORN(void) +{ + return (uint32_t)(READ_BIT(RCC->RSTFR, RCC_RSTFR_PORN_FLAG_Msk) == (RCC_RSTFR_PORN_FLAG_Msk)); +} + +/** + * @brief Clear Power Up Reset Flag + * @rmtoll RSTFR PORN_FLAG FL_RCC_ClearFlag_PORN + * @retval None + */ +__STATIC_INLINE void FL_RCC_ClearFlag_PORN(void) +{ + WRITE_REG(RCC->RSTFR, RCC_RSTFR_PORN_FLAG_Msk); +} + +/** + * @brief Get Power Down Reset Flag + * @rmtoll RSTFR PDRN_FLAG FL_RCC_IsActiveFlag_PDRN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsActiveFlag_PDRN(void) +{ + return (uint32_t)(READ_BIT(RCC->RSTFR, RCC_RSTFR_PDRN_FLAG_Msk) == (RCC_RSTFR_PDRN_FLAG_Msk)); +} + +/** + * @brief Clear Power Down Reset Flag + * @rmtoll RSTFR PDRN_FLAG FL_RCC_ClearFlag_PDRN + * @retval None + */ +__STATIC_INLINE void FL_RCC_ClearFlag_PDRN(void) +{ + WRITE_REG(RCC->RSTFR, RCC_RSTFR_PDRN_FLAG_Msk); +} + +/** + * @brief Get Software Reset Flag + * @rmtoll RSTFR SOFTN_FLAG FL_RCC_IsActiveFlag_SOFTN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsActiveFlag_SOFTN(void) +{ + return (uint32_t)(READ_BIT(RCC->RSTFR, RCC_RSTFR_SOFTN_FLAG_Msk) == (RCC_RSTFR_SOFTN_FLAG_Msk)); +} + +/** + * @brief Clear Software Reset Flag + * @rmtoll RSTFR SOFTN_FLAG FL_RCC_ClearFlag_SOFTN + * @retval None + */ +__STATIC_INLINE void FL_RCC_ClearFlag_SOFTN(void) +{ + WRITE_REG(RCC->RSTFR, RCC_RSTFR_SOFTN_FLAG_Msk); +} + +/** + * @brief Get IWDT Reset Flag + * @rmtoll RSTFR IWDTN_FLAG FL_RCC_IsActiveFlag_IWDTN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsActiveFlag_IWDTN(void) +{ + return (uint32_t)(READ_BIT(RCC->RSTFR, RCC_RSTFR_IWDTN_FLAG_Msk) == (RCC_RSTFR_IWDTN_FLAG_Msk)); +} + +/** + * @brief Clear IWDT Reset Flag + * @rmtoll RSTFR IWDTN_FLAG FL_RCC_ClearFlag_IWDTN + * @retval None + */ +__STATIC_INLINE void FL_RCC_ClearFlag_IWDTN(void) +{ + WRITE_REG(RCC->RSTFR, RCC_RSTFR_IWDTN_FLAG_Msk); +} + +/** + * @brief Get WWDT Reset Flag + * @rmtoll RSTFR WWDTN_FLAG FL_RCC_IsActiveFlag_WWDTN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsActiveFlag_WWDTN(void) +{ + return (uint32_t)(READ_BIT(RCC->RSTFR, RCC_RSTFR_WWDTN_FLAG_Msk) == (RCC_RSTFR_WWDTN_FLAG_Msk)); +} + +/** + * @brief Clear WWDT Reset Flag + * @rmtoll RSTFR WWDTN_FLAG FL_RCC_ClearFlag_WWDTN + * @retval None + */ +__STATIC_INLINE void FL_RCC_ClearFlag_WWDTN(void) +{ + WRITE_REG(RCC->RSTFR, RCC_RSTFR_WWDTN_FLAG_Msk); +} + +/** + * @brief Get LockUp Reset Flag + * @rmtoll RSTFR LKUPN_FLAG FL_RCC_IsActiveFlag_LKUPN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsActiveFlag_LKUPN(void) +{ + return (uint32_t)(READ_BIT(RCC->RSTFR, RCC_RSTFR_LKUPN_FLAG_Msk) == (RCC_RSTFR_LKUPN_FLAG_Msk)); +} + +/** + * @brief Clear LockUp Reset Flag + * @rmtoll RSTFR LKUPN_FLAG FL_RCC_ClearFlag_LKUPN + * @retval None + */ +__STATIC_INLINE void FL_RCC_ClearFlag_LKUPN(void) +{ + WRITE_REG(RCC->RSTFR, RCC_RSTFR_LKUPN_FLAG_Msk); +} + +/** + * @brief Get NVIC Reset Flag + * @rmtoll RSTFR NVICN_FLAG FL_RCC_IsActiveFlag_NVICN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RCC_IsActiveFlag_NVICN(void) +{ + return (uint32_t)(READ_BIT(RCC->RSTFR, RCC_RSTFR_NVICN_FLAG_Msk) == (RCC_RSTFR_NVICN_FLAG_Msk)); +} + +/** + * @brief Clear NVIC Reset Flag + * @rmtoll RSTFR NVICN_FLAG FL_RCC_ClearFlag_NVICN + * @retval None + */ +__STATIC_INLINE void FL_RCC_ClearFlag_NVICN(void) +{ + WRITE_REG(RCC->RSTFR, RCC_RSTFR_NVICN_FLAG_Msk); +} + +/** + * @brief Disable Peripheral Reset + * @rmtoll PRSTEN FL_RCC_DisablePeripheralReset + * @retval None + */ +__STATIC_INLINE void FL_RCC_DisablePeripheralReset(void) +{ + WRITE_REG(RCC->PRSTEN, (~FL_RCC_PERIPHERAL_RESET_KEY)); +} + +/** + * @brief Enable Peripheral Reset + * @rmtoll PRSTEN FL_RCC_EnablePeripheralReset + * @retval None + */ +__STATIC_INLINE void FL_RCC_EnablePeripheralReset(void) +{ + WRITE_REG(RCC->PRSTEN, FL_RCC_PERIPHERAL_RESET_KEY); +} + +/** + * @brief Enable AHB Peripheral Reset + * @rmtoll AHBRSTCR FL_RCC_EnableResetAHBPeripheral + * @param peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_RSTAHB_DMA + * @arg @ref FL_RCC_RSTAHB_USB + * @retval None + */ +__STATIC_INLINE void FL_RCC_EnableResetAHBPeripheral(uint32_t peripheral) +{ + SET_BIT(RCC->AHBRSTCR, ((peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Enable APB1 Peripheral Reset + * @rmtoll APBRSTCR1 FL_RCC_EnableResetAPB1Peripheral + * @param peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_RSTAPB_UART5 + * @arg @ref FL_RCC_RSTAPB_UART4 + * @arg @ref FL_RCC_RSTAPB_GPTIM1 + * @arg @ref FL_RCC_RSTAPB_GPTIM0 + * @arg @ref FL_RCC_RSTAPB_LCD + * @arg @ref FL_RCC_RSTAPB_U7816 + * @arg @ref FL_RCC_RSTAPB_SPI2 + * @arg @ref FL_RCC_RSTAPB_LPUART0 + * @arg @ref FL_RCC_RSTAPB_I2C + * @arg @ref FL_RCC_RSTAPB_LPTIM32 + * @retval None + */ +__STATIC_INLINE void FL_RCC_EnableResetAPB1Peripheral(uint32_t peripheral) +{ + SET_BIT(RCC->APBRSTCR1, ((peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Enable APB2 Peripheral Reset + * @rmtoll APBRSTCR2 FL_RCC_EnableResetAPB2Peripheral + * @param peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_RSTAPB_ATIM + * @arg @ref FL_RCC_RSTAPB_BSTIM32 + * @arg @ref FL_RCC_RSTAPB_ADCCR + * @arg @ref FL_RCC_RSTAPB_ADC + * @arg @ref FL_RCC_RSTAPB_OPA + * @arg @ref FL_RCC_RSTAPB_DIVAS + * @arg @ref FL_RCC_RSTAPB_AES + * @arg @ref FL_RCC_RSTAPB_CRC + * @arg @ref FL_RCC_RSTAPB_RNG + * @arg @ref FL_RCC_RSTAPB_UART1 + * @arg @ref FL_RCC_RSTAPB_UART0 + * @arg @ref FL_RCC_RSTAPB_SPI1 + * @arg @ref FL_RCC_RSTAPB_UCIR + * @arg @ref FL_RCC_RSTAPB_LPUART1 + * @retval None + */ +__STATIC_INLINE void FL_RCC_EnableResetAPB2Peripheral(uint32_t peripheral) +{ + SET_BIT(RCC->APBRSTCR2, ((peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Disable AHB Peripheral Reset + * @rmtoll AHBRSTCR FL_RCC_DisableResetAHBPeripheral + * @param peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_RSTAHB_DMA + * @arg @ref FL_RCC_RSTAHB_USB + * @retval None + */ +__STATIC_INLINE void FL_RCC_DisableResetAHBPeripheral(uint32_t peripheral) +{ + CLEAR_BIT(RCC->AHBRSTCR, ((peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Disable APB1 Peripheral Reset + * @rmtoll APBRSTCR1 FL_RCC_DisableResetAPB1Peripheral + * @param peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_RSTAPB_UART5 + * @arg @ref FL_RCC_RSTAPB_UART4 + * @arg @ref FL_RCC_RSTAPB_GPTIM1 + * @arg @ref FL_RCC_RSTAPB_GPTIM0 + * @arg @ref FL_RCC_RSTAPB_LCD + * @arg @ref FL_RCC_RSTAPB_U7816 + * @arg @ref FL_RCC_RSTAPB_SPI2 + * @arg @ref FL_RCC_RSTAPB_LPUART0 + * @arg @ref FL_RCC_RSTAPB_I2C + * @arg @ref FL_RCC_RSTAPB_LPTIM32 + * @retval None + */ +__STATIC_INLINE void FL_RCC_DisableResetAPB1Peripheral(uint32_t peripheral) +{ + CLEAR_BIT(RCC->APBRSTCR1, ((peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @brief Disable APB2 Peripheral Reset + * @rmtoll APBRSTCR2 FL_RCC_DisableResetAPB2Peripheral + * @param peripheral This parameter can be one of the following values: + * @arg @ref FL_RCC_RSTAPB_ATIM + * @arg @ref FL_RCC_RSTAPB_BSTIM32 + * @arg @ref FL_RCC_RSTAPB_ADCCR + * @arg @ref FL_RCC_RSTAPB_ADC + * @arg @ref FL_RCC_RSTAPB_OPA + * @arg @ref FL_RCC_RSTAPB_DIVAS + * @arg @ref FL_RCC_RSTAPB_AES + * @arg @ref FL_RCC_RSTAPB_CRC + * @arg @ref FL_RCC_RSTAPB_RNG + * @arg @ref FL_RCC_RSTAPB_UART1 + * @arg @ref FL_RCC_RSTAPB_UART0 + * @arg @ref FL_RCC_RSTAPB_SPI1 + * @arg @ref FL_RCC_RSTAPB_UCIR + * @arg @ref FL_RCC_RSTAPB_LPUART1 + * @retval None + */ +__STATIC_INLINE void FL_RCC_DisableResetAPB2Peripheral(uint32_t peripheral) +{ + CLEAR_BIT(RCC->APBRSTCR2, ((peripheral & 0xffffffff) << 0x0U)); +} + +/** + * @} + */ + +/** @defgroup RCC_FL_EF_Init Initialization and de-initialization functions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup RCC_FL_EF_Operation Opeartion functions + * @{ + */ + +uint32_t FL_RCC_GetSystemClockFreq(void); +uint32_t FL_RCC_GetAHBClockFreq(void); +uint32_t FL_RCC_GetAPB1ClockFreq(void); +uint32_t FL_RCC_GetAPB2ClockFreq(void); + +uint32_t FL_RCC_GetRC4MClockFreq(void); +uint32_t FL_RCC_GetRCHFClockFreq(void); +uint32_t FL_RCC_GetPLLClockFreq(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_RCC_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-27*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rmu.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rmu.h new file mode 100644 index 0000000000..311e440058 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rmu.h @@ -0,0 +1,287 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_rmu.h + * @author FMSH Application Team + * @brief Head file of RMU FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_RMU_H +#define __FM33LC0XX_FL_RMU_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup RMU RMU + * @brief RMU FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup RMU_FL_ES_INIT RMU Exported Init structures + * @{ + */ + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup RMU_FL_Exported_Constants RMU Exported Constants + * @{ + */ + +#define RMU_PDRCR_CFG_Pos (1U) +#define RMU_PDRCR_CFG_Msk (0x3U << RMU_PDRCR_CFG_Pos) +#define RMU_PDRCR_CFG RMU_PDRCR_CFG_Msk + +#define RMU_PDRCR_EN_Pos (0U) +#define RMU_PDRCR_EN_Msk (0x1U << RMU_PDRCR_EN_Pos) +#define RMU_PDRCR_EN RMU_PDRCR_EN_Msk + +#define RMU_BORCR_CFG_Pos (1U) +#define RMU_BORCR_CFG_Msk (0x3U << RMU_BORCR_CFG_Pos) +#define RMU_BORCR_CFG RMU_BORCR_CFG_Msk + +#define RMU_BORCR_OFF_BOR_1P2_Pos (0U) +#define RMU_BORCR_OFF_BOR_1P2_Msk (0x1U << RMU_BORCR_OFF_BOR_1P2_Pos) +#define RMU_BORCR_OFF_BOR_1P2 RMU_BORCR_OFF_BOR_1P2_Msk + +#define RMU_BORCR_OFF_BOR_1P0_Pos (1U) +#define RMU_BORCR_OFF_BOR_1P0_Msk (0x1U << RMU_BORCR_OFF_BOR_1P0_Pos) +#define RMU_BORCR_OFF_BOR_1P0 RMU_BORCR_OFF_BOR_1P0_Msk + + + + + + +#define FL_RMU_PDR_THRESHOLD_1P5V (0x0U << RMU_PDRCR_CFG_Pos) +#define FL_RMU_PDR_THRESHOLD_1P25V (0x1U << RMU_PDRCR_CFG_Pos) +#define FL_RMU_PDR_THRESHOLD_1P35V (0x2U << RMU_PDRCR_CFG_Pos) +#define FL_RMU_PDR_THRESHOLD_1P4V (0x3U << RMU_PDRCR_CFG_Pos) + + +#define FL_RMU_BOR_THRESHOLD_1P7V (0x0U << RMU_BORCR_CFG_Pos) +#define FL_RMU_BOR_THRESHOLD_1P6V (0x1U << RMU_BORCR_CFG_Pos) +#define FL_RMU_BOR_THRESHOLD_1P65V (0x2U << RMU_BORCR_CFG_Pos) +#define FL_RMU_BOR_THRESHOLD_1P75V (0x3U << RMU_BORCR_CFG_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup RMU_FL_Exported_Functions RMU Exported Functions + * @{ + */ + +/** + * @brief Set PDR Power Down Reset Voltage + * @rmtoll PDRCR CFG FL_RMU_PDR_SetThreshold + * @param RMUx RMU instance + * @param threshold This parameter can be one of the following values: + * @arg @ref FL_RMU_PDR_THRESHOLD_1P5V + * @arg @ref FL_RMU_PDR_THRESHOLD_1P25V + * @arg @ref FL_RMU_PDR_THRESHOLD_1P35V + * @arg @ref FL_RMU_PDR_THRESHOLD_1P4V + * @retval None + */ +__STATIC_INLINE void FL_RMU_PDR_SetThreshold(RMU_Type *RMUx, uint32_t threshold) +{ + MODIFY_REG(RMUx->PDRCR, RMU_PDRCR_CFG_Msk, threshold); +} + +/** + * @brief Get PDR Power Down Reset Voltage Setting + * @rmtoll PDRCR CFG FL_RMU_PDR_GetThreshold + * @param RMUx RMU instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_RMU_PDR_THRESHOLD_1P5V + * @arg @ref FL_RMU_PDR_THRESHOLD_1P25V + * @arg @ref FL_RMU_PDR_THRESHOLD_1P35V + * @arg @ref FL_RMU_PDR_THRESHOLD_1P4V + */ +__STATIC_INLINE uint32_t FL_RMU_PDR_GetThreshold(RMU_Type *RMUx) +{ + return (uint32_t)(READ_BIT(RMUx->PDRCR, RMU_PDRCR_CFG_Msk)); +} + +/** + * @brief Get PDR Power Down Reset Enable Status + * @rmtoll PDRCR EN FL_RMU_PDR_IsEnabled + * @param RMUx RMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RMU_PDR_IsEnabled(RMU_Type *RMUx) +{ + return (uint32_t)(READ_BIT(RMUx->PDRCR, RMU_PDRCR_EN_Msk) == RMU_PDRCR_EN_Msk); +} + +/** + * @brief Disable PDR Power Down Reset + * @rmtoll PDRCR EN FL_RMU_PDR_Disable + * @param RMUx RMU instance + * @retval None + */ +__STATIC_INLINE void FL_RMU_PDR_Disable(RMU_Type *RMUx) +{ + CLEAR_BIT(RMUx->PDRCR, RMU_PDRCR_EN_Msk); +} + +/** + * @brief Enable PDR Power Down Reset + * @rmtoll PDRCR EN FL_RMU_PDR_Enable + * @param RMUx RMU instance + * @retval None + */ +__STATIC_INLINE void FL_RMU_PDR_Enable(RMU_Type *RMUx) +{ + SET_BIT(RMUx->PDRCR, RMU_PDRCR_EN_Msk); +} + +/** + * @brief Set BOR Power Down Reset Voltage + * @rmtoll BORCR CFG FL_RMU_BOR_SetThreshold + * @param RMUx RMU instance + * @param threshold This parameter can be one of the following values: + * @arg @ref FL_RMU_BOR_THRESHOLD_1P7V + * @arg @ref FL_RMU_BOR_THRESHOLD_1P6V + * @arg @ref FL_RMU_BOR_THRESHOLD_1P65V + * @arg @ref FL_RMU_BOR_THRESHOLD_1P75V + * @retval None + */ +__STATIC_INLINE void FL_RMU_BOR_SetThreshold(RMU_Type *RMUx, uint32_t threshold) +{ + MODIFY_REG(RMUx->BORCR, RMU_BORCR_CFG_Msk, threshold); +} + +/** + * @brief Get BOR Power Down Reset Voltage Setting + * @rmtoll BORCR CFG FL_RMU_BOR_GetThreshold + * @param RMUx RMU instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_RMU_BOR_THRESHOLD_1P7V + * @arg @ref FL_RMU_BOR_THRESHOLD_1P6V + * @arg @ref FL_RMU_BOR_THRESHOLD_1P65V + * @arg @ref FL_RMU_BOR_THRESHOLD_1P75V + */ +__STATIC_INLINE uint32_t FL_RMU_BOR_GetThreshold(RMU_Type *RMUx) +{ + return (uint32_t)(READ_BIT(RMUx->BORCR, RMU_BORCR_CFG_Msk)); +} + +/** + * @brief Get BOR Power Down Reset Enable Status + * @rmtoll BORCR OFF_BOR_1P2 FL_RMU_BORPowerDown_IsEnabled + * @param RMUx RMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RMU_BORPowerDown_IsEnabled(RMU_Type *RMUx) +{ + return (uint32_t)!(READ_BIT(RMUx->BORCR, RMU_BORCR_OFF_BOR_1P2_Msk) == RMU_BORCR_OFF_BOR_1P2_Msk); +} + +/** + * @brief Disable BOR Power Down Reset + * @rmtoll BORCR OFF_BOR_1P2 FL_RMU_BORPowerDown_Disable + * @param RMUx RMU instance + * @retval None + */ +__STATIC_INLINE void FL_RMU_BORPowerDown_Disable(RMU_Type *RMUx) +{ + SET_BIT(RMUx->BORCR, RMU_BORCR_OFF_BOR_1P2_Msk); +} + +/** + * @brief Enable BOR Power Down Reset + * @rmtoll BORCR OFF_BOR_1P2 FL_RMU_BORPowerDown_Enable + * @param RMUx RMU instance + * @retval None + */ +__STATIC_INLINE void FL_RMU_BORPowerDown_Enable(RMU_Type *RMUx) +{ + CLEAR_BIT(RMUx->BORCR, RMU_BORCR_OFF_BOR_1P2_Msk); +} + +/** + * @brief Get BOR Power On Reset Enable Status + * @rmtoll BORCR OFF_BOR_1P0 FL_RMU_BORPowerUp_IsEnabled + * @param RMUx RMU instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RMU_BORPowerUp_IsEnabled(RMU_Type *RMUx) +{ + return (uint32_t)!(READ_BIT(RMUx->BORCR, RMU_BORCR_OFF_BOR_1P0_Msk) == RMU_BORCR_OFF_BOR_1P0_Msk); +} + +/** + * @brief Disable BOR Power On Reset + * @rmtoll BORCR OFF_BOR_1P0 FL_RMU_BORPowerUp_Disable + * @param RMUx RMU instance + * @retval None + */ +__STATIC_INLINE void FL_RMU_BORPowerUp_Disable(RMU_Type *RMUx) +{ + SET_BIT(RMUx->BORCR, RMU_BORCR_OFF_BOR_1P0_Msk); +} + +/** + * @brief Enable BOR Power On Reset + * @rmtoll BORCR OFF_BOR_1P0 FL_RMU_BORPowerUp_Enable + * @param RMUx RMU instance + * @retval None + */ +__STATIC_INLINE void FL_RMU_BORPowerUp_Enable(RMU_Type *RMUx) +{ + CLEAR_BIT(RMUx->BORCR, RMU_BORCR_OFF_BOR_1P0_Msk); +} + +/** + * @} + */ + +/** @defgroup RMU_FL_EF_Init Initialization and de-initialization functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_RMU_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rng.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rng.h new file mode 100644 index 0000000000..b72be86caa --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rng.h @@ -0,0 +1,264 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_rng.h + * @author FMSH Application Team + * @brief Head file of RNG FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_RNG_H +#define __FM33LC0XX_FL_RNG_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup RNG RNG + * @brief RNG FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup RNG_FL_ES_INIT RNG Exported Init structures + * @{ + */ + +/** + * @brief RNG Init Sturcture definition + */ + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup RNG_FL_Exported_Constants RNG Exported Constants + * @{ + */ + +#define RNG_CR_EN_Pos (0U) +#define RNG_CR_EN_Msk (0x1U << RNG_CR_EN_Pos) +#define RNG_CR_EN RNG_CR_EN_Msk + +#define RNG_SR_RBUSY_Pos (1U) +#define RNG_SR_RBUSY_Msk (0x1U << RNG_SR_RBUSY_Pos) +#define RNG_SR_RBUSY RNG_SR_RBUSY_Msk + +#define RNG_SR_RNF_Pos (0U) +#define RNG_SR_RNF_Msk (0x1U << RNG_SR_RNF_Pos) +#define RNG_SR_RNF RNG_SR_RNF_Msk + +#define RNG_CRCCR_CRCEN_Pos (0U) +#define RNG_CRCCR_CRCEN_Msk (0x1U << RNG_CRCCR_CRCEN_Pos) +#define RNG_CRCCR_CRCEN RNG_CRCCR_CRCEN_Msk + +#define RNG_CRCSR_CRCDONE_Pos (0U) +#define RNG_CRCSR_CRCDONE_Msk (0x1U << RNG_CRCSR_CRCDONE_Pos) +#define RNG_CRCSR_CRCDONE RNG_CRCSR_CRCDONE_Msk + + + + + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup RNG_FL_Exported_Functions RNG Exported Functions + * @{ + */ + +/** + * @brief RNG enable + * @rmtoll CR EN FL_RNG_Enable + * @param RNGCTLx RNGCTL instance + * @retval None + */ +__STATIC_INLINE void FL_RNG_Enable(RNGCTL_Type *RNGCTLx) +{ + SET_BIT(RNGCTLx->CR, RNG_CR_EN_Msk); +} + +/** + * @brief RNG enable status + * @rmtoll CR EN FL_RNG_IsEnabled + * @param RNGCTLx RNGCTL instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RNG_IsEnabled(RNGCTL_Type *RNGCTLx) +{ + return (uint32_t)(READ_BIT(RNGCTLx->CR, RNG_CR_EN_Msk) == RNG_CR_EN_Msk); +} + +/** + * @brief RNG disable + * @rmtoll CR EN FL_RNG_Disable + * @param RNGCTLx RNGCTL instance + * @retval None + */ +__STATIC_INLINE void FL_RNG_Disable(RNGCTL_Type *RNGCTLx) +{ + CLEAR_BIT(RNGCTLx->CR, RNG_CR_EN_Msk); +} + +/** + * @brief Read RNG output data register + * @rmtoll DOR FL_RNG_ReadData + * @param RNGx RNG instance + * @retval + */ +__STATIC_INLINE uint32_t FL_RNG_ReadData(RNG_Type *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->DOR, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @brief Get LFSR Flag + * @rmtoll SR RBUSY FL_RNG_IsActiveFlag_Busy + * @param RNGx RNG instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RNG_IsActiveFlag_Busy(RNG_Type *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->SR, RNG_SR_RBUSY_Msk) == (RNG_SR_RBUSY_Msk)); +} + +/** + * @brief Get random number fail flag + * @rmtoll SR RNF FL_RNG_IsActiveFlag_RandomFail + * @param RNGx RNG instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RNG_IsActiveFlag_RandomFail(RNG_Type *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->SR, RNG_SR_RNF_Msk) == (RNG_SR_RNF_Msk)); +} + +/** + * @brief Clear random number fail flag + * @rmtoll SR RNF FL_RNG_ClearFlag_RandomFail + * @param RNGx RNG instance + * @retval None + */ +__STATIC_INLINE void FL_RNG_ClearFlag_RandomFail(RNG_Type *RNGx) +{ + WRITE_REG(RNGx->SR, RNG_SR_RNF_Msk); +} + +/** + * @brief CRC enable + * @rmtoll CRCCR CRCEN FL_RNG_CRC_Enable + * @param RNGx RNG instance + * @retval None + */ +__STATIC_INLINE void FL_RNG_CRC_Enable(RNG_Type *RNGx) +{ + SET_BIT(RNGx->CRCCR, RNG_CRCCR_CRCEN_Msk); +} + +/** + * @brief Get CRC enable status + * @rmtoll CRCCR CRCEN FL_RNG_CRC_IsEnabled + * @param RNGx RNG instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RNG_CRC_IsEnabled(RNG_Type *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->CRCCR, RNG_CRCCR_CRCEN_Msk) == RNG_CRCCR_CRCEN_Msk); +} + +/** + * @brief Write CRC data input + * @rmtoll CRCDIR FL_RNG_CRC_WriteData + * @param RNGx RNG instance + * @param data + * @retval None + */ +__STATIC_INLINE void FL_RNG_CRC_WriteData(RNG_Type *RNGx, uint32_t data) +{ + MODIFY_REG(RNGx->CRCDIR, (0xffffffffU << 0U), (data << 0U)); +} + +/** + * @brief Get CRC calculation done Flag + * @rmtoll CRCSR CRCDONE FL_RNG_IsActiveFlag_CRCComplete + * @param RNGx RNG instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RNG_IsActiveFlag_CRCComplete(RNG_Type *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->CRCSR, RNG_CRCSR_CRCDONE_Msk) == (RNG_CRCSR_CRCDONE_Msk)); +} + +/** + * @brief Clear CRC calculation done Flag + * @rmtoll CRCSR CRCDONE FL_RNG_ClearFlag_CRCComplete + * @param RNGx RNG instance + * @retval None + */ +__STATIC_INLINE void FL_RNG_ClearFlag_CRCComplete(RNG_Type *RNGx) +{ + CLEAR_BIT(RNGx->CRCSR, RNG_CRCSR_CRCDONE_Msk); +} + +/** + * @} + */ + +/** @defgroup RNG_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_RNG_DeInit(RNG_Type *RNGx); +FL_ErrorStatus FL_RNG_Init(RNG_Type *RNGx); + +/** + * @} + */ + +/** @defgroup RNG_FL_EF_Operation Opeartion functions + * @{ + */ + +uint32_t GetRandomNumber(void); +uint32_t GetCrc32(uint32_t dataIn); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_RNG_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rtc.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rtc.h new file mode 100644 index 0000000000..0087c43899 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_rtc.h @@ -0,0 +1,1389 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_rtc.h + * @author FMSH Application Team + * @brief Head file of RTC FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_RTC_H +#define __FM33LC0XX_FL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup RTC RTC + * @brief RTC FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup RTC_FL_ES_INIT RTC Exported Init structures + * @{ + */ + +/** + * @brief Configuration with temporary structure variable users will not be used directly + */ +typedef struct +{ + __IO uint32_t backup[7]; +} FL_RTC_Backup_ADDR; + +/** + * @brief RTC Init Sturcture definition + */ +typedef struct +{ + /** 年 */ + uint32_t year; + /** 月 */ + uint32_t month; + /** 日 */ + uint32_t day; + /** 周 */ + uint32_t week; + /** 时 */ + uint32_t hour; + /** 分 */ + uint32_t minute; + /** 秒 */ + uint32_t second; + +} FL_RTC_InitTypeDef; + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup RTC_FL_Exported_Constants RTC Exported Constants + * @{ + */ + +#define RTC_IER_ADJ_IE_Pos (12U) +#define RTC_IER_ADJ_IE_Msk (0x1U << RTC_IER_ADJ_IE_Pos) +#define RTC_IER_ADJ_IE RTC_IER_ADJ_IE_Msk + +#define RTC_IER_ALARM_IE_Pos (11U) +#define RTC_IER_ALARM_IE_Msk (0x1U << RTC_IER_ALARM_IE_Pos) +#define RTC_IER_ALARM_IE RTC_IER_ALARM_IE_Msk + +#define RTC_IER_1KHZ_IE_Pos (10U) +#define RTC_IER_1KHZ_IE_Msk (0x1U << RTC_IER_1KHZ_IE_Pos) +#define RTC_IER_1KHZ_IE RTC_IER_1KHZ_IE_Msk + +#define RTC_IER_256HZ_IE_Pos (9U) +#define RTC_IER_256HZ_IE_Msk (0x1U << RTC_IER_256HZ_IE_Pos) +#define RTC_IER_256HZ_IE RTC_IER_256HZ_IE_Msk + +#define RTC_IER_64HZ_IE_Pos (8U) +#define RTC_IER_64HZ_IE_Msk (0x1U << RTC_IER_64HZ_IE_Pos) +#define RTC_IER_64HZ_IE RTC_IER_64HZ_IE_Msk + +#define RTC_IER_16HZ_IE_Pos (7U) +#define RTC_IER_16HZ_IE_Msk (0x1U << RTC_IER_16HZ_IE_Pos) +#define RTC_IER_16HZ_IE RTC_IER_16HZ_IE_Msk + +#define RTC_IER_8HZ_IE_Pos (6U) +#define RTC_IER_8HZ_IE_Msk (0x1U << RTC_IER_8HZ_IE_Pos) +#define RTC_IER_8HZ_IE RTC_IER_8HZ_IE_Msk + +#define RTC_IER_4HZ_IE_Pos (5U) +#define RTC_IER_4HZ_IE_Msk (0x1U << RTC_IER_4HZ_IE_Pos) +#define RTC_IER_4HZ_IE RTC_IER_4HZ_IE_Msk + +#define RTC_IER_2HZ_IE_Pos (4U) +#define RTC_IER_2HZ_IE_Msk (0x1U << RTC_IER_2HZ_IE_Pos) +#define RTC_IER_2HZ_IE RTC_IER_2HZ_IE_Msk + +#define RTC_IER_SEC_IE_Pos (3U) +#define RTC_IER_SEC_IE_Msk (0x1U << RTC_IER_SEC_IE_Pos) +#define RTC_IER_SEC_IE RTC_IER_SEC_IE_Msk + +#define RTC_IER_MIN_IE_Pos (2U) +#define RTC_IER_MIN_IE_Msk (0x1U << RTC_IER_MIN_IE_Pos) +#define RTC_IER_MIN_IE RTC_IER_MIN_IE_Msk + +#define RTC_IER_HOUR_IE_Pos (1U) +#define RTC_IER_HOUR_IE_Msk (0x1U << RTC_IER_HOUR_IE_Pos) +#define RTC_IER_HOUR_IE RTC_IER_HOUR_IE_Msk + +#define RTC_IER_DAY_IE_Pos (0U) +#define RTC_IER_DAY_IE_Msk (0x1U << RTC_IER_DAY_IE_Pos) +#define RTC_IER_DAY_IE RTC_IER_DAY_IE_Msk + +#define RTC_ISR_ADJ_IF_Pos (12U) +#define RTC_ISR_ADJ_IF_Msk (0x1U << RTC_ISR_ADJ_IF_Pos) +#define RTC_ISR_ADJ_IF RTC_ISR_ADJ_IF_Msk + +#define RTC_ISR_ALARM_IF_Pos (11U) +#define RTC_ISR_ALARM_IF_Msk (0x1U << RTC_ISR_ALARM_IF_Pos) +#define RTC_ISR_ALARM_IF RTC_ISR_ALARM_IF_Msk + +#define RTC_ISR_1KHZ_IF_Pos (10U) +#define RTC_ISR_1KHZ_IF_Msk (0x1U << RTC_ISR_1KHZ_IF_Pos) +#define RTC_ISR_1KHZ_IF RTC_ISR_1KHZ_IF_Msk + +#define RTC_ISR_256HZ_IF_Pos (9U) +#define RTC_ISR_256HZ_IF_Msk (0x1U << RTC_ISR_256HZ_IF_Pos) +#define RTC_ISR_256HZ_IF RTC_ISR_256HZ_IF_Msk + +#define RTC_ISR_64HZ_IF_Pos (8U) +#define RTC_ISR_64HZ_IF_Msk (0x1U << RTC_ISR_64HZ_IF_Pos) +#define RTC_ISR_64HZ_IF RTC_ISR_64HZ_IF_Msk + +#define RTC_ISR_16HZ_IF_Pos (7U) +#define RTC_ISR_16HZ_IF_Msk (0x1U << RTC_ISR_16HZ_IF_Pos) +#define RTC_ISR_16HZ_IF RTC_ISR_16HZ_IF_Msk + +#define RTC_ISR_8HZ_IF_Pos (6U) +#define RTC_ISR_8HZ_IF_Msk (0x1U << RTC_ISR_8HZ_IF_Pos) +#define RTC_ISR_8HZ_IF RTC_ISR_8HZ_IF_Msk + +#define RTC_ISR_4HZ_IF_Pos (5U) +#define RTC_ISR_4HZ_IF_Msk (0x1U << RTC_ISR_4HZ_IF_Pos) +#define RTC_ISR_4HZ_IF RTC_ISR_4HZ_IF_Msk + +#define RTC_ISR_2HZ_IF_Pos (4U) +#define RTC_ISR_2HZ_IF_Msk (0x1U << RTC_ISR_2HZ_IF_Pos) +#define RTC_ISR_2HZ_IF RTC_ISR_2HZ_IF_Msk + +#define RTC_ISR_SEC_IF_Pos (3U) +#define RTC_ISR_SEC_IF_Msk (0x1U << RTC_ISR_SEC_IF_Pos) +#define RTC_ISR_SEC_IF RTC_ISR_SEC_IF_Msk + +#define RTC_ISR_MIN_IF_Pos (2U) +#define RTC_ISR_MIN_IF_Msk (0x1U << RTC_ISR_MIN_IF_Pos) +#define RTC_ISR_MIN_IF RTC_ISR_MIN_IF_Msk + +#define RTC_ISR_HOUR_IF_Pos (1U) +#define RTC_ISR_HOUR_IF_Msk (0x1U << RTC_ISR_HOUR_IF_Pos) +#define RTC_ISR_HOUR_IF RTC_ISR_HOUR_IF_Msk + +#define RTC_ISR_DAY_IF_Pos (0U) +#define RTC_ISR_DAY_IF_Msk (0x1U << RTC_ISR_DAY_IF_Pos) +#define RTC_ISR_DAY_IF RTC_ISR_DAY_IF_Msk + +#define RTC_TMSEL_TMSEL_Pos (0U) +#define RTC_TMSEL_TMSEL_Msk (0xfU << RTC_TMSEL_TMSEL_Pos) +#define RTC_TMSEL_TMSEL RTC_TMSEL_TMSEL_Msk + +#define RTC_ADSIGN_ADSIGN_Pos (0U) +#define RTC_ADSIGN_ADSIGN_Msk (0x1U << RTC_ADSIGN_ADSIGN_Pos) +#define RTC_ADSIGN_ADSIGN RTC_ADSIGN_ADSIGN_Msk + + + +#define FL_RTC_BACKUP_0 (0x0U) +#define FL_RTC_BACKUP_1 (0x1U) +#define FL_RTC_BACKUP_2 (0x2U) +#define FL_RTC_BACKUP_3 (0x3U) +#define FL_RTC_BACKUP_4 (0x4U) +#define FL_RTC_BACKUP_5 (0x5U) +#define FL_RTC_BACKUP_6 (0x6U) +#define FL_RTC_BACKUP_7 (0x7U) + + + +#define FL_RTC_TIME_MARK_SECOND (0x2U << RTC_TMSEL_TMSEL_Pos) +#define FL_RTC_TIME_MARK_MINUTE (0x3U << RTC_TMSEL_TMSEL_Pos) +#define FL_RTC_TIME_MARK_HOUR (0x4U << RTC_TMSEL_TMSEL_Pos) +#define FL_RTC_TIME_MARK_DAY (0x5U << RTC_TMSEL_TMSEL_Pos) +#define FL_RTC_TIME_MARK_ALARM (0x6U << RTC_TMSEL_TMSEL_Pos) +#define FL_RTC_TIME_MARK_32_SEC (0x7U << RTC_TMSEL_TMSEL_Pos) +#define FL_RTC_TIME_MARK_SECOND_REVERSE (0x9U << RTC_TMSEL_TMSEL_Pos) +#define FL_RTC_TIME_MARK_MINUTE_REVERSE (0xaU << RTC_TMSEL_TMSEL_Pos) +#define FL_RTC_TIME_MARK_HOUR_REVERSE (0xbU << RTC_TMSEL_TMSEL_Pos) +#define FL_RTC_TIME_MARK_DAY_REVERSE (0xcU << RTC_TMSEL_TMSEL_Pos) +#define FL_RTC_TIME_MARK_ALARM_REVERSE (0xdU << RTC_TMSEL_TMSEL_Pos) +#define FL_RTC_TIME_MARK_SEC (0xfU << RTC_TMSEL_TMSEL_Pos) + + +#define FL_RTC_ADJUST_DIR_INCREASE (0x0U << RTC_ADSIGN_ADSIGN_Pos) +#define FL_RTC_ADJUST_DIR_DECREASE (0x1U << RTC_ADSIGN_ADSIGN_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup RTC_FL_Exported_Functions RTC Exported Functions + * @{ + */ + +/** + * @brief Enable RTC Config Time + * @rmtoll WER FL_RTC_WriteEnable + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteEnable(RTC_Type *RTCx) +{ + RTCx->WER = 0xACACACAC; +} + +/** + * @brief Disable RTC Config Time + * @rmtoll WER FL_RTC_WriteDisable + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteDisable(RTC_Type *RTCx) +{ + RTCx->WER = 0x5A5A5A5A; +} + +/** + * @brief Enable RTC Time Adjust Interrupt + * @rmtoll IER ADJ_IE FL_RTC_EnableIT_Adjust + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_EnableIT_Adjust(RTC_Type *RTCx) +{ + SET_BIT(RTCx->IER, RTC_IER_ADJ_IE_Msk); +} + +/** + * @brief Get RTC Time Adjust Interrupt Enable Status + * @rmtoll IER ADJ_IE FL_RTC_IsEnabledIT_Adjust + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsEnabledIT_Adjust(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->IER, RTC_IER_ADJ_IE_Msk) == RTC_IER_ADJ_IE_Msk); +} + +/** + * @brief Disable RTC Time Adjust Interrupt + * @rmtoll IER ADJ_IE FL_RTC_DisableIT_Adjust + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_DisableIT_Adjust(RTC_Type *RTCx) +{ + CLEAR_BIT(RTCx->IER, RTC_IER_ADJ_IE_Msk); +} + +/** + * @brief Enable RTC Alarm Interrupt + * @rmtoll IER ALARM_IE FL_RTC_EnableIT_Alarm + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_EnableIT_Alarm(RTC_Type *RTCx) +{ + SET_BIT(RTCx->IER, RTC_IER_ALARM_IE_Msk); +} + +/** + * @brief Get RTC Alarm Interrupt Enable Status + * @rmtoll IER ALARM_IE FL_RTC_IsEnabledIT_Alarm + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsEnabledIT_Alarm(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->IER, RTC_IER_ALARM_IE_Msk) == RTC_IER_ALARM_IE_Msk); +} + +/** + * @brief Disable RTC Alarm Interrupt + * @rmtoll IER ALARM_IE FL_RTC_DisableIT_Alarm + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_DisableIT_Alarm(RTC_Type *RTCx) +{ + CLEAR_BIT(RTCx->IER, RTC_IER_ALARM_IE_Msk); +} + +/** + * @brief Enable RTC 1KHz Interrupt + * @rmtoll IER 1KHZ_IE FL_RTC_EnableIT_1KHz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_EnableIT_1KHz(RTC_Type *RTCx) +{ + SET_BIT(RTCx->IER, RTC_IER_1KHZ_IE_Msk); +} + +/** + * @brief Get RTC 1KHz Interrupt Enable Status + * @rmtoll IER 1KHZ_IE FL_RTC_IsEnabledIT_1KHz + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsEnabledIT_1KHz(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->IER, RTC_IER_1KHZ_IE_Msk) == RTC_IER_1KHZ_IE_Msk); +} + +/** + * @brief Disable RTC 1KHz Interrupt + * @rmtoll IER 1KHZ_IE FL_RTC_DisableIT_1KHz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_DisableIT_1KHz(RTC_Type *RTCx) +{ + CLEAR_BIT(RTCx->IER, RTC_IER_1KHZ_IE_Msk); +} + +/** + * @brief Enable RTC 256Hz Interrupt + * @rmtoll IER 256HZ_IE FL_RTC_EnableIT_256Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_EnableIT_256Hz(RTC_Type *RTCx) +{ + SET_BIT(RTCx->IER, RTC_IER_256HZ_IE_Msk); +} + +/** + * @brief Get RTC 256Hz Interrupt Enable Status + * @rmtoll IER 256HZ_IE FL_RTC_IsEnabledIT_256Hz + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsEnabledIT_256Hz(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->IER, RTC_IER_256HZ_IE_Msk) == RTC_IER_256HZ_IE_Msk); +} + +/** + * @brief Disable RTC 256Hz Interrupt + * @rmtoll IER 256HZ_IE FL_RTC_DisableIT_256Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_DisableIT_256Hz(RTC_Type *RTCx) +{ + CLEAR_BIT(RTCx->IER, RTC_IER_256HZ_IE_Msk); +} + +/** + * @brief Enable RTC 64Hz Interrupt + * @rmtoll IER 64HZ_IE FL_RTC_EnableIT_64Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_EnableIT_64Hz(RTC_Type *RTCx) +{ + SET_BIT(RTCx->IER, RTC_IER_64HZ_IE_Msk); +} + +/** + * @brief Get RTC 64Hz Interrupt Enable Status + * @rmtoll IER 64HZ_IE FL_RTC_IsEnabledIT_64Hz + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsEnabledIT_64Hz(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->IER, RTC_IER_64HZ_IE_Msk) == RTC_IER_64HZ_IE_Msk); +} + +/** + * @brief Disable RTC 64Hz Interrupt + * @rmtoll IER 64HZ_IE FL_RTC_DisableIT_64Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_DisableIT_64Hz(RTC_Type *RTCx) +{ + CLEAR_BIT(RTCx->IER, RTC_IER_64HZ_IE_Msk); +} + +/** + * @brief Enable RTC 16Hz Interrupt + * @rmtoll IER 16HZ_IE FL_RTC_EnableIT_16Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_EnableIT_16Hz(RTC_Type *RTCx) +{ + SET_BIT(RTCx->IER, RTC_IER_16HZ_IE_Msk); +} + +/** + * @brief Get RTC 16Hz Interrupt Enable Status + * @rmtoll IER 16HZ_IE FL_RTC_IsEnabledIT_16Hz + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsEnabledIT_16Hz(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->IER, RTC_IER_16HZ_IE_Msk) == RTC_IER_16HZ_IE_Msk); +} + +/** + * @brief Disable RTC 16Hz Interrupt + * @rmtoll IER 16HZ_IE FL_RTC_DisableIT_16Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_DisableIT_16Hz(RTC_Type *RTCx) +{ + CLEAR_BIT(RTCx->IER, RTC_IER_16HZ_IE_Msk); +} + +/** + * @brief Enable RTC 8Hz Interrupt + * @rmtoll IER 8HZ_IE FL_RTC_EnableIT_8Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_EnableIT_8Hz(RTC_Type *RTCx) +{ + SET_BIT(RTCx->IER, RTC_IER_8HZ_IE_Msk); +} + +/** + * @brief Get RTC 8Hz Interrupt Enable Status + * @rmtoll IER 8HZ_IE FL_RTC_IsEnabledIT_8Hz + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsEnabledIT_8Hz(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->IER, RTC_IER_8HZ_IE_Msk) == RTC_IER_8HZ_IE_Msk); +} + +/** + * @brief Disable RTC 8Hz Interrupt + * @rmtoll IER 8HZ_IE FL_RTC_DisableIT_8Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_DisableIT_8Hz(RTC_Type *RTCx) +{ + CLEAR_BIT(RTCx->IER, RTC_IER_8HZ_IE_Msk); +} + +/** + * @brief Enable RTC 4Hz Interrupt + * @rmtoll IER 4HZ_IE FL_RTC_EnableIT_4Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_EnableIT_4Hz(RTC_Type *RTCx) +{ + SET_BIT(RTCx->IER, RTC_IER_4HZ_IE_Msk); +} + +/** + * @brief Get RTC 4Hz Interrupt Enable Status + * @rmtoll IER 4HZ_IE FL_RTC_IsEnabledIT_4Hz + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsEnabledIT_4Hz(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->IER, RTC_IER_4HZ_IE_Msk) == RTC_IER_4HZ_IE_Msk); +} + +/** + * @brief Disable RTC 4Hz Interrupt + * @rmtoll IER 4HZ_IE FL_RTC_DisableIT_4Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_DisableIT_4Hz(RTC_Type *RTCx) +{ + CLEAR_BIT(RTCx->IER, RTC_IER_4HZ_IE_Msk); +} + +/** + * @brief Enable RTC 2Hz Interrupt + * @rmtoll IER 2HZ_IE FL_RTC_EnableIT_2Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_EnableIT_2Hz(RTC_Type *RTCx) +{ + SET_BIT(RTCx->IER, RTC_IER_2HZ_IE_Msk); +} + +/** + * @brief Get RTC 2Hz Interrupt Enable Status + * @rmtoll IER 2HZ_IE FL_RTC_IsEnabledIT_2Hz + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsEnabledIT_2Hz(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->IER, RTC_IER_2HZ_IE_Msk) == RTC_IER_2HZ_IE_Msk); +} + +/** + * @brief Disable RTC 2Hz Interrupt + * @rmtoll IER 2HZ_IE FL_RTC_DisableIT_2Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_DisableIT_2Hz(RTC_Type *RTCx) +{ + CLEAR_BIT(RTCx->IER, RTC_IER_2HZ_IE_Msk); +} + +/** + * @brief Enable RTC Second Interrupt + * @rmtoll IER SEC_IE FL_RTC_EnableIT_Second + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_EnableIT_Second(RTC_Type *RTCx) +{ + SET_BIT(RTCx->IER, RTC_IER_SEC_IE_Msk); +} + +/** + * @brief Get RTC Second Interrupt Enable Status + * @rmtoll IER SEC_IE FL_RTC_IsEnabledIT_Second + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsEnabledIT_Second(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->IER, RTC_IER_SEC_IE_Msk) == RTC_IER_SEC_IE_Msk); +} + +/** + * @brief Disable RTC Second Interrupt + * @rmtoll IER SEC_IE FL_RTC_DisableIT_Second + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_DisableIT_Second(RTC_Type *RTCx) +{ + CLEAR_BIT(RTCx->IER, RTC_IER_SEC_IE_Msk); +} + +/** + * @brief Enable RTC Minute Interrupt + * @rmtoll IER MIN_IE FL_RTC_EnableIT_Minute + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_EnableIT_Minute(RTC_Type *RTCx) +{ + SET_BIT(RTCx->IER, RTC_IER_MIN_IE_Msk); +} + +/** + * @brief Get RTC Minute Interrupt Enable Status + * @rmtoll IER MIN_IE FL_RTC_IsEnabledIT_Minute + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsEnabledIT_Minute(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->IER, RTC_IER_MIN_IE_Msk) == RTC_IER_MIN_IE_Msk); +} + +/** + * @brief Disable RTC Minute Interrupt + * @rmtoll IER MIN_IE FL_RTC_DisableIT_Minute + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_DisableIT_Minute(RTC_Type *RTCx) +{ + CLEAR_BIT(RTCx->IER, RTC_IER_MIN_IE_Msk); +} + +/** + * @brief Enable RTC Hour Interrupt + * @rmtoll IER HOUR_IE FL_RTC_EnableIT_Hour + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_EnableIT_Hour(RTC_Type *RTCx) +{ + SET_BIT(RTCx->IER, RTC_IER_HOUR_IE_Msk); +} + +/** + * @brief Get RTC Hour Interrupt Enable Status + * @rmtoll IER HOUR_IE FL_RTC_IsEnabledIT_Hour + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsEnabledIT_Hour(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->IER, RTC_IER_HOUR_IE_Msk) == RTC_IER_HOUR_IE_Msk); +} + +/** + * @brief Disable RTC Hour Interrupt + * @rmtoll IER HOUR_IE FL_RTC_DisableIT_Hour + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_DisableIT_Hour(RTC_Type *RTCx) +{ + CLEAR_BIT(RTCx->IER, RTC_IER_HOUR_IE_Msk); +} + +/** + * @brief Enable RTC Day Interrupt + * @rmtoll IER DAY_IE FL_RTC_EnableIT_Day + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_EnableIT_Day(RTC_Type *RTCx) +{ + SET_BIT(RTCx->IER, RTC_IER_DAY_IE_Msk); +} + +/** + * @brief Get RTC Day Interrupt Enable Status + * @rmtoll IER DAY_IE FL_RTC_IsEnabledIT_Day + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsEnabledIT_Day(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->IER, RTC_IER_DAY_IE_Msk) == RTC_IER_DAY_IE_Msk); +} + +/** + * @brief Disable RTC Day Interrupt + * @rmtoll IER DAY_IE FL_RTC_DisableIT_Day + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_DisableIT_Day(RTC_Type *RTCx) +{ + CLEAR_BIT(RTCx->IER, RTC_IER_DAY_IE_Msk); +} + +/** + * @brief Clear RTC Time Adjust Interrupt Flag + * @rmtoll ISR ADJ_IF FL_RTC_ClearFlag_Adjust + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_ClearFlag_Adjust(RTC_Type *RTCx) +{ + WRITE_REG(RTCx->ISR, RTC_ISR_ADJ_IF_Msk); +} + +/** + * @brief Get RTC Time Adjust Interrupt Flag + * @rmtoll ISR ADJ_IF FL_RTC_IsActiveFlag_Adjust + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsActiveFlag_Adjust(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ISR, RTC_ISR_ADJ_IF_Msk) == (RTC_ISR_ADJ_IF_Msk)); +} + +/** + * @brief Clear RTC Alarm Interrupt Flag + * @rmtoll ISR ALARM_IF FL_RTC_ClearFlag_Alarm + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_ClearFlag_Alarm(RTC_Type *RTCx) +{ + WRITE_REG(RTCx->ISR, RTC_ISR_ALARM_IF_Msk); +} + +/** + * @brief Get RTC Alarm Interrupt Flag + * @rmtoll ISR ALARM_IF FL_RTC_IsActiveFlag_Alarm + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsActiveFlag_Alarm(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ISR, RTC_ISR_ALARM_IF_Msk) == (RTC_ISR_ALARM_IF_Msk)); +} + +/** + * @brief Clear RTC 1KHz Interrupt Flag + * @rmtoll ISR 1KHZ_IF FL_RTC_ClearFlag_1KHz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_ClearFlag_1KHz(RTC_Type *RTCx) +{ + WRITE_REG(RTCx->ISR, RTC_ISR_1KHZ_IF_Msk); +} + +/** + * @brief Get RTC 1KHz Interrupt Flag + * @rmtoll ISR 1KHZ_IF FL_RTC_IsActiveFlag_1KHz + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsActiveFlag_1KHz(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ISR, RTC_ISR_1KHZ_IF_Msk) == (RTC_ISR_1KHZ_IF_Msk)); +} + +/** + * @brief Clear RTC 256Hz Interrupt Flag + * @rmtoll ISR 256HZ_IF FL_RTC_ClearFlag_256Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_ClearFlag_256Hz(RTC_Type *RTCx) +{ + WRITE_REG(RTCx->ISR, RTC_ISR_256HZ_IF_Msk); +} + +/** + * @brief Get RTC 256Hz Interrupt Flag + * @rmtoll ISR 256HZ_IF FL_RTC_IsActiveFlag_256Hz + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsActiveFlag_256Hz(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ISR, RTC_ISR_256HZ_IF_Msk) == (RTC_ISR_256HZ_IF_Msk)); +} + +/** + * @brief Clear RTC 64Hz Interrupt Flag + * @rmtoll ISR 64HZ_IF FL_RTC_ClearFlag_64Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_ClearFlag_64Hz(RTC_Type *RTCx) +{ + WRITE_REG(RTCx->ISR, RTC_ISR_64HZ_IF_Msk); +} + +/** + * @brief Get RTC 64Hz Interrupt Flag + * @rmtoll ISR 64HZ_IF FL_RTC_IsActiveFlag_64Hz + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsActiveFlag_64Hz(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ISR, RTC_ISR_64HZ_IF_Msk) == (RTC_ISR_64HZ_IF_Msk)); +} + +/** + * @brief Clear RTC 16Hz Interrupt Flag + * @rmtoll ISR 16HZ_IF FL_RTC_ClearFlag_16Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_ClearFlag_16Hz(RTC_Type *RTCx) +{ + WRITE_REG(RTCx->ISR, RTC_ISR_16HZ_IF_Msk); +} + +/** + * @brief Get RTC 16Hz Interrupt Flag + * @rmtoll ISR 16HZ_IF FL_RTC_IsActiveFlag_16Hz + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsActiveFlag_16Hz(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ISR, RTC_ISR_16HZ_IF_Msk) == (RTC_ISR_16HZ_IF_Msk)); +} + +/** + * @brief Clear RTC 8Hz Interrupt Flag + * @rmtoll ISR 8HZ_IF FL_RTC_ClearFlag_8Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_ClearFlag_8Hz(RTC_Type *RTCx) +{ + WRITE_REG(RTCx->ISR, RTC_ISR_8HZ_IF_Msk); +} + +/** + * @brief Get RTC 8Hz Interrupt Flag + * @rmtoll ISR 8HZ_IF FL_RTC_IsActiveFlag_8Hz + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsActiveFlag_8Hz(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ISR, RTC_ISR_8HZ_IF_Msk) == (RTC_ISR_8HZ_IF_Msk)); +} + +/** + * @brief Clear RTC 4Hz Interrupt Flag + * @rmtoll ISR 4HZ_IF FL_RTC_ClearFlag_4Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_ClearFlag_4Hz(RTC_Type *RTCx) +{ + WRITE_REG(RTCx->ISR, RTC_ISR_4HZ_IF_Msk); +} + +/** + * @brief Get RTC 4Hz Interrupt Flag + * @rmtoll ISR 4HZ_IF FL_RTC_IsActiveFlag_4Hz + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsActiveFlag_4Hz(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ISR, RTC_ISR_4HZ_IF_Msk) == (RTC_ISR_4HZ_IF_Msk)); +} + +/** + * @brief Clear RTC 2Hz Interrupt Flag + * @rmtoll ISR 2HZ_IF FL_RTC_ClearFlag_2Hz + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_ClearFlag_2Hz(RTC_Type *RTCx) +{ + WRITE_REG(RTCx->ISR, RTC_ISR_2HZ_IF_Msk); +} + +/** + * @brief Get RTC 2Hz Interrupt Flag + * @rmtoll ISR 2HZ_IF FL_RTC_IsActiveFlag_2Hz + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsActiveFlag_2Hz(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ISR, RTC_ISR_2HZ_IF_Msk) == (RTC_ISR_2HZ_IF_Msk)); +} + +/** + * @brief Clear RTC Second Interrupt Flag + * @rmtoll ISR SEC_IF FL_RTC_ClearFlag_Second + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_ClearFlag_Second(RTC_Type *RTCx) +{ + WRITE_REG(RTCx->ISR, RTC_ISR_SEC_IF_Msk); +} + +/** + * @brief Get RTC Second Interrupt Flag + * @rmtoll ISR SEC_IF FL_RTC_IsActiveFlag_Second + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsActiveFlag_Second(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ISR, RTC_ISR_SEC_IF_Msk) == (RTC_ISR_SEC_IF_Msk)); +} + +/** + * @brief Clear RTC Minute Interrupt Flag + * @rmtoll ISR MIN_IF FL_RTC_ClearFlag_Minute + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_ClearFlag_Minute(RTC_Type *RTCx) +{ + WRITE_REG(RTCx->ISR, RTC_ISR_MIN_IF_Msk); +} + +/** + * @brief Get RTC Minute Interrupt Flag + * @rmtoll ISR MIN_IF FL_RTC_IsActiveFlag_Minute + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsActiveFlag_Minute(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ISR, RTC_ISR_MIN_IF_Msk) == (RTC_ISR_MIN_IF_Msk)); +} + +/** + * @brief Clear RTC Hour Interrupt Flag + * @rmtoll ISR HOUR_IF FL_RTC_ClearFlag_Hour + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_ClearFlag_Hour(RTC_Type *RTCx) +{ + WRITE_REG(RTCx->ISR, RTC_ISR_HOUR_IF_Msk); +} + +/** + * @brief Get RTC Hour Interrupt Flag + * @rmtoll ISR HOUR_IF FL_RTC_IsActiveFlag_Hour + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsActiveFlag_Hour(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ISR, RTC_ISR_HOUR_IF_Msk) == (RTC_ISR_HOUR_IF_Msk)); +} + +/** + * @brief Clear RTC Day Interrupt Flag + * @rmtoll ISR DAY_IF FL_RTC_ClearFlag_Day + * @param RTCx RTC instance + * @retval None + */ +__STATIC_INLINE void FL_RTC_ClearFlag_Day(RTC_Type *RTCx) +{ + WRITE_REG(RTCx->ISR, RTC_ISR_DAY_IF_Msk); +} + +/** + * @brief Get RTC Day Interrupt Flag + * @rmtoll ISR DAY_IF FL_RTC_IsActiveFlag_Day + * @param RTCx RTC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_RTC_IsActiveFlag_Day(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ISR, RTC_ISR_DAY_IF_Msk) == (RTC_ISR_DAY_IF_Msk)); +} + +/** + * @brief Get RTC Second Value + * @rmtoll BCDSEC FL_RTC_ReadSecond + * @param RTCx RTC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_RTC_ReadSecond(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->BCDSEC, (0x7fU << 0U)) >> 0U); +} + +/** + * @brief Set RTC Second Value + * @rmtoll BCDSEC FL_RTC_WriteSecond + * @param RTCx RTC instance + * @param second + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteSecond(RTC_Type *RTCx, uint32_t second) +{ + MODIFY_REG(RTCx->BCDSEC, (0x7fU << 0U), (second << 0U)); +} + +/** + * @brief Get RTC Minute Value + * @rmtoll BCDMIN FL_RTC_ReadMinute + * @param RTCx RTC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_RTC_ReadMinute(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->BCDMIN, (0x7fU << 0U)) >> 0U); +} + +/** + * @brief Set RTC Minute Value + * @rmtoll BCDMIN FL_RTC_WriteMinute + * @param RTCx RTC instance + * @param minute + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteMinute(RTC_Type *RTCx, uint32_t minute) +{ + MODIFY_REG(RTCx->BCDMIN, (0x7fU << 0U), (minute << 0U)); +} + +/** + * @brief Get RTC Hour Value + * @rmtoll BCDHOUR FL_RTC_ReadHour + * @param RTCx RTC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_RTC_ReadHour(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->BCDHOUR, (0x3fU << 0U)) >> 0U); +} + +/** + * @brief Set RTC Hour Value + * @rmtoll BCDHOUR FL_RTC_WriteHour + * @param RTCx RTC instance + * @param hour + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteHour(RTC_Type *RTCx, uint32_t hour) +{ + MODIFY_REG(RTCx->BCDHOUR, (0x3fU << 0U), (hour << 0U)); +} + +/** + * @brief Get RTC Day Value + * @rmtoll BCDDAY FL_RTC_ReadDay + * @param RTCx RTC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_RTC_ReadDay(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->BCDDAY, (0x3fU << 0U)) >> 0U); +} + +/** + * @brief Set RTC Day Value + * @rmtoll BCDDAY FL_RTC_WriteDay + * @param RTCx RTC instance + * @param day + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteDay(RTC_Type *RTCx, uint32_t day) +{ + MODIFY_REG(RTCx->BCDDAY, (0x3fU << 0U), (day << 0U)); +} + +/** + * @brief Get RTC Week Value + * @rmtoll BCDWEEK FL_RTC_ReadWeek + * @param RTCx RTC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_RTC_ReadWeek(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->BCDWEEK, (0x7U << 0U)) >> 0U); +} + +/** + * @brief Set RTC Week Value + * @rmtoll BCDWEEK FL_RTC_WriteWeek + * @param RTCx RTC instance + * @param week + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteWeek(RTC_Type *RTCx, uint32_t week) +{ + MODIFY_REG(RTCx->BCDWEEK, (0x7U << 0U), (week << 0U)); +} + +/** + * @brief Get RTC Month Value + * @rmtoll BCDMONTH FL_RTC_ReadMonth + * @param RTCx RTC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_RTC_ReadMonth(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->BCDMONTH, (0x1fU << 0U)) >> 0U); +} + +/** + * @brief Set RTC Month Value + * @rmtoll BCDMONTH FL_RTC_WriteMonth + * @param RTCx RTC instance + * @param month + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteMonth(RTC_Type *RTCx, uint32_t month) +{ + MODIFY_REG(RTCx->BCDMONTH, (0x1fU << 0U), (month << 0U)); +} + +/** + * @brief Get RTC Year Value + * @rmtoll BCDYEAR FL_RTC_ReadYear + * @param RTCx RTC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_RTC_ReadYear(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->BCDYEAR, (0xffU << 0U)) >> 0U); +} + +/** + * @brief Set RTC Year Value + * @rmtoll BCDYEAR FL_RTC_WriteYear + * @param RTCx RTC instance + * @param year + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteYear(RTC_Type *RTCx, uint32_t year) +{ + MODIFY_REG(RTCx->BCDYEAR, (0xffU << 0U), (year << 0U)); +} + +/** + * @brief Get RTC Alarm Hour Value + * @rmtoll ALARM FL_RTC_ReadHourAlarm + * @param RTCx RTC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_RTC_ReadHourAlarm(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALARM, (0x3fU << 16U)) >> 16U); +} + +/** + * @brief Set RTC Alarm Hour Value + * @rmtoll ALARM FL_RTC_WriteHourAlarm + * @param RTCx RTC instance + * @param hour + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteHourAlarm(RTC_Type *RTCx, uint32_t hour) +{ + MODIFY_REG(RTCx->ALARM, (0x3fU << 16U), (hour << 16U)); +} + +/** + * @brief Get RTC Alarm Minute Value + * @rmtoll ALARM FL_RTC_ReadMinuteAlarm + * @param RTCx RTC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_RTC_ReadMinuteAlarm(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALARM, (0x7fU << 8U)) >> 8U); +} + +/** + * @brief Set RTC Alarm Minute Value + * @rmtoll ALARM FL_RTC_WriteMinuteAlarm + * @param RTCx RTC instance + * @param minute + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteMinuteAlarm(RTC_Type *RTCx, uint32_t minute) +{ + MODIFY_REG(RTCx->ALARM, (0x7fU << 8U), (minute << 8U)); +} + +/** + * @brief Get RTC Alarm Second Value + * @rmtoll ALARM FL_RTC_ReadSecondAlarm + * @param RTCx RTC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_RTC_ReadSecondAlarm(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALARM, (0x7fU << 0U)) >> 0U); +} + +/** + * @brief Set RTC Alarm Second Value + * @rmtoll ALARM FL_RTC_WriteSecondAlarm + * @param RTCx RTC instance + * @param second + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteSecondAlarm(RTC_Type *RTCx, uint32_t second) +{ + MODIFY_REG(RTCx->ALARM, (0x7fU << 0U), (second << 0U)); +} + +/** + * @brief Set RTC Output Time Mark Signal + * @rmtoll TMSEL TMSEL FL_RTC_SetTimeMarkOutput + * @param RTCx RTC instance + * @param markSelect This parameter can be one of the following values: + * @arg @ref FL_RTC_TIME_MARK_SECOND + * @arg @ref FL_RTC_TIME_MARK_MINUTE + * @arg @ref FL_RTC_TIME_MARK_HOUR + * @arg @ref FL_RTC_TIME_MARK_DAY + * @arg @ref FL_RTC_TIME_MARK_ALARM + * @arg @ref FL_RTC_TIME_MARK_32_SEC + * @arg @ref FL_RTC_TIME_MARK_SECOND_REVERSE + * @arg @ref FL_RTC_TIME_MARK_MINUTE_REVERSE + * @arg @ref FL_RTC_TIME_MARK_HOUR_REVERSE + * @arg @ref FL_RTC_TIME_MARK_DAY_REVERSE + * @arg @ref FL_RTC_TIME_MARK_ALARM_REVERSE + * @arg @ref FL_RTC_TIME_MARK_SEC + * @retval None + */ +__STATIC_INLINE void FL_RTC_SetTimeMarkOutput(RTC_Type *RTCx, uint32_t markSelect) +{ + MODIFY_REG(RTCx->TMSEL, RTC_TMSEL_TMSEL_Msk, markSelect); +} + +/** + * @brief Get RTC Output Time Mark Signal Setting + * @rmtoll TMSEL TMSEL FL_RTC_GetTimeMarkOutput + * @param RTCx RTC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_RTC_TIME_MARK_SECOND + * @arg @ref FL_RTC_TIME_MARK_MINUTE + * @arg @ref FL_RTC_TIME_MARK_HOUR + * @arg @ref FL_RTC_TIME_MARK_DAY + * @arg @ref FL_RTC_TIME_MARK_ALARM + * @arg @ref FL_RTC_TIME_MARK_32_SEC + * @arg @ref FL_RTC_TIME_MARK_SECOND_REVERSE + * @arg @ref FL_RTC_TIME_MARK_MINUTE_REVERSE + * @arg @ref FL_RTC_TIME_MARK_HOUR_REVERSE + * @arg @ref FL_RTC_TIME_MARK_DAY_REVERSE + * @arg @ref FL_RTC_TIME_MARK_ALARM_REVERSE + * @arg @ref FL_RTC_TIME_MARK_SEC + */ +__STATIC_INLINE uint32_t FL_RTC_GetTimeMarkOutput(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TMSEL, RTC_TMSEL_TMSEL_Msk)); +} + +/** + * @brief Get RTC Adjust Value + * @rmtoll ADJUST FL_RTC_ReadAdjustValue + * @param RTCx RTC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_RTC_ReadAdjustValue(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ADJUST, (0x1ffU << 0U)) >> 0U); +} + +/** + * @brief Set RTC Adjust Value + * @rmtoll ADJUST FL_RTC_WriteAdjustValue + * @param RTCx RTC instance + * @param adjustValue + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteAdjustValue(RTC_Type *RTCx, uint32_t adjustValue) +{ + MODIFY_REG(RTCx->ADJUST, (0x1ffU << 0U), (adjustValue << 0U)); +} + +/** + * @brief Set RTC Adjust Direction + * @rmtoll ADSIGN ADSIGN FL_RTC_SetAdjustDirection + * @param RTCx RTC instance + * @param adjustDir This parameter can be one of the following values: + * @arg @ref FL_RTC_ADJUST_DIR_INCREASE + * @arg @ref FL_RTC_ADJUST_DIR_DECREASE + * @retval None + */ +__STATIC_INLINE void FL_RTC_SetAdjustDirection(RTC_Type *RTCx, uint32_t adjustDir) +{ + MODIFY_REG(RTCx->ADSIGN, RTC_ADSIGN_ADSIGN_Msk, adjustDir); +} + +/** + * @brief Get RTC Adjust Direction + * @rmtoll ADSIGN ADSIGN FL_RTC_GetAdjustDirection + * @param RTCx RTC instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_RTC_ADJUST_DIR_INCREASE + * @arg @ref FL_RTC_ADJUST_DIR_DECREASE + */ +__STATIC_INLINE uint32_t FL_RTC_GetAdjustDirection(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ADSIGN, RTC_ADSIGN_ADSIGN_Msk)); +} + +/** + * @brief Get RTC MilliSecond Counter Value + * @rmtoll SBSCNT FL_RTC_ReadMilliSecondCounter + * @param RTCx RTC instance + * @retval + */ +__STATIC_INLINE uint32_t FL_RTC_ReadMilliSecondCounter(RTC_Type *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->SBSCNT, (0xffU << 0U)) >> 0U); +} + +/** + * @brief Set RTC MilliSecond Counter Value + * @rmtoll SBSCNT FL_RTC_WriteMilliSecondCounter + * @param RTCx RTC instance + * @param milliSecondCount + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteMilliSecondCounter(RTC_Type *RTCx, uint32_t milliSecondCount) +{ + MODIFY_REG(RTCx->SBSCNT, (0xffU << 0U), (milliSecondCount << 0U)); +} + +/** + * @brief Get RTC Backup Register + * @rmtoll BACKUP FL_RTC_ReadBackupRegisters + * @param RTCx RTC instance + * @param backupRegNum This parameter can be one of the following values: + * @arg @ref FL_RTC_BACKUP_0 + * @arg @ref FL_RTC_BACKUP_1 + * @arg @ref FL_RTC_BACKUP_2 + * @arg @ref FL_RTC_BACKUP_3 + * @arg @ref FL_RTC_BACKUP_4 + * @arg @ref FL_RTC_BACKUP_5 + * @arg @ref FL_RTC_BACKUP_6 + * @arg @ref FL_RTC_BACKUP_7 + * @retval + */ +__STATIC_INLINE uint32_t FL_RTC_ReadBackupRegisters(RTC_Type *RTCx, uint32_t backupRegNum) +{ + FL_RTC_Backup_ADDR *addr = (FL_RTC_Backup_ADDR *)&RTCx->BKR0; + return (uint32_t)(READ_BIT(addr->backup[backupRegNum], 0xFFFFFFFFu)); +} + +/** + * @brief Set RTC Backup Register + * @rmtoll BACKUP FL_RTC_WriteBackupRegisters + * @param RTCx RTC instance + * @param backupReg + * @param backupNum + * @retval None + */ +__STATIC_INLINE void FL_RTC_WriteBackupRegisters(RTC_Type *RTCx, uint32_t backupReg, uint32_t backupNum) +{ + FL_RTC_Backup_ADDR *addr = (FL_RTC_Backup_ADDR *)&RTCx->BKR0; + MODIFY_REG(addr->backup[backupNum], (0xFFFFFFFFu), backupReg); +} + +/** + * @} + */ + +/** @defgroup RTC_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_RTC_DeInit(RTC_Type *RTCx); +void FL_RTC_StructInit(FL_RTC_InitTypeDef *initStruct); +FL_ErrorStatus FL_RTC_GetTime(RTC_Type *RTCx, FL_RTC_InitTypeDef *initStruct); +FL_ErrorStatus FL_RTC_Init(RTC_Type *RTCx, FL_RTC_InitTypeDef *initStruct); +FL_ErrorStatus FL_RTC_ConfigTime(RTC_Type *RTCx, FL_RTC_InitTypeDef *initStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_RTC_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.1 @ 2020-09-22*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_spi.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_spi.h new file mode 100644 index 0000000000..6b2cd02274 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_spi.h @@ -0,0 +1,1252 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_spi.h + * @author FMSH Application Team + * @brief Head file of SPI FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_SPI_H +#define __FM33LC0XX_FL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup SPI_FL_ES_INIT SPI Exported Init structures + * @{ + */ + +/** + * @brief FL SPI Init Sturcture definition + */ +typedef struct +{ + /*! 传输模式 单双工 */ + uint32_t transferMode; + /*! 主从模式 */ + uint32_t mode; + /*! 数据位宽 */ + uint32_t dataWidth; + /*! 时钟极性 */ + uint32_t clockPolarity; + /*! 时钟相位 */ + uint32_t clockPhase; + /*! NSS 脚使能软件控制 */ + uint32_t softControl; + /*! 通讯速率 */ + uint32_t baudRate; + /*! Bit方向 */ + uint32_t bitOrder; + +} FL_SPI_InitTypeDef; + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup SPI_FL_Exported_Constants SPI Exported Constants + * @{ + */ + +#define SPI_CR1_IOSWAP_Pos (11U) +#define SPI_CR1_IOSWAP_Msk (0x1U << SPI_CR1_IOSWAP_Pos) +#define SPI_CR1_IOSWAP SPI_CR1_IOSWAP_Msk + +#define SPI_CR1_MSPA_Pos (10U) +#define SPI_CR1_MSPA_Msk (0x1U << SPI_CR1_MSPA_Pos) +#define SPI_CR1_MSPA SPI_CR1_MSPA_Msk + +#define SPI_CR1_SSPA_Pos (9U) +#define SPI_CR1_SSPA_Msk (0x1U << SPI_CR1_SSPA_Pos) +#define SPI_CR1_SSPA SPI_CR1_SSPA_Msk + +#define SPI_CR1_MM_Pos (8U) +#define SPI_CR1_MM_Msk (0x1U << SPI_CR1_MM_Pos) +#define SPI_CR1_MM SPI_CR1_MM_Msk + +#define SPI_CR1_WAIT_Pos (6U) +#define SPI_CR1_WAIT_Msk (0x3U << SPI_CR1_WAIT_Pos) +#define SPI_CR1_WAIT SPI_CR1_WAIT_Msk + +#define SPI_CR1_BAUD_Pos (3U) +#define SPI_CR1_BAUD_Msk (0x7U << SPI_CR1_BAUD_Pos) +#define SPI_CR1_BAUD SPI_CR1_BAUD_Msk + +#define SPI_CR1_LSBF_Pos (2U) +#define SPI_CR1_LSBF_Msk (0x1U << SPI_CR1_LSBF_Pos) +#define SPI_CR1_LSBF SPI_CR1_LSBF_Msk + +#define SPI_CR1_CPOL_Pos (1U) +#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) +#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk + +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk + +#define SPI_CR2_DUMMY_EN_Pos (15U) +#define SPI_CR2_DUMMY_EN_Msk (0x1U << SPI_CR2_DUMMY_EN_Pos) +#define SPI_CR2_DUMMY_EN SPI_CR2_DUMMY_EN_Msk + +#define SPI_CR2_RXO_Pos (11U) +#define SPI_CR2_RXO_Msk (0x1U << SPI_CR2_RXO_Pos) +#define SPI_CR2_RXO SPI_CR2_RXO_Msk + +#define SPI_CR2_DLEN_Pos (9U) +#define SPI_CR2_DLEN_Msk (0x3U << SPI_CR2_DLEN_Pos) +#define SPI_CR2_DLEN SPI_CR2_DLEN_Msk + +#define SPI_CR2_HALFDUPLEX_Pos (8U) +#define SPI_CR2_HALFDUPLEX_Msk (0x1U << SPI_CR2_HALFDUPLEX_Pos) +#define SPI_CR2_HALFDUPLEX SPI_CR2_HALFDUPLEX_Msk + +#define SPI_CR2_HD_RW_Pos (7U) +#define SPI_CR2_HD_RW_Msk (0x1U << SPI_CR2_HD_RW_Pos) +#define SPI_CR2_HD_RW SPI_CR2_HD_RW_Msk + +#define SPI_CR2_CMD8B_Pos (6U) +#define SPI_CR2_CMD8B_Msk (0x1U << SPI_CR2_CMD8B_Pos) +#define SPI_CR2_CMD8B SPI_CR2_CMD8B_Msk + +#define SPI_CR2_SSNM_Pos (5U) +#define SPI_CR2_SSNM_Msk (0x1U << SPI_CR2_SSNM_Pos) +#define SPI_CR2_SSNM SPI_CR2_SSNM_Msk + +#define SPI_CR2_TXO_AC_Pos (4U) +#define SPI_CR2_TXO_AC_Msk (0x1U << SPI_CR2_TXO_AC_Pos) +#define SPI_CR2_TXO_AC SPI_CR2_TXO_AC_Msk + +#define SPI_CR2_TXO_Pos (3U) +#define SPI_CR2_TXO_Msk (0x1U << SPI_CR2_TXO_Pos) +#define SPI_CR2_TXO SPI_CR2_TXO_Msk + +#define SPI_CR2_SSN_Pos (2U) +#define SPI_CR2_SSN_Msk (0x1U << SPI_CR2_SSN_Pos) +#define SPI_CR2_SSN SPI_CR2_SSN_Msk + +#define SPI_CR2_SSNSEN_Pos (1U) +#define SPI_CR2_SSNSEN_Msk (0x1U << SPI_CR2_SSNSEN_Pos) +#define SPI_CR2_SSNSEN SPI_CR2_SSNSEN_Msk + +#define SPI_CR2_SPIEN_Pos (0U) +#define SPI_CR2_SPIEN_Msk (0x1U << SPI_CR2_SPIEN_Pos) +#define SPI_CR2_SPIEN SPI_CR2_SPIEN_Msk + +#define SPI_CR3_TXBFC_Pos (3U) +#define SPI_CR3_TXBFC_Msk (0x1U << SPI_CR3_TXBFC_Pos) +#define SPI_CR3_TXBFC SPI_CR3_TXBFC_Msk + +#define SPI_CR3_RXBFC_Pos (2U) +#define SPI_CR3_RXBFC_Msk (0x1U << SPI_CR3_RXBFC_Pos) +#define SPI_CR3_RXBFC SPI_CR3_RXBFC_Msk + +#define SPI_CR3_MERRC_Pos (1U) +#define SPI_CR3_MERRC_Msk (0x1U << SPI_CR3_MERRC_Pos) +#define SPI_CR3_MERRC SPI_CR3_MERRC_Msk + +#define SPI_CR3_SERRC_Pos (0U) +#define SPI_CR3_SERRC_Msk (0x1U << SPI_CR3_SERRC_Pos) +#define SPI_CR3_SERRC SPI_CR3_SERRC_Msk + +#define SPI_IER_ERRIE_Pos (2U) +#define SPI_IER_ERRIE_Msk (0x1U << SPI_IER_ERRIE_Pos) +#define SPI_IER_ERRIE SPI_IER_ERRIE_Msk + +#define SPI_IER_TXIE_Pos (1U) +#define SPI_IER_TXIE_Msk (0x1U << SPI_IER_TXIE_Pos) +#define SPI_IER_TXIE SPI_IER_TXIE_Msk + +#define SPI_IER_RXIE_Pos (0U) +#define SPI_IER_RXIE_Msk (0x1U << SPI_IER_RXIE_Pos) +#define SPI_IER_RXIE SPI_IER_RXIE_Msk + +#define SPI_ISR_DCN_TX_Pos (12U) +#define SPI_ISR_DCN_TX_Msk (0x1U << SPI_ISR_DCN_TX_Pos) +#define SPI_ISR_DCN_TX SPI_ISR_DCN_TX_Msk + +#define SPI_ISR_RXCOL_Pos (10U) +#define SPI_ISR_RXCOL_Msk (0x1U << SPI_ISR_RXCOL_Pos) +#define SPI_ISR_RXCOL SPI_ISR_RXCOL_Msk + +#define SPI_ISR_TXCOL_Pos (9U) +#define SPI_ISR_TXCOL_Msk (0x1U << SPI_ISR_TXCOL_Pos) +#define SPI_ISR_TXCOL SPI_ISR_TXCOL_Msk + +#define SPI_ISR_BUSY_Pos (8U) +#define SPI_ISR_BUSY_Msk (0x1U << SPI_ISR_BUSY_Pos) +#define SPI_ISR_BUSY SPI_ISR_BUSY_Msk + +#define SPI_ISR_MERR_Pos (6U) +#define SPI_ISR_MERR_Msk (0x1U << SPI_ISR_MERR_Pos) +#define SPI_ISR_MERR SPI_ISR_MERR_Msk + +#define SPI_ISR_SERR_Pos (5U) +#define SPI_ISR_SERR_Msk (0x1U << SPI_ISR_SERR_Pos) +#define SPI_ISR_SERR SPI_ISR_SERR_Msk + +#define SPI_ISR_TXBE_Pos (1U) +#define SPI_ISR_TXBE_Msk (0x1U << SPI_ISR_TXBE_Pos) +#define SPI_ISR_TXBE SPI_ISR_TXBE_Msk + +#define SPI_ISR_RXBF_Pos (0U) +#define SPI_ISR_RXBF_Msk (0x1U << SPI_ISR_RXBF_Pos) +#define SPI_ISR_RXBF SPI_ISR_RXBF_Msk + + + + + + +#define FL_SPI_MASTER_SAMPLING_NORMAL (0x0U << SPI_CR1_MSPA_Pos) +#define FL_SPI_MASTER_SAMPLING_DELAY_HALFCLK (0x1U << SPI_CR1_MSPA_Pos) + + +#define FL_SPI_SLAVE_SAMPLING_NORMAL (0x0U << SPI_CR1_SSPA_Pos) +#define FL_SPI_SLAVE_SAMPLING_ADVANCE_HALFCLK (0x1U << SPI_CR1_SSPA_Pos) + + +#define FL_SPI_WORK_MODE_SLAVE (0x0U << SPI_CR1_MM_Pos) +#define FL_SPI_WORK_MODE_MASTER (0x1U << SPI_CR1_MM_Pos) + + +#define FL_SPI_SEND_WAIT_1 (0x0U << SPI_CR1_WAIT_Pos) +#define FL_SPI_SEND_WAIT_2 (0x1U << SPI_CR1_WAIT_Pos) +#define FL_SPI_SEND_WAIT_3 (0x2U << SPI_CR1_WAIT_Pos) +#define FL_SPI_SEND_WAIT_4 (0x3U << SPI_CR1_WAIT_Pos) + + +#define FL_SPI_CLK_DIV2 (0x0U << SPI_CR1_BAUD_Pos) +#define FL_SPI_CLK_DIV4 (0x1U << SPI_CR1_BAUD_Pos) +#define FL_SPI_CLK_DIV8 (0x2U << SPI_CR1_BAUD_Pos) +#define FL_SPI_CLK_DIV16 (0x3U << SPI_CR1_BAUD_Pos) +#define FL_SPI_CLK_DIV32 (0x4U << SPI_CR1_BAUD_Pos) +#define FL_SPI_CLK_DIV64 (0x5U << SPI_CR1_BAUD_Pos) +#define FL_SPI_CLK_DIV128 (0x6U << SPI_CR1_BAUD_Pos) +#define FL_SPI_CLK_DIV256 (0x7U << SPI_CR1_BAUD_Pos) + +#define FL_SPI_BAUDRATE_DIV2 (0x0U << SPI_CR1_BAUD_Pos) +#define FL_SPI_BAUDRATE_DIV4 (0x1U << SPI_CR1_BAUD_Pos) +#define FL_SPI_BAUDRATE_DIV8 (0x2U << SPI_CR1_BAUD_Pos) +#define FL_SPI_BAUDRATE_DIV16 (0x3U << SPI_CR1_BAUD_Pos) +#define FL_SPI_BAUDRATE_DIV32 (0x4U << SPI_CR1_BAUD_Pos) +#define FL_SPI_BAUDRATE_DIV64 (0x5U << SPI_CR1_BAUD_Pos) +#define FL_SPI_BAUDRATE_DIV128 (0x6U << SPI_CR1_BAUD_Pos) +#define FL_SPI_BAUDRATE_DIV256 (0x7U << SPI_CR1_BAUD_Pos) + +#define FL_SPI_BIT_ORDER_MSB_FIRST (0x0U << SPI_CR1_LSBF_Pos) +#define FL_SPI_BIT_ORDER_LSB_FIRST (0x1U << SPI_CR1_LSBF_Pos) + + +#define FL_SPI_POLARITY_NORMAL (0x0U << SPI_CR1_CPOL_Pos) +#define FL_SPI_POLARITY_INVERT (0x1U << SPI_CR1_CPOL_Pos) + + +#define FL_SPI_PHASE_EDGE1 (0x0U << SPI_CR1_CPHA_Pos) +#define FL_SPI_PHASE_EDGE2 (0x1U << SPI_CR1_CPHA_Pos) + + +#define FL_SPI_DATA_WIDTH_8B (0x0U << SPI_CR2_DLEN_Pos) +#define FL_SPI_DATA_WIDTH_16B (0x1U << SPI_CR2_DLEN_Pos) +#define FL_SPI_DATA_WIDTH_24B (0x2U << SPI_CR2_DLEN_Pos) +#define FL_SPI_DATA_WIDTH_32B (0x3U << SPI_CR2_DLEN_Pos) + + +#define FL_SPI_TRANSFER_MODE_FULL_DUPLEX (0x0U << SPI_CR2_HALFDUPLEX_Pos) +#define FL_SPI_TRANSFER_MODE_HALF_DUPLEX (0x1U << SPI_CR2_HALFDUPLEX_Pos) + + +#define FL_SPI_HALF_DUPLEX_TX (0x0U << SPI_CR2_HD_RW_Pos) +#define FL_SPI_HALF_DUPLEX_RX (0x1U << SPI_CR2_HD_RW_Pos) + + +#define FL_SPI_HALF_DUPLEX_CMDLEN_DLEN (0x0U << SPI_CR2_CMD8B_Pos) +#define FL_SPI_HALF_DUPLEX_CMDLEN_8B (0x1U << SPI_CR2_CMD8B_Pos) + +#define FL_SPI_HALFDUPLEX_CMDLEN_DLEN (0x0U << SPI_CR2_CMD8B_Pos) +#define FL_SPI_HALFDUPLEX_CMDLEN_8B (0x1U << SPI_CR2_CMD8B_Pos) + +#define FL_SPI_HARDWARE_SSN_AUTO_HIGH (0x0U << SPI_CR2_SSNM_Pos) +#define FL_SPI_HARDWARE_SSN_KEEP_LOW (0x1U << SPI_CR2_SSNM_Pos) + + +#define FL_SPI_SSN_LOW (0x0U << SPI_CR2_SSN_Pos) +#define FL_SPI_SSN_HIGH (0x1U << SPI_CR2_SSN_Pos) + + +#define FL_SPI_FRAME_MODE_CMD (0x0U << SPI_ISR_DCN_TX_Pos) +#define FL_SPI_FRAME_MODE_DATA (0x1U << SPI_ISR_DCN_TX_Pos) + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup SPI_FL_Exported_Functions SPI Exported Functions + * @{ + */ + +/** + * @brief Enable SPI IO Pin Swap + * @rmtoll CR1 IOSWAP FL_SPI_EnablePinSwap + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_EnablePinSwap(SPI_Type *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_IOSWAP_Msk); +} + +/** + * @brief Get SPI IO Pin Swap State + * @rmtoll CR1 IOSWAP FL_SPI_IsEnabledPinSwap + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsEnabledPinSwap(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_IOSWAP_Msk) == SPI_CR1_IOSWAP_Msk); +} + +/** + * @brief Disable SPI IO Pin Swap + * @rmtoll CR1 IOSWAP FL_SPI_DisablePinSwap + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_DisablePinSwap(SPI_Type *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_IOSWAP_Msk); +} + +/** + * @brief Set Master Sampling Position Adjustment + * @rmtoll CR1 MSPA FL_SPI_SetMasterSamplingAdjust + * @param SPIx SPI instance + * @param adjust This parameter can be one of the following values: + * @arg @ref FL_SPI_MASTER_SAMPLING_NORMAL + * @arg @ref FL_SPI_MASTER_SAMPLING_DELAY_HALFCLK + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetMasterSamplingAdjust(SPI_Type *SPIx, uint32_t adjust) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_MSPA_Msk, adjust); +} + +/** + * @brief Get Master Sampling Position Adjustment + * @rmtoll CR1 MSPA FL_SPI_GetMasterSamplingAdjust + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SPI_MASTER_SAMPLING_NORMAL + * @arg @ref FL_SPI_MASTER_SAMPLING_DELAY_HALFCLK + */ +__STATIC_INLINE uint32_t FL_SPI_GetMasterSamplingAdjust(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSPA_Msk)); +} + +/** + * @brief Set Slave Sending Position Adjustment + * @rmtoll CR1 SSPA FL_SPI_SetSlaveSamplingAdjust + * @param SPIx SPI instance + * @param adjust This parameter can be one of the following values: + * @arg @ref FL_SPI_SLAVE_SAMPLING_NORMAL + * @arg @ref FL_SPI_SLAVE_SAMPLING_ADVANCE_HALFCLK + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetSlaveSamplingAdjust(SPI_Type *SPIx, uint32_t adjust) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_SSPA_Msk, adjust); +} + +/** + * @brief Get Slave Sending Position Adjustment + * @rmtoll CR1 SSPA FL_SPI_GetSlaveSamplingAdjust + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SPI_SLAVE_SAMPLING_NORMAL + * @arg @ref FL_SPI_SLAVE_SAMPLING_ADVANCE_HALFCLK + */ +__STATIC_INLINE uint32_t FL_SPI_GetSlaveSamplingAdjust(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSPA_Msk)); +} + +/** + * @brief Set SPI Working Mode + * @rmtoll CR1 MM FL_SPI_SetWorkMode + * @param SPIx SPI instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_SPI_WORK_MODE_SLAVE + * @arg @ref FL_SPI_WORK_MODE_MASTER + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetWorkMode(SPI_Type *SPIx, uint32_t mode) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_MM_Msk, mode); +} + +/** + * @brief Get SPI Working Mode + * @rmtoll CR1 MM FL_SPI_GetWorkMode + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SPI_WORK_MODE_SLAVE + * @arg @ref FL_SPI_WORK_MODE_MASTER + */ +__STATIC_INLINE uint32_t FL_SPI_GetWorkMode(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MM_Msk)); +} + +/** + * @brief Set SPI Send Wait Cycle Length in Master Mode + * @rmtoll CR1 WAIT FL_SPI_SetSendWait + * @param SPIx SPI instance + * @param wait This parameter can be one of the following values: + * @arg @ref FL_SPI_SEND_WAIT_1 + * @arg @ref FL_SPI_SEND_WAIT_2 + * @arg @ref FL_SPI_SEND_WAIT_3 + * @arg @ref FL_SPI_SEND_WAIT_4 + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetSendWait(SPI_Type *SPIx, uint32_t wait) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_WAIT_Msk, wait); +} + +/** + * @brief Get SPI Send Wait Cycle Length in Master Mode + * @rmtoll CR1 WAIT FL_SPI_GetSendWait + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + */ +__STATIC_INLINE uint32_t FL_SPI_GetSendWait(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_WAIT_Msk)); +} + +/** + * @brief Set SPI Baudrate in Master Mode + * @rmtoll CR1 BAUD FL_SPI_SetClockDivision + * @param SPIx SPI instance + * @param clock This parameter can be one of the following values: + * @arg @ref FL_SPI_CLK_DIV2 + * @arg @ref FL_SPI_CLK_DIV4 + * @arg @ref FL_SPI_CLK_DIV8 + * @arg @ref FL_SPI_CLK_DIV16 + * @arg @ref FL_SPI_CLK_DIV32 + * @arg @ref FL_SPI_CLK_DIV64 + * @arg @ref FL_SPI_CLK_DIV128 + * @arg @ref FL_SPI_CLK_DIV256 + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetClockDivision(SPI_Type *SPIx, uint32_t clock) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_BAUD_Msk, clock); +} + +/** + * @brief Get SPI Baudrate in Master Mode + * @rmtoll CR1 BAUD FL_SPI_GetClockDivision + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SPI_BAUDRATE_DIV2 + * @arg @ref FL_SPI_BAUDRATE_DIV4 + * @arg @ref FL_SPI_BAUDRATE_DIV8 + * @arg @ref FL_SPI_BAUDRATE_DIV16 + * @arg @ref FL_SPI_BAUDRATE_DIV32 + * @arg @ref FL_SPI_BAUDRATE_DIV64 + * @arg @ref FL_SPI_BAUDRATE_DIV128 + * @arg @ref FL_SPI_BAUDRATE_DIV256 + */ +__STATIC_INLINE uint32_t FL_SPI_GetClockDivision(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BAUD_Msk)); +} + +/** + * @brief Set SPI Bit Order + * @rmtoll CR1 LSBF FL_SPI_SetBitOrder + * @param SPIx SPI instance + * @param bitOrder This parameter can be one of the following values: + * @arg @ref FL_SPI_BIT_ORDER_MSB_FIRST + * @arg @ref FL_SPI_BIT_ORDER_LSB_FIRST + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetBitOrder(SPI_Type *SPIx, uint32_t bitOrder) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_LSBF_Msk, bitOrder); +} + +/** + * @brief Get SPI Bit Order + * @rmtoll CR1 LSBF FL_SPI_GetBitOrder + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SPI_BIT_ORDER_MSB_FIRST + * @arg @ref FL_SPI_BIT_ORDER_LSB_FIRST + */ +__STATIC_INLINE uint32_t FL_SPI_GetBitOrder(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBF_Msk)); +} + +/** + * @brief Set SPI Clock Polarity + * @rmtoll CR1 CPOL FL_SPI_SetClockPolarity + * @param SPIx SPI instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_SPI_POLARITY_NORMAL + * @arg @ref FL_SPI_POLARITY_INVERT + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetClockPolarity(SPI_Type *SPIx, uint32_t polarity) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL_Msk, polarity); +} + +/** + * @brief Get SPI Clock Polarity + * @rmtoll CR1 CPOL FL_SPI_GetClockPolarity + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SPI_POLARITY_NORMAL + * @arg @ref FL_SPI_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_SPI_GetClockPolarity(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL_Msk)); +} + +/** + * @brief Set SPI Clock Phase + * @rmtoll CR1 CPHA FL_SPI_SetClockPhase + * @param SPIx SPI instance + * @param phase This parameter can be one of the following values: + * @arg @ref FL_SPI_PHASE_EDGE1 + * @arg @ref FL_SPI_PHASE_EDGE2 + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetClockPhase(SPI_Type *SPIx, uint32_t phase) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA_Msk, phase); +} + +/** + * @brief Get SPI Clock Phase + * @rmtoll CR1 CPHA FL_SPI_GetClockPhase + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SPI_PHASE_EDGE1 + * @arg @ref FL_SPI_PHASE_EDGE2 + */ +__STATIC_INLINE uint32_t FL_SPI_GetClockPhase(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA_Msk)); +} + +/** + * @brief Enable SPI Dummy Cycle Setting Under 4-lines Half Duplex Mode + * @rmtoll CR2 DUMMY_EN FL_SPI_EnableDummyCycle + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_EnableDummyCycle(SPI_Type *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_DUMMY_EN_Msk); +} + +/** + * @brief Disable SPI Dummy Cycle Setting Under 4-lines Half Duplex Mode + * @rmtoll CR2 DUMMY_EN FL_SPI_DisableDummyCycle + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_DisableDummyCycle(SPI_Type *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_DUMMY_EN_Msk); +} + +/** + * @brief Get SPI Dummy Cycle Mode Setting + * @rmtoll CR2 DUMMY_EN FL_SPI_IsEnabledDummyCycle + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsEnabledDummyCycle(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DUMMY_EN_Msk) == SPI_CR2_DUMMY_EN_Msk); +} + +/** + * @brief Enable SPI Receive Only Mode + * @rmtoll CR2 RXO FL_SPI_EnableRXOnlyMode + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_EnableRXOnlyMode(SPI_Type *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXO_Msk); +} + +/** + * @brief Disable SPI Receive Only Mode Setting + * @rmtoll CR2 RXO FL_SPI_DisableRXOnlyMode + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_DisableRXOnlyMode(SPI_Type *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXO_Msk); +} + +/** + * @brief Get SPI Receive Only Mode state + * @rmtoll CR2 RXO FL_SPI_IsEnabledRXOnlyMode + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsEnabledRXOnlyMode(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_RXO_Msk) == SPI_CR2_RXO_Msk); +} + +/** + * @brief Set SPI Data Width + * @rmtoll CR2 DLEN FL_SPI_SetDataWidth + * @param SPIx SPI instance + * @param width This parameter can be one of the following values: + * @arg @ref FL_SPI_DATA_WIDTH_8B + * @arg @ref FL_SPI_DATA_WIDTH_16B + * @arg @ref FL_SPI_DATA_WIDTH_24B + * @arg @ref FL_SPI_DATA_WIDTH_32B + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetDataWidth(SPI_Type *SPIx, uint32_t width) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_DLEN_Msk, width); +} + +/** + * @brief Get SPI Data Width + * @rmtoll CR2 DLEN FL_SPI_GetDataWidth + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SPI_DATA_WIDTH_8B + * @arg @ref FL_SPI_DATA_WIDTH_16B + * @arg @ref FL_SPI_DATA_WIDTH_24B + * @arg @ref FL_SPI_DATA_WIDTH_32B + */ +__STATIC_INLINE uint32_t FL_SPI_GetDataWidth(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DLEN_Msk)); +} + +/** + * @brief Set SPI Transfer Mode + * @rmtoll CR2 HALFDUPLEX FL_SPI_SetTransferMode + * @param SPIx SPI instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_SPI_TRANSFER_MODE_FULL_DUPLEX + * @arg @ref FL_SPI_TRANSFER_MODE_HALF_DUPLEX + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetTransferMode(SPI_Type *SPIx, uint32_t mode) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_HALFDUPLEX_Msk, mode); +} + +/** + * @brief Get SPI Transfer Mode + * @rmtoll CR2 HALFDUPLEX FL_SPI_GetTransferMode + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SPI_TRANSFER_MODE_FULL_DUPLEX + * @arg @ref FL_SPI_TRANSFER_MODE_HALF_DUPLEX + */ +__STATIC_INLINE uint32_t FL_SPI_GetTransferMode(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_HALFDUPLEX_Msk)); +} + +/** + * @brief Set SPI Transfer Direction Under Half-Duplex Mode + * @rmtoll CR2 HD_RW FL_SPI_SetTransferDirection + * @param SPIx SPI instance + * @param direction This parameter can be one of the following values: + * @arg @ref FL_SPI_HALF_DUPLEX_TX + * @arg @ref FL_SPI_HALF_DUPLEX_RX + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetTransferDirection(SPI_Type *SPIx, uint32_t direction) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_HD_RW_Msk, direction); +} + +/** + * @brief Get SPI Transfer Direction Under Half-Duplex Mode + * @rmtoll CR2 HD_RW FL_SPI_GetTransferDirection + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SPI_HALF_DUPLEX_TX + * @arg @ref FL_SPI_HALF_DUPLEX_RX + */ +__STATIC_INLINE uint32_t FL_SPI_GetTransferDirection(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_HD_RW_Msk)); +} + +/** + * @brief Set Command Frame Length Under Half-Duplex Mode + * @rmtoll CR2 CMD8B FL_SPI_SetHalfDuplexCommandLength + * @param SPIx SPI instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_SPI_HALF_DUPLEX_CMDLEN_DLEN + * @arg @ref FL_SPI_HALF_DUPLEX_CMDLEN_8B + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetHalfDuplexCommandLength(SPI_Type *SPIx, uint32_t mode) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_CMD8B_Msk, mode); +} + +/** + * @brief Get Command Frame Length Under Half-Duplex Mode + * @rmtoll CR2 CMD8B FL_SPI_GetHalfDuplexCommandLength + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SPI_HALFDUPLEX_CMDLEN_DLEN + * @arg @ref FL_SPI_HALFDUPLEX_CMDLEN_8B + */ +__STATIC_INLINE uint32_t FL_SPI_GetHalfDuplexCommandLength(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_CMD8B_Msk)); +} + +/** + * @brief Set SPI SSN Hard Pin Mode + * @rmtoll CR2 SSNM FL_SPI_SetHardwareSSNMode + * @param SPIx SPI instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_SPI_HARDWARE_SSN_AUTO_HIGH + * @arg @ref FL_SPI_HARDWARE_SSN_KEEP_LOW + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetHardwareSSNMode(SPI_Type *SPIx, uint32_t mode) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_SSNM_Msk, mode); +} + +/** + * @brief Get SPI SSN Hard Pin Mode + * @rmtoll CR2 SSNM FL_SPI_GetHardwareSSNMode + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SPI_HARDWARE_SSN_AUTO_HIGH + * @arg @ref FL_SPI_HARDWARE_SSN_KEEP_LOW + */ +__STATIC_INLINE uint32_t FL_SPI_GetHardwareSSNMode(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_SSNM_Msk)); +} + +/** + * @brief Enabel TX Only Mode Auto Disable + * @rmtoll CR2 TXO_AC FL_SPI_EnableTXOnlyModeAutoDisable + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_EnableTXOnlyModeAutoDisable(SPI_Type *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXO_AC_Msk); +} + +/** + * @brief Disable TX Only Mode Auto Disable + * @rmtoll CR2 TXO_AC FL_SPI_DisableTXOnlyModeAutoDisable + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_DisableTXOnlyModeAutoDisable(SPI_Type *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXO_AC_Msk); +} + +/** + * @brief Get TX Only Mode Auto Disable Setting + * @rmtoll CR2 TXO_AC FL_SPI_IsEnabledTXOnlyModeAutoDisable + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsEnabledTXOnlyModeAutoDisable(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TXO_AC_Msk) == SPI_CR2_TXO_AC_Msk); +} + +/** + * @brief EnableSPI TX Only Mode + * @rmtoll CR2 TXO FL_SPI_EnableTXOnlyMode + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_EnableTXOnlyMode(SPI_Type *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXO_Msk); +} + +/** + * @brief Get SPI TX Only Mode Setting State + * @rmtoll CR2 TXO FL_SPI_IsEnabledTXOnlyMode + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsEnabledTXOnlyMode(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TXO_Msk) == SPI_CR2_TXO_Msk); +} + +/** + * @brief Set SSN Pin + * @rmtoll CR2 SSN FL_SPI_SetSSNPin + * @param SPIx SPI instance + * @param state This parameter can be one of the following values: + * @arg @ref FL_SPI_SSN_LOW + * @arg @ref FL_SPI_SSN_HIGH + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetSSNPin(SPI_Type *SPIx, uint32_t state) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_SSN_Msk, state); +} + +/** + * @brief Reset SSN Pin + * @rmtoll CR2 SSN FL_SPI_GetSSNPin + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SPI_SSN_LOW + * @arg @ref FL_SPI_SSN_HIGH + */ +__STATIC_INLINE uint32_t FL_SPI_GetSSNPin(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_SSN_Msk)); +} + +/** + * @brief Enable SNN Sofe Control Under Master Mode + * @rmtoll CR2 SSNSEN FL_SPI_EnableSSNSoftControl + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_EnableSSNSoftControl(SPI_Type *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_SSNSEN_Msk); +} + +/** + * @brief Get SNN Sofe Control State Under Master Mode + * @rmtoll CR2 SSNSEN FL_SPI_IsEnabledSSNSoftControl + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsEnabledSSNSoftControl(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_SSNSEN_Msk) == SPI_CR2_SSNSEN_Msk); +} + +/** + * @brief Disable SNN Sofe Control Under Master Mode + * @rmtoll CR2 SSNSEN FL_SPI_DisableSSNSoftControl + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_DisableSSNSoftControl(SPI_Type *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_SSNSEN_Msk); +} + +/** + * @brief Enable SPI + * @rmtoll CR2 SPIEN FL_SPI_Enable + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_Enable(SPI_Type *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_SPIEN_Msk); +} + +/** + * @brief Get SPI Enable Status + * @rmtoll CR2 SPIEN FL_SPI_IsEnabled + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsEnabled(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_SPIEN_Msk) == SPI_CR2_SPIEN_Msk); +} + +/** + * @brief Disable SPI + * @rmtoll CR2 SPIEN FL_SPI_Disable + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_Disable(SPI_Type *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_SPIEN_Msk); +} + +/** + * @brief Clear SPI TX Buffer + * @rmtoll CR3 TXBFC FL_SPI_ClearTXBuff + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_ClearTXBuff(SPI_Type *SPIx) +{ + WRITE_REG(SPIx->CR3, SPI_CR3_TXBFC_Msk); +} + +/** + * @brief Clear SPI RX Buffer + * @rmtoll CR3 RXBFC FL_SPI_ClearRXBuff + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_ClearRXBuff(SPI_Type *SPIx) +{ + WRITE_REG(SPIx->CR3, SPI_CR3_RXBFC_Msk); +} + +/** + * @brief Clear SPI Master Error Flag + * @rmtoll CR3 MERRC FL_SPI_ClearFlag_MasterError + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_ClearFlag_MasterError(SPI_Type *SPIx) +{ + WRITE_REG(SPIx->CR3, SPI_CR3_MERRC_Msk); +} + +/** + * @brief Clear SPI Slave Error Flag + * @rmtoll CR3 SERRC FL_SPI_ClearFlag_SlaveError + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_ClearFlag_SlaveError(SPI_Type *SPIx) +{ + WRITE_REG(SPIx->CR3, SPI_CR3_SERRC_Msk); +} + +/** + * @brief Disable SPI Error Interrupt + * @rmtoll IER ERRIE FL_SPI_DisableIT_Error + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_DisableIT_Error(SPI_Type *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_ERRIE_Msk); +} + +/** + * @brief Enable SPI Error Interrupt + * @rmtoll IER ERRIE FL_SPI_EnableIT_Error + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_EnableIT_Error(SPI_Type *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_ERRIE_Msk); +} + +/** + * @brief Get SPI Error Interrupt Enable Status + * @rmtoll IER ERRIE FL_SPI_IsEnabledIT_Error + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsEnabledIT_Error(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IER, SPI_IER_ERRIE_Msk) == SPI_IER_ERRIE_Msk); +} + +/** + * @brief Disable SPI Transmit Complete Interrupt + * @rmtoll IER TXIE FL_SPI_DisableIT_TXComplete + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_DisableIT_TXComplete(SPI_Type *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_TXIE_Msk); +} + +/** + * @brief Enable SPI Transmit Complete Interrupt + * @rmtoll IER TXIE FL_SPI_EnableIT_TXComplete + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_EnableIT_TXComplete(SPI_Type *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXIE_Msk); +} + +/** + * @brief Get SPI Transmit Complete Interrupt Enable Status + * @rmtoll IER TXIE FL_SPI_IsEnabledIT_TXComplete + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsEnabledIT_TXComplete(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IER, SPI_IER_TXIE_Msk) == SPI_IER_TXIE_Msk); +} + +/** + * @brief Disable SPI Receive Complete Interrupt + * @rmtoll IER RXIE FL_SPI_DisableIT_RXComplete + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_DisableIT_RXComplete(SPI_Type *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_RXIE_Msk); +} + +/** + * @brief Enable SPI Receive Complete Interrupt + * @rmtoll IER RXIE FL_SPI_EnableIT_RXComplete + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_EnableIT_RXComplete(SPI_Type *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXIE_Msk); +} + +/** + * @brief Get SPI Receive Complete Interrupt Enable Status + * @rmtoll IER RXIE FL_SPI_IsEnabledIT_RXComplete + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsEnabledIT_RXComplete(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IER, SPI_IER_RXIE_Msk) == SPI_IER_RXIE_Msk); +} + +/** + * @brief Set SPI Output Data/Command Under Half-Duplex Mode + * @rmtoll ISR DCN_TX FL_SPI_SetFrameMode + * @param SPIx SPI instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_SPI_FRAME_MODE_CMD + * @arg @ref FL_SPI_FRAME_MODE_DATA + * @retval None + */ +__STATIC_INLINE void FL_SPI_SetFrameMode(SPI_Type *SPIx, uint32_t mode) +{ + MODIFY_REG(SPIx->ISR, SPI_ISR_DCN_TX_Msk, mode); +} + +/** + * @brief Get SPI Output Data/Command Under Half-Duplex Mode Setting + * @rmtoll ISR DCN_TX FL_SPI_GetFrameMode + * @param SPIx SPI instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SPI_FRAME_MODE_CMD + * @arg @ref FL_SPI_FRAME_MODE_DATA + */ +__STATIC_INLINE uint32_t FL_SPI_GetFrameMode(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->ISR, SPI_ISR_DCN_TX_Msk)); +} + +/** + * @brief Get SPI Receive Collision Flag + * @rmtoll ISR RXCOL FL_SPI_IsActiveFlag_RXBuffOverflow + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsActiveFlag_RXBuffOverflow(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->ISR, SPI_ISR_RXCOL_Msk) == (SPI_ISR_RXCOL_Msk)); +} + +/** + * @brief Clear SPI Receive Collision Flag + * @rmtoll ISR RXCOL FL_SPI_ClearFlag_RXBuffOverflow + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_ClearFlag_RXBuffOverflow(SPI_Type *SPIx) +{ + WRITE_REG(SPIx->ISR, SPI_ISR_RXCOL_Msk); +} + +/** + * @brief Get SPI Transmit Collision Flag + * @rmtoll ISR TXCOL FL_SPI_IsActiveFlag_TXBuffOverflow + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsActiveFlag_TXBuffOverflow(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->ISR, SPI_ISR_TXCOL_Msk) == (SPI_ISR_TXCOL_Msk)); +} + +/** + * @brief Clear SPI Transmit Collision Flag + * @rmtoll ISR TXCOL FL_SPI_ClearFlag_TXBuffOverflow + * @param SPIx SPI instance + * @retval None + */ +__STATIC_INLINE void FL_SPI_ClearFlag_TXBuffOverflow(SPI_Type *SPIx) +{ + WRITE_REG(SPIx->ISR, SPI_ISR_TXCOL_Msk); +} + +/** + * @brief Get SPI Busy Flag + * @rmtoll ISR BUSY FL_SPI_IsActiveFlag_Busy + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsActiveFlag_Busy(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->ISR, SPI_ISR_BUSY_Msk) == (SPI_ISR_BUSY_Msk)); +} + +/** + * @brief Get SPI Master Error Flag + * @rmtoll ISR MERR FL_SPI_IsActiveFlag_MasterError + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsActiveFlag_MasterError(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->ISR, SPI_ISR_MERR_Msk) == (SPI_ISR_MERR_Msk)); +} + +/** + * @brief Get SPI Slave Error Flag + * @rmtoll ISR SERR FL_SPI_IsActiveFlag_SlaveError + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsActiveFlag_SlaveError(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->ISR, SPI_ISR_SERR_Msk) == (SPI_ISR_SERR_Msk)); +} + +/** + * @brief Get SPI TX Buffer Empty Flag + * @rmtoll ISR TXBE FL_SPI_IsActiveFlag_TXBuffEmpty + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsActiveFlag_TXBuffEmpty(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->ISR, SPI_ISR_TXBE_Msk) == (SPI_ISR_TXBE_Msk)); +} + +/** + * @brief Get SPI RX Buffer Full Flag + * @rmtoll ISR RXBF FL_SPI_IsActiveFlag_RXBuffFull + * @param SPIx SPI instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SPI_IsActiveFlag_RXBuffFull(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->ISR, SPI_ISR_RXBF_Msk) == (SPI_ISR_RXBF_Msk)); +} + +/** + * @brief Write SPI TX Buffer + * @rmtoll TXBUF FL_SPI_WriteTXBuff + * @param SPIx SPI instance + * @param data + * @retval None + */ +__STATIC_INLINE void FL_SPI_WriteTXBuff(SPI_Type *SPIx, uint32_t data) +{ + MODIFY_REG(SPIx->TXBUF, (0xffffffffU << 0U), (data << 0U)); +} + +/** + * @brief Read SPI TX Buffer + * @rmtoll RXBUF FL_SPI_ReadRXBuff + * @param SPIx SPI instance + * @retval + */ +__STATIC_INLINE uint32_t FL_SPI_ReadRXBuff(SPI_Type *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RXBUF, (0xffffffffU << 0U)) >> 0U); +} + +/** + * @} + */ + +/** @defgroup SPI_FL_EF_Init Initialization and de-initialization functions + * @{ + */ + +FL_ErrorStatus FL_SPI_DeInit(SPI_Type *SPIx); +FL_ErrorStatus FL_SPI_Init(SPI_Type *SPIx, FL_SPI_InitTypeDef *initStruct); +void FL_SPI_StructInit(FL_SPI_InitTypeDef *initStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_SPI_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.14-0.1 @ 2020-10-20*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_svd.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_svd.h new file mode 100644 index 0000000000..9e86deff59 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_svd.h @@ -0,0 +1,679 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_svd.h + * @author FMSH Application Team + * @brief Head file of SVD FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_SVD_H +#define __FM33LC0XX_FL_SVD_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup SVD SVD + * @brief SVD FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup SVD_FL_ES_INIT SVD Exported Init structures + * @{ + */ + +/** + * @brief SVD Init Sturcture definition + */ +typedef struct +{ + /* 参考电压 */ + uint32_t referenceVoltage; + + /* 报警阈值 */ + uint32_t warningThreshold; + + /* 数字滤波 */ + uint32_t digitalFilter; + + /* SVS通道选择 */ + uint32_t SVSChannel; + +} FL_SVD_InitTypeDef; + +/** + * @} + */ + +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup SVD_FL_Exported_Constants SVD Exported Constants + * @{ + */ + +#define SVD_CFGR_ADSVD_SEL_Pos (9U) +#define SVD_CFGR_ADSVD_SEL_Msk (0x7U << SVD_CFGR_ADSVD_SEL_Pos) +#define SVD_CFGR_ADSVD_SEL SVD_CFGR_ADSVD_SEL_Msk + +#define SVD_CFGR_ADSVD_EN_Pos (8U) +#define SVD_CFGR_ADSVD_EN_Msk (0x1U << SVD_CFGR_ADSVD_EN_Pos) +#define SVD_CFGR_ADSVD_EN SVD_CFGR_ADSVD_EN_Msk + +#define SVD_CFGR_LVL_Pos (4U) +#define SVD_CFGR_LVL_Msk (0xfU << SVD_CFGR_LVL_Pos) +#define SVD_CFGR_LVL SVD_CFGR_LVL_Msk + +#define SVD_CFGR_DFEN_Pos (3U) +#define SVD_CFGR_DFEN_Msk (0x1U << SVD_CFGR_DFEN_Pos) +#define SVD_CFGR_DFEN SVD_CFGR_DFEN_Msk + +#define SVD_CFGR_MOD_Pos (2U) +#define SVD_CFGR_MOD_Msk (0x1U << SVD_CFGR_MOD_Pos) +#define SVD_CFGR_MOD SVD_CFGR_MOD_Msk + +#define SVD_CFGR_ITVL_Pos (0U) +#define SVD_CFGR_ITVL_Msk (0x3U << SVD_CFGR_ITVL_Pos) +#define SVD_CFGR_ITVL SVD_CFGR_ITVL_Msk + +#define SVD_CR_SVSEN_Pos (1U) +#define SVD_CR_SVSEN_Msk (0x1U << SVD_CR_SVSEN_Pos) +#define SVD_CR_SVSEN SVD_CR_SVSEN_Msk + +#define SVD_CR_EN_Pos (0U) +#define SVD_CR_EN_Msk (0x1U << SVD_CR_EN_Pos) +#define SVD_CR_EN SVD_CR_EN_Msk + +#define SVD_IER_PFIE_Pos (1U) +#define SVD_IER_PFIE_Msk (0x1U << SVD_IER_PFIE_Pos) +#define SVD_IER_PFIE SVD_IER_PFIE_Msk + +#define SVD_IER_PRIE_Pos (0U) +#define SVD_IER_PRIE_Msk (0x1U << SVD_IER_PRIE_Pos) +#define SVD_IER_PRIE SVD_IER_PRIE_Msk + +#define SVD_ISR_ADLVDO_Pos (16U) +#define SVD_ISR_ADLVDO_Msk (0x1U << SVD_ISR_ADLVDO_Pos) +#define SVD_ISR_ADLVDO SVD_ISR_ADLVDO_Msk + +#define SVD_ISR_SVDO_Pos (8U) +#define SVD_ISR_SVDO_Msk (0x1U << SVD_ISR_SVDO_Pos) +#define SVD_ISR_SVDO SVD_ISR_SVDO_Msk + +#define SVD_ISR_SVDR_Pos (7U) +#define SVD_ISR_SVDR_Msk (0x1U << SVD_ISR_SVDR_Pos) +#define SVD_ISR_SVDR SVD_ISR_SVDR_Msk + +#define SVD_ISR_PFF_Pos (1U) +#define SVD_ISR_PFF_Msk (0x1U << SVD_ISR_PFF_Pos) +#define SVD_ISR_PFF SVD_ISR_PFF_Msk + +#define SVD_ISR_PRF_Pos (0U) +#define SVD_ISR_PRF_Msk (0x1U << SVD_ISR_PRF_Pos) +#define SVD_ISR_PRF SVD_ISR_PRF_Msk + +#define SVD_VSR_EN_Pos (0U) +#define SVD_VSR_EN_Msk (0x7U << SVD_VSR_EN_Pos) +#define SVD_VSR_EN SVD_VSR_EN_Msk + + + +#define FL_SVD_REFERENCE_1P2V (0x1U << 2U) +#define FL_SVD_REFERENCE_1P1V (0x1U << 1U) +#define FL_SVD_REFERENCE_1P0V (0x1U << 0U) + + + +#define FL_SVD_ADC_THRESHOLD_3P300V (0x0U << SVD_CFGR_ADSVD_SEL_Pos) +#define FL_SVD_ADC_THRESHOLD_3P514V (0x1U << SVD_CFGR_ADSVD_SEL_Pos) +#define FL_SVD_ADC_THRESHOLD_3P729V (0x2U << SVD_CFGR_ADSVD_SEL_Pos) +#define FL_SVD_ADC_THRESHOLD_3P943V (0x3U << SVD_CFGR_ADSVD_SEL_Pos) +#define FL_SVD_ADC_THRESHOLD_4P157V (0x4U << SVD_CFGR_ADSVD_SEL_Pos) +#define FL_SVD_ADC_THRESHOLD_4P371V (0x5U << SVD_CFGR_ADSVD_SEL_Pos) +#define FL_SVD_ADC_THRESHOLD_4P586V (0x6U << SVD_CFGR_ADSVD_SEL_Pos) +#define FL_SVD_ADC_THRESHOLD_4P800V (0x7U << SVD_CFGR_ADSVD_SEL_Pos) + + +#define FL_SVD_WARNING_THRESHOLD_GROUP0 (0x0U << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP1 (0x1U << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP2 (0x2U << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP3 (0x3U << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP4 (0x4U << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP5 (0x5U << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP6 (0x6U << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP7 (0x7U << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP8 (0x8U << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP9 (0x9U << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP10 (0xaU << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP11 (0xbU << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP12 (0xcU << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP13 (0xdU << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP14 (0xeU << SVD_CFGR_LVL_Pos) +#define FL_SVD_WARNING_THRESHOLD_GROUP15 (0xfU << SVD_CFGR_LVL_Pos) + + +#define FL_SVD_WORK_MODE_CONTINUOUS (0x0U << SVD_CFGR_MOD_Pos) +#define FL_SVD_WORK_MODE_PERIODIC (0x1U << SVD_CFGR_MOD_Pos) + + +#define FL_SVD_ENABLE_PERIOD_62MS (0x0U << SVD_CFGR_ITVL_Pos) +#define FL_SVD_ENABLE_PERIOD_256MS (0x1U << SVD_CFGR_ITVL_Pos) +#define FL_SVD_ENABLE_PERIOD_1000MS (0x2U << SVD_CFGR_ITVL_Pos) +#define FL_SVD_ENABLE_PERIOD_4000MS (0x3U << SVD_CFGR_ITVL_Pos) + + +#define FL_SVD_ADC_POWER_STATUS_RISING (0x0U << SVD_ISR_ADLVDO_Pos) +#define FL_SVD_ADC_POWER_STATUS_FALLING (0x1U << SVD_ISR_ADLVDO_Pos) + +#define FL_SVD_POWER_STATUS_FALLING (0x0U << SVD_ISR_SVDO_Pos) +#define FL_SVD_POWER_STATUS_RISING (0x1U << SVD_ISR_SVDO_Pos) + +#define FL_SVD_LATCHED_POWER_STATUS_FALLING (0x0U << SVD_ISR_SVDR_Pos) +#define FL_SVD_LATCHED_POWER_STATUS_RISING (0x1U << SVD_ISR_SVDR_Pos) + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup SVD_FL_Exported_Functions SVD Exported Functions + * @{ + */ + +/** + * @brief Set ADC SVD Level + * @rmtoll CFGR ADSVD_SEL FL_SVD_SetADCThreshold + * @param SVDx SVD instance + * @param level This parameter can be one of the following values: + * @arg @ref FL_SVD_ADC_THRESHOLD_3P300V + * @arg @ref FL_SVD_ADC_THRESHOLD_3P514V + * @arg @ref FL_SVD_ADC_THRESHOLD_3P729V + * @arg @ref FL_SVD_ADC_THRESHOLD_3P943V + * @arg @ref FL_SVD_ADC_THRESHOLD_4P157V + * @arg @ref FL_SVD_ADC_THRESHOLD_4P371V + * @arg @ref FL_SVD_ADC_THRESHOLD_4P586V + * @arg @ref FL_SVD_ADC_THRESHOLD_4P800V + * @retval None + */ +__STATIC_INLINE void FL_SVD_SetADCThreshold(SVD_Type *SVDx, uint32_t level) +{ + MODIFY_REG(SVDx->CFGR, SVD_CFGR_ADSVD_SEL_Msk, level); +} + +/** + * @brief Get ADC SVD Level + * @rmtoll CFGR ADSVD_SEL FL_SVD_GetADCThreshold + * @param SVDx SVD instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SVD_ADC_THRESHOLD_3P300V + * @arg @ref FL_SVD_ADC_THRESHOLD_3P514V + * @arg @ref FL_SVD_ADC_THRESHOLD_3P729V + * @arg @ref FL_SVD_ADC_THRESHOLD_3P943V + * @arg @ref FL_SVD_ADC_THRESHOLD_4P157V + * @arg @ref FL_SVD_ADC_THRESHOLD_4P371V + * @arg @ref FL_SVD_ADC_THRESHOLD_4P586V + * @arg @ref FL_SVD_ADC_THRESHOLD_4P800V + */ +__STATIC_INLINE uint32_t FL_SVD_GetADCThreshold(SVD_Type *SVDx) +{ + return (uint32_t)(READ_BIT(SVDx->CFGR, SVD_CFGR_ADSVD_SEL_Msk)); +} + +/** + * @brief Enable ADC SVD + * @rmtoll CFGR ADSVD_EN FL_SVD_EnableADCMonitor + * @param SVDx SVD instance + * @retval None + */ +__STATIC_INLINE void FL_SVD_EnableADCMonitor(SVD_Type *SVDx) +{ + SET_BIT(SVDx->CFGR, SVD_CFGR_ADSVD_EN_Msk); +} + +/** + * @brief Get ADC SVD Enable Status + * @rmtoll CFGR ADSVD_EN FL_SVD_IsEnabledADCMonitor + * @param SVDx SVD instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SVD_IsEnabledADCMonitor(SVD_Type *SVDx) +{ + return (uint32_t)(READ_BIT(SVDx->CFGR, SVD_CFGR_ADSVD_EN_Msk) == SVD_CFGR_ADSVD_EN_Msk); +} + +/** + * @brief Disable ADC SVD + * @rmtoll CFGR ADSVD_EN FL_SVD_DisableADCMonitor + * @param SVDx SVD instance + * @retval None + */ +__STATIC_INLINE void FL_SVD_DisableADCMonitor(SVD_Type *SVDx) +{ + CLEAR_BIT(SVDx->CFGR, SVD_CFGR_ADSVD_EN_Msk); +} + +/** + * @brief Set SVD Threshold Level + * @rmtoll CFGR LVL FL_SVD_SetWarningThreshold + * @param SVDx SVD instance + * @param level This parameter can be one of the following values: + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP0 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP1 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP2 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP3 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP4 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP5 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP6 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP7 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP8 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP9 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP10 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP11 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP12 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP13 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP14 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP15 + * @retval None + */ +__STATIC_INLINE void FL_SVD_SetWarningThreshold(SVD_Type *SVDx, uint32_t level) +{ + MODIFY_REG(SVDx->CFGR, SVD_CFGR_LVL_Msk, level); +} + +/** + * @brief Get SVD Threshold Level + * @rmtoll CFGR LVL FL_SVD_GetWarningThreshold + * @param SVDx SVD instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP0 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP1 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP2 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP3 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP4 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP5 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP6 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP7 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP8 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP9 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP10 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP11 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP12 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP13 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP14 + * @arg @ref FL_SVD_WARNING_THRESHOLD_GROUP15 + */ +__STATIC_INLINE uint32_t FL_SVD_GetWarningThreshold(SVD_Type *SVDx) +{ + return (uint32_t)(READ_BIT(SVDx->CFGR, SVD_CFGR_LVL_Msk)); +} + +/** + * @brief Enable SVD Digital Filtering + * @rmtoll CFGR DFEN FL_SVD_EnableDigitalFilter + * @param SVDx SVD instance + * @retval None + */ +__STATIC_INLINE void FL_SVD_EnableDigitalFilter(SVD_Type *SVDx) +{ + SET_BIT(SVDx->CFGR, SVD_CFGR_DFEN_Msk); +} + +/** + * @brief Get SVD Digital Filtering Enable Status + * @rmtoll CFGR DFEN FL_SVD_IsEnabledDigitalFilter + * @param SVDx SVD instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SVD_IsEnabledDigitalFilter(SVD_Type *SVDx) +{ + return (uint32_t)(READ_BIT(SVDx->CFGR, SVD_CFGR_DFEN_Msk) == SVD_CFGR_DFEN_Msk); +} + +/** + * @brief Disable SVD Digital Filtering + * @rmtoll CFGR DFEN FL_SVD_DisableDigitalFilter + * @param SVDx SVD instance + * @retval None + */ +__STATIC_INLINE void FL_SVD_DisableDigitalFilter(SVD_Type *SVDx) +{ + CLEAR_BIT(SVDx->CFGR, SVD_CFGR_DFEN_Msk); +} + +/** + * @brief Set SVD Working Mode + * @rmtoll CFGR MOD FL_SVD_SetWorkMode + * @param SVDx SVD instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_SVD_WORK_MODE_CONTINUOUS + * @arg @ref FL_SVD_WORK_MODE_PERIODIC + * @retval None + */ +__STATIC_INLINE void FL_SVD_SetWorkMode(SVD_Type *SVDx, uint32_t mode) +{ + MODIFY_REG(SVDx->CFGR, SVD_CFGR_MOD_Msk, mode); +} + +/** + * @brief Get SVD Working Mode + * @rmtoll CFGR MOD FL_SVD_GetWorkMode + * @param SVDx SVD instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SVD_WORK_MODE_CONTINUOUS + * @arg @ref FL_SVD_WORK_MODE_PERIODIC + */ +__STATIC_INLINE uint32_t FL_SVD_GetWorkMode(SVD_Type *SVDx) +{ + return (uint32_t)(READ_BIT(SVDx->CFGR, SVD_CFGR_MOD_Msk)); +} + +/** + * @brief Enable External SVS Channel + * @rmtoll CR SVSEN FL_SVD_EnableSVSChannel + * @param SVDx SVD instance + * @retval None + */ +__STATIC_INLINE void FL_SVD_EnableSVSChannel(SVD_Type *SVDx) +{ + SET_BIT(SVDx->CR, SVD_CR_SVSEN_Msk); +} + +/** + * @brief Get External SVS Channel Enable Status + * @rmtoll CR SVSEN FL_SVD_IsEnabledSVSChannel + * @param SVDx SVD instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SVD_IsEnabledSVSChannel(SVD_Type *SVDx) +{ + return (uint32_t)(READ_BIT(SVDx->CR, SVD_CR_SVSEN_Msk) == SVD_CR_SVSEN_Msk); +} + +/** + * @brief Disable External SVS Channel + * @rmtoll CR SVSEN FL_SVD_DisableSVSChannel + * @param SVDx SVD instance + * @retval None + */ +__STATIC_INLINE void FL_SVD_DisableSVSChannel(SVD_Type *SVDx) +{ + CLEAR_BIT(SVDx->CR, SVD_CR_SVSEN_Msk); +} + +/** + * @brief Enable SVD + * @rmtoll CR EN FL_SVD_Enable + * @param SVDx SVD instance + * @retval None + */ +__STATIC_INLINE void FL_SVD_Enable(SVD_Type *SVDx) +{ + SET_BIT(SVDx->CR, SVD_CR_EN_Msk); +} + +/** + * @brief Get SVD Enable Status + * @rmtoll CR EN FL_SVD_IsEnabled + * @param SVDx SVD instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SVD_IsEnabled(SVD_Type *SVDx) +{ + return (uint32_t)(READ_BIT(SVDx->CR, SVD_CR_EN_Msk) == SVD_CR_EN_Msk); +} + +/** + * @brief Disable SVD + * @rmtoll CR EN FL_SVD_Disable + * @param SVDx SVD instance + * @retval None + */ +__STATIC_INLINE void FL_SVD_Disable(SVD_Type *SVDx) +{ + CLEAR_BIT(SVDx->CR, SVD_CR_EN_Msk); +} + +/** + * @brief Enable Power Fall Interrupt + * @rmtoll IER PFIE FL_SVD_EnableIT_PowerFall + * @param SVDx SVD instance + * @retval None + */ +__STATIC_INLINE void FL_SVD_EnableIT_PowerFall(SVD_Type *SVDx) +{ + SET_BIT(SVDx->IER, SVD_IER_PFIE_Msk); +} + +/** + * @brief Get Power Fall Interrupt Status + * @rmtoll IER PFIE FL_SVD_IsEnabledIT_PowerFall + * @param SVDx SVD instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SVD_IsEnabledIT_PowerFall(SVD_Type *SVDx) +{ + return (uint32_t)(READ_BIT(SVDx->IER, SVD_IER_PFIE_Msk) == SVD_IER_PFIE_Msk); +} + +/** + * @brief Disable Power Fall Interrupt + * @rmtoll IER PFIE FL_SVD_DisableIT_PowerFall + * @param SVDx SVD instance + * @retval None + */ +__STATIC_INLINE void FL_SVD_DisableIT_PowerFall(SVD_Type *SVDx) +{ + CLEAR_BIT(SVDx->IER, SVD_IER_PFIE_Msk); +} + +/** + * @brief Enable Power Rise Interrupt + * @rmtoll IER PRIE FL_SVD_EnableIT_PowerRise + * @param SVDx SVD instance + * @retval None + */ +__STATIC_INLINE void FL_SVD_EnableIT_PowerRise(SVD_Type *SVDx) +{ + SET_BIT(SVDx->IER, SVD_IER_PRIE_Msk); +} + +/** + * @brief Get Power Rise Interrupt Status + * @rmtoll IER PRIE FL_SVD_IsEnabledIT_PowerRise + * @param SVDx SVD instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SVD_IsEnabledIT_PowerRise(SVD_Type *SVDx) +{ + return (uint32_t)(READ_BIT(SVDx->IER, SVD_IER_PRIE_Msk) == SVD_IER_PRIE_Msk); +} + +/** + * @brief Disable Power Rise Interrupt + * @rmtoll IER PRIE FL_SVD_DisableIT_PowerRise + * @param SVDx SVD instance + * @retval None + */ +__STATIC_INLINE void FL_SVD_DisableIT_PowerRise(SVD_Type *SVDx) +{ + CLEAR_BIT(SVDx->IER, SVD_IER_PRIE_Msk); +} + +/** + * @brief Get ADC SVD Status + * @rmtoll ISR ADLVDO FL_SVD_GetADCPowerStatus + * @param SVDx SVD instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SVD_ADC_POWER_STATUS_RISING + * @arg @ref FL_SVD_ADC_POWER_STATUS_FALLING + */ +__STATIC_INLINE uint32_t FL_SVD_GetADCPowerStatus(SVD_Type *SVDx) +{ + return (uint32_t)(READ_BIT(SVDx->ISR, SVD_ISR_ADLVDO_Msk)); +} + +/** + * @brief Get SVD Status + * @rmtoll ISR SVDO FL_SVD_GetCurrentPowerStatus + * @param SVDx SVD instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SVD_POWER_STATUS_FALLING + * @arg @ref FL_SVD_POWER_STATUS_RISING + */ +__STATIC_INLINE uint32_t FL_SVD_GetCurrentPowerStatus(SVD_Type *SVDx) +{ + return (uint32_t)(READ_BIT(SVDx->ISR, SVD_ISR_SVDO_Msk)); +} + +/** + * @brief Get SVD Latched Status + * @rmtoll ISR SVDR FL_SVD_GetLatchedPowerStatus + * @param SVDx SVD instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_SVD_LATCHED_POWER_STATUS_FALLING + * @arg @ref FL_SVD_LATCHED_POWER_STATUS_RISING + */ +__STATIC_INLINE uint32_t FL_SVD_GetLatchedPowerStatus(SVD_Type *SVDx) +{ + return (uint32_t)(READ_BIT(SVDx->ISR, SVD_ISR_SVDR_Msk)); +} + +/** + * @brief Get SVD Power Fall Flag + * @rmtoll ISR PFF FL_SVD_IsActiveFlag_PowerFall + * @param SVDx SVD instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SVD_IsActiveFlag_PowerFall(SVD_Type *SVDx) +{ + return (uint32_t)(READ_BIT(SVDx->ISR, SVD_ISR_PFF_Msk) == (SVD_ISR_PFF_Msk)); +} + +/** + * @brief Clear SVD Power Fall Flag + * @rmtoll ISR PFF FL_SVD_ClearFlag_PowerFall + * @param SVDx SVD instance + * @retval None + */ +__STATIC_INLINE void FL_SVD_ClearFlag_PowerFall(SVD_Type *SVDx) +{ + WRITE_REG(SVDx->ISR, SVD_ISR_PFF_Msk); +} + +/** + * @brief Get SVD Power Rise Flag + * @rmtoll ISR PRF FL_SVD_IsActiveFlag_PowerRise + * @param SVDx SVD instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SVD_IsActiveFlag_PowerRise(SVD_Type *SVDx) +{ + return (uint32_t)(READ_BIT(SVDx->ISR, SVD_ISR_PRF_Msk) == (SVD_ISR_PRF_Msk)); +} + +/** + * @brief Clear SVD Power Rise Flag + * @rmtoll ISR PRF FL_SVD_ClearFlag_PowerRise + * @param SVDx SVD instance + * @retval None + */ +__STATIC_INLINE void FL_SVD_ClearFlag_PowerRise(SVD_Type *SVDx) +{ + WRITE_REG(SVDx->ISR, SVD_ISR_PRF_Msk); +} + +/** + * @brief Enable SVD Reference + * @rmtoll VSR EN FL_SVD_EnableReference + * @param SVDx SVD instance + * @param ref This parameter can be one of the following values: + * @arg @ref FL_SVD_REFERENCE_1P2V + * @arg @ref FL_SVD_REFERENCE_1P1V + * @arg @ref FL_SVD_REFERENCE_1P0V + * @retval None + */ +__STATIC_INLINE void FL_SVD_EnableReference(SVD_Type *SVDx, uint32_t ref) +{ + WRITE_REG(SVDx->VSR, ((ref & 0x7) << 0x0U)); +} + +/** + * @brief Get SVD Reference Enable Status + * @rmtoll VSR EN FL_SVD_IsEnabledReference + * @param SVDx SVD instance + * @param ref This parameter can be one of the following values: + * @arg @ref FL_SVD_REFERENCE_1P2V + * @arg @ref FL_SVD_REFERENCE_1P1V + * @arg @ref FL_SVD_REFERENCE_1P0V + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_SVD_IsEnabledReference(SVD_Type *SVDx, uint32_t ref) +{ + return (uint32_t)(READ_BIT(SVDx->VSR, ((ref & 0x7) << 0x0U)) == ((ref & 0x7) << 0x0U)); +} + +/** + * @brief Disable SVD Reference + * @rmtoll VSR EN FL_SVD_DisableReference + * @param SVDx SVD instance + * @param ref This parameter can be one of the following values: + * @arg @ref FL_SVD_REFERENCE_1P2V + * @arg @ref FL_SVD_REFERENCE_1P1V + * @arg @ref FL_SVD_REFERENCE_1P0V + * @retval None + */ +__STATIC_INLINE void FL_SVD_DisableReference(SVD_Type *SVDx, uint32_t ref) +{ + CLEAR_BIT(SVDx->VSR, ((ref & 0x7) << 0x0U)); +} + +/** + * @} + */ + +/** @defgroup SVD_FL_EF_Init Initialization and de-initialization functions + * @{ + */ + +FL_ErrorStatus FL_SVD_DeInit(SVD_Type *SVDx); +FL_ErrorStatus FL_SVD_Init(SVD_Type *SVDx, FL_SVD_InitTypeDef *initStruct); +void FL_SVD_StructInit(FL_SVD_InitTypeDef *initStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_SVD_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-25*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_u7816.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_u7816.h new file mode 100644 index 0000000000..3beb208b25 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_u7816.h @@ -0,0 +1,1071 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_u7816.h + * @author FMSH Application Team + * @brief Head file of U7816 FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_U7816_H +#define __FM33LC0XX_FL_U7816_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup U7816 U7816 + * @brief U7816 FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup U7816_FL_ES_INIT U7816 Exported Init structures + * @{ + */ + +/** + * @brief U7816 Init Sturcture definition + */ +typedef struct +{ + /** 卡时钟频率 */ + uint32_t outputClockFreqence; + + /** 接口发送失败后自动重装使能 */ + uint32_t txAutoRetry; + + /** 自动重装次数 */ + uint32_t retryCnt; + + /** 插入BGT使能 */ + uint32_t blockGuard; + + /** 强上拉使能 */ + uint32_t strongPullUp; + + /** 帧格式奇偶校验模式 */ + uint32_t parity; + + /** 帧格式接收Guard时间 */ + uint32_t rxGuardTime; + + /** 帧格式发送Guard时间 */ + uint32_t txGuardTime; + /** 帧格式错误Guard时间 */ + uint32_t errorGuardTime; + + /** 帧错误信号长度 */ + uint32_t errorSignalWidth; + + /** 接收校验错误自动回发error signal使能 */ + uint32_t rxAutoErrorSignal; + + /** 传输BIT顺序 */ + uint32_t transferOrder; + + /** 通讯速率 */ + uint32_t baud; + + /** 额外发送Guard时间 */ + uint32_t extraGuardTime; + +} FL_U7816_InitTypeDef; + +/** + * @} + */ + +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup U7816_FL_Exported_Constants U7816 Exported Constants + * @{ + */ + +#define U7816_CR_TXEN_Pos (5U) +#define U7816_CR_TXEN_Msk (0x1U << U7816_CR_TXEN_Pos) +#define U7816_CR_TXEN U7816_CR_TXEN_Msk + +#define U7816_CR_RXEN_Pos (4U) +#define U7816_CR_RXEN_Msk (0x1U << U7816_CR_RXEN_Pos) +#define U7816_CR_RXEN U7816_CR_RXEN_Msk + +#define U7816_CR_CKOEN_Pos (3U) +#define U7816_CR_CKOEN_Msk (0x1U << U7816_CR_CKOEN_Pos) +#define U7816_CR_CKOEN U7816_CR_CKOEN_Msk + +#define U7816_CR_HPUAT_Pos (2U) +#define U7816_CR_HPUAT_Msk (0x1U << U7816_CR_HPUAT_Pos) +#define U7816_CR_HPUAT U7816_CR_HPUAT_Msk + +#define U7816_CR_HPUEN_Pos (1U) +#define U7816_CR_HPUEN_Msk (0x1U << U7816_CR_HPUEN_Pos) +#define U7816_CR_HPUEN U7816_CR_HPUEN_Msk + +#define U7816_FFR_SFREN_Pos (11U) +#define U7816_FFR_SFREN_Msk (0x1U << U7816_FFR_SFREN_Pos) +#define U7816_FFR_SFREN U7816_FFR_SFREN_Msk + +#define U7816_FFR_ERSW_Pos (9U) +#define U7816_FFR_ERSW_Msk (0x3U << U7816_FFR_ERSW_Pos) +#define U7816_FFR_ERSW U7816_FFR_ERSW_Msk + +#define U7816_FFR_ERSGD_Pos (8U) +#define U7816_FFR_ERSGD_Msk (0x1U << U7816_FFR_ERSGD_Pos) +#define U7816_FFR_ERSGD U7816_FFR_ERSGD_Msk + +#define U7816_FFR_BGTEN_Pos (7U) +#define U7816_FFR_BGTEN_Msk (0x1U << U7816_FFR_BGTEN_Pos) +#define U7816_FFR_BGTEN U7816_FFR_BGTEN_Msk + +#define U7816_FFR_REP_T_Pos (6U) +#define U7816_FFR_REP_T_Msk (0x1U << U7816_FFR_REP_T_Pos) +#define U7816_FFR_REP_T U7816_FFR_REP_T_Msk + +#define U7816_FFR_PAR_Pos (4U) +#define U7816_FFR_PAR_Msk (0x3U << U7816_FFR_PAR_Pos) +#define U7816_FFR_PAR U7816_FFR_PAR_Msk + +#define U7816_FFR_RFREN_Pos (3U) +#define U7816_FFR_RFREN_Msk (0x1U << U7816_FFR_RFREN_Pos) +#define U7816_FFR_RFREN U7816_FFR_RFREN_Msk + +#define U7816_FFR_TREPEN_Pos (2U) +#define U7816_FFR_TREPEN_Msk (0x1U << U7816_FFR_TREPEN_Pos) +#define U7816_FFR_TREPEN U7816_FFR_TREPEN_Msk + +#define U7816_FFR_RREPEN_Pos (1U) +#define U7816_FFR_RREPEN_Msk (0x1U << U7816_FFR_RREPEN_Pos) +#define U7816_FFR_RREPEN U7816_FFR_RREPEN_Msk + +#define U7816_FFR_DICONV_Pos (0U) +#define U7816_FFR_DICONV_Msk (0x1U << U7816_FFR_DICONV_Pos) +#define U7816_FFR_DICONV U7816_FFR_DICONV_Msk + +#define U7816_IER_RXIE_Pos (2U) +#define U7816_IER_RXIE_Msk (0x1U << U7816_IER_RXIE_Pos) +#define U7816_IER_RXIE U7816_IER_RXIE_Msk + +#define U7816_IER_TXIE_Pos (1U) +#define U7816_IER_TXIE_Msk (0x1U << U7816_IER_TXIE_Pos) +#define U7816_IER_TXIE U7816_IER_TXIE_Msk + +#define U7816_IER_LSIE_Pos (0U) +#define U7816_IER_LSIE_Msk (0x1U << U7816_IER_LSIE_Pos) +#define U7816_IER_LSIE U7816_IER_LSIE_Msk + +#define U7816_ISR_WAIT_RPT_Pos (18U) +#define U7816_ISR_WAIT_RPT_Msk (0x1U << U7816_ISR_WAIT_RPT_Pos) +#define U7816_ISR_WAIT_RPT U7816_ISR_WAIT_RPT_Msk + +#define U7816_ISR_TXBUSY_Pos (17U) +#define U7816_ISR_TXBUSY_Msk (0x1U << U7816_ISR_TXBUSY_Pos) +#define U7816_ISR_TXBUSY U7816_ISR_TXBUSY_Msk + +#define U7816_ISR_RXBUSY_Pos (16U) +#define U7816_ISR_RXBUSY_Msk (0x1U << U7816_ISR_RXBUSY_Pos) +#define U7816_ISR_RXBUSY U7816_ISR_RXBUSY_Msk + +#define U7816_ISR_TPARERR_Pos (11U) +#define U7816_ISR_TPARERR_Msk (0x1U << U7816_ISR_TPARERR_Pos) +#define U7816_ISR_TPARERR U7816_ISR_TPARERR_Msk + +#define U7816_ISR_RPARERR_Pos (10U) +#define U7816_ISR_RPARERR_Msk (0x1U << U7816_ISR_RPARERR_Pos) +#define U7816_ISR_RPARERR U7816_ISR_RPARERR_Msk + +#define U7816_ISR_FRERR_Pos (9U) +#define U7816_ISR_FRERR_Msk (0x1U << U7816_ISR_FRERR_Pos) +#define U7816_ISR_FRERR U7816_ISR_FRERR_Msk + +#define U7816_ISR_OVERR_Pos (8U) +#define U7816_ISR_OVERR_Msk (0x1U << U7816_ISR_OVERR_Pos) +#define U7816_ISR_OVERR U7816_ISR_OVERR_Msk + +#define U7816_ISR_RXIF_Pos (2U) +#define U7816_ISR_RXIF_Msk (0x1U << U7816_ISR_RXIF_Pos) +#define U7816_ISR_RXIF U7816_ISR_RXIF_Msk + +#define U7816_ISR_TXIF_Pos (1U) +#define U7816_ISR_TXIF_Msk (0x1U << U7816_ISR_TXIF_Pos) +#define U7816_ISR_TXIF U7816_ISR_TXIF_Msk + +#define U7816_ISR_ERRIF_Pos (0U) +#define U7816_ISR_ERRIF_Msk (0x1U << U7816_ISR_ERRIF_Pos) +#define U7816_ISR_ERRIF U7816_ISR_ERRIF_Msk + + + + + + +#define FL_U7816_TX_GUARD_TIME_2ETU (0x0U << U7816_FFR_SFREN_Pos) +#define FL_U7816_TX_GUARD_TIME_3ETU (0x1U << U7816_FFR_SFREN_Pos) + + +#define FL_U7816_ERROR_SIGNAL_WIDTH_2ETU (0x1U << U7816_FFR_ERSW_Pos) +#define FL_U7816_ERROR_SIGNAL_WIDTH_1P5ETU (0x2U << U7816_FFR_ERSW_Pos) +#define FL_U7816_ERROR_SIGNAL_WIDTH_1ETU (0x3U << U7816_FFR_ERSW_Pos) + + +#define FL_U7816_ERROR_GUARD_TIME_2ETU (0x0U << U7816_FFR_ERSGD_Pos) +#define FL_U7816_ERROR_GUARD_TIME_1ETU (0x1U << U7816_FFR_ERSGD_Pos) + + +#define FL_U7816_RETRY_COUNT_1 (0x0U << U7816_FFR_REP_T_Pos) +#define FL_U7816_RETRY_COUNT_3 (0x1U << U7816_FFR_REP_T_Pos) + + +#define FL_U7816_PARITY_EVEN (0x0U << U7816_FFR_PAR_Pos) +#define FL_U7816_PARITY_ODD (0x1U << U7816_FFR_PAR_Pos) +#define FL_U7816_PARITY_ALWAYS_1 (0x2U << U7816_FFR_PAR_Pos) +#define FL_U7816_PARITY_NONE (0x3U << U7816_FFR_PAR_Pos) + + +#define FL_U7816_RX_GUARD_TIME_2ETU (0x0U << U7816_FFR_RFREN_Pos) +#define FL_U7816_RX_GUARD_TIME_1ETU (0x1U << U7816_FFR_RFREN_Pos) + + +#define FL_U7816_BIT_ORDER_LSB_FIRST (0x0U << U7816_FFR_DICONV_Pos) +#define FL_U7816_BIT_ORDER_MSB_FIRST (0x1U << U7816_FFR_DICONV_Pos) + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup U7816_FL_Exported_Functions U7816 Exported Functions + * @{ + */ + +/** + * @brief Enable U7816 Transmit + * @rmtoll CR TXEN FL_U7816_EnableTX + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_EnableTX(U7816_Type *U7816x) +{ + SET_BIT(U7816x->CR, U7816_CR_TXEN_Msk); +} + +/** + * @brief Get U7816 Transmit Enable Status + * @rmtoll CR TXEN FL_U7816_IsEnabledTX + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsEnabledTX(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->CR, U7816_CR_TXEN_Msk) == U7816_CR_TXEN_Msk); +} + +/** + * @brief Disable U7816 Transmit + * @rmtoll CR TXEN FL_U7816_DisableTX + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_DisableTX(U7816_Type *U7816x) +{ + CLEAR_BIT(U7816x->CR, U7816_CR_TXEN_Msk); +} + +/** + * @brief Enable U7816 Receive + * @rmtoll CR RXEN FL_U7816_EnableRX + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_EnableRX(U7816_Type *U7816x) +{ + SET_BIT(U7816x->CR, U7816_CR_RXEN_Msk); +} + +/** + * @brief Get U7816 Receive Enable Status + * @rmtoll CR RXEN FL_U7816_IsEnabledRX + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsEnabledRX(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->CR, U7816_CR_RXEN_Msk) == U7816_CR_RXEN_Msk); +} + +/** + * @brief Disable U7816 Receive + * @rmtoll CR RXEN FL_U7816_DisableRX + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_DisableRX(U7816_Type *U7816x) +{ + CLEAR_BIT(U7816x->CR, U7816_CR_RXEN_Msk); +} + +/** + * @brief Enable U7816 Clock Output + * @rmtoll CR CKOEN FL_U7816_EnableClockOutput + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_EnableClockOutput(U7816_Type *U7816x) +{ + SET_BIT(U7816x->CR, U7816_CR_CKOEN_Msk); +} + +/** + * @brief Get U7816 Clock Output Enable Status + * @rmtoll CR CKOEN FL_U7816_IsEnabledClockOutput + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsEnabledClockOutput(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->CR, U7816_CR_CKOEN_Msk) == U7816_CR_CKOEN_Msk); +} + +/** + * @brief Disable U7816 Clock Output + * @rmtoll CR CKOEN FL_U7816_DisableClockOutput + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_DisableClockOutput(U7816_Type *U7816x) +{ + CLEAR_BIT(U7816x->CR, U7816_CR_CKOEN_Msk); +} + +/** + * @brief Enable U7816 Automatically High-Pullup + * @rmtoll CR HPUAT FL_U7816_EnableTXAutoPullup + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_EnableTXAutoPullup(U7816_Type *U7816x) +{ + SET_BIT(U7816x->CR, U7816_CR_HPUAT_Msk); +} + +/** + * @brief Get U7816 Automatically High-Pullup Enable Status + * @rmtoll CR HPUAT FL_U7816_IsEnabledTXAutoPullup + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsEnabledTXAutoPullup(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->CR, U7816_CR_HPUAT_Msk) == U7816_CR_HPUAT_Msk); +} + +/** + * @brief Disable U7816 Automatically High-Pullup + * @rmtoll CR HPUAT FL_U7816_DisableTXAutoPullup + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_DisableTXAutoPullup(U7816_Type *U7816x) +{ + CLEAR_BIT(U7816x->CR, U7816_CR_HPUAT_Msk); +} + +/** + * @brief Enable U7816 High-Pullup + * @rmtoll CR HPUEN FL_U7816_EnablePullup + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_EnablePullup(U7816_Type *U7816x) +{ + SET_BIT(U7816x->CR, U7816_CR_HPUEN_Msk); +} + +/** + * @brief Disable U7816 High-Pullup + * @rmtoll CR HPUEN FL_U7816_DisablePullup + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_DisablePullup(U7816_Type *U7816x) +{ + CLEAR_BIT(U7816x->CR, U7816_CR_HPUEN_Msk); +} + +/** + * @brief Set U7816 TX Guard Time Length + * @rmtoll FFR SFREN FL_U7816_SetTXGuardTime + * @param U7816x U7816 instance + * @param config This parameter can be one of the following values: + * @arg @ref FL_U7816_TX_GUARD_TIME_2ETU + * @arg @ref FL_U7816_TX_GUARD_TIME_3ETU + * @retval None + */ +__STATIC_INLINE void FL_U7816_SetTXGuardTime(U7816_Type *U7816x, uint32_t config) +{ + MODIFY_REG(U7816x->FFR, U7816_FFR_SFREN_Msk, config); +} + +/** + * @brief Get U7816 TX Guard Time Length + * @rmtoll FFR SFREN FL_U7816_GetTXGuardTime + * @param U7816x U7816 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_U7816_TX_GUARD_TIME_2ETU + * @arg @ref FL_U7816_TX_GUARD_TIME_3ETU + */ +__STATIC_INLINE uint32_t FL_U7816_GetTXGuardTime(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->FFR, U7816_FFR_SFREN_Msk)); +} + +/** + * @brief Set U7816 TX Error Signal Length + * @rmtoll FFR ERSW FL_U7816_SetErrorSignalWidth + * @param U7816x U7816 instance + * @param width This parameter can be one of the following values: + * @arg @ref FL_U7816_ERROR_SIGNAL_WIDTH_2ETU + * @arg @ref FL_U7816_ERROR_SIGNAL_WIDTH_1P5ETU + * @arg @ref FL_U7816_ERROR_SIGNAL_WIDTH_1ETU + * @retval None + */ +__STATIC_INLINE void FL_U7816_SetErrorSignalWidth(U7816_Type *U7816x, uint32_t width) +{ + MODIFY_REG(U7816x->FFR, U7816_FFR_ERSW_Msk, width); +} + +/** + * @brief Get U7816 TX Error Signal Length + * @rmtoll FFR ERSW FL_U7816_GetErrorSignalWidth + * @param U7816x U7816 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_U7816_ERROR_SIGNAL_WIDTH_2ETU + * @arg @ref FL_U7816_ERROR_SIGNAL_WIDTH_1P5ETU + * @arg @ref FL_U7816_ERROR_SIGNAL_WIDTH_1ETU + */ +__STATIC_INLINE uint32_t FL_U7816_GetErrorSignalWidth(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->FFR, U7816_FFR_ERSW_Msk)); +} + +/** + * @brief Set Error Signal Guard Time + * @rmtoll FFR ERSGD FL_U7816_SetErrorGuardTime + * @param U7816x U7816 instance + * @param config This parameter can be one of the following values: + * @arg @ref FL_U7816_ERROR_GUARD_TIME_2ETU + * @arg @ref FL_U7816_ERROR_GUARD_TIME_1ETU + * @retval None + */ +__STATIC_INLINE void FL_U7816_SetErrorGuardTime(U7816_Type *U7816x, uint32_t config) +{ + MODIFY_REG(U7816x->FFR, U7816_FFR_ERSGD_Msk, config); +} + +/** + * @brief Get Error Signal Guard Time + * @rmtoll FFR ERSGD FL_U7816_GetErrorGuardTime + * @param U7816x U7816 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_U7816_ERROR_GUARD_TIME_2ETU + * @arg @ref FL_U7816_ERROR_GUARD_TIME_1ETU + */ +__STATIC_INLINE uint32_t FL_U7816_GetErrorGuardTime(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->FFR, U7816_FFR_ERSGD_Msk)); +} + +/** + * @brief Enable U7816 to Insert Block Guard Time + * @rmtoll FFR BGTEN FL_U7816_EnableBlockGuardTime + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_EnableBlockGuardTime(U7816_Type *U7816x) +{ + SET_BIT(U7816x->FFR, U7816_FFR_BGTEN_Msk); +} + +/** + * @brief Get U7816 Block Guard Time Enable Status + * @rmtoll FFR BGTEN FL_U7816_IsEnabledBlockGuardTime + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsEnabledBlockGuardTime(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->FFR, U7816_FFR_BGTEN_Msk) == U7816_FFR_BGTEN_Msk); +} + +/** + * @brief Disable U7816 to Insert Block Guard Time + * @rmtoll FFR BGTEN FL_U7816_DisableBlockGuardTime + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_DisableBlockGuardTime(U7816_Type *U7816x) +{ + CLEAR_BIT(U7816x->FFR, U7816_FFR_BGTEN_Msk); +} + +/** + * @brief Set U7816 Retry Counts When Parity Error Occurred + * @rmtoll FFR REP_T FL_U7816_SetRetryCount + * @param U7816x U7816 instance + * @param cnt This parameter can be one of the following values: + * @arg @ref FL_U7816_RETRY_COUNT_1 + * @arg @ref FL_U7816_RETRY_COUNT_3 + * @retval None + */ +__STATIC_INLINE void FL_U7816_SetRetryCount(U7816_Type *U7816x, uint32_t cnt) +{ + MODIFY_REG(U7816x->FFR, U7816_FFR_REP_T_Msk, cnt); +} + +/** + * @brief Get U7816 Retry Counts When Parity Error Occurred + * @rmtoll FFR REP_T FL_U7816_GetRetryCount + * @param U7816x U7816 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_U7816_RETRY_COUNT_1 + * @arg @ref FL_U7816_RETRY_COUNT_3 + */ +__STATIC_INLINE uint32_t FL_U7816_GetRetryCount(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->FFR, U7816_FFR_REP_T_Msk)); +} + +/** + * @brief Set U7816 Parity + * @rmtoll FFR PAR FL_U7816_SetParity + * @param U7816x U7816 instance + * @param parity This parameter can be one of the following values: + * @arg @ref FL_U7816_PARITY_EVEN + * @arg @ref FL_U7816_PARITY_ODD + * @arg @ref FL_U7816_PARITY_ALWAYS_1 + * @arg @ref FL_U7816_PARITY_NONE + * @retval None + */ +__STATIC_INLINE void FL_U7816_SetParity(U7816_Type *U7816x, uint32_t parity) +{ + MODIFY_REG(U7816x->FFR, U7816_FFR_PAR_Msk, parity); +} + +/** + * @brief Get U7816 Parity + * @rmtoll FFR PAR FL_U7816_GetParity + * @param U7816x U7816 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_U7816_PARITY_EVEN + * @arg @ref FL_U7816_PARITY_ODD + * @arg @ref FL_U7816_PARITY_ALWAYS_1 + * @arg @ref FL_U7816_PARITY_NONE + */ +__STATIC_INLINE uint32_t FL_U7816_GetParity(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->FFR, U7816_FFR_PAR_Msk)); +} + +/** + * @brief Set U7816 RX Guard Time Length + * @rmtoll FFR RFREN FL_U7816_SetRXGuardTime + * @param U7816x U7816 instance + * @param config This parameter can be one of the following values: + * @arg @ref FL_U7816_RX_GUARD_TIME_2ETU + * @arg @ref FL_U7816_RX_GUARD_TIME_1ETU + * @retval None + */ +__STATIC_INLINE void FL_U7816_SetRXGuardTime(U7816_Type *U7816x, uint32_t config) +{ + MODIFY_REG(U7816x->FFR, U7816_FFR_RFREN_Msk, config); +} + +/** + * @brief Get U7816 RX Guard Time Length + * @rmtoll FFR RFREN FL_U7816_GetRXGuardTime + * @param U7816x U7816 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_U7816_RX_GUARD_TIME_2ETU + * @arg @ref FL_U7816_RX_GUARD_TIME_1ETU + */ +__STATIC_INLINE uint32_t FL_U7816_GetRXGuardTime(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->FFR, U7816_FFR_RFREN_Msk)); +} + +/** + * @brief Set U7816 TX Auto Retry When Parity Error Occurred + * @rmtoll FFR TREPEN FL_U7816_EnableTXParityErrorAutoRetry + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_EnableTXParityErrorAutoRetry(U7816_Type *U7816x) +{ + SET_BIT(U7816x->FFR, U7816_FFR_TREPEN_Msk); +} + +/** + * @brief Get U7816 TX Auto Retry When Parity Error Occurred + * @rmtoll FFR TREPEN FL_U7816_DisableTXParityErrorAutoRetry + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_DisableTXParityErrorAutoRetry(U7816_Type *U7816x) +{ + CLEAR_BIT(U7816x->FFR, U7816_FFR_TREPEN_Msk); +} + +/** + * @brief Get U7816 TX Auto Retry When Parity Error Occurred + * @rmtoll FFR TREPEN FL_U7816_IsEnabledTXParityErrorAutoRetry + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsEnabledTXParityErrorAutoRetry(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->FFR, U7816_FFR_TREPEN_Msk) == U7816_FFR_TREPEN_Msk); +} + +/** + * @brief Get U7816 RX Auto Retry When Parity Error Occurred + * @rmtoll FFR RREPEN FL_U7816_EnableRXParityErrorAutoRetry + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_EnableRXParityErrorAutoRetry(U7816_Type *U7816x) +{ + SET_BIT(U7816x->FFR, U7816_FFR_RREPEN_Msk); +} + +/** + * @brief Get U7816 RX Auto Retry When Parity Error Occurred + * @rmtoll FFR RREPEN FL_U7816_DisableRXParityErrorAutoRetry + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_DisableRXParityErrorAutoRetry(U7816_Type *U7816x) +{ + CLEAR_BIT(U7816x->FFR, U7816_FFR_RREPEN_Msk); +} + +/** + * @brief Get U7816 RX Auto Retry When Parity Error Occurred + * @rmtoll FFR RREPEN FL_U7816_IsEnabledRXParityErrorAutoRetry + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsEnabledRXParityErrorAutoRetry(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->FFR, U7816_FFR_RREPEN_Msk) == U7816_FFR_RREPEN_Msk); +} + +/** + * @brief Set U7816 Bit Order + * @rmtoll FFR DICONV FL_U7816_SetBitOrder + * @param U7816x U7816 instance + * @param order This parameter can be one of the following values: + * @arg @ref FL_U7816_BIT_ORDER_LSB_FIRST + * @arg @ref FL_U7816_BIT_ORDER_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void FL_U7816_SetBitOrder(U7816_Type *U7816x, uint32_t order) +{ + MODIFY_REG(U7816x->FFR, U7816_FFR_DICONV_Msk, order); +} + +/** + * @brief Get U7816 Bit Order + * @rmtoll FFR DICONV FL_U7816_GetBitOrder + * @param U7816x U7816 instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_U7816_BIT_ORDER_LSB_FIRST + * @arg @ref FL_U7816_BIT_ORDER_MSB_FIRST + */ +__STATIC_INLINE uint32_t FL_U7816_GetBitOrder(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->FFR, U7816_FFR_DICONV_Msk)); +} + +/** + * @brief Set U7816 Extra Guard Time + * @rmtoll EGTR FL_U7816_WriteExtraGuardTime + * @param U7816x U7816 instance + * @param time + * @retval None + */ +__STATIC_INLINE void FL_U7816_WriteExtraGuardTime(U7816_Type *U7816x, uint32_t time) +{ + MODIFY_REG(U7816x->EGTR, (0xffU << 0U), (time << 0U)); +} + +/** + * @brief Get U7816 Extra Guard Time + * @rmtoll EGTR FL_U7816_ReadExtraGuardTime + * @param U7816x U7816 instance + * @retval + */ +__STATIC_INLINE uint32_t FL_U7816_ReadExtraGuardTime(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->EGTR, (0xffU << 0U)) >> 0U); +} + +/** + * @brief Set U7816 Clock Divide + * @rmtoll PSC FL_U7816_WriteClockDivision + * @param U7816x U7816 instance + * @param div + * @retval None + */ +__STATIC_INLINE void FL_U7816_WriteClockDivision(U7816_Type *U7816x, uint32_t div) +{ + MODIFY_REG(U7816x->PSC, (0x1fU << 0U), (div << 0U)); +} + +/** + * @brief Get U7816 Clock Divide + * @rmtoll PSC FL_U7816_ReadClockDivision + * @param U7816x U7816 instance + * @retval + */ +__STATIC_INLINE uint32_t FL_U7816_ReadClockDivision(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->PSC, (0x1fU << 0U)) >> 0U); +} + +/** + * @brief Set U7816 BaudRate + * @rmtoll BGR FL_U7816_WriteBaudRate + * @param U7816x U7816 instance + * @param baud + * @retval None + */ +__STATIC_INLINE void FL_U7816_WriteBaudRate(U7816_Type *U7816x, uint32_t baud) +{ + MODIFY_REG(U7816x->BGR, (0xfffU << 0U), (baud << 0U)); +} + +/** + * @brief Get U7816 BaudRate + * @rmtoll BGR FL_U7816_ReadBaudRate + * @param U7816x U7816 instance + * @retval + */ +__STATIC_INLINE uint32_t FL_U7816_ReadBaudRate(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->BGR, (0xfffU << 0U)) >> 0U); +} + +/** + * @brief U7816 Write 1 byte of data + * @rmtoll TXBUF FL_U7816_WriteTXBuff + * @param U7816x U7816 instance + * @param data + * @retval None + */ +__STATIC_INLINE void FL_U7816_WriteTXBuff(U7816_Type *U7816x, uint32_t data) +{ + MODIFY_REG(U7816x->TXBUF, (0xffU << 0U), (data << 0U)); +} + +/** + * @brief U7816 Read 1 byte of data + * @rmtoll RXBUF FL_U7816_ReadRXBuff + * @param U7816x U7816 instance + * @retval + */ +__STATIC_INLINE uint32_t FL_U7816_ReadRXBuff(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->RXBUF, (0xffU << 0U)) >> 0U); +} + +/** + * @brief Disable U7816 Receive Complete Interrupt + * @rmtoll IER RXIE FL_U7816_DisableIT_RXComplete + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_DisableIT_RXComplete(U7816_Type *U7816x) +{ + CLEAR_BIT(U7816x->IER, U7816_IER_RXIE_Msk); +} + +/** + * @brief Enable U7816 Receive Complete Interrupt + * @rmtoll IER RXIE FL_U7816_EnableIT_RXComplete + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_EnableIT_RXComplete(U7816_Type *U7816x) +{ + SET_BIT(U7816x->IER, U7816_IER_RXIE_Msk); +} + +/** + * @brief Get U7816 Receive Complete Interrupt Enable Status + * @rmtoll IER RXIE FL_U7816_IsEnabledIT_RXComplete + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsEnabledIT_RXComplete(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->IER, U7816_IER_RXIE_Msk) == U7816_IER_RXIE_Msk); +} + +/** + * @brief Disable U7816 Transmit Complete Interrupt + * @rmtoll IER TXIE FL_U7816_DisableIT_TXComplete + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_DisableIT_TXComplete(U7816_Type *U7816x) +{ + CLEAR_BIT(U7816x->IER, U7816_IER_TXIE_Msk); +} + +/** + * @brief Enable U7816 Transmit Complete Interrupt + * @rmtoll IER TXIE FL_U7816_EnableIT_TXComplete + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_EnableIT_TXComplete(U7816_Type *U7816x) +{ + SET_BIT(U7816x->IER, U7816_IER_TXIE_Msk); +} + +/** + * @brief Disable U7816 Line Status Interrupt + * @rmtoll IER LSIE FL_U7816_DisableIT_Error + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_DisableIT_Error(U7816_Type *U7816x) +{ + CLEAR_BIT(U7816x->IER, U7816_IER_LSIE_Msk); +} + +/** + * @brief Enable U7816 Line Status Interrupt + * @rmtoll IER LSIE FL_U7816_EnableIT_Error + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_EnableIT_Error(U7816_Type *U7816x) +{ + SET_BIT(U7816x->IER, U7816_IER_LSIE_Msk); +} + +/** + * @brief Get U7816 Line Status Interrupt Enable Status + * @rmtoll IER LSIE FL_U7816_IsEnabledIT_Error + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsEnabledIT_Error(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->IER, U7816_IER_LSIE_Msk) == U7816_IER_LSIE_Msk); +} + +/** + * @brief Get U7816 Waiting for Retry Flag + * @rmtoll ISR WAIT_RPT FL_U7816_IsActiveFlag_WaitRetry + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsActiveFlag_WaitRetry(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->ISR, U7816_ISR_WAIT_RPT_Msk) == (U7816_ISR_WAIT_RPT_Msk)); +} + +/** + * @brief Get U7816 Transmission Busy Flag + * @rmtoll ISR TXBUSY FL_U7816_IsActiveFlag_TXBusy + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsActiveFlag_TXBusy(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->ISR, U7816_ISR_TXBUSY_Msk) == (U7816_ISR_TXBUSY_Msk)); +} + +/** + * @brief Get U7816 Receivement Busy Flag + * @rmtoll ISR RXBUSY FL_U7816_IsActiveFlag_RXBusy + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsActiveFlag_RXBusy(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->ISR, U7816_ISR_RXBUSY_Msk) == (U7816_ISR_RXBUSY_Msk)); +} + +/** + * @brief Get U7816 Transmit Parity Error Flag + * @rmtoll ISR TPARERR FL_U7816_IsActiveFlag_TXParityError + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsActiveFlag_TXParityError(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->ISR, U7816_ISR_TPARERR_Msk) == (U7816_ISR_TPARERR_Msk)); +} + +/** + * @brief Clear U7816 Transmit Parity Error Flag + * @rmtoll ISR TPARERR FL_U7816_ClearFlag_TXParityError + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_ClearFlag_TXParityError(U7816_Type *U7816x) +{ + WRITE_REG(U7816x->ISR, U7816_ISR_TPARERR_Msk); +} + +/** + * @brief Get U7816 Receive Parity Error Flag + * @rmtoll ISR RPARERR FL_U7816_IsActiveFlag_RXParityError + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsActiveFlag_RXParityError(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->ISR, U7816_ISR_RPARERR_Msk) == (U7816_ISR_RPARERR_Msk)); +} + +/** + * @brief Clear U7816 Receive Parity Error Flag + * @rmtoll ISR RPARERR FL_U7816_ClearFlag_RXParityError + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_ClearFlag_RXParityError(U7816_Type *U7816x) +{ + WRITE_REG(U7816x->ISR, U7816_ISR_RPARERR_Msk); +} + +/** + * @brief Get U7816 Receive Frame Error Flag + * @rmtoll ISR FRERR FL_U7816_IsActiveFlag_RXFrameError + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsActiveFlag_RXFrameError(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->ISR, U7816_ISR_FRERR_Msk) == (U7816_ISR_FRERR_Msk)); +} + +/** + * @brief Clear U7816 Receive Frame Error Flag + * @rmtoll ISR FRERR FL_U7816_ClearFlag_RXFrameError + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_ClearFlag_RXFrameError(U7816_Type *U7816x) +{ + WRITE_REG(U7816x->ISR, U7816_ISR_FRERR_Msk); +} + +/** + * @brief Get U7816 Receive Overflow Error Flag + * @rmtoll ISR OVERR FL_U7816_IsActiveFlag_RXOverflow + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsActiveFlag_RXOverflow(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->ISR, U7816_ISR_OVERR_Msk) == (U7816_ISR_OVERR_Msk)); +} + +/** + * @brief Clear U7816 Receive Overflow Error Flag + * @rmtoll ISR OVERR FL_U7816_ClearFlag_RXOverflow + * @param U7816x U7816 instance + * @retval None + */ +__STATIC_INLINE void FL_U7816_ClearFlag_RXOverflow(U7816_Type *U7816x) +{ + WRITE_REG(U7816x->ISR, U7816_ISR_OVERR_Msk); +} + +/** + * @brief Get U7816 Receive Complete Flag + * @rmtoll ISR RXIF FL_U7816_IsActiveFlag_RXComplete + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsActiveFlag_RXComplete(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->ISR, U7816_ISR_RXIF_Msk) == (U7816_ISR_RXIF_Msk)); +} + +/** + * @brief Get U7816 Transmit Buffer Empty Flag + * @rmtoll ISR TXIF FL_U7816_IsActiveFlag_TXBuffEmpty + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsActiveFlag_TXBuffEmpty(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->ISR, U7816_ISR_TXIF_Msk) == (U7816_ISR_TXIF_Msk)); +} + +/** + * @brief Get U7816 Error Flag + * @rmtoll ISR ERRIF FL_U7816_IsActiveFlag_Error + * @param U7816x U7816 instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_U7816_IsActiveFlag_Error(U7816_Type *U7816x) +{ + return (uint32_t)(READ_BIT(U7816x->ISR, U7816_ISR_ERRIF_Msk) == (U7816_ISR_ERRIF_Msk)); +} + +/** + * @} + */ + +/** @defgroup U7816_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_U7816_DeInit(U7816_Type *U7816x); +FL_ErrorStatus FL_U7816_Init(U7816_Type *U7816x, FL_U7816_InitTypeDef *U7816_InitStruct); +void FL_U7816_StructInit(FL_U7816_InitTypeDef *U7816_InitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_U7816_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-27*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_uart.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_uart.h new file mode 100644 index 0000000000..dc9997fc7d --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_uart.h @@ -0,0 +1,1253 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_uart.h + * @author FMSH Application Team + * @brief Head file of UART FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_UART_H +#define __FM33LC0XX_FL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief UART FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup UART_FL_ES_INIT UART Exported Init structures + * @{ + */ + +/** + * @brief FL UART Init Sturcture definition + */ +typedef struct +{ + /** 时钟源选择 */ + uint32_t clockSrc; + + /** 通信波特率 */ + uint32_t baudRate; + + /** 数据宽度 */ + uint32_t dataWidth; + + /** 停止位 */ + uint32_t stopBits; + + /** 奇偶校验位 */ + uint32_t parity; + + /** 传输反向 */ + uint32_t transferDirection; + +} FL_UART_InitTypeDef; + +/** + * @brief FL UART InfraRed Init Sturcture definition + */ +typedef struct +{ + /** 调制极性默认bit1调制 */ + uint32_t polarity; + /** 红外调制占空比 */ + uint32_t modulationDuty; + /** 红外调制频率*/ + uint32_t modulationFrequency; + +} FL_UART_InfraRed_InitTypeDef; + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup UART_FL_Exported_Constants UART Exported Constants + * @{ + */ + +#define UART_IRCR_IRFLAG_Pos (15U) +#define UART_IRCR_IRFLAG_Msk (0x1U << UART_IRCR_IRFLAG_Pos) +#define UART_IRCR_IRFLAG UART_IRCR_IRFLAG_Msk + +#define UART_IRCR_TH_Pos (11U) +#define UART_IRCR_TH_Msk (0xfU << UART_IRCR_TH_Pos) +#define UART_IRCR_TH UART_IRCR_TH_Msk + +#define UART_IRCR_TZBRG_Pos (0U) +#define UART_IRCR_TZBRG_Msk (0x7ffU << UART_IRCR_TZBRG_Pos) +#define UART_IRCR_TZBRG UART_IRCR_TZBRG_Msk + +#define UART_CSR_BUSY_Pos (21U) +#define UART_CSR_BUSY_Msk (0x1U << UART_CSR_BUSY_Pos) +#define UART_CSR_BUSY UART_CSR_BUSY_Msk + +#define UART_CSR_TXIREN_Pos (17U) +#define UART_CSR_TXIREN_Msk (0x1U << UART_CSR_TXIREN_Pos) +#define UART_CSR_TXIREN UART_CSR_TXIREN_Msk + +#define UART_CSR_RXTOEN_Pos (16U) +#define UART_CSR_RXTOEN_Msk (0x1U << UART_CSR_RXTOEN_Pos) +#define UART_CSR_RXTOEN UART_CSR_RXTOEN_Msk + +#define UART_CSR_IOSWAP_Pos (12U) +#define UART_CSR_IOSWAP_Msk (0x1U << UART_CSR_IOSWAP_Pos) +#define UART_CSR_IOSWAP UART_CSR_IOSWAP_Msk + +#define UART_CSR_NEWUP_Pos (11U) +#define UART_CSR_NEWUP_Msk (0x1U << UART_CSR_NEWUP_Pos) +#define UART_CSR_NEWUP UART_CSR_NEWUP_Msk + +#define UART_CSR_DMATXIFCFG_Pos (10U) +#define UART_CSR_DMATXIFCFG_Msk (0x1U << UART_CSR_DMATXIFCFG_Pos) +#define UART_CSR_DMATXIFCFG UART_CSR_DMATXIFCFG_Msk + +#define UART_CSR_BITORD_Pos (9U) +#define UART_CSR_BITORD_Msk (0x1U << UART_CSR_BITORD_Pos) +#define UART_CSR_BITORD UART_CSR_BITORD_Msk + +#define UART_CSR_STOPCFG_Pos (8U) +#define UART_CSR_STOPCFG_Msk (0x1U << UART_CSR_STOPCFG_Pos) +#define UART_CSR_STOPCFG UART_CSR_STOPCFG_Msk + +#define UART_CSR_PDSEL_Pos (6U) +#define UART_CSR_PDSEL_Msk (0x3U << UART_CSR_PDSEL_Pos) +#define UART_CSR_PDSEL UART_CSR_PDSEL_Msk + +#define UART_CSR_PARITY_Pos (4U) +#define UART_CSR_PARITY_Msk (0x3U << UART_CSR_PARITY_Pos) +#define UART_CSR_PARITY UART_CSR_PARITY_Msk + +#define UART_CSR_RXPOL_Pos (3U) +#define UART_CSR_RXPOL_Msk (0x1U << UART_CSR_RXPOL_Pos) +#define UART_CSR_RXPOL UART_CSR_RXPOL_Msk + +#define UART_CSR_TXPOL_Pos (2U) +#define UART_CSR_TXPOL_Msk (0x1U << UART_CSR_TXPOL_Pos) +#define UART_CSR_TXPOL UART_CSR_TXPOL_Msk + +#define UART_CSR_RXEN_Pos (1U) +#define UART_CSR_RXEN_Msk (0x1U << UART_CSR_RXEN_Pos) +#define UART_CSR_RXEN UART_CSR_RXEN_Msk + +#define UART_CSR_TXEN_Pos (0U) +#define UART_CSR_TXEN_Msk (0x1U << UART_CSR_TXEN_Pos) +#define UART_CSR_TXEN UART_CSR_TXEN_Msk + +#define UART_IER_RXTOIE_Pos (11U) +#define UART_IER_RXTOIE_Msk (0x1U << UART_IER_RXTOIE_Pos) +#define UART_IER_RXTOIE UART_IER_RXTOIE_Msk + +#define UART_IER_RXERRIE_Pos (10U) +#define UART_IER_RXERRIE_Msk (0x1U << UART_IER_RXERRIE_Pos) +#define UART_IER_RXERRIE UART_IER_RXERRIE_Msk + +#define UART_IER_RXBFIE_Pos (8U) +#define UART_IER_RXBFIE_Msk (0x1U << UART_IER_RXBFIE_Pos) +#define UART_IER_RXBFIE UART_IER_RXBFIE_Msk + +#define UART_IER_NEWUPIE_Pos (7U) +#define UART_IER_NEWUPIE_Msk (0x1U << UART_IER_NEWUPIE_Pos) +#define UART_IER_NEWUPIE UART_IER_NEWUPIE_Msk + +#define UART_IER_TXBEIE_Pos (1U) +#define UART_IER_TXBEIE_Msk (0x1U << UART_IER_TXBEIE_Pos) +#define UART_IER_TXBEIE UART_IER_TXBEIE_Msk + +#define UART_IER_TXSEIE_Pos (0U) +#define UART_IER_TXSEIE_Msk (0x1U << UART_IER_TXSEIE_Pos) +#define UART_IER_TXSEIE UART_IER_TXSEIE_Msk + +#define UART_ISR_PERR_Pos (18U) +#define UART_ISR_PERR_Msk (0x1U << UART_ISR_PERR_Pos) +#define UART_ISR_PERR UART_ISR_PERR_Msk + +#define UART_ISR_FERR_Pos (17U) +#define UART_ISR_FERR_Msk (0x1U << UART_ISR_FERR_Pos) +#define UART_ISR_FERR UART_ISR_FERR_Msk + +#define UART_ISR_OERR_Pos (16U) +#define UART_ISR_OERR_Msk (0x1U << UART_ISR_OERR_Pos) +#define UART_ISR_OERR UART_ISR_OERR_Msk + +#define UART_ISR_RXTO_Pos (11U) +#define UART_ISR_RXTO_Msk (0x1U << UART_ISR_RXTO_Pos) +#define UART_ISR_RXTO UART_ISR_RXTO_Msk + +#define UART_ISR_RXBF_Pos (8U) +#define UART_ISR_RXBF_Msk (0x1U << UART_ISR_RXBF_Pos) +#define UART_ISR_RXBF UART_ISR_RXBF_Msk + +#define UART_ISR_NEWKF_Pos (7U) +#define UART_ISR_NEWKF_Msk (0x1U << UART_ISR_NEWKF_Pos) +#define UART_ISR_NEWKF UART_ISR_NEWKF_Msk + +#define UART_ISR_TXBE_Pos (1U) +#define UART_ISR_TXBE_Msk (0x1U << UART_ISR_TXBE_Pos) +#define UART_ISR_TXBE UART_ISR_TXBE_Msk + +#define UART_ISR_TXSE_Pos (0U) +#define UART_ISR_TXSE_Msk (0x1U << UART_ISR_TXSE_Pos) +#define UART_ISR_TXSE UART_ISR_TXSE_Msk + +#define UART_TODR_TXDLY_LEN_Pos (8U) +#define UART_TODR_TXDLY_LEN_Msk (0xffU << UART_TODR_TXDLY_LEN_Pos) +#define UART_TODR_TXDLY_LEN UART_TODR_TXDLY_LEN_Msk + +#define UART_TODR_RXTO_LEN_Pos (0U) +#define UART_TODR_RXTO_LEN_Msk (0xffU << UART_TODR_RXTO_LEN_Pos) +#define UART_TODR_RXTO_LEN UART_TODR_RXTO_LEN_Msk + + + +#define FL_UART_INFRARED_POLARITY_NORMAL (0x0U << UART_IRCR_IRFLAG_Pos) +#define FL_UART_INFRARED_POLARITY_INVERT (0x1U << UART_IRCR_IRFLAG_Pos) + + +#define FL_UART_TXIF_MODE_ALWAYS (0x0U << UART_CSR_DMATXIFCFG_Pos) +#define FL_UART_TXIF_MODE_AFTER_DMA (0x1U << UART_CSR_DMATXIFCFG_Pos) + + +#define FL_UART_BIT_ORDER_LSB_FIRST (0x0U << UART_CSR_BITORD_Pos) +#define FL_UART_BIT_ORDER_MSB_FIRST (0x1U << UART_CSR_BITORD_Pos) + + +#define FL_UART_STOP_BIT_WIDTH_1B (0x0U << UART_CSR_STOPCFG_Pos) +#define FL_UART_STOP_BIT_WIDTH_2B (0x1U << UART_CSR_STOPCFG_Pos) + + +#define FL_UART_DATA_WIDTH_7B (0x0U << UART_CSR_PDSEL_Pos) +#define FL_UART_DATA_WIDTH_8B (0x1U << UART_CSR_PDSEL_Pos) +#define FL_UART_DATA_WIDTH_9B (0x2U << UART_CSR_PDSEL_Pos) +#define FL_UART_DATA_WIDTH_6B (0x3U << UART_CSR_PDSEL_Pos) + + +#define FL_UART_PARITY_NONE (0x0U << UART_CSR_PARITY_Pos) +#define FL_UART_PARITY_EVEN (0x1U << UART_CSR_PARITY_Pos) +#define FL_UART_PARITY_ODD (0x2U << UART_CSR_PARITY_Pos) + + +#define FL_UART_RX_POLARITY_NORMAL (0x0U << UART_CSR_RXPOL_Pos) +#define FL_UART_RX_POLARITY_INVERT (0x1U << UART_CSR_RXPOL_Pos) + + +#define FL_UART_TX_POLARITY_NORMAL (0x0U << UART_CSR_TXPOL_Pos) +#define FL_UART_TX_POLARITY_INVERT (0x1U << UART_CSR_TXPOL_Pos) + + +#define FL_UART_DIRECTION_NONE 0x00000000U +#define FL_UART_DIRECTION_RX UART_CSR_RXEN +#define FL_UART_DIRECTION_TX UART_CSR_TXEN +#define FL_UART_DIRECTION_TX_RX (UART_CSR_RXEN | UART_CSR_TXEN) + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup UART_FL_Exported_Functions UART Exported Functions + * @{ + */ + +/** + * @brief Set Infrared Polarity + * @rmtoll IRCR IRFLAG FL_UART_SetIRPolarity + * @param UARTx UART instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_UART_INFRARED_POLARITY_NORMAL + * @arg @ref FL_UART_INFRARED_POLARITY_INVERT + * @retval None + */ +__STATIC_INLINE void FL_UART_SetIRPolarity(UART_COMMON_Type *UARTx, uint32_t polarity) +{ + MODIFY_REG(UARTx->IRCR, UART_IRCR_IRFLAG_Msk, polarity); +} + +/** + * @brief Get Infrared Polarity + * @rmtoll IRCR IRFLAG FL_UART_GetIRPolarity + * @param UARTx UART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_UART_INFRARED_POLARITY_NORMAL + * @arg @ref FL_UART_INFRARED_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_UART_GetIRPolarity(UART_COMMON_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->IRCR, UART_IRCR_IRFLAG_Msk)); +} + +/** + * @brief Set Infrared Modulation Duty + * @rmtoll IRCR TH FL_UART_WriteIRModulationDuty + * @param UARTx UART instance + * @param duty + * @retval None + */ +__STATIC_INLINE void FL_UART_WriteIRModulationDuty(UART_COMMON_Type *UARTx, uint32_t duty) +{ + MODIFY_REG(UARTx->IRCR, (0xfU << 11U), (duty << 11U)); +} + +/** + * @brief Get Infrared Modulation Duty + * @rmtoll IRCR TH FL_UART_ReadIRModulationDuty + * @param UARTx UART instance + * @retval + */ +__STATIC_INLINE uint32_t FL_UART_ReadIRModulationDuty(UART_COMMON_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->IRCR, (0xfU << 11U)) >> 11U); +} + +/** + * @brief Set Infrared Modulation Frequency + * @rmtoll IRCR TZBRG FL_UART_WriteIRModulationFrequency + * @param UARTx UART instance + * @param freq + * @retval None + */ +__STATIC_INLINE void FL_UART_WriteIRModulationFrequency(UART_COMMON_Type *UARTx, uint32_t freq) +{ + MODIFY_REG(UARTx->IRCR, (0x7ffU << 0U), (freq << 0U)); +} + +/** + * @brief Get Infrared Modulation Frequency + * @rmtoll IRCR TZBRG FL_UART_ReadIRModulationFrequency + * @param UARTx UART instance + * @retval + */ +__STATIC_INLINE uint32_t FL_UART_ReadIRModulationFrequency(UART_COMMON_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->IRCR, (0x7ffU << 0U)) >> 0U); +} + +/** + * @brief Get UART Busy Flag + * @rmtoll CSR BUSY FL_UART_IsActiveFlag_Busy + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsActiveFlag_Busy(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->CSR, UART_CSR_BUSY_Msk) == (UART_CSR_BUSY_Msk)); +} + +/** + * @brief Enable UART Infrared Modulation + * @rmtoll CSR TXIREN FL_UART_EnableIRModulation + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_EnableIRModulation(UART_Type *UARTx) +{ + SET_BIT(UARTx->CSR, UART_CSR_TXIREN_Msk); +} + +/** + * @brief Disable UART Infrared Modulation + * @rmtoll CSR TXIREN FL_UART_DisableIRModulation + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_DisableIRModulation(UART_Type *UARTx) +{ + CLEAR_BIT(UARTx->CSR, UART_CSR_TXIREN_Msk); +} + +/** + * @brief Get UART Infrared Modulation Enable Status + * @rmtoll CSR TXIREN FL_UART_IsEnabledIRModulation + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsEnabledIRModulation(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->CSR, UART_CSR_TXIREN_Msk) == UART_CSR_TXIREN_Msk); +} + +/** + * @brief Enable UART Receive Time-Out Function + * @rmtoll CSR RXTOEN FL_UART_EnableRXTimeout + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_EnableRXTimeout(UART_Type *UARTx) +{ + SET_BIT(UARTx->CSR, UART_CSR_RXTOEN_Msk); +} + +/** + * @brief Disable UART Receive Time-Out Function + * @rmtoll CSR RXTOEN FL_UART_DisableRXTimeout + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_DisableRXTimeout(UART_Type *UARTx) +{ + CLEAR_BIT(UARTx->CSR, UART_CSR_RXTOEN_Msk); +} + +/** + * @brief Get UART Receive Time-Out Function Enable Status + * @rmtoll CSR RXTOEN FL_UART_IsEnabledRXTimeout + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsEnabledRXTimeout(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->CSR, UART_CSR_RXTOEN_Msk) == UART_CSR_RXTOEN_Msk); +} + +/** + * @brief Enable UART Pin Swap Between UART TX Pin and RX Pin + * @rmtoll CSR IOSWAP FL_UART_EnablePinSwap + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_EnablePinSwap(UART_Type *UARTx) +{ + SET_BIT(UARTx->CSR, UART_CSR_IOSWAP_Msk); +} + +/** + * @brief Disable UART Pin Swap Between UART TX Pin and RX Pin + * @rmtoll CSR IOSWAP FL_UART_DisablePinSwap + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_DisablePinSwap(UART_Type *UARTx) +{ + CLEAR_BIT(UARTx->CSR, UART_CSR_IOSWAP_Msk); +} + +/** + * @brief Get UART Pin Swap Enable Status Between UART TX Pin and RX Pin + * @rmtoll CSR IOSWAP FL_UART_IsEnabledPinSwap + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsEnabledPinSwap(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->CSR, UART_CSR_IOSWAP_Msk) == UART_CSR_IOSWAP_Msk); +} + +/** + * @brief Enable UART Negtive Edge Wakeup Function + * @note Only UART0 and UART1 Available + * @rmtoll CSR NEWUP FL_UART_EnableFallingEdgeWakeup + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_EnableFallingEdgeWakeup(UART_Type *UARTx) +{ + SET_BIT(UARTx->CSR, UART_CSR_NEWUP_Msk); +} + +/** + * @brief Disable UART Negtive Edge Wakeup Function + * @rmtoll CSR NEWUP FL_UART_DisableFallingEdgeWakeup + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_DisableFallingEdgeWakeup(UART_Type *UARTx) +{ + CLEAR_BIT(UARTx->CSR, UART_CSR_NEWUP_Msk); +} + +/** + * @brief Get UART Negtive Edge Wakeup Function Enable Status + * @rmtoll CSR NEWUP FL_UART_IsEnabledFallingEdgeWakeup + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsEnabledFallingEdgeWakeup(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->CSR, UART_CSR_NEWUP_Msk) == UART_CSR_NEWUP_Msk); +} + +/** + * @brief Set UART DMA Transmit Finish Interrupt + * @note Only DMA Mode Available + * @rmtoll CSR DMATXIFCFG FL_UART_SetTXIFMode + * @param UARTx UART instance + * @param mode This parameter can be one of the following values: + * @arg @ref FL_UART_TXIF_MODE_ALWAYS + * @arg @ref FL_UART_TXIF_MODE_AFTER_DMA + * @retval None + */ +__STATIC_INLINE void FL_UART_SetTXIFMode(UART_Type *UARTx, uint32_t mode) +{ + MODIFY_REG(UARTx->CSR, UART_CSR_DMATXIFCFG_Msk, mode); +} + +/** + * @brief Get UART DMA Transmit Finish Interrupt + * @rmtoll CSR DMATXIFCFG FL_UART_GetTXIFMode + * @param UARTx UART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_UART_TXIF_MODE_ALWAYS + * @arg @ref FL_UART_TXIF_MODE_AFTER_DMA + */ +__STATIC_INLINE uint32_t FL_UART_GetTXIFMode(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->CSR, UART_CSR_DMATXIFCFG_Msk)); +} + +/** + * @brief Set UART Transfer Bit Order + * @rmtoll CSR BITORD FL_UART_SetBitOrder + * @param UARTx UART instance + * @param order This parameter can be one of the following values: + * @arg @ref FL_UART_BIT_ORDER_LSB_FIRST + * @arg @ref FL_UART_BIT_ORDER_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void FL_UART_SetBitOrder(UART_Type *UARTx, uint32_t order) +{ + MODIFY_REG(UARTx->CSR, UART_CSR_BITORD_Msk, order); +} + +/** + * @brief Get UART Transfer Bit Order + * @rmtoll CSR BITORD FL_UART_GetBitOrder + * @param UARTx UART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_UART_BIT_ORDER_LSB_FIRST + * @arg @ref FL_UART_BIT_ORDER_MSB_FIRST + */ +__STATIC_INLINE uint32_t FL_UART_GetBitOrder(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->CSR, UART_CSR_BITORD_Msk)); +} + +/** + * @brief Set UART Stop Bits Length + * @rmtoll CSR STOPCFG FL_UART_SetStopBitsWidth + * @param UARTx UART instance + * @param length This parameter can be one of the following values: + * @arg @ref FL_UART_STOP_BIT_WIDTH_1B + * @arg @ref FL_UART_STOP_BIT_WIDTH_2B + * @retval None + */ +__STATIC_INLINE void FL_UART_SetStopBitsWidth(UART_Type *UARTx, uint32_t length) +{ + MODIFY_REG(UARTx->CSR, UART_CSR_STOPCFG_Msk, length); +} + +/** + * @brief Get UART Stop Bits Length + * @rmtoll CSR STOPCFG FL_UART_GetStopBitsWidth + * @param UARTx UART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_UART_STOP_BIT_WIDTH_1B + * @arg @ref FL_UART_STOP_BIT_WIDTH_2B + */ +__STATIC_INLINE uint32_t FL_UART_GetStopBitsWidth(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->CSR, UART_CSR_STOPCFG_Msk)); +} + +/** + * @brief Set UART Data Width + * @rmtoll CSR PDSEL FL_UART_SetDataWidth + * @param UARTx UART instance + * @param dataWidth This parameter can be one of the following values: + * @arg @ref FL_UART_DATA_WIDTH_7B + * @arg @ref FL_UART_DATA_WIDTH_8B + * @arg @ref FL_UART_DATA_WIDTH_9B + * @arg @ref FL_UART_DATA_WIDTH_6B + * @retval None + */ +__STATIC_INLINE void FL_UART_SetDataWidth(UART_Type *UARTx, uint32_t dataWidth) +{ + MODIFY_REG(UARTx->CSR, UART_CSR_PDSEL_Msk, dataWidth); +} + +/** + * @brief Get UART Data Width + * @rmtoll CSR PDSEL FL_UART_GetDataWidth + * @param UARTx UART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_UART_DATA_WIDTH_7B + * @arg @ref FL_UART_DATA_WIDTH_8B + * @arg @ref FL_UART_DATA_WIDTH_9B + * @arg @ref FL_UART_DATA_WIDTH_6B + */ +__STATIC_INLINE uint32_t FL_UART_GetDataWidth(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->CSR, UART_CSR_PDSEL_Msk)); +} + +/** + * @brief Set UART Parity + * @rmtoll CSR PARITY FL_UART_SetParity + * @param UARTx UART instance + * @param parity This parameter can be one of the following values: + * @arg @ref FL_UART_PARITY_NONE + * @arg @ref FL_UART_PARITY_EVEN + * @arg @ref FL_UART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void FL_UART_SetParity(UART_Type *UARTx, uint32_t parity) +{ + MODIFY_REG(UARTx->CSR, UART_CSR_PARITY_Msk, parity); +} + +/** + * @brief Get UART Parity + * @rmtoll CSR PARITY FL_UART_GetParity + * @param UARTx UART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_UART_PARITY_NONE + * @arg @ref FL_UART_PARITY_EVEN + * @arg @ref FL_UART_PARITY_ODD + */ +__STATIC_INLINE uint32_t FL_UART_GetParity(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->CSR, UART_CSR_PARITY_Msk)); +} + +/** + * @brief Set UART Receive Polarity + * @rmtoll CSR RXPOL FL_UART_SetRXPolarity + * @param UARTx UART instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_UART_RX_POLARITY_NORMAL + * @arg @ref FL_UART_RX_POLARITY_INVERT + * @retval None + */ +__STATIC_INLINE void FL_UART_SetRXPolarity(UART_Type *UARTx, uint32_t polarity) +{ + MODIFY_REG(UARTx->CSR, UART_CSR_RXPOL_Msk, polarity); +} + +/** + * @brief Get UART Receive Polarity + * @rmtoll CSR RXPOL FL_UART_GetRXPolarity + * @param UARTx UART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_UART_RX_POLARITY_NORMAL + * @arg @ref FL_UART_RX_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_UART_GetRXPolarity(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->CSR, UART_CSR_RXPOL_Msk)); +} + +/** + * @brief Set UART Transmit Polarity + * @rmtoll CSR TXPOL FL_UART_SetTXPolarity + * @param UARTx UART instance + * @param polarity This parameter can be one of the following values: + * @arg @ref FL_UART_TX_POLARITY_NORMAL + * @arg @ref FL_UART_TX_POLARITY_INVERT + * @retval None + */ +__STATIC_INLINE void FL_UART_SetTXPolarity(UART_Type *UARTx, uint32_t polarity) +{ + MODIFY_REG(UARTx->CSR, UART_CSR_TXPOL_Msk, polarity); +} + +/** + * @brief Get UART Transmit Polarity + * @rmtoll CSR TXPOL FL_UART_GetTXPolarity + * @param UARTx UART instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_UART_TX_POLARITY_NORMAL + * @arg @ref FL_UART_TX_POLARITY_INVERT + */ +__STATIC_INLINE uint32_t FL_UART_GetTXPolarity(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->CSR, UART_CSR_TXPOL_Msk)); +} + +/** + * @brief Enable UART Receive + * @rmtoll CSR RXEN FL_UART_EnableRX + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_EnableRX(UART_Type *UARTx) +{ + SET_BIT(UARTx->CSR, UART_CSR_RXEN_Msk); +} + +/** + * @brief Disable UART Receive + * @rmtoll CSR RXEN FL_UART_DisableRX + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_DisableRX(UART_Type *UARTx) +{ + CLEAR_BIT(UARTx->CSR, UART_CSR_RXEN_Msk); +} + +/** + * @brief Get UART Receive Enable Status + * @rmtoll CSR RXEN FL_UART_IsEnabledRX + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsEnabledRX(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->CSR, UART_CSR_RXEN_Msk) == UART_CSR_RXEN_Msk); +} + +/** + * @brief Enable UART Transmit + * @rmtoll CSR TXEN FL_UART_EnableTX + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_EnableTX(UART_Type *UARTx) +{ + SET_BIT(UARTx->CSR, UART_CSR_TXEN_Msk); +} + +/** + * @brief Disable UART Receive + * @rmtoll CSR TXEN FL_UART_DisableTX + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_DisableTX(UART_Type *UARTx) +{ + CLEAR_BIT(UARTx->CSR, UART_CSR_TXEN_Msk); +} + +/** + * @brief Get UART Receive Enable Status + * @rmtoll CSR TXEN FL_UART_IsEnabledTX + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsEnabledTX(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->CSR, UART_CSR_TXEN_Msk) == UART_CSR_TXEN_Msk); +} + +/** + * @brief Enable UART Receive Time-Out Interrupt + * @rmtoll IER RXTOIE FL_UART_EnableIT_RXTimeout + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_EnableIT_RXTimeout(UART_Type *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RXTOIE_Msk); +} + +/** + * @brief Disable UART Receive Time-Out Interrupt + * @rmtoll IER RXTOIE FL_UART_DisableIT_RXTimeout + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_DisableIT_RXTimeout(UART_Type *UARTx) +{ + CLEAR_BIT(UARTx->IER, UART_IER_RXTOIE_Msk); +} + +/** + * @brief Get UART Receive Time-Out Interrupt Enable Status + * @rmtoll IER RXTOIE FL_UART_IsEnabledIT_RXTimeout + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsEnabledIT_RXTimeout(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->IER, UART_IER_RXTOIE_Msk) == UART_IER_RXTOIE_Msk); +} + +/** + * @brief Enable UART Receive Error Interrupt + * @rmtoll IER RXERRIE FL_UART_EnableIT_RXError + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_EnableIT_RXError(UART_Type *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RXERRIE_Msk); +} + +/** + * @brief Disable UART Receive Error Interrupt + * @rmtoll IER RXERRIE FL_UART_DisableIT_RXError + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_DisableIT_RXError(UART_Type *UARTx) +{ + CLEAR_BIT(UARTx->IER, UART_IER_RXERRIE_Msk); +} + +/** + * @brief Get UART Receive Error Interrupt Enable Status + * @rmtoll IER RXERRIE FL_UART_IsEnabledIT_RXError + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsEnabledIT_RXError(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->IER, UART_IER_RXERRIE_Msk) == UART_IER_RXERRIE_Msk); +} + +/** + * @brief Enable UART Receive Buffer Full Interrupt + * @rmtoll IER RXBFIE FL_UART_EnableIT_RXBuffFull + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_EnableIT_RXBuffFull(UART_Type *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RXBFIE_Msk); +} + +/** + * @brief Disable UART Receive Buffer Full Interrupt + * @rmtoll IER RXBFIE FL_UART_DisableIT_RXBuffFull + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_DisableIT_RXBuffFull(UART_Type *UARTx) +{ + CLEAR_BIT(UARTx->IER, UART_IER_RXBFIE_Msk); +} + +/** + * @brief Get UART Receive Buffer Full Interrupt Enable Status + * @rmtoll IER RXBFIE FL_UART_IsEnabledIT_RXBuffFull + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsEnabledIT_RXBuffFull(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->IER, UART_IER_RXBFIE_Msk) == UART_IER_RXBFIE_Msk); +} + +/** + * @brief Enable UART Negedge Wakeup Interrupt + * @rmtoll IER NEWUPIE FL_UART_EnableIT_FallingEdgeWakeup + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_EnableIT_FallingEdgeWakeup(UART_Type *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_NEWUPIE_Msk); +} + +/** + * @brief Disable UART Negedge Wakeup Interrupt + * @rmtoll IER NEWUPIE FL_UART_DisableIT_FallingEdgeWakeup + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_DisableIT_FallingEdgeWakeup(UART_Type *UARTx) +{ + CLEAR_BIT(UARTx->IER, UART_IER_NEWUPIE_Msk); +} + +/** + * @brief Get UART Negedge Wakeup Interrupt Enable Status + * @rmtoll IER NEWUPIE FL_UART_IsEnabledIT_FallingEdgeWakeup + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsEnabledIT_FallingEdgeWakeup(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->IER, UART_IER_NEWUPIE_Msk) == UART_IER_NEWUPIE_Msk); +} + +/** + * @brief Enable UART Transmit Buffer Empty Interrupt + * @rmtoll IER TXBEIE FL_UART_EnableIT_TXBuffEmpty + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_EnableIT_TXBuffEmpty(UART_Type *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TXBEIE_Msk); +} + +/** + * @brief Disable UART Transmit Buffer Empty Interrupt + * @rmtoll IER TXBEIE FL_UART_DisableIT_TXBuffEmpty + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_DisableIT_TXBuffEmpty(UART_Type *UARTx) +{ + CLEAR_BIT(UARTx->IER, UART_IER_TXBEIE_Msk); +} + +/** + * @brief Get UART Transmit Buffer Empty Interrupt Enable Status + * @rmtoll IER TXBEIE FL_UART_IsEnabledIT_TXBuffEmpty + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsEnabledIT_TXBuffEmpty(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->IER, UART_IER_TXBEIE_Msk) == UART_IER_TXBEIE_Msk); +} + +/** + * @brief Enable UART Transmit Shift Register Empty Interrupt + * @rmtoll IER TXSEIE FL_UART_EnableIT_TXShiftBuffEmpty + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_EnableIT_TXShiftBuffEmpty(UART_Type *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TXSEIE_Msk); +} + +/** + * @brief Disable UART Transmit Shift Register Empty Interrupt + * @rmtoll IER TXSEIE FL_UART_DisableIT_TXShiftBuffEmpty + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_DisableIT_TXShiftBuffEmpty(UART_Type *UARTx) +{ + CLEAR_BIT(UARTx->IER, UART_IER_TXSEIE_Msk); +} + +/** + * @brief Get UART Transmit Shift Register Empty Interrupt Enable Status + * @rmtoll IER TXSEIE FL_UART_IsEnabledIT_TXShiftBuffEmpty + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsEnabledIT_TXShiftBuffEmpty(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->IER, UART_IER_TXSEIE_Msk) == UART_IER_TXSEIE_Msk); +} + +/** + * @brief Get UART Parity Error Flag + * @rmtoll ISR PERR FL_UART_IsActiveFlag_ParityError + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsActiveFlag_ParityError(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->ISR, UART_ISR_PERR_Msk) == (UART_ISR_PERR_Msk)); +} + +/** + * @brief Clear UART Parity Error Flag + * @rmtoll ISR PERR FL_UART_ClearFlag_ParityError + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_ClearFlag_ParityError(UART_Type *UARTx) +{ + WRITE_REG(UARTx->ISR, UART_ISR_PERR_Msk); +} + +/** + * @brief Get UART Frame Error Flag + * @rmtoll ISR FERR FL_UART_IsActiveFlag_FrameError + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsActiveFlag_FrameError(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->ISR, UART_ISR_FERR_Msk) == (UART_ISR_FERR_Msk)); +} + +/** + * @brief Clear UART Frame Error Flag + * @rmtoll ISR FERR FL_UART_ClearFlag_FrameError + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_ClearFlag_FrameError(UART_Type *UARTx) +{ + WRITE_REG(UARTx->ISR, UART_ISR_FERR_Msk); +} + +/** + * @brief Get UART RX buffer Overflow Error Flag + * @rmtoll ISR OERR FL_UART_IsActiveFlag_RXBuffOverflowError + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsActiveFlag_RXBuffOverflowError(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->ISR, UART_ISR_OERR_Msk) == (UART_ISR_OERR_Msk)); +} + +/** + * @brief Clear UART RX buffer Overflow Error Flag + * @rmtoll ISR OERR FL_UART_ClearFlag_RXBuffOverflowError + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_ClearFlag_RXBuffOverflowError(UART_Type *UARTx) +{ + WRITE_REG(UARTx->ISR, UART_ISR_OERR_Msk); +} + +/** + * @brief Get UART Receive Time-Out Flag + * @rmtoll ISR RXTO FL_UART_IsActiveFlag_RXBuffTimeout + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsActiveFlag_RXBuffTimeout(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->ISR, UART_ISR_RXTO_Msk) == (UART_ISR_RXTO_Msk)); +} + +/** + * @brief Clear UART Receive Time-Out Flag + * @rmtoll ISR RXTO FL_UART_ClearFlag_RXBuffTimeout + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_ClearFlag_RXBuffTimeout(UART_Type *UARTx) +{ + WRITE_REG(UARTx->ISR, UART_ISR_RXTO_Msk); +} + +/** + * @brief Get UART Receive Buffer Full Flag + * @rmtoll ISR RXBF FL_UART_IsActiveFlag_RXBuffFull + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsActiveFlag_RXBuffFull(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->ISR, UART_ISR_RXBF_Msk) == (UART_ISR_RXBF_Msk)); +} + +/** + * @brief Clear UART Receive Buffer Full Flag + * @rmtoll ISR RXBF FL_UART_ClearFlag_RXBuffFull + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_ClearFlag_RXBuffFull(UART_Type *UARTx) +{ + WRITE_REG(UARTx->ISR, UART_ISR_RXBF_Msk); +} + +/** + * @brief Get UART Negedge Wakeup Flag + * @rmtoll ISR NEWKF FL_UART_IsActiveFlag_FallingEdgeWakeup + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsActiveFlag_FallingEdgeWakeup(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->ISR, UART_ISR_NEWKF_Msk) == (UART_ISR_NEWKF_Msk)); +} + +/** + * @brief Clear UART Negedge Wakeup Flag + * @rmtoll ISR NEWKF FL_UART_ClearFlag_FallingEdgeWakeup + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_ClearFlag_FallingEdgeWakeup(UART_Type *UARTx) +{ + WRITE_REG(UARTx->ISR, UART_ISR_NEWKF_Msk); +} + +/** + * @brief Get UART Transmit Buffer Empty Flag + * @rmtoll ISR TXBE FL_UART_IsActiveFlag_TXBuffEmpty + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsActiveFlag_TXBuffEmpty(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->ISR, UART_ISR_TXBE_Msk) == (UART_ISR_TXBE_Msk)); +} + +/** + * @brief Clear UART Transmit Buffer Empty Flag + * @rmtoll ISR TXBE FL_UART_ClearFlag_TXBuffEmpty + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_ClearFlag_TXBuffEmpty(UART_Type *UARTx) +{ + WRITE_REG(UARTx->ISR, UART_ISR_TXBE_Msk); +} + +/** + * @brief Get UART Transmit Shift register Empty Flag + * @rmtoll ISR TXSE FL_UART_IsActiveFlag_TXShiftBuffEmpty + * @param UARTx UART instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_UART_IsActiveFlag_TXShiftBuffEmpty(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->ISR, UART_ISR_TXSE_Msk) == (UART_ISR_TXSE_Msk)); +} + +/** + * @brief Clear UART Transmit Shift register Empty Flag + * @rmtoll ISR TXSE FL_UART_ClearFlag_TXShiftBuffEmpty + * @param UARTx UART instance + * @retval None + */ +__STATIC_INLINE void FL_UART_ClearFlag_TXShiftBuffEmpty(UART_Type *UARTx) +{ + WRITE_REG(UARTx->ISR, UART_ISR_TXSE_Msk); +} + +/** + * @brief Set UART Transmit Delay Length + * @rmtoll TODR TXDLY_LEN FL_UART_WriteTXDelay + * @param UARTx UART instance + * @param time + * @retval None + */ +__STATIC_INLINE void FL_UART_WriteTXDelay(UART_Type *UARTx, uint32_t time) +{ + MODIFY_REG(UARTx->TODR, (0xffU << 8U), (time << 8U)); +} + +/** + * @brief Get UART Transmit Delay Length + * @rmtoll TODR TXDLY_LEN FL_UART_ReadTXDelay + * @param UARTx UART instance + * @retval + */ +__STATIC_INLINE uint32_t FL_UART_ReadTXDelay(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->TODR, (0xffU << 8U)) >> 8U); +} + +/** + * @brief Set UART Receive Time-Out Length + * @rmtoll TODR RXTO_LEN FL_UART_WriteRXTimeout + * @param UARTx UART instance + * @param time + * @retval None + */ +__STATIC_INLINE void FL_UART_WriteRXTimeout(UART_Type *UARTx, uint32_t time) +{ + MODIFY_REG(UARTx->TODR, (0xffU << 0U), (time << 0U)); +} + +/** + * @brief Get UART Receive Time-Out Length + * @rmtoll TODR RXTO_LEN FL_UART_ReadRXTimeout + * @param UARTx UART instance + * @retval + */ +__STATIC_INLINE uint32_t FL_UART_ReadRXTimeout(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->TODR, (0xffU << 0U)) >> 0U); +} + +/** + * @brief UART Receive 1 byte of data + * @rmtoll RXBUF FL_UART_ReadRXBuff + * @param UARTx UART instance + * @retval + */ +__STATIC_INLINE uint32_t FL_UART_ReadRXBuff(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RXBUF, 0x1ffU)); +} + +/** + * @brief UART Transmit 1 byte of data + * @rmtoll TXBUF FL_UART_WriteTXBuff + * @param UARTx UART instance + * @param data + * @retval None + */ +__STATIC_INLINE void FL_UART_WriteTXBuff(UART_Type *UARTx, uint32_t data) +{ + MODIFY_REG(UARTx->TXBUF, 0x1ffU, data); +} + +/** + * @brief Set UART BaudRate + * @rmtoll BGR FL_UART_WriteBaudRate + * @param UARTx UART instance + * @param baudRate + * @retval None + */ +__STATIC_INLINE void FL_UART_WriteBaudRate(UART_Type *UARTx, uint32_t baudRate) +{ + MODIFY_REG(UARTx->BGR, (0xffffU << 0U), (baudRate << 0U)); +} + +/** + * @brief Get UART BaudRate + * @rmtoll BGR FL_UART_ReadBaudRate + * @param UARTx UART instance + * @retval + */ +__STATIC_INLINE uint32_t FL_UART_ReadBaudRate(UART_Type *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->BGR, (0xffffU << 0U)) >> 0U); +} + +/** + * @} + */ + +/** @defgroup UART_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_UART_DeInit(UART_Type *UARTx); +FL_ErrorStatus FL_UART_Init(UART_Type *UARTx, FL_UART_InitTypeDef *initStruct); +FL_ErrorStatus FL_UART_InfraRed_Init(UART_Type *UARTx, FL_UART_InfraRed_InitTypeDef *initStruct); +void FL_UART_InfraRed_StructInit(FL_UART_InfraRed_InitTypeDef *initStruct); +void FL_UART_StructInit(FL_UART_InitTypeDef *initStruct); + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_UART_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-27*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_vref.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_vref.h new file mode 100644 index 0000000000..1ac4f2e675 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_vref.h @@ -0,0 +1,410 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_vref.h + * @author FMSH Application Team + * @brief Head file of VREF FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_VREF_H +#define __FM33LC0XX_FL_VREF_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup VREF VREF + * @brief VREF FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup VREF_FL_ES_INIT VREF Exported Init structures + * @{ + */ + +/** + * @} + */ +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup VREF_FL_Exported_Constants VREF Exported Constants + * @{ + */ + +#define VREF_CR_VREF_EN_Pos (0U) +#define VREF_CR_VREF_EN_Msk (0x1U << VREF_CR_VREF_EN_Pos) +#define VREF_CR_VREF_EN VREF_CR_VREF_EN_Msk + +#define VREF_CR_PTAT_EN_Pos (1U) +#define VREF_CR_PTAT_EN_Msk (0x1U << VREF_CR_PTAT_EN_Pos) +#define VREF_CR_PTAT_EN VREF_CR_PTAT_EN_Msk + +#define VREF_SR_FLAG_Pos (8U) +#define VREF_SR_FLAG_Msk (0x1U << VREF_SR_FLAG_Pos) +#define VREF_SR_FLAG VREF_SR_FLAG_Msk + +#define VREF_SR_RDY_Pos (1U) +#define VREF_SR_RDY_Msk (0x1U << VREF_SR_RDY_Pos) +#define VREF_SR_RDY VREF_SR_RDY_Msk + +#define VREF_SR_IF_Pos (0U) +#define VREF_SR_IF_Msk (0x1U << VREF_SR_IF_Pos) +#define VREF_SR_IF VREF_SR_IF_Msk + +#define VREF_IER_IE_Pos (0U) +#define VREF_IER_IE_Msk (0x1U << VREF_IER_IE_Pos) +#define VREF_IER_IE VREF_IER_IE_Msk + +#define VREF_BUFCR_VPTATBUFFER_OUTEN_Pos (3U) +#define VREF_BUFCR_VPTATBUFFER_OUTEN_Msk (0x1U << VREF_BUFCR_VPTATBUFFER_OUTEN_Pos) +#define VREF_BUFCR_VPTATBUFFER_OUTEN VREF_BUFCR_VPTATBUFFER_OUTEN_Msk + +#define VREF_BUFCR_VPTATBUFFER_EN_Pos (2U) +#define VREF_BUFCR_VPTATBUFFER_EN_Msk (0x1U << VREF_BUFCR_VPTATBUFFER_EN_Pos) +#define VREF_BUFCR_VPTATBUFFER_EN VREF_BUFCR_VPTATBUFFER_EN_Msk + +#define VREF_BUFCR_VREFBUFFER_OUTEN_Pos (1U) +#define VREF_BUFCR_VREFBUFFER_OUTEN_Msk (0x1U << VREF_BUFCR_VREFBUFFER_OUTEN_Pos) +#define VREF_BUFCR_VREFBUFFER_OUTEN VREF_BUFCR_VREFBUFFER_OUTEN_Msk + +#define VREF_BUFCR_VREFBUFFER_EN_Pos (0U) +#define VREF_BUFCR_VREFBUFFER_EN_Msk (0x1U << VREF_BUFCR_VREFBUFFER_EN_Pos) +#define VREF_BUFCR_VREFBUFFER_EN VREF_BUFCR_VREFBUFFER_EN_Msk + + + + + + +/** + * @} + */ +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup VREF_FL_Exported_Functions VREF Exported Functions + * @{ + */ + +/** + * @brief Enable VREF + * @rmtoll CR VREF_EN FL_VREF_Enable + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_Enable(VREF_Type *VREFx) +{ + SET_BIT(VREFx->CR, VREF_CR_VREF_EN_Msk); +} + +/** + * @brief Get VREF Enable Status + * @rmtoll CR VREF_EN FL_VREF_IsEnabled + * @param VREFx VREF instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_VREF_IsEnabled(VREF_Type *VREFx) +{ + return (uint32_t)(READ_BIT(VREFx->CR, VREF_CR_VREF_EN_Msk) == VREF_CR_VREF_EN_Msk); +} + +/** + * @brief Disable VREF + * @rmtoll CR VREF_EN FL_VREF_Disable + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_Disable(VREF_Type *VREFx) +{ + CLEAR_BIT(VREFx->CR, VREF_CR_VREF_EN_Msk); +} + +/** + * @brief Enable Temperatue Sensor + * @rmtoll CR PTAT_EN FL_VREF_EnableTemperatureSensor + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_EnableTemperatureSensor(VREF_Type *VREFx) +{ + SET_BIT(VREFx->CR, VREF_CR_PTAT_EN_Msk); +} + +/** + * @brief Get Temperatue Sensor Enable Status + * @rmtoll CR PTAT_EN FL_VREF_IsEnabledTemperatureSensor + * @param VREFx VREF instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_VREF_IsEnabledTemperatureSensor(VREF_Type *VREFx) +{ + return (uint32_t)(READ_BIT(VREFx->CR, VREF_CR_PTAT_EN_Msk) == VREF_CR_PTAT_EN_Msk); +} + +/** + * @brief Disable Temperatue Sensor + * @rmtoll CR PTAT_EN FL_VREF_DisableTemperatureSensor + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_DisableTemperatureSensor(VREF_Type *VREFx) +{ + CLEAR_BIT(VREFx->CR, VREF_CR_PTAT_EN_Msk); +} + +/** + * @brief Get VREF Setable Flag From Analog + * @rmtoll SR FLAG FL_VREF_IsActiveFlag_AnalogReady + * @param VREFx VREF instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_VREF_IsActiveFlag_AnalogReady(VREF_Type *VREFx) +{ + return (uint32_t)(READ_BIT(VREFx->SR, VREF_SR_FLAG_Msk) == (VREF_SR_FLAG_Msk)); +} + +/** + * @brief Get VREF Ready Flag + * @rmtoll SR RDY FL_VREF_IsActiveFlag_DigitalReady + * @param VREFx VREF instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_VREF_IsActiveFlag_DigitalReady(VREF_Type *VREFx) +{ + return (uint32_t)(READ_BIT(VREFx->SR, VREF_SR_RDY_Msk) == (VREF_SR_RDY_Msk)); +} + +/** + * @brief Get VREF Ready Interrupt Flag + * @rmtoll SR IF FL_VREF_IsActiveFlag_Ready + * @param VREFx VREF instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_VREF_IsActiveFlag_Ready(VREF_Type *VREFx) +{ + return (uint32_t)(READ_BIT(VREFx->SR, VREF_SR_IF_Msk) == (VREF_SR_IF_Msk)); +} + +/** + * @brief Clear VREF Ready Interrupt Flag + * @rmtoll SR IF FL_VREF_ClearFlag_Ready + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_ClearFlag_Ready(VREF_Type *VREFx) +{ + WRITE_REG(VREFx->SR, VREF_SR_IF_Msk); +} + +/** + * @brief Enable VREF Ready Interrupt + * @rmtoll IER IE FL_VREF_EnableIT_Ready + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_EnableIT_Ready(VREF_Type *VREFx) +{ + SET_BIT(VREFx->IER, VREF_IER_IE_Msk); +} + +/** + * @brief Get VREF Ready Interrupt Enable Status + * @rmtoll IER IE FL_VREF_IsEnabledIT_Ready + * @param VREFx VREF instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_VREF_IsEnabledIT_Ready(VREF_Type *VREFx) +{ + return (uint32_t)(READ_BIT(VREFx->IER, VREF_IER_IE_Msk) == VREF_IER_IE_Msk); +} + +/** + * @brief Disable VREF Ready Interrupt + * @rmtoll IER IE FL_VREF_DisableIT_Ready + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_DisableIT_Ready(VREF_Type *VREFx) +{ + CLEAR_BIT(VREFx->IER, VREF_IER_IE_Msk); +} + +/** + * @brief Enable VPTAT Buffer Output + * @rmtoll BUFCR VPTATBUFFER_OUTEN FL_VREF_EnableVPTATBufferOutput + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_EnableVPTATBufferOutput(VREF_Type *VREFx) +{ + SET_BIT(VREFx->BUFCR, VREF_BUFCR_VPTATBUFFER_OUTEN_Msk); +} + +/** + * @brief Get VPTAT Buffer Output Enable Status + * @rmtoll BUFCR VPTATBUFFER_OUTEN FL_VREF_IsEnabledVPTATBufferOutput + * @param VREFx VREF instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_VREF_IsEnabledVPTATBufferOutput(VREF_Type *VREFx) +{ + return (uint32_t)(READ_BIT(VREFx->BUFCR, VREF_BUFCR_VPTATBUFFER_OUTEN_Msk) == VREF_BUFCR_VPTATBUFFER_OUTEN_Msk); +} + +/** + * @brief Disable VPTAT Buffer Output + * @rmtoll BUFCR VPTATBUFFER_OUTEN FL_VREF_DisableVPTATBufferOutput + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_DisableVPTATBufferOutput(VREF_Type *VREFx) +{ + CLEAR_BIT(VREFx->BUFCR, VREF_BUFCR_VPTATBUFFER_OUTEN_Msk); +} + +/** + * @brief Enable VPTAT Buffer + * @rmtoll BUFCR VPTATBUFFER_EN FL_VREF_EnableVPTATBuffer + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_EnableVPTATBuffer(VREF_Type *VREFx) +{ + SET_BIT(VREFx->BUFCR, VREF_BUFCR_VPTATBUFFER_EN_Msk); +} + +/** + * @brief Get VPTAT Buffer Enable Status + * @rmtoll BUFCR VPTATBUFFER_EN FL_VREF_IsEnabledVPTATBuffer + * @param VREFx VREF instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_VREF_IsEnabledVPTATBuffer(VREF_Type *VREFx) +{ + return (uint32_t)(READ_BIT(VREFx->BUFCR, VREF_BUFCR_VPTATBUFFER_EN_Msk) == VREF_BUFCR_VPTATBUFFER_EN_Msk); +} + +/** + * @brief Disable VPTAT Buffer + * @rmtoll BUFCR VPTATBUFFER_EN FL_VREF_DisableVPTATBuffer + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_DisableVPTATBuffer(VREF_Type *VREFx) +{ + CLEAR_BIT(VREFx->BUFCR, VREF_BUFCR_VPTATBUFFER_EN_Msk); +} + +/** + * @brief Enable VREF Buffer Output + * @rmtoll BUFCR VREFBUFFER_OUTEN FL_VREF_EnableVREFBufferOutput + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_EnableVREFBufferOutput(VREF_Type *VREFx) +{ + SET_BIT(VREFx->BUFCR, VREF_BUFCR_VREFBUFFER_OUTEN_Msk); +} + +/** + * @brief Get VREF Buffer Output Enable Status + * @rmtoll BUFCR VREFBUFFER_OUTEN FL_VREF_IsEnabledVREFBufferOutput + * @param VREFx VREF instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_VREF_IsEnabledVREFBufferOutput(VREF_Type *VREFx) +{ + return (uint32_t)(READ_BIT(VREFx->BUFCR, VREF_BUFCR_VREFBUFFER_OUTEN_Msk) == VREF_BUFCR_VREFBUFFER_OUTEN_Msk); +} + +/** + * @brief Disable VREF Buffer Output + * @rmtoll BUFCR VREFBUFFER_OUTEN FL_VREF_DisableVREFBufferOutput + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_DisableVREFBufferOutput(VREF_Type *VREFx) +{ + CLEAR_BIT(VREFx->BUFCR, VREF_BUFCR_VREFBUFFER_OUTEN_Msk); +} + +/** + * @brief Enable VREF Buffer + * @rmtoll BUFCR VREFBUFFER_EN FL_VREF_EnableVREFBuffer + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_EnableVREFBuffer(VREF_Type *VREFx) +{ + SET_BIT(VREFx->BUFCR, VREF_BUFCR_VREFBUFFER_EN_Msk); +} + +/** + * @brief Get VREF Buffer Enable Status + * @rmtoll BUFCR VREFBUFFER_EN FL_VREF_IsEnabledVREFBuffer + * @param VREFx VREF instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_VREF_IsEnabledVREFBuffer(VREF_Type *VREFx) +{ + return (uint32_t)(READ_BIT(VREFx->BUFCR, VREF_BUFCR_VREFBUFFER_EN_Msk) == VREF_BUFCR_VREFBUFFER_EN_Msk); +} + +/** + * @brief Disable VREF Buffer + * @rmtoll BUFCR VREFBUFFER_EN FL_VREF_DisableVREFBuffer + * @param VREFx VREF instance + * @retval None + */ +__STATIC_INLINE void FL_VREF_DisableVREFBuffer(VREF_Type *VREFx) +{ + CLEAR_BIT(VREFx->BUFCR, VREF_BUFCR_VREFBUFFER_EN_Msk); +} + +/** + * @} + */ + +/** @defgroup VREF_FL_EF_Init Initialization and de-initialization functions + * @{ + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_VREF_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_wwdt.h b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_wwdt.h new file mode 100644 index 0000000000..43c63f0ea9 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/fm33lc0xx_fl_wwdt.h @@ -0,0 +1,265 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_wwdt.h + * @author FMSH Application Team + * @brief Head file of WWDT FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + + +/* Define to prevent recursive inclusion---------------------------------------------------------------*/ +#ifndef __FM33LC0XX_FL_WWDT_H +#define __FM33LC0XX_FL_WWDT_H + +#ifdef __cplusplus +extern "C" { +#endif +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @defgroup WWDT WWDT + * @brief WWDT FL driver + * @{ + */ + +/* Exported types -------------------------------------------------------------------------------------*/ +/** @defgroup WWDT_FL_ES_INIT WWDT Exported Init structures + * @{ + */ + +/** + * @brief WWDT Init Sturcture definition + */ +typedef struct +{ + /** 看门狗溢出周期 */ + uint32_t overflowPeriod; + +} FL_WWDT_InitTypeDef; + +/** + * @} + */ + +/* Exported constants ---------------------------------------------------------------------------------*/ +/** @defgroup WWDT_FL_Exported_Constants WWDT Exported Constants + * @{ + */ + +#define WWDT_CR_CON_Pos (0U) +#define WWDT_CR_CON_Msk (0x7fU << WWDT_CR_CON_Pos) +#define WWDT_CR_CON WWDT_CR_CON_Msk + +#define WWDT_CFGR_CFG_Pos (0U) +#define WWDT_CFGR_CFG_Msk (0x7U << WWDT_CFGR_CFG_Pos) +#define WWDT_CFGR_CFG WWDT_CFGR_CFG_Msk + +#define WWDT_IER_IE_Pos (0U) +#define WWDT_IER_IE_Msk (0x1U << WWDT_IER_IE_Pos) +#define WWDT_IER_IE WWDT_IER_IE_Msk + +#define WWDT_ISR_IF_Pos (0U) +#define WWDT_ISR_IF_Msk (0x1U << WWDT_ISR_IF_Pos) +#define WWDT_ISR_IF WWDT_ISR_IF_Msk + + + + + + +#define FL_WWDT_KEY_ENABLE (0x5AU << WWDT_CR_CON_Pos) + +#define FL_WWDT_RELOAD_ENABLE (0xACU << WWDT_CR_CON_Pos) + +#define FL_WWDT_PERIOD_1CNT (0x0U << WWDT_CFGR_CFG_Pos) +#define FL_WWDT_PERIOD_4CNT (0x1U << WWDT_CFGR_CFG_Pos) +#define FL_WWDT_PERIOD_16CNT (0x2U << WWDT_CFGR_CFG_Pos) +#define FL_WWDT_PERIOD_64CNT (0x3U << WWDT_CFGR_CFG_Pos) +#define FL_WWDT_PERIOD_128CNT (0x4U << WWDT_CFGR_CFG_Pos) +#define FL_WWDT_PERIOD_256CNT (0x5U << WWDT_CFGR_CFG_Pos) +#define FL_WWDT_PERIOD_512CNT (0x6U << WWDT_CFGR_CFG_Pos) +#define FL_WWDT_PERIOD_1024CNT (0x7U << WWDT_CFGR_CFG_Pos) + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------------------------------*/ +/** @defgroup WWDT_FL_Exported_Functions WWDT Exported Functions + * @{ + */ + +/** + * @brief WWDT enable counter + * @rmtoll CR CON FL_WWDT_Enable + * @param WWDTx WWDT instance + * @retval None + */ +__STATIC_INLINE void FL_WWDT_Enable(WWDT_Type *WWDTx) +{ + WRITE_REG(WWDTx->CR, FL_WWDT_KEY_ENABLE); +} + +/** + * @brief WWDT reset counter + * @rmtoll CR CON FL_WWDT_ReloadCounter + * @param WWDTx WWDT instance + * @retval None + */ +__STATIC_INLINE void FL_WWDT_ReloadCounter(WWDT_Type *WWDTx) +{ + WRITE_REG(WWDTx->CR, FL_WWDT_RELOAD_ENABLE); +} + +/** + * @brief Set WWDT overflow period + * @rmtoll CFGR CFG FL_WWDT_SetPeriod + * @param WWDTx WWDT instance + * @param period This parameter can be one of the following values: + * @arg @ref FL_WWDT_PERIOD_1CNT + * @arg @ref FL_WWDT_PERIOD_4CNT + * @arg @ref FL_WWDT_PERIOD_16CNT + * @arg @ref FL_WWDT_PERIOD_64CNT + * @arg @ref FL_WWDT_PERIOD_128CNT + * @arg @ref FL_WWDT_PERIOD_256CNT + * @arg @ref FL_WWDT_PERIOD_512CNT + * @arg @ref FL_WWDT_PERIOD_1024CNT + * @retval None + */ +__STATIC_INLINE void FL_WWDT_SetPeriod(WWDT_Type *WWDTx, uint32_t period) +{ + MODIFY_REG(WWDTx->CFGR, WWDT_CFGR_CFG_Msk, period); +} + +/** + * @brief Get WWDT overflow period + * @rmtoll CFGR CFG FL_WWDT_GetPeriod + * @param WWDTx WWDT instance + * @retval Returned value can be one of the following values: + * @arg @ref FL_WWDT_PERIOD_1CNT + * @arg @ref FL_WWDT_PERIOD_4CNT + * @arg @ref FL_WWDT_PERIOD_16CNT + * @arg @ref FL_WWDT_PERIOD_64CNT + * @arg @ref FL_WWDT_PERIOD_128CNT + * @arg @ref FL_WWDT_PERIOD_256CNT + * @arg @ref FL_WWDT_PERIOD_512CNT + * @arg @ref FL_WWDT_PERIOD_1024CNT + */ +__STATIC_INLINE uint32_t FL_WWDT_GetPeriod(WWDT_Type *WWDTx) +{ + return (uint32_t)(READ_BIT(WWDTx->CFGR, WWDT_CFGR_CFG_Msk)); +} + +/** + * @brief Get WWDT Counter value + * @rmtoll CNT FL_WWDT_ReadCounter + * @param WWDTx WWDT instance + * @retval + */ +__STATIC_INLINE uint32_t FL_WWDT_ReadCounter(WWDT_Type *WWDTx) +{ + return (uint32_t)(READ_BIT(WWDTx->CNT, (0xfffU << 0U)) >> 0U); +} + +/** + * @brief WWDT interrupt enable + * @rmtoll IER IE FL_WWDT_EnableIT_NearOverflow + * @param WWDTx WWDT instance + * @retval None + */ +__STATIC_INLINE void FL_WWDT_EnableIT_NearOverflow(WWDT_Type *WWDTx) +{ + SET_BIT(WWDTx->IER, WWDT_IER_IE_Msk); +} + +/** + * @brief WWDT interrupt enable status + * @rmtoll IER IE FL_WWDT_IsEnabledIT_NearOverflow + * @param WWDTx WWDT instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_WWDT_IsEnabledIT_NearOverflow(WWDT_Type *WWDTx) +{ + return (uint32_t)(READ_BIT(WWDTx->IER, WWDT_IER_IE_Msk) == WWDT_IER_IE_Msk); +} + +/** + * @brief WWDT interrupt disable + * @rmtoll IER IE FL_WWDT_DisableIT_NearOverflow + * @param WWDTx WWDT instance + * @retval None + */ +__STATIC_INLINE void FL_WWDT_DisableIT_NearOverflow(WWDT_Type *WWDTx) +{ + CLEAR_BIT(WWDTx->IER, WWDT_IER_IE_Msk); +} + +/** + * @brief Get WWDT 75% overflow flag + * @rmtoll ISR IF FL_WWDT_IsActiveFlag_NearOverflow + * @param WWDTx WWDT instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t FL_WWDT_IsActiveFlag_NearOverflow(WWDT_Type *WWDTx) +{ + return (uint32_t)(READ_BIT(WWDTx->ISR, WWDT_ISR_IF_Msk) == (WWDT_ISR_IF_Msk)); +} + +/** + * @brief Clear WWDT 75% overflow flag + * @rmtoll ISR IF FL_WWDT_ClearFlag_NearOverflow + * @param WWDTx WWDT instance + * @retval None + */ +__STATIC_INLINE void FL_WWDT_ClearFlag_NearOverflow(WWDT_Type *WWDTx) +{ + WRITE_REG(WWDTx->ISR, WWDT_ISR_IF_Msk); +} + +/** + * @} + */ + +/** @defgroup WWDT_FL_EF_Init Initialization and de-initialization functions + * @{ + */ +FL_ErrorStatus FL_WWDT_DeInit(WWDT_Type *WWDTx); +FL_ErrorStatus FL_WWDT_Init(WWDT_Type *WWDTx, FL_WWDT_InitTypeDef *WWDT_InitStruct); +void FL_WWDT_StructInit(FL_WWDT_InitTypeDef *WWDT_InitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FM33LC0XX_FL_WWDT_H*/ + +/*************************Py_Code_Generator Version: 0.1-0.11-0.2 @ 2020-09-23*************************/ +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/SConscript b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/SConscript new file mode 100644 index 0000000000..8585d46077 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/SConscript @@ -0,0 +1,49 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +CMSIS/system_fm33lc0xx.c +Src/fm33lc0xx_fl_dma.c +Src/fm33lc0xx_fl_crc.c +Src/fm33lc0xx_fl_rcc.c +Src/fm33lc0xx_fl_gpio.c +""") + +if GetDepend(['RT_USING_SERIAL']): + src += ['Src/fm33lc0xx_fl_uart.c'] + src += ['Src/fm33lc0xx_fl_lpuart.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['Src/fm33lc0xx_fl_i2c.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['Src/fm33lc0xx_fl_spi.c'] + +if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): + src += ['Src/fm33lc0xx_fl_atim.c'] + src += ['Src/fm33lc0xx_fl_bstim32.c'] + +if GetDepend(['RT_USING_ADC']): + src += ['Src/fm33lc0xx_fl_adc.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['Src/fm33lc0xx_fl_rtc.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['Src/fm33lc0xx_fl_wwdt.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH']): + src += ['Src/fm33lc0xx_fl_flash.c'] + +path = [cwd + '/CMSIS/Include', + cwd + '/Inc'] + +CPPDEFINES = ['USE_HAL_DRIVER'] +group = DefineGroup('FM33LC0xx_FL_Driver', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl.c new file mode 100644 index 0000000000..691f07109a --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl.c @@ -0,0 +1,137 @@ +/** + **************************************************************************************************** + * @file fm33lc0xx_fl.c + * @author FMSH Application Team + * @brief Source file of FL Driver Library + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ + +/* Includes -------------------------------------------------------------------------------------------*/ +#include "fm33lc0xx_fl.h" + +/** @addtogroup FL_EF_DELAY + * @{ + */ + +/** + * @brief Initialize the timer(default is Systick) used as delay timer. + * @note The function is declared as __WEAK to be overwritten in case of other + * implementation in user file. + * @param None + * @retval None + */ +__WEAK void FL_DelayInit(void) +{ + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief Provide block delay in microseconds. + * @note The function is declared as __WEAK to be overwritten in case of other + * implementation in user file. + * @param count specifies the delay count in microseconds. + * @retval None + */ +__WEAK void FL_DelayUs(uint32_t count) +{ + count = FL_DELAY_US * count; + count = count > 16777216 ? 16777216 : count; + SysTick->LOAD = count - 1; + SysTick->VAL = 0; + while(!((SysTick->CTRL >> 16) & 0x1)); +} + +/** + * @brief Provide blocking delay in milliseconds. + * @note The function is declared as __WEAK to be overwritten in case of other + * implementation in user file. + * @param count specifies the delay count in milliseconds. + * @retval None + */ +__WEAK void FL_DelayMs(uint32_t count) +{ + while(count--) + { + FL_DelayUs(1000); + } +} + +/** + * @brief Provide no-blocking delay initialization in microseconds. + * @note Should be follow By while(!FL_DelayEnd()){ ** user code ** } immediately. + The function is declared as __WEAK to be overwritten in case of other + * implementation in user file. + * @param count specifies the delay count in microseconds. + * @retval None + */ +__WEAK void FL_DelayUsStart(uint32_t count) +{ + count = FL_DELAY_US * count; + count = count > 16777216 ? 16777216 : count; + SysTick->LOAD = count - 1; + SysTick->VAL = 0; +} + +/** + * @brief Provide no-blocking delay initialization in milliseconds. + * @note Should be followed By while(!FL_DelayEnd()){ ** user code ** }. + * The function is declared as __WEAK to be overwritten in case of other + * implementation in user file. + * @param count specifies the delay count in milliseconds. + * @retval None + */ +__WEAK void FL_DelayMsStart(uint32_t count) +{ + FL_DelayUsStart(1000 * count); +} + +/** + * @brief Showing if the no-blocking delay has ended. + * @note Should be used with FL_DelayMs/UsStart() function. + The function is declared as __WEAK to be overwritten in case of other + * implementation in user file. + * @param count specifies the delay count in milliseconds. + * @retval true - delay has ended + * false - delay is in progress + */ +__WEAK bool FL_DelayEnd(void) +{ + return (((SysTick->CTRL >> 16) & 0x1) == 0x1); +} + +/** + *@} + */ + +/** @addtogroup FL_EF_DELAY + * @{ + */ + +void FL_Init(void) +{ + // Init delay support function + FL_DelayInit(); +} + +/** + *@} + */ + +/*************************(C) COPYRIGHT Fudan Microelectronics **** END OF FILE*************************/ + + + diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_adc.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_adc.c new file mode 100644 index 0000000000..89f3d99c27 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_adc.c @@ -0,0 +1,361 @@ +/** + **************************************************************************************************** + * @file fm33lc0xx_fl_adc.c + * @author FMSH Application Team + * @brief Src file of ADC FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_adc.h" +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_rmu.h" +#include "fm33lc0xx_fl_svd.h" +#include "fm33lc0xx_fl_vref.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup ADC_FL_Private_Macros + * @{ + */ + +#define IS_FL_ADC_INSTANCE(INSTANCE) ((INSTANCE) == ADC) + +#define IS_FL_ADC_ADCCLK_SOURCE(__VALUE__) (((__VALUE__) == FL_RCC_ADC_CLK_SOURCE_RCMF_PSC)||\ + ((__VALUE__) == FL_RCC_ADC_CLK_SOURCE_RCHF)||\ + ((__VALUE__) == FL_RCC_ADC_CLK_SOURCE_XTHF)||\ + ((__VALUE__) == FL_RCC_ADC_CLK_SOURCE_PLL)) + + +#define IS_FL_ADC_ADCCLK_PRESCALER(__VALUE__) (((__VALUE__) == FL_RCC_ADC_PSC_DIV1)||\ + ((__VALUE__) == FL_RCC_ADC_PSC_DIV2)||\ + ((__VALUE__) == FL_RCC_ADC_PSC_DIV4)||\ + ((__VALUE__) == FL_RCC_ADC_PSC_DIV8)||\ + ((__VALUE__) == FL_RCC_ADC_PSC_DIV16)||\ + ((__VALUE__) == FL_RCC_ADC_PSC_DIV32)) + + +#define IS_FL_ADC_CONTINUOUSCONVMODE(__VALUE__) (((__VALUE__) == FL_ADC_CONV_MODE_SINGLE)||\ + ((__VALUE__) == FL_ADC_CONV_MODE_CONTINUOUS)) + +#define IS_FL_ADC_AUTO_MODE(__VALUE__) (((__VALUE__) == FL_ADC_SINGLE_CONV_MODE_AUTO)||\ + ((__VALUE__) == FL_ADC_SINGLE_CONV_MODE_SEMIAUTO)) + + +#define IS_FL_ADC_SCANDIRECTION(__VALUE__) (((__VALUE__) == FL_ADC_SEQ_SCAN_DIR_FORWARD)||\ + ((__VALUE__) == FL_ADC_SEQ_SCAN_DIR_BACKWARD)) + + +#define IS_FL_ADC_EXTERNALTRIGCONV(__VALUE__) (((__VALUE__) == FL_ADC_TRIGGER_EDGE_NONE)||\ + ((__VALUE__) == FL_ADC_TRIGGER_EDGE_RISING)||\ + ((__VALUE__) == FL_ADC_TRIGGER_EDGE_FALLING)||\ + ((__VALUE__) == FL_ADC_TRIGGER_EDGE_BOTH)) + +#define IS_FL_ADC_EXTERNALTRIGSOURCE(__VALUE__) (((__VALUE__) == FL_ADC_TRGI_PA8)||\ + ((__VALUE__) == FL_ADC_TRGI_PB9)||\ + ((__VALUE__) == FL_ADC_TRGI_ATIM)||\ + ((__VALUE__) == FL_ADC_TRGI_GPTIM0)||\ + ((__VALUE__) == FL_ADC_TRGI_GPTIM1)||\ + ((__VALUE__) == FL_ADC_TRGI_RTC)||\ + ((__VALUE__) == FL_ADC_TRGI_BSTIM1)||\ + ((__VALUE__) == FL_ADC_TRGI_COMP1)||\ + ((__VALUE__) == FL_ADC_TRGI_COMP2)) + +#define IS_FL_ADC_CHANNEL_FAST_TIME(__VALUE__) (((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_4_ADCCLK)||\ + ((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_6_ADCCLK)||\ + ((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_9_ADCCLK)||\ + ((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_10_ADCCLK)||\ + ((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_16_ADCCLK)||\ + ((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_24_ADCCLK)||\ + ((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_32_ADCCLK)||\ + ((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_48_ADCCLK)||\ + ((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_96_ADCCLK)||\ + ((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_128_ADCCLK)||\ + ((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_192_ADCCLK)||\ + ((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_256_ADCCLK)||\ + ((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_384_ADCCLK)||\ + ((__VALUE__) == FL_ADC_FAST_CH_SAMPLING_TIME_SOFTWARE_CONTROL)) + +#define IS_FL_ADC_CHANNEL_SLOW_TIME(__VALUE__) (((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_4_ADCCLK)||\ + ((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_6_ADCCLK)||\ + ((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_9_ADCCLK)||\ + ((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_10_ADCCLK)||\ + ((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_16_ADCCLK)||\ + ((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_24_ADCCLK)||\ + ((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_32_ADCCLK)||\ + ((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_48_ADCCLK)||\ + ((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_96_ADCCLK)||\ + ((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_128_ADCCLK)||\ + ((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_192_ADCCLK)||\ + ((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_256_ADCCLK)||\ + ((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_384_ADCCLK)||\ + ((__VALUE__) == FL_ADC_SLOW_CH_SAMPLING_TIME_SOFTWARE_CONTROL)) + +#define IS_FL_ADC_OVERSAMPCOFIG(__VALUE__) (((__VALUE__) == FL_DISABLE)||\ + ((__VALUE__) == FL_ENABLE)) + +#define IS_FL_ADC_OVERSAMPINGRATIO(__VALUE__) (((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_2X)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_4X)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_8X)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_16X)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_32X)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_64X)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_128X)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_MUL_256X)) + +#define IS_FL_ADC_OVERSAMPINGSHIFT(__VALUE__) (((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_0B)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_1B)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_2B)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_3B)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_4B)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_5B)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_6B)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_7B)||\ + ((__VALUE__) == FL_ADC_OVERSAMPLING_SHIFT_8B)) + +#define ADC_CALIBRATIN_TIME_OUT (500000) +/** + * @} + */ + +/** @addtogroup ADC_FL_EF_Init + * @{ + */ + +/** + * @brief ADC外设寄存器值为复位值 + * @param 外设入口地址 + * @retval 返回错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_ADC_CommonDeInit(void) +{ + /* 关闭总线时钟 */ + FL_RCC_DisableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_ADC); + /* 关闭操作时钟 */ + FL_RCC_DisableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_ADC); + return FL_PASS; +} +/** + * @brief ADC共用寄存器设置以配置外设工作时钟 + * + * @note 其中LL_LPTIM_OPERATION_MODE_EXTERNAL_ASYN_PAUSE_CNT 模式需要外部脉冲提供给LPTIM模块作为工作时钟，此时 + * LPTIM完全工作在异步模式下。 + * @param LPTIM 外设入口地址 + * @param LPTIM_InitStruct指向LL_LPTIM_TimeInitTypeDef类的结构体，它包含指定LPTIM外设的配置信息 + * + * @retval ErrorStatus枚举值 + * -FL_FAIL 配置过程发生错误 + * -FL_PASS LPUART配置成功 + */ +FL_ErrorStatus FL_ADC_CommonInit(FL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +{ + FL_ErrorStatus status = FL_PASS; + /* 入口参数检查 */ + assert_param(IS_FL_ADC_ADCCLK_PRESCALER(ADC_CommonInitStruct->clockPrescaler)); + assert_param(IS_FL_ADC_ADCCLK_SOURCE(ADC_CommonInitStruct->clockSource)); + /* 开启总线时钟 */ + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_ADC); + /* 开启操作时钟 */ + FL_RCC_EnableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_ADC); + /* 配置ADCCLOCK时钟预分频 */ + FL_RCC_SetADCPrescaler(ADC_CommonInitStruct->clockPrescaler); + /* 配置ADCCLOCK时钟模块时钟源 */ + FL_RCC_SetADCClockSource(ADC_CommonInitStruct->clockSource); + return status; +} +/** + * @brief 设置 ADC_CommonInitStruct 为默认配置 + * @param ADC_CommonInitStruct 指向需要将值设置为默认配置的结构体 @ref LL_ADC_CommonInitTypeDef 结构体 + * + * @retval None + */ +void FL_ADC_CommonStructInit(FL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +{ + /*默认使用RCHF作为ADC时钟模块时钟源，预分频系数16*/ + ADC_CommonInitStruct->clockSource = FL_RCC_ADC_CLK_SOURCE_RCHF; + ADC_CommonInitStruct->clockPrescaler = FL_RCC_ADC_PSC_DIV16; +} +/** + * @brief 恢复对应的ADC入口地址寄存器为默认值 + * + * @param ADCx 外设入口地址 + * + * @retval ErrorStatus枚举值 + * -FL_FAIL 配置过程发生错误 + * -FL_PASS LPUART配置成功 + */ +FL_ErrorStatus FL_ADC_DeInit(ADC_Type *ADCx) +{ + FL_ErrorStatus status = FL_PASS; + /* 入口合法性检查 */ + assert_param(IS_FL_ADC_INSTANCE(ADCx)); + /* 外设复位使能 */ + FL_RCC_EnablePeripheralReset(); + FL_RCC_EnableResetAPB2Peripheral(FL_RCC_RSTAPB_ADC); + FL_RCC_DisableResetAPB2Peripheral(FL_RCC_RSTAPB_ADC); + FL_RCC_EnableResetAPB2Peripheral(FL_RCC_RSTAPB_ADCCR); + FL_RCC_DisableResetAPB2Peripheral(FL_RCC_RSTAPB_ADCCR); + FL_RCC_DisablePeripheralReset(); + return status; +} +/** + * @brief 初始化ADCx指定的入口地址的外设寄存器 + * + * @note 用户必须检查此函数的返回值，以确保自校准完成，否则转换结果精度无法保证，除此之外ADC使能过采样实际不会增加ADC的 + * 转换精度只会提高转换结果的稳定性（同时配置移位寄存器的情况下），同时过采样会降低转换速度。 + * @param ADCx 外设入口地址 + * @param ADC_InitStruct 向一FL_ADC_InitTypeDef结构体，它包含指定ADC外设的配置信息 + * + * @retval ErrorStatus枚举值 + * -FL_FAIL 配置过程发生错误 + * -FL_PASS LPUART配置成功 + */ +FL_ErrorStatus FL_ADC_Init(ADC_Type *ADCx, FL_ADC_InitTypeDef *ADC_InitStruct) +{ + FL_ErrorStatus status = FL_PASS; + uint32_t i = 0; + /* 入口合法性检查 */ + assert_param(IS_FL_ADC_INSTANCE(ADCx)); + assert_param(IS_FL_ADC_CONTINUOUSCONVMODE(ADC_InitStruct->conversionMode)); + assert_param(IS_FL_ADC_AUTO_MODE(ADC_InitStruct->autoMode)); + assert_param(IS_FL_ADC_SCANDIRECTION(ADC_InitStruct->scanDirection)); + assert_param(IS_FL_ADC_EXTERNALTRIGCONV(ADC_InitStruct->externalTrigConv)); + assert_param(IS_FL_ADC_OVERSAMPCOFIG(ADC_InitStruct->oversamplingMode)); + assert_param(IS_FL_ADC_OVERSAMPINGRATIO(ADC_InitStruct->overSampingMultiplier)); + assert_param(IS_FL_ADC_OVERSAMPINGSHIFT(ADC_InitStruct->oversamplingShift)); + /* 使能a工作时钟 */ + FL_RCC_EnableGroup1BusClock(FL_RCC_GROUP1_BUSCLK_ANAC); + FL_SVD_EnableADCMonitor(SVD); + if(!FL_VREF_IsEnabled(VREF)) + { + FL_VREF_ClearFlag_Ready(VREF); + FL_VREF_Enable(VREF);//置位VREF_EN寄存器，使能VREF1p2模块 + } + FL_VREF_EnableTemperatureSensor(VREF);//置位PTAT_EN寄存器 + while(FL_VREF_IsActiveFlag_Ready(VREF) == 0) + { + if(i >= 128000) + { + break; + } + i++; + } + FL_ADC_Disable(ADCx); + if(FL_ADC_IsEnabled(ADCx) == 0U) + { + /* 连续转换模式 */ + FL_ADC_SetConversionMode(ADCx, ADC_InitStruct->conversionMode); + /* 自动转换模式 */ + FL_ADC_SetSingleConversionAutoMode(ADCx, ADC_InitStruct->autoMode); + /* 通道等待使能 */ + if(ADC_InitStruct->waitMode) + { + FL_ADC_EnableWaitMode(ADCx); + } + else + { + FL_ADC_DisableWaitMode(ADCx); + } + /*数据冲突模式设置*/ + if(ADC_InitStruct->overrunMode) + { + FL_ADC_EnableOverrunMode(ADCx); + } + else + { + FL_ADC_DisableOverrunMode(ADCx); + } + /* 多通道扫描方向 */ + FL_ADC_SetSequenceScanDirection(ADCx, ADC_InitStruct->scanDirection); + /* 采样控制模式*/ + FL_ADC_SetSamplingTimeControlMode(ADCx, FL_ADC_SAMPLING_TIME_CONTROL_BY_REG); + FL_ADC_SetSamplingStartControlMode(ADCx, FL_ADC_SAMPLING_START_CONTROL_BY_REG); + /* 触发模式 */ + FL_ADC_SetTriggerEdge(ADCx, ADC_InitStruct->externalTrigConv); + /* 触发源 */ + FL_ADC_SetTriggerSource(ADCx, ADC_InitStruct->triggerSource); + /*通道采样时间设置*/ + FL_ADC_SetSamplingInterval(ADCx, FL_ADC_SAMPLING_INTERVAL_11_CYCLE); + FL_ADC_SetFastChannelSamplingTime(ADCx, ADC_InitStruct->fastChannelTime); + FL_ADC_SetSlowChannelSamplingTime(ADCx, ADC_InitStruct->lowChannelTime); + if(ADC_InitStruct->oversamplingMode) + { + /*使能过采样倍数后，需要配置移位寄存器进行移位，这一过程是硬件自动完成的最终最大 + 可输出16位的结果值（即256被采样得到的结果是20bit的，右移4bit结果就是16bit的）*/ + FL_ADC_SetOverSamplingMultiplier(ADCx, ADC_InitStruct->overSampingMultiplier); + FL_ADC_SetOverSamplingShift(ADCx, ADC_InitStruct->oversamplingShift); + /* 过采样使能 */ + FL_ADC_EnableOverSampling(ADCx); + } + else + { + /* 关闭过采样 */ + FL_ADC_DisableOverSampling(ADCx); + } + } + else + { + status = FL_FAIL; + } + return status; +} + +/** + * @brief 设置 ADC_InitStruct 为默认配置 + * @param ADC_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_ADC_InitTypeDef 结构体 + * + * @retval None + */ +void FL_ADC_StructInit(FL_ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->conversionMode = FL_ADC_CONV_MODE_SINGLE; + ADC_InitStruct->autoMode = FL_ADC_SINGLE_CONV_MODE_AUTO; + ADC_InitStruct->scanDirection = FL_ADC_SEQ_SCAN_DIR_FORWARD; + ADC_InitStruct->externalTrigConv = FL_ADC_TRIGGER_EDGE_NONE; + ADC_InitStruct->overrunMode = FL_ENABLE; + ADC_InitStruct->waitMode = FL_ENABLE; + ADC_InitStruct->fastChannelTime = FL_ADC_FAST_CH_SAMPLING_TIME_4_ADCCLK; + ADC_InitStruct->lowChannelTime = FL_ADC_SLOW_CH_SAMPLING_TIME_192_ADCCLK; + ADC_InitStruct->oversamplingMode = FL_ENABLE; + ADC_InitStruct->overSampingMultiplier = FL_ADC_OVERSAMPLING_MUL_16X; + ADC_InitStruct->oversamplingShift = FL_ADC_OVERSAMPLING_SHIFT_4B; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ + + + diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_aes.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_aes.c new file mode 100644 index 0000000000..1c9adbc857 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_aes.c @@ -0,0 +1,152 @@ +/** + **************************************************************************************************** + * @file fm33lc0xx_fl_aes.c + * @author FMSH Application Team + * @brief Src file of AES FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_aes.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup AES + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup AES_FL_Private_Macros + * @{ + */ + +#define IS_FL_AES_INSTANCE(INSTANCE) (((INSTANCE) == AES)) + +#define IS_FL_AES_KEYLENGTH(__VALUE__) (((__VALUE__) == FL_AES_KEY_LENGTH_128B)||\ + ((__VALUE__) == FL_AES_KEY_LENGTH_192B)||\ + ((__VALUE__) == FL_AES_KEY_LENGTH_256B)) + +#define IS_FL_AES_CIPHERMODE(__VALUE__) (((__VALUE__) == FL_AES_CIPHER_ECB)||\ + ((__VALUE__) == FL_AES_CIPHER_CBC)||\ + ((__VALUE__) == FL_AES_CIPHER_CTR)||\ + ((__VALUE__) == FL_AES_CIPHER_MULTH)) + +#define IS_FL_AES_OPERATIONMODE(__VALUE__) (((__VALUE__) == FL_AES_OPERATION_MODE_ENCRYPTION)||\ + ((__VALUE__) == FL_AES_OPERATION_MODE_KEYDERIVATION)||\ + ((__VALUE__) == FL_AES_OPERATION_MODE_DECRYPTION)||\ + ((__VALUE__) == FL_AES_OPERATION_MODE_KEYDERIVATION_DECRYPTION)) + +#define IS_FL_AES_DATATYPE(__VALUE__) (((__VALUE__) == FL_AES_DATA_TYPE_32B)||\ + ((__VALUE__) == FL_AES_DATA_TYPE_16B)||\ + ((__VALUE__) == FL_AES_DATA_TYPE_8B)||\ + ((__VALUE__) == FL_AES_DATA_TYPE_1B)) +/** + * @} + */ + +/** @addtogroup AES_FL_EF_Init + * @{ + */ + +/** + * @brief 复位AES外设 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_AES_DeInit(void) +{ + /* 外设复位使能 */ + FL_RCC_EnablePeripheralReset(); + /* 复位AES */ + FL_RCC_EnableResetAPB2Peripheral(FL_RCC_RSTAPB_AES); + FL_RCC_DisableResetAPB2Peripheral(FL_RCC_RSTAPB_AES); + /* 关闭总线时钟 */ + FL_RCC_DisableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_AES); + /* 锁定外设复位功能 */ + FL_RCC_DisablePeripheralReset(); + return FL_PASS; +} + +/** + * @brief 根据 AES_InitStructer 初始化对应外设入口地址的寄存器值. + * + * @param AESx 外设入口地址 + * @param AES_InitStructer 指向 @ref FL_AES_InitTypeDef 结构体的指针 + * + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_AES_Init(AES_Type *AESx, FL_AES_InitTypeDef *AES_InitStructer) +{ + /* 入口合法性检查 */ + assert_param(IS_FL_AES_INSTANCE(AESx)); + assert_param(IS_FL_AES_KEYLENGTH(AES_InitStructer->keyLength)); + assert_param(IS_FL_AES_CIPHERMODE(AES_InitStructer->cipherMode)); + assert_param(IS_FL_AES_OPERATIONMODE(AES_InitStructer->operationMode)); + assert_param(IS_FL_AES_DATATYPE(AES_InitStructer->dataType)); + FL_AES_Disable(AES); + if(FL_AES_IsEnabled(AESx) == 0) + { + /* 开启总线时钟 */ + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_AES); + /* key长度 */ + FL_AES_SetKeySize(AESx, AES_InitStructer->keyLength); + /* 数据流处理模式 */ + FL_AES_SetCipherMode(AESx, AES_InitStructer->cipherMode); + /* 操作模式 */ + FL_AES_SetOperationMode(AESx, AES_InitStructer->operationMode); + /* 数据类型 */ + FL_AES_SetDataType(AESx, AES_InitStructer->dataType); + } + else + { + return FL_FAIL; + } + return FL_PASS; +} + +/** + * @brief 将 @ref FL_AES_InitTypeDef 结构体初始化为默认配置 + * @param AES_InitStructer 指向 @ref FL_AES_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_AES_StructInit(FL_AES_InitTypeDef *AES_InitStructer) +{ + AES_InitStructer->keyLength = FL_AES_KEY_LENGTH_128B; + AES_InitStructer->cipherMode = FL_AES_CIPHER_ECB; + AES_InitStructer->operationMode = FL_AES_OPERATION_MODE_ENCRYPTION; + AES_InitStructer->dataType = FL_AES_DATA_TYPE_32B; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ + diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_atim.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_atim.c new file mode 100644 index 0000000000..d4b28258f4 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_atim.c @@ -0,0 +1,777 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_atim.c + * @author FMSH Application Team + * @brief Src file of ATIM FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_rmu.h" +#include "fm33lc0xx_fl_atim.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup ATIM + * @{ + */ + +/* Private macros ------------------------------------------------------------------*/ +/** @addtogroup ATIM_FL_Private_Macros + * @{ + */ + + +#define IS_ATIM_INSTANCE(TIMx) ((TIMx) == ATIM) + +#define IS_ATIM_CLKSRC(__VALUE__) (((__VALUE__) == FL_RCC_ATIM_CLK_SOURCE_APB2CLK ) \ + || ((__VALUE__) == FL_RCC_ATIM_CLK_SOURCE_PLLx2))\ + || ((__VALUE__) == FL_RCC_ATIM_CLK_SOURCE_USBPHYBCK120M) + + +#define IS_FL_ATIM_COUNTERMODE(__VALUE__) (((__VALUE__) == FL_ATIM_COUNTER_DIR_UP) \ + || ((__VALUE__) == FL_ATIM_COUNTER_DIR_DOWN) \ + || ((__VALUE__) == FL_ATIM_COUNTER_ALIGNED_CENTER_DOWN ) \ + || ((__VALUE__) == FL_ATIM_COUNTER_ALIGNED_CENTER_UP ) \ + || ((__VALUE__) == FL_ATIM_COUNTER_ALIGNED_CENTER_UP_DOWN)) + +#define IS_FL_ATIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == FL_ATIM_CLK_DIVISION_DIV1) \ + || ((__VALUE__) == FL_ATIM_CLK_DIVISION_DIV2) \ + || ((__VALUE__) == FL_ATIM_CLK_DIVISION_DIV4)) + + +#define IS_FL_ATIM_CC_MODE(__VALUE__) (((__VALUE__) == FL_ATIM_CHANNEL_MODE_OUTPUT) \ + || ((__VALUE__) == FL_ATIM_CHANNEL_MODE_INPUT_NORMAL) \ + || ((__VALUE__) == FL_ATIM_CHANNEL_MODE_INPUT_CROSSOVER) \ + || ((__VALUE__) == FL_ATIM_CHANNEL_MODE_INPUT_TRC)) + +#define IS_FL_ATIM_IC_FILTER(__VALUE__) (((__VALUE__) == FL_ATIM_IC_FILTER_DIV1 ) \ + || ((__VALUE__) ==FL_ATIM_IC_FILTER_DIV1_N2) \ + || ((__VALUE__) == FL_ATIM_IC_FILTER_DIV1_N4) \ + || ((__VALUE__) == FL_ATIM_IC_FILTER_DIV1_N8) \ + || ((__VALUE__) == FL_ATIM_IC_FILTER_DIV2_N6) \ + || ((__VALUE__) == FL_ATIM_IC_FILTER_DIV2_N8) \ + || ((__VALUE__) == FL_ATIM_IC_FILTER_DIV4_N6) \ + || ((__VALUE__) == FL_ATIM_IC_FILTER_DIV4_N8) \ + || ((__VALUE__) == FL_ATIM_IC_FILTER_DIV8_N6) \ + || ((__VALUE__) == FL_ATIM_IC_FILTER_DIV8_N8) \ + || ((__VALUE__) == FL_ATIM_IC_FILTER_DIV16_N5) \ + || ((__VALUE__) == FL_ATIM_IC_FILTER_DIV16_N6) \ + || ((__VALUE__) == FL_ATIM_IC_FILTER_DIV16_N8) \ + || ((__VALUE__) == FL_ATIM_IC_FILTER_DIV32_N5) \ + || ((__VALUE__) == FL_ATIM_IC_FILTER_DIV32_N6) \ + || ((__VALUE__) == FL_ATIM_IC_FILTER_DIV32_N8)) + +#define IS_FL_ATIM_CHANNEL(__VALUE__) (((__VALUE__) == FL_ATIM_CHANNEL_1)\ + || ((__VALUE__) == FL_ATIM_CHANNEL_2)\ + || ((__VALUE__) == FL_ATIM_CHANNEL_3)\ + || ((__VALUE__) == FL_ATIM_CHANNEL_4)) + + + +#define IS_FL_ATIM_SLAVE_MODE(__VALUE__) (((__VALUE__) == FL_ATIM_SLAVE_MODE_PROHIBITED)\ + || ((__VALUE__) == FL_ATIM_SLAVE_MODE_ENCODER_X2_TI1)\ + || ((__VALUE__) == FL_ATIM_SLAVE_MODE_ENCODER_X2_TI2)\ + || ((__VALUE__) == FL_ATIM_SLAVE_MODE_ENCODER_X4_TI1TI2)\ + || ((__VALUE__) == FL_ATIM_SLAVE_MODE_TRGI_RISE_RST)\ + || ((__VALUE__) == FL_ATIM_SLAVE_MODE_TRGI_HIGH_RUN)\ + || ((__VALUE__) == FL_ATIM_SLAVE_MODE_TRGI_RISE_RUN)\ + || ((__VALUE__) == FL_ATIM_SLAVE_MODE_TRGI_CLK)) + + +#define IS_FL_ATIM_TRIGGER_SRC(__VALUE__) (((__VALUE__) == FL_ATIM_TRGI_ITR0 )\ + ||((__VALUE__) ==FL_ATIM_TRGI_ITR1 )\ + ||((__VALUE__) ==FL_ATIM_TRGI_ITR2)\ + ||((__VALUE__) ==FL_ATIM_TRGI_ITR3)\ + ||((__VALUE__) ==FL_ATIM_TRGI_TI1F_EDGE)\ + ||((__VALUE__) ==FL_ATIM_TRGI_TI1FP1)\ + ||((__VALUE__) ==FL_ATIM_TRGI_TI2FP2)\ + ||((__VALUE__) ==FL_ATIM_TRGI_ETRF)) + + + +#define IS_FL_ATIM_ETP_FILTER(__VALUE__) (((__VALUE__) == FL_ATIM_ETR_FILTER_DIV1) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV1_N2) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV1_N4) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV1_N8) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV2_N6) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV2_N8) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV4_N6) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV4_N8) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV8_N6) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV8_N8) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV16_N5) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV16_N6) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV16_N8) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV32_N5) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV32_N6) \ + || ((__VALUE__) == FL_ATIM_ETR_FILTER_DIV32_N8)) + + +#define IS_FL_ATIM_ETR_PSC(__VALUE__) (((__VALUE__) == FL_ATIM_ETR_PSC_DIV1) \ + || ((__VALUE__) == FL_ATIM_ETR_PSC_DIV2) \ + || ((__VALUE__) == FL_ATIM_ETR_PSC_DIV4) \ + || ((__VALUE__) == FL_ATIM_ETR_PSC_DIV8)) + + + +#define IS_FL_ATIM_ETR_POLARITY(__VALUE__) (((__VALUE__) == FL_ATIM_ETR_POLARITY_NORMAL) \ + || ((__VALUE__) == FL_ATIM_ETR_POLARITY_INVERT)) + + + +#define IS_FL_ATIM_IC_POLARITY(__VALUE__) (((__VALUE__) == FL_ATIM_IC_POLARITY_NORMAL) \ + || ((__VALUE__) == FL_ATIM_IC_POLARITY_INVERT)) + + + +#define IS_FL_ATIM_IC_ACTIVEINPUT(__VALUE__) (((__VALUE__) == FL_ATIM_CHANNEL_MODE_INPUT_NORMAL) \ + || ((__VALUE__) == FL_ATIM_CHANNEL_MODE_INPUT_CROSSOVER) \ + || ((__VALUE__) == FL_ATIM_CHANNEL_MODE_INPUT_TRC)) + + +#define IS_FL_ATIM_IC_PRESCALER(__VALUE__) (((__VALUE__) == FL_ATIM_IC_PSC_DIV1) \ + || ((__VALUE__) == FL_ATIM_IC_PSC_DIV2) \ + || ((__VALUE__) == FL_ATIM_IC_PSC_DIV4) \ + || ((__VALUE__) == FL_ATIM_IC_PSC_DIV8)) + + + +#define IS_FL_ATIM_OC_POLARITY(__VALUE__) (((__VALUE__) == FL_ATIM_OC_POLARITY_NORMAL) \ + || ((__VALUE__) == FL_ATIM_OC_POLARITY_INVERT)) + + + +#define IS_FL_ATIM_OC_MODE(__VALUE__) (((__VALUE__) == FL_ATIM_OC_MODE_FROZEN) \ + || ((__VALUE__) == FL_ATIM_OC_MODE_ACTIVE) \ + || ((__VALUE__) == FL_ATIM_OC_MODE_INACTIVE) \ + || ((__VALUE__) == FL_ATIM_OC_MODE_TOGGLE) \ + || ((__VALUE__) == FL_ATIM_OC_MODE_FORCED_INACTIVE) \ + || ((__VALUE__) == FL_ATIM_OC_MODE_FORCED_ACTIVE) \ + || ((__VALUE__) == FL_ATIM_OC_MODE_PWM1) \ + || ((__VALUE__) == FL_ATIM_OC_MODE_PWM2)) + +#define IS_FL_ATIM_AUTORELOAB_STATE(__VALUE__) (((__VALUE__) == FL_ENABLE) \ + || ((__VALUE__) == FL_DISABLE)) + +#define IS_FL_ATIM_OC_FASTMODE(__VALUE__) (((__VALUE__) == FL_ENABLE) \ + || ((__VALUE__) == FL_DISABLE)) + +#define IS_FL_ATIM_OC_PRELOAD(__VALUE__) (((__VALUE__) == FL_ENABLE) \ + || ((__VALUE__) == FL_DISABLE)) + +#define IS_FL_ATIM_OC_ETR_CLEARN(__VALUE__) (((__VALUE__) == FL_ENABLE) \ + || ((__VALUE__) == FL_DISABLE)) + +#define IS_FL_ATIM_OC_STATE(__VALUE__) (((__VALUE__) == FL_ENABLE)\ + || ((__VALUE__) == FL_DISABLE)) + +#define IS_FL_ATIM_OCN_STATE(__VALUE__) (((__VALUE__) == FL_ENABLE)\ + || ((__VALUE__) == FL_DISABLE)) + +#define IS_FL_ATIM_OC_IDLESTATE(__VALUE__) (((__VALUE__) == FL_ATIM_OC_IDLE_STATE_LOW) \ + || ((__VALUE__) == FL_ATIM_OC_IDLE_STATE_HIGH)) + +#define IS_FL_ATIM_OC_NIDLESTATE(__VALUE__) (((__VALUE__) == FL_ATIM_OCN_IDLE_STATE_LOW) \ + || ((__VALUE__) == FL_ATIM_OCN_IDLE_STATE_HIGH)) + + +#define IS_FL_ATIM_OC_NPOLARITY(__VALUE__) (((__VALUE__) == FL_ATIM_OCN_POLARITY_NORMAL) \ + || ((__VALUE__) == FL_ATIM_OCN_POLARITY_INVERT)) + + + +#define IS_FL_ATIM_BDTR_FILTER(__VALUE__) (((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV1) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV1_N2) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV1_N4) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV1_N8) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV2_N6) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV2_N8) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV4_N6) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV4_N8) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV8_N6) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV8_N8) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV16_N5) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV16_N6) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV16_N8) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV32_N5) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV32_N6) \ + || ((__VALUE__) == FL_ATIM_BREAK_FILTER_DIV32_N8)) + +#define IS_FL_ATIM_OSSR_STATE(__VALUE__) (((__VALUE__) == FL_ATIM_OSSR_DISABLE) \ + || ((__VALUE__) == FL_ATIM_OSSR_ENABLE)) + +#define IS_FL_ATIM_OSSI_STATE(__VALUE__) (((__VALUE__) == FL_ATIM_OSSI_DISABLE) \ + || ((__VALUE__) == FL_ATIM_OSSI_ENABLE)) + +#define IS_FL_ATIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == FL_ATIM_LOCK_LEVEL_OFF) \ + || ((__VALUE__) == FL_ATIM_LOCK_LEVEL_1) \ + || ((__VALUE__) == FL_ATIM_LOCK_LEVEL_2) \ + || ((__VALUE__) == FL_ATIM_LOCK_LEVEL_3)) + +#define IS_FL_ATIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == FL_ATIM_BREAK_POLARITY_LOW) \ + || ((__VALUE__) == FL_ATIM_BREAK_POLARITY_HIGH)) + +#define IS_FL_ATIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == FL_DISABLE) \ + || ((__VALUE__) == FL_ENABLE)) + +#define IS_FL_ATIM_TRIGGER_DELAY(__VALUE__) (((__VALUE__) == FL_DISABLE) \ + || ((__VALUE__) == FL_ENABLE)) + +#define IS_FL_ATIM_IC_CAPTURE_STATE(__VALUE__) (((__VALUE__) == FL_DISABLE) \ + || ((__VALUE__) == FL_ENABLE)) + +/** + * @} + */ + +/* Private functions -----------------------------------------------*/ +/** @defgroup ATIM_FL_PF ATIM Private Functions + * @{ + */ + +/** + * @brief ATIM配置输出通道 + * @param TIMx 外设入口地址 + * @param channel ATIM通道 + * 此参数可取以下值： + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @param TIM_OC_InitStruct 指向 @ref FL_ATIM_OC_InitTypeDef 结构体指针. + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +static FL_ErrorStatus OCConfig(ATIM_Type *TIMx, uint32_t channel, FL_ATIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + FL_ErrorStatus result = FL_PASS; + /* 配置比较输出通道模式 */ + FL_ATIM_OC_SetMode(TIMx, TIM_OC_InitStruct->OCMode, channel); + /* 配置TRF清零使能 */ + if(TIM_OC_InitStruct->OCETRFStatus == FL_ENABLE) + { + FL_ATIM_OC_EnableClear(TIMx, channel); + } + else + { + FL_ATIM_OC_DisableClear(TIMx, channel); + } + /* 比较输出通道快速模式 */ + if(TIM_OC_InitStruct->OCFastMode == FL_ENABLE) + { + FL_ATIM_OC_EnableFastMode(TIMx, channel); + } + else + { + FL_ATIM_OC_DisableFastMode(TIMx, channel); + } + /* 比较输出通道缓冲模式 */ + if(TIM_OC_InitStruct->OCPreload == FL_ENABLE) + { + FL_ATIM_OC_EnablePreload(TIMx, channel); + } + else + { + FL_ATIM_OC_DisablePreload(TIMx, channel); + } + if(TIM_OC_InitStruct->OCNState == FL_ENABLE) + { + /* 互补通道使能 */ + FL_ATIM_OC_EnableReverseChannel(TIMx, channel); + } + else + { + FL_ATIM_OC_DisableReverseChannel(TIMx, channel); + } + if(TIM_OC_InitStruct->OCState == FL_ENABLE) + { + /* 通道使能 */ + FL_ATIM_OC_EnableChannel(TIMx, channel); + } + else + { + FL_ATIM_OC_DisableChannel(TIMx, channel); + } + /* 设置比较值 */ + switch(channel) + { + case FL_ATIM_CHANNEL_1: + FL_ATIM_WriteCompareCH1(TIMx, TIM_OC_InitStruct->compareValue); + break; + case FL_ATIM_CHANNEL_2: + FL_ATIM_WriteCompareCH2(TIMx, TIM_OC_InitStruct->compareValue); + break; + case FL_ATIM_CHANNEL_3: + FL_ATIM_WriteCompareCH3(TIMx, TIM_OC_InitStruct->compareValue); + break; + case FL_ATIM_CHANNEL_4: + FL_ATIM_WriteCompareCH4(TIMx, TIM_OC_InitStruct->compareValue); + break; + default : + result = FL_FAIL; + break; + } + return result; +} + +/** + * @} + */ + +/* Exported functions -----------------------------------------------*/ +/** @addtogroup ATIM_FL_EF_Init + * @{ + */ + +/** + * @brief 复位ATIM外设 + * @param TIMx 外设入口地址 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_ATIM_DeInit(ATIM_Type *TIMx) +{ + FL_ErrorStatus result = FL_PASS; + /* Check the parameters */ + assert_param(IS_ATIM_INSTANCE(TIMx)); + /* 使能外设复位 */ + FL_RCC_EnablePeripheralReset(); + /* 复位ATIM外设寄存器 */ + FL_RCC_EnableResetAPB2Peripheral(FL_RCC_RSTAPB_ATIM); + FL_RCC_DisableResetAPB2Peripheral(FL_RCC_RSTAPB_ATIM); + /* 关闭外设总线始时钟和工作时钟 */ + FL_RCC_DisableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_ATIM); + FL_RCC_DisableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_ATIM); + /* 锁定外设复位 */ + FL_RCC_DisablePeripheralReset(); + return result; +} + +/** + * @brief 配置基本定时器时基单元（内部时钟源） + * @param TIMx 外设入口地址 + * @param TIM_InitStruct 指向 @ref FL_ATIM_InitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_ATIM_Init(ATIM_Type *TIMx, FL_ATIM_InitTypeDef *TIM_InitStruct) +{ + uint32_t i = 5; + /* 参数检查 */ + assert_param(IS_ATIM_INSTANCE(TIMx)); + assert_param(IS_FL_ATIM_COUNTERMODE(TIM_InitStruct->counterMode)); + assert_param(IS_FL_ATIM_CLOCKDIVISION(TIM_InitStruct->clockDivision)); + assert_param(IS_FL_ATIM_AUTORELOAB_STATE(TIM_InitStruct->autoReloadState)); + assert_param(IS_ATIM_CLKSRC(TIM_InitStruct->clockSource)); + /* 时钟总线使能配置 */ + FL_RCC_SetATIMClockSource(TIM_InitStruct->clockSource); + FL_RCC_EnableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_ATIM); + FL_RCC_EnableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_ATIM); + /* 设置重复计数值 */ + FL_ATIM_WriteRepetitionCounter(TIMx, TIM_InitStruct->repetitionCounter); + /* 计数器计数模式配置 */ + switch(TIM_InitStruct->counterMode) + { + /* 中心对称模式 */ + case FL_ATIM_COUNTER_ALIGNED_CENTER_DOWN : + case FL_ATIM_COUNTER_ALIGNED_CENTER_UP : + case FL_ATIM_COUNTER_ALIGNED_CENTER_UP_DOWN: + FL_ATIM_SetCounterAlignedMode(TIMx, TIM_InitStruct->counterMode); + break; + default: + /* 边沿模式 */ + FL_ATIM_SetCounterDirection(TIMx, TIM_InitStruct->counterMode); + FL_ATIM_SetCounterAlignedMode(TIMx, FL_ATIM_COUNTER_ALIGNED_EDGE); + break; + } + /* 自动重装载值 */ + FL_ATIM_WriteAutoReload(TIMx, TIM_InitStruct->autoReload); + /* 定时器分频系数与数字滤波器所使用的采样时钟分频比 */ + FL_ATIM_SetClockDivision(TIMx, TIM_InitStruct->clockDivision); + /* 时钟分频 */ + FL_ATIM_WritePrescaler(TIMx, TIM_InitStruct->prescaler); + /* 预装载配置 */ + if(TIM_InitStruct->autoReloadState == FL_ENABLE) + { + FL_ATIM_EnableARRPreload(TIMx); + } + else + { + FL_ATIM_DisableARRPreload(TIMx); + } + /* 手动触发更新事件，将配置值写入 */ + FL_ATIM_GenerateUpdateEvent(TIMx); + while((!FL_ATIM_IsActiveFlag_Update(ATIM))&i) + { + i--; + } + /*清除UIF标志，防止产生UG事件中断*/ + FL_ATIM_ClearFlag_Update(ATIM); + return FL_PASS; +} + + +/** + * @brief 将 @ref FL_ATIM_InitTypeDef 结构体初始化为默认配置 + * @param TIM_InitStruct 指向 @ref FL_ATIM_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_ATIM_StructInit(FL_ATIM_InitTypeDef *TIM_InitStruct) +{ + /* Set the default configuration */ + TIM_InitStruct->clockSource = FL_RCC_ATIM_CLK_SOURCE_APB2CLK; + TIM_InitStruct->prescaler = (uint16_t)0x0000; + TIM_InitStruct->counterMode = FL_ATIM_COUNTER_DIR_UP; + TIM_InitStruct->autoReload = 0xFFFFU; + TIM_InitStruct->clockDivision = FL_ATIM_CLK_DIVISION_DIV1; + TIM_InitStruct->repetitionCounter = 0; + TIM_InitStruct->autoReloadState = FL_DISABLE; +} + +/** + * @brief 配置基本定时器从模式，包括编码器模式 + * @param TIMx 外设入口地址 + * @param TIM_InitStruct 指向 @ref FL_ATIM_SlaveInitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_ATIM_SlaveMode_Init(ATIM_Type *TIMx, FL_ATIM_SlaveInitTypeDef *TIM_InitStruct) +{ + /* 参数检查 */ + assert_param(IS_ATIM_INSTANCE(TIMx)); + assert_param(IS_FL_ATIM_TRIGGER_DELAY(TIM_InitStruct->triggerDelay)); + assert_param(IS_FL_ATIM_TRIGGER_SRC(TIM_InitStruct->triggerSrc)); + assert_param(IS_FL_ATIM_SLAVE_MODE(TIM_InitStruct->slaveMode)); + /* 时钟总线使能配置 */ + FL_RCC_EnableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_ATIM); + FL_RCC_EnableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_ATIM); + /* 触发延迟默认关闭 */ + FL_ATIM_DisableMasterSlaveMode(TIMx); + /* 关闭从模式以能写入TS */ + FL_ATIM_SetSlaveMode(TIMx, 0); + /* 从模式输入源选择 */ + FL_ATIM_SetTriggerInput(TIMx, TIM_InitStruct->triggerSrc); + /* 从模式选择 */ + FL_ATIM_SetSlaveMode(TIMx, TIM_InitStruct->slaveMode); + /* 触发延迟默认关闭 */ + if(TIM_InitStruct->triggerDelay == FL_ENABLE) + { + FL_ATIM_EnableMasterSlaveMode(TIMx); + } + return FL_PASS; +} + +/** + * @brief 将 @ref FL_ATIM_SlaveInitTypeDef 结构体初始化为默认配置 + * @param TIM_InitStruct 指向 @ref FL_ATIM_SlaveInitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_ATIM_SlaveModeStructInit(FL_ATIM_SlaveInitTypeDef *TIM_InitStruct) +{ + TIM_InitStruct->slaveMode = FL_ATIM_SLAVE_MODE_PROHIBITED; + TIM_InitStruct->triggerSrc = FL_ATIM_TRGI_TI1FP1; + TIM_InitStruct->triggerDelay = FL_DISABLE; +} + +/** + * @brief 配置ATIM的输入捕获通道 + * @param TIMx 外设入口地址 + * @param channel ATIM通道 + * 此参数可取以下值： + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @param TIM_IC_InitStruct 指向 @ref FL_ATIM_IC_InitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_ATIM_IC_Init(ATIM_Type *TIMx, uint32_t channel, FL_ATIM_IC_InitTypeDef *IC_InitStruct) +{ + /* 参数检查 */ + assert_param(IS_FL_ATIM_CHANNEL(channel)); + assert_param(IS_FL_ATIM_IC_CAPTURE_STATE(IC_InitStruct->captureState)); + assert_param(IS_FL_ATIM_IC_POLARITY(IC_InitStruct->ICPolarity)); + assert_param(IS_FL_ATIM_IC_ACTIVEINPUT(IC_InitStruct->ICActiveInput)); + assert_param(IS_FL_ATIM_IC_PRESCALER(IC_InitStruct->ICPrescaler)); + assert_param(IS_FL_ATIM_IC_FILTER(IC_InitStruct->ICFilter)); + /* 时钟总线使能配置 */ + FL_RCC_EnableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_ATIM); + FL_RCC_EnableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_ATIM); + /* 通道关闭 */ + FL_ATIM_OC_DisableChannel(TIMx, channel); + /*捕获极性 */ + FL_ATIM_IC_SetChannelPolarity(TIMx, IC_InitStruct->ICPolarity, channel); + /* 捕获映射通道 */ + FL_ATIM_CC_SetChannelMode(TIMx, IC_InitStruct->ICActiveInput, channel); + /* 捕获预分频 */ + FL_ATIM_IC_SetPrescaler(TIMx, IC_InitStruct->ICPrescaler, channel); + /* 捕获滤波器 */ + FL_ATIM_IC_SetFilter(TIMx, IC_InitStruct->ICFilter, channel); + if(IC_InitStruct->captureState == FL_ENABLE) + { + FL_ATIM_IC_EnableChannel(TIMx, channel); + } + return FL_PASS; +} + +/** + * @brief 将 @ref FL_ATIM_IC_InitTypeDef 结构体初始化为默认配置 + * @param TIM_ICInitStruct 指向 @ref FL_ATIM_IC_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_ATIM_IC_StructInit(FL_ATIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* 默认配置 */ + TIM_ICInitStruct->ICPolarity = FL_ATIM_IC_POLARITY_NORMAL; + TIM_ICInitStruct->ICActiveInput = FL_ATIM_CHANNEL_MODE_INPUT_NORMAL; + TIM_ICInitStruct->ICPrescaler = FL_ATIM_IC_PSC_DIV1; + TIM_ICInitStruct->ICFilter = FL_ATIM_IC_FILTER_DIV1; + TIM_ICInitStruct->captureState = FL_DISABLE; +} + +/** + * @brief 配置ATIM触发输入捕获通道ETR + * @param TIMx 外设入口地址 + * @param TIM_InitStruct 指向一个 @ref FL_ATIM_ETR_InitTypeDef 结构体 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_ATIM_ETR_Init(ATIM_Type *TIMx, FL_ATIM_ETR_InitTypeDef *TIM_InitStruct) +{ + assert_param(IS_FL_ATIM_ETP_FILTER(TIM_InitStruct->ETRFilter)); + assert_param(IS_FL_ATIM_ETR_PSC(TIM_InitStruct->ETRClockDivision)); + assert_param(IS_FL_ATIM_ETR_POLARITY(TIM_InitStruct->ETRPolarity)); + /* 时钟总线使能配置 */ + FL_RCC_EnableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_ATIM); + FL_RCC_EnableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_ATIM); + /* 外部时钟极性 */ + FL_ATIM_SetETRPolarity(TIMx, TIM_InitStruct->ETRPolarity); + /* 外部时钟滤波 */ + FL_ATIM_SetETRFilter(TIMx, TIM_InitStruct->ETRFilter); + /* 外部时钟分频 */ + FL_ATIM_SetETRPrescaler(TIMx, TIM_InitStruct->ETRClockDivision); + if(TIM_InitStruct->useExternalTrigger == FL_ENABLE) + { + FL_ATIM_EnableExternalClock(TIMx); + } + else + { + FL_ATIM_DisableExternalClock(TIMx); + } + return FL_PASS; +} + +/** + * @brief 将 @ref FL_ATIM_ETR_InitTypeDef 结构体初始化为默认配置 + * @param TIM_InitStruct 指向 @ref FL_ATIM_ETR_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_ATIM_ETRStructInit(FL_ATIM_ETR_InitTypeDef *TIM_InitStruct) +{ + TIM_InitStruct->useExternalTrigger = FL_DISABLE; + TIM_InitStruct->ETRFilter = FL_ATIM_ETR_FILTER_DIV1; + TIM_InitStruct->ETRPolarity = FL_ATIM_ETR_POLARITY_NORMAL; + TIM_InitStruct->ETRClockDivision = FL_ATIM_ETR_PSC_DIV1; +} + +/** + * @brief 配置TIM的比较输出通道. + * @param TIMx 外设入口地址 + * @param channel ATIM通道 + * 此参数可取以下值： + * @arg @ref FL_ATIM_CHANNEL_1 + * @arg @ref FL_ATIM_CHANNEL_2 + * @arg @ref FL_ATIM_CHANNEL_3 + * @arg @ref FL_ATIM_CHANNEL_4 + * @param TIM_OC_InitStruct 指向 @ref FL_ATIM_OC_InitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_ATIM_OC_Init(ATIM_Type *TIMx, uint32_t channel, FL_ATIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + uint32_t i = 5; + FL_ErrorStatus result = FL_PASS; + /* 参数检查 */ + assert_param(IS_ATIM_INSTANCE(TIMx)); + assert_param(IS_FL_ATIM_OC_MODE(TIM_OC_InitStruct->OCMode)); + assert_param(IS_FL_ATIM_OC_PRELOAD(TIM_OC_InitStruct->OCPreload)); + assert_param(IS_FL_ATIM_OC_POLARITY(TIM_OC_InitStruct->OCPolarity)); + assert_param(IS_FL_ATIM_OC_FASTMODE(TIM_OC_InitStruct->OCFastMode)); + assert_param(IS_FL_ATIM_OC_ETR_CLEARN(TIM_OC_InitStruct->OCETRFStatus)); + assert_param(IS_FL_ATIM_OCN_STATE(TIM_OC_InitStruct->OCNState)); + assert_param(IS_FL_ATIM_OC_STATE(TIM_OC_InitStruct->OCState)); + assert_param(IS_FL_ATIM_OC_IDLESTATE(TIM_OC_InitStruct->OCIdleState)); + assert_param(IS_FL_ATIM_OC_NIDLESTATE(TIM_OC_InitStruct->OCNIdleState)); + assert_param(IS_FL_ATIM_OC_NPOLARITY(TIM_OC_InitStruct->OCNPolarity)); + /* 通道关闭 */ + FL_ATIM_OC_DisableChannel(TIMx, channel); + FL_ATIM_OC_DisableReverseChannel(TIMx, channel); + /* 通道极性 */ + FL_ATIM_OC_SetChannelPolarity(TIMx, TIM_OC_InitStruct->OCPolarity, channel); + /* 通道空闲电平 */ + FL_ATIM_OC_SetChannelIdleState(TIMx, TIM_OC_InitStruct->OCIdleState, channel); + /* 互补通道空闲电平 */ + FL_ATIM_OC_SetReverseChannelIdleState(TIMx, TIM_OC_InitStruct->OCNIdleState, channel); + /* 互补通道极性 */ + FL_ATIM_OC_SetReverseChannelPolarity(TIMx, TIM_OC_InitStruct->OCNPolarity, channel); + /* 捕获映射到输出通道 */ + FL_ATIM_CC_SetChannelMode(TIMx, FL_ATIM_CHANNEL_MODE_OUTPUT, channel); + /* 输出比较模式寄存器配置 */ + OCConfig(TIMx, channel, TIM_OC_InitStruct); + /* 手动触发更新事件，将配置值写入 */ + FL_ATIM_GenerateUpdateEvent(TIMx); + while((!FL_ATIM_IsActiveFlag_Update(ATIM))&i) + { + i--; + } + /*清除UIF标志，防止产生UG事件中断*/ + FL_ATIM_ClearFlag_Update(ATIM); + return result; +} + +/** + * @brief 将 @ref FL_ATIM_OC_InitTypeDef 结构体初始化为默认配置 + * @param TIM_OC_InitStruct 指向 @ref FL_ATIM_OC_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_ATIM_OC_StructInit(FL_ATIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + /* Set the default configuration */ + TIM_OC_InitStruct->OCMode = FL_ATIM_OC_MODE_FROZEN; + TIM_OC_InitStruct->OCETRFStatus = FL_DISABLE; + TIM_OC_InitStruct->OCFastMode = FL_DISABLE; + TIM_OC_InitStruct->compareValue = 0x00000000U; + TIM_OC_InitStruct->OCPolarity = FL_ATIM_OC_POLARITY_NORMAL; + TIM_OC_InitStruct->OCPreload = FL_DISABLE; + TIM_OC_InitStruct->OCIdleState = FL_ATIM_OC_IDLE_STATE_LOW; + TIM_OC_InitStruct->OCNIdleState = FL_ATIM_OCN_IDLE_STATE_LOW; + TIM_OC_InitStruct->OCNPolarity = FL_ATIM_OCN_POLARITY_NORMAL; + TIM_OC_InitStruct->OCNState = FL_DISABLE; +} + +/** + * @brief 配置ATIM的输入捕获通道 + * @param TIMx 外设入口地址 + * @param TIM_BDTR_InitStruct 指向 @ref FL_ATIM_BDTR_InitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_ATIM_BDTR_Init(ATIM_Type *TIMx, FL_ATIM_BDTR_InitTypeDef *TIM_BDTR_InitStruct) +{ + FL_ErrorStatus result = FL_PASS; + /* 参数检查 */ + assert_param(IS_ATIM_INSTANCE(TIMx)); + assert_param(IS_FL_ATIM_OSSR_STATE(TIM_BDTR_InitStruct->OSSRState)); + assert_param(IS_FL_ATIM_OSSI_STATE(TIM_BDTR_InitStruct->OSSIState)); + assert_param(IS_FL_ATIM_LOCK_LEVEL(TIM_BDTR_InitStruct->lockLevel)); + assert_param(IS_FL_ATIM_BREAK_POLARITY(TIM_BDTR_InitStruct->breakPolarity)); + assert_param(IS_FL_ATIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTR_InitStruct->automaticOutput)); + assert_param(IS_FL_ATIM_BDTR_FILTER(TIM_BDTR_InitStruct->breakFilter)); + /* 关闭所有输出 */ + FL_ATIM_DisableALLOutput(TIMx); + /* 设置死区时间 */ + FL_ATIM_WriteDeadTime(TIMx, TIM_BDTR_InitStruct->deadTime); + /* 设置寄存器锁定等级 */ + FL_ATIM_SetLockLevel(TIMx, TIM_BDTR_InitStruct->lockLevel); + /* Idle状态下关闭状态 */ + FL_ATIM_SetOffStateIdle(TIMx, TIM_BDTR_InitStruct->OSSIState); + /* run状态下关闭状态 */ + FL_ATIM_SetOffStateRun(TIMx, TIM_BDTR_InitStruct->OSSRState); + /* 门控1刹车信号 */ + FL_ATIM_SetBreak1GateState(TIMx, TIM_BDTR_InitStruct->gatedBrakeSignal_1); + /* 门控2刹车信号 */ + FL_ATIM_SetBreak2GateState(TIMx, TIM_BDTR_InitStruct->gatedBrakeSignal_2); + /* 门控刹车信号组合方式设置 */ + FL_ATIM_SetBreakSignalCombination(TIMx, TIM_BDTR_InitStruct->brakeSignalCombined); + /* 刹车极性设置 */ + FL_ATIM_SetBreakPolarity(TIMx, TIM_BDTR_InitStruct->breakPolarity); + /* 更新时间自动设置输出配置，如果刹车事件发生过并且当前功能使能，则下一个更新事件将重新自动输出 */ + if(TIM_BDTR_InitStruct->automaticOutput == FL_ENABLE) + { + FL_ATIM_EnableAutomaticOutput(TIMx); + } + else + { + FL_ATIM_DisableAutomaticOutput(TIMx); + } + /* 刹车功能开关配置 */ + if(TIM_BDTR_InitStruct->breakState == FL_ENABLE) + { + FL_ATIM_EnableBreak(TIMx); + } + else + { + FL_ATIM_DisableBreak(TIMx); + } + /* 使能全部输出 */ + FL_ATIM_EnableALLOutput(TIMx); + /* 手动触发更新事件，将配置值写入 */ + FL_ATIM_GenerateCOMEvent(TIMx); + return result; +} + +/** + * @brief 将 @ref FL_ATIM_BDTR_InitTypeDef 结构体初始化为默认配置 + * @param TIM_BDTR_InitStruct 指向 @ref FL_ATIM_BDTR_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_ATIM_BDTR_StructInit(FL_ATIM_BDTR_InitTypeDef *TIM_BDTR_InitStruct) +{ + TIM_BDTR_InitStruct->deadTime = 0x00; + TIM_BDTR_InitStruct->lockLevel = FL_ATIM_LOCK_LEVEL_OFF; + TIM_BDTR_InitStruct->OSSRState = FL_ATIM_OSSR_DISABLE; + TIM_BDTR_InitStruct->OSSIState = FL_ATIM_OSSI_DISABLE; + TIM_BDTR_InitStruct->breakFilter = FL_ATIM_BREAK_FILTER_DIV1; + TIM_BDTR_InitStruct->breakPolarity = FL_ATIM_BREAK_POLARITY_LOW; + TIM_BDTR_InitStruct->automaticOutput = FL_DISABLE; + TIM_BDTR_InitStruct->gatedBrakeSignal_1 = FL_ATIM_BREAK1_GATE_AUTO; + TIM_BDTR_InitStruct->gatedBrakeSignal_2 = FL_ATIM_BREAK2_GATE_AUTO; + TIM_BDTR_InitStruct->breakState = FL_DISABLE; + TIM_BDTR_InitStruct->brakeSignalCombined = FL_ATIM_BREAK_COMBINATION_OR; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_bstim32.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_bstim32.c new file mode 100644 index 0000000000..9f729f82ea --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_bstim32.c @@ -0,0 +1,151 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_bstim32.c + * @author FMSH Application Team + * @brief Src file of BSTIM32 FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_rmu.h" +#include "fm33lc0xx_fl_bstim32.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup BSTIM32 + * @{ + */ + +/* Private macros ------------------------------------------------------------------*/ +/** @addtogroup BSTIM32_FL_Private_Macros + * @{ + */ + +#define IS_FL_BSTIM32_INSTANCE(INSTANCE) ((INSTANCE) == BSTIM32) + +#define IS_FL_BSTIM32_AUTORELOAD_MODE(__VALUE__) (((__VALUE__) == FL_ENABLE)||\ + ((__VALUE__) == FL_DISABLE)) + +#define IS_FL_BSTIM32_CLOCK_SRC(__VALUE__) (((__VALUE__) == FL_RCC_BSTIM32_CLK_SOURCE_APB1CLK)||\ + ((__VALUE__) == FL_RCC_BSTIM32_CLK_SOURCE_LSCLK)||\ + ((__VALUE__) == FL_RCC_BSTIM32_CLK_SOURCE_RCLP)||\ + ((__VALUE__) == FL_RCC_BSTIM32_CLK_SOURCE_RCMF_PSC)) + +/** + * @} + */ + +/** @addtogroup BSTIM32_FL_EF_Init + * @{ + */ + +/** + * @brief 复位BSTIM32外设 + * @param BSTIM32x 外设入口地址 + * @retval 错误状态，可能值: + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_BSTIM32_DeInit(BSTIM32_Type *BSTIM32x) +{ + assert_param(IS_FL_BSTIM32_INSTANCE(BSTIM32x)); + /* 使能外设复位 */ + FL_RCC_EnablePeripheralReset(); + /* 复位外设寄存器 */ + FL_RCC_EnableResetAPB2Peripheral(FL_RCC_RSTAPB_BSTIM32); + FL_RCC_EnableResetAPB2Peripheral(FL_RCC_RSTAPB_BSTIM32); + /* 关闭外设总线始时钟和工作时钟 */ + FL_RCC_DisableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_BSTIM32); + FL_RCC_DisableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_BSTIM32); + /* 锁定外设复位 */ + FL_RCC_DisablePeripheralReset(); + return FL_PASS; +} +/** + * @brief 配置BSTIM32工作在定时器模式 + * @param BSTIM32x 外设入口地址 + * @param initStruct 指向 @ref FL_BSTIM32_InitTypeDef 结构体的指针 + * + * @retval 错误状态，可能值: + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_BSTIM32_Init(BSTIM32_Type *BSTIM32x, FL_BSTIM32_InitTypeDef *initStruct) +{ + uint32_t i = 4000; + /* 参数检查 */ + assert_param(IS_FL_BSTIM32_INSTANCE(BSTIM32x)); + assert_param(IS_FL_BSTIM32_CLOCK_SRC(initStruct->clockSource)); + assert_param(IS_FL_BSTIM32_AUTORELOAD_MODE(initStruct->autoReloadState)); + /* 时钟使能 */ + FL_RCC_EnableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_BSTIM32); + /* 选择时钟源 */ + FL_RCC_SetBSTIM32ClockSource(initStruct->clockSource); + FL_RCC_EnableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_BSTIM32); + /* 分频系数 */ + FL_BSTIM32_WritePrescaler(BSTIM32x, initStruct->prescaler); + /* 自动重装载值 */ + FL_BSTIM32_EnableUpdateEvent(BSTIM32x); + FL_BSTIM32_WriteAutoReload(BSTIM32x, initStruct->autoReload); + if(initStruct->autoReloadState == FL_ENABLE) + { + FL_BSTIM32_EnableARRPreload(BSTIM32x); + } + else + { + FL_BSTIM32_DisableARRPreload(BSTIM32x); + } + /* 手动触发更新事件，将配置值写入 */ + FL_BSTIM32_GenerateUpdateEvent(BSTIM32x); + while((!FL_BSTIM32_IsActiveFlag_Update(BSTIM32x))&i) + { + i--; + } + /*清除UIF标志，防止产生UG事件中断*/ + FL_BSTIM32_ClearFlag_Update(BSTIM32x); + return FL_PASS; +} + +/** + * @brief 将 @ref FL_BSTIM32_InitTypeDef 结构体初始化为默认配置 + * @param initStruct 指向 @ref FL_BSTIM32_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_BSTIM32_StructInit(FL_BSTIM32_InitTypeDef *initStruct) +{ + initStruct->prescaler = 0; + initStruct->autoReload = 0xFFFFFFFF; + initStruct->autoReloadState = FL_ENABLE; + initStruct->clockSource = FL_RCC_BSTIM32_CLK_SOURCE_APB1CLK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_comp.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_comp.c new file mode 100644 index 0000000000..1e4c309dbe --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_comp.c @@ -0,0 +1,178 @@ +/** + **************************************************************************************************** + * @file fm33lc0xx_fl_comp.c + * @author FMSH Application Team + * @brief Src file of COMP FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_comp.h" +#include "fm33lc0xx_fl_rmu.h" +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_opa.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup COMP + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup COMP_FL_Private_Macros + * @{ + */ + +#define IS_COMP_ALL_INSTANCE(INTENCE) (((INTENCE) == COMP1)||\ + ((INTENCE) == COMP2)) + +#define IS_FL_COMP_POSITIVEINPUT(__VALUE__) (((__VALUE__) == FL_COMP_INP_SOURCE_INP1)||\ + ((__VALUE__) == FL_COMP_INP_SOURCE_INP2)||\ + ((__VALUE__) == FL_COMP_INP_SOURCE_INP3)) + +#define IS_FL_COMP_NEGATIVEINPUT(__VALUE__) (((__VALUE__) == FL_COMP_INN_SOURCE_INN1)||\ + ((__VALUE__) == FL_COMP_INN_SOURCE_INN2)||\ + ((__VALUE__) == FL_COMP_INN_SOURCE_VREF)||\ + ((__VALUE__) == FL_COMP_INN_SOURCE_VREF_DIV_2)) + +#define IS_FL_COMP_POLARITY(__VALUE__) (((__VALUE__) == FL_COMP_OUTPUT_POLARITY_NORMAL)||\ + ((__VALUE__) == FL_COMP_OUTPUT_POLARITY_INVERT)) + +#define IS_FL_COMP_EDGE(__VALUE__) (((__VALUE__) == FL_COMP_INTERRUPT_EDGE_BOTH)||\ + ((__VALUE__) == FL_COMP_INTERRUPT_EDGE_RISING )||\ + ((__VALUE__) == FL_COMP_INTERRUPT_EDGE_FALLING)) + +#define IS_FL_COMP_DIGITAL_FILTER(__VALUE__) (((__VALUE__) == FL_DISABLE)||\ + ((__VALUE__) == FL_ENABLE)) + +/** + * @} + */ + +/** @addtogroup COMP_FL_EF_Init + * @{ + */ + +/** + * @brief 复位COMP外设 + * @param COMPx 外设入口地址 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_COMP_DeInit(COMP_Type *COMPx) +{ + /* 入口参数检查 */ + assert_param(IS_COMP_ALL_INSTANCE(COMPx)); + /* 恢复寄存器值为默认值 */ + COMPx->CR = 0x00000000U; + /* 关闭外设总线时钟和工作时钟 */ + FL_RCC_DisableGroup1BusClock(FL_RCC_GROUP1_BUSCLK_ANAC); + /* 锁定外设复位 */ + FL_RCC_DisablePeripheralReset(); + return FL_PASS; +} + +/** + * @brief 根据 COMP_InitStruct 的配置信息初始化对应外设. + * @param COMPx 外设入口地址 + * @param initStruct 指向 @ref FL_COMP_InitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_COMP_Init(COMP_Type *COMPx, FL_COMP_InitTypeDef *initStruct) +{ + /* 入口参数检查 */ + assert_param(IS_COMP_ALL_INSTANCE(COMPx)); + assert_param(IS_FL_COMP_EDGE(initStruct->edge)); + assert_param(IS_FL_COMP_POLARITY(initStruct->polarity)); + assert_param(IS_FL_COMP_POSITIVEINPUT(initStruct->positiveInput)); + assert_param(IS_FL_COMP_NEGATIVEINPUT(initStruct->negativeInput)); + assert_param(IS_FL_COMP_DIGITAL_FILTER(initStruct->digitalFilter)); + /* 使能时钟总线 */ + FL_RCC_EnableGroup1BusClock(FL_RCC_GROUP1_BUSCLK_ANAC); + /* 比较器输出极性选择 */ + FL_COMP_SetOutputPolarity(COMPx, initStruct->polarity); + /* 比较器正向输入选择 */ + FL_COMP_SetINPSource(COMPx, initStruct->positiveInput); + /* 比较器反向输入选择 */ + FL_COMP_SetINNSource(COMPx, initStruct->negativeInput); + /* 比较器使用vref 打开vref_buf */ + if((initStruct->negativeInput == FL_COMP_INN_SOURCE_VREF) || (initStruct->negativeInput == FL_COMP_INN_SOURCE_VREF_DIV_2)) + { + FL_OPA_EnableVrefBuffer(OPA1);//使能 + FL_OPA_DisableBypassVrefBuffer(OPA1);//不bypass + } + if(COMPx == COMP1) + { + /* 比较器中断边沿选择 */ + FL_COMP_SetComparator1InterruptEdge(COMP, initStruct->edge); + } + else + { + /* 比较器中断边沿选择 */ + FL_COMP_SetComparator2InterruptEdge(COMP, initStruct->edge); + } + /* 滤波 */ + if(initStruct->digitalFilter) + { + if(COMPx == COMP1) + { FL_COMP_EnableComparator1OutputFilter(COMP); } + else + { FL_COMP_EnableComparator2OutputFilter(COMP); } + } + else + { + if(COMPx == COMP1) + { FL_COMP_DisableComparator1OutputFilter(COMP); } + else + { FL_COMP_DisableComparator2OutputFilter(COMP); } + } + return FL_PASS; +} +/** + * @brief 将 @ref FL_COMP_InitTypeDef 结构体初始化为默认配置 + * @param initStruct 指向 @ref FL_COMP_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_COMP_StructInit(FL_COMP_InitTypeDef *initStruct) +{ + /* 复位配置信息 */ + initStruct->edge = FL_COMP_INTERRUPT_EDGE_BOTH; + initStruct->polarity = FL_COMP_OUTPUT_POLARITY_NORMAL; + initStruct->negativeInput = FL_COMP_INN_SOURCE_INN1; + initStruct->positiveInput = FL_COMP_INP_SOURCE_INP1; + initStruct->digitalFilter = FL_ENABLE; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/*************************************************************END OF FILE************************************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_crc.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_crc.c new file mode 100644 index 0000000000..7fa4510d8d --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_crc.c @@ -0,0 +1,161 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_crc.c + * @author FMSH Application Team + * @brief Src file of CRC FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_crc.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup CRC_FL_Private_Macros + * @{ + */ + +#define IS_FL_CRC_INSTANCE(INTANCE) ((INTANCE) == CRC) + +#define IS_FL_CRC_POLYNOMIAL_WIDTH(__VALUE__) (((__VALUE__) == FL_CRC_POLYNOMIAL_16B)||\ + ((__VALUE__) == FL_CRC_POLYNOMIAL_32B)||\ + ((__VALUE__) == FL_CRC_POLYNOMIAL_8B)||\ + ((__VALUE__) == FL_CRC_POLYNOMIAL_7B)) + +#define IS_FL_CRC_DR_WIDTH(__VALUE__) (((__VALUE__) == FL_CRC_DATA_WIDTH_8B)||\ + ((__VALUE__) == FL_CRC_DATA_WIDTH_32B)) + + +#define IS_FL_CRC_OUPUT_REFLECTE_MODE(__VALUE__) (((__VALUE__) == FL_CRC_OUPUT_INVERT_NONE)||\ + ((__VALUE__) == FL_CRC_OUPUT_INVERT_BYTE)) + +#define IS_FL_CRC_INPUT_REFLECTE_MODE(__VALUE__) (((__VALUE__) == FL_CRC_INPUT_INVERT_NONE)||\ + ((__VALUE__) == FL_CRC_INPUT_INVERT_BYTE)||\ + ((__VALUE__) == FL_CRC_INPUT_INVERT_HALF_WORD)||\ + ((__VALUE__) == FL_CRC_INPUT_INVERT_WORD)) + +#define IS_FL_CRC_CALCULA_MODE(__VALUE__) (((__VALUE__) == FL_CRC_CALCULATE_SERIAL)||\ + ((__VALUE__) == FL_CRC_CALCULATE_PARALLEL)) + +/** + * @} + */ + +/** @addtogroup CRC_FL_EF_Init + * @{ + */ + +/** + * @brief 复位CRC外设 + * @param CRCx 外设入口地址 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_CRC_DeInit(CRC_Type *CRCx) +{ + assert_param(IS_FL_CRC_INSTANCE(CRCx)); + /* 外设复位使能 */ + FL_RCC_EnablePeripheralReset(); + /* 复位外设寄存器 */ + FL_RCC_EnableResetAPB2Peripheral(FL_RCC_RSTAPB_CRC); + FL_RCC_DisableResetAPB2Peripheral(FL_RCC_RSTAPB_CRC); + /* 关闭总线时钟 */ + FL_RCC_DisableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_CRC); + /* 锁定外设复位功能 */ + FL_RCC_DisablePeripheralReset(); + return FL_PASS; +} + +/** + * @brief 根据 CRC_InitStruct 的配置信息初始化对应外设入口地址的寄存器值. + * + * @param CRCx 外设入口地址 + * @param CRC_InitStruct 指向一个 @ref FL_CRC_InitTypeDef 结构体其中包含了外设的相关配置信息. + * + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_CRC_Init(CRC_Type *CRCx, FL_CRC_InitTypeDef *CRC_InitStruct) +{ + /* 参数检查 */ + assert_param(IS_FL_CRC_INSTANCE(CRCx)); + assert_param(IS_FL_CRC_DR_WIDTH(CRC_InitStruct->dataWidth)); + assert_param(IS_FL_CRC_CALCULA_MODE(CRC_InitStruct->calculatMode)); + assert_param(IS_FL_CRC_POLYNOMIAL_WIDTH(CRC_InitStruct->polynomialWidth)); + assert_param(IS_FL_CRC_INPUT_REFLECTE_MODE(CRC_InitStruct->reflectIn)); + assert_param(IS_FL_CRC_OUPUT_REFLECTE_MODE(CRC_InitStruct->reflectOut)); + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_CRC); + FL_CRC_SetCalculateMode(CRCx, CRC_InitStruct->calculatMode); + FL_CRC_SetInputInvertMode(CRCx, CRC_InitStruct->reflectIn); + FL_CRC_SetOutputInvertMode(CRCx, CRC_InitStruct->reflectOut); + FL_CRC_SetPolynomialWidth(CRCx, CRC_InitStruct->polynomialWidth); + FL_CRC_WriteXORValue(CRCx, CRC_InitStruct->xorReg); + FL_CRC_WritePolynominalParam(CRCx, CRC_InitStruct->polynomial); + FL_CRC_WriteInitialValue(CRCx, CRC_InitStruct->initVal); + FL_CRC_SetDataWidth(CRCx, CRC_InitStruct->dataWidth); + if(CRC_InitStruct->xorRegState == FL_ENABLE) + { + FL_CRC_EnableOutputXOR(CRCx); + } + else + { + FL_CRC_DisableOutputXOR(CRCx); + } + return FL_PASS; +} + + +/** + * @brief 将 @ref FL_CRC_InitTypeDef 结构体初始化为默认配置 + * @param CRC_InitStruct 指向 @ref FL_CRC_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_CRC_StructInit(FL_CRC_InitTypeDef *CRC_InitStruct) +{ + CRC_InitStruct->polynomial = 0x00000000; + CRC_InitStruct->polynomialWidth = FL_CRC_POLYNOMIAL_16B; + CRC_InitStruct->dataWidth = FL_CRC_DATA_WIDTH_8B; + CRC_InitStruct->calculatMode = FL_CRC_CALCULATE_SERIAL; + CRC_InitStruct->reflectIn = FL_CRC_INPUT_INVERT_NONE; + CRC_InitStruct->reflectOut = FL_CRC_OUPUT_INVERT_NONE; + CRC_InitStruct->xorReg = 0x00000000; + CRC_InitStruct->xorRegState = FL_DISABLE; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_divas.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_divas.c new file mode 100644 index 0000000000..5da99d8b25 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_divas.c @@ -0,0 +1,155 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_divas.c + * @author FMSH Application Team + * @brief Src file of DIVAS FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_divas.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup DIVAS + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup DIVAS_FL_Private_Macros + * @{ + */ +#define IS_DIVAS_ALL_INSTANCE(INTENCE) ((INTENCE) == DIV) + +#define IS_FL_DIVAS_DIVISOR(__VALUE__) (((__VALUE__) != 0)) + +/** + * @} + */ + +/** @addtogroup DIVAS_FL_EF_Init + * @{ + */ + +/** + * @brief 复位DIVAS外设 + * + * @param DIVx 外设入口地址 + * + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_DIVAS_DeInit(DIV_Type *DIVx) +{ + /* 入口参数检查 */ + assert_param(IS_DIVAS_ALL_INSTANCE(DIVx)); + /* 外设复位使能 */ + FL_RCC_EnablePeripheralReset(); + /* 恢复寄存器值为默认值 */ + FL_RCC_EnableResetAPB2Peripheral(FL_RCC_RSTAPB_DIVAS); + FL_RCC_DisableResetAPB2Peripheral(FL_RCC_RSTAPB_DIVAS); + /* 关闭总线时钟 */ + FL_RCC_DisableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_HDIV); + /* 锁定外设复位功能 */ + FL_RCC_DisablePeripheralReset(); + return FL_PASS; +} + +/** + * @brief 配置DIVAS外设的DIV模块 + * + * @param DIVx 外设入口地址 + * + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_DIVAS_Init(DIV_Type *DIVx) +{ + /* 入口参数检查 */ + assert_param(IS_DIVAS_ALL_INSTANCE(DIVx)); + /* 使能时钟总线 */ + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_HDIV); + return FL_PASS; +} + +/** + * @} + */ + +/** @addtogroup DIVAS_FL_EF_Operation + * @{ + */ + +/** + * @brief 硬件除法器计算 + * + * @param DIVx 外设入口地址 + * @param DivisorEnd 32位有符号被除数 + * @param Divisor 16位有符号除数，注意不能为0 + * @param Quotient 指向 @ref int32_t 指针 保存商的地址 + * @param Residue 指向 @ref int16_t 指针 保存余数的地址 + * + * @retval 计算正确性与否 + * -0 计算结果正确 + * -非0 计算过程发生错误 + */ +uint32_t FL_DIVAS_Hdiv_Calculation(DIV_Type *DIVx, int32_t DivisorEnd, int16_t Divisor, int32_t *Quotient, int16_t *Residue) +{ + uint32_t TimeOut ; + FL_DIV_WriteDividend_S32(DIVx, DivisorEnd); + FL_DIV_WriteDivisor_S16(DIVx, Divisor); + if(FL_DIV_IsActiveFlag_DividedZero(DIVx)) + { + /*除数为0 */ + *Quotient = 0; + *Residue = 0; + return 1; + } + TimeOut = FL_DIVAS_SR_BUSY_TIMEOUT; + while(FL_DIV_IsActiveFlag_Busy(DIVx)) + { + TimeOut--; + if(TimeOut == 0) + { + /* 计算超时*/ + *Quotient = 0; + *Residue = 0; + return 3; + } + } + *Quotient = FL_DIV_ReadQuotient_S32(DIVx); + *Residue = FL_DIV_ReadResidue_S16(DIVx); + return 0; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_dma.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_dma.c new file mode 100644 index 0000000000..be17ea2ad6 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_dma.c @@ -0,0 +1,238 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_dma.c + * @author FMSH Application Team + * @brief Src file of DMA FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_rmu.h" +#include "fm33lc0xx_fl_dma.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup DMA_FL_Private_Macros + * @{ + */ + +#define IS_FL_DMA_INSTANCE(INTANCE) ((INTANCE) == DMA) + +#define IS_FL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == FL_DMA_PRIORITY_LOW)||\ + ((__VALUE__) == FL_DMA_PRIORITY_MEDIUM)||\ + ((__VALUE__) == FL_DMA_PRIORITY_HIGH)||\ + ((__VALUE__) == FL_DMA_PRIORITY_VERYHIGH)) + +#define IS_FL_DMA_CIRC_MODE(__VALUE__) (((__VALUE__) == FL_DISABLE)||\ + ((__VALUE__) == FL_ENABLE)) + + +#define IS_FL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == FL_DMA_DIR_PERIPHERAL_TO_RAM)||\ + ((__VALUE__) == FL_DMA_DIR_RAM_TO_PERIPHERAL)||\ + ((__VALUE__) == FL_DMA_DIR_FLASH_TO_RAM)||\ + ((__VALUE__) == FL_DMA_DIR_RAM_TO_FLASH)) + + +#define IS_FL_DMA_DATA_SIZE(__VALUE__) (((__VALUE__) == FL_DMA_BANDWIDTH_8B)||\ + ((__VALUE__) == FL_DMA_BANDWIDTH_32B)||\ + ((__VALUE__) == FL_DMA_BANDWIDTH_16B)) + +#define IS_FL_DMA_INCMODE(__VALUE__) (((__VALUE__) == FL_DMA_MEMORY_INC_MODE_INCREASE)||\ + ((__VALUE__) == FL_DMA_MEMORY_INC_MODE_DECREASE) ||\ + ((__VALUE__) == FL_DMA_CH7_MEMORY_INC_MODE_INCREASE)||\ + ((__VALUE__) == FL_DMA_CH7_MEMORY_INC_MODE_DECREASE)||\ + ((__VALUE__) == FL_DMA_CH7_FLASH_INC_MODE_INCREASE)||\ + ((__VALUE__) == FL_DMA_CH7_FLASH_INC_MODE_DECREASE)) + +#define IS_FL_DMA_PERIPH(__VALUE__) (((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION1)||\ + ((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION2)||\ + ((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION3)||\ + ((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION4)||\ + ((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION5)||\ + ((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION6)||\ + ((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION7)||\ + ((__VALUE__) == FL_DMA_PERIPHERAL_FUNCTION8)) +/** + * @} + */ + +/** @addtogroup DMA_FL_EF_Init + * @{ + */ + +/** + * @brief 复位DMA相关寄存器 + * @param DMAx 外设入口地址 + * @retval 错误状态，可能值 + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_DMA_DeInit(DMA_Type *DMAx) +{ + assert_param(IS_FL_DMA_INSTANCE(DMAx)); + /* 使能外设复位 */ + FL_RCC_EnablePeripheralReset(); + /* 复位外设寄存器 */ + FL_RCC_EnableResetAHBPeripheral(FL_RCC_RSTAHB_DMA); + FL_RCC_DisableResetAHBPeripheral(FL_RCC_RSTAHB_DMA); + /* 关闭外设总线始时钟和工作时钟 */ + FL_RCC_DisableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_DMA); + /* 锁定外设复位 */ + FL_RCC_DisablePeripheralReset(); + return FL_PASS; +} + +/** + * @brief 根据 initStruct 的配置信息初始化对应外设入口地址的寄存器值. + * @param DMAx 外设入口地址 + * @param initStruct 指向一个 @ref FL_DMA_InitTypeDef 结构体 + * 其中包含了外设的相关配置信息. + * @param Channel 此参数可取以下值： + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval 错误状态，可能值： + * -FL_FAIL 配置过程发生错误 + * -FL_PASS 配置成功 + */ +FL_ErrorStatus FL_DMA_Init(DMA_Type *DMAx, FL_DMA_InitTypeDef *initStruct, uint32_t channel) +{ + /* 参数检查 */ + assert_param(IS_FL_DMA_INSTANCE(DMAx)); + assert_param(IS_FL_DMA_PRIORITY(initStruct->priority)); + assert_param(IS_FL_DMA_CIRC_MODE(initStruct->circMode)); + assert_param(IS_FL_DMA_DIRECTION(initStruct->direction)); + assert_param(IS_FL_DMA_DATA_SIZE(initStruct->dataSize)); + assert_param(IS_FL_DMA_INCMODE(initStruct->memoryAddressIncMode)); + /* 开启时钟 */ + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_DMA); + /* 配置通道优先级 */ + FL_DMA_SetPriority(DMAx, initStruct->priority, channel); + /* RAM地址方向 */ + FL_DMA_SetMemoryIncrementMode(DMAx, initStruct->memoryAddressIncMode, channel); + /* 传输方向 */ + FL_DMA_SetTransmissionDirection(DMAx, initStruct->direction, channel); + /* 数据宽度 */ + FL_DMA_SetBandwidth(DMAx, initStruct->dataSize, channel); + /* 循环模式 */ + if(initStruct->circMode == FL_ENABLE) + { + FL_DMA_EnableCircularMode(DMAx, channel); + if(channel == FL_DMA_CHANNEL_7) + { + return FL_FAIL; + } + } + else + { + FL_DMA_DisableCircularMode(DMAx, channel); + } + /* 如果是通道7 外设地址实际就是FLASH地址，因此这里针对通道7做了单独处理 */ + if(channel != FL_DMA_CHANNEL_7) + { + assert_param(IS_FL_DMA_PERIPH(initStruct->periphAddress)); + FL_DMA_SetPeripheralMap(DMAx, initStruct->periphAddress, channel); + } + else + { + /* Flash地址方向 */ + FL_DMA_SetFlashIncrementMode(DMAx, initStruct->flashAddressIncMode); + } + return FL_PASS; +} + +/** + * @brief 将 @ref FL_DMA_InitTypeDef 结构体初始化为默认配置 + * @param initStruct 指向需要将值设置为默认配置的结构体 @ref FL_DMA_InitTypeDef 结构体 + * + * @retval None + */ +void FL_DMA_StructInit(FL_DMA_InitTypeDef *initStruct) +{ + initStruct->circMode = FL_DISABLE; + initStruct->dataSize = FL_DMA_BANDWIDTH_8B; + initStruct->direction = FL_DMA_DIR_PERIPHERAL_TO_RAM; + initStruct->periphAddress = FL_DMA_PERIPHERAL_FUNCTION1; + initStruct->priority = FL_DMA_PRIORITY_LOW; + initStruct->memoryAddressIncMode = FL_DMA_MEMORY_INC_MODE_INCREASE; +} + +/** + *@} + */ + +/** @addtogroup DMA_FL_EF_Operation + * @{ + */ + +/** + * @brief 启动一次DMA传输. + * @param DMAx 外设入口地址 + * @param configStruct 指向一个 @ref FL_DMA_ConfigTypeDef 结构体 + * 其中包含了外设的相关配置信息. + * @param channel 此参数可取以下值: + * @arg @ref FL_DMA_CHANNEL_0 + * @arg @ref FL_DMA_CHANNEL_1 + * @arg @ref FL_DMA_CHANNEL_2 + * @arg @ref FL_DMA_CHANNEL_3 + * @arg @ref FL_DMA_CHANNEL_4 + * @arg @ref FL_DMA_CHANNEL_5 + * @arg @ref FL_DMA_CHANNEL_6 + * @arg @ref FL_DMA_CHANNEL_7 + * @retval 错误状态，可能值： + * -FL_FAIL 配置过程发生错误可能是超时也可能是地址非法 + * -FL_PASS 配置成功 + */ +FL_ErrorStatus FL_DMA_StartTransmission(DMA_Type *DMAx, FL_DMA_ConfigTypeDef *configStruct, uint32_t channel) +{ + /* 配置传输个数 */ + FL_DMA_WriteTransmissionSize(DMAx, configStruct->transmissionCount, channel); + /* 配置Memory地址 */ + FL_DMA_WriteMemoryAddress(DMAx, configStruct->memoryAddress, channel); + /* 清除DMA通道中断标志位 */ + FL_DMA_ClearFlag_TransferHalfComplete(DMAx, channel); + FL_DMA_ClearFlag_TransferComplete(DMAx, channel); + /* 使能DMA通道使能开关 */ + FL_DMA_EnableChannel(DMAx, channel); + return FL_PASS; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_exti.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_exti.c new file mode 100644 index 0000000000..40cdcd4937 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_exti.c @@ -0,0 +1,235 @@ +/** + **************************************************************************************************** + * @file fm33lc0xx_fl_exti.c + * @author FMSH Application Team + * @brief Src file of EXTI FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_exti.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver_EXTI + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup EXTI_FL_Private_Macros + * @{ + */ + +#define IS_EXTI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FL_GPIO_EXTI_LINE_0)||\ + ((INSTANCE) == FL_GPIO_EXTI_LINE_1)||\ + ((INSTANCE) == FL_GPIO_EXTI_LINE_2)||\ + ((INSTANCE) == FL_GPIO_EXTI_LINE_3)||\ + ((INSTANCE) == FL_GPIO_EXTI_LINE_4)||\ + ((INSTANCE) == FL_GPIO_EXTI_LINE_5)||\ + ((INSTANCE) == FL_GPIO_EXTI_LINE_6)||\ + ((INSTANCE) == FL_GPIO_EXTI_LINE_7)||\ + ((INSTANCE) == FL_GPIO_EXTI_LINE_8)||\ + ((INSTANCE) == FL_GPIO_EXTI_LINE_9)||\ + ((INSTANCE) == FL_GPIO_EXTI_LINE_10)||\ + ((INSTANCE) == FL_GPIO_EXTI_LINE_11)||\ + ((INSTANCE) == FL_GPIO_EXTI_LINE_12)||\ + ((INSTANCE) == FL_GPIO_EXTI_LINE_13)||\ + ((INSTANCE) == FL_GPIO_EXTI_LINE_14)) + +#define IS_EXTI_CLK_SOURCE(__VALUE__) (((__VALUE__) == FL_RCC_EXTI_CLK_SOURCE_HCLK)||\ + ((__VALUE__) == FL_RCC_EXTI_CLK_SOURCE_LSCLK)) + +#define IS_EXTI_INPUT_GROUP(__VALUE__) (((__VALUE__) == FL_GPIO_EXTI_INPUT_GROUP0)||\ + ((__VALUE__) == FL_GPIO_EXTI_INPUT_GROUP1)||\ + ((__VALUE__) == FL_GPIO_EXTI_INPUT_GROUP2)||\ + ((__VALUE__) == FL_GPIO_EXTI_INPUT_GROUP3)) + +#define IS_EXTI_TRIG_EDGE(__VALUE__) (((__VALUE__) == FL_GPIO_EXTI_TRIGGER_EDGE_RISING)||\ + ((__VALUE__) == FL_GPIO_EXTI_TRIGGER_EDGE_FALLING)||\ + ((__VALUE__) == FL_GPIO_EXTI_TRIGGER_EDGE_BOTH)) + +#define IS_EXTI_FILTER(__VALUE__) (((__VALUE__) == FL_ENABLE)||\ + ((__VALUE__) == FL_DISABLE)) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup EXTI_FL_Private_Consts + * @{ + */ + +typedef void (*pSetExtiLineFunc)(GPIO_COMMON_Type *, uint32_t); +static const pSetExtiLineFunc setExtiLineFuncs[] = +{ + FL_GPIO_SetExtiLine0, + FL_GPIO_SetExtiLine1, + FL_GPIO_SetExtiLine2, + FL_GPIO_SetExtiLine3, + FL_GPIO_SetExtiLine4, + FL_GPIO_SetExtiLine5, + FL_GPIO_SetExtiLine6, + FL_GPIO_SetExtiLine7, + FL_GPIO_SetExtiLine8, + FL_GPIO_SetExtiLine9, + FL_GPIO_SetExtiLine10, + NULL, + FL_GPIO_SetExtiLine12, + FL_GPIO_SetExtiLine13, + FL_GPIO_SetExtiLine14, +}; + +typedef void (*pSetTrigEdgeFunc)(GPIO_COMMON_Type *, uint32_t, uint32_t); +static const pSetTrigEdgeFunc setTrigEdgeFuncs[] = +{ + FL_GPIO_SetTriggerEdge, +}; + +/** + * @} + */ + +/** @addtogroup EXTI_FL_EF_Init + * @{ + */ + +/** + * @brief EXTI通用配置设置 + * + * @param EXTI_CommonInitStruct 指向 @ref FL_EXTI_CommonInitTypeDef 类型的结构体，它包含EXTI外设通用配置信息 + * + * @retval ErrorStatus枚举值 + * -FL_FAIL 配置过程发生错误 + * -FL_PASS EXTI配置成功 + */ +FL_ErrorStatus FL_EXTI_CommonInit(FL_EXTI_CommonInitTypeDef *EXTI_CommonInitStruct) +{ + assert_param(IS_EXTI_CLK_SOURCE(EXTI_CommonInitStruct->clockSource)); + // 使能IO时钟寄存器总线时钟 + FL_RCC_EnableGroup1BusClock(FL_RCC_GROUP1_BUSCLK_PAD); + // 使能并配置外部中断时钟源 + FL_RCC_EnableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_EXTI); + FL_RCC_SetEXTIClockSource(EXTI_CommonInitStruct->clockSource); + return FL_PASS; +} + +/** + * @brief 复位EXTI通用配置设置 + * + * @retval ErrorStatus枚举值 + * -FL_FAIL 发生错误 + * -FL_PASS EXTI通用设置复位成功 + */ +FL_ErrorStatus FL_EXTI_CommonDeinit(void) +{ + // 关闭外部中断时钟源 + FL_RCC_DisableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_EXTI); + return FL_PASS; +} + +/** + * @brief 设置 EXTI_CommonInitStruct 为默认配置 + * @param EXTI_CommonInitStruct 指向需要将值设置为默认配置的结构体 @ref FL_EXTI_CommonInitTypeDef 结构体 + * + * @retval None + */ +void FL_EXTI_CommonStructInit(FL_EXTI_CommonInitTypeDef *EXTI_CommonInitStruct) +{ + EXTI_CommonInitStruct->clockSource = FL_RCC_EXTI_CLK_SOURCE_LSCLK; +} + +/** + * @brief EXTI配置设置 + * + * @param extiLineX 外设入口地址 + * @param EXTI_InitStruct 指向 @ref FL_EXTI_InitTypeDef 类型的结构体，它包含EXTI外设配置信息 + * + * @retval ErrorStatus枚举值 + * -FL_FAIL 配置过程发生错误 + * -FL_PASS EXTI配置成功 + */ +FL_ErrorStatus FL_EXTI_Init(uint32_t extiLineX, FL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint8_t extiLineId; + uint32_t tmpExtiLineX; + // 检查参数合法性 + assert_param(IS_EXTI_ALL_INSTANCE(extiLineX)); + assert_param(IS_EXTI_INPUT_GROUP(EXTI_InitStruct->input)); + assert_param(IS_EXTI_TRIG_EDGE(EXTI_InitStruct->triggerEdge)); + assert_param(IS_EXTI_FILTER(EXTI_InitStruct->filter)); + // 获取EXTI中断线对应id号 + tmpExtiLineX = extiLineX; + for(extiLineId = 0; tmpExtiLineX != FL_GPIO_EXTI_LINE_0; tmpExtiLineX >>= 1, extiLineId++); + // 设置中断线连接的IO + setExtiLineFuncs[extiLineId](GPIO, EXTI_InitStruct->input << (2 * extiLineId)); + // 设置数字滤波 + EXTI_InitStruct->filter == FL_ENABLE ? FL_GPIO_EnableDigitalFilter(GPIO, extiLineX) : FL_GPIO_DisableDigitalFilter(GPIO, extiLineX); + // 设置中断线触发边沿 + setTrigEdgeFuncs[extiLineId / 16](GPIO, extiLineX, EXTI_InitStruct->triggerEdge); + // 延时需要大于1个32K的周期 + FL_DelayUs(50); + // 清除外部中断标志 + FL_GPIO_ClearFlag_EXTI(GPIO, extiLineX); + // 清除中断挂起 + NVIC_ClearPendingIRQ(GPIO_IRQn); + return FL_PASS; +} + +/** + * @brief 复位EXTI配置设置 + * + * @retval ErrorStatus枚举值 + * -FL_FAIL 发生错误 + * -FL_PASS EXTI设置复位成功 + */ +FL_ErrorStatus FL_EXTI_DeInit(uint32_t extiLineX) +{ + uint8_t extiLineId; + uint32_t tmpExtiLineX; + // 检查参数合法性 + assert_param(IS_EXTI_ALL_INSTANCE(extiLineX)); + // 获取EXTI中断线对应id号 + tmpExtiLineX = extiLineX; + for(extiLineId = 0; tmpExtiLineX != FL_GPIO_EXTI_LINE_0; tmpExtiLineX >>= 1, extiLineId++); + // 清除外部中断标志 + FL_GPIO_ClearFlag_EXTI(GPIO, extiLineX); + // 中断线触发边沿禁止 + setTrigEdgeFuncs[extiLineId / 16](GPIO, extiLineX, FL_GPIO_EXTI_TRIGGER_EDGE_DISABLE); + // 禁止数字滤波 + FL_GPIO_DisableDigitalFilter(GPIO, extiLineX); + return FL_PASS; +} + +/** + * @brief 设置 EXTI_InitStruct 为默认配置 + * @param EXTI_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_EXTI_InitTypeDef 结构体 + * + * @retval None + */ +void FL_EXTI_StructInit(FL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->filter = FL_DISABLE; + EXTI_InitStruct->input = FL_GPIO_EXTI_INPUT_GROUP0; + EXTI_InitStruct->triggerEdge = FL_GPIO_EXTI_TRIGGER_EDGE_RISING; +} + +/** + * @} + */ + +/** + * @} + */ +/*************************************************************END OF FILE************************************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_flash.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_flash.c new file mode 100644 index 0000000000..b2f106c801 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_flash.c @@ -0,0 +1,571 @@ +/** + **************************************************************************************************** + * @file fm33lc0xx_fl_flash.c + * @author FMSH Application Team + * @brief Src file of FLASH FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_flash.h" +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_dma.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup FLASH_FL_Private_Macros + * @{ + */ + +#define IS_FLASH_ALL_INSTANCE(INTENCE) (((INTENCE) == FLASH)) + +#define IS_FL_FLASH_PAGE_NUM(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) &&\ + ((__VALUE__) <= (FL_FLASH_MAX_PAGE_NUM))) + +#define IS_FL_FLASH_SECTOR_NUM(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) &&\ + ((__VALUE__) <= (FL_FLASH_MAX_SECTOR_NUM))) + +#define IS_FL_FLASH_MAX_ADDR(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) &&\ + ((__VALUE__) <= (FL_FLASH_ADDR_MAXPROGRAM))) + +#define IS_FL_FLASH_MAX_PAGE(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) &&\ + ((__VALUE__) <= (FL_FLASH_MAX_PAGE_NUM))) + +#define IS_FL_FLASH_MAX_SECTOR(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) &&\ + ((__VALUE__) <= (FL_FLASH_MAX_SECTOR_NUM))) +/** + * @} + */ + +/** @addtogroup FLASH_FL_EF_Init + * @{ + */ + +/** + *@} + */ + +/** @addtogroup FLASH_FL_EF_Operation + * @{ + */ + +/** + * @brief Flash 页擦除函数，一个页为512byte. + * @param FLASHx 外设入口地址 + * @param address 为需要擦除的页内任意地址，推荐使用页开始的首地址（字对齐） + * . + * @retval 错误状态，可能值： + * -FL_FAIL 擦写发生错误 + * -FL_PASS 擦写成功 + */ +FL_ErrorStatus FL_FLASH_PageErase(FLASH_Type *FLASHx, uint32_t address) +{ + uint32_t timeout = 0; + uint32_t primask; + FL_ErrorStatus ret = FL_PASS; + /* 入口参数检查 */ + assert_param(IS_FLASH_ALL_INSTANCE(FLASHx)); + assert_param(IS_FL_FLASH_MAX_ADDR((uint32_t)address)); + /*时钟使能*/ + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_FLASH); + if(address & (FL_FLASH_ADDRS_ALIGN - 1)) + { + /*地址未对齐*/ + return FL_FAIL; + } + if(FL_FLASH_GetFlashLockStatus(FLASHx) == FL_FLASH_KEY_STATUS_ERROR) + { + /*Flash 已经锁定，复位前无法操作*/ + return FL_FAIL; + } + FL_RCC_EnableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_FLASH); + /*配置擦写类型*/ + FL_FLASH_SetFlashEraseType(FLASHx, FL_FLASH_ERASE_TYPE_PAGE); + /* 开始擦除页*/ + FL_FLASH_EnableErase(FLASHx); + /* Key 序列*/ + primask = __get_PRIMASK(); + __disable_irq(); + FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_ERASE_KEY); + FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PAGE_ERASE_KEY); + __set_PRIMASK(primask); + FL_FLASH_ClearFlag_EraseComplete(FLASHx); + /* 擦请求 */ + *((uint32_t *)address) = FL_FLASH_ERASE_REQUEST; + while(1) + { + timeout++; + if((timeout > FL_FLASH_ERASE_TIMEOUT)\ + || (FL_FLASH_IsActiveFlag_ClockError(FLASHx))\ + || (FL_FLASH_IsActiveFlag_KeyError(FLASHx))\ + || (FL_FLASH_IsActiveFlag_AuthenticationError(FLASHx))) + { + /* 超时或出现错误 */ + ret = FL_FAIL; + break; + } + else + if(FL_FLASH_IsActiveFlag_EraseComplete(FLASHx)) + { + /*编程成功*/ + FL_FLASH_ClearFlag_EraseComplete(FLASHx); + ret = FL_PASS; + break; + } + } + FL_FLASH_LockFlash(FLASHx); + FL_RCC_DisableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_FLASH); + FL_RCC_DisableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_FLASH); + return ret; +} + +/** + * @brief Flash 扇区擦除函数，一个扇区为2k byte. + * @param FLASHx 外设入口地址 + * @param address 为需要擦除的扇区内任意地址，推荐使用扇区开始的首地址（字对齐） + * . + * @retval 错误状态，可能值： + * -FL_FAIL 擦写发生错误 + * -FL_PASS 擦写成功 + */ +FL_ErrorStatus FL_FLASH_SectorErase(FLASH_Type *FLASHx, uint32_t address) +{ + uint32_t timeout = 0; + uint32_t primask; + FL_ErrorStatus ret = FL_PASS; + /* 入口参数检查 */ + assert_param(IS_FLASH_ALL_INSTANCE(FLASHx)); + assert_param(IS_FL_FLASH_MAX_ADDR((uint32_t)address)); + /*时钟使能*/ + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_FLASH); + if(address & (FL_FLASH_ADDRS_ALIGN - 1)) + { + /*地址未对齐*/ + return FL_FAIL; + } + if(FL_FLASH_GetFlashLockStatus(FLASHx) == FL_FLASH_KEY_STATUS_ERROR) + { + /*Flash 已经锁定，复位前无法操作*/ + return FL_FAIL; + } + FL_RCC_EnableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_FLASH); + /*配置擦写类型*/ + FL_FLASH_SetFlashEraseType(FLASHx, FL_FLASH_ERASE_TYPE_SECTOR); + /* 开始擦除扇区*/ + FL_FLASH_EnableErase(FLASHx); + /* Key 序列*/ + primask = __get_PRIMASK(); + __disable_irq(); + FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_ERASE_KEY); + FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_SECTOR_ERASE_KEY); + __set_PRIMASK(primask); + FL_FLASH_ClearFlag_EraseComplete(FLASHx); + /* 擦请求 */ + *((uint32_t *)address) = FL_FLASH_ERASE_REQUEST; + while(1) + { + timeout++; + if((timeout > FL_FLASH_ERASE_TIMEOUT)\ + || (FL_FLASH_IsActiveFlag_ClockError(FLASHx))\ + || (FL_FLASH_IsActiveFlag_KeyError(FLASHx))\ + || (FL_FLASH_IsActiveFlag_AuthenticationError(FLASHx))) + { + /* 超时或出现错误 */ + ret = FL_FAIL; + break; + } + else + if(FL_FLASH_IsActiveFlag_EraseComplete(FLASHx)) + { + /*编程成功*/ + FL_FLASH_ClearFlag_EraseComplete(FLASHx); + ret = FL_PASS; + break; + } + } + FL_FLASH_LockFlash(FLASHx); + FL_RCC_DisableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_FLASH); + FL_RCC_DisableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_FLASH); + return ret; +} + +/** + * @brief 单次编程函数，编程地址必须对齐到字边界. + * @param FLASHx 外设入口地址 + * @param address 为需要编程的已经擦除过的扇区内任意地址，非对齐地址编程将触发fault。 + * @param data 待写入数据 + * @retval 错误状态，可能值： + * -FL_FAIL 编程发生错误 + * -FL_PASS 编程成功 + */ +FL_ErrorStatus FL_FLASH_Program_Word(FLASH_Type *FLASHx, uint32_t address, uint32_t data) +{ + uint32_t timeout = 0; + uint32_t primask; + FL_ErrorStatus ret = FL_PASS; + /* 入口参数检查 */ + assert_param(IS_FLASH_ALL_INSTANCE(FLASHx)); + assert_param(IS_FL_FLASH_MAX_ADDR((uint32_t)address)); + /*时钟使能*/ + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_FLASH); + if(address & (FL_FLASH_ADDRS_ALIGN - 1)) + { + /*地址未对齐*/ + return FL_FAIL; + } + if(FL_FLASH_GetFlashLockStatus(FLASHx) == FL_FLASH_KEY_STATUS_ERROR) + { + /*Flash 已经锁定，复位前无法操作*/ + return FL_FAIL; + } + FL_RCC_EnableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_FLASH); + /* 开始编程*/ + FL_FLASH_EnableProgram(FLASHx); + /* Key 序列*/ + primask = __get_PRIMASK(); + __disable_irq(); + FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY1); + FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY2); + __set_PRIMASK(primask); + *((uint32_t *)address) = data; + while(1) + { + timeout++; + if((timeout > FL_FLASH_ERASE_TIMEOUT)\ + || (FL_FLASH_IsActiveFlag_ClockError(FLASHx))\ + || (FL_FLASH_IsActiveFlag_KeyError(FLASHx))\ + || (FL_FLASH_IsActiveFlag_AuthenticationError(FLASHx))) + { + /* 超时或出现错误 */ + ret = FL_FAIL; + break; + } + else + if(FL_FLASH_IsActiveFlag_ProgramComplete(FLASHx)) + { + /*编程成功*/ + FL_FLASH_ClearFlag_ProgramComplete(FLASHx); + ret = FL_PASS; + break; + } + } + FL_FLASH_LockFlash(FLASHx); + FL_RCC_DisableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_FLASH); + FL_RCC_DisableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_FLASH); + return ret; +} + +/** + * @brief 页编程函数，编程地址必须对齐到字边界. + * @param FLASHx 外设入口地址 + * @param PageNum 为需要编程的已经擦除过的扇区号，FM33LC04最大为256，非对齐地址编程将触发fault。 + * @param *data 待写入页数据 + * @retval 错误状态，可能值： + * -FL_FAIL 编程发生错误 + * -FL_PASS 编程成功 + */ +FL_ErrorStatus FL_FLASH_Program_Page(FLASH_Type *FLASHx, uint32_t pageNum, uint32_t *data) +{ + uint32_t count; + uint32_t primask; + uint32_t address; + uint32_t timeout; + FL_ErrorStatus ret; + /* 入口参数检查 */ + assert_param(IS_FLASH_ALL_INSTANCE(FLASHx)); + assert_param(IS_FL_FLASH_MAX_PAGE((uint32_t)pageNum)); + address = pageNum * FL_FLASH_PAGE_SIZE_BYTE; + /* 页对齐*/ + if(address & (FL_FLASH_PAGE_SIZE_BYTE - 1)) + { + /*地址未对齐*/ + return FL_FAIL; + } + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_FLASH); + FL_RCC_EnableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_FLASH); + FL_FLASH_EnableProgram(FLASHx); + /* Key 序列*/ + primask = __get_PRIMASK(); + __disable_irq(); + FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY1); + FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY2); + __set_PRIMASK(primask); + for(count = 0; count < FL_FLASH_PAGE_SIZE_BYTE; count += 4) + { + timeout = 0; + FL_FLASH_EnableProgram(FLASHx); + *((uint32_t *)address) = *data; + address += 4; + data++; + while(1) + { + timeout++; + if((timeout > FL_FLASH_ERASE_TIMEOUT)\ + || (FL_FLASH_IsActiveFlag_ClockError(FLASHx))\ + || (FL_FLASH_IsActiveFlag_KeyError(FLASHx))\ + || (FL_FLASH_IsActiveFlag_AuthenticationError(FLASHx))) + { + /* 超时或出现错误 */ + ret = FL_FAIL; + break; + } + if(FL_FLASH_IsActiveFlag_ProgramComplete(FLASHx)) + { + /*编程成功*/ + FL_FLASH_ClearFlag_ProgramComplete(FLASHx); + ret = FL_PASS; + break; + } + } + if(ret == FL_FAIL) + { + break; + } + } + FL_FLASH_LockFlash(FLASHx); + FL_RCC_DisableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_FLASH); + FL_RCC_DisableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_FLASH); + return ret; +} + +/** + * @brief 扇区编程函数，编程地址必须对齐到字边界. + * @param FLASHx 外设入口地址 + * @param sectorNum 为需要编程的已经擦除过的扇区号，最大为128，非对齐地址编程将触发fault。 + * @param *data 待写入扇区数据 + * @retval 错误状态，可能值： + * -FL_FAIL 编程发生错误 + * -PASS编程成功 + */ +FL_ErrorStatus FL_FLASH_Program_Sector(FLASH_Type *FLASHx, uint32_t sectorNum, uint32_t *data) +{ + uint32_t count; + uint32_t primask; + uint32_t address; + uint32_t timeout; + FL_ErrorStatus ret; + /* 入口参数检查 */ + assert_param(IS_FLASH_ALL_INSTANCE(FLASHx)); + assert_param(IS_FL_FLASH_MAX_SECTOR((uint32_t)sectorNum)); + address = sectorNum * FL_FLASH_SECTOR_SIZE_BYTE; + /* 页对齐*/ + if(address & (FL_FLASH_SECTOR_SIZE_BYTE - 1)) + { + /*地址未对齐*/ + return FL_FAIL; + } + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_FLASH); + FL_RCC_EnableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_FLASH); + FL_FLASH_EnableProgram(FLASHx); + /* Key 序列*/ + primask = __get_PRIMASK(); + __disable_irq(); + FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY1); + FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY2); + __set_PRIMASK(primask); + for(count = 0; count < FL_FLASH_SECTOR_SIZE_BYTE; count += 4) + { + timeout = 0; + FL_FLASH_EnableProgram(FLASHx); + *((uint32_t *)address) = *data; + address += 4; + data++; + while(1) + { + timeout++; + if((timeout > FL_FLASH_ERASE_TIMEOUT)\ + || (FL_FLASH_IsActiveFlag_ClockError(FLASHx))\ + || (FL_FLASH_IsActiveFlag_KeyError(FLASHx))\ + || (FL_FLASH_IsActiveFlag_AuthenticationError(FLASHx))) + { + /* 超时或出现错误 */ + ret = FL_FAIL; + break; + } + if(FL_FLASH_IsActiveFlag_ProgramComplete(FLASHx)) + { + /*编程成功*/ + FL_FLASH_ClearFlag_ProgramComplete(FLASHx); + ret = FL_PASS; + break; + } + } + if(ret == FL_FAIL) + { + break; + } + } + FL_FLASH_LockFlash(FLASHx); + FL_RCC_DisableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_FLASH); + FL_RCC_DisableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_FLASH); + return ret; +} + +/** + * @brief DMA编程函数，编程地址必须对齐到halt-page，长度固定为64字. + * @param FLASHx 外设入口地址 + * @param address 待编程Flash地址 + * @param *data 待写入Flash数据 + * + * @retval 错误状态，可能值： + * -FL_FAIL 编程发生错误 + * -FL_PASS 编程成功 + */ +FL_ErrorStatus FL_FLASH_Write_Dma(FLASH_Type *FLASHx, uint32_t address, uint32_t *data) +{ + FL_ErrorStatus ret; + uint32_t primask; + uint32_t timeout; + FL_DMA_InitTypeDef initStruct = {0}; + /* 入口参数检查 */ + assert_param(IS_FLASH_ALL_INSTANCE(FLASHx)); + assert_param(IS_FL_FLASH_MAX_ADDR(address)); + /* 半页对齐*/ + if(address & (FL_FLASH_PAGE_SIZE_BYTE / 2 - 1)) + { + /*地址未对齐*/ + return FL_FAIL; + } + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_DMA); + FL_DMA_Disable(DMA); + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_FLASH); + FL_RCC_EnableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_FLASH); + FL_FLASH_EnableProgram(FLASHx); + /* Key 序列*/ + primask = __get_PRIMASK(); + __disable_irq(); + FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY1); + FL_FLASH_UnlockFlash(FLASHx, FL_FLASH_PROGRAM_KEY2); + __set_PRIMASK(primask); + FL_FLASH_EnableProgram(FLASHx); + initStruct.circMode = FL_DISABLE; + initStruct.direction = FL_DMA_DIR_RAM_TO_FLASH; + initStruct.memoryAddressIncMode = FL_DMA_CH7_MEMORY_INC_MODE_INCREASE; + initStruct.flashAddressIncMode = FL_DMA_CH7_FLASH_INC_MODE_INCREASE; + initStruct.priority = FL_DMA_PRIORITY_HIGH; + FL_DMA_Init(DMA, &initStruct, FL_DMA_CHANNEL_7); + FL_DMA_WriteFlashAddress(DMA, address >> 2); + FL_DMA_WriteMemoryAddress(DMA, (uint32_t)data >> 2, FL_DMA_CHANNEL_7); + FL_DMA_WriteTransmissionSize(DMA, 64 - 1, FL_DMA_CHANNEL_7); + FL_DMA_ClearFlag_TransferComplete(DMA, FL_DMA_CHANNEL_7); + FL_DMA_EnableChannel(DMA, FL_DMA_CHANNEL_7); + FL_DMA_Enable(DMA); + timeout = 0; + while(1) + { + timeout++; + if(timeout > FL_FLASH_ERASE_TIMEOUT) + { + ret = FL_FAIL; + break; + } + if(FL_DMA_IsActiveFlag_TransferComplete(DMA, FL_DMA_CHANNEL_7) == FL_SET) + { + ret = FL_PASS; + break; + } + } + FL_DMA_Disable(DMA); + FL_FLASH_LockFlash(FLASHx); + FL_RCC_DisableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_FLASH); + FL_RCC_DisableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_FLASH); + return ret; +} + +/** + * @brief DMA读取函数，编程地址必须对齐到halt-page. + * @param FLASHx 外设入口地址 + * @param address 读取数据Flash地址 + * @param *data 读出数据存储区 + * @param length 读出数据的字长度 + * + * @retval 错误状态，可能值： + * -FL_FAIL 读取发生错误 + * -FL_PASS 读取成功 + */ +FL_ErrorStatus FL_FLASH_Read_Dma(FLASH_Type *FLASHx, uint32_t address, uint32_t *data, uint16_t length) +{ + FL_ErrorStatus ret; + uint32_t Timeout; + FL_DMA_InitTypeDef initStruct = {0}; + /* 入口参数检查 */ + assert_param(IS_FLASH_ALL_INSTANCE(FLASHx)); + assert_param(IS_FL_FLASH_MAX_ADDR(address)); + /* 半页对齐*/ + if(address & (FL_FLASH_PAGE_SIZE_BYTE / 2 - 1)) + { + /*地址未对齐*/ + return FL_FAIL; + } + initStruct.circMode = FL_DISABLE; + initStruct.direction = FL_DMA_DIR_FLASH_TO_RAM; + initStruct.memoryAddressIncMode = FL_DMA_CH7_MEMORY_INC_MODE_INCREASE; + initStruct.flashAddressIncMode = FL_DMA_CH7_FLASH_INC_MODE_INCREASE; + initStruct.priority = FL_DMA_PRIORITY_HIGH; + FL_DMA_Init(DMA, &initStruct, FL_DMA_CHANNEL_7); + FL_DMA_WriteFlashAddress(DMA, address >> 2); + FL_DMA_WriteMemoryAddress(DMA, (uint32_t)data >> 2, FL_DMA_CHANNEL_7); + FL_DMA_WriteTransmissionSize(DMA, length - 1, FL_DMA_CHANNEL_7); + FL_DMA_ClearFlag_TransferComplete(DMA, FL_DMA_CHANNEL_7); + FL_DMA_EnableChannel(DMA, FL_DMA_CHANNEL_7); + FL_DMA_Enable(DMA); + Timeout = 0; + while(1) + { + Timeout++; + if(Timeout > FL_FLASH_ERASE_TIMEOUT) + { + ret = FL_FAIL; + break; + } + if(FL_DMA_IsActiveFlag_TransferComplete(DMA, FL_DMA_CHANNEL_7) == FL_SET) + { + ret = FL_PASS; + break; + } + } + return ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/*************************************************************END OF FILE************************************************************/ + + + + + + + + + diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_gpio.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_gpio.c new file mode 100644 index 0000000000..7001c08410 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_gpio.c @@ -0,0 +1,318 @@ +/** + **************************************************************************************************** + * @file fm33lC0xx_fl_gpio.c + * @author FMSH Application Team + * @brief Src file of GPIO FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_gpio.h" +#include "fm33lc0xx_fl_rcc.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_FL_Private_Macros + * @{ + */ + +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA)||\ + ((INSTANCE) == GPIOB)||\ + ((INSTANCE) == GPIOC)||\ + ((INSTANCE) == GPIOD)) + +#define IS_FL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) &&\ + ((__VALUE__) <= (FL_GPIO_PIN_ALL))) + +#define IS_FL_GPIO_MODE(__VALUE__) (((__VALUE__) == FL_GPIO_MODE_ANALOG)||\ + ((__VALUE__) == FL_GPIO_MODE_INPUT)||\ + ((__VALUE__) == FL_GPIO_MODE_OUTPUT)||\ + ((__VALUE__) == FL_GPIO_MODE_DIGITAL)) + +#define IS_FL_GPIO_OPENDRAIN(__VALUE__) (((__VALUE__) == FL_GPIO_OUTPUT_OPENDRAIN)||\ + ((__VALUE__) == FL_GPIO_OUTPUT_PUSHPULL)) + +#define IS_FL_GPIO_PULL_UP(__VALUE__) (((__VALUE__) == FL_DISABLE)||\ + ((__VALUE__) == FL_ENABLE)) + + +#define IS_FL_GPIO_WKUP_ENTRY(__VALUE__) (((__VALUE__) == FL_GPIO_WAKEUP_INT_ENTRY_NMI)||\ + ((__VALUE__) == FL_GPIO_WAKEUP_INT_ENTRY_38)) + +#define IS_FL_GPIO_WKUP_EDGE(__VALUE__) (((__VALUE__) == FL_GPIO_WAKEUP_TRIGGER_RISING)||\ + ((__VALUE__) == FL_GPIO_WAKEUP_TRIGGER_FALLING)) + + +#define IS_FL_GPIO_WKUP_NUM(__VALUE__) (((__VALUE__) == FL_GPIO_WAKEUP_0)||\ + ((__VALUE__) == FL_GPIO_WAKEUP_1)||\ + ((__VALUE__) == FL_GPIO_WAKEUP_2)||\ + ((__VALUE__) == FL_GPIO_WAKEUP_3)||\ + ((__VALUE__) == FL_GPIO_WAKEUP_4)||\ + ((__VALUE__) == FL_GPIO_WAKEUP_5)||\ + ((__VALUE__) == FL_GPIO_WAKEUP_6)||\ + ((__VALUE__) == FL_GPIO_WAKEUP_7)) +/** + * @} + */ + +/** @addtogroup GPIO_FL_EF_Init + * @{ + */ + +/** + * @brief 复位GPIO外设 + * @param GPIOx 外设入口地址 + * @param pin 引脚 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_GPIO_DeInit(GPIO_Type *GPIOx, uint32_t pin) +{ + uint32_t pinPos = 0x00000000U; + uint32_t currentPin = 0x00000000U; + /* 入口参数检查 */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_FL_GPIO_PIN(pin)); + /* 恢复寄存器值为默认值 */ + while(((pin) >> pinPos) != 0x00000000U) + { + /* 获取当前遍历到的Pin脚 */ + currentPin = (pin) & (0x00000001U << pinPos); + if(currentPin) + { + FL_GPIO_SetPinMode(GPIOx, currentPin, FL_GPIO_MODE_INPUT); + FL_GPIO_DisablePinInput(GPIOx, currentPin); + FL_GPIO_DisablePinOpenDrain(GPIOx, currentPin); + FL_GPIO_DisablePinPullup(GPIOx, currentPin); + FL_GPIO_DisablePinAnalogSwitch(GPIOx, currentPin); + FL_GPIO_DisablePinRemap(GPIOx, currentPin); + } + pinPos++; + } + return FL_PASS; +} + +/** + * @brief 根据 GPIO_InitStruct 的配置信息初始化对应外设. + * @param GPIOx GPIO Port + * @param GPIO_InitStruct 指向一个 @ref FL_GPIO_InitTypeDef 结构体 + * 其中包含了外设的相关配置信息. + * @retval 错误状态，可能值： + * -FL_FAIL 配置过程发生错误 + * -FL_PASS 配置成功 + */ +FL_ErrorStatus FL_GPIO_Init(GPIO_Type *GPIOx, FL_GPIO_InitTypeDef *initStruct) +{ + uint32_t pinPos = 0x00000000U; + uint32_t currentPin = 0x00000000U; + /* 入口参数检查 */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_FL_GPIO_PIN(initStruct->pin)); + assert_param(IS_FL_GPIO_MODE(initStruct->mode)); + assert_param(IS_FL_GPIO_OPENDRAIN(initStruct->outputType)); + assert_param(IS_FL_GPIO_PULL_UP(initStruct->pull)); + /* 使能时钟总线 */ + FL_RCC_EnableGroup1BusClock(FL_RCC_GROUP1_BUSCLK_PAD); + /* 这里考虑到PIN有可能不止一个因此需要遍历 */ + while(((initStruct->pin) >> pinPos) != 0x00000000U) + { + /* 获取当前遍历到的Pin脚 */ + currentPin = (initStruct->pin) & (0x00000001U << pinPos); + if(currentPin) + { + /* Pin脚模拟模式设置 */ + if(initStruct->mode == FL_GPIO_MODE_ANALOG) + { + FL_GPIO_DisablePinInput(GPIOx, currentPin); + FL_GPIO_DisablePinPullup(GPIOx, currentPin); + FL_GPIO_DisablePinOpenDrain(GPIOx, currentPin); + FL_GPIO_EnablePinAnalogSwitch(GPIOx, currentPin); + } + else + { + FL_GPIO_DisablePinAnalogSwitch(GPIOx, currentPin); + /* Pin脚输入使能控制 */ + if(initStruct->mode == FL_GPIO_MODE_INPUT) + { + FL_GPIO_EnablePinInput(GPIOx, currentPin); + } + else + { + FL_GPIO_DisablePinInput(GPIOx, currentPin); + } + /* Pin脚输出模式设置 */ + if(initStruct->outputType == FL_GPIO_OUTPUT_PUSHPULL) + { + FL_GPIO_DisablePinOpenDrain(GPIOx, currentPin); + } + else + { + FL_GPIO_EnablePinOpenDrain(GPIOx, currentPin); + } + /* Pin脚上拉模式设置 */ + if(initStruct->pull) + { + FL_GPIO_EnablePinPullup(GPIOx, currentPin); + } + else + { + FL_GPIO_DisablePinPullup(GPIOx, currentPin); + } + } + /* 数字模式复用功能选择 */ + if(initStruct->mode == FL_GPIO_MODE_DIGITAL) + { + /*重定向*/ + if(initStruct->remapPin == FL_ENABLE) + { + FL_GPIO_EnablePinRemap(GPIOx, currentPin); + } + else + { + FL_GPIO_DisablePinRemap(GPIOx, currentPin); + } + } + /* Pin脚工作模式设置 */ + FL_GPIO_SetPinMode(GPIOx, currentPin, initStruct->mode); + } + pinPos++; + } + return FL_PASS; +} + +/** + * @brief 将 @ref FL_GPIO_InitTypeDef 结构体初始化为默认配置 + * @param initStruct 指向 @ref FL_GPIO_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_GPIO_StructInit(FL_GPIO_InitTypeDef *initStruct) +{ + /* 复位配置信息 */ + initStruct->pin = FL_GPIO_PIN_ALL; + initStruct->mode = FL_GPIO_MODE_INPUT; + initStruct->outputType = FL_GPIO_OUTPUT_OPENDRAIN; + initStruct->pull = FL_DISABLE; + initStruct->remapPin = FL_DISABLE; +} + +/** + * @brief 根据 FL_WKUP_InitTypeDef 配置GPIO唤醒对应外设 + * @param initStruct 指向一个 @ref FL_WKUP_InitTypeDef 结构体 + * 其中包含了外设的相关配置信息. + * @param wakeup 唤醒入口 + * FL_GPIO_WAKEUP_0 + * FL_GPIO_WAKEUP_1 + * FL_GPIO_WAKEUP_2 + * FL_GPIO_WAKEUP_3 + * FL_GPIO_WAKEUP_4 + * FL_GPIO_WAKEUP_5 + * FL_GPIO_WAKEUP_6 + * FL_GPIO_WAKEUP_7 + * @retval 错误状态，可能值： + * -FL_FAIL 配置过程发生错误 + * -FL_PASS 配置成功 + */ +FL_ErrorStatus FL_WKUP_Init(FL_WKUP_InitTypeDef *initStruct, uint32_t wakeup) +{ + /* 入口参数检查 */ + assert_param(IS_FL_GPIO_WKUP_NUM(wakeup)); + assert_param(IS_FL_GPIO_WKUP_EDGE(initStruct->polarity)); + FL_GPIO_EnableWakeup(GPIO, wakeup); + FL_GPIO_SetWakeupEdge(GPIO, wakeup, initStruct->polarity); + return FL_PASS; +} + +/** + * @brief 去初始化Wakeup配置 + * @param Wkupx 唤醒入口 + * FL_GPIO_WKUP_0 + * FL_GPIO_WKUP_1 + * FL_GPIO_WKUP_2 + * FL_GPIO_WKUP_3 + * FL_GPIO_WKUP_4 + * FL_GPIO_WKUP_5 + * FL_GPIO_WKUP_6 + * FL_GPIO_WKUP_7 + * @retval 错误状态，可能值： + * -FL_FAIL 配置过程发生错误 + * -FL_PASS 配置成功 + */ +FL_ErrorStatus FL_WKUP_DeInit(uint32_t wkupx) +{ + /* 入口参数检查 */ + assert_param(IS_FL_GPIO_WKUP_NUM(wkupx)); + FL_GPIO_EnableWakeup(GPIO, wkupx); + return FL_PASS; +} + +/** + * @brief 将 @ref FL_WKUP_InitTypeDef 结构体初始化为默认配置 + * @param initStruct_Wakeup 指向需要将值设置为默认配置的结构体 @ref FL_WKUP_InitTypeDef 结构体 + * + * @retval None + */ +void FL_WKUP_StructInit(FL_WKUP_InitTypeDef *initStruct_Wakeup) +{ + /* 复位配置信息 */ + initStruct_Wakeup->polarity = FL_GPIO_WAKEUP_TRIGGER_FALLING; +} + +/** + *@} + */ + +/** @addtogroup RNG_FL_EF_Operation + * @{ + */ + +/** + * @brief 设置所有GPIO为输入模式、输入使能关闭（高阻态），SWD接口除外。 + * @note PD7和PD8为调试接口 + * + * @param None + * + * @retval None + */ +void FL_GPIO_ALLPIN_LPM_MODE(void) +{ + FL_GPIO_DeInit(GPIOA, FL_GPIO_PIN_ALL); + FL_GPIO_DeInit(GPIOB, FL_GPIO_PIN_ALL); + FL_GPIO_DeInit(GPIOC, FL_GPIO_PIN_ALL); + FL_GPIO_DeInit(GPIOD, FL_GPIO_PIN_ALL_EXCEPTSWD); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/*************************************************************END OF FILE************************************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_gptim.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_gptim.c new file mode 100644 index 0000000000..4f52ea1d0a --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_gptim.c @@ -0,0 +1,617 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_gptim.c + * @author FMSH Application Team + * @brief Src file of GPTIM FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_rmu.h" +#include "fm33lc0xx_fl_gptim.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup GPTIM + * @{ + */ + +/* Private macros ------------------------------------------------------------------*/ +/** @addtogroup GPTIM_FL_Private_Macros + * @{ + */ + + +#define IS_GPTIM_INSTANCE(TIMx) (((TIMx) == GPTIM0) || \ + ((TIMx) == GPTIM1)) + + +#define IS_FL_GPTIM_COUNTERMODE(__VALUE__) (((__VALUE__) == FL_GPTIM_COUNTER_DIR_UP) || \ + ((__VALUE__) == FL_GPTIM_COUNTER_DIR_DOWN) || \ + ((__VALUE__) == FL_GPTIM_COUNTER_ALIGNED_EDGE) || \ + ((__VALUE__) == FL_GPTIM_COUNTER_ALIGNED_CENTER_UP) || \ + ((__VALUE__) == FL_GPTIM_COUNTER_ALIGNED_CENTER_DOWN) || \ + ((__VALUE__) == FL_GPTIM_COUNTER_ALIGNED_CENTER_UP_DOWN)) + +#define IS_FL_GPTIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == FL_GPTIM_CLK_DIVISION_DIV1) || \ + ((__VALUE__) == FL_GPTIM_CLK_DIVISION_DIV2) || \ + ((__VALUE__) == FL_GPTIM_CLK_DIVISION_DIV4)) + + +#define IS_FL_GPTIM_CHANNEL_MODE(__VALUE__) (((__VALUE__) == FL_GPTIM_CHANNEL_MODE_OUTPUT) || \ + ((__VALUE__) == FL_GPTIM_CHANNEL_MODE_INPUT_NORMAL) || \ + ((__VALUE__) == FL_GPTIM_CHANNEL_MODE_INPUT_CROSSOVER) || \ + ((__VALUE__) == FL_GPTIM_CHANNEL_MODE_INPUT_TRC)) + +#define IS_FL_GPTIM_IC_FILTER(__VALUE__) (((__VALUE__) == FL_GPTIM_IC_FILTER_DIV1) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV1_N2) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV1_N4) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV1_N8) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV2_N6) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV2_N8) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV4_N6) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV4_N8) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV8_N6) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV8_N8) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV16_N5) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV16_N6) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV16_N8) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV32_N5) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV32_N6) || \ + ((__VALUE__) == FL_GPTIM_IC_FILTER_DIV32_N8)) + +#define IS_FL_GPTIM_CHANNEL(__VALUE__) (((__VALUE__) == FL_GPTIM_CHANNEL_1)\ + || ((__VALUE__) == FL_GPTIM_CHANNEL_2)\ + || ((__VALUE__) == FL_GPTIM_CHANNEL_3)\ + || ((__VALUE__) == FL_GPTIM_CHANNEL_4)) + + + +#define IS_FL_GPTIM_SLAVE_MODE(__VALUE__) (((__VALUE__) == FL_GPTIM_SLAVE_MODE_PROHIBITED)\ + || ((__VALUE__) == FL_GPTIM_SLAVE_MODE_ENCODER_X2_TI1)\ + || ((__VALUE__) == FL_GPTIM_SLAVE_MODE_ENCODER_X2_TI2)\ + || ((__VALUE__) == FL_GPTIM_SLAVE_MODE_ENCODER_X4_TI1TI2)\ + || ((__VALUE__) == FL_GPTIM_SLAVE_MODE_TRGI_RISE_RST)\ + || ((__VALUE__) == FL_GPTIM_SLAVE_MODE_TRGI_HIGH_RUN)\ + || ((__VALUE__) == FL_GPTIM_SLAVE_MODE_TRGI_RISE_RUN)\ + || ((__VALUE__) == FL_GPTIM_SLAVE_MODE_TRGI_CLK)) + + +#define IS_FL_GPTIM_TRIGGER_SRC(__VALUE__) (((__VALUE__) ==FL_GPTIM_TIM_TS_ITR0 )\ + ||((__VALUE__) ==FL_GPTIM_TIM_TS_ITR1 )\ + ||((__VALUE__) ==FL_GPTIM_TIM_TS_ITR2)\ + ||((__VALUE__) ==FL_GPTIM_TIM_TS_ITR3)\ + ||((__VALUE__) ==FL_GPTIM_TIM_TS_TI1F_ED)\ + ||((__VALUE__) ==FL_GPTIM_TIM_TS_TI1FP1)\ + ||((__VALUE__) ==FL_GPTIM_TIM_TS_TI2FP2)\ + ||((__VALUE__) ==FL_GPTIM_TIM_TS_ETRF)) + + + +#define IS_FL_GPTIM_ETR_FILTER(__VALUE__) (((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV1) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV1_N2) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV1_N4) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV1_N8) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV2_N6) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV2_N8) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV4_N6) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV4_N8) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV8_N6) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV8_N8) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV16_N5) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV16_N6) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV16_N8) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV32_N5) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV32_N6) || \ + ((__VALUE__) == FL_GPTIM_ETR_FILTER_DIV32_N8)) + + +#define IS_FL_GPTIM_ETR_PSC(__VALUE__) (((__VALUE__) == FL_GPTIM_ETR_PSC_DIV1) ||\ + ((__VALUE__) == FL_GPTIM_ETR_PSC_DIV2) ||\ + ((__VALUE__) == FL_GPTIM_ETR_PSC_DIV4) ||\ + ((__VALUE__) == FL_GPTIM_ETR_PSC_DIV8)) + +#define IS_FL_GPTIM_ETR_POLARITY(__VALUE__) (((__VALUE__) == FL_GPTIM_ETR_POLARITY_NORMAL) || \ + ((__VALUE__) == FL_GPTIM_ETR_POLARITY_INVERT)) + + + +#define IS_FL_GPTIM_IC_POLARITY(__VALUE__) (((__VALUE__) == FL_GPTIM_IC_POLARITY_NORMAL) \ + || ((__VALUE__) == FL_GPTIM_IC_POLARITY_INVERT)) + + + +#define IS_FL_GPTIM_IC_PSC(__VALUE__) (((__VALUE__) == FL_GPTIM_IC_PSC_DIV1) \ + || ((__VALUE__) == FL_GPTIM_IC_PSC_DIV2) \ + || ((__VALUE__) == FL_GPTIM_IC_PSC_DIV4) \ + || ((__VALUE__) == FL_GPTIM_IC_PSC_DIV8)) + +#define IS_FL_GPTIM_OC_POLARITY(__VALUE__) (((__VALUE__) == FL_GPTIM_OC_POLARITY_NORMAL) \ + || ((__VALUE__) == FL_GPTIM_OC_POLARITY_INVERT)) + +#define IS_FL_GPTIM_OC_MODE(__VALUE__) (((__VALUE__) == FL_GPTIM_OC_MODE_FROZEN) \ + || ((__VALUE__) == FL_GPTIM_OC_MODE_ACTIVE) \ + || ((__VALUE__) == FL_GPTIM_OC_MODE_INACTIVE) \ + || ((__VALUE__) == FL_GPTIM_OC_MODE_TOGGLE) \ + || ((__VALUE__) == FL_GPTIM_OC_MODE_FORCED_INACTIVE) \ + || ((__VALUE__) == FL_GPTIM_OC_MODE_FORCED_ACTIVE) \ + || ((__VALUE__) == FL_GPTIM_OC_MODE_PWM1) \ + || ((__VALUE__) == FL_GPTIM_OC_MODE_PWM2)) + +#define IS_FL_GPTIM_OC_FASTMODE(__VALUE__) (((__VALUE__) == FL_ENABLE) \ + || ((__VALUE__) == FL_DISABLE)) + +#define IS_FL_GPTIM_OC_PRELOAD(__VALUE__) (((__VALUE__) == FL_ENABLE) \ + || ((__VALUE__) == FL_DISABLE)) + +#define IS_FL_GPTIM_OC_ETR_CLEARN(__VALUE__) (((__VALUE__) == FL_ENABLE) \ + || ((__VALUE__) == FL_DISABLE)) + + +#define IS_FL_GPTIM_TRIGGER_DELAY(__VALUE__) (((__VALUE__) == FL_DISABLE) \ + || ((__VALUE__) == FL_ENABLE)) + + +#define IS_FL_GPTIM_IC_CAPTURE_STATE(__VALUE__) (((__VALUE__) == FL_DISABLE) \ + || ((__VALUE__) == FL_ENABLE)) +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup GPTIM_FL_Private_Functions GPTIM Private Functions + * @{ + */ +static FL_ErrorStatus OCConfig(GPTIM_Type *TIMx, uint32_t Channel, FL_GPTIM_OC_InitTypeDef *TIM_OC_InitStruct); + +/** + * @} + */ + +/** @addtogroup GPTIM_FL_EF_Init + * @{ + */ + +/** + * @brief 复位GPTIM外设 + * @param TIMx 外设入口地址 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_GPTIM_DeInit(GPTIM_Type *TIMx) +{ + FL_ErrorStatus result = FL_PASS; + /* Check the parameters */ + assert_param(IS_GPTIM_INSTANCE(TIMx)); + /* 使能外设复位 */ + FL_RCC_EnablePeripheralReset(); + if(TIMx == GPTIM0) + { + /* 使能外设复位 */ + FL_RCC_EnableResetAPB1Peripheral(FL_RCC_RSTAPB_GPTIM0); + FL_RCC_DisableResetAPB1Peripheral(FL_RCC_RSTAPB_GPTIM0); + /* 关闭外设时钟 */ + FL_RCC_DisableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_GPTIM0); + } + else + if(TIMx == GPTIM1) + { + /* 使能外设复位 */ + FL_RCC_EnableResetAPB1Peripheral(FL_RCC_RSTAPB_GPTIM1); + FL_RCC_DisableResetAPB1Peripheral(FL_RCC_RSTAPB_GPTIM1); + /* 关闭外设时钟 */ + FL_RCC_DisableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_GPTIM1); + } + else + { + result = FL_FAIL; + } + /* 锁定外设复位 */ + FL_RCC_DisablePeripheralReset(); + return result; +} + +/** + * @brief 配置GPTIM基本定时器时基单元（内部时钟源） + * @param TIMx 外设入口地址 + * @param init 指向 @ref FL_GPTIM_InitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_GPTIM_Init(GPTIM_Type *TIMx, FL_GPTIM_InitTypeDef *init) +{ + uint32_t i = 5; + /* 参数检查 */ + assert_param(IS_GPTIM_INSTANCE(TIMx)); + assert_param(IS_FL_GPTIM_COUNTERMODE(init->counterMode)); + assert_param(IS_FL_GPTIM_CLOCKDIVISION(init->clockDivision)); + /* 时钟总线使能配置 */ + if(TIMx == GPTIM0) + { + FL_RCC_EnableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_GPTIM0); + } + else + if(TIMx == GPTIM1) + { + FL_RCC_EnableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_GPTIM1); + } + /* 计数器计数模式配置 */ + switch(init->counterMode) + { + /* 中心对称模式 */ + case FL_GPTIM_COUNTER_ALIGNED_CENTER_DOWN : + case FL_GPTIM_COUNTER_ALIGNED_CENTER_UP : + case FL_GPTIM_COUNTER_ALIGNED_CENTER_UP_DOWN: + FL_GPTIM_SetCounterAlignedMode(TIMx, init->counterMode); + break; + default: + /* 边沿模式 */ + FL_GPTIM_SetCounterDirection(TIMx, init->counterMode); + FL_GPTIM_SetCounterAlignedMode(TIMx, FL_GPTIM_COUNTER_ALIGNED_EDGE); + break; + } + /* 自动重装载值 */ + FL_GPTIM_WriteAutoReload(TIMx, init->autoReload); + /* 定时器分频系数与数字滤波器所使用的采样时钟分频比 */ + FL_GPTIM_SetClockDivision(TIMx, init->clockDivision); + /* 时钟分频 */ + FL_GPTIM_WritePrescaler(TIMx, init->prescaler); + /* 预装载配置 */ + if(init->autoReloadState == FL_ENABLE) + { + FL_GPTIM_EnableARRPreload(TIMx); + } + else + { + FL_GPTIM_DisableARRPreload(TIMx); + } + /* 手动触发更新事件，将配置值写入 */ + FL_GPTIM_GenerateUpdateEvent(TIMx); + while((!FL_GPTIM_IsActiveFlag_Update(TIMx))&i) + { + i--; + } + /*清除UIF标志，防止产生UG事件中断*/ + FL_GPTIM_ClearFlag_Update(TIMx); + return FL_PASS; +} + +/** + * @brief 将 @ref FL_GPTIM_InitTypeDef 结构体初始化为默认配置 + * @param TIM_InitStruct 指向 @ref FL_GPTIM_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_GPTIM_StructInit(FL_GPTIM_InitTypeDef *TIM_InitStruct) +{ + /* Set the default configuration */ + TIM_InitStruct->prescaler = (uint16_t)0x0000; + TIM_InitStruct->autoReloadState = FL_DISABLE; + TIM_InitStruct->counterMode = FL_GPTIM_COUNTER_DIR_UP; + TIM_InitStruct->autoReload = 0xFFFFU; + TIM_InitStruct->clockDivision = FL_GPTIM_CLK_DIVISION_DIV1; +} + +/** + * @brief 配置GPTIM基本定时器外部时钟源模式，包括编码器模式. + * @param TIMx 外设入口地址 + * @param slave_init 指向 @ref FL_GPTIM_SlaveInitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_GPTIM_SlaveMode_Init(GPTIM_Type *TIMx, FL_GPTIM_SlaveInitTypeDef *slave_init) +{ + /* 参数检查 */ + assert_param(IS_GPTIM_INSTANCE(TIMx)); + assert_param(IS_FL_GPTIM_SLAVE_MODE(slave_init->slaveMode)); + assert_param(IS_FL_GPTIM_TRIGGER_SRC(slave_init->triggerSrc)); + assert_param(IS_FL_GPTIM_TRIGGER_DELAY(slave_init->triggerDelay)); + /* 时钟总线使能配置 */ + if(TIMx == GPTIM0) + { + FL_RCC_EnableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_GPTIM0); + } + else + if(TIMx == GPTIM1) + { + FL_RCC_EnableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_GPTIM1); + } + /* 触发延迟默认关闭 */ + FL_GPTIM_DisableMasterSlaveMode(TIMx); + /* 关闭从模式以能写入TS */ + FL_GPTIM_SetSlaveMode(TIMx, 0); + /* 从模式输入源选择 */ + FL_GPTIM_SetTriggerInput(TIMx, slave_init->triggerSrc); + /* ITRx 输入源选择 */ + if(slave_init->triggerSrc <= FL_GPTIM_TIM_TS_ITR3) + { + /* 内部触发ITRx源选择 */ + FL_GPTIM_SetITRInput(TIMx, (1U << (slave_init->triggerSrc >> GPTIM_SMCR_TS_Pos)), slave_init->ITRSourceGroup); + } + /* 从模式选择 */ + FL_GPTIM_SetSlaveMode(TIMx, slave_init->slaveMode); + /* 触发延迟默认关闭 */ + if(slave_init->triggerDelay == FL_ENABLE) + { + FL_GPTIM_EnableMasterSlaveMode(TIMx); + } + return FL_PASS; +} + +/** + * @brief 将 @ref FL_GPTIM_SlaveInitTypeDef 结构体初始化为默认配置 + * @param slave_init 指向 @ref FL_GPTIM_SlaveInitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_GPTIM_SlaveMode_StructInit(FL_GPTIM_SlaveInitTypeDef *slave_init) +{ + slave_init->ITRSourceGroup = 0; + slave_init->slaveMode = FL_GPTIM_SLAVE_MODE_PROHIBITED; + slave_init->triggerSrc = FL_GPTIM_TIM_TS_TI1FP1; + slave_init->triggerDelay = FL_DISABLE; +} + +/** + * @brief 配置GPTIM触发输入捕获通道ETR. + * @param TIMx 外设入口地址 + * @param etr_init 指向 @ref FL_GPTIM_ETR_InitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_GPTIM_ETR_Init(GPTIM_Type *TIMx, FL_GPTIM_ETR_InitTypeDef *etr_init) +{ + assert_param(IS_FL_GPTIM_ETR_FILTER(etr_init->ETRFilter)); + assert_param(IS_FL_GPTIM_ETR_PSC(etr_init->ETRClockDivision)); + assert_param(IS_FL_GPTIM_ETR_POLARITY(etr_init->ETRPolarity)); + /* 时钟总线使能配置 */ + if(TIMx == GPTIM0) + { + FL_RCC_EnableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_GPTIM0); + } + else + if(TIMx == GPTIM1) + { + FL_RCC_EnableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_GPTIM1); + } + /* 外部时钟极性 */ + FL_GPTIM_SetETRPolarity(TIMx, etr_init->ETRPolarity); + /* 外部时钟滤波 */ + FL_GPTIM_SetETRFilter(TIMx, etr_init->ETRFilter); + /* 外部时钟分频 */ + FL_GPTIM_SetETRPrescaler(TIMx, etr_init->ETRClockDivision); + if(etr_init->useExternalTrigger == FL_ENABLE) + { + FL_GPTIM_EnableExternalClock(TIMx); + } + else + { + FL_GPTIM_DisableExternalClock(TIMx); + } + return FL_PASS; +} + +/** + * @brief 将 @ref FL_GPTIM_ETR_InitTypeDef 结构体初始化为默认配置 + * @param etr_init 指向 @ref FL_GPTIM_ETR_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_GPTIM_ETR_StructInit(FL_GPTIM_ETR_InitTypeDef *etr_init) +{ + etr_init->useExternalTrigger = FL_DISABLE; + etr_init->ETRFilter = FL_GPTIM_ETR_FILTER_DIV1; + etr_init->ETRPolarity = FL_GPTIM_ETR_POLARITY_NORMAL; + etr_init->ETRClockDivision = FL_GPTIM_ETR_PSC_DIV1; +} + +/** + * @brief 配置GPTIM的比较输出通道. + * @param TIMx 外设入口地址 + * @param channel GPTIM通道 + * 此参数可取以下值： + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @param oc_init 指向 @ref FL_GPTIM_OC_InitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_GPTIM_OC_Init(GPTIM_Type *TIMx, uint32_t channel, FL_GPTIM_OC_InitTypeDef *oc_init) +{ + FL_ErrorStatus result = FL_PASS; + /* 参数检查 */ + assert_param(IS_GPTIM_INSTANCE(TIMx)); + assert_param(IS_FL_GPTIM_OC_MODE(oc_init->OCMode)); + assert_param(IS_FL_GPTIM_OC_PRELOAD(oc_init->OCPreload)); + assert_param(IS_FL_GPTIM_OC_POLARITY(oc_init->OCPolarity)); + assert_param(IS_FL_GPTIM_OC_FASTMODE(oc_init->OCFastMode)); + assert_param(IS_FL_GPTIM_OC_ETR_CLEARN(oc_init->OCETRFStatus)); + /* 通道关闭 */ + FL_GPTIM_OC_DisableChannel(TIMx, channel); + /* 通道极性 */ + FL_GPTIM_OC_SetChannelPolarity(TIMx, oc_init->OCPolarity, channel); + /* 捕获映射到输出通道 */ + FL_GPTIM_CC_SetChannelMode(TIMx, FL_GPTIM_CHANNEL_MODE_OUTPUT, channel); + /* 输出比较模式寄存器配置 */ + OCConfig(TIMx, channel, oc_init); + /* 通道使能 */ + FL_GPTIM_OC_EnableChannel(TIMx, channel); + return result; +} + +/** + * @brief 配置输出通道 + * @param TIMx 外设入口地址 + * @param channel GPTIM通道 + * 此参数可取以下值： + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @param oc_init 指向 @ref FL_GPTIM_OC_InitTypeDef 结构体的指针. + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +static FL_ErrorStatus OCConfig(GPTIM_Type *TIMx, uint32_t channel, FL_GPTIM_OC_InitTypeDef *oc_init) +{ + FL_ErrorStatus result = FL_PASS; + /* 配置比较输出通道模式 */ + FL_GPTIM_OC_SetMode(TIMx, oc_init->OCMode, channel); + /* 配置ETRF清零使能 */ + if(oc_init->OCETRFStatus == FL_ENABLE) + { + FL_GPTIM_OC_EnableClear(TIMx, channel); + } + /* 比较输出通道快速模式 */ + if(oc_init->OCFastMode == FL_ENABLE) + { + FL_GPTIM_OC_EnableFastMode(TIMx, channel); + } + /* 比较输出通道缓冲模式 */ + if(oc_init->OCPreload == FL_ENABLE) + { + FL_GPTIM_OC_EnablePreload(TIMx, channel); + } + /* 设置比较值 */ + switch(channel) + { + case FL_GPTIM_CHANNEL_1: + FL_GPTIM_WriteCompareCH1(TIMx, oc_init->compareValue); + break; + case FL_GPTIM_CHANNEL_2: + FL_GPTIM_WriteCompareCH2(TIMx, oc_init->compareValue); + break; + case FL_GPTIM_CHANNEL_3: + FL_GPTIM_WriteCompareCH3(TIMx, oc_init->compareValue); + break; + case FL_GPTIM_CHANNEL_4: + FL_GPTIM_WriteCompareCH4(TIMx, oc_init->compareValue); + break; + default : + result = FL_FAIL; + break; + } + return result; +} + +/** + * @brief 将 @ref FL_GPTIM_OC_InitTypeDef 结构体初始化为默认配置 + * @param oc_init 指向 @ref FL_GPTIM_OC_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_GPTIM_OC_StructInit(FL_GPTIM_OC_InitTypeDef *oc_init) +{ + /* Set the default configuration */ + oc_init->OCMode = FL_GPTIM_OC_MODE_FROZEN; + oc_init->OCETRFStatus = FL_DISABLE; + oc_init->OCFastMode = FL_DISABLE; + oc_init->compareValue = 0x00000000U; + oc_init->OCPolarity = FL_GPTIM_OC_POLARITY_NORMAL; + oc_init->OCPreload = FL_DISABLE; +} + +/** + * @brief 配置GPTIM的输入捕获通道. + * @param TIMx 外设入口地址 + * @param channel GPTIM通道 + * 此参数可取以下值： + * @arg @ref FL_GPTIM_CHANNEL_1 + * @arg @ref FL_GPTIM_CHANNEL_2 + * @arg @ref FL_GPTIM_CHANNEL_3 + * @arg @ref FL_GPTIM_CHANNEL_4 + * @param ic_init 指向 @ref FL_GPTIM_IC_InitTypeDef 结构体的指针 + * @retval ErrorStatus枚举值 + * -FL_FAIL 配置过程发生错误 + * -FL_PASS 成功 + */ +FL_ErrorStatus FL_GPTIM_IC_Init(GPTIM_Type *TIMx, uint32_t channel, FL_GPTIM_IC_InitTypeDef *ic_init) +{ + FL_ErrorStatus result = FL_PASS; + /* 参数检查 */ + assert_param(IS_FL_GPTIM_CHANNEL(channel)); + assert_param(IS_FL_GPTIM_IC_CAPTURE_STATE(ic_init->captureState)); + assert_param(IS_FL_GPTIM_IC_POLARITY(ic_init->ICPolarity)); + assert_param(IS_FL_GPTIM_CHANNEL_MODE(ic_init->ICActiveInput)); + assert_param(IS_FL_GPTIM_IC_PSC(ic_init->ICPrescaler)); + assert_param(IS_FL_GPTIM_IC_FILTER(ic_init->ICFilter)); + /* 时钟总线使能配置 */ + if(TIMx == GPTIM0) + { + FL_RCC_EnableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_GPTIM0); + } + else + if(TIMx == GPTIM1) + { + FL_RCC_EnableGroup4BusClock(FL_RCC_GROUP4_BUSCLK_GPTIM1); + } + /* 通道关闭 */ + FL_GPTIM_IC_DisableChannel(TIMx, channel); + /*捕获极性 */ + FL_GPTIM_IC_SetChannelPolarity(TIMx, ic_init->ICPolarity, channel); + /* 捕获映射通道 */ + FL_GPTIM_CC_SetChannelMode(TIMx, ic_init->ICActiveInput, channel); + /* 捕获预分频 */ + FL_GPTIM_IC_SetPrescaler(TIMx, ic_init->ICPrescaler, channel); + /* 捕获滤波器 */ + FL_GPTIM_IC_SetFilter(TIMx, ic_init->ICFilter, channel); + if(ic_init->captureState == FL_ENABLE) + { + FL_GPTIM_IC_EnableChannel(TIMx, channel); + } + return result; +} + +/** + * @brief 将 @ref FL_GPTIM_IC_InitTypeDef 结构体初始化为默认配置 + * @param ic_init 指向 @ref FL_GPTIM_IC_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_GPTIM_IC_StructInit(FL_GPTIM_IC_InitTypeDef *ic_init) +{ + /* Set the default configuration */ + ic_init->ICPolarity = FL_GPTIM_IC_POLARITY_NORMAL; + ic_init->ICActiveInput = FL_GPTIM_CHANNEL_MODE_INPUT_NORMAL; + ic_init->ICPrescaler = FL_GPTIM_IC_PSC_DIV1; + ic_init->ICFilter = FL_GPTIM_IC_FILTER_DIV1; + ic_init->captureState = FL_DISABLE; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_i2c.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_i2c.c new file mode 100644 index 0000000000..c549f28982 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_i2c.c @@ -0,0 +1,243 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_i2c.c + * @author FMSH Application Team + * @brief Src file of I2C FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_rmu.h" +#include "fm33lc0xx_fl_i2c.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_FL_Private_Macros + * @{ + */ + +#define IS_FL_I2C_INSTANCE(INSTANCE) ((INSTANCE) == I2C) + +#define IS_FL_I2C_BAUDRATE(__VALUE__) (((__VALUE__) > 0 )&&((__VALUE__) <= 1000000)) + +#define IS_FL_I2C_CLOCKSRC(__VALUE__) (((__VALUE__) == FL_RCC_I2C_CLK_SOURCE_APB1CLK )||\ + ((__VALUE__) == FL_RCC_I2C_CLK_SOURCE_RCHF)||\ + ((__VALUE__) == FL_RCC_I2C_CLK_SOURCE_SYSCLK)||\ + ((__VALUE__) == FL_RCC_I2C_CLK_SOURCE_RCMF_PSC )) + +#define IS_FL_I2C_MSATER_TIMEOUT(__VALUE__) (((__VALUE__) == FL_IWDT_PERIOD_125MS)||\ + ((__VALUE__) == FL_IWDT_PERIOD_16000MS)) + + +#define IS_FL_I2C_SLAVE_ACK(__VALUE__) (((__VALUE__) == FL_ENABLE)||\ + ((__VALUE__) == FL_DISABLE)) + + + +#define IS_FL_I2C_ANGLOGFILTER(__VALUE__) (((__VALUE__) == FL_ENABLE)||\ + ((__VALUE__) == FL_DISABLE)) + +#define IS_FL_I2C_ADDRSIZE10BIT(__VALUE__) (((__VALUE__) == FL_ENABLE)||\ + ((__VALUE__) == FL_DISABLE)) + +#define IS_FL_I2C_SLAVE_SCLSEN(__VALUE__) (((__VALUE__) == FL_ENABLE)||\ + ((__VALUE__) == FL_DISABLE)) + +/** + * @} + */ + +/** @addtogroup I2C_FL_EF_Init + * @{ + */ + +/** + * @brief 复位I2C外设. + * @param I2Cx 外设入口地址 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_I2C_DeInit(I2C_Type *I2Cx) +{ + assert_param(IS_FL_I2C_INSTANCE(I2Cx)); + /* 使能外设复位 */ + FL_RCC_EnablePeripheralReset(); + /* 复位I2C外设寄存器 */ + FL_RCC_EnableResetAPB1Peripheral(FL_RCC_RSTAPB_I2C); + FL_RCC_DisableResetAPB1Peripheral(FL_RCC_RSTAPB_I2C); + /* 关闭外设总线始时钟和工作时钟 */ + FL_RCC_DisableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_I2C); + FL_RCC_DisableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_I2C); + /* 锁定外设复位 */ + FL_RCC_DisablePeripheralReset(); + return FL_PASS; +} + +/** + * @brief 配置I2C主机模式. + * @param I2Cx 外设入口地址 + * @param I2C_InitStruct 指向 @ref FL_I2C_MasterMode_InitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_I2C_MasterMode_Init(I2C_Type *I2Cx, FL_I2C_MasterMode_InitTypeDef *I2C_InitStruct) +{ + uint32_t I2C_Clk_Freq = 0, BRG = 0; + assert_param(IS_FL_I2C_INSTANCE(I2Cx)); + assert_param(IS_FL_I2C_CLOCKSRC(I2C_InitStruct->clockSource)); + assert_param(IS_FL_I2C_BAUDRATE(I2C_InitStruct->baudRate)); + /* 外设总线时钟和工作时钟开启 */ + FL_RCC_EnableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_I2C); + FL_RCC_EnableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_I2C); + /* 选择I2C工作时钟源 */ + FL_RCC_SetI2CClockSource(I2C_InitStruct->clockSource); + /* 获取时钟源速度 */ + switch(I2C_InitStruct->clockSource) + { + case FL_RCC_I2C_CLK_SOURCE_APB1CLK: + I2C_Clk_Freq = FL_RCC_GetAPB1ClockFreq(); + break; + case FL_RCC_I2C_CLK_SOURCE_RCHF: + I2C_Clk_Freq = FL_RCC_GetRCHFClockFreq(); + break; + case FL_RCC_I2C_CLK_SOURCE_SYSCLK: + I2C_Clk_Freq = FL_RCC_GetSystemClockFreq(); + break; + case FL_RCC_I2C_CLK_SOURCE_RCMF_PSC: + I2C_Clk_Freq = FL_RCC_GetRC4MClockFreq(); + break; + default: + break; + } + /* 根据不同的时钟源速度计算出配置速率需要的寄存器值并配置相关寄存器 */ + BRG = (uint32_t)(I2C_Clk_Freq / (2 * I2C_InitStruct->baudRate)) - 1; + FL_I2C_Master_WriteSCLHighWidth(I2Cx, BRG); + FL_I2C_Master_WriteSCLLowWidth(I2Cx, BRG); + FL_I2C_Master_WriteSDAHoldTime(I2Cx, (uint32_t)(BRG / 2.0 + 0.5)); + /* 使能外设 */ + FL_I2C_Master_Enable(I2C); + return FL_PASS; +} + +/** + * @brief 将 @ref FL_I2C_MasterMode_InitTypeDef 结构体初始化为默认配置 + * @param I2C_InitStruct 指向 @ref FL_I2C_MasterMode_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_I2C_MasterMode_StructInit(FL_I2C_MasterMode_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->clockSource = FL_RCC_I2C_CLK_SOURCE_RCHF; + I2C_InitStruct->baudRate = 40000; +} + +/** + * @brief 配置I2C从机模式. + * @param I2Cx 外设入口地址 + * @param I2C_InitStruct 指向 @ref FL_I2C_SlaveMode_InitTypeDef 结构体的指针. + * @note 作为从机时的从机地址应参考手册推荐具体设置 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_I2C_SlaveMode_Init(I2C_Type *I2Cx, FL_I2C_SlaveMode_InitTypeDef *I2C_InitStruct) +{ + assert_param(IS_FL_I2C_INSTANCE(I2Cx)); + assert_param(IS_FL_I2C_SLAVE_ACK(I2C_InitStruct->ACK)); + assert_param(IS_FL_I2C_ADDRSIZE10BIT(I2C_InitStruct->ownAddrSize10bit)); + assert_param(IS_FL_I2C_SLAVE_SCLSEN(I2C_InitStruct->SCLSEN)); + /* 外设总线时钟开启 注：不需要工作时钟*/ + FL_RCC_EnableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_I2C); + /* 使能SDA输出延迟 注：推荐开启*/ + FL_I2C_Slave_EnableSDAStretching(I2Cx); + /* 使能SCL模拟滤波使能 注：推荐开启*/ + FL_I2C_Slave_EnableSCLAnalogFilter(I2Cx); + /* 从机ACK */ + if(I2C_InitStruct->ACK == FL_ENABLE) + { + FL_I2C_Slave_EnableACK(I2Cx); + } + else + { + FL_I2C_Slave_DisableACK(I2Cx); + } + /* 从机地址宽度 和地址配置 */ + if(I2C_InitStruct->ownAddrSize10bit == FL_ENABLE) + { + FL_I2C_Slave_Enable10BitAddress(I2Cx); + FL_I2C_Slave_WriteSlaveAddress(I2Cx, I2C_InitStruct->ownAddr); + } + else + { + FL_I2C_Slave_Disable10BitAddress(I2Cx); + FL_I2C_Slave_WriteSlaveAddress(I2Cx, I2C_InitStruct->ownAddr & 0x7F); + } + /* 从机时钟延展使能 */ + if(I2C_InitStruct->SCLSEN == FL_ENABLE) + { + FL_I2C_Slave_EnableSCLStretching(I2Cx); + } + else + { + FL_I2C_Slave_DisableSCLStretching(I2Cx); + } + /* 外设开启 */ + FL_I2C_Slave_Enable(I2Cx); + return FL_PASS; +} + +/** + * @brief 将 @ref FL_I2C_SlaveMode_InitTypeDef 结构体初始化为默认配置 + * @param I2C_InitStruct 指向 @ref FL_I2C_SlaveMode_InitTypeDef 结构体的指针 + * + * @retval None + */ + +void FL_I2C_SlaveMode_StructInit(FL_I2C_SlaveMode_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->ACK = FL_ENABLE; + I2C_InitStruct->ownAddr = 0x55; + I2C_InitStruct->ownAddrSize10bit = FL_DISABLE; + I2C_InitStruct->SCLSEN = FL_DISABLE; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ + + + diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_iwdt.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_iwdt.c new file mode 100644 index 0000000000..021d617a93 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_iwdt.c @@ -0,0 +1,131 @@ +/** + **************************************************************************************************** + * @file fm33lc0xx_fl_iwdt.c + * @author FMSH Application Team + * @brief Src file of IWDT FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_iwdt.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup IWDT + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup IWDT_FL_Private_Macros + * @{ + */ +#define IS_IWDT_INSTANCE(INTANCE) ((INTANCE) == IWDT) + +#define IS_FL_IWDT_WINDOWSVEL(__VALUE__) ((__VALUE__) < 0xFFF) + +#define IS_FL_IWDT_OVERFLOWPERIOD(__VALUE__) (((__VALUE__) == FL_IWDT_PERIOD_125MS)||\ + ((__VALUE__) == FL_IWDT_PERIOD_250MS)||\ + ((__VALUE__) == FL_IWDT_PERIOD_500MS)||\ + ((__VALUE__) == FL_IWDT_PERIOD_1000MS)||\ + ((__VALUE__) == FL_IWDT_PERIOD_2000MS)||\ + ((__VALUE__) == FL_IWDT_PERIOD_4000MS)||\ + ((__VALUE__) == FL_IWDT_PERIOD_8000MS)||\ + ((__VALUE__) == FL_IWDT_PERIOD_16000MS)) +/** + * @} + */ + +/** @addtogroup IWDT_FL_EF_Init + * @{ + */ + +/** + * @brief 复位IWDT外设 + * + * @note 此函数只能用于配制前复位外设，因为IWDT开启后不可以关闭 + * + * @param IWDTx 外设入口地址 + * + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_IWDT_DeInit(IWDT_Type *IWDTx) +{ + assert_param(IS_IWDT_INSTANCE(IWDTx)); + return FL_PASS; +} + +/** + * @brief 配置IWDT + * + * @note IWTD使能后将无法关闭，直到下一次芯片复位 + * + * @param IWDTx 外设入口地址 + * @param IWDT_InitStruct 指向 @ref FL_IWDT_InitTypeDef 结构体的指针 + * + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_IWDT_Init(IWDT_Type *IWDTx, FL_IWDT_InitTypeDef *IWDT_InitStruct) +{ + FL_ErrorStatus status = FL_PASS; + /* 入口参数检查 */ + assert_param(IS_IWDT_INSTANCE(IWDTx)); + assert_param(IS_FL_IWDT_WINDOWSVEL(IWDT_InitStruct->iwdtWindows)); + assert_param(IS_FL_IWDT_OVERFLOWPERIOD(IWDT_InitStruct->overflowPeriod)); + /* 开启总线时钟 */ + FL_RCC_EnableGroup1BusClock(FL_RCC_GROUP1_BUSCLK_IWDT); + /* 配置独立看门狗溢出周期 */ + FL_IWDT_SetPeriod(IWDTx, IWDT_InitStruct->overflowPeriod); + /* 配置独立看门狗清狗窗口*/ + FL_IWDT_WriteWindow(IWDTx, IWDT_InitStruct->iwdtWindows); + /* 启动看门狗 */ + FL_IWDT_ReloadCounter(IWDTx); + return status; +} + +/** + * @brief 将 @ref FL_IWDT_InitTypeDef 结构体初始化为默认配置 + * @param IWDT_InitStruct 指向 @ref FL_IWDT_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_IWDT_StructInit(FL_IWDT_InitTypeDef *IWDT_InitStruct) +{ + /* 默认不使用窗口 */ + IWDT_InitStruct->iwdtWindows = 0; + /*最长溢出时间*/ + IWDT_InitStruct->overflowPeriod = FL_IWDT_PERIOD_500MS; +} + +/** + *@} + */ + +/** + *@} + */ + +/** + *@} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_lcd.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_lcd.c new file mode 100644 index 0000000000..fcf262fcd6 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_lcd.c @@ -0,0 +1,301 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_lcd.c + * @author FMSH Application Team + * @brief Src file of LCD FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_lcd.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup LCD + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup Private_Macros + * @{ + */ + +#define IS_FL_LCD_INSTANCE(INTENCE) ((INTENCE) == LCD) + +#define IS_FL_LCD_BIASCURRENT(__VALUE__) (((__VALUE__) == (FL_LCD_BIAS_CURRENT_VERYHIGH))||\ + ((__VALUE__) == (FL_LCD_BIAS_CURRENT_HIGH))||\ + ((__VALUE__) == (FL_LCD_BIAS_CURRENT_MEDIUM))||\ + ((__VALUE__) == (FL_LCD_BIAS_CURRENT_LOW))) + +#define IS_FL_LCD_ENMODE(__VALUE__) ((__VALUE__) == (FL_LCD_DRIVER_MODE_INNER_RESISTER)) + +#define IS_FL_LCD_BIASVOLTAGE(__VALUE__) (((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL0))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL1))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL2))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL3))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL4))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL5))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL6))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL7))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL8))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL9))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL10))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL11))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL12))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL13))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL14))||\ + ((__VALUE__) == (FL_LCD_BIAS_VOLTAGE_LEVEL15))) + +#define IS_FL_LCD_BIASMD(__VALUE__) (((__VALUE__) == (FL_LCD_BIAS_MODE_4BIAS))||\ + ((__VALUE__) == (FL_LCD_BIAS_MODE_3BIAS))) + +#define IS_FL_LCD_BWFT(__VALUE__) (((__VALUE__) == (FL_LCD_WAVEFORM_TYPEA))||\ + ((__VALUE__) == (FL_LCD_WAVEFORM_TYPEB))) + +#define IS_FL_LCD_LMUX(__VALUE__) (((__VALUE__) == (FL_LCD_COM_NUM_4COM))||\ + ((__VALUE__) == (FL_LCD_COM_NUM_6COM))||\ + ((__VALUE__) == (FL_LCD_COM_NUM_8COM))) + + +/** + * @} + */ + +/* Private functions -----------------------------------------------*/ +/** @defgroup LCD_FL_PF LCD Private Functions + * @{ + */ + +/** + * @brief 获取LCD工作频率寄存器值 + * @param freq 工作频率 + * @retval 工作频率寄存器值 + */ +static uint32_t FL_LCD_DisplayFreq(uint32_t freq) +{ + uint32_t displayFreq = 32; + if((freq > 0) && (freq <= 100)) + { + switch(FL_LCD_GetCOMNumber(LCD)) + { + case FL_LCD_COM_NUM_4COM: + displayFreq = (uint32_t)(32768.0 / (float)(4 * freq * 2) + 0.5); + break; + case FL_LCD_COM_NUM_6COM: + displayFreq = (uint32_t)(32768.0 / (float)(6 * freq * 2) + 0.5); + break; + case FL_LCD_COM_NUM_8COM: + displayFreq = (uint32_t)(32768.0 / (float)(8 * freq * 2) + 0.5); + break; + } + } + return displayFreq & 0xff; +} + +/** + * @brief 获取LCD闪烁时间寄存器值 + * @param time 闪烁时间 + * @retval 闪烁时间寄存器值 + */ +static uint32_t FL_LCD_FlickTime(uint32_t time) +{ + float stepTime = 0; + switch(FL_LCD_GetCOMNumber(LCD)) + { + case FL_LCD_COM_NUM_4COM: + stepTime = (float)(4 * FL_LCD_ReadDisplayFrequency(LCD) * 2 * 16 * 1000) / 32768.0; + break; + case FL_LCD_COM_NUM_6COM: + stepTime = (float)(6 * FL_LCD_ReadDisplayFrequency(LCD) * 2 * 16 * 1000) / 32768.0; + break; + case FL_LCD_COM_NUM_8COM: + stepTime = (float)(8 * FL_LCD_ReadDisplayFrequency(LCD) * 2 * 16 * 1000) / 32768.0; + break; + } + return (uint32_t)(time / stepTime + 0.5); +} + +/** + * @} + */ + +/* Exported functions -----------------------------------------------*/ +/** @addtogroup LCD_FL_EF_Init + * @{ + */ + +/** + * @brief 复位LCD + * + * @param LCDx 外设入口地址 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_LCD_DeInit(LCD_Type *LCDx) +{ + assert_param(IS_FL_LCD_INSTANCE(LCDx)); + /* 使能外设复位 */ + FL_RCC_EnablePeripheralReset(); + /* 复位LCD外设寄存器 */ + FL_RCC_EnableResetAPB1Peripheral(FL_RCC_RSTAPB_LCD); + FL_RCC_DisableResetAPB1Peripheral(FL_RCC_RSTAPB_LCD); + /* 关闭外设总线始时钟和工作时钟 */ + FL_RCC_DisableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_LCD); + /* 锁定外设复位 */ + FL_RCC_DisablePeripheralReset(); + return FL_PASS; +} + +/** + * @brief 配置LCD + * @param LCDx 外设入口地址 + * @param initStruct 指向 @ref FL_LPTIM32_InitTypeDef 结构体的指针 + * + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_LCD_Init(LCD_Type *LCDx, FL_LCD_InitTypeDef *initStruct) +{ + assert_param(IS_FL_LCD_INSTANCE(LCDx)); + assert_param(IS_FL_LCD_BIASCURRENT(initStruct->biasCurrent)); + assert_param(IS_FL_LCD_ENMODE(initStruct->mode)); + assert_param(IS_FL_LCD_BIASVOLTAGE(initStruct->biasVoltage)); + assert_param(IS_FL_LCD_BIASMD(initStruct->biasMode)); + assert_param(IS_FL_LCD_BWFT(initStruct->waveform)); + assert_param(IS_FL_LCD_LMUX(initStruct->COMxNum)); + /* 外设总线始时钟 */ + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_LCD); + /* 电流源电流控制 */ + FL_LCD_SetBiasCurrent(LCD, initStruct->biasCurrent); + /* LCD驱动模式 */ + FL_LCD_SetDriverMode(LCD, initStruct->mode); + /* 偏执电压设置 */ + FL_LCD_SetBiasVoltage(LCD, initStruct->biasVoltage); + /* 偏执模式选择 */ + FL_LCD_SetBiasMode(LCD, initStruct->biasMode); + /* 驱动波形设置 */ + FL_LCD_SetWaveform(LCD, initStruct->waveform); + /* COMx口选择 */ + FL_LCD_SetCOMNumber(LCD, initStruct->COMxNum); + /* 设置工作频率 */ + FL_LCD_WriteDisplayFrequency(LCD, FL_LCD_DisplayFreq(initStruct->displayFreq)); + /* 设置闪烁频率 */ + FL_LCD_WriteDisplayOnTime(LCD, FL_LCD_FlickTime(initStruct->flickOnTime)); + FL_LCD_WriteDisplayOffTime(LCD, FL_LCD_FlickTime(initStruct->flickOffTime)); + /* 使能外设 */ + FL_LCD_Enable(LCD); + return FL_PASS; +} + +/** + * @brief 将 @ref FL_LCD_InitTypeDef 结构体初始化为默认配置 + * @param initStruct 指向 @ref FL_LCD_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_LCD_StructInit(FL_LCD_InitTypeDef *initStruct) +{ + initStruct->biasCurrent = FL_LCD_BIAS_CURRENT_HIGH; + initStruct->mode = FL_LCD_DRIVER_MODE_INNER_RESISTER; + initStruct->biasVoltage = FL_LCD_BIAS_VOLTAGE_LEVEL10; + initStruct->biasMode = FL_LCD_BIAS_MODE_3BIAS; + initStruct->waveform = FL_LCD_WAVEFORM_TYPEA; + initStruct->COMxNum = FL_LCD_COM_NUM_6COM; + initStruct->displayFreq = 42; + initStruct->flickOnTime = 0; + initStruct->flickOffTime = 0; +} + +/** + * @} + */ + +/** @addtogroup LCD_FL_EF_Operation + * @{ + */ + +/** + * @brief 设置 LCD 4COM显示字端 + * @param display 指向显示信息的缓存区域，可直接指向LCD的DATAx寄存器。 + * @param com 待显示字段所在COM。范围0-4。 + * @param seg 待显示字段所在SEG。范围0-31。 + * @param state 待显示字段状态。0，熄灭；否则，点亮。 + * + * @retval None + */ +void FL_LCD_4COMDisplay(uint32_t *display, uint8_t com, uint8_t seg, uint8_t state) +{ + if(state != 0) + { + state = 1; + } + MODIFY_REG(display[com], 0x1 << seg, state << seg); +} + +/** + * @brief 设置 LCD 6COM显示字端 + * @param display 指向显示信息的缓存区域，可直接指向LCD的DATAx寄存器。 + * @param com 待显示字段所在COM。范围0-6。 + * @param seg 待显示字段所在SEG。范围0-29。 + * @param state 待显示字段状态。0，熄灭；否则，点亮。 + * + * @retval None + */ +void FL_LCD_6COMDisplay(uint32_t *display, uint8_t com, uint8_t seg, uint8_t state) +{ + if(state != 0) + { + state = 1; + } + MODIFY_REG(display[com], 0x1 << seg, state << seg); +} + +/** + * @brief 设置 LCD 8COM显示字端 + * @param display 指向显示信息的缓存区域，可直接指向LCD的DATAx寄存器。 + * @param com 待显示字段所在COM。范围0-8。 + * @param seg 待显示字段所在SEG。范围0-27。 + * @param state 待显示字段状态。0，熄灭；否则，点亮。 + * + * @retval None + */ +void FL_LCD_8COMDisplay(uint32_t *display, uint8_t com, uint8_t seg, uint8_t state) +{ + if(state != 0) + { + state = 1; + } + MODIFY_REG(display[com], 0x1 << seg, state << seg); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_lptim32.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_lptim32.c new file mode 100644 index 0000000000..95ce02f6f6 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_lptim32.c @@ -0,0 +1,325 @@ +/** + **************************************************************************************************** + * @file fm33lc0xx_fl_lptim32.c + * @author FMSH Application Team + * @brief Src file of LPTIM32 FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_lptim32.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup LPTIM32 + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup LPTIM32_FL_Private_Macros + * @{ + */ + +#define IS_LPTIM32_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM32)) + +#define IS_FL_LPTIM32_OPCLK_SOURCE(__VALUE__) (((__VALUE__) == FL_RCC_LPTIM32_CLK_SOURCE_APB1CLK)||\ + ((__VALUE__) == FL_RCC_LPTIM32_CLK_SOURCE_LSCLK)||\ + ((__VALUE__) == FL_RCC_LPTIM32_CLK_SOURCE_RCLP)||\ + ((__VALUE__) == FL_RCC_LPTIM32_CLK_SOURCE_RCMF_PSC)) + +#define IS_FL_LPTIM32_CLK_SOURCE(__VALUE__) (((__VALUE__) == FL_LPTIM32_CLK_SOURCE_INTERNAL)||\ + ((__VALUE__) == FL_LPTIM32_CLK_SOURCE_EXTERNAL)) + +#define IS_FL_LPTIM32_PRESCALER(__VALUE__) (((__VALUE__) == FL_LPTIM32_PSC_DIV1)||\ + ((__VALUE__) == FL_LPTIM32_PSC_DIV2)||\ + ((__VALUE__) == FL_LPTIM32_PSC_DIV4)||\ + ((__VALUE__) == FL_LPTIM32_PSC_DIV8)||\ + ((__VALUE__) == FL_LPTIM32_PSC_DIV16)||\ + ((__VALUE__) == FL_LPTIM32_PSC_DIV32)||\ + ((__VALUE__) == FL_LPTIM32_PSC_DIV64)||\ + ((__VALUE__) == FL_LPTIM32_PSC_DIV128)) + +#define IS_FL_LPTIM32_MODE(__VALUE__) (((__VALUE__) == FL_LPTIM32_OPERATION_MODE_NORMAL)||\ + ((__VALUE__) == FL_LPTIM32_OPERATION_MODE_EXTERNAL_TRIGGER_CNT)||\ + ((__VALUE__) == FL_LPTIM32_OPERATION_MODE_EXTERNAL_ASYNC_PULSE_CNT)||\ + ((__VALUE__) == FL_LPTIM32_OPERATION_MODE_TIMEOUT)) + +#define IS_FL_LPTIM32_ETR_TRIGEER_EDGE(__VALUE__) (((__VALUE__) == FL_LPTIM32_ETR_TRIGGER_EDGE_RISING)||\ + ((__VALUE__) == FL_LPTIM32_ETR_TRIGGER_EDGE_FALLING)||\ + ((__VALUE__) == FL_LPTIM32_ETR_TRIGGER_EDGE_BOTH)) + +#define IS_FL_LPTIM32_ONE_PULSE_MODE(__VALUE__) (((__VALUE__) == FL_LPTIM32_ONE_PULSE_MODE_CONTINUOUS)||\ + ((__VALUE__) == FL_LPTIM32_ONE_PULSE_MODE_SINGLE)) + +#define IS_FL_LPTIM32_ETR_COUNT_EDGE(__VALUE__) (((__VALUE__) == FL_LPTIM32_ETR_COUNT_EDGE_RISING)||\ + ((__VALUE__) == FL_LPTIM32_ETR_COUNT_EDGE_FALLING)) + +#define IS_FL_LPTIM32_IC_EDGE(__VALUE__) (((__VALUE__) == FL_LPTIM32_IC_EDGE_RISING)||\ + ((__VALUE__) == FL_LPTIM32_IC_EDGE_FALLING)||\ + ((__VALUE__) == FL_LPTIM32_IC_EDGE_BOTH)) + +#define IS_FL_LPTIM32_OC_POLARITY(__VALUE__) (((__VALUE__) == FL_LPTIM32_OC_POLARITY_NORMAL)||\ + ((__VALUE__) == FL_LPTIM32_OC_POLARITY_INVERT)) + +#define IS_FL_LPTIM32_CHANNEL(__VALUE__) (((__VALUE__) == FL_LPTIM32_CHANNEL_1)||\ + ((__VALUE__) == FL_LPTIM32_CHANNEL_2)) + +#define IS_FL_LPTIM32_CAPTURE_SOURCE(__VALUE__) (((__VALUE__) == FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP0)||\ + ((__VALUE__) == FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP1)||\ + ((__VALUE__) == FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP2)||\ + ((__VALUE__) == FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP3)) + + +/** + * @} + */ + +/** @addtogroup LPTIM32_FL_EF_Init + * @{ + */ + +/** + * @brief 复位LPTIM32外设 + * @param LPTIM32x 外设入口地址 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_LPTIM32_DeInit(LPTIM32_Type *LPTIM32x) +{ + FL_ErrorStatus status = FL_FAIL; + assert_param(IS_LPTIM32_INSTANCE(LPTIM32x)); + /* 使能外设复位 */ + FL_RCC_EnablePeripheralReset(); + /*复位LPTIM*/ + FL_RCC_EnableResetAPB1Peripheral(FL_RCC_RSTAPB_LPTIM32); + FL_RCC_DisableResetAPB1Peripheral(FL_RCC_RSTAPB_LPTIM32); + /* 关闭外设总线时钟和工作时钟 */ + FL_RCC_DisableGroup1BusClock(FL_RCC_GROUP1_BUSCLK_LPTIM32); + FL_RCC_DisableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_LPTIM32); + /* 锁定外设复位功能 */ + FL_RCC_DisablePeripheralReset(); + status = FL_PASS; + return status; +} +/** + * @brief 配置LPTIM32工作在定时器模式 + * + * @note 其中 @ref FL_LPTIM32_OPERATION_MODE_EXTERNAL_ASYNC_PULSE_CNT 模式需要外部脉冲提供给LPTIM32模块作为工作时钟，此时 + * LPTIM32完全工作在异步模式下。 + * @param LPTIM32x 外设入口地址 + * @param initStruct 指向 @ref FL_LPTIM32_InitTypeDef 结构体的指针 + * + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_LPTIM32_Init(LPTIM32_Type *LPTIM32x, FL_LPTIM32_InitTypeDef *initStruct) +{ + FL_ErrorStatus status = FL_PASS; + /* 检查入口参数 */ + assert_param(IS_LPTIM32_INSTANCE(LPTIM32x)); + assert_param(IS_FL_LPTIM32_OPCLK_SOURCE(initStruct->clockSource)); + assert_param(IS_FL_LPTIM32_CLK_SOURCE(initStruct->prescalerClockSource)); + assert_param(IS_FL_LPTIM32_PRESCALER(initStruct->prescaler)); + assert_param(IS_FL_LPTIM32_MODE(initStruct->mode)); + assert_param(IS_FL_LPTIM32_ETR_TRIGEER_EDGE(initStruct->triggerEdge)); + assert_param(IS_FL_LPTIM32_ONE_PULSE_MODE(initStruct->onePulseMode)); + assert_param(IS_FL_LPTIM32_ETR_COUNT_EDGE(initStruct->countEdge)); + /* 时钟配置 */ + if(LPTIM32x == LPTIM32) + { + /* 使能总线时钟 */ + FL_RCC_EnableGroup1BusClock(FL_RCC_GROUP1_BUSCLK_LPTIM32); + /* 除了异步计数模式，其他模式都需要使能工作时钟 */ + if(initStruct->mode != FL_LPTIM32_OPERATION_MODE_EXTERNAL_ASYNC_PULSE_CNT) + { + /* 使能工作时钟 */ + FL_RCC_EnableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_LPTIM32); + /* 设置工作时钟时钟源 */ + FL_RCC_SetLPTIM32ClockSource(initStruct->clockSource); + } + } + /* 配置分频器的时钟源 */ + FL_LPTIM32_SetClockSource(LPTIM32x, initStruct->prescalerClockSource); + /* 配置时钟分频 */ + FL_LPTIM32_SetPrescaler(LPTIM32x, initStruct->prescaler); + /* 配置定时器工作模式 */ + FL_LPTIM32_SetOperationMode(LPTIM32x, initStruct->mode); + /* 配置定时器不同模式下的特殊寄存器 */ + switch(initStruct->mode) + { + case FL_LPTIM32_OPERATION_MODE_NORMAL: + { + } + break; + case FL_LPTIM32_OPERATION_MODE_EXTERNAL_TRIGGER_CNT: + { + /* 配置外部输入有效边沿 */ + FL_LPTIM32_SetETRTriggerEdge(LPTIM32x, initStruct->triggerEdge); + } + break; + case FL_LPTIM32_OPERATION_MODE_EXTERNAL_ASYNC_PULSE_CNT: + { + /* 配置外部计数边沿 */ + FL_LPTIM32_SetETRCountEdge(LPTIM32x, initStruct->countEdge); + /* 开启外部输入滤波 */ + FL_LPTIM32_EnableETRFilter(LPTIM32x); + } + break; + case FL_LPTIM32_OPERATION_MODE_TIMEOUT: + { + /* 配置外部输入有效边沿 */ + FL_LPTIM32_SetETRTriggerEdge(LPTIM32x, initStruct->triggerEdge); + } + break; + } + /* 单次计数模式 */ + FL_LPTIM32_SetOnePulseMode(LPTIM32x, initStruct->onePulseMode); + /* 设置重装载值 */ + FL_LPTIM32_WriteAutoReload(LPTIM32x, initStruct->autoReload); + return status; +} +/** + * @brief 将 @ref FL_LPTIM32_InitTypeDef 结构体初始化为默认配置 + * @param initStruct 指向 @ref FL_LPTIM32_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_LPTIM32_StructInit(FL_LPTIM32_InitTypeDef *initStruct) +{ + initStruct->clockSource = FL_RCC_LPTIM32_CLK_SOURCE_APB1CLK; + initStruct->prescalerClockSource = FL_LPTIM32_CLK_SOURCE_INTERNAL; + initStruct->prescaler = FL_LPTIM32_PSC_DIV1; + initStruct->autoReload = 0; + initStruct->mode = FL_LPTIM32_OPERATION_MODE_NORMAL; + initStruct->countEdge = FL_LPTIM32_ETR_COUNT_EDGE_RISING; + initStruct->triggerEdge = FL_LPTIM32_ETR_TRIGGER_EDGE_RISING; + initStruct->onePulseMode = FL_LPTIM32_ONE_PULSE_MODE_CONTINUOUS; +} + +/** + * @brief 配置LPTIM32工作在输入捕获模式 + * + * @param LPTIM32x 外设入口地址 + * @param initStruct_IC 指向 @ref FL_LPTIM32_IC_InitTypeDef 结构体的指针 + * @param channel LPTIM32通道 + * 此参数可取以下值： + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_LPTIM32_IC_Init(LPTIM32_Type *LPTIM32x, uint32_t channel, FL_LPTIM32_IC_InitTypeDef *initStruct_IC) +{ + FL_ErrorStatus status = FL_PASS; + /* 参数检查 */ + assert_param(IS_LPTIM32_INSTANCE(LPTIM32x)); + assert_param(IS_FL_LPTIM32_CHANNEL(channel)); + assert_param(IS_FL_LPTIM32_IC_EDGE(initStruct_IC->ICEdge)); + assert_param(IS_FL_LPTIM32_CAPTURE_SOURCE(initStruct_IC->ICSource)); + /* 通道捕获源 */ + FL_LPTIM32_IC_SetCaptureSource(LPTIM32, initStruct_IC->ICSource, channel); + /* 捕获通道边沿 */ + FL_LPTIM32_IC_SetCaptureEdge(LPTIM32, initStruct_IC->ICEdge, channel); + /* 通道输入捕获使能 */ + FL_LPTIM32_SetChannelMode(LPTIM32, FL_LPTIM32_CHANNEL_MODE_INPUT, channel); + return status; +} +/** + * @brief 将 @ref FL_LPTIM32_IC_InitTypeDef 结构体初始化为默认配置 + * @param initStruct_IC 指向 @ref FL_LPTIM32_IC_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_LPTIM32_IC_StructInit(FL_LPTIM32_IC_InitTypeDef *initStruct_IC) +{ + initStruct_IC->ICEdge = FL_LPTIM32_IC_EDGE_RISING; + initStruct_IC->ICSource = FL_LPTIM32_IC_CAPTURE_SOURCE_GROUP0; +} + +/** + * @brief 配置LPTIM32寄存器工作在输出比较模式 + * + * @param LPTIM32x 外设入口地址 + * @param initStruct_OC 指向 @ref FL_LPTIM32_OC_InitTypeDef 结构体的指针 + * @param channel LPTIM32通道 + * 此参数可取以下值： + * @arg @ref FL_LPTIM32_CHANNEL_1 + * @arg @ref FL_LPTIM32_CHANNEL_2 + * + * @retval ErrorStatus枚举值 + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_LPTIM32_OC_Init(LPTIM32_Type *LPTIM32x, uint32_t channel, FL_LPTIM32_OC_InitTypeDef *initStruct_OC) +{ + FL_ErrorStatus result = FL_PASS; + /* 参数检查 */ + assert_param(IS_LPTIM32_INSTANCE(LPTIM32x)); + assert_param(IS_FL_LPTIM32_CHANNEL(channel)); + assert_param(IS_FL_LPTIM32_OC_POLARITY(initStruct_OC->OCPolarity)); + /* 比较通道极性 */ + FL_LPTIM32_OC_SetPolarity(LPTIM32x, initStruct_OC->OCPolarity, channel); + /* 设置比较值 */ + switch(channel) + { + case FL_LPTIM32_CHANNEL_1: + FL_LPTIM32_WriteCompareCH1(LPTIM32x, initStruct_OC->compareValue); + break; + case FL_LPTIM32_CHANNEL_2: + FL_LPTIM32_WriteCompareCH2(LPTIM32x, initStruct_OC->compareValue); + break; + default : + result = FL_FAIL; + break; + } + /* 通道输出比较使能 */ + FL_LPTIM32_SetChannelMode(LPTIM32x, FL_LPTIM32_CHANNEL_MODE_OUTPUT, channel); + return result; +} + +/** + * @brief 将 @ref FL_LPTIM32_OC_InitTypeDef 结构体初始化为默认配置 + * @param initStruct_OC 指向 @ref FL_LPTIM32_OC_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_LPTIM32_OC_StructInit(FL_LPTIM32_OC_InitTypeDef *initStruct_OC) +{ + initStruct_OC->compareValue = 0; + initStruct_OC->OCPolarity = FL_LPTIM32_OC_POLARITY_NORMAL; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ + diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_lpuart.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_lpuart.c new file mode 100644 index 0000000000..b25a6b20e8 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_lpuart.c @@ -0,0 +1,245 @@ +/** + **************************************************************************************************** + * @file fm33lc0xx_fl_lpuart.c + * @author FMSH Application Team + * @brief Src file of LPUART FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_lpuart.h" +#include "fm33lc0xx_fl_rmu.h" +#include "fm33lc0xx_fl_rcc.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup LPUART + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup LPUART_FL_Private_Macros + * @{ + */ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART0)||\ + ((INSTANCE) == LPUART1)) + +#define IS_FL_LPUART_CLKSRC(__VALUE__) (((__VALUE__) == FL_RCC_LPUART_CLK_SOURCE_LSCLK)||\ + ((__VALUE__) == FL_RCC_LPUART_CLK_SOURCE_RCHF)||\ + ((__VALUE__) == FL_RCC_LPUART_CLK_SOURCE_RCMF)) + +#define IS_FL_LPUART_BAUDRATE(__VALUE__) (((__VALUE__) == FL_LPUART_BAUDRATE_300)||\ + ((__VALUE__) == FL_LPUART_BAUDRATE_600)||\ + ((__VALUE__) == FL_LPUART_BAUDRATE_1200)||\ + ((__VALUE__) == FL_LPUART_BAUDRATE_2400)||\ + ((__VALUE__) == FL_LPUART_BAUDRATE_4800)||\ + ((__VALUE__) == FL_LPUART_BAUDRATE_9600)) + +#define IS_FL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == FL_LPUART_DATA_WIDTH_6B)||\ + ((__VALUE__) == FL_LPUART_DATA_WIDTH_7B)||\ + ((__VALUE__) == FL_LPUART_DATA_WIDTH_8B)||\ + ((__VALUE__) == FL_LPUART_DATA_WIDTH_9B)) + +#define IS_FL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == FL_LPUART_STOP_BIT_WIDTH_1B)||\ + ((__VALUE__) == FL_LPUART_STOP_BIT_WIDTH_2B)) + +#define IS_FL_LPUART_PARITY(__VALUE__) (((__VALUE__) == FL_LPUART_PARITY_NONE)||\ + ((__VALUE__) == FL_LPUART_PARITY_EVEN)||\ + ((__VALUE__) == FL_LPUART_PARITY_ODD)) + +#define IS_FL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == FL_LPUART_DIRECTION_NONE)||\ + ((__VALUE__) == FL_LPUART_DIRECTION_RX)||\ + ((__VALUE__) == FL_LPUART_DIRECTION_TX)||\ + ((__VALUE__) == FL_LPUART_DIRECTION_TX_RX)) + +/** + * @} + */ + +/** @addtogroup LPUART_FL_EF_Init + * @{ + */ + +/** + * @brief 复位LPUART + * @param LPUARTx 外设入口地址 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_LPUART_DeInit(LPUART_Type *LPUARTx) +{ + FL_ErrorStatus status = FL_PASS; + /* 入口参数合法性断言 */ + assert_param(IS_LPUART_INSTANCE(LPUARTx)); + /* 外设复位使能 */ + FL_RCC_EnablePeripheralReset(); + if(LPUARTx == LPUART0) + { + /*复位LPUART*/ + FL_RCC_EnableResetAPB1Peripheral(FL_RCC_RSTAPB_LPUART0); + FL_RCC_DisableResetAPB1Peripheral(FL_RCC_RSTAPB_LPUART0); + /* 外设总线时钟关闭 */ + FL_RCC_IsEnabledGroup3BusClock(FL_RCC_GROUP3_BUSCLK_LPUART0); + /* 外设工作时钟关闭 */ + FL_RCC_DisableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_LPUART0); + } + else + if(LPUARTx == LPUART1) + { + /*复位LPUART*/ + FL_RCC_EnableResetAPB2Peripheral(FL_RCC_RSTAPB_LPUART1); + FL_RCC_DisableResetAPB2Peripheral(FL_RCC_RSTAPB_LPUART1); + /* 外设总线时钟关闭 */ + FL_RCC_IsEnabledGroup3BusClock(FL_RCC_GROUP3_BUSCLK_LPUART1); + /* 外设工作时钟关闭 */ + FL_RCC_DisableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_LPUART1); + } + else + { + status = FL_FAIL; + } + /* 锁定外设复位功能 */ + FL_RCC_DisablePeripheralReset(); + return (status); +} + +/** + * @brief 配置LPUART + * + * @note 波特率调制寄存器中的MCTL值，默认为工作时钟为32768Hz的频率下的调制值，用户如果外设工作时钟不是此前 + * 提则可能需要手动调整这个寄存器的值，以达到更好的通信效果。 + * @param LPUARTx 外设入口地址 + * @param initStruct 指向 @ref FL_LPUART_InitTypeDef 结构体的指针 + * + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_LPUART_Init(LPUART_Type *LPUARTx, FL_LPUART_InitTypeDef *initStruct) +{ + FL_ErrorStatus status = FL_FAIL; + uint16_t MCTLVel = 0; + /* 参数合法性检查 */ + assert_param(IS_LPUART_INSTANCE(LPUARTx)); + assert_param(IS_FL_LPUART_CLKSRC(initStruct->clockSrc)); + assert_param(IS_FL_LPUART_BAUDRATE(initStruct->baudRate)); + assert_param(IS_FL_LPUART_DATAWIDTH(initStruct->dataWidth)); + assert_param(IS_FL_LPUART_STOPBITS(initStruct->stopBits)); + assert_param(IS_FL_LPUART_PARITY(initStruct->parity)); + assert_param(IS_FL_LPUART_DIRECTION(initStruct->transferDirection)); + if(LPUARTx == LPUART0) + { + /*总线时钟使能*/ + FL_RCC_EnableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_LPUART0); + /*操作时钟使能*/ + FL_RCC_EnableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_LPUART0); + /*时钟源选择*/ + FL_RCC_SetLPUART0ClockSource(initStruct->clockSrc << RCC_OPCCR1_LPUART0CKS_Pos); + } + else + { + /*总线时钟使能*/ + FL_RCC_EnableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_LPUART1); + /*操作时钟使能*/ + FL_RCC_EnableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_LPUART1); + /*时钟源选择*/ + FL_RCC_SetLPUART1ClockSource(initStruct->clockSrc << RCC_OPCCR1_LPUART1CKS_Pos); + } + /*发送接收配置*/ + if(initStruct->transferDirection & FL_LPUART_DIRECTION_TX) + { + do + { + FL_LPUART_EnableTX(LPUARTx); + } while(FL_LPUART_IsEnabledTX(LPUARTx) != FL_SET); + } + if(initStruct->transferDirection & FL_LPUART_DIRECTION_RX) + { + do + { + FL_LPUART_EnableRX(LPUARTx); + } while(FL_LPUART_IsEnabledRX(LPUARTx) != FL_SET); + } + /*配置波特率*/ + FL_LPUART_SetBaudRate(LPUARTx, initStruct->baudRate); + /*配置停止位*/ + FL_LPUART_SetStopBitsWidth(LPUARTx, initStruct->stopBits); + /*配置数据位宽*/ + FL_LPUART_SetDataWidth(LPUARTx, initStruct->dataWidth); + /*配置波特率*/ + FL_LPUART_SetParity(LPUARTx, initStruct->parity); + /*根据波特率配置MCTL值*/ + switch(initStruct->baudRate) + { + case FL_LPUART_BAUDRATE_9600: + MCTLVel = 0x0552; + break; + case FL_LPUART_BAUDRATE_4800: + MCTLVel = 0x1EFB; + break; + case FL_LPUART_BAUDRATE_2400: + MCTLVel = 0x16DB; + break; + case FL_LPUART_BAUDRATE_1200: + MCTLVel = 0x0492; + break; + case FL_LPUART_BAUDRATE_600: + MCTLVel = 0x16D6; + break; + case FL_LPUART_BAUDRATE_300: + MCTLVel = 0x0842; + break; + default: + MCTLVel = 0x0552; + break; + } + FL_LPUART_WriteBitModulation(LPUARTx, MCTLVel); + status = FL_PASS; + return status; +} + +/** + * @brief 将 @ref FL_LPUART_InitTypeDef 结构体初始化为默认配置 + * @param initStruct 指向 @ref FL_LPUART_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_LPUART_StructInit(FL_LPUART_InitTypeDef *initStruct) +{ + initStruct->baudRate = FL_LPUART_BAUDRATE_9600; + initStruct->dataWidth = FL_LPUART_DATA_WIDTH_8B; + initStruct->stopBits = FL_LPUART_STOP_BIT_WIDTH_1B; + initStruct->parity = FL_LPUART_PARITY_NONE ; + initStruct->transferDirection = FL_LPUART_DIRECTION_TX_RX; + initStruct->clockSrc = FL_RCC_LPUART_CLK_SOURCE_LSCLK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_opa.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_opa.c new file mode 100644 index 0000000000..0db3ac8a77 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_opa.c @@ -0,0 +1,182 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_opa.c + * @author FMSH Application Team + * @brief Src file of OPA FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_rmu.h" +#include "fm33lc0xx_fl_opa.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup OPA + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup OPA_FL_Private_Macros + * @{ + */ + +#define IS_OPA_ALL_INSTANCE(INTENCE) (((INTENCE) == OPA1)||\ + ((INTENCE) == OPA2)) + +#define IS_FL_OPA_INP_CHANNAL(__VALUE__) (((__VALUE__) == FL_OPA_INP_SOURCE_INP1)||\ + ((__VALUE__) == FL_OPA_INP_SOURCE_INP2)) + + +#define IS_FL_OPA_INN_CHANNAL(__VALUE__) (((__VALUE__) == FL_OPA_INN_SOURCE_INN1)||\ + ((__VALUE__) == FL_OPA_INN_SOURCE_INN2)||\ + ((__VALUE__) == FL_OPA_INN_SOURCE_VREF)||\ + ((__VALUE__) == FL_OPA_INN_SOURCE_THREE_QUARTERS_VREF)||\ + ((__VALUE__) == FL_OPA_INN_SOURCE_HALF_VREF)||\ + ((__VALUE__) == FL_OPA_INN_SOURCE_ONE_QUARTER_VREF)||\ + ((__VALUE__) == FL_OPA_INN_SOURCE_ONE_EIGHTH_VREF)) + +#define IS_FL_OPA_MODE(__VALUE__) (((__VALUE__) == FL_OPA_MODE_STANDALONE)||\ + ((__VALUE__) == FL_OPA_MODE_COMPARATOR)||\ + ((__VALUE__) == FL_OPA_MODE_PGA)||\ + ((__VALUE__) == FL_OPA_MODE_BUFFER)) + +#define IS_FL_OPA_DIGITALFILTER(__VALUE__) (((__VALUE__) == FL_DISABLE)||\ + ((__VALUE__) == FL_ENABLE)) + +#define IS_FL_OPA_NEGTIVE_TO_PIN(__VALUE__) (((__VALUE__) == FL_DISABLE)||\ + ((__VALUE__) == FL_ENABLE)) + +#define IS_FL_OPA_LOW_POWER_MODE(__VALUE__) (((__VALUE__) == FL_DISABLE)||\ + ((__VALUE__) == FL_ENABLE)) + +#define IS_FL_OPA_GAIN(__VALUE__) (((__VALUE__) == FL_OPA_GAIN_X2)||\ + ((__VALUE__) == FL_OPA_GAIN_X4)||\ + ((__VALUE__) == FL_OPA_GAIN_X8)||\ + ((__VALUE__) == FL_OPA_GAIN_X16)) + +/** + * @} + */ + +/** @addtogroup OPA_FL_EF_Init + * @{ + */ + +/** + * @brief 复位OPA + * @param OPAx 外设入口地址 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_OPA_DeInit(OPA_Type *OPAx) +{ + /* 入口参数合法性断言 */ + assert_param(IS_OPA_ALL_INSTANCE(OPAx)); + /* 使能外设复位 */ + FL_RCC_EnablePeripheralReset(); + /* 复位外设寄存器 */ + FL_RCC_EnableResetAPB2Peripheral(FL_RCC_RSTAPB_OPA); + FL_RCC_DisableResetAPB2Peripheral(FL_RCC_RSTAPB_OPA); + /* 关闭外设总线时钟和工作时钟 */ + FL_RCC_DisableGroup1BusClock(FL_RCC_GROUP1_BUSCLK_ANAC); + /* 锁定外设复位 */ + FL_RCC_DisablePeripheralReset(); + return FL_PASS; +} + +/** + * @brief 配置OPA + * + * @param OPAx 外设入口地址 + * @param initStruct 指向 @ref FL_OPA_InitTypeDef 结构体的指针 + * + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_OPA_Init(OPA_Type *OPAx, FL_OPA_InitTypeDef *initStruct) +{ + FL_ErrorStatus status = FL_PASS; + /* 入口参数检查 */ + assert_param(IS_OPA_ALL_INSTANCE(OPAx)); + assert_param(IS_FL_OPA_INP_CHANNAL(initStruct->INP)); + assert_param(IS_FL_OPA_INN_CHANNAL(initStruct->INN)); + assert_param(IS_FL_OPA_MODE(initStruct->mode)); + assert_param(IS_FL_OPA_DIGITALFILTER(initStruct->digitalFilter)); + assert_param(IS_FL_OPA_NEGTIVE_TO_PIN(initStruct->negtiveToPin)); + assert_param(IS_FL_OPA_LOW_POWER_MODE(initStruct->lowPowermode)); + assert_param(IS_FL_OPA_GAIN(initStruct->gain)); + /*总线时钟使能*/ + FL_RCC_EnableGroup1BusClock(FL_RCC_GROUP1_BUSCLK_ANAC); + /*配置模式*/ + FL_OPA_SetMode(OPAx, initStruct->mode); + /*配置反向输入*/ + FL_OPA_SetINNSource(OPAx, initStruct->INN); + /*配置正向输入*/ + FL_OPA_SetINPSource(OPAx, initStruct->INP); + /*配置低功耗模式*/ + if(initStruct->lowPowermode == FL_ENABLE) + { + FL_OPA_EnableLowPowerMode(OPAx); + } + if(initStruct->mode == FL_OPA_MODE_PGA) + { + /*配置PGA增益*/ + FL_OPA_PGA_SetGain(OPAx, initStruct->gain); + if(initStruct->negtiveToPin == FL_ENABLE) + { + /*配置PGA模式下反向输入端接到PIN*/ + FL_OPA_PGA_EnableINNConnectToPin(OPAx); + } + } + return status; +} + +/** + * @brief 将 @ref FL_OPA_InitTypeDef 结构体初始化为默认配置 + * @param initStruct 指向 @ref FL_OPA_InitTypeDef 结构体的指针 + * + * @retval None + */ + +void FL_OPA_StructInit(FL_OPA_InitTypeDef *initStruct) +{ + initStruct->INP = FL_OPA_INP_SOURCE_INP1; + initStruct->INN = FL_OPA_INN_SOURCE_INN1; + initStruct->mode = FL_OPA_MODE_STANDALONE; + initStruct->digitalFilter = FL_DISABLE; + initStruct->negtiveToPin = FL_DISABLE; + initStruct->gain = FL_OPA_GAIN_X2; + initStruct->lowPowermode = FL_DISABLE; +} + +/** + *@} + */ + +/** + *@} + */ + +/** + *@} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_pmu.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_pmu.c new file mode 100644 index 0000000000..8ea2bae768 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_pmu.c @@ -0,0 +1,144 @@ +/** + **************************************************************************************************** + * @file fm33lc0xx_fl_pmu.c + * @author FMSH Application Team + * @brief Src file of PMU FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_rmu.h" +#include "fm33lc0xx_fl_pmu.h" +#include "fm33_assert.h" + + + + +#define IS_FL_PMU_INSTANCE(INSTANCE) (((INSTANCE) == PMU)) + +#define IS_FL_PMU_MODE(__VALUE__) (((__VALUE__) == FL_PMU_POWER_MODE_ACTIVE_OR_LPACTIVE)||\ + ((__VALUE__) == FL_PMU_POWER_MODE_LPRUN_ONLY)||\ + ((__VALUE__) == FL_PMU_POWER_MODE_SLEEP_OR_DEEPSLEEP)) + +#define IS_FL_PMU_COREVOLTAGESCALING(__VALUE__) (((__VALUE__) == FL_DISABLE)||\ + ((__VALUE__) == FL_ENABLE)) + +#define IS_FL_PMU_DEEPSLEEP(__VALUE__) (((__VALUE__) == FL_PMU_SLEEP_MODE_DEEP)||\ + ((__VALUE__) == FL_PMU_SLEEP_MODE_NORMAL)) + +#define IS_FL_PMU_WAKEUPFREQUENCY(__VALUE__) (((__VALUE__) == FL_PMU_RCHF_WAKEUP_FREQ_8MHZ)||\ + ((__VALUE__) == FL_PMU_RCHF_WAKEUP_FREQ_16MHZ)||\ + ((__VALUE__) == FL_PMU_RCHF_WAKEUP_FREQ_24MHZ)) + +#define IS_FL_PMU_LDOLOWMODE(__VALUE__) (((__VALUE__) == FL_PMU_LDO_LPM_DISABLE)||\ + ((__VALUE__) == FL_PMU_LDO_LPM_ENABLE)) + +#define IS_FL_PMU_WAKEUPDELAY(__VALUE__) (((__VALUE__) == FL_PMU_WAKEUP_DELAY_0US)||\ + ((__VALUE__) == FL_PMU_WAKEUP_DELAY_2US)||\ + ((__VALUE__) == FL_PMU_WAKEUP_DELAY_4US)||\ + ((__VALUE__) == FL_PMU_WAKEUP_DELAY_8US)) + +/** + *@} + */ +/** @addtogroup PMU_FL_EF_Init + * @{ + */ +/** + * @brief 复位PMU外设 + * + * @param 外设入口地址 + * + * @retval 返回错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_PMU_Sleep_DeInit(PMU_Type *PMUx) +{ + FL_ErrorStatus status = FL_FAIL; + /* 参数合法性检查 */ + assert_param(IS_FL_PMU_INSTANCE(PMUx)); + PMUx->CR = 0x00060000U; + PMUx->WKTR = 0xC0000001U; + PMUx->IER = 0x00000000U; + status = FL_PASS; + return status; +} + + +/** + * @brief 根据LPM_InitStruct结构体包含的配置信息配置PMU寄存器 + * + * @note 为更好的睡眠功耗用户可能需要根据实际应用，调用 @ref fm33lc0xx_fl_pmu.h中的其他接口 + * 来完成睡眠前的模式配置，包括睡眠行为和唤醒后的行为（注：此函数会关闭BOR） + * @param PMUx 外设入口地址 + * @param LPM_InitStruct 指向一个 @ref LL_PMU_SleepInitTypeDef 类型的结构体，它包含指定LPUART外设的配置信息 + * + * @retval ErrorStatus枚举值 + * -FL_FAIL 配置过程发生错误 + * -FL_PASS LPUART配置成功 + */ +FL_ErrorStatus FL_PMU_Sleep_Init(PMU_Type *PMUx, FL_PMU_SleepInitTypeDef *LPM_InitStruct) +{ + FL_ErrorStatus status = FL_FAIL; + /* 参数合法性检查 */ + assert_param(IS_FL_PMU_INSTANCE(PMUx)); + assert_param(IS_FL_PMU_LDOLOWMODE(LPM_InitStruct->LDOLowPowerMode)); + assert_param(IS_FL_PMU_COREVOLTAGESCALING(LPM_InitStruct->coreVoltageScaling)); + assert_param(IS_FL_PMU_DEEPSLEEP(LPM_InitStruct->deepSleep)); + assert_param(IS_FL_PMU_WAKEUPFREQUENCY(LPM_InitStruct->wakeupFrequency)); + assert_param(IS_FL_PMU_WAKEUPDELAY(LPM_InitStruct->wakeupDelay)); + /* 唤醒延时 */ + FL_PMU_SetWakeupDelay(PMUx, LPM_InitStruct->wakeupDelay); + /* 唤醒后RCHF的频率 */ + FL_PMU_SetRCHFWakeupFrequency(PMUx, LPM_InitStruct->wakeupFrequency); + /* 睡眠下内核电压配置 */ + if(LPM_InitStruct->coreVoltageScaling == FL_ENABLE) + { + FL_PMU_EnableCoreVoltageScaling(PMUx); + } + else + { + FL_PMU_DisableCoreVoltageScaling(PMUx); + } + /* M0系统控制器,一般配置为0即可*/ + SCB->SCR = 0; + /* 睡眠模式 */ + FL_PMU_SetSleepMode(PMUx, LPM_InitStruct->deepSleep); + status = FL_PASS; + return status; +} + +/** + * @brief LPM_InitStruct 为默认配置 + * @param LPM_InitStruct 指向需要将值设置为默认配置的结构体 @ref FL_PMU_SleepInitTypeDef structure + * 结构体 + * @retval None + */ +void FL_PMU_StructInit(FL_PMU_SleepInitTypeDef *LPM_InitStruct) +{ + LPM_InitStruct->deepSleep = FL_PMU_SLEEP_MODE_NORMAL; + LPM_InitStruct->LDOLowPowerMode = FL_PMU_LDO_LPM_DISABLE; + LPM_InitStruct->wakeupFrequency = FL_PMU_RCHF_WAKEUP_FREQ_8MHZ; + LPM_InitStruct->wakeupDelay = FL_PMU_WAKEUP_DELAY_2US; + LPM_InitStruct->coreVoltageScaling = FL_DISABLE; +} +/** + *@} + */ +/** + *@} + */ +/*********************** (C) COPYRIGHT Fudan Microelectronics *****END OF FILE************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_rcc.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_rcc.c new file mode 100644 index 0000000000..8079513196 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_rcc.c @@ -0,0 +1,331 @@ +/** + **************************************************************************************************** + * @file fm33lC0xx_fl_rcc.c + * @author FMSH Application Team + * @brief Src file of RCC FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "system_fm33lc0xx.h" +#include "fm33lc0xx_fl_rcc.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_FL_EF_Operation + * @{ + */ + +/** + * @brief 获取USB提供给系统总线时钟的频率 + * + * @retval USB提供给SYSCLK的时钟频率(Hz) + */ +uint32_t FL_RCC_GetUSBClockFreqToSysclk(void) +{ + if(FL_RCC_GetUSBClockSource() == FL_RCC_USB_CLOCK_SELECT_48M) + { + return 48000000; + } + else + { + return 60000000; + } +} + +/** + * @brief 获取系统当前工作时钟SYSCLK + * + * @note 函数中用到了 @ref XTHF_VALUE 宏，这个宏应该被定义为外部晶振的输入频率值 + * + * @retval 系统时钟频率(Hz) + * + */ +uint32_t FL_RCC_GetSystemClockFreq(void) +{ + uint32_t frequency = 0; + /* 获取系统时钟源 */ + switch(FL_RCC_GetSystemClockSource()) + { + /* 系统时钟源为内部RCHF */ + case FL_RCC_SYSTEM_CLK_SOURCE_RCHF: + /* 内部RCHF默认为8MHz ,可以配置为16或24M */ + frequency = FL_RCC_GetRCHFClockFreq(); + break; + /* 系统时钟源为XTHF */ + case FL_RCC_SYSTEM_CLK_SOURCE_XTHF: + frequency = XTHF_VALUE; + break; + /* 系统时钟源为PLL */ + case FL_RCC_SYSTEM_CLK_SOURCE_PLL: + frequency = FL_RCC_GetPLLClockFreq(); + break; + /* 系统时钟源为内部RCMF */ + case FL_RCC_SYSTEM_CLK_SOURCE_RCMFPSC: + /* 根据RC4M的分频配置得出系统时钟 */ + frequency = FL_RCC_GetRC4MClockFreq(); + break; + /* 系统时钟源为XTLF */ + case FL_RCC_SYSTEM_CLK_SOURCE_XTLF: + /* 根据外部晶振的频率得出系统时钟 */ + frequency = XTLF_VALUE; + break; + case FL_RCC_SYSTEM_CLK_SOURCE_USBCLK: + /* USB时钟频率获取*/ + frequency = FL_RCC_GetUSBClockFreqToSysclk(); + break; + /* 系统时钟源为RCLP */ + case FL_RCC_SYSTEM_CLK_SOURCE_RCLP: + frequency = 32000; + break; + default: + frequency = FL_RCC_GetRCHFClockFreq(); + break; + } + return frequency; +} +/** + * @brief 获取AHB总线时钟频率 + * + * @retval AHB总线时钟频率(Hz) + * + */ +uint32_t FL_RCC_GetAHBClockFreq(void) +{ + uint32_t frequency = 0; + /* 获取AHB分频系数，AHB源自系统主时钟 */ + switch(FL_RCC_GetAHBPrescaler()) + { + case FL_RCC_AHBCLK_PSC_DIV1: + frequency = FL_RCC_GetSystemClockFreq(); + break; + case FL_RCC_AHBCLK_PSC_DIV2: + frequency = FL_RCC_GetSystemClockFreq() / 2; + break; + case FL_RCC_AHBCLK_PSC_DIV4: + frequency = FL_RCC_GetSystemClockFreq() / 4; + break; + case FL_RCC_AHBCLK_PSC_DIV8: + frequency = FL_RCC_GetSystemClockFreq() / 8; + break; + case FL_RCC_AHBCLK_PSC_DIV16: + frequency = FL_RCC_GetSystemClockFreq() / 16; + break; + default: + frequency = FL_RCC_GetSystemClockFreq(); + break; + } + return frequency; +} + +/** + * @brief 获取当前系统的APB1总线时钟 + * + * @retval APB1总线时钟频率(Hz) + * + */ +uint32_t FL_RCC_GetAPB1ClockFreq(void) +{ + uint32_t frequency = 0; + /* 获取APB1分频系数，APB源自AHB */ + switch(FL_RCC_GetAPB1Prescaler()) + { + case FL_RCC_APB1CLK_PSC_DIV1: + frequency = FL_RCC_GetAHBClockFreq(); + break; + case FL_RCC_APB1CLK_PSC_DIV2: + frequency = FL_RCC_GetAHBClockFreq() / 2; + break; + case FL_RCC_APB1CLK_PSC_DIV4: + frequency = FL_RCC_GetAHBClockFreq() / 4; + break; + case FL_RCC_APB1CLK_PSC_DIV8: + frequency = FL_RCC_GetAHBClockFreq() / 8; + break; + case FL_RCC_APB1CLK_PSC_DIV16: + frequency = FL_RCC_GetAHBClockFreq() / 16; + break; + default: + frequency = FL_RCC_GetAHBClockFreq(); + break; + } + return frequency; +} +/** + * @brief 获取当前系统的APB2总线时钟 + * + * @retval APB2总线时钟频率(Hz) + * + */ +uint32_t FL_RCC_GetAPB2ClockFreq(void) +{ + uint32_t frequency = 0; + /* 获取APB2分频系数，APB源自AHB */ + switch(FL_RCC_GetAPB2Prescaler()) + { + case FL_RCC_APB2CLK_PSC_DIV1: + frequency = FL_RCC_GetAHBClockFreq(); + break; + case FL_RCC_APB2CLK_PSC_DIV2: + frequency = FL_RCC_GetAHBClockFreq() / 2; + break; + case FL_RCC_APB2CLK_PSC_DIV4: + frequency = FL_RCC_GetAHBClockFreq() / 4; + break; + case FL_RCC_APB2CLK_PSC_DIV8: + frequency = FL_RCC_GetAHBClockFreq() / 8; + break; + case FL_RCC_APB2CLK_PSC_DIV16: + frequency = FL_RCC_GetAHBClockFreq() / 16; + break; + default: + frequency = FL_RCC_GetAHBClockFreq(); + break; + } + return frequency; +} +/** + * @brief 获取RC4M输出时钟频率 + * + * @retval RC4M输出时钟频率(Hz) + * + */ +uint32_t FL_RCC_GetRC4MClockFreq(void) +{ + uint32_t frequency = 0; + switch(FL_RCC_RCMF_GetPrescaler()) + { + case FL_RCC_RCMF_PSC_DIV1: + frequency = 4000000; + break; + case FL_RCC_RCMF_PSC_DIV4: + frequency = 1000000; + break; + case FL_RCC_RCMF_PSC_DIV8: + frequency = 500000; + break; + case FL_RCC_RCMF_PSC_DIV16: + frequency = 250000; + break; + default: + frequency = 4000000; + break; + } + return frequency; +} +/** + * @brief 获取RCHF输出时钟频率 + * + * @retval 返回RCHF输出时钟频率(Hz) + * + */ +uint32_t FL_RCC_GetRCHFClockFreq(void) +{ + uint32_t frequency = 0; + switch(FL_RCC_RCHF_GetFrequency()) + { + case FL_RCC_RCHF_FREQUENCY_8MHZ: + frequency = 8000000; + break; + case FL_RCC_RCHF_FREQUENCY_16MHZ: + frequency = 16000000; + break; + case FL_RCC_RCHF_FREQUENCY_24MHZ: + frequency = 24000000; + break; + default: + frequency = 8000000; + break; + } + return frequency; +} +/** + * @brief 获取PLL输出时钟频率 + * + * @retval 返回PLL输出时钟频率(Hz) + * + */ +uint32_t FL_RCC_GetPLLClockFreq(void) +{ + uint32_t frequency = 0; + uint32_t multiplier = 0; + /* 获取PLL时钟源 */ + switch(FL_RCC_PLL_GetClockSource()) + { + case FL_RCC_PLL_CLK_SOURCE_RCHF: + /* 获取RCHF配置主频 */ + frequency = FL_RCC_GetRCHFClockFreq(); + break; + case FL_RCC_PLL_CLK_SOURCE_XTHF: + frequency = XTHF_VALUE; + break; + default: + frequency = FL_RCC_GetRCHFClockFreq(); + break; + } + /* 获取PLL时钟分频系数 */ + switch(FL_RCC_PLL_GetPrescaler()) + { + case FL_RCC_PLL_PSC_DIV1: + break; + case FL_RCC_PLL_PSC_DIV2: + frequency /= 2; + break; + case FL_RCC_PLL_PSC_DIV4: + frequency /= 4; + break; + case FL_RCC_PLL_PSC_DIV8: + frequency /= 8; + break; + case FL_RCC_PLL_PSC_DIV12: + frequency /= 12; + break; + case FL_RCC_PLL_PSC_DIV16: + frequency /= 16; + break; + case FL_RCC_PLL_PSC_DIV24: + frequency /= 24; + break; + case FL_RCC_PLL_PSC_DIV32: + frequency /= 32; + break; + default: + break; + } + multiplier = FL_RCC_PLL_ReadMultiplier() + 1; + frequency *= multiplier; + return frequency; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_rng.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_rng.c new file mode 100644 index 0000000000..75b4469829 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_rng.c @@ -0,0 +1,190 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_rng.c + * @author FMSH Application Team + * @brief Src file of RNG FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ + +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_rng.h" +#include "fm33_assert.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup RNG + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RNG_FL_Private_Macros +* @{ +*/ +#define IS_FL_RNG_INSTANCE(INTANCE) ((INTANCE) == RNG) + +#define IS_FL_RNG_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == FL_RCC_RNG_PSC_DIV1)||\ + ((__VALUE__) == FL_RCC_RNG_PSC_DIV2)||\ + ((__VALUE__) == FL_RCC_RNG_PSC_DIV4)||\ + ((__VALUE__) == FL_RCC_RNG_PSC_DIV8)||\ + ((__VALUE__) == FL_RCC_RNG_PSC_DIV16)||\ + ((__VALUE__) == FL_RCC_RNG_PSC_DIV32)) +/** + *@} + */ + +/** @addtogroup RNG_FL_EF_Init + * @{ + */ + +/** + * @brief 复位RNG + * + * @param RNGx 外设入口地址 + * + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_RNG_DeInit(RNG_Type *RNGx) +{ + assert_param(IS_FL_RNG_INSTANCE(RNGx)); + /* 使能外设复位 */ + FL_RCC_EnablePeripheralReset(); + /* 复位外设寄存器 */ + FL_RCC_EnableResetAPB2Peripheral(FL_RCC_RSTAPB_RNG); + FL_RCC_DisableResetAPB2Peripheral(FL_RCC_RSTAPB_RNG); + /* 关闭外设总线始时钟和工作时钟 */ + FL_RCC_DisableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_RNG); + /* 锁定外设复位 */ + FL_RCC_DisablePeripheralReset(); + return FL_PASS; +} + +/** + * @brief 配置RNG + * + * @param RNGx 外设入口地址 + * @param initStruct 指向 @ref FL_RNG_InitTypeDef 结构体的指针 + * + * @note RNG使用RCHF默认的8M作为时钟输入，经2分频后4M提供给RNG + * + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_RNG_Init(RNG_Type *RNGx) +{ + assert_param(IS_FL_RNG_INSTANCE(RNGx)); + /* RNG 使用RCHF作为工作时钟因此必须确认RCHF使能*/ + if(FL_RCC_RCHF_IsEnabled() != FL_SET) + { + FL_RCC_RCHF_Enable(); + } + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_RNG); + /* RNG 工作时钟预分频*/ + switch(FL_RCC_RCHF_GetFrequency()) + { + case FL_RCC_RCHF_FREQUENCY_8MHZ: + FL_RCC_SetRNGPrescaler(FL_RCC_RNG_PSC_DIV2); + break; + case FL_RCC_RCHF_FREQUENCY_16MHZ: + FL_RCC_SetRNGPrescaler(FL_RCC_RNG_PSC_DIV4); + break; + case FL_RCC_RCHF_FREQUENCY_24MHZ: + FL_RCC_SetRNGPrescaler(FL_RCC_RNG_PSC_DIV8); + break; + default: + FL_RCC_SetRNGPrescaler(FL_RCC_RNG_PSC_DIV2); + break; + } + /* RNG 工作时钟使能*/ + FL_RCC_EnableGroup2OperationClock(FL_RCC_GROUP2_OPCLK_RNG); + return FL_PASS; +} + +/** + * @brief 获取一次随机数 + * + * @note 如果返回值为0xFFFFFFFF 则说明随机数生成失败，请用户检查此函数的返回值，失败时重新生成 + * + * @retval 生成的随机数，生成失败返回0xFFFFFFFF + * + */ +uint32_t GetRandomNumber(void) +{ + uint32_t rn32; + FL_RNG_ClearFlag_RandomFail(RNG); + FL_RNG_Enable(RNGCTL); + /* 由于LFSR循环移位周期是32cycle，为保证随机数质量，应用应保证两次读取RNGOUT之间的间隔大于32个TRNG_CLK周期 */ + FL_DelayUs(12); + FL_RNG_Disable(RNGCTL); + rn32 = FL_RNG_ReadData(RNG); + if(FL_RNG_IsActiveFlag_RandomFail(RNG)) + { + FL_RNG_ClearFlag_RandomFail(RNG); + return 0xFFFFFFFF; + } + return rn32; +} + +/** + * @brief 获取CRC32 + * + * @param dataIn 待计算的数据 + * + * @retval 计算得到的CRC32，计算失败返回0xFFFFFFFF + * + */ +uint32_t GetCrc32(uint32_t dataIn) +{ + uint32_t i = 0; + uint32_t crc32 = 0; + FL_RNG_CRC_WriteData(RNG, dataIn); + FL_RNG_ClearFlag_CRCComplete(RNG); + FL_RNG_CRC_Enable(RNG); + while(0 == FL_RNG_IsActiveFlag_CRCComplete(RNG)) + { + i++; + if(i > 600) + { break; } + } + if(i >= 600) + { + FL_RNG_ClearFlag_CRCComplete(RNG); + FL_RNG_Disable(RNGCTL); + return 0xFFFFFFFF; + } + FL_RNG_ClearFlag_CRCComplete(RNG); + crc32 = FL_RNG_ReadData(RNG); + FL_RNG_Disable(RNGCTL); + return crc32; +} + +/** + *@} + */ + +/** + *@} + */ + +/** + *@} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_rtc.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_rtc.c new file mode 100644 index 0000000000..c466b515de --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_rtc.c @@ -0,0 +1,185 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_rtc.c + * @author FMSH Application Team + * @brief Src file of RTC FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_rmu.h" +#include "fm33lc0xx_fl_rtc.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RTC_FL_Private_Macros + * @{ + */ + +#define IS_RTC_INSTANCE(RTCx) ((RTCx) == RTC) + +/** + * @} + */ + +/** @addtogroup RTC_FL_EF_Init + * @{ + */ + +/** + * @brief 复位RTC + * @param RTCx 外设入口地址 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_RTC_DeInit(RTC_Type *RTCx) +{ + FL_ErrorStatus result = FL_PASS; + /* Check the parameters */ + assert_param(IS_RTC_INSTANCE(RTCx)); + RTCx->IER = 0x00000000U; + RTCx->WER = 0x00000000U; + RTCx->ADJUST = 0x00000000U; + RTCx->ADSIGN = 0x00000000U; + RTCx->ALARM = 0x00000000U; + RTCx->BCDDAY = 0x00000000U; + RTCx->BCDHOUR = 0x00000000U; + RTCx->BCDMIN = 0x00000000U; + RTCx->BCDMONTH = 0x00000000U; + RTCx->BCDSEC = 0x00000000U; + RTCx->BCDWEEK = 0x00000000U; + RTCx->BCDYEAR = 0x00000000U; + RTCx->SBSCNT = 0x00000000U; + RTCx->TMSEL = 0x00000000U; + RTCx->WER = 0x00000000U; + return result; +} + +/** + * @brief 配置RTC + * @param RTCx 外设入口地址 + * @param initStruct 指向 @ref FL_RTC_InitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_RTC_Init(RTC_Type *RTCx, FL_RTC_InitTypeDef *initStruct) +{ + /* 参数检查 */ + assert_param(IS_RTC_INSTANCE(RTCx)); + /* 时钟总线使能配置 */ + FL_RCC_EnableGroup1BusClock(FL_RCC_GROUP1_BUSCLK_RTC); + /* 配置时间 */ + FL_RTC_ConfigTime(RTCx, initStruct); + return FL_PASS; +} + +/** + * @brief 设置RTC实时时间 + * @param RTCx 外设入口地址 + * @param initStruct 指向 @ref FL_RTC_InitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_RTC_ConfigTime(RTC_Type *RTCx, FL_RTC_InitTypeDef *initStruct) +{ + /* 使能时间配置 */ + FL_RTC_WriteEnable(RTCx); + /* 配置秒 */ + FL_RTC_WriteSecond(RTCx, initStruct->second); + /* 配置分钟 */ + FL_RTC_WriteMinute(RTCx, initStruct->minute); + /* 配置小时 */ + FL_RTC_WriteHour(RTCx, initStruct->hour); + /* 配置日期 */ + FL_RTC_WriteDay(RTCx, initStruct->day); + /* 配置周 */ + FL_RTC_WriteWeek(RTCx, initStruct->week); + /* 配置月 */ + FL_RTC_WriteMonth(RTCx, initStruct->month); + /* 配置年 */ + FL_RTC_WriteYear(RTCx, initStruct->year); + /* 锁定时间配置 */ + FL_RTC_WriteDisable(RTCx); + return FL_PASS; +} + +/** + * @brief 获取RTC实时时间并保存到指定结构体中 + * @param RTCx 外设入口地址 + * @param initStruct 指向 @ref FL_RTC_InitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 获取成功 + * -FL_FAIL 获取过程发生错误 + */ +FL_ErrorStatus FL_RTC_GetTime(RTC_Type *RTCx, FL_RTC_InitTypeDef *initStruct) +{ + /* 配置秒 */ + initStruct->second = FL_RTC_ReadSecond(RTCx); + /* 配置分钟 */ + initStruct->minute = FL_RTC_ReadMinute(RTCx); + /* 配置小时 */ + initStruct->hour = FL_RTC_ReadHour(RTCx); + /* 配置日期 */ + initStruct->day = FL_RTC_ReadDay(RTCx); + /* 配置周 */ + initStruct->week = FL_RTC_ReadWeek(RTCx); + /* 配置月 */ + initStruct->month = FL_RTC_ReadMonth(RTCx); + /* 配置年 */ + initStruct->year = FL_RTC_ReadYear(RTCx); + return FL_PASS; +} + +/** + * @brief 将 @ref FL_RTC_InitTypeDef 结构体初始化为默认配置 + * @param initStruct 指向 @ref FL_RTC_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_RTC_StructInit(FL_RTC_InitTypeDef *initStruct) +{ + initStruct->year = 0x00; + initStruct->month = 0x00; + initStruct->day = 0x00; + initStruct->week = 0x00; + initStruct->hour = 0x00; + initStruct->minute = 0x00; + initStruct->second = 0x00; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_spi.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_spi.c new file mode 100644 index 0000000000..e132710e87 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_spi.c @@ -0,0 +1,208 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_spi.c + * @author FMSH Application Team + * @brief Src file of SPI FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_spi.h" +#include "fm33_assert.h" +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup Private_Macros + * @{ + */ +#define IS_FL_SPI_INSTANCE(INTANCE) (((INTANCE) == SPI1)||\ + ((INTANCE) == SPI2)) + +#define IS_FL_SPI_MODE(__VALUE__) (((__VALUE__) == FL_SPI_WORK_MODE_SLAVE)||\ + ((__VALUE__) == FL_SPI_WORK_MODE_MASTER)) + +#define IS_FL_SPI_BITORDER(__VALUE__) (((__VALUE__) == FL_SPI_BIT_ORDER_MSB_FIRST)||\ + ((__VALUE__) == FL_SPI_BIT_ORDER_LSB_FIRST)) + +#define IS_FL_SPI_DATAWIDT(__VALUE__) (((__VALUE__) == FL_SPI_DATA_WIDTH_8B)||\ + ((__VALUE__) == FL_SPI_DATA_WIDTH_16B)||\ + ((__VALUE__) == FL_SPI_DATA_WIDTH_24B)||\ + ((__VALUE__) == FL_SPI_DATA_WIDTH_32B)) + +#define IS_FL_SPI_CLOCK_PHASE(__VALUE__) (((__VALUE__) == FL_SPI_PHASE_EDGE1)||\ + ((__VALUE__) == FL_SPI_PHASE_EDGE2)) + +#define IS_FL_SPI_CLOCK_POLARITY(__VALUE__) (((__VALUE__) == FL_SPI_POLARITY_NORMAL)||\ + ((__VALUE__) == FL_SPI_POLARITY_INVERT)) + +#define IS_FL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == FL_SPI_BAUDRATE_DIV2)||\ + ((__VALUE__) == FL_SPI_BAUDRATE_DIV4)||\ + ((__VALUE__) == FL_SPI_BAUDRATE_DIV8)||\ + ((__VALUE__) == FL_SPI_BAUDRATE_DIV16)||\ + ((__VALUE__) == FL_SPI_BAUDRATE_DIV32)||\ + ((__VALUE__) == FL_SPI_BAUDRATE_DIV64)||\ + ((__VALUE__) == FL_SPI_BAUDRATE_DIV128)||\ + ((__VALUE__) == FL_SPI_BAUDRATE_DIV256)) + + +#define IS_FL_SPI_TANSFERMODE(__VALUE__) (((__VALUE__) == FL_SPI_TRANSFER_MODE_FULL_DUPLEX)||\ + ((__VALUE__) == FL_SPI_TRANSFER_MODE_HALF_DUPLEX)) + + +/** + * @} + */ + +/** @addtogroup SPI_FL_EF_Init + * @{ + */ + +/** + * @brief 复位SPI + * @param SPIx 外设入口地址 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_SPI_DeInit(SPI_Type *SPIx) +{ + assert_param(IS_FL_SPI_INSTANCE(SPIx)); + /* 使能外设复位 */ + FL_RCC_EnablePeripheralReset(); + if(SPIx == SPI1) + { + /* 复位SPI外设寄存器 */ + FL_RCC_EnableResetAPB2Peripheral(FL_RCC_RSTAPB_SPI1); + FL_RCC_DisableResetAPB2Peripheral(FL_RCC_RSTAPB_SPI1); + /* 关闭外设总线时钟和工作时钟 */ + FL_RCC_DisableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_SPI1); + } + else + if(SPIx == SPI2) + { + /* 复位SPI外设寄存器 */ + FL_RCC_EnableResetAPB1Peripheral(FL_RCC_RSTAPB_SPI2); + FL_RCC_DisableResetAPB1Peripheral(FL_RCC_RSTAPB_SPI2); + /* 关闭外设总线时钟和工作时钟 */ + FL_RCC_DisableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_SPI2); + } + else + { + FL_RCC_DisablePeripheralReset(); + return FL_FAIL; + } + /* 锁定外设复位 */ + FL_RCC_DisablePeripheralReset(); + return FL_PASS; +} + +/** + * @brief 配置SPI + * @param SPIx 外设入口地址 + * @param initStruct 指向 @ref FL_SPI_InitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_SPI_Init(SPI_Type *SPIx, FL_SPI_InitTypeDef *initStruct) +{ + assert_param(IS_FL_SPI_INSTANCE(SPIx)); + assert_param(IS_FL_SPI_MODE(initStruct->mode)); + assert_param(IS_FL_SPI_BITORDER(initStruct->bitOrder)); + assert_param(IS_FL_SPI_DATAWIDT(initStruct->dataWidth)); + assert_param(IS_FL_SPI_BAUDRATE(initStruct->baudRate)); + assert_param(IS_FL_SPI_CLOCK_PHASE(initStruct->clockPhase)); + assert_param(IS_FL_SPI_CLOCK_POLARITY(initStruct->clockPolarity)); + if(SPIx == SPI1) + { + /* 外设总线时钟 */ + FL_RCC_EnableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_SPI1); + } + else + if(SPIx == SPI2) + { + /* 外设总线时钟 */ + FL_RCC_EnableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_SPI2); + } + else + { + return FL_FAIL; + } + /* 选择NSS脚控制模式 */ + if(initStruct->softControl == FL_ENABLE) + { + FL_SPI_EnableSSNSoftControl(SPIx); + } + else + { + FL_SPI_DisableSSNSoftControl(SPIx); + } + /* 外设工作主从模式 */ + FL_SPI_SetWorkMode(SPIx, initStruct->mode); + /* 总线通讯速率 */ + FL_SPI_SetClockDivision(SPIx, initStruct->baudRate); + /* 数据bit方向 */ + FL_SPI_SetBitOrder(SPIx, initStruct->bitOrder); + /* 总线数据位宽 */ + FL_SPI_SetDataWidth(SPIx, initStruct->dataWidth); + /* 时钟相位 */ + FL_SPI_SetClockPhase(SPIx, initStruct->clockPhase); + /* 传输模式 双工半双工 */ + FL_SPI_SetTransferMode(SPIx, initStruct->transferMode); + /* 时钟极性 */ + FL_SPI_SetClockPolarity(SPIx, initStruct->clockPolarity); + /* 使能 外设*/ + FL_SPI_Enable(SPIx); + return FL_PASS; +} + +/** + * @brief 将 @ref FL_SPI_InitTypeDef 结构体初始化为默认配置 + * @param initStruct 指向 @ref FL_SPI_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_SPI_StructInit(FL_SPI_InitTypeDef *initStruct) +{ + initStruct->softControl = FL_DISABLE; + initStruct->mode = FL_SPI_WORK_MODE_MASTER; + initStruct->baudRate = FL_SPI_CLK_DIV8; + initStruct->bitOrder = FL_SPI_BIT_ORDER_MSB_FIRST; + initStruct->dataWidth = FL_SPI_DATA_WIDTH_8B; + initStruct->clockPolarity = FL_SPI_POLARITY_NORMAL; + initStruct->clockPhase = FL_SPI_PHASE_EDGE1; + initStruct->transferMode = FL_SPI_TRANSFER_MODE_FULL_DUPLEX; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_svd.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_svd.c new file mode 100644 index 0000000000..5bb0bb54e0 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_svd.c @@ -0,0 +1,166 @@ +/** + **************************************************************************************************** + * @file fm33lc0xx_fl_svd.c + * @author FMSH Application Team + * @brief Src file of SVD FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_rmu.h" +#include "fm33lc0xx_fl_svd.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup SVD + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup SVD_FL_Private_Macros + * @{ + */ +#define IS_SVD_INSTANCE(INSTANCE) (((INSTANCE) == SVD)) + +#define IS_FL_SVD_WARNING_THRESHOLD_LEVEL(__VALUE__) (((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP0)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP1)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP2)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP3)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP4)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP5)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP6)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP7)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP8)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP9)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP10)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP11)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP12)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP13)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP14)||\ + ((__VALUE__) == FL_SVD_WARNING_THRESHOLD_GROUP15)) + +#define IS_FL_SVD_SVSCONFIG(__VALUE__) (((__VALUE__) == FL_DISABLE)||\ + ((__VALUE__) == FL_ENABLE)) + +#define IS_FL_SVD_REFERENCE_VOLTAGE(__VALUE__) (((__VALUE__) == FL_SVD_REFERENCE_1P2V)||\ + ((__VALUE__) == FL_SVD_REFERENCE_1P1V)||\ + ((__VALUE__) == FL_SVD_REFERENCE_1P0V)) + +#define IS_FL_SVD_DIGITAL_FILTER(__VALUE__) (((__VALUE__) == FL_DISABLE)||\ + ((__VALUE__) == FL_ENABLE)) +/** + *@} + */ + +/** @addtogroup SVD_FL_EF_Init + * @{ + */ + +/** + * @brief 复位SVD外设 + * @param SVDx 外设入口地址 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_SVD_DeInit(SVD_Type *SVDx) +{ + FL_ErrorStatus status = FL_PASS; + /* 入口参数合法性断言 */ + assert_param(IS_SVD_INSTANCE(SVDx)); + SVDx->CFGR = 0x00000C08U; + SVDx->CR = 0x00000000U; + SVDx->IER = 0x00000000U; + SVDx->VSR = 0x00000004U; + return (status); +} + +/** + * @brief 配置SVD + * @param SVDx 外设入口地址 + * @param initStruct 指向 @ref FL_SVD_InitTypeDef 结构体的指针 + * + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_SVD_Init(SVD_Type *SVDx, FL_SVD_InitTypeDef *initStruct) +{ + FL_ErrorStatus status = FL_FAIL; + /* 参数合法性检查 */ + assert_param(IS_SVD_INSTANCE(SVDx)); + assert_param(IS_FL_SVD_WARNING_THRESHOLD_LEVEL(initStruct->warningThreshold)); + assert_param(IS_FL_SVD_SVSCONFIG(initStruct->SVSChannel)); + assert_param(IS_FL_SVD_REFERENCE_VOLTAGE(initStruct->referenceVoltage)); + assert_param(IS_FL_SVD_DIGITAL_FILTER(initStruct->digitalFilter)); + /* 使能工作时钟 */ + FL_RCC_EnableGroup1BusClock(FL_RCC_GROUP1_BUSCLK_ANAC); + /* 检测阈值 */ + FL_SVD_SetWarningThreshold(SVDx, initStruct->warningThreshold); + /* 参考电压通道选择 */ + FL_SVD_EnableReference(SVD, initStruct->referenceVoltage); + /* 外部通道配置 */ + if(initStruct->SVSChannel == FL_ENABLE) + { + FL_SVD_EnableSVSChannel(SVDx); + } + else + { + FL_SVD_DisableSVSChannel(SVDx); + } + /* 数字滤波配置 */ + if(initStruct->digitalFilter == FL_ENABLE) + { + FL_SVD_EnableDigitalFilter(SVDx); + } + else + { + FL_SVD_DisableDigitalFilter(SVDx); + } + status = FL_PASS; + return status; +} + +/** + * @brief 将 @ref FL_SVD_InitTypeDef 结构体初始化为默认配置 + * @param initStruct 指向 @ref FL_SVD_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_SVD_StructInit(FL_SVD_InitTypeDef *initStruct) +{ + initStruct->SVSChannel = FL_DISABLE; + initStruct->digitalFilter = FL_ENABLE; + initStruct->referenceVoltage = FL_SVD_REFERENCE_1P0V; + initStruct->warningThreshold = FL_SVD_WARNING_THRESHOLD_GROUP0; +} + +/** + *@} + */ + +/** + *@} + */ + +/** + *@} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_u7816.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_u7816.c new file mode 100644 index 0000000000..3c4b7f4c60 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_u7816.c @@ -0,0 +1,236 @@ +/** + ******************************************************************************************************* + * @file fm33lc0xx_fl_u7816.c + * @author FMSH Application Team + * @brief Src file of U7816 FL Module + ******************************************************************************************************* + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + ******************************************************************************************************* + */ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_rmu.h" +#include "fm33lc0xx_fl_u7816.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup U7816 + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup U7816_FL_Private_Macros + * @{ + */ + + +#define IS_FL_U7816_INSTANCE(INTANCE) ((INTANCE) == U7816) + +#define IS_FL_U7816_CLOCK_FRQUENCE(__VALUE__) (((__VALUE__) >=1000000)||\ + ((__VALUE__) <= 5000000)) + +#define IS_FL_U7816_TX_PARITHERROR_AUTO_RETRY(__VALUE__) (((__VALUE__) == FL_DISABLE)||\ + ((__VALUE__) == FL_ENABLE)) + +#define IS_FL_U7816_RETRY_CNT(__VALUE__) (((__VALUE__) == FL_U7816_RETRY_COUNT_1)||\ + ((__VALUE__) == FL_U7816_RETRY_COUNT_3)) + +#define IS_FL_U7816_BLOCKGUARD(__VALUE__) (((__VALUE__) == FL_ENABLE)||\ + ((__VALUE__) == FL_DISABLE)) + +#define IS_FL_U7816_AUTO_PULL(__VALUE__) (((__VALUE__) == FL_ENABLE)||\ + ((__VALUE__) == FL_DISABLE)) + +#define IS_FL_U7816_PARITH(__VALUE__) (((__VALUE__) == FL_U7816_PARITY_EVEN)||\ + ((__VALUE__) == FL_U7816_PARITY_ODD )||\ + ((__VALUE__) == FL_U7816_PARITY_ALWAYS_1)||\ + ((__VALUE__) == FL_U7816_PARITY_NONE)) + +#define IS_FL_U7816_TX_GUARD(__VALUE__) (((__VALUE__) == FL_U7816_TX_GUARD_TIME_2ETU)||\ + ((__VALUE__) == FL_U7816_TX_GUARD_TIME_3ETU)) + +#define IS_FL_U7816_RX_GUARD(__VALUE__) (((__VALUE__) == FL_U7816_RX_GUARD_TIME_2ETU)||\ + ((__VALUE__) == FL_U7816_RX_GUARD_TIME_1ETU)) + +#define IS_FL_U7816_ERROR_GUARD(__VALUE__) (((__VALUE__) == FL_U7816_ERROR_GUARD_TIME_2ETU)||\ + ((__VALUE__) == FL_U7816_ERROR_GUARD_TIME_1ETU)) + +#define IS_FL_U7816_ERROR_SIGNALWIDTH(__VALUE__) (((__VALUE__) == FL_U7816_ERROR_SIGNAL_WIDTH_2ETU)||\ + ((__VALUE__) == FL_U7816_ERROR_SIGNAL_WIDTH_1P5ETU)||\ + ((__VALUE__) == FL_U7816_ERROR_SIGNAL_WIDTH_1ETU)) + +#define IS_FL_U7816_RX_AUTO_ERROR_SIG(__VALUE__) (((__VALUE__) == FL_DISABLE)||\ + ((__VALUE__) == FL_ENABLE)) + +#define IS_FL_U7816_BIT_DIRECTION(__VALUE__) (((__VALUE__) == FL_U7816_BIT_ORDER_LSB_FIRST)||\ + ((__VALUE__) == FL_U7816_BIT_ORDER_MSB_FIRST)) +/** + * @} + */ + +/** @addtogroup UART_FL_EF_Init + * @{ + */ + +/** + * @brief 复位U7816外设 + * @param U7816x 外设入口地址 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_U7816_DeInit(U7816_Type *U7816x) +{ + assert_param(IS_FL_U7816_INSTANCE(U7816x)); + /* 使能外设复位 */ + FL_RCC_EnablePeripheralReset(); + /* 复位U7816外设寄存器 */ + FL_RCC_EnableResetAPB1Peripheral(FL_RCC_RSTAPB_U7816); + FL_RCC_DisableResetAPB1Peripheral(FL_RCC_RSTAPB_U7816); + /* 关闭外设总线始时钟和工作时钟 */ + FL_RCC_DisableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_U7816); + /* 锁定外设复位 */ + FL_RCC_DisablePeripheralReset(); + return FL_PASS; +} + +/** + * @brief 配置U7816 + * @param U7816x 外设入口地址 + * @param U7816_InitStruct 指向 @ref FL_U7816_InitTypeDef 结构体的指针 + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_U7816_Init(U7816_Type *U7816x, FL_U7816_InitTypeDef *U7816_InitStruct) +{ + uint32_t Fclk; + uint32_t tempClkdiv; + /* 参数检查 */ + assert_param(IS_FL_U7816_INSTANCE(U7816x)); + assert_param(IS_FL_U7816_CLOCK_FRQUENCE(U7816_InitStruct->outputClockFreqence)); + assert_param(IS_FL_U7816_TX_PARITHERROR_AUTO_RETRY(U7816_InitStruct->txAutoRetry)); + assert_param(IS_FL_U7816_RETRY_CNT(U7816_InitStruct->retryCnt)); + assert_param(IS_FL_U7816_BLOCKGUARD(U7816_InitStruct->blockGuard)); + assert_param(IS_FL_U7816_PARITH(U7816_InitStruct->parity)); + assert_param(IS_FL_U7816_RX_GUARD(U7816_InitStruct->rxGuardTime)); + assert_param(IS_FL_U7816_ERROR_GUARD(U7816_InitStruct->errorGuardTime)); + assert_param(IS_FL_U7816_ERROR_SIGNALWIDTH(U7816_InitStruct->errorSignalWidth)); + assert_param(IS_FL_U7816_RX_AUTO_ERROR_SIG(U7816_InitStruct->rxAutoErrorSignal)); + assert_param(IS_FL_U7816_BIT_DIRECTION(U7816_InitStruct->transferOrder)); + assert_param(IS_FL_U7816_AUTO_PULL(U7816_InitStruct->strongPullUp)); + assert_param(IS_FL_U7816_TX_GUARD(U7816_InitStruct->txGuardTime)); + /* 时钟使能 */ + FL_RCC_EnableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_U7816); + /* 卡时钟 */ + Fclk = FL_RCC_GetAPB1ClockFreq(); + tempClkdiv = Fclk / U7816_InitStruct->outputClockFreqence - 1; + FL_U7816_WriteClockDivision(U7816x, tempClkdiv); + /* 发送收到error signal后自动重发 */ + if(U7816_InitStruct->txAutoRetry == FL_ENABLE) + { + FL_U7816_EnableTXParityErrorAutoRetry(U7816x); + } + else + { + FL_U7816_DisableTXParityErrorAutoRetry(U7816x); + } + /* 发送失败重试次数 */ + FL_U7816_SetRetryCount(U7816x, U7816_InitStruct->retryCnt); + /* 发送一次之间的保护时间单位etu */ + FL_U7816_SetTXGuardTime(U7816x, U7816_InitStruct->txGuardTime); + /* 强上拉*/ + if(U7816_InitStruct->strongPullUp == FL_ENABLE) + { + FL_U7816_EnablePullup(U7816x); + } + else + { + FL_U7816_DisablePullup(U7816x); + } + /* 块保护,插入block guard time */ + if(U7816_InitStruct->blockGuard == FL_ENABLE) + { + FL_U7816_EnableBlockGuardTime(U7816x); + } + else + { + FL_U7816_DisableBlockGuardTime(U7816x); + } + /* 校验位 */ + FL_U7816_SetParity(U7816x, U7816_InitStruct->parity); + /* 接收一次之间的保护时间单位etu */ + FL_U7816_SetRXGuardTime(U7816x, U7816_InitStruct->rxGuardTime); + /* 错误之后的保护时间单位etu */ + FL_U7816_SetErrorGuardTime(U7816x, U7816_InitStruct->errorGuardTime); + /* 错误信号时间 单位etu */ + FL_U7816_SetErrorSignalWidth(U7816x, U7816_InitStruct->errorSignalWidth); + /* 接收校验错是否自动重发error signal */ + if(U7816_InitStruct->rxAutoErrorSignal == FL_ENABLE) + { + FL_U7816_EnableRXParityErrorAutoRetry(U7816x); + } + else + { + FL_U7816_DisableRXParityErrorAutoRetry(U7816x); + } + /* 传输bit方向 */ + FL_U7816_SetBitOrder(U7816x, U7816_InitStruct->transferOrder); + /* baud */ + FL_U7816_WriteBaudRate(U7816x, U7816_InitStruct->baud); + /* 额外保护时间单位etu */ + FL_U7816_WriteExtraGuardTime(U7816x, U7816_InitStruct->extraGuardTime); + return FL_PASS; +} + +/** + * @brief 将 @ref FL_U7816_InitTypeDef 结构体初始化为默认配置 + * @param U7816_InitStruct 指向 @ref FL_U7816_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_U7816_StructInit(FL_U7816_InitTypeDef *U7816_InitStruct) +{ + U7816_InitStruct->outputClockFreqence = 4000000; + U7816_InitStruct->txAutoRetry = FL_ENABLE; + U7816_InitStruct->retryCnt = FL_U7816_RETRY_COUNT_1; + U7816_InitStruct->strongPullUp = FL_ENABLE; + U7816_InitStruct->blockGuard = FL_DISABLE; + U7816_InitStruct->parity = FL_U7816_PARITY_EVEN; + U7816_InitStruct->rxGuardTime = FL_U7816_RX_GUARD_TIME_2ETU; + U7816_InitStruct->txGuardTime = FL_U7816_TX_GUARD_TIME_2ETU; + U7816_InitStruct->errorGuardTime = FL_U7816_ERROR_GUARD_TIME_1ETU; + U7816_InitStruct->errorSignalWidth = FL_U7816_ERROR_SIGNAL_WIDTH_2ETU; + U7816_InitStruct->rxAutoErrorSignal = FL_ENABLE; + U7816_InitStruct->transferOrder = FL_U7816_BIT_ORDER_LSB_FIRST; + U7816_InitStruct->baud = 372 - 1; + U7816_InitStruct->extraGuardTime = 0; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ + diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_uart.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_uart.c new file mode 100644 index 0000000000..437c015c9c --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_uart.c @@ -0,0 +1,353 @@ +/** + **************************************************************************************************** + * @file fm33lc0xx_fl_uart.c + * @author FMSH Application Team + * @brief Src file of UART FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_uart.h" +#include "fm33lc0xx_fl_rcc.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup UART_FL_Private_Macros + * @{ + */ + + +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == UART0)||\ + ((INSTANCE) == UART1)||\ + ((INSTANCE) == UART4)||\ + ((INSTANCE) == UART5)) + +#define IS_FL_UART_CLKSRC(__VALUE__) (((__VALUE__) == FL_RCC_UART1_CLK_SOURCE_APB1CLK)||\ + ((__VALUE__) == FL_RCC_UART1_CLK_SOURCE_RCHF)||\ + ((__VALUE__) == FL_RCC_UART1_CLK_SOURCE_SYSCLK)||\ + ((__VALUE__) == FL_RCC_UART1_CLK_SOURCE_RCMF_PSC)||\ + ((__VALUE__) == FL_RCC_UART0_CLK_SOURCE_APB1CLK)||\ + ((__VALUE__) == FL_RCC_UART0_CLK_SOURCE_RCHF)||\ + ((__VALUE__) == FL_RCC_UART0_CLK_SOURCE_SYSCLK)||\ + ((__VALUE__) == FL_RCC_UART0_CLK_SOURCE_RCMF_PSC)) + + +#define IS_FL_UART_DATAWIDTH(__VALUE__) (((__VALUE__) == FL_UART_DATA_WIDTH_7B)||\ + ((__VALUE__) == FL_UART_DATA_WIDTH_8B)||\ + ((__VALUE__) == FL_UART_DATA_WIDTH_9B)||\ + ((__VALUE__) == FL_UART_DATA_WIDTH_6B)) + +#define IS_FL_UART_STOPBITS(__VALUE__) (((__VALUE__) == FL_UART_STOP_BIT_WIDTH_1B)||\ + ((__VALUE__) == FL_UART_STOP_BIT_WIDTH_2B)) + +#define IS_FL_UART_PARITY(__VALUE__) (((__VALUE__) == FL_UART_PARITY_NONE)||\ + ((__VALUE__) == FL_UART_PARITY_EVEN)||\ + ((__VALUE__) == FL_UART_PARITY_ODD)) + +#define IS_FL_UART_DIRECTION(__VALUE__) (((__VALUE__) == FL_UART_DIRECTION_NONE)||\ + ((__VALUE__) == FL_UART_DIRECTION_RX)||\ + ((__VALUE__) == FL_UART_DIRECTION_TX)||\ + ((__VALUE__) == FL_UART_DIRECTION_TX_RX)) + +#define IS_FL_UART_INFRA_MODULATION(__VALUE__) (((__VALUE__) == FL_DISABLE)||\ + ((__VALUE__) == FL_ENABLE)) + + +#define IS_FL_UART_INFRARED_POLARITY(__VALUE__) (((__VALUE__) == FL_UART_INFRARED_POLARITY_NORMAL)||\ + ((__VALUE__) == FL_UART_INFRARED_POLARITY_INVERT)) + +#define IS_FL_UART_INFRARED_MODULATION_DUTY(__VALUE__) (((__VALUE__) <= 100)) + + +/** + * @} + */ + +/** @addtogroup UART_FL_EF_Init + * @{ + */ + +/** + * @brief 复位UART外设 + * @param UARTx 外设入口地址 + * @retval 错误状态，可能值: + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 复位未成功 + */ +FL_ErrorStatus FL_UART_DeInit(UART_Type *UARTx) +{ + FL_ErrorStatus status = FL_PASS; + /* 参数入口合法性 */ + assert_param(IS_UART_INSTANCE(UARTx)); + /* 外设复位使能 */ + FL_RCC_EnablePeripheralReset(); + if(UARTx == UART0) + { + /*复位UART*/ + FL_RCC_EnableResetAPB2Peripheral(FL_RCC_RSTAPB_UART0); + FL_RCC_DisableResetAPB2Peripheral(FL_RCC_RSTAPB_UART0); + /* 外设总线时钟关闭 */ + FL_RCC_DisableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_UART0); + /* 外设操作时钟关闭 */ + FL_RCC_DisableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_UART0); + } + else + if(UARTx == UART1) + { + /*复位UART*/ + FL_RCC_EnableResetAPB2Peripheral(FL_RCC_RSTAPB_UART1); + FL_RCC_DisableResetAPB2Peripheral(FL_RCC_RSTAPB_UART1); + /* 外设总线时钟关闭 */ + FL_RCC_DisableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_UART1); + /* 外设操作时钟关闭 */ + FL_RCC_DisableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_UART1); + } + else + if(UARTx == UART4) + { + /*复位UART*/ + FL_RCC_EnableResetAPB1Peripheral(FL_RCC_RSTAPB_UART4); + FL_RCC_DisableResetAPB1Peripheral(FL_RCC_RSTAPB_UART4); + /* 外设总线时钟关闭 */ + FL_RCC_DisableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_UART4); + } + else + if(UARTx == UART5) + { + /*复位UART*/ + FL_RCC_EnableResetAPB1Peripheral(FL_RCC_RSTAPB_UART5); + FL_RCC_DisableResetAPB1Peripheral(FL_RCC_RSTAPB_UART5); + /* 外设总线时钟关闭 */ + FL_RCC_DisableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_UART5); + } + else + { + status = FL_FAIL; + } + /* 锁定外设复位功能 */ + FL_RCC_DisablePeripheralReset(); + return (status); +} + +/** + * @brief 配置UART + * + * @param UARTx 外设入口地址 + * @param initStruct 指向 @ref FL_UART_InitTypeDef 结构体的指针 + * + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_UART_Init(UART_Type *UARTx, FL_UART_InitTypeDef *initStruct) +{ + FL_ErrorStatus status = FL_FAIL; + uint32_t Fclk = 0, baudRate = 0; + /* 参数合法性检查 */ + assert_param(IS_UART_INSTANCE(UARTx)); + assert_param(IS_FL_UART_CLKSRC(initStruct->clockSrc)); + assert_param(IS_FL_UART_DATAWIDTH(initStruct->dataWidth)); + assert_param(IS_FL_UART_PARITY(initStruct->parity)); + assert_param(IS_FL_UART_STOPBITS(initStruct->stopBits)); + assert_param(IS_FL_UART_DIRECTION(initStruct->transferDirection)); + if(UARTx == UART0) + { + /*时钟源选择*/ + FL_RCC_SetUART0ClockSource(initStruct->clockSrc); + /* 根据不同的时钟源计算baudrate 寄存器值,并配置 */ + switch(initStruct->clockSrc) + { + case FL_RCC_UART0_CLK_SOURCE_APB1CLK: + Fclk = FL_RCC_GetAPB1ClockFreq(); + break; + case FL_RCC_UART0_CLK_SOURCE_RCHF: + Fclk = FL_RCC_GetRCHFClockFreq(); + break; + case FL_RCC_UART0_CLK_SOURCE_SYSCLK: + Fclk = FL_RCC_GetSystemClockFreq(); + break; + case FL_RCC_UART0_CLK_SOURCE_RCMF_PSC: + Fclk = FL_RCC_GetRC4MClockFreq(); + break; + } + baudRate = Fclk / initStruct->baudRate - 1; + } + if(UARTx == UART1) + { + /*时钟源选择*/ + FL_RCC_SetUART1ClockSource(initStruct->clockSrc); + /* 根据不同的时钟源计算baudrate 寄存器值,并配置 */ + switch(initStruct->clockSrc) + { + case FL_RCC_UART1_CLK_SOURCE_APB1CLK: + Fclk = FL_RCC_GetAPB1ClockFreq(); + break; + case FL_RCC_UART1_CLK_SOURCE_RCHF: + Fclk = FL_RCC_GetRCHFClockFreq(); + break; + case FL_RCC_UART1_CLK_SOURCE_SYSCLK: + Fclk = FL_RCC_GetSystemClockFreq(); + break; + case FL_RCC_UART1_CLK_SOURCE_RCMF_PSC: + Fclk = FL_RCC_GetRC4MClockFreq(); + break; + } + baudRate = Fclk / initStruct->baudRate - 1; + } + if(UARTx == UART0) + { + /*总线时钟使能*/ + FL_RCC_EnableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_UART0); + /*操作时钟使能*/ + FL_RCC_EnableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_UART0); + } + else + if(UARTx == UART1) + { + /*总线时钟使能*/ + FL_RCC_EnableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_UART1); + /*操作时钟使能*/ + FL_RCC_EnableGroup1OperationClock(FL_RCC_GROUP1_OPCLK_UART1); + } + else + if(UARTx == UART4) + { + /*总线时钟使能*/ + FL_RCC_EnableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_UART4); + Fclk = FL_RCC_GetAPB2ClockFreq(); + baudRate = Fclk / initStruct->baudRate - 1; + } + else + if(UARTx == UART5) + { + FL_RCC_EnableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_UART5); + Fclk = FL_RCC_GetAPB2ClockFreq(); + baudRate = Fclk / initStruct->baudRate - 1; + } + /*发送接收控制*/ + if(initStruct->transferDirection & FL_UART_DIRECTION_TX) + { + FL_UART_EnableTX(UARTx); + } + if(initStruct->transferDirection & FL_UART_DIRECTION_RX) + { + FL_UART_EnableRX(UARTx); + } + /*配置波特率*/ + FL_UART_WriteBaudRate(UARTx, baudRate); + /*配置停止位长度*/ + FL_UART_SetStopBitsWidth(UARTx, initStruct->stopBits); + /*数据长度*/ + FL_UART_SetDataWidth(UARTx, initStruct->dataWidth); + /*配置奇偶校验*/ + FL_UART_SetParity(UARTx, initStruct->parity); + status = FL_PASS; + return status; +} + +/** + * @brief 配置UART红外调制 + * + * @param UARTx 外设入口地址 + * + * @param initStruct 指向 @ref FL_UART_InfraRed_InitTypeDef 结构体的指针 + * + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_UART_InfraRed_Init(UART_Type *UARTx, FL_UART_InfraRed_InitTypeDef *initStruct) +{ + FL_ErrorStatus status = FL_FAIL; + uint32_t tempTZBRG = 0, tempTH = 0; + /* 参数合法性检查 */ + assert_param(IS_UART_INSTANCE(UARTx)); + assert_param(IS_FL_UART_INFRARED_POLARITY(initStruct->polarity)); + assert_param(IS_FL_UART_INFRARED_MODULATION_DUTY(initStruct->modulationDuty)); + FL_RCC_EnableGroup3BusClock(FL_RCC_GROUP3_BUSCLK_UARTIR); + /*红外发送使能*/ + FL_UART_EnableIRModulation(UARTx); + /*红外调制极性*/ + FL_UART_SetIRPolarity(UART, initStruct->polarity); + /*红外调制频率*/ + tempTZBRG = (uint32_t)((FL_RCC_GetAPB1ClockFreq() * 1.0) / initStruct->modulationFrequency - 1); + /* 调制占空比 */ + if((tempTZBRG >> 4) != 0) + { + tempTH = (uint32_t)(((float)initStruct->modulationDuty / 100.0) * ((float)(tempTZBRG + 1) / (float)(tempTZBRG >> 4)) + 0.5); + } + else + { + tempTH = (uint32_t)(((float)initStruct->modulationDuty / 100.0) * (float)(tempTZBRG + 1) + 0.5); + } + /* 占空比限位到小于95%，否则结果会有问题 */ + tempTH = ((float)((tempTZBRG >> 4) * tempTH) / (float)(tempTZBRG + 1)) < 0.95f ? tempTH : tempTH - 1; + /* 占空比和调制频率配置 */ + FL_UART_WriteIRModulationDuty(UART, tempTH); + FL_UART_WriteIRModulationFrequency(UART, tempTZBRG); + status = FL_PASS; + return status; +} + +/** + * @brief 将 @ref FL_UART_InfraRed_InitTypeDef 结构体初始化为默认配置 + * @param initStruct 指向 @ref FL_UART_InfraRed_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_UART_InfraRed_StructInit(FL_UART_InfraRed_InitTypeDef *initStruct) +{ + initStruct->polarity = FL_UART_INFRARED_POLARITY_NORMAL; + initStruct->modulationDuty = 50; + initStruct->modulationFrequency = 38000; +} + +/** + * @brief 将 @ref FL_UART_InitTypeDef 结构体初始化为默认配置 + * @param initStruct 指向 @ref FL_UART_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_UART_StructInit(FL_UART_InitTypeDef *initStruct) +{ + initStruct->baudRate = 115200; + initStruct->dataWidth = FL_UART_DATA_WIDTH_8B; + initStruct->stopBits = FL_UART_STOP_BIT_WIDTH_1B; + initStruct->parity = FL_UART_PARITY_EVEN ; + initStruct->transferDirection = FL_UART_DIRECTION_TX_RX; + initStruct->clockSrc = 0; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_wwdt.c b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_wwdt.c new file mode 100644 index 0000000000..2d967cf195 --- /dev/null +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Src/fm33lc0xx_fl_wwdt.c @@ -0,0 +1,125 @@ +/** + **************************************************************************************************** + * @file fm33lc0xx_fl_wwdt.c + * @author FMSH Application Team + * @brief Src file of WWDT FL Module + **************************************************************************************************** + * @attention + * + * Copyright (c) [2019] [Fudan Microelectronics] + * THIS SOFTWARE is licensed under the Mulan PSL v1. + * can use this software according to the terms and conditions of the Mulan PSL v1. + * You may obtain a copy of Mulan PSL v1 at: + * http://license.coscl.org.cn/MulanPSL + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR + * PURPOSE. + * See the Mulan PSL v1 for more details. + * + **************************************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "fm33lc0xx_fl_rcc.h" +#include "fm33lc0xx_fl_wwdt.h" +#include "fm33_assert.h" + +/** @addtogroup FM33LC0XX_FL_Driver + * @{ + */ + +/** @addtogroup WWDT + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup WWDT_FL_Private_Macros + * @{ + */ + +#define IS_WWDT_INSTANCE(INTANCE) ((INTANCE) == WWDT) + +#define IS_FL_WWDT_OVERFLOWPERIOD(__VALUE__) (((__VALUE__) == FL_WWDT_PERIOD_1CNT)||\ + ((__VALUE__) == FL_WWDT_PERIOD_4CNT)||\ + ((__VALUE__) == FL_WWDT_PERIOD_16CNT)||\ + ((__VALUE__) == FL_WWDT_PERIOD_64CNT)||\ + ((__VALUE__) == FL_WWDT_PERIOD_128CNT)||\ + ((__VALUE__) == FL_WWDT_PERIOD_256CNT)||\ + ((__VALUE__) == FL_WWDT_PERIOD_512CNT)||\ + ((__VALUE__) == FL_WWDT_PERIOD_1024CNT)) +/** + * @} + */ + +/** @addtogroup WWDT_FL_EF_Init + * @{ + */ + +/** + * @brief 关闭WWDT外设总线时钟 + * + * @param WWDTx 外设入口地址 + * + * @retval 错误状态，可能值： + * -FL_PASS 外设寄存器值恢复复位值 + * -FL_FAIL 未成功执行 + */ +FL_ErrorStatus FL_WWDT_DeInit(WWDT_Type *WWDTx) +{ + assert_param(IS_WWDT_INSTANCE(WWDTx)); + return FL_PASS; +} + +/** + * @brief 根据 WWDT_InitStruct初始化对应外设入口地址的寄存器值. + * + * @note WWTD使能后将无法关闭，直到下一次芯片复位 + * + * @param WWDTx 外设入口地址 + * + * @param WWDT_InitStruct 指向 @ref FL_WWDT_InitTypeDef 结构体的指针 + * + * @retval 错误状态，可能值： + * -FL_PASS 配置成功 + * -FL_FAIL 配置过程发生错误 + */ +FL_ErrorStatus FL_WWDT_Init(WWDT_Type *WWDTx, FL_WWDT_InitTypeDef *WWDT_InitStruct) +{ + FL_ErrorStatus status = FL_PASS; + /* 入口参数检查 */ + assert_param(IS_WWDT_INSTANCE(WWDTx)); + assert_param(IS_FL_WWDT_OVERFLOWPERIOD(WWDT_InitStruct->overflowPeriod)); + /* 开启总线时钟 */ + FL_RCC_EnableGroup2BusClock(FL_RCC_GROUP2_BUSCLK_WWDT); + /* 配置独立看门狗溢出周期 */ + FL_WWDT_SetPeriod(WWDTx, WWDT_InitStruct->overflowPeriod); + /* 启动看门狗 */ + FL_WWDT_Enable(WWDTx); + return status; +} + +/** + * @brief 设置 WWDT_InitStruct 为默认配置 + * + * @param WWDT_InitStruct 指向 @ref FL_WWDT_InitTypeDef 结构体的指针 + * + * @retval None + */ +void FL_WWDT_StructInit(FL_WWDT_InitTypeDef *WWDT_InitStruct) +{ + /* 默认最长溢出周期 */ + WWDT_InitStruct->overflowPeriod = FL_WWDT_PERIOD_1024CNT; +} + +/** + *@} + */ + +/** + *@} + */ + +/** + *@} + */ + +/******************************************* END OF FILE *******************************************/ diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/Kconfig b/bsp/fm33lc026/libraries/HAL_Drivers/Kconfig new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/bsp/fm33lc026/libraries/HAL_Drivers/Kconfig @@ -0,0 +1,2 @@ + + diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/SConscript b/bsp/fm33lc026/libraries/HAL_Drivers/SConscript new file mode 100644 index 0000000000..bc470b0fa0 --- /dev/null +++ b/bsp/fm33lc026/libraries/HAL_Drivers/SConscript @@ -0,0 +1,59 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +""") + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_usart.c'] + +if GetDepend(['RT_USING_HWTIMER']): + src += ['drv_hwtimer.c'] + +if GetDepend(['RT_USING_PWM']): + src += ['drv_pwm.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['drv_spi.c'] + +if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): + if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'): + src += ['drv_soft_i2c.c'] + +if GetDepend(['RT_USING_ADC']): + src += Glob('drv_adc.c') + +if GetDepend(['RT_USING_DAC']): + src += Glob('drv_dac.c') + +if GetDepend(['RT_USING_CAN']): + src += ['drv_can.c'] + +if GetDepend(['RT_USING_PM']): + src += ['drv_pm.c'] + src += ['drv_lptim.c'] + +if GetDepend('BSP_USING_ONCHIP_RTC'): + src += ['drv_rtc.c'] + +if GetDepend('BSP_USING_ON_CHIP_FLASH'): + src += ['drv_flash.c'] + +if GetDepend(['BSP_USING_WDT']): + src += ['drv_wdt.c'] + +src += ['drv_common.c'] + +path = [cwd] +path += [cwd + '/config'] + +if GetDepend('BSP_USING_ON_CHIP_FLASH'): + path += [cwd + '/drv_flash'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/config/uart_config.h b/bsp/fm33lc026/libraries/HAL_Drivers/config/uart_config.h new file mode 100644 index 0000000000..7c6fd2bd59 --- /dev/null +++ b/bsp/fm33lc026/libraries/HAL_Drivers/config/uart_config.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-27 Jiao first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_UART0) +#ifndef UART0_CONFIG +#define UART0_CONFIG \ + { \ + .name = "uart0", \ + .InitTypeDef = UART0, \ + .irq_type = UART0_IRQn, \ + .clockSrc = FL_RCC_UART0_CLK_SOURCE_APB1CLK, \ + } +#endif /* UART0_CONFIG */ +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .InitTypeDef = UART1, \ + .irq_type = UART1_IRQn, \ + .clockSrc = FL_RCC_UART1_CLK_SOURCE_APB1CLK, \ + } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .InitTypeDef = UART4, \ + .irq_type = UART4_IRQn, \ + } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = UART5, \ + .irq_type = UART5_IRQn, \ + } +#endif /* UART5_CONFIG */ +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_LPUART0) +#ifndef LPUART0_CONFIG +#define LPUART0_CONFIG \ + { \ + .name = "lpuart0", \ + .Instance = LPUART0, \ + .irq_type = LPUART0_IRQn, \ + } +#endif /* LPUART0_CONFIG */ +#endif /* BSP_USING_LPUART0 */ + +#if defined(BSP_USING_LPUART1) +#ifndef LPUART1_CONFIG +#define LPUART1_CONFIG \ + { \ + .name = "lpuart1", \ + .Instance = LPUART1, \ + .irq_type = LPUART1_IRQn, \ + } +#endif /* LPUART0_CONFIG */ +#endif /* BSP_USING_LPUART0 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __UART_CONFIG_H__ */ diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/drv_common.c b/bsp/fm33lc026/libraries/HAL_Drivers/drv_common.c new file mode 100644 index 0000000000..9decb78d6d --- /dev/null +++ b/bsp/fm33lc026/libraries/HAL_Drivers/drv_common.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-7 SummerGift first version + * 2021-08-27 Jiao change to fm33 +*/ + +#include "drv_common.h" +#include "system_fm33lc0xx.h" + +#ifdef RT_USING_SERIAL + #include "drv_usart.h" +#endif + +#ifdef RT_USING_FINSH +#include +static void reboot(uint8_t argc, char **argv) +{ + rt_hw_cpu_reset(); +} +FINSH_FUNCTION_EXPORT_ALIAS(reboot, __cmd_reboot, Reboot System); +#endif /* RT_USING_FINSH */ + +/* SysTick configuration */ +void rt_hw_systick_init(void) +{ + SystemCoreClockUpdate(); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + NVIC_SetPriority(SysTick_IRQn, 0xFF); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +uint32_t HAL_GetTick(void) +{ + return rt_tick_get() * 1000 / RT_TICK_PER_SECOND; +} + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void _Error_Handler(char *s, int num) +{ + /* USER CODE BEGIN Error_Handler */ + /* User can add his own implementation to report the HAL error return state */ + while (1) + { + } + /* USER CODE END Error_Handler */ +} + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = SystemCoreClock / 1000000UL; + do + { + now = SysTick->VAL; + delta = start > now ? start - now : reload + start - now; + } + while (delta < us_tick * us); +} + +/** + * This function will initial STM32 board. + */ +RT_WEAK void rt_hw_board_init() +{ + void SelRCHFToPLL(uint32_t rchf, uint32_t clock); + + SelRCHFToPLL(RCHF8M_TRIM, 63); + rt_hw_systick_init(); + + extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) + + /* Heap initialization */ +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)(0x20000000 + 0x6000)); +#endif + + /* USART driver initialization is open by default */ +#ifdef RT_USING_SERIAL + rt_hw_usart_init(); +#endif + + /* Set the shell console output device */ +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + /* Board underlying hardware initialization */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/drv_common.h b/bsp/fm33lc026/libraries/HAL_Drivers/drv_common.h new file mode 100644 index 0000000000..bffedddcd0 --- /dev/null +++ b/bsp/fm33lc026/libraries/HAL_Drivers/drv_common.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-7 SummerGift first version + */ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void _Error_Handler(char *s, int num); + +#ifndef Error_Handler +#define Error_Handler() _Error_Handler(__FILE__, __LINE__) +#endif + +#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/drv_config.h b/bsp/fm33lc026/libraries/HAL_Drivers/drv_config.h new file mode 100644 index 0000000000..87ceca10d0 --- /dev/null +++ b/bsp/fm33lc026/libraries/HAL_Drivers/drv_config.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-30 SummerGift first version + * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + * 2021-08-27 Jiao first version +*/ + +#ifndef __DRV_CONFIG_H__ +#define __DRV_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#include "uart_config.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/drv_log.h b/bsp/fm33lc026/libraries/HAL_Drivers/drv_log.h new file mode 100644 index 0000000000..7e0bfee5b4 --- /dev/null +++ b/bsp/fm33lc026/libraries/HAL_Drivers/drv_log.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-15 SummerGift first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/drv_usart.c b/bsp/fm33lc026/libraries/HAL_Drivers/drv_usart.c new file mode 100644 index 0000000000..0e42e60f9a --- /dev/null +++ b/bsp/fm33lc026/libraries/HAL_Drivers/drv_usart.c @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-27 Jiao first version +*/ + +#include "drv_usart.h" +#include "drv_config.h" + +#ifdef RT_USING_SERIAL + +//#define DRV_DEBUG +#define LOG_TAG "drv.usart" +#include + +enum +{ +#ifdef BSP_USING_UART0 + UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif +#ifdef BSP_USING_UART5 + UART5_INDEX, +#endif +#ifdef BSP_USING_LPUART0 + LPUART0_INDEX, +#endif +#ifdef BSP_USING_LPUART1 + LPUART1_INDEX, +#endif +}; + +static struct _uart_config uart_config[] = +{ +#ifdef BSP_USING_UART0 + UART0_CONFIG, +#endif +#ifdef BSP_USING_UART1 + UART1_CONFIG, +#endif +#ifdef BSP_USING_UART4 + UART4_CONFIG, +#endif +#ifdef BSP_USING_UART5 + UART5_CONFIG, +#endif +#ifdef BSP_USING_LPUART0 + LPUART0_CONFIG, +#endif +#ifdef BSP_USING_LPUART1 + LPUART1_CONFIG, +#endif +}; + +static struct _uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + extern FL_ErrorStatus FL_UART_GPIO_Init(UART_Type * UARTx); + + struct _uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = rt_container_of(serial, struct _uart, serial); + + if (FL_UART_GPIO_Init(uart->config->InitTypeDef) != FL_PASS) + { + return -RT_ERROR; + } + + uart->handle.clockSrc = uart->config->clockSrc; + uart->handle.baudRate = cfg->baud_rate; + + switch (cfg->data_bits) + { + case DATA_BITS_8: + uart->handle.dataWidth = FL_UART_DATA_WIDTH_8B; + break; + case DATA_BITS_9: + uart->handle.dataWidth = FL_UART_DATA_WIDTH_9B; + break; + default: + uart->handle.dataWidth = FL_UART_DATA_WIDTH_8B; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->handle.stopBits = FL_UART_STOP_BIT_WIDTH_1B; + break; + case STOP_BITS_2: + uart->handle.stopBits = FL_UART_STOP_BIT_WIDTH_2B; + break; + default: + uart->handle.stopBits = FL_UART_STOP_BIT_WIDTH_1B; + break; + } + switch (cfg->parity) + { + case PARITY_NONE: + uart->handle.parity = FL_UART_PARITY_NONE; + break; + case PARITY_ODD: + uart->handle.parity = FL_UART_PARITY_ODD; + break; + case PARITY_EVEN: + uart->handle.parity = FL_UART_PARITY_EVEN; + break; + default: + uart->handle.parity = FL_UART_PARITY_NONE; + break; + } + + uart->handle.transferDirection = FL_UART_DIRECTION_TX_RX; + + if (FL_UART_Init(uart->config->InitTypeDef, &uart->handle) != FL_PASS) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct _uart *uart; +#ifdef RT_SERIAL_USING_DMA + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; +#endif + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct _uart, serial); + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->config->irq_type); + /* disable interrupt */ + FL_UART_DisableIT_RXBuffFull(uart->config->InitTypeDef); + + break; + + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_SetPriority(uart->config->irq_type, 1); + NVIC_EnableIRQ(uart->config->irq_type); + /* enable interrupt */ + FL_UART_EnableIT_RXBuffFull(uart->config->InitTypeDef); + break; + +#ifdef RT_SERIAL_USING_DMA + case RT_DEVICE_CTRL_CONFIG: + stm32_dma_config(serial, ctrl_arg); + break; +#endif + + case RT_DEVICE_CTRL_CLOSE: + if (FL_UART_DeInit(uart->config->InitTypeDef) != FL_PASS) + { + RT_ASSERT(0) + } + break; + + } + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct _uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct _uart, serial); + FL_UART_WriteTXBuff(uart->config->InitTypeDef, c); //һ + while (FL_SET != FL_UART_IsActiveFlag_TXShiftBuffEmpty(uart->config->InitTypeDef)); + return 1; +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct _uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct _uart, serial); + + ch = -1; + if (FL_SET == FL_UART_IsActiveFlag_RXBuffFull(uart->config->InitTypeDef)) + { + ch = FL_UART_ReadRXBuff(uart->config->InitTypeDef);//жϱ־ͨȡrxregĴ + } + return ch; +} + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) +{ + struct _uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct _uart, serial); + + /* UART in mode Receiver -------------------------------------------------*/ + if ((FL_ENABLE == FL_UART_IsEnabledIT_RXBuffFull(uart->config->InitTypeDef)) + && (FL_SET == FL_UART_IsActiveFlag_RXBuffFull(uart->config->InitTypeDef))) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } +} + +#if defined(BSP_USING_UART0) +void UART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART0_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART1) +void UART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART1_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART4) +void UART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART4_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +void UART5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART5_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_LPUART0) +void LPUART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[LPUART0_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_LPUART0*/ + +#if defined(BSP_USING_LPUART1) +void LPUART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[LPUART1_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_LPUART1*/ + +static const struct rt_uart_ops _uart_ops = +{ + .configure = uart_configure, + .control = uart_control, + .putc = uart_putc, + .getc = uart_getc, + .dma_transmit = 0 +}; + +int rt_hw_usart_init(void) +{ + rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct _uart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t result = 0; + + for (int i = 0; i < obj_num; i++) + { + /* init UART object */ + uart_obj[i].config = &uart_config[i]; + uart_obj[i].serial.ops = &_uart_ops; + uart_obj[i].serial.config = config; + + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, + RT_DEVICE_FLAG_RDWR + | RT_DEVICE_FLAG_INT_RX + | RT_DEVICE_FLAG_INT_TX + | uart_obj[i].uart_dma_flag + , NULL); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +#endif /* RT_USING_SERIAL */ diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/drv_usart.h b/bsp/fm33lc026/libraries/HAL_Drivers/drv_usart.h new file mode 100644 index 0000000000..ba05d74dea --- /dev/null +++ b/bsp/fm33lc026/libraries/HAL_Drivers/drv_usart.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018.10.30 SummerGift first version + * 2019.03.05 whj4674672 add stm32h7 + * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + */ + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +#include +#include "rtdevice.h" +#include +#include +#include "board.h" + +int rt_hw_usart_init(void); + + +/* stm32 config class */ +struct _uart_config +{ + const char *name; + void *InitTypeDef; + IRQn_Type irq_type; + uint32_t clockSrc; +}; + +/* stm32 uart dirver class */ +struct _uart +{ + FL_UART_InitTypeDef handle; + struct _uart_config *config; + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; + +#endif /* __DRV_USART_H__ */ diff --git a/bsp/fm33lc026/libraries/Kconfig b/bsp/fm33lc026/libraries/Kconfig new file mode 100644 index 0000000000..58bc341b4a --- /dev/null +++ b/bsp/fm33lc026/libraries/Kconfig @@ -0,0 +1,7 @@ +config SOC_FAMILY_FM33 + bool + +config SOC_SERIES_FM33LC0XX + bool + select ARCH_ARM_CORTEX_M0 + select SOC_FAMILY_FM33 diff --git a/bsp/gd32e230k-start/project.uvoptx b/bsp/fm33lc026/project.uvoptx similarity index 67% rename from bsp/gd32e230k-start/project.uvoptx rename to bsp/fm33lc026/project.uvoptx index ef882479f1..e7a2060752 100644 --- a/bsp/gd32e230k-start/project.uvoptx +++ b/bsp/fm33lc026/project.uvoptx @@ -22,13 +22,13 @@ - rt-thread_gd32e230 + RT_Thread 0x4 ARM-ADS 12000000 - 1 + 0 1 0 1 @@ -45,7 +45,7 @@ 79 66 8 - .\build\ + .\build\keil\List\ 1 @@ -77,7 +77,7 @@ 0 1 - 255 + 0 0 1 @@ -103,7 +103,7 @@ 1 0 0 - 20 + 0 @@ -114,18 +114,13 @@ - BIN\CMSIS_AGDI_V8M.DLL + BIN\UL2CM3.DLL 0 - UL2V8M - UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E230 -FS08000000 -FL010000 -FP0($$Device:GD32E230K8$Flash\GD32E230.FLM)) - - - 0 - JL2CM3 - -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_HD -FS08000000 -FL080000 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FM33LC04X_FLASH256 -FS00 -FL040000 -FP0($$Device:FM33LC04X$Flash\FM33LC04X_FLASH256.FLM)) @@ -171,197 +166,16 @@ + + 1 + 1 + 0 + 2 + 5000000 + - - Kernel - 1 - 0 - 0 - 0 - - 1 - 1 - 1 - 0 - 0 - 0 - ..\..\src\clock.c - clock.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - ..\..\src\components.c - components.c - 0 - 0 - - - 1 - 3 - 1 - 0 - 0 - 0 - ..\..\src\cpu.c - cpu.c - 0 - 0 - - - 1 - 4 - 1 - 0 - 0 - 0 - ..\..\src\device.c - device.c - 0 - 0 - - - 1 - 5 - 1 - 0 - 0 - 0 - ..\..\src\idle.c - idle.c - 0 - 0 - - - 1 - 6 - 1 - 0 - 0 - 0 - ..\..\src\ipc.c - ipc.c - 0 - 0 - - - 1 - 7 - 1 - 0 - 0 - 0 - ..\..\src\irq.c - irq.c - 0 - 0 - - - 1 - 8 - 1 - 0 - 0 - 0 - ..\..\src\kservice.c - kservice.c - 0 - 0 - - - 1 - 9 - 1 - 0 - 0 - 0 - ..\..\src\mem.c - mem.c - 0 - 0 - - - 1 - 10 - 1 - 0 - 0 - 0 - ..\..\src\mempool.c - mempool.c - 0 - 0 - - - 1 - 11 - 1 - 0 - 0 - 0 - ..\..\src\object.c - object.c - 0 - 0 - - - 1 - 12 - 1 - 0 - 0 - 0 - ..\..\src\scheduler.c - scheduler.c - 0 - 0 - - - 1 - 13 - 1 - 0 - 0 - 0 - ..\..\src\signal.c - signal.c - 0 - 0 - - - 1 - 14 - 1 - 0 - 0 - 0 - ..\..\src\thread.c - thread.c - 0 - 0 - - - 1 - 15 - 1 - 0 - 0 - 0 - ..\..\src\timer.c - timer.c - 0 - 0 - - - Applications 1 @@ -369,8 +183,8 @@ 0 0 - 2 - 16 + 1 + 1 1 0 0 @@ -383,366 +197,14 @@ - Drivers - 1 - 0 - 0 - 0 - - 3 - 17 - 1 - 0 - 0 - 0 - drivers\board.c - board.c - 0 - 0 - - - 3 - 18 - 1 - 0 - 0 - 0 - drivers\drv_usart.c - drv_usart.c - 0 - 0 - - - 3 - 19 - 1 - 0 - 0 - 0 - drivers\drv_spi.c - drv_spi.c - 0 - 0 - - - 3 - 20 - 1 - 0 - 0 - 0 - drivers\drv_i2c.c - drv_i2c.c - 0 - 0 - - - 3 - 21 - 1 - 0 - 0 - 0 - drivers\drv_gpio.c - drv_gpio.c - 0 - 0 - - - - - GD32_Lib + CPU 0 0 0 0 - 4 - 22 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_adc.c - gd32e230_adc.c - 0 - 0 - - - 4 - 23 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_cmp.c - gd32e230_cmp.c - 0 - 0 - - - 4 - 24 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_crc.c - gd32e230_crc.c - 0 - 0 - - - 4 - 25 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_dbg.c - gd32e230_dbg.c - 0 - 0 - - - 4 - 26 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_dma.c - gd32e230_dma.c - 0 - 0 - - - 4 - 27 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_exti.c - gd32e230_exti.c - 0 - 0 - - - 4 - 28 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_fmc.c - gd32e230_fmc.c - 0 - 0 - - - 4 - 29 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_fwdgt.c - gd32e230_fwdgt.c - 0 - 0 - - - 4 - 30 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_gpio.c - gd32e230_gpio.c - 0 - 0 - - - 4 - 31 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_i2c.c - gd32e230_i2c.c - 0 - 0 - - - 4 - 32 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_misc.c - gd32e230_misc.c - 0 - 0 - - - 4 - 33 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_pmu.c - gd32e230_pmu.c - 0 - 0 - - - 4 - 34 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_rcu.c - gd32e230_rcu.c - 0 - 0 - - - 4 - 35 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_rtc.c - gd32e230_rtc.c - 0 - 0 - - - 4 - 36 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_spi.c - gd32e230_spi.c - 0 - 0 - - - 4 - 37 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_syscfg.c - gd32e230_syscfg.c - 0 - 0 - - - 4 - 38 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_timer.c - gd32e230_timer.c - 0 - 0 - - - 4 - 39 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_usart.c - gd32e230_usart.c - 0 - 0 - - - 4 - 40 - 1 - 0 - 0 - 0 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_wwdgt.c - gd32e230_wwdgt.c - 0 - 0 - - - 4 - 41 - 1 - 0 - 0 - 0 - Libraries\CMSIS\GD\GD32E230\Source\system_gd32e230.c - system_gd32e230.c - 0 - 0 - - - 4 - 42 - 2 - 0 - 0 - 0 - Libraries\CMSIS\GD\GD32E230\Source\ARM\startup_gd32e230.s - startup_gd32e230.s - 0 - 0 - - - - - cpu - 0 - 0 - 0 - 0 - - 5 - 43 - 1 - 0 - 0 - 0 - ..\..\libcpu\arm\common\backtrace.c - backtrace.c - 0 - 0 - - - 5 - 44 - 1 - 0 - 0 - 0 - ..\..\libcpu\arm\common\div0.c - div0.c - 0 - 0 - - - 5 - 45 + 2 + 2 1 0 0 @@ -753,29 +215,53 @@ 0 - 5 - 46 + 2 + 3 1 0 0 0 - ..\..\libcpu\arm\cortex-m23\cpuport.c - cpuport.c + ..\..\libcpu\arm\common\div0.c + div0.c 0 0 - 5 - 47 + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 2 + 5 2 0 0 0 - ..\..\libcpu\arm\cortex-m23\context_rvds.S + ..\..\libcpu\arm\cortex-m0\context_rvds.S context_rvds.S 0 0 + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m0\cpuport.c + cpuport.c + 0 + 0 + @@ -785,44 +271,8 @@ 0 0 - 6 - 48 - 1 - 0 - 0 - 0 - ..\..\components\drivers\i2c\i2c_core.c - i2c_core.c - 0 - 0 - - - 6 - 49 - 1 - 0 - 0 - 0 - ..\..\components\drivers\i2c\i2c_dev.c - i2c_dev.c - 0 - 0 - - - 6 - 50 - 1 - 0 - 0 - 0 - ..\..\components\drivers\misc\pin.c - pin.c - 0 - 0 - - - 6 - 51 + 3 + 7 1 0 0 @@ -833,92 +283,8 @@ 0 - 6 - 52 - 1 - 0 - 0 - 0 - ..\..\components\drivers\spi\spi_core.c - spi_core.c - 0 - 0 - - - 6 - 53 - 1 - 0 - 0 - 0 - ..\..\components\drivers\spi\spi_dev.c - spi_dev.c - 0 - 0 - - - 6 - 54 - 1 - 0 - 0 - 0 - ..\..\components\drivers\spi\spi_flash_sfud.c - spi_flash_sfud.c - 0 - 0 - - - 6 - 55 - 1 - 0 - 0 - 0 - ..\..\components\drivers\spi\sfud\src\sfud.c - sfud.c - 0 - 0 - - - 6 - 56 - 1 - 0 - 0 - 0 - ..\..\components\drivers\src\completion.c - completion.c - 0 - 0 - - - 6 - 57 - 1 - 0 - 0 - 0 - ..\..\components\drivers\src\dataqueue.c - dataqueue.c - 0 - 0 - - - 6 - 58 - 1 - 0 - 0 - 0 - ..\..\components\drivers\src\pipe.c - pipe.c - 0 - 0 - - - 6 - 59 + 3 + 8 1 0 0 @@ -929,8 +295,8 @@ 0 - 6 - 60 + 3 + 9 1 0 0 @@ -941,8 +307,8 @@ 0 - 6 - 61 + 3 + 10 1 0 0 @@ -953,8 +319,8 @@ 0 - 6 - 62 + 3 + 11 1 0 0 @@ -964,14 +330,518 @@ 0 0 + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + - ::CMSIS + Drivers + 1 + 0 + 0 + 0 + + 4 + 15 + 2 + 0 + 0 + 0 + libraries\FM\FM33xx\Source\Templates\ARM\startup_fm33lc0xx.s + startup_fm33lc0xx.s + 0 + 0 + + + 4 + 16 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + libraries\HAL_Drivers\drv_usart.c + drv_usart.c + 0 + 0 + + + 4 + 18 + 1 + 0 + 0 + 0 + libraries\HAL_Drivers\drv_common.c + drv_common.c + 0 + 0 + + + + + finsh 0 0 0 - 1 + 0 + + 5 + 19 + 1 + 0 + 0 + 0 + ..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 5 + 20 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_node.c + finsh_node.c + 0 + 0 + + + 5 + 21 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_parser.c + finsh_parser.c + 0 + 0 + + + 5 + 22 + 1 + 0 + 0 + 0 + ..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 5 + 23 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_vm.c + finsh_vm.c + 0 + 0 + + + 5 + 24 + 1 + 0 + 0 + 0 + ..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 5 + 25 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_var.c + finsh_var.c + 0 + 0 + + + 5 + 26 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_compiler.c + finsh_compiler.c + 0 + 0 + + + 5 + 27 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_heap.c + finsh_heap.c + 0 + 0 + + + 5 + 28 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_ops.c + finsh_ops.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_error.c + finsh_error.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_token.c + finsh_token.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_init.c + finsh_init.c + 0 + 0 + + + + + FM33LC0xx_FL_Driver + 0 + 0 + 0 + 0 + + 6 + 32 + 1 + 0 + 0 + 0 + libraries\FM33LC0xx_FL_Driver\Src\fm33lc0xx_fl_rcc.c + fm33lc0xx_fl_rcc.c + 0 + 0 + + + 6 + 33 + 1 + 0 + 0 + 0 + libraries\FM33LC0xx_FL_Driver\Src\fm33lc0xx_fl_crc.c + fm33lc0xx_fl_crc.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + libraries\FM33LC0xx_FL_Driver\Src\fm33lc0xx_fl_uart.c + fm33lc0xx_fl_uart.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + libraries\FM33LC0xx_FL_Driver\Src\fm33lc0xx_fl_lpuart.c + fm33lc0xx_fl_lpuart.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + libraries\FM33LC0xx_FL_Driver\Src\fm33lc0xx_fl_gpio.c + fm33lc0xx_fl_gpio.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + libraries\FM33LC0xx_FL_Driver\Src\fm33lc0xx_fl_dma.c + fm33lc0xx_fl_dma.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + libraries\FM33LC0xx_FL_Driver\CMSIS\system_fm33lc0xx.c + system_fm33lc0xx.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 7 + 39 + 1 + 0 + 0 + 0 + ..\..\src\thread.c + thread.c + 0 + 0 + + + 7 + 40 + 1 + 0 + 0 + 0 + ..\..\src\mem.c + mem.c + 0 + 0 + + + 7 + 41 + 1 + 0 + 0 + 0 + ..\..\src\irq.c + irq.c + 0 + 0 + + + 7 + 42 + 1 + 0 + 0 + 0 + ..\..\src\timer.c + timer.c + 0 + 0 + + + 7 + 43 + 1 + 0 + 0 + 0 + ..\..\src\kservice.c + kservice.c + 0 + 0 + + + 7 + 44 + 1 + 0 + 0 + 0 + ..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 7 + 45 + 1 + 0 + 0 + 0 + ..\..\src\device.c + device.c + 0 + 0 + + + 7 + 46 + 1 + 0 + 0 + 0 + ..\..\src\ipc.c + ipc.c + 0 + 0 + + + 7 + 47 + 1 + 0 + 0 + 0 + ..\..\src\mempool.c + mempool.c + 0 + 0 + + + 7 + 48 + 1 + 0 + 0 + 0 + ..\..\src\clock.c + clock.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + ..\..\src\idle.c + idle.c + 0 + 0 + + + 7 + 50 + 1 + 0 + 0 + 0 + ..\..\src\object.c + object.c + 0 + 0 + + + 7 + 51 + 1 + 0 + 0 + 0 + ..\..\src\components.c + components.c + 0 + 0 + diff --git a/bsp/gd32e230k-start/project.uvprojx b/bsp/fm33lc026/project.uvprojx similarity index 63% rename from bsp/gd32e230k-start/project.uvprojx rename to bsp/fm33lc026/project.uvprojx index 89b4f148c9..4a9373c1e1 100644 --- a/bsp/gd32e230k-start/project.uvprojx +++ b/bsp/fm33lc026/project.uvprojx @@ -7,23 +7,21 @@ - rt-thread_gd32e230 + RT_Thread 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC - 1 + 0 - GD32E230K8 - GigaDevice - GigaDevice.GD32E230_DFP.1.0.0 - http://gd32mcu.21ic.com/data/documents/yingyongruanjian - IRAM(0x20000000,0x0002000) IROM(0x08000000,0x0010000) CPUTYPE("Cortex-M23") CLOCK(12000000) ELITTLE + FM33LC04X + FMSH + Keil.FM33LC0XX_DFP.3.0.1 + IROM(0x00000000,0x40000) IRAM(0x20000000,0x6000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE - UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E230 -FS08000000 -FL010000 -FP0($$Device:GD32E230K8$Flash\GD32E230.FLM)) + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FM33LC04X_FLASH256 -FS00 -FL040000 -FP0($$Device:FM33LC04X$Flash\FM33LC04X_FLASH256.FLM)) 0 - $$Device:GD32E230K8$Device\Include\gd32e230.h + @@ -33,7 +31,7 @@ - $$Device:GD32E230K8$SVD\GD32E230.svd + $$Device:FM33LC04X$SVD\FM33LC0XX.SVD 0 0 @@ -48,14 +46,14 @@ 0 1 - .\build\ - rtthread-gd32e230 + .\build\keil\Obj\ + rt-thread 1 0 - 0 + 1 1 1 - .\build\ + .\build\keil\List\ 1 0 0 @@ -109,14 +107,14 @@ 1 - + SARMCM3.DLL - - - SARMV8M.DLL - -MPU - TCM.DLL - -pCM23 + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 @@ -137,8 +135,8 @@ 4096 1 - BIN\UL2V8M.DLL - + BIN\UL2CM3.DLL + "" () @@ -174,7 +172,7 @@ 1 0 0 - "Cortex-M23" + "Cortex-M0" 0 0 @@ -184,6 +182,7 @@ 0 0 0 + 0 0 0 8 @@ -244,12 +243,12 @@ 0 0x20000000 - 0x2000 + 0x6000 1 - 0x8000000 - 0x10000 + 0x0 + 0x40000 0 @@ -273,8 +272,8 @@ 1 - 0x8000000 - 0x10000 + 0x0 + 0x40000 1 @@ -299,7 +298,7 @@ 0 0x20000000 - 0x2000 + 0x6000 0 @@ -311,7 +310,7 @@ 1 - 7 + 1 0 0 1 @@ -320,14 +319,14 @@ 0 0 0 - 0 + 2 0 0 1 0 0 - 1 - 1 + 0 + 0 1 1 0 @@ -335,9 +334,9 @@ 0 - GD32E230 + USE_HAL_DRIVER, FM33LC0XX, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND - .;..\..\include;applications;drivers;Libraries\CMSIS\GD\GD32E230\Include;Libraries\CMSIS;Libraries\GD32E230_standard_peripheral\Include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m23;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\spi\sfud\inc;..\..\components\drivers\include;..\..\components\libc\compilers\common + applications;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;..\..\components\drivers\include;board;libraries\HAL_Drivers;libraries\HAL_Drivers\config;..\..\components\finsh;libraries\FM33LC0xx_FL_Driver\CMSIS\Include;libraries\FM33LC0xx_FL_Driver\Inc;.;..\..\include;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;..\..\examples\utest\testcases\kernel @@ -365,10 +364,10 @@ 0 1 0 - 0x08000000 + 0x0 0x20000000 - + .\board\linker_scripts\link.sct @@ -378,86 +377,6 @@ - - Kernel - - - clock.c - 1 - ..\..\src\clock.c - - - components.c - 1 - ..\..\src\components.c - - - cpu.c - 1 - ..\..\src\cpu.c - - - device.c - 1 - ..\..\src\device.c - - - idle.c - 1 - ..\..\src\idle.c - - - ipc.c - 1 - ..\..\src\ipc.c - - - irq.c - 1 - ..\..\src\irq.c - - - kservice.c - 1 - ..\..\src\kservice.c - - - mem.c - 1 - ..\..\src\mem.c - - - mempool.c - 1 - ..\..\src\mempool.c - - - object.c - 1 - ..\..\src\object.c - - - scheduler.c - 1 - ..\..\src\scheduler.c - - - signal.c - 1 - ..\..\src\signal.c - - - thread.c - 1 - ..\..\src\thread.c - - - timer.c - 1 - ..\..\src\timer.c - - - Applications @@ -469,152 +388,12 @@ - Drivers + CPU - board.c + showmem.c 1 - drivers\board.c - - - drv_usart.c - 1 - drivers\drv_usart.c - - - drv_spi.c - 1 - drivers\drv_spi.c - - - drv_i2c.c - 1 - drivers\drv_i2c.c - - - drv_gpio.c - 1 - drivers\drv_gpio.c - - - - - GD32_Lib - - - gd32e230_adc.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_adc.c - - - gd32e230_cmp.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_cmp.c - - - gd32e230_crc.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_crc.c - - - gd32e230_dbg.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_dbg.c - - - gd32e230_dma.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_dma.c - - - gd32e230_exti.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_exti.c - - - gd32e230_fmc.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_fmc.c - - - gd32e230_fwdgt.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_fwdgt.c - - - gd32e230_gpio.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_gpio.c - - - gd32e230_i2c.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_i2c.c - - - gd32e230_misc.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_misc.c - - - gd32e230_pmu.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_pmu.c - - - gd32e230_rcu.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_rcu.c - - - gd32e230_rtc.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_rtc.c - - - gd32e230_spi.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_spi.c - - - gd32e230_syscfg.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_syscfg.c - - - gd32e230_timer.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_timer.c - - - gd32e230_usart.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_usart.c - - - gd32e230_wwdgt.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_wwdgt.c - - - system_gd32e230.c - 1 - Libraries\CMSIS\GD\GD32E230\Source\system_gd32e230.c - - - startup_gd32e230.s - 2 - Libraries\CMSIS\GD\GD32E230\Source\ARM\startup_gd32e230.s - - - - - cpu - - - backtrace.c - 1 - ..\..\libcpu\arm\common\backtrace.c + ..\..\libcpu\arm\common\showmem.c div0.c @@ -622,149 +401,30 @@ ..\..\libcpu\arm\common\div0.c - showmem.c + backtrace.c 1 - ..\..\libcpu\arm\common\showmem.c - - - cpuport.c - 1 - ..\..\libcpu\arm\cortex-m23\cpuport.c + ..\..\libcpu\arm\common\backtrace.c context_rvds.S 2 - ..\..\libcpu\arm\cortex-m23\context_rvds.S + ..\..\libcpu\arm\cortex-m0\context_rvds.S + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m0\cpuport.c DeviceDrivers - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 0 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - --c99 - - - - - - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - - - i2c_core.c - 1 - ..\..\components\drivers\i2c\i2c_core.c - - - i2c_dev.c - 1 - ..\..\components\drivers\i2c\i2c_dev.c - - - pin.c - 1 - ..\..\components\drivers\misc\pin.c - serial.c 1 ..\..\components\drivers\serial\serial.c - - spi_core.c - 1 - ..\..\components\drivers\spi\spi_core.c - - - spi_dev.c - 1 - ..\..\components\drivers\spi\spi_dev.c - - - spi_flash_sfud.c - 1 - ..\..\components\drivers\spi\spi_flash_sfud.c - - - sfud.c - 1 - ..\..\components\drivers\spi\sfud\src\sfud.c - - - completion.c - 1 - ..\..\components\drivers\src\completion.c - - - dataqueue.c - 1 - ..\..\components\drivers\src\dataqueue.c - - - pipe.c - 1 - ..\..\components\drivers\src\pipe.c - ringblk_buf.c 1 @@ -785,10 +445,227 @@ 1 ..\..\components\drivers\src\workqueue.c + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + - ::CMSIS + Drivers + + + startup_fm33lc0xx.s + 2 + libraries\FM\FM33xx\Source\Templates\ARM\startup_fm33lc0xx.s + + + board.c + 1 + board\board.c + + + drv_usart.c + 1 + libraries\HAL_Drivers\drv_usart.c + + + drv_common.c + 1 + libraries\HAL_Drivers\drv_common.c + + + + + finsh + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + + + FM33LC0xx_FL_Driver + + + fm33lc0xx_fl_rcc.c + 1 + libraries\FM33LC0xx_FL_Driver\Src\fm33lc0xx_fl_rcc.c + + + fm33lc0xx_fl_crc.c + 1 + libraries\FM33LC0xx_FL_Driver\Src\fm33lc0xx_fl_crc.c + + + fm33lc0xx_fl_uart.c + 1 + libraries\FM33LC0xx_FL_Driver\Src\fm33lc0xx_fl_uart.c + + + fm33lc0xx_fl_lpuart.c + 1 + libraries\FM33LC0xx_FL_Driver\Src\fm33lc0xx_fl_lpuart.c + + + fm33lc0xx_fl_gpio.c + 1 + libraries\FM33LC0xx_FL_Driver\Src\fm33lc0xx_fl_gpio.c + + + fm33lc0xx_fl_dma.c + 1 + libraries\FM33LC0xx_FL_Driver\Src\fm33lc0xx_fl_dma.c + + + system_fm33lc0xx.c + 1 + libraries\FM33LC0xx_FL_Driver\CMSIS\system_fm33lc0xx.c + + + + + Kernel + + + thread.c + 1 + ..\..\src\thread.c + + + mem.c + 1 + ..\..\src\mem.c + + + irq.c + 1 + ..\..\src\irq.c + + + timer.c + 1 + ..\..\src\timer.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + device.c + 1 + ..\..\src\device.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + clock.c + 1 + ..\..\src\clock.c + + + idle.c + 1 + ..\..\src\idle.c + + + object.c + 1 + ..\..\src\object.c + + + components.c + 1 + ..\..\src\components.c + + @@ -796,14 +673,7 @@ - - - - - - - - + diff --git a/bsp/fm33lc026/rtconfig.h b/bsp/fm33lc026/rtconfig.h new file mode 100644 index 0000000000..479210dc99 --- /dev/null +++ b/bsp/fm33lc026/rtconfig.h @@ -0,0 +1,177 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 500 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart4" +#define RT_VER_NUM 0x40004 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* games: games run on RT-Thread console */ + +#define SOC_FAMILY_FM33 +#define SOC_SERIES_FM33LC0XX + +/* Hardware Drivers Config */ + +#define SOC_FM33LC0XX + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_USING_UART1 +#define BSP_USING_UART4 + +#endif diff --git a/bsp/fm33lc026/rtconfig.py b/bsp/fm33lc026/rtconfig.py new file mode 100644 index 0000000000..00c8bc7413 --- /dev/null +++ b/bsp/fm33lc026/rtconfig.py @@ -0,0 +1,151 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M0 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/fm33lc026/template.uvprojx b/bsp/fm33lc026/template.uvprojx new file mode 100644 index 0000000000..a3219e47f6 --- /dev/null +++ b/bsp/fm33lc026/template.uvprojx @@ -0,0 +1,388 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + RT_Thread + 0x4 + ARM-ADS + 0 + + + FM33LC04X + FMSH + Keil.FM33LC0XX_DFP.3.0.1 + IROM(0x00000000,0x40000) IRAM(0x20000000,0x6000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FM33LC04X_FLASH256 -FS00 -FL040000 -FP0($$Device:FM33LC04X$Flash\FM33LC04X_FLASH256.FLM)) + 0 + + + + + + + + + + + $$Device:FM33LC04X$SVD\FM33LC0XX.SVD + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x6000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x6000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x0 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + +